1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
43 STATISTIC(NodesCombined , "Number of dag nodes combined");
44 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
45 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
46 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
50 CombinerAA("combiner-alias-analysis", cl::Hidden,
51 cl::desc("Turn on alias analysis during testing"));
54 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
55 cl::desc("Include global information in alias analysis"));
57 //------------------------------ DAGCombiner ---------------------------------//
59 class VISIBILITY_HIDDEN DAGCombiner {
61 const TargetLowering &TLI;
63 CodeGenOpt::Level OptLevel;
67 // Worklist of all of the nodes that need to be simplified.
68 std::vector<SDNode*> WorkList;
70 // AA - Used for DAG load/store alias analysis.
73 /// AddUsersToWorkList - When an instruction is simplified, add all users of
74 /// the instruction to the work lists because they might get more simplified
77 void AddUsersToWorkList(SDNode *N) {
78 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
83 /// visit - call the node-specific routine that knows how to fold each
84 /// particular type of node.
85 SDValue visit(SDNode *N);
88 /// AddToWorkList - Add to the work list making sure it's instance is at the
89 /// the back (next to be processed.)
90 void AddToWorkList(SDNode *N) {
91 removeFromWorkList(N);
92 WorkList.push_back(N);
95 /// removeFromWorkList - remove all instances of N from the worklist.
97 void removeFromWorkList(SDNode *N) {
98 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
102 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
105 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
106 return CombineTo(N, &Res, 1, AddTo);
109 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
111 SDValue To[] = { Res0, Res1 };
112 return CombineTo(N, To, 2, AddTo);
115 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
119 /// SimplifyDemandedBits - Check the specified integer node value to see if
120 /// it can be simplified or if things it uses can be simplified by bit
121 /// propagation. If so, return true.
122 bool SimplifyDemandedBits(SDValue Op) {
123 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits());
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
133 /// combine - call the node-specific routine that knows how to fold each
134 /// particular type of node. If that doesn't do anything, try the
135 /// target-specific DAG combines.
136 SDValue combine(SDNode *N);
138 // Visitation implementation - Implement dag node combining for different
139 // node types. The semantics are as follows:
141 // SDValue.getNode() == 0 - No change was made
142 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
143 // otherwise - N should be replaced by the returned Operand.
145 SDValue visitTokenFactor(SDNode *N);
146 SDValue visitMERGE_VALUES(SDNode *N);
147 SDValue visitADD(SDNode *N);
148 SDValue visitSUB(SDNode *N);
149 SDValue visitADDC(SDNode *N);
150 SDValue visitADDE(SDNode *N);
151 SDValue visitMUL(SDNode *N);
152 SDValue visitSDIV(SDNode *N);
153 SDValue visitUDIV(SDNode *N);
154 SDValue visitSREM(SDNode *N);
155 SDValue visitUREM(SDNode *N);
156 SDValue visitMULHU(SDNode *N);
157 SDValue visitMULHS(SDNode *N);
158 SDValue visitSMUL_LOHI(SDNode *N);
159 SDValue visitUMUL_LOHI(SDNode *N);
160 SDValue visitSDIVREM(SDNode *N);
161 SDValue visitUDIVREM(SDNode *N);
162 SDValue visitAND(SDNode *N);
163 SDValue visitOR(SDNode *N);
164 SDValue visitXOR(SDNode *N);
165 SDValue SimplifyVBinOp(SDNode *N);
166 SDValue visitSHL(SDNode *N);
167 SDValue visitSRA(SDNode *N);
168 SDValue visitSRL(SDNode *N);
169 SDValue visitCTLZ(SDNode *N);
170 SDValue visitCTTZ(SDNode *N);
171 SDValue visitCTPOP(SDNode *N);
172 SDValue visitSELECT(SDNode *N);
173 SDValue visitSELECT_CC(SDNode *N);
174 SDValue visitSETCC(SDNode *N);
175 SDValue visitSIGN_EXTEND(SDNode *N);
176 SDValue visitZERO_EXTEND(SDNode *N);
177 SDValue visitANY_EXTEND(SDNode *N);
178 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
179 SDValue visitTRUNCATE(SDNode *N);
180 SDValue visitBIT_CONVERT(SDNode *N);
181 SDValue visitBUILD_PAIR(SDNode *N);
182 SDValue visitFADD(SDNode *N);
183 SDValue visitFSUB(SDNode *N);
184 SDValue visitFMUL(SDNode *N);
185 SDValue visitFDIV(SDNode *N);
186 SDValue visitFREM(SDNode *N);
187 SDValue visitFCOPYSIGN(SDNode *N);
188 SDValue visitSINT_TO_FP(SDNode *N);
189 SDValue visitUINT_TO_FP(SDNode *N);
190 SDValue visitFP_TO_SINT(SDNode *N);
191 SDValue visitFP_TO_UINT(SDNode *N);
192 SDValue visitFP_ROUND(SDNode *N);
193 SDValue visitFP_ROUND_INREG(SDNode *N);
194 SDValue visitFP_EXTEND(SDNode *N);
195 SDValue visitFNEG(SDNode *N);
196 SDValue visitFABS(SDNode *N);
197 SDValue visitBRCOND(SDNode *N);
198 SDValue visitBR_CC(SDNode *N);
199 SDValue visitLOAD(SDNode *N);
200 SDValue visitSTORE(SDNode *N);
201 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
203 SDValue visitBUILD_VECTOR(SDNode *N);
204 SDValue visitCONCAT_VECTORS(SDNode *N);
205 SDValue visitVECTOR_SHUFFLE(SDNode *N);
207 SDValue XformToShuffleWithZero(SDNode *N);
208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
216 SDValue N3, ISD::CondCode CC,
217 bool NotExtCompare = false);
218 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
219 DebugLoc DL, bool foldBooleans = true);
220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
222 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
224 SDValue BuildSDIV(SDNode *N);
225 SDValue BuildUDIV(SDNode *N);
226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
227 SDValue ReduceLoadWidth(SDNode *N);
228 SDValue ReduceLoadOpStoreWidth(SDNode *N);
230 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
233 /// looking for aliasing nodes and adding them to the Aliases vector.
234 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
235 SmallVector<SDValue, 8> &Aliases);
237 /// isAlias - Return true if there is any possibility that the two addresses
239 bool isAlias(SDValue Ptr1, int64_t Size1,
240 const Value *SrcValue1, int SrcValueOffset1,
241 SDValue Ptr2, int64_t Size2,
242 const Value *SrcValue2, int SrcValueOffset2) const;
244 /// FindAliasInfo - Extracts the relevant alias information from the memory
245 /// node. Returns true if the operand was a load.
246 bool FindAliasInfo(SDNode *N,
247 SDValue &Ptr, int64_t &Size,
248 const Value *&SrcValue, int &SrcValueOffset) const;
250 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
251 /// looking for a better chain (aliasing node.)
252 SDValue FindBetterChain(SDNode *N, SDValue Chain);
254 /// getShiftAmountTy - Returns a type large enough to hold any valid
255 /// shift amount - before type legalization these can be huge.
256 MVT getShiftAmountTy() {
257 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
261 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
263 TLI(D.getTargetLoweringInfo()),
266 LegalOperations(false),
270 /// Run - runs the dag combiner on all nodes in the work list
271 void Run(CombineLevel AtLevel);
277 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
278 /// nodes from the worklist.
279 class VISIBILITY_HIDDEN WorkListRemover :
280 public SelectionDAG::DAGUpdateListener {
283 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
285 virtual void NodeDeleted(SDNode *N, SDNode *E) {
286 DC.removeFromWorkList(N);
289 virtual void NodeUpdated(SDNode *N) {
295 //===----------------------------------------------------------------------===//
296 // TargetLowering::DAGCombinerInfo implementation
297 //===----------------------------------------------------------------------===//
299 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
300 ((DAGCombiner*)DC)->AddToWorkList(N);
303 SDValue TargetLowering::DAGCombinerInfo::
304 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
305 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
308 SDValue TargetLowering::DAGCombinerInfo::
309 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
310 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
314 SDValue TargetLowering::DAGCombinerInfo::
315 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
316 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
319 void TargetLowering::DAGCombinerInfo::
320 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
321 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
324 //===----------------------------------------------------------------------===//
326 //===----------------------------------------------------------------------===//
328 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
329 /// specified expression for the same cost as the expression itself, or 2 if we
330 /// can compute the negated form more cheaply than the expression itself.
331 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
332 unsigned Depth = 0) {
333 // No compile time optimizations on this type.
334 if (Op.getValueType() == MVT::ppcf128)
337 // fneg is removable even if it has multiple uses.
338 if (Op.getOpcode() == ISD::FNEG) return 2;
340 // Don't allow anything with multiple uses.
341 if (!Op.hasOneUse()) return 0;
343 // Don't recurse exponentially.
344 if (Depth > 6) return 0;
346 switch (Op.getOpcode()) {
347 default: return false;
348 case ISD::ConstantFP:
349 // Don't invert constant FP values after legalize. The negated constant
350 // isn't necessarily legal.
351 return LegalOperations ? 0 : 1;
353 // FIXME: determine better conditions for this xform.
354 if (!UnsafeFPMath) return 0;
356 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
357 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
359 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
360 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
362 // We can't turn -(A-B) into B-A when we honor signed zeros.
363 if (!UnsafeFPMath) return 0;
365 // fold (fneg (fsub A, B)) -> (fsub B, A)
370 if (HonorSignDependentRoundingFPMath()) return 0;
372 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
373 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
376 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
381 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
385 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
386 /// returns the newly negated expression.
387 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
388 bool LegalOperations, unsigned Depth = 0) {
389 // fneg is removable even if it has multiple uses.
390 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
392 // Don't allow anything with multiple uses.
393 assert(Op.hasOneUse() && "Unknown reuse!");
395 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
396 switch (Op.getOpcode()) {
397 default: llvm_unreachable("Unknown code");
398 case ISD::ConstantFP: {
399 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
401 return DAG.getConstantFP(V, Op.getValueType());
404 // FIXME: determine better conditions for this xform.
405 assert(UnsafeFPMath);
407 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
408 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
409 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
410 GetNegatedExpression(Op.getOperand(0), DAG,
411 LegalOperations, Depth+1),
413 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
414 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
415 GetNegatedExpression(Op.getOperand(1), DAG,
416 LegalOperations, Depth+1),
419 // We can't turn -(A-B) into B-A when we honor signed zeros.
420 assert(UnsafeFPMath);
422 // fold (fneg (fsub 0, B)) -> B
423 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
424 if (N0CFP->getValueAPF().isZero())
425 return Op.getOperand(1);
427 // fold (fneg (fsub A, B)) -> (fsub B, A)
428 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
429 Op.getOperand(1), Op.getOperand(0));
433 assert(!HonorSignDependentRoundingFPMath());
435 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
436 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
437 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
438 GetNegatedExpression(Op.getOperand(0), DAG,
439 LegalOperations, Depth+1),
442 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
443 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
445 GetNegatedExpression(Op.getOperand(1), DAG,
446 LegalOperations, Depth+1));
450 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
451 GetNegatedExpression(Op.getOperand(0), DAG,
452 LegalOperations, Depth+1));
454 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
455 GetNegatedExpression(Op.getOperand(0), DAG,
456 LegalOperations, Depth+1),
462 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
463 // that selects between the values 1 and 0, making it equivalent to a setcc.
464 // Also, set the incoming LHS, RHS, and CC references to the appropriate
465 // nodes based on the type of node we are checking. This simplifies life a
466 // bit for the callers.
467 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
469 if (N.getOpcode() == ISD::SETCC) {
470 LHS = N.getOperand(0);
471 RHS = N.getOperand(1);
472 CC = N.getOperand(2);
475 if (N.getOpcode() == ISD::SELECT_CC &&
476 N.getOperand(2).getOpcode() == ISD::Constant &&
477 N.getOperand(3).getOpcode() == ISD::Constant &&
478 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
479 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
480 LHS = N.getOperand(0);
481 RHS = N.getOperand(1);
482 CC = N.getOperand(4);
488 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
489 // one use. If this is true, it allows the users to invert the operation for
490 // free when it is profitable to do so.
491 static bool isOneUseSetCC(SDValue N) {
493 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
498 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
499 SDValue N0, SDValue N1) {
500 MVT VT = N0.getValueType();
501 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
502 if (isa<ConstantSDNode>(N1)) {
503 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
505 DAG.FoldConstantArithmetic(Opc, VT,
506 cast<ConstantSDNode>(N0.getOperand(1)),
507 cast<ConstantSDNode>(N1));
508 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
509 } else if (N0.hasOneUse()) {
510 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
511 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
512 N0.getOperand(0), N1);
513 AddToWorkList(OpNode.getNode());
514 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
518 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
519 if (isa<ConstantSDNode>(N0)) {
520 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
522 DAG.FoldConstantArithmetic(Opc, VT,
523 cast<ConstantSDNode>(N1.getOperand(1)),
524 cast<ConstantSDNode>(N0));
525 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
526 } else if (N1.hasOneUse()) {
527 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
528 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
529 N1.getOperand(0), N0);
530 AddToWorkList(OpNode.getNode());
531 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
538 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
540 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
542 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
543 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG));
544 DOUT << " and " << NumTo-1 << " other values\n";
545 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i)
546 assert(N->getValueType(i) == To[i].getValueType() &&
547 "Cannot combine value to value of different type!"));
548 WorkListRemover DeadNodes(*this);
549 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
552 // Push the new nodes and any users onto the worklist
553 for (unsigned i = 0, e = NumTo; i != e; ++i) {
554 if (To[i].getNode()) {
555 AddToWorkList(To[i].getNode());
556 AddUsersToWorkList(To[i].getNode());
561 // Finally, if the node is now dead, remove it from the graph. The node
562 // may not be dead if the replacement process recursively simplified to
563 // something else needing this node.
564 if (N->use_empty()) {
565 // Nodes can be reintroduced into the worklist. Make sure we do not
566 // process a node that has been replaced.
567 removeFromWorkList(N);
569 // Finally, since the node is now dead, remove it from the graph.
572 return SDValue(N, 0);
576 DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &
578 // Replace all uses. If any nodes become isomorphic to other nodes and
579 // are deleted, make sure to remove them from our worklist.
580 WorkListRemover DeadNodes(*this);
581 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
583 // Push the new node and any (possibly new) users onto the worklist.
584 AddToWorkList(TLO.New.getNode());
585 AddUsersToWorkList(TLO.New.getNode());
587 // Finally, if the node is now dead, remove it from the graph. The node
588 // may not be dead if the replacement process recursively simplified to
589 // something else needing this node.
590 if (TLO.Old.getNode()->use_empty()) {
591 removeFromWorkList(TLO.Old.getNode());
593 // If the operands of this node are only used by the node, they will now
594 // be dead. Make sure to visit them first to delete dead nodes early.
595 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
596 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
597 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
599 DAG.DeleteNode(TLO.Old.getNode());
603 /// SimplifyDemandedBits - Check the specified integer node value to see if
604 /// it can be simplified or if things it uses can be simplified by bit
605 /// propagation. If so, return true.
606 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
607 TargetLowering::TargetLoweringOpt TLO(DAG);
608 APInt KnownZero, KnownOne;
609 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
613 AddToWorkList(Op.getNode());
615 // Replace the old value with the new one.
617 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
618 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
621 CommitTargetLoweringOpt(TLO);
625 //===----------------------------------------------------------------------===//
626 // Main DAG Combiner implementation
627 //===----------------------------------------------------------------------===//
629 void DAGCombiner::Run(CombineLevel AtLevel) {
630 // set the instance variables, so that the various visit routines may use it.
632 LegalOperations = Level >= NoIllegalOperations;
633 LegalTypes = Level >= NoIllegalTypes;
635 // Add all the dag nodes to the worklist.
636 WorkList.reserve(DAG.allnodes_size());
637 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
638 E = DAG.allnodes_end(); I != E; ++I)
639 WorkList.push_back(I);
641 // Create a dummy node (which is not added to allnodes), that adds a reference
642 // to the root node, preventing it from being deleted, and tracking any
643 // changes of the root.
644 HandleSDNode Dummy(DAG.getRoot());
646 // The root of the dag may dangle to deleted nodes until the dag combiner is
647 // done. Set it to null to avoid confusion.
648 DAG.setRoot(SDValue());
650 // while the worklist isn't empty, inspect the node on the end of it and
651 // try and combine it.
652 while (!WorkList.empty()) {
653 SDNode *N = WorkList.back();
656 // If N has no uses, it is dead. Make sure to revisit all N's operands once
657 // N is deleted from the DAG, since they too may now be dead or may have a
658 // reduced number of uses, allowing other xforms.
659 if (N->use_empty() && N != &Dummy) {
660 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
661 AddToWorkList(N->getOperand(i).getNode());
667 SDValue RV = combine(N);
669 if (RV.getNode() == 0)
674 // If we get back the same node we passed in, rather than a new node or
675 // zero, we know that the node must have defined multiple values and
676 // CombineTo was used. Since CombineTo takes care of the worklist
677 // mechanics for us, we have no work to do in this case.
678 if (RV.getNode() == N)
681 assert(N->getOpcode() != ISD::DELETED_NODE &&
682 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
683 "Node was deleted but visit returned new node!");
685 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
686 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG));
688 WorkListRemover DeadNodes(*this);
689 if (N->getNumValues() == RV.getNode()->getNumValues())
690 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
692 assert(N->getValueType(0) == RV.getValueType() &&
693 N->getNumValues() == 1 && "Type mismatch");
695 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
698 // Push the new node and any users onto the worklist
699 AddToWorkList(RV.getNode());
700 AddUsersToWorkList(RV.getNode());
702 // Add any uses of the old node to the worklist in case this node is the
703 // last one that uses them. They may become dead after this node is
705 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
706 AddToWorkList(N->getOperand(i).getNode());
708 // Finally, if the node is now dead, remove it from the graph. The node
709 // may not be dead if the replacement process recursively simplified to
710 // something else needing this node.
711 if (N->use_empty()) {
712 // Nodes can be reintroduced into the worklist. Make sure we do not
713 // process a node that has been replaced.
714 removeFromWorkList(N);
716 // Finally, since the node is now dead, remove it from the graph.
721 // If the root changed (e.g. it was a dead load, update the root).
722 DAG.setRoot(Dummy.getValue());
725 SDValue DAGCombiner::visit(SDNode *N) {
726 switch(N->getOpcode()) {
728 case ISD::TokenFactor: return visitTokenFactor(N);
729 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
730 case ISD::ADD: return visitADD(N);
731 case ISD::SUB: return visitSUB(N);
732 case ISD::ADDC: return visitADDC(N);
733 case ISD::ADDE: return visitADDE(N);
734 case ISD::MUL: return visitMUL(N);
735 case ISD::SDIV: return visitSDIV(N);
736 case ISD::UDIV: return visitUDIV(N);
737 case ISD::SREM: return visitSREM(N);
738 case ISD::UREM: return visitUREM(N);
739 case ISD::MULHU: return visitMULHU(N);
740 case ISD::MULHS: return visitMULHS(N);
741 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
742 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
743 case ISD::SDIVREM: return visitSDIVREM(N);
744 case ISD::UDIVREM: return visitUDIVREM(N);
745 case ISD::AND: return visitAND(N);
746 case ISD::OR: return visitOR(N);
747 case ISD::XOR: return visitXOR(N);
748 case ISD::SHL: return visitSHL(N);
749 case ISD::SRA: return visitSRA(N);
750 case ISD::SRL: return visitSRL(N);
751 case ISD::CTLZ: return visitCTLZ(N);
752 case ISD::CTTZ: return visitCTTZ(N);
753 case ISD::CTPOP: return visitCTPOP(N);
754 case ISD::SELECT: return visitSELECT(N);
755 case ISD::SELECT_CC: return visitSELECT_CC(N);
756 case ISD::SETCC: return visitSETCC(N);
757 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
758 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
759 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
760 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
761 case ISD::TRUNCATE: return visitTRUNCATE(N);
762 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
763 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
764 case ISD::FADD: return visitFADD(N);
765 case ISD::FSUB: return visitFSUB(N);
766 case ISD::FMUL: return visitFMUL(N);
767 case ISD::FDIV: return visitFDIV(N);
768 case ISD::FREM: return visitFREM(N);
769 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
770 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
771 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
772 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
773 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
774 case ISD::FP_ROUND: return visitFP_ROUND(N);
775 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
776 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
777 case ISD::FNEG: return visitFNEG(N);
778 case ISD::FABS: return visitFABS(N);
779 case ISD::BRCOND: return visitBRCOND(N);
780 case ISD::BR_CC: return visitBR_CC(N);
781 case ISD::LOAD: return visitLOAD(N);
782 case ISD::STORE: return visitSTORE(N);
783 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
784 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
785 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
786 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
787 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
792 SDValue DAGCombiner::combine(SDNode *N) {
793 SDValue RV = visit(N);
795 // If nothing happened, try a target-specific DAG combine.
796 if (RV.getNode() == 0) {
797 assert(N->getOpcode() != ISD::DELETED_NODE &&
798 "Node was deleted but visit returned NULL!");
800 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
801 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
803 // Expose the DAG combiner to the target combiner impls.
804 TargetLowering::DAGCombinerInfo
805 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
807 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
811 // If N is a commutative binary node, try commuting it to enable more
813 if (RV.getNode() == 0 &&
814 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
815 N->getNumValues() == 1) {
816 SDValue N0 = N->getOperand(0);
817 SDValue N1 = N->getOperand(1);
819 // Constant operands are canonicalized to RHS.
820 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
821 SDValue Ops[] = { N1, N0 };
822 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
825 return SDValue(CSENode, 0);
832 /// getInputChainForNode - Given a node, return its input chain if it has one,
833 /// otherwise return a null sd operand.
834 static SDValue getInputChainForNode(SDNode *N) {
835 if (unsigned NumOps = N->getNumOperands()) {
836 if (N->getOperand(0).getValueType() == MVT::Other)
837 return N->getOperand(0);
838 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
839 return N->getOperand(NumOps-1);
840 for (unsigned i = 1; i < NumOps-1; ++i)
841 if (N->getOperand(i).getValueType() == MVT::Other)
842 return N->getOperand(i);
847 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
848 // If N has two operands, where one has an input chain equal to the other,
849 // the 'other' chain is redundant.
850 if (N->getNumOperands() == 2) {
851 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
852 return N->getOperand(0);
853 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
854 return N->getOperand(1);
857 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
858 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
859 SmallPtrSet<SDNode*, 16> SeenOps;
860 bool Changed = false; // If we should replace this token factor.
862 // Start out with this token factor.
865 // Iterate through token factors. The TFs grows when new token factors are
867 for (unsigned i = 0; i < TFs.size(); ++i) {
870 // Check each of the operands.
871 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
872 SDValue Op = TF->getOperand(i);
874 switch (Op.getOpcode()) {
875 case ISD::EntryToken:
876 // Entry tokens don't need to be added to the list. They are
881 case ISD::TokenFactor:
882 if ((CombinerAA || Op.hasOneUse()) &&
883 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
884 // Queue up for processing.
885 TFs.push_back(Op.getNode());
886 // Clean up in case the token factor is removed.
887 AddToWorkList(Op.getNode());
894 // Only add if it isn't already in the list.
895 if (SeenOps.insert(Op.getNode()))
906 // If we've change things around then replace token factor.
909 // The entry token is the only possible outcome.
910 Result = DAG.getEntryNode();
912 // New and improved token factor.
913 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
914 MVT::Other, &Ops[0], Ops.size());
917 // Don't add users to work list.
918 return CombineTo(N, Result, false);
924 /// MERGE_VALUES can always be eliminated.
925 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
926 WorkListRemover DeadNodes(*this);
927 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
928 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
930 removeFromWorkList(N);
932 return SDValue(N, 0); // Return N so it doesn't get rechecked!
936 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
938 MVT VT = N0.getValueType();
939 SDValue N00 = N0.getOperand(0);
940 SDValue N01 = N0.getOperand(1);
941 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
943 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
944 isa<ConstantSDNode>(N00.getOperand(1))) {
945 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
946 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
947 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
948 N00.getOperand(0), N01),
949 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
950 N00.getOperand(1), N01));
951 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
957 SDValue DAGCombiner::visitADD(SDNode *N) {
958 SDValue N0 = N->getOperand(0);
959 SDValue N1 = N->getOperand(1);
960 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
961 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
962 MVT VT = N0.getValueType();
966 SDValue FoldedVOp = SimplifyVBinOp(N);
967 if (FoldedVOp.getNode()) return FoldedVOp;
970 // fold (add x, undef) -> undef
971 if (N0.getOpcode() == ISD::UNDEF)
973 if (N1.getOpcode() == ISD::UNDEF)
975 // fold (add c1, c2) -> c1+c2
977 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
978 // canonicalize constant to RHS
980 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
981 // fold (add x, 0) -> x
982 if (N1C && N1C->isNullValue())
984 // fold (add Sym, c) -> Sym+c
985 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
986 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
987 GA->getOpcode() == ISD::GlobalAddress)
988 return DAG.getGlobalAddress(GA->getGlobal(), VT,
990 (uint64_t)N1C->getSExtValue());
991 // fold ((c1-A)+c2) -> (c1+c2)-A
992 if (N1C && N0.getOpcode() == ISD::SUB)
993 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
994 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
995 DAG.getConstant(N1C->getAPIntValue()+
996 N0C->getAPIntValue(), VT),
999 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1000 if (RADD.getNode() != 0)
1002 // fold ((0-A) + B) -> B-A
1003 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1004 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1005 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1006 // fold (A + (0-B)) -> A-B
1007 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1008 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1009 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1010 // fold (A+(B-A)) -> B
1011 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1012 return N1.getOperand(0);
1013 // fold ((B-A)+A) -> B
1014 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1015 return N0.getOperand(0);
1016 // fold (A+(B-(A+C))) to (B-C)
1017 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1018 N0 == N1.getOperand(1).getOperand(0))
1019 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1020 N1.getOperand(1).getOperand(1));
1021 // fold (A+(B-(C+A))) to (B-C)
1022 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1023 N0 == N1.getOperand(1).getOperand(1))
1024 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1025 N1.getOperand(1).getOperand(0));
1026 // fold (A+((B-A)+or-C)) to (B+or-C)
1027 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1028 N1.getOperand(0).getOpcode() == ISD::SUB &&
1029 N0 == N1.getOperand(0).getOperand(1))
1030 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1031 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1033 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1034 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1035 SDValue N00 = N0.getOperand(0);
1036 SDValue N01 = N0.getOperand(1);
1037 SDValue N10 = N1.getOperand(0);
1038 SDValue N11 = N1.getOperand(1);
1040 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1041 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1042 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1043 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1046 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1047 return SDValue(N, 0);
1049 // fold (a+b) -> (a|b) iff a and b share no bits.
1050 if (VT.isInteger() && !VT.isVector()) {
1051 APInt LHSZero, LHSOne;
1052 APInt RHSZero, RHSOne;
1053 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1054 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1056 if (LHSZero.getBoolValue()) {
1057 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1059 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1060 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1061 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1062 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1063 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1067 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1068 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1069 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1070 if (Result.getNode()) return Result;
1072 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1073 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1074 if (Result.getNode()) return Result;
1080 SDValue DAGCombiner::visitADDC(SDNode *N) {
1081 SDValue N0 = N->getOperand(0);
1082 SDValue N1 = N->getOperand(1);
1083 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1084 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1085 MVT VT = N0.getValueType();
1087 // If the flag result is dead, turn this into an ADD.
1088 if (N->hasNUsesOfValue(0, 1))
1089 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1090 DAG.getNode(ISD::CARRY_FALSE,
1091 N->getDebugLoc(), MVT::Flag));
1093 // canonicalize constant to RHS.
1095 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1097 // fold (addc x, 0) -> x + no carry out
1098 if (N1C && N1C->isNullValue())
1099 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1100 N->getDebugLoc(), MVT::Flag));
1102 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1103 APInt LHSZero, LHSOne;
1104 APInt RHSZero, RHSOne;
1105 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1106 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1108 if (LHSZero.getBoolValue()) {
1109 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1111 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1112 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1113 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1114 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1115 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1116 DAG.getNode(ISD::CARRY_FALSE,
1117 N->getDebugLoc(), MVT::Flag));
1123 SDValue DAGCombiner::visitADDE(SDNode *N) {
1124 SDValue N0 = N->getOperand(0);
1125 SDValue N1 = N->getOperand(1);
1126 SDValue CarryIn = N->getOperand(2);
1127 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1128 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1130 // canonicalize constant to RHS
1132 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1135 // fold (adde x, y, false) -> (addc x, y)
1136 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1137 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1142 SDValue DAGCombiner::visitSUB(SDNode *N) {
1143 SDValue N0 = N->getOperand(0);
1144 SDValue N1 = N->getOperand(1);
1145 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1146 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1147 MVT VT = N0.getValueType();
1150 if (VT.isVector()) {
1151 SDValue FoldedVOp = SimplifyVBinOp(N);
1152 if (FoldedVOp.getNode()) return FoldedVOp;
1155 // fold (sub x, x) -> 0
1157 return DAG.getConstant(0, N->getValueType(0));
1158 // fold (sub c1, c2) -> c1-c2
1160 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1161 // fold (sub x, c) -> (add x, -c)
1163 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1164 DAG.getConstant(-N1C->getAPIntValue(), VT));
1165 // fold (A+B)-A -> B
1166 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1167 return N0.getOperand(1);
1168 // fold (A+B)-B -> A
1169 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1170 return N0.getOperand(0);
1171 // fold ((A+(B+or-C))-B) -> A+or-C
1172 if (N0.getOpcode() == ISD::ADD &&
1173 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1174 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1175 N0.getOperand(1).getOperand(0) == N1)
1176 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1177 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1178 // fold ((A+(C+B))-B) -> A+C
1179 if (N0.getOpcode() == ISD::ADD &&
1180 N0.getOperand(1).getOpcode() == ISD::ADD &&
1181 N0.getOperand(1).getOperand(1) == N1)
1182 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1183 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1184 // fold ((A-(B-C))-C) -> A-B
1185 if (N0.getOpcode() == ISD::SUB &&
1186 N0.getOperand(1).getOpcode() == ISD::SUB &&
1187 N0.getOperand(1).getOperand(1) == N1)
1188 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1189 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1191 // If either operand of a sub is undef, the result is undef
1192 if (N0.getOpcode() == ISD::UNDEF)
1194 if (N1.getOpcode() == ISD::UNDEF)
1197 // If the relocation model supports it, consider symbol offsets.
1198 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1199 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1200 // fold (sub Sym, c) -> Sym-c
1201 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1202 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1204 (uint64_t)N1C->getSExtValue());
1205 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1206 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1207 if (GA->getGlobal() == GB->getGlobal())
1208 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1215 SDValue DAGCombiner::visitMUL(SDNode *N) {
1216 SDValue N0 = N->getOperand(0);
1217 SDValue N1 = N->getOperand(1);
1218 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1219 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1220 MVT VT = N0.getValueType();
1223 if (VT.isVector()) {
1224 SDValue FoldedVOp = SimplifyVBinOp(N);
1225 if (FoldedVOp.getNode()) return FoldedVOp;
1228 // fold (mul x, undef) -> 0
1229 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1230 return DAG.getConstant(0, VT);
1231 // fold (mul c1, c2) -> c1*c2
1233 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1234 // canonicalize constant to RHS
1236 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1237 // fold (mul x, 0) -> 0
1238 if (N1C && N1C->isNullValue())
1240 // fold (mul x, -1) -> 0-x
1241 if (N1C && N1C->isAllOnesValue())
1242 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1243 DAG.getConstant(0, VT), N0);
1244 // fold (mul x, (1 << c)) -> x << c
1245 if (N1C && N1C->getAPIntValue().isPowerOf2())
1246 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1247 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1248 getShiftAmountTy()));
1249 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1250 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1251 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1252 // FIXME: If the input is something that is easily negated (e.g. a
1253 // single-use add), we should put the negate there.
1254 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1255 DAG.getConstant(0, VT),
1256 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1257 DAG.getConstant(Log2Val, getShiftAmountTy())));
1259 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1260 if (N1C && N0.getOpcode() == ISD::SHL &&
1261 isa<ConstantSDNode>(N0.getOperand(1))) {
1262 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1263 N1, N0.getOperand(1));
1264 AddToWorkList(C3.getNode());
1265 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1266 N0.getOperand(0), C3);
1269 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1272 SDValue Sh(0,0), Y(0,0);
1273 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1274 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1275 N0.getNode()->hasOneUse()) {
1277 } else if (N1.getOpcode() == ISD::SHL &&
1278 isa<ConstantSDNode>(N1.getOperand(1)) &&
1279 N1.getNode()->hasOneUse()) {
1284 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1285 Sh.getOperand(0), Y);
1286 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1287 Mul, Sh.getOperand(1));
1291 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1292 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1293 isa<ConstantSDNode>(N0.getOperand(1)))
1294 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1295 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1296 N0.getOperand(0), N1),
1297 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1298 N0.getOperand(1), N1));
1301 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1302 if (RMUL.getNode() != 0)
1308 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1309 SDValue N0 = N->getOperand(0);
1310 SDValue N1 = N->getOperand(1);
1311 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1312 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1313 MVT VT = N->getValueType(0);
1316 if (VT.isVector()) {
1317 SDValue FoldedVOp = SimplifyVBinOp(N);
1318 if (FoldedVOp.getNode()) return FoldedVOp;
1321 // fold (sdiv c1, c2) -> c1/c2
1322 if (N0C && N1C && !N1C->isNullValue())
1323 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1324 // fold (sdiv X, 1) -> X
1325 if (N1C && N1C->getSExtValue() == 1LL)
1327 // fold (sdiv X, -1) -> 0-X
1328 if (N1C && N1C->isAllOnesValue())
1329 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1330 DAG.getConstant(0, VT), N0);
1331 // If we know the sign bits of both operands are zero, strength reduce to a
1332 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1333 if (!VT.isVector()) {
1334 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1335 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1338 // fold (sdiv X, pow2) -> simple ops after legalize
1339 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1340 (isPowerOf2_64(N1C->getSExtValue()) ||
1341 isPowerOf2_64(-N1C->getSExtValue()))) {
1342 // If dividing by powers of two is cheap, then don't perform the following
1344 if (TLI.isPow2DivCheap())
1347 int64_t pow2 = N1C->getSExtValue();
1348 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1349 unsigned lg2 = Log2_64(abs2);
1351 // Splat the sign bit into the register
1352 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1353 DAG.getConstant(VT.getSizeInBits()-1,
1354 getShiftAmountTy()));
1355 AddToWorkList(SGN.getNode());
1357 // Add (N0 < 0) ? abs2 - 1 : 0;
1358 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1359 DAG.getConstant(VT.getSizeInBits() - lg2,
1360 getShiftAmountTy()));
1361 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1362 AddToWorkList(SRL.getNode());
1363 AddToWorkList(ADD.getNode()); // Divide by pow2
1364 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1365 DAG.getConstant(lg2, getShiftAmountTy()));
1367 // If we're dividing by a positive value, we're done. Otherwise, we must
1368 // negate the result.
1372 AddToWorkList(SRA.getNode());
1373 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1374 DAG.getConstant(0, VT), SRA);
1377 // if integer divide is expensive and we satisfy the requirements, emit an
1378 // alternate sequence.
1379 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1380 !TLI.isIntDivCheap()) {
1381 SDValue Op = BuildSDIV(N);
1382 if (Op.getNode()) return Op;
1386 if (N0.getOpcode() == ISD::UNDEF)
1387 return DAG.getConstant(0, VT);
1388 // X / undef -> undef
1389 if (N1.getOpcode() == ISD::UNDEF)
1395 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1396 SDValue N0 = N->getOperand(0);
1397 SDValue N1 = N->getOperand(1);
1398 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1399 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1400 MVT VT = N->getValueType(0);
1403 if (VT.isVector()) {
1404 SDValue FoldedVOp = SimplifyVBinOp(N);
1405 if (FoldedVOp.getNode()) return FoldedVOp;
1408 // fold (udiv c1, c2) -> c1/c2
1409 if (N0C && N1C && !N1C->isNullValue())
1410 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1411 // fold (udiv x, (1 << c)) -> x >>u c
1412 if (N1C && N1C->getAPIntValue().isPowerOf2())
1413 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1414 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1415 getShiftAmountTy()));
1416 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1417 if (N1.getOpcode() == ISD::SHL) {
1418 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1419 if (SHC->getAPIntValue().isPowerOf2()) {
1420 MVT ADDVT = N1.getOperand(1).getValueType();
1421 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1423 DAG.getConstant(SHC->getAPIntValue()
1426 AddToWorkList(Add.getNode());
1427 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1431 // fold (udiv x, c) -> alternate
1432 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1433 SDValue Op = BuildUDIV(N);
1434 if (Op.getNode()) return Op;
1438 if (N0.getOpcode() == ISD::UNDEF)
1439 return DAG.getConstant(0, VT);
1440 // X / undef -> undef
1441 if (N1.getOpcode() == ISD::UNDEF)
1447 SDValue DAGCombiner::visitSREM(SDNode *N) {
1448 SDValue N0 = N->getOperand(0);
1449 SDValue N1 = N->getOperand(1);
1450 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1451 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1452 MVT VT = N->getValueType(0);
1454 // fold (srem c1, c2) -> c1%c2
1455 if (N0C && N1C && !N1C->isNullValue())
1456 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1457 // If we know the sign bits of both operands are zero, strength reduce to a
1458 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1459 if (!VT.isVector()) {
1460 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1461 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1464 // If X/C can be simplified by the division-by-constant logic, lower
1465 // X%C to the equivalent of X-X/C*C.
1466 if (N1C && !N1C->isNullValue()) {
1467 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1468 AddToWorkList(Div.getNode());
1469 SDValue OptimizedDiv = combine(Div.getNode());
1470 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1471 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1473 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1474 AddToWorkList(Mul.getNode());
1480 if (N0.getOpcode() == ISD::UNDEF)
1481 return DAG.getConstant(0, VT);
1482 // X % undef -> undef
1483 if (N1.getOpcode() == ISD::UNDEF)
1489 SDValue DAGCombiner::visitUREM(SDNode *N) {
1490 SDValue N0 = N->getOperand(0);
1491 SDValue N1 = N->getOperand(1);
1492 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1493 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1494 MVT VT = N->getValueType(0);
1496 // fold (urem c1, c2) -> c1%c2
1497 if (N0C && N1C && !N1C->isNullValue())
1498 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1499 // fold (urem x, pow2) -> (and x, pow2-1)
1500 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1501 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1502 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1503 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1504 if (N1.getOpcode() == ISD::SHL) {
1505 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1506 if (SHC->getAPIntValue().isPowerOf2()) {
1508 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1509 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1511 AddToWorkList(Add.getNode());
1512 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1517 // If X/C can be simplified by the division-by-constant logic, lower
1518 // X%C to the equivalent of X-X/C*C.
1519 if (N1C && !N1C->isNullValue()) {
1520 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1521 AddToWorkList(Div.getNode());
1522 SDValue OptimizedDiv = combine(Div.getNode());
1523 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1524 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1526 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1527 AddToWorkList(Mul.getNode());
1533 if (N0.getOpcode() == ISD::UNDEF)
1534 return DAG.getConstant(0, VT);
1535 // X % undef -> undef
1536 if (N1.getOpcode() == ISD::UNDEF)
1542 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1543 SDValue N0 = N->getOperand(0);
1544 SDValue N1 = N->getOperand(1);
1545 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1546 MVT VT = N->getValueType(0);
1548 // fold (mulhs x, 0) -> 0
1549 if (N1C && N1C->isNullValue())
1551 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1552 if (N1C && N1C->getAPIntValue() == 1)
1553 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1554 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1555 getShiftAmountTy()));
1556 // fold (mulhs x, undef) -> 0
1557 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1558 return DAG.getConstant(0, VT);
1563 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1564 SDValue N0 = N->getOperand(0);
1565 SDValue N1 = N->getOperand(1);
1566 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1567 MVT VT = N->getValueType(0);
1569 // fold (mulhu x, 0) -> 0
1570 if (N1C && N1C->isNullValue())
1572 // fold (mulhu x, 1) -> 0
1573 if (N1C && N1C->getAPIntValue() == 1)
1574 return DAG.getConstant(0, N0.getValueType());
1575 // fold (mulhu x, undef) -> 0
1576 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1577 return DAG.getConstant(0, VT);
1582 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1583 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1584 /// that are being performed. Return true if a simplification was made.
1586 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1588 // If the high half is not needed, just compute the low half.
1589 bool HiExists = N->hasAnyUseOfValue(1);
1591 (!LegalOperations ||
1592 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1593 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1594 N->op_begin(), N->getNumOperands());
1595 return CombineTo(N, Res, Res);
1598 // If the low half is not needed, just compute the high half.
1599 bool LoExists = N->hasAnyUseOfValue(0);
1601 (!LegalOperations ||
1602 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1603 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1604 N->op_begin(), N->getNumOperands());
1605 return CombineTo(N, Res, Res);
1608 // If both halves are used, return as it is.
1609 if (LoExists && HiExists)
1612 // If the two computed results can be simplified separately, separate them.
1614 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1615 N->op_begin(), N->getNumOperands());
1616 AddToWorkList(Lo.getNode());
1617 SDValue LoOpt = combine(Lo.getNode());
1618 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1619 (!LegalOperations ||
1620 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1621 return CombineTo(N, LoOpt, LoOpt);
1625 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1626 N->op_begin(), N->getNumOperands());
1627 AddToWorkList(Hi.getNode());
1628 SDValue HiOpt = combine(Hi.getNode());
1629 if (HiOpt.getNode() && HiOpt != Hi &&
1630 (!LegalOperations ||
1631 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1632 return CombineTo(N, HiOpt, HiOpt);
1638 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1639 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1640 if (Res.getNode()) return Res;
1645 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1646 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1647 if (Res.getNode()) return Res;
1652 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
1653 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1654 if (Res.getNode()) return Res;
1659 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
1660 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1661 if (Res.getNode()) return Res;
1666 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1667 /// two operands of the same opcode, try to simplify it.
1668 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1669 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1670 MVT VT = N0.getValueType();
1671 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1673 // For each of OP in AND/OR/XOR:
1674 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1675 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1676 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1677 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
1678 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1679 N0.getOpcode() == ISD::SIGN_EXTEND ||
1680 (N0.getOpcode() == ISD::TRUNCATE &&
1681 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) &&
1682 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1683 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1684 N0.getOperand(0).getValueType(),
1685 N0.getOperand(0), N1.getOperand(0));
1686 AddToWorkList(ORNode.getNode());
1687 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
1690 // For each of OP in SHL/SRL/SRA/AND...
1691 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1692 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1693 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1694 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1695 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1696 N0.getOperand(1) == N1.getOperand(1)) {
1697 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1698 N0.getOperand(0).getValueType(),
1699 N0.getOperand(0), N1.getOperand(0));
1700 AddToWorkList(ORNode.getNode());
1701 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
1702 ORNode, N0.getOperand(1));
1708 SDValue DAGCombiner::visitAND(SDNode *N) {
1709 SDValue N0 = N->getOperand(0);
1710 SDValue N1 = N->getOperand(1);
1711 SDValue LL, LR, RL, RR, CC0, CC1;
1712 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1713 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1714 MVT VT = N1.getValueType();
1715 unsigned BitWidth = VT.getSizeInBits();
1718 if (VT.isVector()) {
1719 SDValue FoldedVOp = SimplifyVBinOp(N);
1720 if (FoldedVOp.getNode()) return FoldedVOp;
1723 // fold (and x, undef) -> 0
1724 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1725 return DAG.getConstant(0, VT);
1726 // fold (and c1, c2) -> c1&c2
1728 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
1729 // canonicalize constant to RHS
1731 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
1732 // fold (and x, -1) -> x
1733 if (N1C && N1C->isAllOnesValue())
1735 // if (and x, c) is known to be zero, return 0
1736 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
1737 APInt::getAllOnesValue(BitWidth)))
1738 return DAG.getConstant(0, VT);
1740 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
1741 if (RAND.getNode() != 0)
1743 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1744 if (N1C && N0.getOpcode() == ISD::OR)
1745 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1746 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
1748 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1749 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1750 SDValue N0Op0 = N0.getOperand(0);
1751 APInt Mask = ~N1C->getAPIntValue();
1752 Mask.trunc(N0Op0.getValueSizeInBits());
1753 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
1754 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
1755 N0.getValueType(), N0Op0);
1757 // Replace uses of the AND with uses of the Zero extend node.
1760 // We actually want to replace all uses of the any_extend with the
1761 // zero_extend, to avoid duplicating things. This will later cause this
1762 // AND to be folded.
1763 CombineTo(N0.getNode(), Zext);
1764 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1767 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1768 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1769 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1770 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1772 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1773 LL.getValueType().isInteger()) {
1774 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
1775 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
1776 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1777 LR.getValueType(), LL, RL);
1778 AddToWorkList(ORNode.getNode());
1779 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1781 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
1782 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1783 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
1784 LR.getValueType(), LL, RL);
1785 AddToWorkList(ANDNode.getNode());
1786 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1788 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
1789 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1790 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1791 LR.getValueType(), LL, RL);
1792 AddToWorkList(ORNode.getNode());
1793 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1796 // canonicalize equivalent to ll == rl
1797 if (LL == RR && LR == RL) {
1798 Op1 = ISD::getSetCCSwappedOperands(Op1);
1801 if (LL == RL && LR == RR) {
1802 bool isInteger = LL.getValueType().isInteger();
1803 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1804 if (Result != ISD::SETCC_INVALID &&
1805 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
1806 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
1811 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
1812 if (N0.getOpcode() == N1.getOpcode()) {
1813 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1814 if (Tmp.getNode()) return Tmp;
1817 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1818 // fold (and (sra)) -> (and (srl)) when possible.
1819 if (!VT.isVector() &&
1820 SimplifyDemandedBits(SDValue(N, 0)))
1821 return SDValue(N, 0);
1822 // fold (zext_inreg (extload x)) -> (zextload x)
1823 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
1824 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1825 MVT EVT = LN0->getMemoryVT();
1826 // If we zero all the possible extended bits, then we can turn this into
1827 // a zextload if we are running before legalize or the operation is legal.
1828 unsigned BitWidth = N1.getValueSizeInBits();
1829 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1830 BitWidth - EVT.getSizeInBits())) &&
1831 ((!LegalOperations && !LN0->isVolatile()) ||
1832 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1833 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1834 LN0->getChain(), LN0->getBasePtr(),
1836 LN0->getSrcValueOffset(), EVT,
1837 LN0->isVolatile(), LN0->getAlignment());
1839 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1840 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1843 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1844 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
1846 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1847 MVT EVT = LN0->getMemoryVT();
1848 // If we zero all the possible extended bits, then we can turn this into
1849 // a zextload if we are running before legalize or the operation is legal.
1850 unsigned BitWidth = N1.getValueSizeInBits();
1851 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1852 BitWidth - EVT.getSizeInBits())) &&
1853 ((!LegalOperations && !LN0->isVolatile()) ||
1854 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1855 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1857 LN0->getBasePtr(), LN0->getSrcValue(),
1858 LN0->getSrcValueOffset(), EVT,
1859 LN0->isVolatile(), LN0->getAlignment());
1861 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1862 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1866 // fold (and (load x), 255) -> (zextload x, i8)
1867 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1868 if (N1C && N0.getOpcode() == ISD::LOAD) {
1869 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1870 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1871 LN0->isUnindexed() && N0.hasOneUse() &&
1872 // Do not change the width of a volatile load.
1873 !LN0->isVolatile()) {
1874 MVT EVT = MVT::Other;
1875 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
1876 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
1877 EVT = MVT::getIntegerVT(ActiveBits);
1879 MVT LoadedVT = LN0->getMemoryVT();
1881 // Do not generate loads of non-round integer types since these can
1882 // be expensive (and would be wrong if the type is not byte sized).
1883 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() &&
1884 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1885 MVT PtrType = N0.getOperand(1).getValueType();
1887 // For big endian targets, we need to add an offset to the pointer to
1888 // load the correct bytes. For little endian systems, we merely need to
1889 // read fewer bytes from the same pointer.
1890 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
1891 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
1892 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1893 unsigned Alignment = LN0->getAlignment();
1894 SDValue NewPtr = LN0->getBasePtr();
1896 if (TLI.isBigEndian()) {
1897 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
1898 NewPtr, DAG.getConstant(PtrOff, PtrType));
1899 Alignment = MinAlign(Alignment, PtrOff);
1902 AddToWorkList(NewPtr.getNode());
1904 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(),
1905 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(),
1906 EVT, LN0->isVolatile(), Alignment);
1908 CombineTo(N0.getNode(), Load, Load.getValue(1));
1909 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1917 SDValue DAGCombiner::visitOR(SDNode *N) {
1918 SDValue N0 = N->getOperand(0);
1919 SDValue N1 = N->getOperand(1);
1920 SDValue LL, LR, RL, RR, CC0, CC1;
1921 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1922 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1923 MVT VT = N1.getValueType();
1926 if (VT.isVector()) {
1927 SDValue FoldedVOp = SimplifyVBinOp(N);
1928 if (FoldedVOp.getNode()) return FoldedVOp;
1931 // fold (or x, undef) -> -1
1932 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1933 return DAG.getConstant(~0ULL, VT);
1934 // fold (or c1, c2) -> c1|c2
1936 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
1937 // canonicalize constant to RHS
1939 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
1940 // fold (or x, 0) -> x
1941 if (N1C && N1C->isNullValue())
1943 // fold (or x, -1) -> -1
1944 if (N1C && N1C->isAllOnesValue())
1946 // fold (or x, c) -> c iff (x & ~c) == 0
1947 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
1950 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
1951 if (ROR.getNode() != 0)
1953 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1954 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
1955 isa<ConstantSDNode>(N0.getOperand(1))) {
1956 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1957 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
1958 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
1959 N0.getOperand(0), N1),
1960 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
1962 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1963 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1964 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1965 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1967 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1968 LL.getValueType().isInteger()) {
1969 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
1970 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
1971 if (cast<ConstantSDNode>(LR)->isNullValue() &&
1972 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1973 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
1974 LR.getValueType(), LL, RL);
1975 AddToWorkList(ORNode.getNode());
1976 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1978 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
1979 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
1980 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1981 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1982 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
1983 LR.getValueType(), LL, RL);
1984 AddToWorkList(ANDNode.getNode());
1985 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1988 // canonicalize equivalent to ll == rl
1989 if (LL == RR && LR == RL) {
1990 Op1 = ISD::getSetCCSwappedOperands(Op1);
1993 if (LL == RL && LR == RR) {
1994 bool isInteger = LL.getValueType().isInteger();
1995 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1996 if (Result != ISD::SETCC_INVALID &&
1997 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
1998 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2003 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2004 if (N0.getOpcode() == N1.getOpcode()) {
2005 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2006 if (Tmp.getNode()) return Tmp;
2009 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2010 if (N0.getOpcode() == ISD::AND &&
2011 N1.getOpcode() == ISD::AND &&
2012 N0.getOperand(1).getOpcode() == ISD::Constant &&
2013 N1.getOperand(1).getOpcode() == ISD::Constant &&
2014 // Don't increase # computations.
2015 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2016 // We can only do this xform if we know that bits from X that are set in C2
2017 // but not in C1 are already zero. Likewise for Y.
2018 const APInt &LHSMask =
2019 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2020 const APInt &RHSMask =
2021 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2023 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2024 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2025 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2026 N0.getOperand(0), N1.getOperand(0));
2027 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2028 DAG.getConstant(LHSMask | RHSMask, VT));
2032 // See if this is some rotate idiom.
2033 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2034 return SDValue(Rot, 0);
2039 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2040 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2041 if (Op.getOpcode() == ISD::AND) {
2042 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2043 Mask = Op.getOperand(1);
2044 Op = Op.getOperand(0);
2050 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2058 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2059 // idioms for rotate, and if the target supports rotation instructions, generate
2061 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2062 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2063 MVT VT = LHS.getValueType();
2064 if (!TLI.isTypeLegal(VT)) return 0;
2066 // The target must have at least one rotate flavor.
2067 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2068 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2069 if (!HasROTL && !HasROTR) return 0;
2071 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2072 SDValue LHSShift; // The shift.
2073 SDValue LHSMask; // AND value if any.
2074 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2075 return 0; // Not part of a rotate.
2077 SDValue RHSShift; // The shift.
2078 SDValue RHSMask; // AND value if any.
2079 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2080 return 0; // Not part of a rotate.
2082 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2083 return 0; // Not shifting the same value.
2085 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2086 return 0; // Shifts must disagree.
2088 // Canonicalize shl to left side in a shl/srl pair.
2089 if (RHSShift.getOpcode() == ISD::SHL) {
2090 std::swap(LHS, RHS);
2091 std::swap(LHSShift, RHSShift);
2092 std::swap(LHSMask , RHSMask );
2095 unsigned OpSizeInBits = VT.getSizeInBits();
2096 SDValue LHSShiftArg = LHSShift.getOperand(0);
2097 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2098 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2100 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2101 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2102 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2103 RHSShiftAmt.getOpcode() == ISD::Constant) {
2104 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2105 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2106 if ((LShVal + RShVal) != OpSizeInBits)
2111 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2113 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2115 // If there is an AND of either shifted operand, apply it to the result.
2116 if (LHSMask.getNode() || RHSMask.getNode()) {
2117 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2119 if (LHSMask.getNode()) {
2120 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2121 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2123 if (RHSMask.getNode()) {
2124 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2125 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2128 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2131 return Rot.getNode();
2134 // If there is a mask here, and we have a variable shift, we can't be sure
2135 // that we're masking out the right stuff.
2136 if (LHSMask.getNode() || RHSMask.getNode())
2139 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2140 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2141 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2142 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2143 if (ConstantSDNode *SUBC =
2144 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2145 if (SUBC->getAPIntValue() == OpSizeInBits) {
2147 return DAG.getNode(ISD::ROTL, DL, VT,
2148 LHSShiftArg, LHSShiftAmt).getNode();
2150 return DAG.getNode(ISD::ROTR, DL, VT,
2151 LHSShiftArg, RHSShiftAmt).getNode();
2156 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2157 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2158 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2159 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2160 if (ConstantSDNode *SUBC =
2161 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2162 if (SUBC->getAPIntValue() == OpSizeInBits) {
2164 return DAG.getNode(ISD::ROTR, DL, VT,
2165 LHSShiftArg, RHSShiftAmt).getNode();
2167 return DAG.getNode(ISD::ROTL, DL, VT,
2168 LHSShiftArg, LHSShiftAmt).getNode();
2173 // Look for sign/zext/any-extended or truncate cases:
2174 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2175 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2176 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2177 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2178 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2179 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2180 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2181 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2182 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2183 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2184 if (RExtOp0.getOpcode() == ISD::SUB &&
2185 RExtOp0.getOperand(1) == LExtOp0) {
2186 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2188 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2189 // (rotr x, (sub 32, y))
2190 if (ConstantSDNode *SUBC =
2191 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2192 if (SUBC->getAPIntValue() == OpSizeInBits) {
2193 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2195 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2198 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2199 RExtOp0 == LExtOp0.getOperand(1)) {
2200 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2202 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2203 // (rotl x, (sub 32, y))
2204 if (ConstantSDNode *SUBC =
2205 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2206 if (SUBC->getAPIntValue() == OpSizeInBits) {
2207 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2209 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2218 SDValue DAGCombiner::visitXOR(SDNode *N) {
2219 SDValue N0 = N->getOperand(0);
2220 SDValue N1 = N->getOperand(1);
2221 SDValue LHS, RHS, CC;
2222 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2223 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2224 MVT VT = N0.getValueType();
2227 if (VT.isVector()) {
2228 SDValue FoldedVOp = SimplifyVBinOp(N);
2229 if (FoldedVOp.getNode()) return FoldedVOp;
2232 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2233 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2234 return DAG.getConstant(0, VT);
2235 // fold (xor x, undef) -> undef
2236 if (N0.getOpcode() == ISD::UNDEF)
2238 if (N1.getOpcode() == ISD::UNDEF)
2240 // fold (xor c1, c2) -> c1^c2
2242 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2243 // canonicalize constant to RHS
2245 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2246 // fold (xor x, 0) -> x
2247 if (N1C && N1C->isNullValue())
2250 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2251 if (RXOR.getNode() != 0)
2254 // fold !(x cc y) -> (x !cc y)
2255 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2256 bool isInt = LHS.getValueType().isInteger();
2257 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2260 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2261 switch (N0.getOpcode()) {
2263 llvm_unreachable("Unhandled SetCC Equivalent!");
2265 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2266 case ISD::SELECT_CC:
2267 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2268 N0.getOperand(3), NotCC);
2273 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2274 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2275 N0.getNode()->hasOneUse() &&
2276 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2277 SDValue V = N0.getOperand(0);
2278 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2279 DAG.getConstant(1, V.getValueType()));
2280 AddToWorkList(V.getNode());
2281 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2284 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2285 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2286 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2287 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2288 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2289 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2290 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2291 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2292 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2293 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2296 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2297 if (N1C && N1C->isAllOnesValue() &&
2298 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2299 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2300 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2301 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2302 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2303 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2304 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2305 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2308 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2309 if (N1C && N0.getOpcode() == ISD::XOR) {
2310 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2311 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2313 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2314 DAG.getConstant(N1C->getAPIntValue() ^
2315 N00C->getAPIntValue(), VT));
2317 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2318 DAG.getConstant(N1C->getAPIntValue() ^
2319 N01C->getAPIntValue(), VT));
2321 // fold (xor x, x) -> 0
2323 if (!VT.isVector()) {
2324 return DAG.getConstant(0, VT);
2325 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2326 // Produce a vector of zeros.
2327 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2328 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2329 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2330 &Ops[0], Ops.size());
2334 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2335 if (N0.getOpcode() == N1.getOpcode()) {
2336 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2337 if (Tmp.getNode()) return Tmp;
2340 // Simplify the expression using non-local knowledge.
2341 if (!VT.isVector() &&
2342 SimplifyDemandedBits(SDValue(N, 0)))
2343 return SDValue(N, 0);
2348 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2349 /// the shift amount is a constant.
2350 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2351 SDNode *LHS = N->getOperand(0).getNode();
2352 if (!LHS->hasOneUse()) return SDValue();
2354 // We want to pull some binops through shifts, so that we have (and (shift))
2355 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2356 // thing happens with address calculations, so it's important to canonicalize
2358 bool HighBitSet = false; // Can we transform this if the high bit is set?
2360 switch (LHS->getOpcode()) {
2361 default: return SDValue();
2364 HighBitSet = false; // We can only transform sra if the high bit is clear.
2367 HighBitSet = true; // We can only transform sra if the high bit is set.
2370 if (N->getOpcode() != ISD::SHL)
2371 return SDValue(); // only shl(add) not sr[al](add).
2372 HighBitSet = false; // We can only transform sra if the high bit is clear.
2376 // We require the RHS of the binop to be a constant as well.
2377 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2378 if (!BinOpCst) return SDValue();
2380 // FIXME: disable this unless the input to the binop is a shift by a constant.
2381 // If it is not a shift, it pessimizes some common cases like:
2383 // void foo(int *X, int i) { X[i & 1235] = 1; }
2384 // int bar(int *X, int i) { return X[i & 255]; }
2385 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2386 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2387 BinOpLHSVal->getOpcode() != ISD::SRA &&
2388 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2389 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2392 MVT VT = N->getValueType(0);
2394 // If this is a signed shift right, and the high bit is modified by the
2395 // logical operation, do not perform the transformation. The highBitSet
2396 // boolean indicates the value of the high bit of the constant which would
2397 // cause it to be modified for this operation.
2398 if (N->getOpcode() == ISD::SRA) {
2399 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2400 if (BinOpRHSSignSet != HighBitSet)
2404 // Fold the constants, shifting the binop RHS by the shift amount.
2405 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2407 LHS->getOperand(1), N->getOperand(1));
2409 // Create the new shift.
2410 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2411 VT, LHS->getOperand(0), N->getOperand(1));
2413 // Create the new binop.
2414 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2417 SDValue DAGCombiner::visitSHL(SDNode *N) {
2418 SDValue N0 = N->getOperand(0);
2419 SDValue N1 = N->getOperand(1);
2420 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2421 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2422 MVT VT = N0.getValueType();
2423 unsigned OpSizeInBits = VT.getSizeInBits();
2425 // fold (shl c1, c2) -> c1<<c2
2427 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2428 // fold (shl 0, x) -> 0
2429 if (N0C && N0C->isNullValue())
2431 // fold (shl x, c >= size(x)) -> undef
2432 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2433 return DAG.getUNDEF(VT);
2434 // fold (shl x, 0) -> x
2435 if (N1C && N1C->isNullValue())
2437 // if (shl x, c) is known to be zero, return 0
2438 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2439 APInt::getAllOnesValue(VT.getSizeInBits())))
2440 return DAG.getConstant(0, VT);
2441 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2442 if (N1.getOpcode() == ISD::TRUNCATE &&
2443 N1.getOperand(0).getOpcode() == ISD::AND &&
2444 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2445 SDValue N101 = N1.getOperand(0).getOperand(1);
2446 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2447 MVT TruncVT = N1.getValueType();
2448 SDValue N100 = N1.getOperand(0).getOperand(0);
2449 APInt TruncC = N101C->getAPIntValue();
2450 TruncC.trunc(TruncVT.getSizeInBits());
2451 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2452 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2453 DAG.getNode(ISD::TRUNCATE,
2456 DAG.getConstant(TruncC, TruncVT)));
2460 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2461 return SDValue(N, 0);
2463 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2464 if (N1C && N0.getOpcode() == ISD::SHL &&
2465 N0.getOperand(1).getOpcode() == ISD::Constant) {
2466 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2467 uint64_t c2 = N1C->getZExtValue();
2468 if (c1 + c2 > OpSizeInBits)
2469 return DAG.getConstant(0, VT);
2470 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2471 DAG.getConstant(c1 + c2, N1.getValueType()));
2473 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2474 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2475 if (N1C && N0.getOpcode() == ISD::SRL &&
2476 N0.getOperand(1).getOpcode() == ISD::Constant) {
2477 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2478 if (c1 < VT.getSizeInBits()) {
2479 uint64_t c2 = N1C->getZExtValue();
2480 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT,
2482 DAG.getConstant(~0ULL << c1, VT));
2484 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2485 DAG.getConstant(c2-c1, N1.getValueType()));
2487 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2488 DAG.getConstant(c1-c2, N1.getValueType()));
2491 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2492 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2493 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2494 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT));
2496 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2499 SDValue DAGCombiner::visitSRA(SDNode *N) {
2500 SDValue N0 = N->getOperand(0);
2501 SDValue N1 = N->getOperand(1);
2502 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2503 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2504 MVT VT = N0.getValueType();
2506 // fold (sra c1, c2) -> (sra c1, c2)
2508 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2509 // fold (sra 0, x) -> 0
2510 if (N0C && N0C->isNullValue())
2512 // fold (sra -1, x) -> -1
2513 if (N0C && N0C->isAllOnesValue())
2515 // fold (sra x, (setge c, size(x))) -> undef
2516 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits())
2517 return DAG.getUNDEF(VT);
2518 // fold (sra x, 0) -> x
2519 if (N1C && N1C->isNullValue())
2521 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2523 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2524 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
2525 MVT EVT = MVT::getIntegerVT(LowBits);
2526 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
2527 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2528 N0.getOperand(0), DAG.getValueType(EVT));
2531 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2532 if (N1C && N0.getOpcode() == ISD::SRA) {
2533 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2534 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2535 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
2536 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2537 DAG.getConstant(Sum, N1C->getValueType(0)));
2541 // fold (sra (shl X, m), (sub result_size, n))
2542 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2543 // result_size - n != m.
2544 // If truncate is free for the target sext(shl) is likely to result in better
2546 if (N0.getOpcode() == ISD::SHL) {
2547 // Get the two constanst of the shifts, CN0 = m, CN = n.
2548 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2550 // Determine what the truncate's result bitsize and type would be.
2551 unsigned VTValSize = VT.getSizeInBits();
2553 MVT::getIntegerVT(VTValSize - N1C->getZExtValue());
2554 // Determine the residual right-shift amount.
2555 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2557 // If the shift is not a no-op (in which case this should be just a sign
2558 // extend already), the truncated to type is legal, sign_extend is legal
2559 // on that type, and the the truncate to that type is both legal and free,
2560 // perform the transform.
2561 if ((ShiftAmt > 0) &&
2562 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2563 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
2564 TLI.isTruncateFree(VT, TruncVT)) {
2566 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
2567 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
2568 N0.getOperand(0), Amt);
2569 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
2571 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
2572 N->getValueType(0), Trunc);
2577 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
2578 if (N1.getOpcode() == ISD::TRUNCATE &&
2579 N1.getOperand(0).getOpcode() == ISD::AND &&
2580 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2581 SDValue N101 = N1.getOperand(0).getOperand(1);
2582 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2583 MVT TruncVT = N1.getValueType();
2584 SDValue N100 = N1.getOperand(0).getOperand(0);
2585 APInt TruncC = N101C->getAPIntValue();
2586 TruncC.trunc(TruncVT.getSizeInBits());
2587 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
2588 DAG.getNode(ISD::AND, N->getDebugLoc(),
2590 DAG.getNode(ISD::TRUNCATE,
2593 DAG.getConstant(TruncC, TruncVT)));
2597 // Simplify, based on bits shifted out of the LHS.
2598 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2599 return SDValue(N, 0);
2602 // If the sign bit is known to be zero, switch this to a SRL.
2603 if (DAG.SignBitIsZero(N0))
2604 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
2606 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2609 SDValue DAGCombiner::visitSRL(SDNode *N) {
2610 SDValue N0 = N->getOperand(0);
2611 SDValue N1 = N->getOperand(1);
2612 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2613 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2614 MVT VT = N0.getValueType();
2615 unsigned OpSizeInBits = VT.getSizeInBits();
2617 // fold (srl c1, c2) -> c1 >>u c2
2619 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
2620 // fold (srl 0, x) -> 0
2621 if (N0C && N0C->isNullValue())
2623 // fold (srl x, c >= size(x)) -> undef
2624 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2625 return DAG.getUNDEF(VT);
2626 // fold (srl x, 0) -> x
2627 if (N1C && N1C->isNullValue())
2629 // if (srl x, c) is known to be zero, return 0
2630 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2631 APInt::getAllOnesValue(OpSizeInBits)))
2632 return DAG.getConstant(0, VT);
2634 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
2635 if (N1C && N0.getOpcode() == ISD::SRL &&
2636 N0.getOperand(1).getOpcode() == ISD::Constant) {
2637 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2638 uint64_t c2 = N1C->getZExtValue();
2639 if (c1 + c2 > OpSizeInBits)
2640 return DAG.getConstant(0, VT);
2641 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
2642 DAG.getConstant(c1 + c2, N1.getValueType()));
2645 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2646 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2647 // Shifting in all undef bits?
2648 MVT SmallVT = N0.getOperand(0).getValueType();
2649 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
2650 return DAG.getUNDEF(VT);
2652 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
2653 N0.getOperand(0), N1);
2654 AddToWorkList(SmallShift.getNode());
2655 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
2658 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2659 // bit, which is unmodified by sra.
2660 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
2661 if (N0.getOpcode() == ISD::SRA)
2662 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
2665 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2666 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2667 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
2668 APInt KnownZero, KnownOne;
2669 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
2670 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2672 // If any of the input bits are KnownOne, then the input couldn't be all
2673 // zeros, thus the result of the srl will always be zero.
2674 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
2676 // If all of the bits input the to ctlz node are known to be zero, then
2677 // the result of the ctlz is "32" and the result of the shift is one.
2678 APInt UnknownBits = ~KnownZero & Mask;
2679 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2681 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2682 if ((UnknownBits & (UnknownBits - 1)) == 0) {
2683 // Okay, we know that only that the single bit specified by UnknownBits
2684 // could be set on input to the CTLZ node. If this bit is set, the SRL
2685 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2686 // to an SRL/XOR pair, which is likely to simplify more.
2687 unsigned ShAmt = UnknownBits.countTrailingZeros();
2688 SDValue Op = N0.getOperand(0);
2691 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
2692 DAG.getConstant(ShAmt, getShiftAmountTy()));
2693 AddToWorkList(Op.getNode());
2696 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
2697 Op, DAG.getConstant(1, VT));
2701 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
2702 if (N1.getOpcode() == ISD::TRUNCATE &&
2703 N1.getOperand(0).getOpcode() == ISD::AND &&
2704 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2705 SDValue N101 = N1.getOperand(0).getOperand(1);
2706 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2707 MVT TruncVT = N1.getValueType();
2708 SDValue N100 = N1.getOperand(0).getOperand(0);
2709 APInt TruncC = N101C->getAPIntValue();
2710 TruncC.trunc(TruncVT.getSizeInBits());
2711 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
2712 DAG.getNode(ISD::AND, N->getDebugLoc(),
2714 DAG.getNode(ISD::TRUNCATE,
2717 DAG.getConstant(TruncC, TruncVT)));
2721 // fold operands of srl based on knowledge that the low bits are not
2723 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2724 return SDValue(N, 0);
2726 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2729 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
2730 SDValue N0 = N->getOperand(0);
2731 MVT VT = N->getValueType(0);
2733 // fold (ctlz c1) -> c2
2734 if (isa<ConstantSDNode>(N0))
2735 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
2739 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
2740 SDValue N0 = N->getOperand(0);
2741 MVT VT = N->getValueType(0);
2743 // fold (cttz c1) -> c2
2744 if (isa<ConstantSDNode>(N0))
2745 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
2749 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
2750 SDValue N0 = N->getOperand(0);
2751 MVT VT = N->getValueType(0);
2753 // fold (ctpop c1) -> c2
2754 if (isa<ConstantSDNode>(N0))
2755 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
2759 SDValue DAGCombiner::visitSELECT(SDNode *N) {
2760 SDValue N0 = N->getOperand(0);
2761 SDValue N1 = N->getOperand(1);
2762 SDValue N2 = N->getOperand(2);
2763 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2764 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2765 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2766 MVT VT = N->getValueType(0);
2767 MVT VT0 = N0.getValueType();
2769 // fold (select C, X, X) -> X
2772 // fold (select true, X, Y) -> X
2773 if (N0C && !N0C->isNullValue())
2775 // fold (select false, X, Y) -> Y
2776 if (N0C && N0C->isNullValue())
2778 // fold (select C, 1, X) -> (or C, X)
2779 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
2780 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2781 // fold (select C, 0, 1) -> (xor C, 1)
2782 if (VT.isInteger() &&
2785 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
2786 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
2789 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
2790 N0, DAG.getConstant(1, VT0));
2791 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
2792 N0, DAG.getConstant(1, VT0));
2793 AddToWorkList(XORNode.getNode());
2795 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
2796 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
2798 // fold (select C, 0, X) -> (and (not C), X)
2799 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2800 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2801 AddToWorkList(NOTNode.getNode());
2802 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
2804 // fold (select C, X, 1) -> (or (not C), X)
2805 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
2806 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2807 AddToWorkList(NOTNode.getNode());
2808 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
2810 // fold (select C, X, 0) -> (and C, X)
2811 if (VT == MVT::i1 && N2C && N2C->isNullValue())
2812 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2813 // fold (select X, X, Y) -> (or X, Y)
2814 // fold (select X, 1, Y) -> (or X, Y)
2815 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
2816 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2817 // fold (select X, Y, X) -> (and X, Y)
2818 // fold (select X, Y, 0) -> (and X, Y)
2819 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
2820 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2822 // If we can fold this based on the true/false value, do so.
2823 if (SimplifySelectOps(N, N1, N2))
2824 return SDValue(N, 0); // Don't revisit N.
2826 // fold selects based on a setcc into other things, such as min/max/abs
2827 if (N0.getOpcode() == ISD::SETCC) {
2829 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2830 // having to say they don't support SELECT_CC on every type the DAG knows
2831 // about, since there is no way to mark an opcode illegal at all value types
2832 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
2833 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
2834 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
2835 N0.getOperand(0), N0.getOperand(1),
2836 N1, N2, N0.getOperand(2));
2837 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
2843 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
2844 SDValue N0 = N->getOperand(0);
2845 SDValue N1 = N->getOperand(1);
2846 SDValue N2 = N->getOperand(2);
2847 SDValue N3 = N->getOperand(3);
2848 SDValue N4 = N->getOperand(4);
2849 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2851 // fold select_cc lhs, rhs, x, x, cc -> x
2855 // Determine if the condition we're dealing with is constant
2856 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
2857 N0, N1, CC, N->getDebugLoc(), false);
2858 if (SCC.getNode()) AddToWorkList(SCC.getNode());
2860 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
2861 if (!SCCC->isNullValue())
2862 return N2; // cond always true -> true val
2864 return N3; // cond always false -> false val
2867 // Fold to a simpler select_cc
2868 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
2869 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
2870 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2873 // If we can fold this based on the true/false value, do so.
2874 if (SimplifySelectOps(N, N2, N3))
2875 return SDValue(N, 0); // Don't revisit N.
2877 // fold select_cc into other things, such as min/max/abs
2878 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
2881 SDValue DAGCombiner::visitSETCC(SDNode *N) {
2882 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2883 cast<CondCodeSDNode>(N->getOperand(2))->get(),
2887 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2888 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
2889 // transformation. Returns true if extension are possible and the above
2890 // mentioned transformation is profitable.
2891 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
2893 SmallVector<SDNode*, 4> &ExtendNodes,
2894 const TargetLowering &TLI) {
2895 bool HasCopyToRegUses = false;
2896 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2897 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
2898 UE = N0.getNode()->use_end();
2903 if (UI.getUse().getResNo() != N0.getResNo())
2905 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2906 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
2907 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2908 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2909 // Sign bits will be lost after a zext.
2912 for (unsigned i = 0; i != 2; ++i) {
2913 SDValue UseOp = User->getOperand(i);
2916 if (!isa<ConstantSDNode>(UseOp))
2921 ExtendNodes.push_back(User);
2924 // If truncates aren't free and there are users we can't
2925 // extend, it isn't worthwhile.
2928 // Remember if this value is live-out.
2929 if (User->getOpcode() == ISD::CopyToReg)
2930 HasCopyToRegUses = true;
2933 if (HasCopyToRegUses) {
2934 bool BothLiveOut = false;
2935 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2937 SDUse &Use = UI.getUse();
2938 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
2944 // Both unextended and extended values are live out. There had better be
2945 // good a reason for the transformation.
2946 return ExtendNodes.size();
2951 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2952 SDValue N0 = N->getOperand(0);
2953 MVT VT = N->getValueType(0);
2955 // fold (sext c1) -> c1
2956 if (isa<ConstantSDNode>(N0))
2957 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
2959 // fold (sext (sext x)) -> (sext x)
2960 // fold (sext (aext x)) -> (sext x)
2961 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2962 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
2965 if (N0.getOpcode() == ISD::TRUNCATE) {
2966 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2967 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2968 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
2969 if (NarrowLoad.getNode()) {
2970 if (NarrowLoad.getNode() != N0.getNode())
2971 CombineTo(N0.getNode(), NarrowLoad);
2972 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2975 // See if the value being truncated is already sign extended. If so, just
2976 // eliminate the trunc/sext pair.
2977 SDValue Op = N0.getOperand(0);
2978 unsigned OpBits = Op.getValueType().getSizeInBits();
2979 unsigned MidBits = N0.getValueType().getSizeInBits();
2980 unsigned DestBits = VT.getSizeInBits();
2981 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2983 if (OpBits == DestBits) {
2984 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2985 // bits, it is already ready.
2986 if (NumSignBits > DestBits-MidBits)
2988 } else if (OpBits < DestBits) {
2989 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2990 // bits, just sext from i32.
2991 if (NumSignBits > OpBits-MidBits)
2992 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
2994 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2995 // bits, just truncate to i32.
2996 if (NumSignBits > OpBits-MidBits)
2997 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3000 // fold (sext (truncate x)) -> (sextinreg x).
3001 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3002 N0.getValueType())) {
3003 if (Op.getValueType().bitsLT(VT))
3004 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3005 else if (Op.getValueType().bitsGT(VT))
3006 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3007 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3008 DAG.getValueType(N0.getValueType()));
3012 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3013 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3014 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3015 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3016 bool DoXform = true;
3017 SmallVector<SDNode*, 4> SetCCs;
3018 if (!N0.hasOneUse())
3019 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3021 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3022 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3024 LN0->getBasePtr(), LN0->getSrcValue(),
3025 LN0->getSrcValueOffset(),
3027 LN0->isVolatile(), LN0->getAlignment());
3028 CombineTo(N, ExtLoad);
3029 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3030 N0.getValueType(), ExtLoad);
3031 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3033 // Extend SetCC uses if necessary.
3034 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3035 SDNode *SetCC = SetCCs[i];
3036 SmallVector<SDValue, 4> Ops;
3038 for (unsigned j = 0; j != 2; ++j) {
3039 SDValue SOp = SetCC->getOperand(j);
3041 Ops.push_back(ExtLoad);
3043 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3044 N->getDebugLoc(), VT, SOp));
3047 Ops.push_back(SetCC->getOperand(2));
3048 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3049 SetCC->getValueType(0),
3050 &Ops[0], Ops.size()));
3053 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3057 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3058 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3059 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3060 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3061 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3062 MVT EVT = LN0->getMemoryVT();
3063 if ((!LegalOperations && !LN0->isVolatile()) ||
3064 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) {
3065 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3067 LN0->getBasePtr(), LN0->getSrcValue(),
3068 LN0->getSrcValueOffset(), EVT,
3069 LN0->isVolatile(), LN0->getAlignment());
3070 CombineTo(N, ExtLoad);
3071 CombineTo(N0.getNode(),
3072 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3073 N0.getValueType(), ExtLoad),
3074 ExtLoad.getValue(1));
3075 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3079 if (N0.getOpcode() == ISD::SETCC) {
3080 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
3081 if (VT.isVector() &&
3082 // We know that the # elements of the results is the same as the
3083 // # elements of the compare (and the # elements of the compare result
3084 // for that matter). Check to see that they are the same size. If so,
3085 // we know that the element size of the sext'd result matches the
3086 // element size of the compare operands.
3087 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() &&
3089 // Only do this before legalize for now.
3091 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3093 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3096 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3098 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3099 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
3100 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3101 if (SCC.getNode()) return SCC;
3106 // fold (sext x) -> (zext x) if the sign bit is known zero.
3107 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3108 DAG.SignBitIsZero(N0))
3109 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3114 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3115 SDValue N0 = N->getOperand(0);
3116 MVT VT = N->getValueType(0);
3118 // fold (zext c1) -> c1
3119 if (isa<ConstantSDNode>(N0))
3120 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3121 // fold (zext (zext x)) -> (zext x)
3122 // fold (zext (aext x)) -> (zext x)
3123 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3124 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3127 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3128 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3129 if (N0.getOpcode() == ISD::TRUNCATE) {
3130 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3131 if (NarrowLoad.getNode()) {
3132 if (NarrowLoad.getNode() != N0.getNode())
3133 CombineTo(N0.getNode(), NarrowLoad);
3134 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3138 // fold (zext (truncate x)) -> (and x, mask)
3139 if (N0.getOpcode() == ISD::TRUNCATE &&
3140 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
3141 SDValue Op = N0.getOperand(0);
3142 if (Op.getValueType().bitsLT(VT)) {
3143 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3144 } else if (Op.getValueType().bitsGT(VT)) {
3145 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3147 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType());
3150 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
3151 // if either of the casts is not free.
3152 if (N0.getOpcode() == ISD::AND &&
3153 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3154 N0.getOperand(1).getOpcode() == ISD::Constant &&
3155 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3156 N0.getValueType()) ||
3157 !TLI.isZExtFree(N0.getValueType(), VT))) {
3158 SDValue X = N0.getOperand(0).getOperand(0);
3159 if (X.getValueType().bitsLT(VT)) {
3160 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3161 } else if (X.getValueType().bitsGT(VT)) {
3162 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3164 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3165 Mask.zext(VT.getSizeInBits());
3166 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3167 X, DAG.getConstant(Mask, VT));
3170 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3171 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3172 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3173 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3174 bool DoXform = true;
3175 SmallVector<SDNode*, 4> SetCCs;
3176 if (!N0.hasOneUse())
3177 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3179 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3180 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3182 LN0->getBasePtr(), LN0->getSrcValue(),
3183 LN0->getSrcValueOffset(),
3185 LN0->isVolatile(), LN0->getAlignment());
3186 CombineTo(N, ExtLoad);
3187 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3188 N0.getValueType(), ExtLoad);
3189 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3191 // Extend SetCC uses if necessary.
3192 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3193 SDNode *SetCC = SetCCs[i];
3194 SmallVector<SDValue, 4> Ops;
3196 for (unsigned j = 0; j != 2; ++j) {
3197 SDValue SOp = SetCC->getOperand(j);
3199 Ops.push_back(ExtLoad);
3201 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3202 N->getDebugLoc(), VT, SOp));
3205 Ops.push_back(SetCC->getOperand(2));
3206 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3207 SetCC->getValueType(0),
3208 &Ops[0], Ops.size()));
3211 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3215 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3216 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3217 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3218 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3219 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3220 MVT EVT = LN0->getMemoryVT();
3221 if ((!LegalOperations && !LN0->isVolatile()) ||
3222 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) {
3223 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3225 LN0->getBasePtr(), LN0->getSrcValue(),
3226 LN0->getSrcValueOffset(), EVT,
3227 LN0->isVolatile(), LN0->getAlignment());
3228 CombineTo(N, ExtLoad);
3229 CombineTo(N0.getNode(),
3230 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3232 ExtLoad.getValue(1));
3233 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3237 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3238 if (N0.getOpcode() == ISD::SETCC) {
3240 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3241 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3242 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3243 if (SCC.getNode()) return SCC;
3249 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3250 SDValue N0 = N->getOperand(0);
3251 MVT VT = N->getValueType(0);
3253 // fold (aext c1) -> c1
3254 if (isa<ConstantSDNode>(N0))
3255 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3256 // fold (aext (aext x)) -> (aext x)
3257 // fold (aext (zext x)) -> (zext x)
3258 // fold (aext (sext x)) -> (sext x)
3259 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3260 N0.getOpcode() == ISD::ZERO_EXTEND ||
3261 N0.getOpcode() == ISD::SIGN_EXTEND)
3262 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3264 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3265 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3266 if (N0.getOpcode() == ISD::TRUNCATE) {
3267 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3268 if (NarrowLoad.getNode()) {
3269 if (NarrowLoad.getNode() != N0.getNode())
3270 CombineTo(N0.getNode(), NarrowLoad);
3271 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3275 // fold (aext (truncate x))
3276 if (N0.getOpcode() == ISD::TRUNCATE) {
3277 SDValue TruncOp = N0.getOperand(0);
3278 if (TruncOp.getValueType() == VT)
3279 return TruncOp; // x iff x size == zext size.
3280 if (TruncOp.getValueType().bitsGT(VT))
3281 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3282 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3285 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
3286 // if the trunc is not free.
3287 if (N0.getOpcode() == ISD::AND &&
3288 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3289 N0.getOperand(1).getOpcode() == ISD::Constant &&
3290 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3291 N0.getValueType())) {
3292 SDValue X = N0.getOperand(0).getOperand(0);
3293 if (X.getValueType().bitsLT(VT)) {
3294 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3295 } else if (X.getValueType().bitsGT(VT)) {
3296 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3298 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3299 Mask.zext(VT.getSizeInBits());
3300 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3301 X, DAG.getConstant(Mask, VT));
3304 // fold (aext (load x)) -> (aext (truncate (extload x)))
3305 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3306 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3307 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3308 bool DoXform = true;
3309 SmallVector<SDNode*, 4> SetCCs;
3310 if (!N0.hasOneUse())
3311 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
3313 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3314 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
3316 LN0->getBasePtr(), LN0->getSrcValue(),
3317 LN0->getSrcValueOffset(),
3319 LN0->isVolatile(), LN0->getAlignment());
3320 CombineTo(N, ExtLoad);
3321 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3322 N0.getValueType(), ExtLoad);
3323 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3325 // Extend SetCC uses if necessary.
3326 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3327 SDNode *SetCC = SetCCs[i];
3328 SmallVector<SDValue, 4> Ops;
3330 for (unsigned j = 0; j != 2; ++j) {
3331 SDValue SOp = SetCC->getOperand(j);
3333 Ops.push_back(ExtLoad);
3335 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
3336 N->getDebugLoc(), VT, SOp));
3339 Ops.push_back(SetCC->getOperand(2));
3340 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3341 SetCC->getValueType(0),
3342 &Ops[0], Ops.size()));
3345 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3349 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3350 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3351 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3352 if (N0.getOpcode() == ISD::LOAD &&
3353 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3355 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3356 MVT EVT = LN0->getMemoryVT();
3357 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
3358 VT, LN0->getChain(), LN0->getBasePtr(),
3360 LN0->getSrcValueOffset(), EVT,
3361 LN0->isVolatile(), LN0->getAlignment());
3362 CombineTo(N, ExtLoad);
3363 CombineTo(N0.getNode(),
3364 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3365 N0.getValueType(), ExtLoad),
3366 ExtLoad.getValue(1));
3367 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3370 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3371 if (N0.getOpcode() == ISD::SETCC) {
3373 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3374 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3375 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3383 /// GetDemandedBits - See if the specified operand can be simplified with the
3384 /// knowledge that only the bits specified by Mask are used. If so, return the
3385 /// simpler operand, otherwise return a null SDValue.
3386 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
3387 switch (V.getOpcode()) {
3391 // If the LHS or RHS don't contribute bits to the or, drop them.
3392 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3393 return V.getOperand(1);
3394 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3395 return V.getOperand(0);
3398 // Only look at single-use SRLs.
3399 if (!V.getNode()->hasOneUse())
3401 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3402 // See if we can recursively simplify the LHS.
3403 unsigned Amt = RHSC->getZExtValue();
3405 // Watch out for shift count overflow though.
3406 if (Amt >= Mask.getBitWidth()) break;
3407 APInt NewMask = Mask << Amt;
3408 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
3409 if (SimplifyLHS.getNode())
3410 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
3411 SimplifyLHS, V.getOperand(1));
3417 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3418 /// bits and then truncated to a narrower type and where N is a multiple
3419 /// of number of bits of the narrower type, transform it to a narrower load
3420 /// from address + N / num of bits of new type. If the result is to be
3421 /// extended, also fold the extension to form a extending load.
3422 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
3423 unsigned Opc = N->getOpcode();
3424 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3425 SDValue N0 = N->getOperand(0);
3426 MVT VT = N->getValueType(0);
3429 // This transformation isn't valid for vector loads.
3433 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3435 if (Opc == ISD::SIGN_EXTEND_INREG) {
3436 ExtType = ISD::SEXTLOAD;
3437 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3438 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))
3442 unsigned EVTBits = EVT.getSizeInBits();
3444 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3445 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3446 ShAmt = N01->getZExtValue();
3447 // Is the shift amount a multiple of size of VT?
3448 if ((ShAmt & (EVTBits-1)) == 0) {
3449 N0 = N0.getOperand(0);
3450 if (N0.getValueType().getSizeInBits() <= EVTBits)
3456 // Do not generate loads of non-round integer types since these can
3457 // be expensive (and would be wrong if the type is not byte sized).
3458 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() &&
3459 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
3460 // Do not change the width of a volatile load.
3461 !cast<LoadSDNode>(N0)->isVolatile()) {
3462 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3463 MVT PtrType = N0.getOperand(1).getValueType();
3465 // For big endian targets, we need to adjust the offset to the pointer to
3466 // load the correct bytes.
3467 if (TLI.isBigEndian()) {
3468 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
3469 unsigned EVTStoreBits = EVT.getStoreSizeInBits();
3470 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3473 uint64_t PtrOff = ShAmt / 8;
3474 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3475 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
3476 PtrType, LN0->getBasePtr(),
3477 DAG.getConstant(PtrOff, PtrType));
3478 AddToWorkList(NewPtr.getNode());
3480 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
3481 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
3482 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3483 LN0->isVolatile(), NewAlign)
3484 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
3485 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3486 EVT, LN0->isVolatile(), NewAlign);
3488 // Replace the old load's chain with the new load's chain.
3489 WorkListRemover DeadNodes(*this);
3490 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
3493 // Return the new loaded value.
3500 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3501 SDValue N0 = N->getOperand(0);
3502 SDValue N1 = N->getOperand(1);
3503 MVT VT = N->getValueType(0);
3504 MVT EVT = cast<VTSDNode>(N1)->getVT();
3505 unsigned VTBits = VT.getSizeInBits();
3506 unsigned EVTBits = EVT.getSizeInBits();
3508 // fold (sext_in_reg c1) -> c1
3509 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3510 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
3512 // If the input is already sign extended, just drop the extension.
3513 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
3516 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3517 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3518 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
3519 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3520 N0.getOperand(0), N1);
3523 // fold (sext_in_reg (sext x)) -> (sext x)
3524 // fold (sext_in_reg (aext x)) -> (sext x)
3525 // if x is small enough.
3526 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
3527 SDValue N00 = N0.getOperand(0);
3528 if (N00.getValueType().getSizeInBits() < EVTBits)
3529 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
3532 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3533 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
3534 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
3536 // fold operands of sext_in_reg based on knowledge that the top bits are not
3538 if (SimplifyDemandedBits(SDValue(N, 0)))
3539 return SDValue(N, 0);
3541 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3542 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3543 SDValue NarrowLoad = ReduceLoadWidth(N);
3544 if (NarrowLoad.getNode())
3547 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
3548 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
3549 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3550 if (N0.getOpcode() == ISD::SRL) {
3551 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3552 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) {
3553 // We can turn this into an SRA iff the input to the SRL is already sign
3555 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3556 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
3557 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
3558 N0.getOperand(0), N0.getOperand(1));
3562 // fold (sext_inreg (extload x)) -> (sextload x)
3563 if (ISD::isEXTLoad(N0.getNode()) &&
3564 ISD::isUNINDEXEDLoad(N0.getNode()) &&
3565 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3566 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3567 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3568 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3569 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3571 LN0->getBasePtr(), LN0->getSrcValue(),
3572 LN0->getSrcValueOffset(), EVT,
3573 LN0->isVolatile(), LN0->getAlignment());
3574 CombineTo(N, ExtLoad);
3575 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3576 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3578 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3579 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3581 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3582 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3583 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3584 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3585 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3587 LN0->getBasePtr(), LN0->getSrcValue(),
3588 LN0->getSrcValueOffset(), EVT,
3589 LN0->isVolatile(), LN0->getAlignment());
3590 CombineTo(N, ExtLoad);
3591 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3592 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3597 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
3598 SDValue N0 = N->getOperand(0);
3599 MVT VT = N->getValueType(0);
3602 if (N0.getValueType() == N->getValueType(0))
3604 // fold (truncate c1) -> c1
3605 if (isa<ConstantSDNode>(N0))
3606 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
3607 // fold (truncate (truncate x)) -> (truncate x)
3608 if (N0.getOpcode() == ISD::TRUNCATE)
3609 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3610 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3611 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3612 N0.getOpcode() == ISD::ANY_EXTEND) {
3613 if (N0.getOperand(0).getValueType().bitsLT(VT))
3614 // if the source is smaller than the dest, we still need an extend
3615 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
3617 else if (N0.getOperand(0).getValueType().bitsGT(VT))
3618 // if the source is larger than the dest, than we just need the truncate
3619 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3621 // if the source and dest are the same type, we can drop both the extend
3623 return N0.getOperand(0);
3626 // See if we can simplify the input to this truncate through knowledge that
3627 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3630 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3631 VT.getSizeInBits()));
3632 if (Shorter.getNode())
3633 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
3635 // fold (truncate (load x)) -> (smaller load x)
3636 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3637 return ReduceLoadWidth(N);
3640 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
3641 SDValue Elt = N->getOperand(i);
3642 if (Elt.getOpcode() != ISD::MERGE_VALUES)
3643 return Elt.getNode();
3644 return Elt.getOperand(Elt.getResNo()).getNode();
3647 /// CombineConsecutiveLoads - build_pair (load, load) -> load
3648 /// if load locations are consecutive.
3649 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
3650 assert(N->getOpcode() == ISD::BUILD_PAIR);
3652 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
3653 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
3654 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
3656 MVT LD1VT = LD1->getValueType(0);
3657 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3659 if (ISD::isNON_EXTLoad(LD2) &&
3661 // If both are volatile this would reduce the number of volatile loads.
3662 // If one is volatile it might be ok, but play conservative and bail out.
3663 !LD1->isVolatile() &&
3664 !LD2->isVolatile() &&
3665 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
3666 unsigned Align = LD1->getAlignment();
3667 unsigned NewAlign = TLI.getTargetData()->
3668 getABITypeAlignment(VT.getTypeForMVT());
3670 if (NewAlign <= Align &&
3671 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
3672 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
3673 LD1->getBasePtr(), LD1->getSrcValue(),
3674 LD1->getSrcValueOffset(), false, Align);
3680 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3681 SDValue N0 = N->getOperand(0);
3682 MVT VT = N->getValueType(0);
3684 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3685 // Only do this before legalize, since afterward the target may be depending
3686 // on the bitconvert.
3687 // First check to see if this is all constant.
3689 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
3691 bool isSimple = true;
3692 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3693 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3694 N0.getOperand(i).getOpcode() != ISD::Constant &&
3695 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3700 MVT DestEltVT = N->getValueType(0).getVectorElementType();
3701 assert(!DestEltVT.isVector() &&
3702 "Element type of vector ValueType must not be vector!");
3704 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
3707 // If the input is a constant, let getNode fold it.
3708 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3709 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
3710 if (Res.getNode() != N) return Res;
3713 // (conv (conv x, t1), t2) -> (conv x, t2)
3714 if (N0.getOpcode() == ISD::BIT_CONVERT)
3715 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
3718 // fold (conv (load x)) -> (load (conv*)x)
3719 // If the resultant load doesn't need a higher alignment than the original!
3720 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
3721 // Do not change the width of a volatile load.
3722 !cast<LoadSDNode>(N0)->isVolatile() &&
3723 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
3724 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3725 unsigned Align = TLI.getTargetData()->
3726 getABITypeAlignment(VT.getTypeForMVT());
3727 unsigned OrigAlign = LN0->getAlignment();
3729 if (Align <= OrigAlign) {
3730 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
3732 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3733 LN0->isVolatile(), OrigAlign);
3735 CombineTo(N0.getNode(),
3736 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3737 N0.getValueType(), Load),
3743 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
3744 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
3745 // This often reduces constant pool loads.
3746 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3747 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
3748 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
3750 AddToWorkList(NewConv.getNode());
3752 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3753 if (N0.getOpcode() == ISD::FNEG)
3754 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3755 NewConv, DAG.getConstant(SignBit, VT));
3756 assert(N0.getOpcode() == ISD::FABS);
3757 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3758 NewConv, DAG.getConstant(~SignBit, VT));
3761 // fold (bitconvert (fcopysign cst, x)) ->
3762 // (or (and (bitconvert x), sign), (and cst, (not sign)))
3763 // Note that we don't handle (copysign x, cst) because this can always be
3764 // folded to an fneg or fabs.
3765 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
3766 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
3767 VT.isInteger() && !VT.isVector()) {
3768 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
3769 MVT IntXVT = MVT::getIntegerVT(OrigXWidth);
3770 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) {
3771 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3772 IntXVT, N0.getOperand(1));
3773 AddToWorkList(X.getNode());
3775 // If X has a different width than the result/lhs, sext it or truncate it.
3776 unsigned VTWidth = VT.getSizeInBits();
3777 if (OrigXWidth < VTWidth) {
3778 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
3779 AddToWorkList(X.getNode());
3780 } else if (OrigXWidth > VTWidth) {
3781 // To get the sign bit in the right place, we have to shift it right
3782 // before truncating.
3783 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
3784 X.getValueType(), X,
3785 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
3786 AddToWorkList(X.getNode());
3787 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3788 AddToWorkList(X.getNode());
3791 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3792 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
3793 X, DAG.getConstant(SignBit, VT));
3794 AddToWorkList(X.getNode());
3796 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3797 VT, N0.getOperand(0));
3798 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
3799 Cst, DAG.getConstant(~SignBit, VT));
3800 AddToWorkList(Cst.getNode());
3802 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
3806 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
3807 if (N0.getOpcode() == ISD::BUILD_PAIR) {
3808 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
3809 if (CombineLD.getNode())
3816 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
3817 MVT VT = N->getValueType(0);
3818 return CombineConsecutiveLoads(N, VT);
3821 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3822 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3823 /// destination element value type.
3824 SDValue DAGCombiner::
3825 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
3826 MVT SrcEltVT = BV->getValueType(0).getVectorElementType();
3828 // If this is already the right type, we're done.
3829 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
3831 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
3832 unsigned DstBitSize = DstEltVT.getSizeInBits();
3834 // If this is a conversion of N elements of one type to N elements of another
3835 // type, convert each element. This handles FP<->INT cases.
3836 if (SrcBitSize == DstBitSize) {
3837 SmallVector<SDValue, 8> Ops;
3838 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3839 SDValue Op = BV->getOperand(i);
3840 // If the vector element type is not legal, the BUILD_VECTOR operands
3841 // are promoted and implicitly truncated. Make that explicit here.
3842 if (Op.getValueType() != SrcEltVT)
3843 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
3844 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
3846 AddToWorkList(Ops.back().getNode());
3848 MVT VT = MVT::getVectorVT(DstEltVT,
3849 BV->getValueType(0).getVectorNumElements());
3850 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3851 &Ops[0], Ops.size());
3854 // Otherwise, we're growing or shrinking the elements. To avoid having to
3855 // handle annoying details of growing/shrinking FP values, we convert them to
3857 if (SrcEltVT.isFloatingPoint()) {
3858 // Convert the input float vector to a int vector where the elements are the
3860 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3861 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
3862 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
3866 // Now we know the input is an integer vector. If the output is a FP type,
3867 // convert to integer first, then to FP of the right size.
3868 if (DstEltVT.isFloatingPoint()) {
3869 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3870 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
3871 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
3873 // Next, convert to FP elements of the same size.
3874 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3877 // Okay, we know the src/dst types are both integers of differing types.
3878 // Handling growing first.
3879 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
3880 if (SrcBitSize < DstBitSize) {
3881 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3883 SmallVector<SDValue, 8> Ops;
3884 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3885 i += NumInputsPerOutput) {
3886 bool isLE = TLI.isLittleEndian();
3887 APInt NewBits = APInt(DstBitSize, 0);
3888 bool EltIsUndef = true;
3889 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3890 // Shift the previously computed bits over.
3891 NewBits <<= SrcBitSize;
3892 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3893 if (Op.getOpcode() == ISD::UNDEF) continue;
3896 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).
3897 zextOrTrunc(SrcBitSize).zext(DstBitSize));
3901 Ops.push_back(DAG.getUNDEF(DstEltVT));
3903 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3906 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size());
3907 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3908 &Ops[0], Ops.size());
3911 // Finally, this must be the case where we are shrinking elements: each input
3912 // turns into multiple outputs.
3913 bool isS2V = ISD::isScalarToVector(BV);
3914 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3915 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
3916 SmallVector<SDValue, 8> Ops;
3918 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3919 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3920 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3921 Ops.push_back(DAG.getUNDEF(DstEltVT));
3925 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))->
3926 getAPIntValue()).zextOrTrunc(SrcBitSize);
3928 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3929 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
3930 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3931 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
3932 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
3933 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
3935 OpVal = OpVal.lshr(DstBitSize);
3938 // For big endian targets, swap the order of the pieces of each element.
3939 if (TLI.isBigEndian())
3940 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3943 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3944 &Ops[0], Ops.size());
3947 SDValue DAGCombiner::visitFADD(SDNode *N) {
3948 SDValue N0 = N->getOperand(0);
3949 SDValue N1 = N->getOperand(1);
3950 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3951 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3952 MVT VT = N->getValueType(0);
3955 if (VT.isVector()) {
3956 SDValue FoldedVOp = SimplifyVBinOp(N);
3957 if (FoldedVOp.getNode()) return FoldedVOp;
3960 // fold (fadd c1, c2) -> (fadd c1, c2)
3961 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3962 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
3963 // canonicalize constant to RHS
3964 if (N0CFP && !N1CFP)
3965 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
3966 // fold (fadd A, 0) -> A
3967 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
3969 // fold (fadd A, (fneg B)) -> (fsub A, B)
3970 if (isNegatibleForFree(N1, LegalOperations) == 2)
3971 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
3972 GetNegatedExpression(N1, DAG, LegalOperations));
3973 // fold (fadd (fneg A), B) -> (fsub B, A)
3974 if (isNegatibleForFree(N0, LegalOperations) == 2)
3975 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
3976 GetNegatedExpression(N0, DAG, LegalOperations));
3978 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3979 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3980 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3981 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
3982 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
3983 N0.getOperand(1), N1));
3988 SDValue DAGCombiner::visitFSUB(SDNode *N) {
3989 SDValue N0 = N->getOperand(0);
3990 SDValue N1 = N->getOperand(1);
3991 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3992 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3993 MVT VT = N->getValueType(0);
3996 if (VT.isVector()) {
3997 SDValue FoldedVOp = SimplifyVBinOp(N);
3998 if (FoldedVOp.getNode()) return FoldedVOp;
4001 // fold (fsub c1, c2) -> c1-c2
4002 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4003 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
4004 // fold (fsub A, 0) -> A
4005 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4007 // fold (fsub 0, B) -> -B
4008 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
4009 if (isNegatibleForFree(N1, LegalOperations))
4010 return GetNegatedExpression(N1, DAG, LegalOperations);
4011 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4012 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
4014 // fold (fsub A, (fneg B)) -> (fadd A, B)
4015 if (isNegatibleForFree(N1, LegalOperations))
4016 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
4017 GetNegatedExpression(N1, DAG, LegalOperations));
4022 SDValue DAGCombiner::visitFMUL(SDNode *N) {
4023 SDValue N0 = N->getOperand(0);
4024 SDValue N1 = N->getOperand(1);
4025 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4026 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4027 MVT VT = N->getValueType(0);
4030 if (VT.isVector()) {
4031 SDValue FoldedVOp = SimplifyVBinOp(N);
4032 if (FoldedVOp.getNode()) return FoldedVOp;
4035 // fold (fmul c1, c2) -> c1*c2
4036 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4037 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4038 // canonicalize constant to RHS
4039 if (N0CFP && !N1CFP)
4040 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4041 // fold (fmul A, 0) -> 0
4042 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4044 // fold (fmul A, 0) -> 0, vector edition.
4045 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
4047 // fold (fmul X, 2.0) -> (fadd X, X)
4048 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4049 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4050 // fold (fmul X, (fneg 1.0)) -> (fneg X)
4051 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4052 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4053 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4055 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4056 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4057 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4058 // Both can be negated for free, check to see if at least one is cheaper
4060 if (LHSNeg == 2 || RHSNeg == 2)
4061 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4062 GetNegatedExpression(N0, DAG, LegalOperations),
4063 GetNegatedExpression(N1, DAG, LegalOperations));
4067 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4068 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4069 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4070 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4071 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4072 N0.getOperand(1), N1));
4077 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4078 SDValue N0 = N->getOperand(0);
4079 SDValue N1 = N->getOperand(1);
4080 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4081 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4082 MVT VT = N->getValueType(0);
4085 if (VT.isVector()) {
4086 SDValue FoldedVOp = SimplifyVBinOp(N);
4087 if (FoldedVOp.getNode()) return FoldedVOp;
4090 // fold (fdiv c1, c2) -> c1/c2
4091 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4092 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4095 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4096 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4097 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4098 // Both can be negated for free, check to see if at least one is cheaper
4100 if (LHSNeg == 2 || RHSNeg == 2)
4101 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4102 GetNegatedExpression(N0, DAG, LegalOperations),
4103 GetNegatedExpression(N1, DAG, LegalOperations));
4110 SDValue DAGCombiner::visitFREM(SDNode *N) {
4111 SDValue N0 = N->getOperand(0);
4112 SDValue N1 = N->getOperand(1);
4113 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4114 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4115 MVT VT = N->getValueType(0);
4117 // fold (frem c1, c2) -> fmod(c1,c2)
4118 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4119 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4124 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4125 SDValue N0 = N->getOperand(0);
4126 SDValue N1 = N->getOperand(1);
4127 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4128 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4129 MVT VT = N->getValueType(0);
4131 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4132 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4135 const APFloat& V = N1CFP->getValueAPF();
4136 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4137 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4138 if (!V.isNegative()) {
4139 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4140 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4142 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4143 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4144 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4148 // copysign(fabs(x), y) -> copysign(x, y)
4149 // copysign(fneg(x), y) -> copysign(x, y)
4150 // copysign(copysign(x,z), y) -> copysign(x, y)
4151 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4152 N0.getOpcode() == ISD::FCOPYSIGN)
4153 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4154 N0.getOperand(0), N1);
4156 // copysign(x, abs(y)) -> abs(x)
4157 if (N1.getOpcode() == ISD::FABS)
4158 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4160 // copysign(x, copysign(y,z)) -> copysign(x, z)
4161 if (N1.getOpcode() == ISD::FCOPYSIGN)
4162 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4163 N0, N1.getOperand(1));
4165 // copysign(x, fp_extend(y)) -> copysign(x, y)
4166 // copysign(x, fp_round(y)) -> copysign(x, y)
4167 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4168 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4169 N0, N1.getOperand(0));
4174 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4175 SDValue N0 = N->getOperand(0);
4176 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4177 MVT VT = N->getValueType(0);
4178 MVT OpVT = N0.getValueType();
4180 // fold (sint_to_fp c1) -> c1fp
4181 if (N0C && OpVT != MVT::ppcf128)
4182 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4184 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4185 // but UINT_TO_FP is legal on this target, try to convert.
4186 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4187 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4188 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4189 if (DAG.SignBitIsZero(N0))
4190 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4196 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4197 SDValue N0 = N->getOperand(0);
4198 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4199 MVT VT = N->getValueType(0);
4200 MVT OpVT = N0.getValueType();
4202 // fold (uint_to_fp c1) -> c1fp
4203 if (N0C && OpVT != MVT::ppcf128)
4204 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4206 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
4207 // but SINT_TO_FP is legal on this target, try to convert.
4208 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4209 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4210 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4211 if (DAG.SignBitIsZero(N0))
4212 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4218 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4219 SDValue N0 = N->getOperand(0);
4220 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4221 MVT VT = N->getValueType(0);
4223 // fold (fp_to_sint c1fp) -> c1
4225 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
4230 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4231 SDValue N0 = N->getOperand(0);
4232 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4233 MVT VT = N->getValueType(0);
4235 // fold (fp_to_uint c1fp) -> c1
4236 if (N0CFP && VT != MVT::ppcf128)
4237 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
4242 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4243 SDValue N0 = N->getOperand(0);
4244 SDValue N1 = N->getOperand(1);
4245 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4246 MVT VT = N->getValueType(0);
4248 // fold (fp_round c1fp) -> c1fp
4249 if (N0CFP && N0.getValueType() != MVT::ppcf128)
4250 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
4252 // fold (fp_round (fp_extend x)) -> x
4253 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4254 return N0.getOperand(0);
4256 // fold (fp_round (fp_round x)) -> (fp_round x)
4257 if (N0.getOpcode() == ISD::FP_ROUND) {
4258 // This is a value preserving truncation if both round's are.
4259 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4260 N0.getNode()->getConstantOperandVal(1) == 1;
4261 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
4262 DAG.getIntPtrConstant(IsTrunc));
4265 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4266 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4267 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
4268 N0.getOperand(0), N1);
4269 AddToWorkList(Tmp.getNode());
4270 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4271 Tmp, N0.getOperand(1));
4277 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4278 SDValue N0 = N->getOperand(0);
4279 MVT VT = N->getValueType(0);
4280 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4281 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4283 // fold (fp_round_inreg c1fp) -> c1fp
4284 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) {
4285 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4286 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
4292 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4293 SDValue N0 = N->getOperand(0);
4294 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4295 MVT VT = N->getValueType(0);
4297 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4298 if (N->hasOneUse() &&
4299 N->use_begin()->getOpcode() == ISD::FP_ROUND)
4302 // fold (fp_extend c1fp) -> c1fp
4303 if (N0CFP && VT != MVT::ppcf128)
4304 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
4306 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4308 if (N0.getOpcode() == ISD::FP_ROUND
4309 && N0.getNode()->getConstantOperandVal(1) == 1) {
4310 SDValue In = N0.getOperand(0);
4311 if (In.getValueType() == VT) return In;
4312 if (VT.bitsLT(In.getValueType()))
4313 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
4314 In, N0.getOperand(1));
4315 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
4318 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
4319 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
4320 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4321 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4322 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4323 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4325 LN0->getBasePtr(), LN0->getSrcValue(),
4326 LN0->getSrcValueOffset(),
4328 LN0->isVolatile(), LN0->getAlignment());
4329 CombineTo(N, ExtLoad);
4330 CombineTo(N0.getNode(),
4331 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
4332 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
4333 ExtLoad.getValue(1));
4334 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4340 SDValue DAGCombiner::visitFNEG(SDNode *N) {
4341 SDValue N0 = N->getOperand(0);
4343 if (isNegatibleForFree(N0, LegalOperations))
4344 return GetNegatedExpression(N0, DAG, LegalOperations);
4346 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
4347 // constant pool values.
4348 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4349 N0.getOperand(0).getValueType().isInteger() &&
4350 !N0.getOperand(0).getValueType().isVector()) {
4351 SDValue Int = N0.getOperand(0);
4352 MVT IntVT = Int.getValueType();
4353 if (IntVT.isInteger() && !IntVT.isVector()) {
4354 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
4355 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4356 AddToWorkList(Int.getNode());
4357 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4358 N->getValueType(0), Int);
4365 SDValue DAGCombiner::visitFABS(SDNode *N) {
4366 SDValue N0 = N->getOperand(0);
4367 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4368 MVT VT = N->getValueType(0);
4370 // fold (fabs c1) -> fabs(c1)
4371 if (N0CFP && VT != MVT::ppcf128)
4372 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4373 // fold (fabs (fabs x)) -> (fabs x)
4374 if (N0.getOpcode() == ISD::FABS)
4375 return N->getOperand(0);
4376 // fold (fabs (fneg x)) -> (fabs x)
4377 // fold (fabs (fcopysign x, y)) -> (fabs x)
4378 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
4379 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
4381 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
4382 // constant pool values.
4383 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4384 N0.getOperand(0).getValueType().isInteger() &&
4385 !N0.getOperand(0).getValueType().isVector()) {
4386 SDValue Int = N0.getOperand(0);
4387 MVT IntVT = Int.getValueType();
4388 if (IntVT.isInteger() && !IntVT.isVector()) {
4389 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
4390 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4391 AddToWorkList(Int.getNode());
4392 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4393 N->getValueType(0), Int);
4400 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
4401 SDValue Chain = N->getOperand(0);
4402 SDValue N1 = N->getOperand(1);
4403 SDValue N2 = N->getOperand(2);
4404 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4406 // never taken branch, fold to chain
4407 if (N1C && N1C->isNullValue())
4409 // unconditional branch
4410 if (N1C && N1C->getAPIntValue() == 1)
4411 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2);
4412 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
4414 if (N1.getOpcode() == ISD::SETCC &&
4415 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
4416 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4417 Chain, N1.getOperand(2),
4418 N1.getOperand(0), N1.getOperand(1), N2);
4421 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) {
4422 // Match this pattern so that we can generate simpler code:
4425 // %b = and i32 %a, 2
4426 // %c = srl i32 %b, 1
4427 // brcond i32 %c ...
4433 // %c = setcc eq %b, 0
4436 // This applies only when the AND constant value has one bit set and the
4437 // SRL constant is equal to the log2 of the AND constant. The back-end is
4438 // smart enough to convert the result into a TEST/JMP sequence.
4439 SDValue Op0 = N1.getOperand(0);
4440 SDValue Op1 = N1.getOperand(1);
4442 if (Op0.getOpcode() == ISD::AND &&
4444 Op1.getOpcode() == ISD::Constant) {
4445 SDValue AndOp0 = Op0.getOperand(0);
4446 SDValue AndOp1 = Op0.getOperand(1);
4448 if (AndOp1.getOpcode() == ISD::Constant) {
4449 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
4451 if (AndConst.isPowerOf2() &&
4452 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
4454 DAG.getSetCC(N->getDebugLoc(),
4455 TLI.getSetCCResultType(Op0.getValueType()),
4456 Op0, DAG.getConstant(0, Op0.getValueType()),
4459 // Replace the uses of SRL with SETCC
4460 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
4461 removeFromWorkList(N1.getNode());
4462 DAG.DeleteNode(N1.getNode());
4463 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4464 MVT::Other, Chain, SetCC, N2);
4473 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
4475 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
4476 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
4477 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
4479 // Use SimplifySetCC to simplify SETCC's.
4480 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
4481 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
4483 if (Simp.getNode()) AddToWorkList(Simp.getNode());
4485 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
4487 // fold br_cc true, dest -> br dest (unconditional branch)
4488 if (SCCC && !SCCC->isNullValue())
4489 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other,
4490 N->getOperand(0), N->getOperand(4));
4491 // fold br_cc false, dest -> unconditional fall through
4492 if (SCCC && SCCC->isNullValue())
4493 return N->getOperand(0);
4495 // fold to a simpler setcc
4496 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
4497 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4498 N->getOperand(0), Simp.getOperand(2),
4499 Simp.getOperand(0), Simp.getOperand(1),
4505 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
4506 /// pre-indexed load / store when the base pointer is an add or subtract
4507 /// and it has other uses besides the load / store. After the
4508 /// transformation, the new indexed load / store has effectively folded
4509 /// the add / subtract in and all of its other uses are redirected to the
4510 /// new load / store.
4511 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
4512 if (!LegalOperations)
4518 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4519 if (LD->isIndexed())
4521 VT = LD->getMemoryVT();
4522 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
4523 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
4525 Ptr = LD->getBasePtr();
4526 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4527 if (ST->isIndexed())
4529 VT = ST->getMemoryVT();
4530 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
4531 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
4533 Ptr = ST->getBasePtr();
4539 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
4540 // out. There is no reason to make this a preinc/predec.
4541 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
4542 Ptr.getNode()->hasOneUse())
4545 // Ask the target to do addressing mode selection.
4548 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4549 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
4551 // Don't create a indexed load / store with zero offset.
4552 if (isa<ConstantSDNode>(Offset) &&
4553 cast<ConstantSDNode>(Offset)->isNullValue())
4556 // Try turning it into a pre-indexed load / store except when:
4557 // 1) The new base ptr is a frame index.
4558 // 2) If N is a store and the new base ptr is either the same as or is a
4559 // predecessor of the value being stored.
4560 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
4561 // that would create a cycle.
4562 // 4) All uses are load / store ops that use it as old base ptr.
4564 // Check #1. Preinc'ing a frame index would require copying the stack pointer
4565 // (plus the implicit offset) to a register to preinc anyway.
4566 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
4571 SDValue Val = cast<StoreSDNode>(N)->getValue();
4572 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
4576 // Now check for #3 and #4.
4577 bool RealUse = false;
4578 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4579 E = Ptr.getNode()->use_end(); I != E; ++I) {
4583 if (Use->isPredecessorOf(N))
4586 if (!((Use->getOpcode() == ISD::LOAD &&
4587 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
4588 (Use->getOpcode() == ISD::STORE &&
4589 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
4598 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4599 BasePtr, Offset, AM);
4601 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4602 BasePtr, Offset, AM);
4605 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
4606 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4608 WorkListRemover DeadNodes(*this);
4610 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4612 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4615 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4619 // Finally, since the node is now dead, remove it from the graph.
4622 // Replace the uses of Ptr with uses of the updated base value.
4623 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
4625 removeFromWorkList(Ptr.getNode());
4626 DAG.DeleteNode(Ptr.getNode());
4631 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
4632 /// add / sub of the base pointer node into a post-indexed load / store.
4633 /// The transformation folded the add / subtract into the new indexed
4634 /// load / store effectively and all of its uses are redirected to the
4635 /// new load / store.
4636 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
4637 if (!LegalOperations)
4643 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4644 if (LD->isIndexed())
4646 VT = LD->getMemoryVT();
4647 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
4648 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
4650 Ptr = LD->getBasePtr();
4651 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4652 if (ST->isIndexed())
4654 VT = ST->getMemoryVT();
4655 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
4656 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
4658 Ptr = ST->getBasePtr();
4664 if (Ptr.getNode()->hasOneUse())
4667 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4668 E = Ptr.getNode()->use_end(); I != E; ++I) {
4671 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
4676 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4677 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
4679 std::swap(BasePtr, Offset);
4682 // Don't create a indexed load / store with zero offset.
4683 if (isa<ConstantSDNode>(Offset) &&
4684 cast<ConstantSDNode>(Offset)->isNullValue())
4687 // Try turning it into a post-indexed load / store except when
4688 // 1) All uses are load / store ops that use it as base ptr.
4689 // 2) Op must be independent of N, i.e. Op is neither a predecessor
4690 // nor a successor of N. Otherwise, if Op is folded that would
4693 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
4697 bool TryNext = false;
4698 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
4699 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
4701 if (Use == Ptr.getNode())
4704 // If all the uses are load / store addresses, then don't do the
4706 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
4707 bool RealUse = false;
4708 for (SDNode::use_iterator III = Use->use_begin(),
4709 EEE = Use->use_end(); III != EEE; ++III) {
4710 SDNode *UseUse = *III;
4711 if (!((UseUse->getOpcode() == ISD::LOAD &&
4712 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
4713 (UseUse->getOpcode() == ISD::STORE &&
4714 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
4729 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
4730 SDValue Result = isLoad
4731 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4732 BasePtr, Offset, AM)
4733 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4734 BasePtr, Offset, AM);
4737 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4738 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4740 WorkListRemover DeadNodes(*this);
4742 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4744 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4747 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4751 // Finally, since the node is now dead, remove it from the graph.
4754 // Replace the uses of Use with uses of the updated base value.
4755 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
4756 Result.getValue(isLoad ? 1 : 0),
4758 removeFromWorkList(Op);
4768 /// InferAlignment - If we can infer some alignment information from this
4769 /// pointer, return it.
4770 static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) {
4771 // If this is a direct reference to a stack slot, use information about the
4772 // stack slot's alignment.
4773 int FrameIdx = 1 << 31;
4774 int64_t FrameOffset = 0;
4775 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) {
4776 FrameIdx = FI->getIndex();
4777 } else if (Ptr.getOpcode() == ISD::ADD &&
4778 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4779 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4780 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4781 FrameOffset = Ptr.getConstantOperandVal(1);
4784 if (FrameIdx != (1 << 31)) {
4785 // FIXME: Handle FI+CST.
4786 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
4787 if (MFI.isFixedObjectIndex(FrameIdx)) {
4788 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset;
4790 // The alignment of the frame index can be determined from its offset from
4791 // the incoming frame position. If the frame object is at offset 32 and
4792 // the stack is guaranteed to be 16-byte aligned, then we know that the
4793 // object is 16-byte aligned.
4794 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment();
4795 unsigned Align = MinAlign(ObjectOffset, StackAlign);
4797 // Finally, the frame object itself may have a known alignment. Factor
4798 // the alignment + offset into a new alignment. For example, if we know
4799 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a
4800 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte
4801 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc.
4802 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
4804 return std::max(Align, FIInfoAlign);
4811 SDValue DAGCombiner::visitLOAD(SDNode *N) {
4812 LoadSDNode *LD = cast<LoadSDNode>(N);
4813 SDValue Chain = LD->getChain();
4814 SDValue Ptr = LD->getBasePtr();
4816 // Try to infer better alignment information than the load already has.
4817 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
4818 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4819 if (Align > LD->getAlignment())
4820 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
4821 LD->getValueType(0),
4822 Chain, Ptr, LD->getSrcValue(),
4823 LD->getSrcValueOffset(), LD->getMemoryVT(),
4824 LD->isVolatile(), Align);
4828 // If load is not volatile and there are no uses of the loaded value (and
4829 // the updated indexed value in case of indexed loads), change uses of the
4830 // chain value into uses of the chain input (i.e. delete the dead load).
4831 if (!LD->isVolatile()) {
4832 if (N->getValueType(1) == MVT::Other) {
4834 if (N->hasNUsesOfValue(0, 0)) {
4835 // It's not safe to use the two value CombineTo variant here. e.g.
4836 // v1, chain2 = load chain1, loc
4837 // v2, chain3 = load chain2, loc
4839 // Now we replace use of chain2 with chain1. This makes the second load
4840 // isomorphic to the one we are deleting, and thus makes this load live.
4841 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4842 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG));
4844 WorkListRemover DeadNodes(*this);
4845 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
4847 if (N->use_empty()) {
4848 removeFromWorkList(N);
4852 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4856 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4857 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4858 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
4859 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4860 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
4861 DOUT << " and 2 other values\n";
4862 WorkListRemover DeadNodes(*this);
4863 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
4864 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
4865 DAG.getUNDEF(N->getValueType(1)),
4867 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
4868 removeFromWorkList(N);
4870 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4875 // If this load is directly stored, replace the load value with the stored
4877 // TODO: Handle store large -> read small portion.
4878 // TODO: Handle TRUNCSTORE/LOADEXT
4879 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
4880 !LD->isVolatile()) {
4881 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
4882 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4883 if (PrevST->getBasePtr() == Ptr &&
4884 PrevST->getValue().getValueType() == N->getValueType(0))
4885 return CombineTo(N, Chain.getOperand(1), Chain);
4890 // Walk up chain skipping non-aliasing memory nodes.
4891 SDValue BetterChain = FindBetterChain(N, Chain);
4893 // If there is a better chain.
4894 if (Chain != BetterChain) {
4897 // Replace the chain to void dependency.
4898 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4899 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
4901 LD->getSrcValue(), LD->getSrcValueOffset(),
4902 LD->isVolatile(), LD->getAlignment());
4904 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
4905 LD->getValueType(0),
4906 BetterChain, Ptr, LD->getSrcValue(),
4907 LD->getSrcValueOffset(),
4910 LD->getAlignment());
4913 // Create token factor to keep old chain connected.
4914 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
4915 MVT::Other, Chain, ReplLoad.getValue(1));
4917 // Replace uses with load result and token factor. Don't add users
4919 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4923 // Try transforming N to an indexed load.
4924 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4925 return SDValue(N, 0);
4931 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
4932 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
4933 /// of the loaded bits, try narrowing the load and store if it would end up
4934 /// being a win for performance or code size.
4935 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
4936 StoreSDNode *ST = cast<StoreSDNode>(N);
4937 if (ST->isVolatile())
4940 SDValue Chain = ST->getChain();
4941 SDValue Value = ST->getValue();
4942 SDValue Ptr = ST->getBasePtr();
4943 MVT VT = Value.getValueType();
4945 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
4948 unsigned Opc = Value.getOpcode();
4949 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
4950 Value.getOperand(1).getOpcode() != ISD::Constant)
4953 SDValue N0 = Value.getOperand(0);
4954 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) {
4955 LoadSDNode *LD = cast<LoadSDNode>(N0);
4956 if (LD->getBasePtr() != Ptr)
4959 // Find the type to narrow it the load / op / store to.
4960 SDValue N1 = Value.getOperand(1);
4961 unsigned BitWidth = N1.getValueSizeInBits();
4962 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
4963 if (Opc == ISD::AND)
4964 Imm ^= APInt::getAllOnesValue(BitWidth);
4965 if (Imm == 0 || Imm.isAllOnesValue())
4967 unsigned ShAmt = Imm.countTrailingZeros();
4968 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
4969 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
4970 MVT NewVT = MVT::getIntegerVT(NewBW);
4971 while (NewBW < BitWidth &&
4972 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
4973 TLI.isNarrowingProfitable(VT, NewVT))) {
4974 NewBW = NextPowerOf2(NewBW);
4975 NewVT = MVT::getIntegerVT(NewBW);
4977 if (NewBW >= BitWidth)
4980 // If the lsb changed does not start at the type bitwidth boundary,
4981 // start at the previous one.
4983 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
4984 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
4985 if ((Imm & Mask) == Imm) {
4986 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
4987 if (Opc == ISD::AND)
4988 NewImm ^= APInt::getAllOnesValue(NewBW);
4989 uint64_t PtrOff = ShAmt / 8;
4990 // For big endian targets, we need to adjust the offset to the pointer to
4991 // load the correct bytes.
4992 if (TLI.isBigEndian())
4993 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
4995 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
4997 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT()))
5000 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
5001 Ptr.getValueType(), Ptr,
5002 DAG.getConstant(PtrOff, Ptr.getValueType()));
5003 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
5004 LD->getChain(), NewPtr,
5005 LD->getSrcValue(), LD->getSrcValueOffset(),
5006 LD->isVolatile(), NewAlign);
5007 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
5008 DAG.getConstant(NewImm, NewVT));
5009 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
5011 ST->getSrcValue(), ST->getSrcValueOffset(),
5014 AddToWorkList(NewPtr.getNode());
5015 AddToWorkList(NewLD.getNode());
5016 AddToWorkList(NewVal.getNode());
5017 WorkListRemover DeadNodes(*this);
5018 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
5028 SDValue DAGCombiner::visitSTORE(SDNode *N) {
5029 StoreSDNode *ST = cast<StoreSDNode>(N);
5030 SDValue Chain = ST->getChain();
5031 SDValue Value = ST->getValue();
5032 SDValue Ptr = ST->getBasePtr();
5034 // Try to infer better alignment information than the store already has.
5035 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
5036 if (unsigned Align = InferAlignment(Ptr, DAG)) {
5037 if (Align > ST->getAlignment())
5038 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
5039 Ptr, ST->getSrcValue(),
5040 ST->getSrcValueOffset(), ST->getMemoryVT(),
5041 ST->isVolatile(), Align);
5045 // If this is a store of a bit convert, store the input value if the
5046 // resultant store does not need a higher alignment than the original.
5047 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
5048 ST->isUnindexed()) {
5049 unsigned OrigAlign = ST->getAlignment();
5050 MVT SVT = Value.getOperand(0).getValueType();
5051 unsigned Align = TLI.getTargetData()->
5052 getABITypeAlignment(SVT.getTypeForMVT());
5053 if (Align <= OrigAlign &&
5054 ((!LegalOperations && !ST->isVolatile()) ||
5055 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
5056 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5057 Ptr, ST->getSrcValue(),
5058 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign);
5061 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
5062 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
5063 // NOTE: If the original store is volatile, this transform must not increase
5064 // the number of stores. For example, on x86-32 an f64 can be stored in one
5065 // processor operation but an i64 (which is not legal) requires two. So the
5066 // transform should not be done in this case.
5067 if (Value.getOpcode() != ISD::TargetConstantFP) {
5069 switch (CFP->getValueType(0).getSimpleVT()) {
5070 default: llvm_unreachable("Unknown FP type");
5071 case MVT::f80: // We don't do this for these yet.
5076 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
5077 !ST->isVolatile()) ||
5078 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5079 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
5080 bitcastToAPInt().getZExtValue(), MVT::i32);
5081 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5082 Ptr, ST->getSrcValue(),
5083 ST->getSrcValueOffset(), ST->isVolatile(),
5084 ST->getAlignment());
5088 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
5089 !ST->isVolatile()) ||
5090 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
5091 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
5092 getZExtValue(), MVT::i64);
5093 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5094 Ptr, ST->getSrcValue(),
5095 ST->getSrcValueOffset(), ST->isVolatile(),
5096 ST->getAlignment());
5097 } else if (!ST->isVolatile() &&
5098 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5099 // Many FP stores are not made apparent until after legalize, e.g. for
5100 // argument passing. Since this is so common, custom legalize the
5101 // 64-bit integer store into two 32-bit stores.
5102 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
5103 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
5104 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
5105 if (TLI.isBigEndian()) std::swap(Lo, Hi);
5107 int SVOffset = ST->getSrcValueOffset();
5108 unsigned Alignment = ST->getAlignment();
5109 bool isVolatile = ST->isVolatile();
5111 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
5112 Ptr, ST->getSrcValue(),
5113 ST->getSrcValueOffset(),
5114 isVolatile, ST->getAlignment());
5115 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
5116 DAG.getConstant(4, Ptr.getValueType()));
5118 Alignment = MinAlign(Alignment, 4U);
5119 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
5120 Ptr, ST->getSrcValue(),
5121 SVOffset, isVolatile, Alignment);
5122 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
5132 // Walk up chain skipping non-aliasing memory nodes.
5133 SDValue BetterChain = FindBetterChain(N, Chain);
5135 // If there is a better chain.
5136 if (Chain != BetterChain) {
5137 // Replace the chain to avoid dependency.
5139 if (ST->isTruncatingStore()) {
5140 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5141 ST->getSrcValue(),ST->getSrcValueOffset(),
5143 ST->isVolatile(), ST->getAlignment());
5145 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5146 ST->getSrcValue(), ST->getSrcValueOffset(),
5147 ST->isVolatile(), ST->getAlignment());
5150 // Create token to keep both nodes around.
5151 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5152 MVT::Other, Chain, ReplStore);
5154 // Don't add users to work list.
5155 return CombineTo(N, Token, false);
5159 // Try transforming N to an indexed store.
5160 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5161 return SDValue(N, 0);
5163 // FIXME: is there such a thing as a truncating indexed store?
5164 if (ST->isTruncatingStore() && ST->isUnindexed() &&
5165 Value.getValueType().isInteger()) {
5166 // See if we can simplify the input to this truncstore with knowledge that
5167 // only the low bits are being used. For example:
5168 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
5170 GetDemandedBits(Value,
5171 APInt::getLowBitsSet(Value.getValueSizeInBits(),
5172 ST->getMemoryVT().getSizeInBits()));
5173 AddToWorkList(Value.getNode());
5174 if (Shorter.getNode())
5175 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
5176 Ptr, ST->getSrcValue(),
5177 ST->getSrcValueOffset(), ST->getMemoryVT(),
5178 ST->isVolatile(), ST->getAlignment());
5180 // Otherwise, see if we can simplify the operation with
5181 // SimplifyDemandedBits, which only works if the value has a single use.
5182 if (SimplifyDemandedBits(Value,
5183 APInt::getLowBitsSet(
5184 Value.getValueSizeInBits(),
5185 ST->getMemoryVT().getSizeInBits())))
5186 return SDValue(N, 0);
5189 // If this is a load followed by a store to the same location, then the store
5191 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
5192 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
5193 ST->isUnindexed() && !ST->isVolatile() &&
5194 // There can't be any side effects between the load and store, such as
5196 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
5197 // The store is dead, remove it.
5202 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
5203 // truncating store. We can do this even if this is already a truncstore.
5204 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
5205 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
5206 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
5207 ST->getMemoryVT())) {
5208 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5209 Ptr, ST->getSrcValue(),
5210 ST->getSrcValueOffset(), ST->getMemoryVT(),
5211 ST->isVolatile(), ST->getAlignment());
5214 return ReduceLoadOpStoreWidth(N);
5217 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
5218 SDValue InVec = N->getOperand(0);
5219 SDValue InVal = N->getOperand(1);
5220 SDValue EltNo = N->getOperand(2);
5222 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
5223 // vector with the inserted element.
5224 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
5225 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5226 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
5227 InVec.getNode()->op_end());
5228 if (Elt < Ops.size())
5230 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5231 InVec.getValueType(), &Ops[0], Ops.size());
5233 // If the invec is an UNDEF and if EltNo is a constant, create a new
5234 // BUILD_VECTOR with undef elements and the inserted element.
5235 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
5236 isa<ConstantSDNode>(EltNo)) {
5237 MVT VT = InVec.getValueType();
5238 MVT EVT = VT.getVectorElementType();
5239 unsigned NElts = VT.getVectorNumElements();
5240 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT));
5242 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5243 if (Elt < Ops.size())
5245 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5246 InVec.getValueType(), &Ops[0], Ops.size());
5251 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
5252 // (vextract (scalar_to_vector val, 0) -> val
5253 SDValue InVec = N->getOperand(0);
5255 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5256 // If the operand is wider than the vector element type then it is implicitly
5257 // truncated. Make that explicit here.
5258 MVT EltVT = InVec.getValueType().getVectorElementType();
5259 SDValue InOp = InVec.getOperand(0);
5260 if (InOp.getValueType() != EltVT)
5261 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp);
5265 // Perform only after legalization to ensure build_vector / vector_shuffle
5266 // optimizations have already been done.
5267 if (!LegalOperations) return SDValue();
5269 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
5270 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
5271 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
5272 SDValue EltNo = N->getOperand(1);
5274 if (isa<ConstantSDNode>(EltNo)) {
5275 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5276 bool NewLoad = false;
5277 bool BCNumEltsChanged = false;
5278 MVT VT = InVec.getValueType();
5279 MVT EVT = VT.getVectorElementType();
5282 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
5283 MVT BCVT = InVec.getOperand(0).getValueType();
5284 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
5286 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
5287 BCNumEltsChanged = true;
5288 InVec = InVec.getOperand(0);
5289 EVT = BCVT.getVectorElementType();
5293 LoadSDNode *LN0 = NULL;
5294 const ShuffleVectorSDNode *SVN = NULL;
5295 if (ISD::isNormalLoad(InVec.getNode())) {
5296 LN0 = cast<LoadSDNode>(InVec);
5297 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5298 InVec.getOperand(0).getValueType() == EVT &&
5299 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
5300 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
5301 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
5302 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
5304 // (load $addr+1*size)
5306 // If the bit convert changed the number of elements, it is unsafe
5307 // to examine the mask.
5308 if (BCNumEltsChanged)
5311 // Select the input vector, guarding against out of range extract vector.
5312 unsigned NumElems = VT.getVectorNumElements();
5313 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt);
5314 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
5316 if (InVec.getOpcode() == ISD::BIT_CONVERT)
5317 InVec = InVec.getOperand(0);
5318 if (ISD::isNormalLoad(InVec.getNode())) {
5319 LN0 = cast<LoadSDNode>(InVec);
5320 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems;
5324 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
5327 unsigned Align = LN0->getAlignment();
5329 // Check the resultant load doesn't need a higher alignment than the
5332 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT());
5334 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
5340 SDValue NewPtr = LN0->getBasePtr();
5342 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
5343 MVT PtrType = NewPtr.getValueType();
5344 if (TLI.isBigEndian())
5345 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
5346 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
5347 DAG.getConstant(PtrOff, PtrType));
5350 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
5351 LN0->getSrcValue(), LN0->getSrcValueOffset(),
5352 LN0->isVolatile(), Align);
5358 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
5359 unsigned NumInScalars = N->getNumOperands();
5360 MVT VT = N->getValueType(0);
5361 MVT EltType = VT.getVectorElementType();
5363 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
5364 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
5365 // at most two distinct vectors, turn this into a shuffle node.
5366 SDValue VecIn1, VecIn2;
5367 for (unsigned i = 0; i != NumInScalars; ++i) {
5368 // Ignore undef inputs.
5369 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5371 // If this input is something other than a EXTRACT_VECTOR_ELT with a
5372 // constant index, bail out.
5373 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5374 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
5375 VecIn1 = VecIn2 = SDValue(0, 0);
5379 // If the input vector type disagrees with the result of the build_vector,
5380 // we can't make a shuffle.
5381 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
5382 if (ExtractedFromVec.getValueType() != VT) {
5383 VecIn1 = VecIn2 = SDValue(0, 0);
5387 // Otherwise, remember this. We allow up to two distinct input vectors.
5388 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
5391 if (VecIn1.getNode() == 0) {
5392 VecIn1 = ExtractedFromVec;
5393 } else if (VecIn2.getNode() == 0) {
5394 VecIn2 = ExtractedFromVec;
5397 VecIn1 = VecIn2 = SDValue(0, 0);
5402 // If everything is good, we can make a shuffle operation.
5403 if (VecIn1.getNode()) {
5404 SmallVector<int, 8> Mask;
5405 for (unsigned i = 0; i != NumInScalars; ++i) {
5406 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
5411 // If extracting from the first vector, just use the index directly.
5412 SDValue Extract = N->getOperand(i);
5413 SDValue ExtVal = Extract.getOperand(1);
5414 if (Extract.getOperand(0) == VecIn1) {
5415 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5416 if (ExtIndex > VT.getVectorNumElements())
5419 Mask.push_back(ExtIndex);
5423 // Otherwise, use InIdx + VecSize
5424 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5425 Mask.push_back(Idx+NumInScalars);
5428 // Add count and size info.
5429 if (!TLI.isTypeLegal(VT) && LegalTypes)
5432 // Return the new VECTOR_SHUFFLE node.
5435 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5436 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
5442 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
5443 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
5444 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
5445 // inputs come from at most two distinct vectors, turn this into a shuffle
5448 // If we only have one input vector, we don't need to do any concatenation.
5449 if (N->getNumOperands() == 1)
5450 return N->getOperand(0);
5455 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
5458 MVT VT = N->getValueType(0);
5459 unsigned NumElts = VT.getVectorNumElements();
5461 SDValue N0 = N->getOperand(0);
5462 SDValue N1 = N->getOperand(1);
5464 assert(N0.getValueType().getVectorNumElements() == NumElts &&
5465 "Vector shuffle must be normalized in DAG");
5467 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
5469 // If it is a splat, check if the argument vector is a build_vector with
5470 // all scalar elements the same.
5471 if (cast<ShuffleVectorSDNode>(N)->isSplat()) {
5472 SDNode *V = N0.getNode();
5475 // If this is a bit convert that changes the element type of the vector but
5476 // not the number of vector elements, look through it. Be careful not to
5477 // look though conversions that change things like v4f32 to v2f64.
5478 if (V->getOpcode() == ISD::BIT_CONVERT) {
5479 SDValue ConvInput = V->getOperand(0);
5480 if (ConvInput.getValueType().isVector() &&
5481 ConvInput.getValueType().getVectorNumElements() == NumElts)
5482 V = ConvInput.getNode();
5485 if (V->getOpcode() == ISD::BUILD_VECTOR) {
5486 unsigned NumElems = V->getNumOperands();
5487 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex();
5488 if (NumElems > BaseIdx) {
5490 bool AllSame = true;
5491 for (unsigned i = 0; i != NumElems; ++i) {
5492 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
5493 Base = V->getOperand(i);
5497 // Splat of <u, u, u, u>, return <u, u, u, u>
5498 if (!Base.getNode())
5500 for (unsigned i = 0; i != NumElems; ++i) {
5501 if (V->getOperand(i) != Base) {
5506 // Splat of <x, x, x, x>, return <x, x, x, x>
5515 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
5516 /// an AND to a vector_shuffle with the destination vector and a zero vector.
5517 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
5518 /// vector_shuffle V, Zero, <0, 4, 2, 4>
5519 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
5520 MVT VT = N->getValueType(0);
5521 DebugLoc dl = N->getDebugLoc();
5522 SDValue LHS = N->getOperand(0);
5523 SDValue RHS = N->getOperand(1);
5524 if (N->getOpcode() == ISD::AND) {
5525 if (RHS.getOpcode() == ISD::BIT_CONVERT)
5526 RHS = RHS.getOperand(0);
5527 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
5528 SmallVector<int, 8> Indices;
5529 unsigned NumElts = RHS.getNumOperands();
5530 for (unsigned i = 0; i != NumElts; ++i) {
5531 SDValue Elt = RHS.getOperand(i);
5532 if (!isa<ConstantSDNode>(Elt))
5534 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
5535 Indices.push_back(i);
5536 else if (cast<ConstantSDNode>(Elt)->isNullValue())
5537 Indices.push_back(NumElts);
5542 // Let's see if the target supports this vector_shuffle.
5543 MVT RVT = RHS.getValueType();
5544 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
5547 // Return the new VECTOR_SHUFFLE node.
5548 MVT EVT = RVT.getVectorElementType();
5549 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
5550 DAG.getConstant(0, EVT));
5551 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5552 RVT, &ZeroOps[0], ZeroOps.size());
5553 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS);
5554 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
5555 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf);
5562 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
5563 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
5564 // After legalize, the target may be depending on adds and other
5565 // binary ops to provide legal ways to construct constants or other
5566 // things. Simplifying them may result in a loss of legality.
5567 if (LegalOperations) return SDValue();
5569 MVT VT = N->getValueType(0);
5570 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
5572 MVT EltType = VT.getVectorElementType();
5573 SDValue LHS = N->getOperand(0);
5574 SDValue RHS = N->getOperand(1);
5575 SDValue Shuffle = XformToShuffleWithZero(N);
5576 if (Shuffle.getNode()) return Shuffle;
5578 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
5580 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
5581 RHS.getOpcode() == ISD::BUILD_VECTOR) {
5582 SmallVector<SDValue, 8> Ops;
5583 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
5584 SDValue LHSOp = LHS.getOperand(i);
5585 SDValue RHSOp = RHS.getOperand(i);
5586 // If these two elements can't be folded, bail out.
5587 if ((LHSOp.getOpcode() != ISD::UNDEF &&
5588 LHSOp.getOpcode() != ISD::Constant &&
5589 LHSOp.getOpcode() != ISD::ConstantFP) ||
5590 (RHSOp.getOpcode() != ISD::UNDEF &&
5591 RHSOp.getOpcode() != ISD::Constant &&
5592 RHSOp.getOpcode() != ISD::ConstantFP))
5595 // Can't fold divide by zero.
5596 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
5597 N->getOpcode() == ISD::FDIV) {
5598 if ((RHSOp.getOpcode() == ISD::Constant &&
5599 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
5600 (RHSOp.getOpcode() == ISD::ConstantFP &&
5601 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
5605 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(),
5606 EltType, LHSOp, RHSOp));
5607 AddToWorkList(Ops.back().getNode());
5608 assert((Ops.back().getOpcode() == ISD::UNDEF ||
5609 Ops.back().getOpcode() == ISD::Constant ||
5610 Ops.back().getOpcode() == ISD::ConstantFP) &&
5611 "Scalar binop didn't fold!");
5614 if (Ops.size() == LHS.getNumOperands()) {
5615 MVT VT = LHS.getValueType();
5616 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
5617 &Ops[0], Ops.size());
5624 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
5625 SDValue N1, SDValue N2){
5626 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
5628 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
5629 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5631 // If we got a simplified select_cc node back from SimplifySelectCC, then
5632 // break it down into a new SETCC node, and a new SELECT node, and then return
5633 // the SELECT node, since we were called with a SELECT node.
5634 if (SCC.getNode()) {
5635 // Check to see if we got a select_cc back (to turn into setcc/select).
5636 // Otherwise, just return whatever node we got back, like fabs.
5637 if (SCC.getOpcode() == ISD::SELECT_CC) {
5638 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
5640 SCC.getOperand(0), SCC.getOperand(1),
5642 AddToWorkList(SETCC.getNode());
5643 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
5644 SCC.getOperand(2), SCC.getOperand(3), SETCC);
5652 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
5653 /// are the two values being selected between, see if we can simplify the
5654 /// select. Callers of this should assume that TheSelect is deleted if this
5655 /// returns true. As such, they should return the appropriate thing (e.g. the
5656 /// node) back to the top-level of the DAG combiner loop to avoid it being
5658 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
5661 // If this is a select from two identical things, try to pull the operation
5662 // through the select.
5663 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
5664 // If this is a load and the token chain is identical, replace the select
5665 // of two loads with a load through a select of the address to load from.
5666 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
5667 // constants have been dropped into the constant pool.
5668 if (LHS.getOpcode() == ISD::LOAD &&
5669 // Do not let this transformation reduce the number of volatile loads.
5670 !cast<LoadSDNode>(LHS)->isVolatile() &&
5671 !cast<LoadSDNode>(RHS)->isVolatile() &&
5672 // Token chains must be identical.
5673 LHS.getOperand(0) == RHS.getOperand(0)) {
5674 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
5675 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
5677 // If this is an EXTLOAD, the VT's must match.
5678 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
5679 // FIXME: this conflates two src values, discarding one. This is not
5680 // the right thing to do, but nothing uses srcvalues now. When they do,
5681 // turn SrcValue into a list of locations.
5683 if (TheSelect->getOpcode() == ISD::SELECT) {
5684 // Check that the condition doesn't reach either load. If so, folding
5685 // this will induce a cycle into the DAG.
5686 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5687 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) {
5688 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
5689 LLD->getBasePtr().getValueType(),
5690 TheSelect->getOperand(0), LLD->getBasePtr(),
5694 // Check that the condition doesn't reach either load. If so, folding
5695 // this will induce a cycle into the DAG.
5696 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5697 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5698 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) &&
5699 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) {
5700 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
5701 LLD->getBasePtr().getValueType(),
5702 TheSelect->getOperand(0),
5703 TheSelect->getOperand(1),
5704 LLD->getBasePtr(), RLD->getBasePtr(),
5705 TheSelect->getOperand(4));
5709 if (Addr.getNode()) {
5711 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
5712 Load = DAG.getLoad(TheSelect->getValueType(0),
5713 TheSelect->getDebugLoc(),
5715 Addr,LLD->getSrcValue(),
5716 LLD->getSrcValueOffset(),
5718 LLD->getAlignment());
5720 Load = DAG.getExtLoad(LLD->getExtensionType(),
5721 TheSelect->getDebugLoc(),
5722 TheSelect->getValueType(0),
5723 LLD->getChain(), Addr, LLD->getSrcValue(),
5724 LLD->getSrcValueOffset(),
5727 LLD->getAlignment());
5730 // Users of the select now use the result of the load.
5731 CombineTo(TheSelect, Load);
5733 // Users of the old loads now use the new load's chain. We know the
5734 // old-load value is dead now.
5735 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
5736 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
5746 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
5747 /// where 'cond' is the comparison specified by CC.
5748 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
5749 SDValue N2, SDValue N3,
5750 ISD::CondCode CC, bool NotExtCompare) {
5751 // (x ? y : y) -> y.
5752 if (N2 == N3) return N2;
5754 MVT VT = N2.getValueType();
5755 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
5756 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
5757 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
5759 // Determine if the condition we're dealing with is constant
5760 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
5761 N0, N1, CC, DL, false);
5762 if (SCC.getNode()) AddToWorkList(SCC.getNode());
5763 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
5765 // fold select_cc true, x, y -> x
5766 if (SCCC && !SCCC->isNullValue())
5768 // fold select_cc false, x, y -> y
5769 if (SCCC && SCCC->isNullValue())
5772 // Check to see if we can simplify the select into an fabs node
5773 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
5774 // Allow either -0.0 or 0.0
5775 if (CFP->getValueAPF().isZero()) {
5776 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
5777 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
5778 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
5779 N2 == N3.getOperand(0))
5780 return DAG.getNode(ISD::FABS, DL, VT, N0);
5782 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
5783 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
5784 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
5785 N2.getOperand(0) == N3)
5786 return DAG.getNode(ISD::FABS, DL, VT, N3);
5790 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
5791 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
5792 // in it. This is a win when the constant is not otherwise available because
5793 // it replaces two constant pool loads with one. We only do this if the FP
5794 // type is known to be legal, because if it isn't, then we are before legalize
5795 // types an we want the other legalization to happen first (e.g. to avoid
5796 // messing with soft float) and if the ConstantFP is not legal, because if
5797 // it is legal, we may not need to store the FP constant in a constant pool.
5798 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
5799 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
5800 if (TLI.isTypeLegal(N2.getValueType()) &&
5801 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
5802 TargetLowering::Legal) &&
5803 // If both constants have multiple uses, then we won't need to do an
5804 // extra load, they are likely around in registers for other users.
5805 (TV->hasOneUse() || FV->hasOneUse())) {
5806 Constant *Elts[] = {
5807 const_cast<ConstantFP*>(FV->getConstantFPValue()),
5808 const_cast<ConstantFP*>(TV->getConstantFPValue())
5810 const Type *FPTy = Elts[0]->getType();
5811 const TargetData &TD = *TLI.getTargetData();
5813 // Create a ConstantArray of the two constants.
5814 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
5815 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
5816 TD.getPrefTypeAlignment(FPTy));
5817 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5819 // Get the offsets to the 0 and 1 element of the array so that we can
5820 // select between them.
5821 SDValue Zero = DAG.getIntPtrConstant(0);
5822 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
5823 SDValue One = DAG.getIntPtrConstant(EltSize);
5825 SDValue Cond = DAG.getSetCC(DL,
5826 TLI.getSetCCResultType(N0.getValueType()),
5828 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
5830 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
5832 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
5833 PseudoSourceValue::getConstantPool(), 0, false,
5839 // Check to see if we can perform the "gzip trick", transforming
5840 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
5841 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
5842 N0.getValueType().isInteger() &&
5843 N2.getValueType().isInteger() &&
5844 (N1C->isNullValue() || // (a < 0) ? b : 0
5845 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
5846 MVT XType = N0.getValueType();
5847 MVT AType = N2.getValueType();
5848 if (XType.bitsGE(AType)) {
5849 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
5850 // single-bit constant.
5851 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
5852 unsigned ShCtV = N2C->getAPIntValue().logBase2();
5853 ShCtV = XType.getSizeInBits()-ShCtV-1;
5854 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
5855 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
5857 AddToWorkList(Shift.getNode());
5859 if (XType.bitsGT(AType)) {
5860 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
5861 AddToWorkList(Shift.getNode());
5864 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
5867 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
5869 DAG.getConstant(XType.getSizeInBits()-1,
5870 getShiftAmountTy()));
5871 AddToWorkList(Shift.getNode());
5873 if (XType.bitsGT(AType)) {
5874 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
5875 AddToWorkList(Shift.getNode());
5878 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
5882 // fold select C, 16, 0 -> shl C, 4
5883 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
5884 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
5886 // If the caller doesn't want us to simplify this into a zext of a compare,
5888 if (NotExtCompare && N2C->getAPIntValue() == 1)
5891 // Get a SetCC of the condition
5892 // FIXME: Should probably make sure that setcc is legal if we ever have a
5893 // target where it isn't.
5895 // cast from setcc result type to select result type
5897 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
5899 if (N2.getValueType().bitsLT(SCC.getValueType()))
5900 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
5902 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
5903 N2.getValueType(), SCC);
5905 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
5906 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
5907 N2.getValueType(), SCC);
5910 AddToWorkList(SCC.getNode());
5911 AddToWorkList(Temp.getNode());
5913 if (N2C->getAPIntValue() == 1)
5916 // shl setcc result by log2 n2c
5917 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
5918 DAG.getConstant(N2C->getAPIntValue().logBase2(),
5919 getShiftAmountTy()));
5922 // Check to see if this is the equivalent of setcc
5923 // FIXME: Turn all of these into setcc if setcc if setcc is legal
5924 // otherwise, go ahead with the folds.
5925 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
5926 MVT XType = N0.getValueType();
5927 if (!LegalOperations ||
5928 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
5929 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
5930 if (Res.getValueType() != VT)
5931 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
5935 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
5936 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
5937 (!LegalOperations ||
5938 TLI.isOperationLegal(ISD::CTLZ, XType))) {
5939 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
5940 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
5941 DAG.getConstant(Log2_32(XType.getSizeInBits()),
5942 getShiftAmountTy()));
5944 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
5945 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
5946 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
5947 XType, DAG.getConstant(0, XType), N0);
5948 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
5949 return DAG.getNode(ISD::SRL, DL, XType,
5950 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
5951 DAG.getConstant(XType.getSizeInBits()-1,
5952 getShiftAmountTy()));
5954 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
5955 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
5956 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
5957 DAG.getConstant(XType.getSizeInBits()-1,
5958 getShiftAmountTy()));
5959 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
5963 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
5964 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5965 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
5966 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
5967 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
5968 MVT XType = N0.getValueType();
5969 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
5970 DAG.getConstant(XType.getSizeInBits()-1,
5971 getShiftAmountTy()));
5972 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
5974 AddToWorkList(Shift.getNode());
5975 AddToWorkList(Add.getNode());
5976 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
5978 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
5979 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5980 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
5981 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
5982 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
5983 MVT XType = N0.getValueType();
5984 if (SubC->isNullValue() && XType.isInteger()) {
5985 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
5987 DAG.getConstant(XType.getSizeInBits()-1,
5988 getShiftAmountTy()));
5989 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
5991 AddToWorkList(Shift.getNode());
5992 AddToWorkList(Add.getNode());
5993 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6001 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
6002 SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0,
6003 SDValue N1, ISD::CondCode Cond,
6004 DebugLoc DL, bool foldBooleans) {
6005 TargetLowering::DAGCombinerInfo
6006 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
6007 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
6010 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
6011 /// return a DAG expression to select that will generate the same value by
6012 /// multiplying by a magic number. See:
6013 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6014 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
6015 std::vector<SDNode*> Built;
6016 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
6018 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6024 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
6025 /// return a DAG expression to select that will generate the same value by
6026 /// multiplying by a magic number. See:
6027 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6028 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
6029 std::vector<SDNode*> Built;
6030 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
6032 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6038 /// FindBaseOffset - Return true if base is known not to alias with anything
6039 /// but itself. Provides base object and offset as results.
6040 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
6041 // Assume it is a primitive operation.
6042 Base = Ptr; Offset = 0;
6044 // If it's an adding a simple constant then integrate the offset.
6045 if (Base.getOpcode() == ISD::ADD) {
6046 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
6047 Base = Base.getOperand(0);
6048 Offset += C->getZExtValue();
6052 // If it's any of the following then it can't alias with anything but itself.
6053 return isa<FrameIndexSDNode>(Base) ||
6054 isa<ConstantPoolSDNode>(Base) ||
6055 isa<GlobalAddressSDNode>(Base);
6058 /// isAlias - Return true if there is any possibility that the two addresses
6060 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
6061 const Value *SrcValue1, int SrcValueOffset1,
6062 SDValue Ptr2, int64_t Size2,
6063 const Value *SrcValue2, int SrcValueOffset2) const {
6064 // If they are the same then they must be aliases.
6065 if (Ptr1 == Ptr2) return true;
6067 // Gather base node and offset information.
6068 SDValue Base1, Base2;
6069 int64_t Offset1, Offset2;
6070 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
6071 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
6073 // If they have a same base address then...
6075 // Check to see if the addresses overlap.
6076 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
6078 // If we know both bases then they can't alias.
6079 if (KnownBase1 && KnownBase2) return false;
6081 if (CombinerGlobalAA) {
6082 // Use alias analysis information.
6083 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
6084 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
6085 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
6086 AliasAnalysis::AliasResult AAResult =
6087 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
6088 if (AAResult == AliasAnalysis::NoAlias)
6092 // Otherwise we have to assume they alias.
6096 /// FindAliasInfo - Extracts the relevant alias information from the memory
6097 /// node. Returns true if the operand was a load.
6098 bool DAGCombiner::FindAliasInfo(SDNode *N,
6099 SDValue &Ptr, int64_t &Size,
6100 const Value *&SrcValue, int &SrcValueOffset) const {
6101 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6102 Ptr = LD->getBasePtr();
6103 Size = LD->getMemoryVT().getSizeInBits() >> 3;
6104 SrcValue = LD->getSrcValue();
6105 SrcValueOffset = LD->getSrcValueOffset();
6107 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6108 Ptr = ST->getBasePtr();
6109 Size = ST->getMemoryVT().getSizeInBits() >> 3;
6110 SrcValue = ST->getSrcValue();
6111 SrcValueOffset = ST->getSrcValueOffset();
6113 llvm_unreachable("FindAliasInfo expected a memory operand");
6119 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
6120 /// looking for aliasing nodes and adding them to the Aliases vector.
6121 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
6122 SmallVector<SDValue, 8> &Aliases) {
6123 SmallVector<SDValue, 8> Chains; // List of chains to visit.
6124 std::set<SDNode *> Visited; // Visited node set.
6126 // Get alias information for node.
6129 const Value *SrcValue = 0;
6130 int SrcValueOffset = 0;
6131 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
6134 Chains.push_back(OriginalChain);
6136 // Look at each chain and determine if it is an alias. If so, add it to the
6137 // aliases list. If not, then continue up the chain looking for the next
6139 while (!Chains.empty()) {
6140 SDValue Chain = Chains.back();
6143 // Don't bother if we've been before.
6144 if (Visited.find(Chain.getNode()) != Visited.end()) continue;
6145 Visited.insert(Chain.getNode());
6147 switch (Chain.getOpcode()) {
6148 case ISD::EntryToken:
6149 // Entry token is ideal chain operand, but handled in FindBetterChain.
6154 // Get alias information for Chain.
6157 const Value *OpSrcValue = 0;
6158 int OpSrcValueOffset = 0;
6159 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
6160 OpSrcValue, OpSrcValueOffset);
6162 // If chain is alias then stop here.
6163 if (!(IsLoad && IsOpLoad) &&
6164 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
6165 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
6166 Aliases.push_back(Chain);
6168 // Look further up the chain.
6169 Chains.push_back(Chain.getOperand(0));
6170 // Clean up old chain.
6171 AddToWorkList(Chain.getNode());
6176 case ISD::TokenFactor:
6177 // We have to check each of the operands of the token factor, so we queue
6178 // then up. Adding the operands to the queue (stack) in reverse order
6179 // maintains the original order and increases the likelihood that getNode
6180 // will find a matching token factor (CSE.)
6181 for (unsigned n = Chain.getNumOperands(); n;)
6182 Chains.push_back(Chain.getOperand(--n));
6183 // Eliminate the token factor if we can.
6184 AddToWorkList(Chain.getNode());
6188 // For all other instructions we will just have to take what we can get.
6189 Aliases.push_back(Chain);
6195 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
6196 /// for a better chain (aliasing node.)
6197 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
6198 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
6200 // Accumulate all the aliases to this node.
6201 GatherAllAliases(N, OldChain, Aliases);
6203 if (Aliases.size() == 0) {
6204 // If no operands then chain to entry token.
6205 return DAG.getEntryNode();
6206 } else if (Aliases.size() == 1) {
6207 // If a single operand then chain to it. We don't need to revisit it.
6211 // Construct a custom tailored token factor.
6212 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6213 &Aliases[0], Aliases.size());
6215 // Make sure the old chain gets cleaned up.
6216 if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
6221 // SelectionDAG::Combine - This is the entry point for the file.
6223 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
6224 CodeGenOpt::Level OptLevel) {
6225 /// run - This is the main entry point to this class.
6227 DAGCombiner(*this, AA, OptLevel).Run(Level);