1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: Should add a corresponding version of fold AND with
20 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
23 // FIXME: select C, pow2, pow2 -> something smart
24 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
25 // FIXME: (select C, load A, load B) -> load (select C, A, B)
26 // FIXME: Dead stores -> nuke
27 // FIXME: shr X, (and Y,31) -> shr X, Y
28 // FIXME: TRUNC (LOAD) -> EXT_LOAD/LOAD(smaller)
29 // FIXME: mul (x, const) -> shifts + adds
30 // FIXME: undef values
31 // FIXME: make truncate see through SIGN_EXTEND and AND
32 // FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
33 // FIXME: verify that getNode can't return extends with an operand whose type
34 // is >= to that of the extend.
35 // FIXME: divide by zero is currently left unfolded. do we want to turn this
37 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
38 // FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use
40 //===----------------------------------------------------------------------===//
42 #define DEBUG_TYPE "dagcombine"
43 #include "llvm/ADT/Statistic.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Target/TargetLowering.h"
53 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
60 // Worklist of all of the nodes that need to be simplified.
61 std::vector<SDNode*> WorkList;
63 /// AddUsersToWorkList - When an instruction is simplified, add all users of
64 /// the instruction to the work lists because they might get more simplified
67 void AddUsersToWorkList(SDNode *N) {
68 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
70 WorkList.push_back(*UI);
73 /// removeFromWorkList - remove all instances of N from the worklist.
74 void removeFromWorkList(SDNode *N) {
75 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
79 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
81 DEBUG(std::cerr << "\nReplacing "; N->dump();
82 std::cerr << "\nWith: "; To[0].Val->dump();
83 std::cerr << " and " << To.size()-1 << " other values\n");
84 std::vector<SDNode*> NowDead;
85 DAG.ReplaceAllUsesWith(N, To, &NowDead);
87 // Push the new nodes and any users onto the worklist
88 for (unsigned i = 0, e = To.size(); i != e; ++i) {
89 WorkList.push_back(To[i].Val);
90 AddUsersToWorkList(To[i].Val);
93 // Nodes can end up on the worklist more than once. Make sure we do
94 // not process a node that has been replaced.
95 removeFromWorkList(N);
96 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
97 removeFromWorkList(NowDead[i]);
99 // Finally, since the node is now dead, remove it from the graph.
101 return SDOperand(N, 0);
104 SDOperand CombineTo(SDNode *N, SDOperand Res) {
105 std::vector<SDOperand> To;
107 return CombineTo(N, To);
110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
111 std::vector<SDOperand> To;
114 return CombineTo(N, To);
117 /// visit - call the node-specific routine that knows how to fold each
118 /// particular type of node.
119 SDOperand visit(SDNode *N);
121 // Visitation implementation - Implement dag node combining for different
122 // node types. The semantics are as follows:
124 // SDOperand.Val == 0 - No change was made
125 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
126 // otherwise - N should be replaced by the returned Operand.
128 SDOperand visitTokenFactor(SDNode *N);
129 SDOperand visitADD(SDNode *N);
130 SDOperand visitSUB(SDNode *N);
131 SDOperand visitMUL(SDNode *N);
132 SDOperand visitSDIV(SDNode *N);
133 SDOperand visitUDIV(SDNode *N);
134 SDOperand visitSREM(SDNode *N);
135 SDOperand visitUREM(SDNode *N);
136 SDOperand visitMULHU(SDNode *N);
137 SDOperand visitMULHS(SDNode *N);
138 SDOperand visitAND(SDNode *N);
139 SDOperand visitOR(SDNode *N);
140 SDOperand visitXOR(SDNode *N);
141 SDOperand visitSHL(SDNode *N);
142 SDOperand visitSRA(SDNode *N);
143 SDOperand visitSRL(SDNode *N);
144 SDOperand visitCTLZ(SDNode *N);
145 SDOperand visitCTTZ(SDNode *N);
146 SDOperand visitCTPOP(SDNode *N);
147 SDOperand visitSELECT(SDNode *N);
148 SDOperand visitSELECT_CC(SDNode *N);
149 SDOperand visitSETCC(SDNode *N);
150 SDOperand visitADD_PARTS(SDNode *N);
151 SDOperand visitSUB_PARTS(SDNode *N);
152 SDOperand visitSIGN_EXTEND(SDNode *N);
153 SDOperand visitZERO_EXTEND(SDNode *N);
154 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
155 SDOperand visitTRUNCATE(SDNode *N);
157 SDOperand visitFADD(SDNode *N);
158 SDOperand visitFSUB(SDNode *N);
159 SDOperand visitFMUL(SDNode *N);
160 SDOperand visitFDIV(SDNode *N);
161 SDOperand visitFREM(SDNode *N);
162 SDOperand visitSINT_TO_FP(SDNode *N);
163 SDOperand visitUINT_TO_FP(SDNode *N);
164 SDOperand visitFP_TO_SINT(SDNode *N);
165 SDOperand visitFP_TO_UINT(SDNode *N);
166 SDOperand visitFP_ROUND(SDNode *N);
167 SDOperand visitFP_ROUND_INREG(SDNode *N);
168 SDOperand visitFP_EXTEND(SDNode *N);
169 SDOperand visitFNEG(SDNode *N);
170 SDOperand visitFABS(SDNode *N);
171 SDOperand visitBRCOND(SDNode *N);
172 SDOperand visitBRCONDTWOWAY(SDNode *N);
173 SDOperand visitBR_CC(SDNode *N);
174 SDOperand visitBRTWOWAY_CC(SDNode *N);
176 SDOperand visitLOAD(SDNode *N);
177 SDOperand visitSTORE(SDNode *N);
179 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
180 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
181 SDOperand N3, ISD::CondCode CC);
182 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
183 ISD::CondCode Cond, bool foldBooleans = true);
185 DAGCombiner(SelectionDAG &D)
186 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
188 /// Run - runs the dag combiner on all nodes in the work list
189 void Run(bool RunningAfterLegalize);
193 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use
194 /// this predicate to simplify operations downstream. Op and Mask are known to
195 /// be the same type.
196 static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
197 const TargetLowering &TLI) {
199 if (Mask == 0) return true;
201 // If we know the result of a setcc has the top bits zero, use this info.
202 switch (Op.getOpcode()) {
204 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
206 return ((Mask & 1) == 0) &&
207 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
209 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
210 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
211 case ISD::ZERO_EXTEND:
212 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
213 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
214 case ISD::AssertZext:
215 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
216 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
218 // If either of the operands has zero bits, the result will too.
219 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
220 MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
222 // (X & C1) & C2 == 0 iff C1 & C2 == 0.
223 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
224 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
228 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
229 MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
231 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
232 MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
234 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
235 MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
237 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0
238 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
239 uint64_t NewVal = Mask << ShAmt->getValue();
240 SrcBits = MVT::getSizeInBits(Op.getValueType());
241 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
242 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
246 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0
247 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
248 uint64_t NewVal = Mask >> ShAmt->getValue();
249 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
253 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
254 if ((Mask&(Mask+1)) == 0) { // All low bits
255 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
256 MaskedValueIsZero(Op.getOperand(1), Mask, TLI))
261 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
262 // We know that the top bits of C-X are clear if X contains less bits
263 // than C (i.e. no wrap-around can happen). For example, 20-X is
264 // positive if we can prove that X is >= 0 and < 16.
265 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
266 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear
267 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
268 uint64_t MaskV = (1ULL << (63-NLZ))-1;
269 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) {
270 // High bits are clear this value is known to be >= C.
271 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
272 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
281 // Bit counting instructions can not set the high bits of the result
282 // register. The max number of bits sets depends on the input.
283 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
289 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
290 // that selects between the values 1 and 0, making it equivalent to a setcc.
291 // Also, set the incoming LHS, RHS, and CC references to the appropriate
292 // nodes based on the type of node we are checking. This simplifies life a
293 // bit for the callers.
294 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
296 if (N.getOpcode() == ISD::SETCC) {
297 LHS = N.getOperand(0);
298 RHS = N.getOperand(1);
299 CC = N.getOperand(2);
302 if (N.getOpcode() == ISD::SELECT_CC &&
303 N.getOperand(2).getOpcode() == ISD::Constant &&
304 N.getOperand(3).getOpcode() == ISD::Constant &&
305 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
306 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
307 LHS = N.getOperand(0);
308 RHS = N.getOperand(1);
309 CC = N.getOperand(4);
315 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
316 // one use. If this is true, it allows the users to invert the operation for
317 // free when it is profitable to do so.
318 static bool isOneUseSetCC(SDOperand N) {
319 SDOperand N0, N1, N2;
320 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
325 // FIXME: This should probably go in the ISD class rather than being duplicated
327 static bool isCommutativeBinOp(unsigned Opcode) {
333 case ISD::XOR: return true;
334 default: return false; // FIXME: Need commutative info for user ops!
338 void DAGCombiner::Run(bool RunningAfterLegalize) {
339 // set the instance variable, so that the various visit routines may use it.
340 AfterLegalize = RunningAfterLegalize;
342 // Add all the dag nodes to the worklist.
343 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end());
345 // Create a dummy node (which is not added to allnodes), that adds a reference
346 // to the root node, preventing it from being deleted, and tracking any
347 // changes of the root.
348 HandleSDNode Dummy(DAG.getRoot());
350 // while the worklist isn't empty, inspect the node on the end of it and
351 // try and combine it.
352 while (!WorkList.empty()) {
353 SDNode *N = WorkList.back();
356 // If N has no uses, it is dead. Make sure to revisit all N's operands once
357 // N is deleted from the DAG, since they too may now be dead or may have a
358 // reduced number of uses, allowing other xforms.
359 if (N->use_empty() && N != &Dummy) {
360 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
361 WorkList.push_back(N->getOperand(i).Val);
363 removeFromWorkList(N);
368 SDOperand RV = visit(N);
371 // If we get back the same node we passed in, rather than a new node or
372 // zero, we know that the node must have defined multiple values and
373 // CombineTo was used. Since CombineTo takes care of the worklist
374 // mechanics for us, we have no work to do in this case.
376 DEBUG(std::cerr << "\nReplacing "; N->dump();
377 std::cerr << "\nWith: "; RV.Val->dump();
379 std::vector<SDNode*> NowDead;
380 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
382 // Push the new node and any users onto the worklist
383 WorkList.push_back(RV.Val);
384 AddUsersToWorkList(RV.Val);
386 // Nodes can end up on the worklist more than once. Make sure we do
387 // not process a node that has been replaced.
388 removeFromWorkList(N);
389 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
390 removeFromWorkList(NowDead[i]);
392 // Finally, since the node is now dead, remove it from the graph.
398 // If the root changed (e.g. it was a dead load, update the root).
399 DAG.setRoot(Dummy.getValue());
402 SDOperand DAGCombiner::visit(SDNode *N) {
403 switch(N->getOpcode()) {
405 case ISD::TokenFactor: return visitTokenFactor(N);
406 case ISD::ADD: return visitADD(N);
407 case ISD::SUB: return visitSUB(N);
408 case ISD::MUL: return visitMUL(N);
409 case ISD::SDIV: return visitSDIV(N);
410 case ISD::UDIV: return visitUDIV(N);
411 case ISD::SREM: return visitSREM(N);
412 case ISD::UREM: return visitUREM(N);
413 case ISD::MULHU: return visitMULHU(N);
414 case ISD::MULHS: return visitMULHS(N);
415 case ISD::AND: return visitAND(N);
416 case ISD::OR: return visitOR(N);
417 case ISD::XOR: return visitXOR(N);
418 case ISD::SHL: return visitSHL(N);
419 case ISD::SRA: return visitSRA(N);
420 case ISD::SRL: return visitSRL(N);
421 case ISD::CTLZ: return visitCTLZ(N);
422 case ISD::CTTZ: return visitCTTZ(N);
423 case ISD::CTPOP: return visitCTPOP(N);
424 case ISD::SELECT: return visitSELECT(N);
425 case ISD::SELECT_CC: return visitSELECT_CC(N);
426 case ISD::SETCC: return visitSETCC(N);
427 case ISD::ADD_PARTS: return visitADD_PARTS(N);
428 case ISD::SUB_PARTS: return visitSUB_PARTS(N);
429 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
430 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
431 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
432 case ISD::TRUNCATE: return visitTRUNCATE(N);
433 case ISD::FADD: return visitFADD(N);
434 case ISD::FSUB: return visitFSUB(N);
435 case ISD::FMUL: return visitFMUL(N);
436 case ISD::FDIV: return visitFDIV(N);
437 case ISD::FREM: return visitFREM(N);
438 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
439 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
440 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
441 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
442 case ISD::FP_ROUND: return visitFP_ROUND(N);
443 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
444 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
445 case ISD::FNEG: return visitFNEG(N);
446 case ISD::FABS: return visitFABS(N);
447 case ISD::BRCOND: return visitBRCOND(N);
448 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
449 case ISD::BR_CC: return visitBR_CC(N);
450 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
451 case ISD::LOAD: return visitLOAD(N);
452 case ISD::STORE: return visitSTORE(N);
457 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
458 std::vector<SDOperand> Ops;
459 bool Changed = false;
461 // If the token factor has two operands and one is the entry token, replace
462 // the token factor with the other operand.
463 if (N->getNumOperands() == 2) {
464 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
465 return N->getOperand(1);
466 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
467 return N->getOperand(0);
470 // fold (tokenfactor (tokenfactor)) -> tokenfactor
471 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
472 SDOperand Op = N->getOperand(i);
473 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
475 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
476 Ops.push_back(Op.getOperand(j));
482 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
486 SDOperand DAGCombiner::visitADD(SDNode *N) {
487 SDOperand N0 = N->getOperand(0);
488 SDOperand N1 = N->getOperand(1);
489 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
490 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
491 MVT::ValueType VT = N0.getValueType();
493 // fold (add c1, c2) -> c1+c2
495 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT);
496 // canonicalize constant to RHS
501 // fold (add x, 0) -> x
502 if (N1C && N1C->isNullValue())
504 // fold (add (add x, c1), c2) -> (add x, c1+c2)
505 if (N1C && N0.getOpcode() == ISD::ADD) {
506 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
507 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
509 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1),
510 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT));
512 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
513 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT));
515 // fold ((0-A) + B) -> B-A
516 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
517 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
518 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
519 // fold (A + (0-B)) -> A-B
520 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
521 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
522 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
523 // fold (A+(B-A)) -> B
524 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
525 return N1.getOperand(0);
529 SDOperand DAGCombiner::visitSUB(SDNode *N) {
530 SDOperand N0 = N->getOperand(0);
531 SDOperand N1 = N->getOperand(1);
532 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
533 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
535 // fold (sub c1, c2) -> c1-c2
537 return DAG.getConstant(N0C->getValue() - N1C->getValue(),
539 // fold (sub x, c) -> (add x, -c)
541 return DAG.getNode(ISD::ADD, N0.getValueType(), N0,
542 DAG.getConstant(-N1C->getValue(), N0.getValueType()));
545 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
546 return N0.getOperand(1);
548 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
549 return N0.getOperand(0);
553 SDOperand DAGCombiner::visitMUL(SDNode *N) {
554 SDOperand N0 = N->getOperand(0);
555 SDOperand N1 = N->getOperand(1);
556 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
557 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
558 MVT::ValueType VT = N0.getValueType();
560 // fold (mul c1, c2) -> c1*c2
562 return DAG.getConstant(N0C->getValue() * N1C->getValue(),
564 // canonicalize constant to RHS
569 // fold (mul x, 0) -> 0
570 if (N1C && N1C->isNullValue())
572 // fold (mul x, -1) -> 0-x
573 if (N1C && N1C->isAllOnesValue())
574 return DAG.getNode(ISD::SUB, N->getValueType(0),
575 DAG.getConstant(0, N->getValueType(0)), N0);
576 // fold (mul x, (1 << c)) -> x << c
577 if (N1C && isPowerOf2_64(N1C->getValue()))
578 return DAG.getNode(ISD::SHL, N->getValueType(0), N0,
579 DAG.getConstant(Log2_64(N1C->getValue()),
580 TLI.getShiftAmountTy()));
581 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
582 if (N1C && N0.getOpcode() == ISD::MUL) {
583 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
584 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
586 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1),
587 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT));
589 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
590 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT));
595 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
596 SDOperand N0 = N->getOperand(0);
597 SDOperand N1 = N->getOperand(1);
598 MVT::ValueType VT = N->getValueType(0);
599 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
600 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
602 // fold (sdiv c1, c2) -> c1/c2
603 if (N0C && N1C && !N1C->isNullValue())
604 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(),
606 // If we know the sign bits of both operands are zero, strength reduce to a
607 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
608 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
609 if (MaskedValueIsZero(N1, SignBit, TLI) &&
610 MaskedValueIsZero(N0, SignBit, TLI))
611 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
615 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
616 SDOperand N0 = N->getOperand(0);
617 SDOperand N1 = N->getOperand(1);
618 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
619 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
621 // fold (udiv c1, c2) -> c1/c2
622 if (N0C && N1C && !N1C->isNullValue())
623 return DAG.getConstant(N0C->getValue() / N1C->getValue(),
625 // fold (udiv x, (1 << c)) -> x >>u c
626 if (N1C && isPowerOf2_64(N1C->getValue()))
627 return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
628 DAG.getConstant(Log2_64(N1C->getValue()),
629 TLI.getShiftAmountTy()));
633 SDOperand DAGCombiner::visitSREM(SDNode *N) {
634 SDOperand N0 = N->getOperand(0);
635 SDOperand N1 = N->getOperand(1);
636 MVT::ValueType VT = N->getValueType(0);
637 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
638 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
640 // fold (srem c1, c2) -> c1%c2
641 if (N0C && N1C && !N1C->isNullValue())
642 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(),
644 // If we know the sign bits of both operands are zero, strength reduce to a
645 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
646 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
647 if (MaskedValueIsZero(N1, SignBit, TLI) &&
648 MaskedValueIsZero(N0, SignBit, TLI))
649 return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1);
653 SDOperand DAGCombiner::visitUREM(SDNode *N) {
654 SDOperand N0 = N->getOperand(0);
655 SDOperand N1 = N->getOperand(1);
656 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
657 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
659 // fold (urem c1, c2) -> c1%c2
660 if (N0C && N1C && !N1C->isNullValue())
661 return DAG.getConstant(N0C->getValue() % N1C->getValue(),
663 // fold (urem x, pow2) -> (and x, pow2-1)
664 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
665 return DAG.getNode(ISD::AND, N0.getValueType(), N0,
666 DAG.getConstant(N1C->getValue()-1, N1.getValueType()));
670 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
671 SDOperand N0 = N->getOperand(0);
672 SDOperand N1 = N->getOperand(1);
673 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
675 // fold (mulhs x, 0) -> 0
676 if (N1C && N1C->isNullValue())
678 // fold (mulhs x, 1) -> (sra x, size(x)-1)
679 if (N1C && N1C->getValue() == 1)
680 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
681 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
682 TLI.getShiftAmountTy()));
686 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
687 SDOperand N0 = N->getOperand(0);
688 SDOperand N1 = N->getOperand(1);
689 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
691 // fold (mulhu x, 0) -> 0
692 if (N1C && N1C->isNullValue())
694 // fold (mulhu x, 1) -> 0
695 if (N1C && N1C->getValue() == 1)
696 return DAG.getConstant(0, N0.getValueType());
700 SDOperand DAGCombiner::visitAND(SDNode *N) {
701 SDOperand N0 = N->getOperand(0);
702 SDOperand N1 = N->getOperand(1);
703 SDOperand LL, LR, RL, RR, CC0, CC1;
704 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
705 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
706 MVT::ValueType VT = N1.getValueType();
707 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
709 // fold (and c1, c2) -> c1&c2
711 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT);
712 // canonicalize constant to RHS
717 // fold (and x, -1) -> x
718 if (N1C && N1C->isAllOnesValue())
720 // if (and x, c) is known to be zero, return 0
721 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
722 return DAG.getConstant(0, VT);
723 // fold (and x, c) -> x iff (x & ~c) == 0
724 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
727 // fold (and (and x, c1), c2) -> (and x, c1^c2)
728 if (N1C && N0.getOpcode() == ISD::AND) {
729 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
730 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
732 return DAG.getNode(ISD::AND, VT, N0.getOperand(1),
733 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT));
735 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
736 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
738 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
739 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
740 unsigned ExtendBits =
741 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
742 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0)
743 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
745 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
746 if (N0.getOpcode() == ISD::OR && N1C)
747 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
748 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
750 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
751 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
752 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
753 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
755 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
756 MVT::isInteger(LL.getValueType())) {
757 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
758 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
759 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
760 WorkList.push_back(ORNode.Val);
761 return DAG.getSetCC(VT, ORNode, LR, Op1);
763 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
764 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
765 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
766 WorkList.push_back(ANDNode.Val);
767 return DAG.getSetCC(VT, ANDNode, LR, Op1);
769 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
770 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
771 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
772 WorkList.push_back(ORNode.Val);
773 return DAG.getSetCC(VT, ORNode, LR, Op1);
776 // canonicalize equivalent to ll == rl
777 if (LL == RR && LR == RL) {
778 Op1 = ISD::getSetCCSwappedOperands(Op1);
781 if (LL == RL && LR == RR) {
782 bool isInteger = MVT::isInteger(LL.getValueType());
783 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
784 if (Result != ISD::SETCC_INVALID)
785 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
788 // fold (and (zext x), (zext y)) -> (zext (and x, y))
789 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
790 N1.getOpcode() == ISD::ZERO_EXTEND &&
791 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
792 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
793 N0.getOperand(0), N1.getOperand(0));
794 WorkList.push_back(ANDNode.Val);
795 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
797 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y))
798 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
799 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) &&
800 N0.getOperand(1) == N1.getOperand(1)) {
801 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
802 N0.getOperand(0), N1.getOperand(0));
803 WorkList.push_back(ANDNode.Val);
804 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
806 // fold (zext_inreg (extload x)) -> (zextload x)
807 if (N0.getOpcode() == ISD::EXTLOAD) {
808 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
809 // If we zero all the possible extended bits, then we can turn this into
810 // a zextload if we are running before legalize or the operation is legal.
811 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
812 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
813 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
814 N0.getOperand(1), N0.getOperand(2),
816 WorkList.push_back(N);
817 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
821 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
822 if (N0.getOpcode() == ISD::SEXTLOAD && N0.Val->hasNUsesOfValue(1, 0)) {
823 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
824 // If we zero all the possible extended bits, then we can turn this into
825 // a zextload if we are running before legalize or the operation is legal.
826 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) &&
827 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
828 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
829 N0.getOperand(1), N0.getOperand(2),
831 WorkList.push_back(N);
832 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
839 SDOperand DAGCombiner::visitOR(SDNode *N) {
840 SDOperand N0 = N->getOperand(0);
841 SDOperand N1 = N->getOperand(1);
842 SDOperand LL, LR, RL, RR, CC0, CC1;
843 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
845 MVT::ValueType VT = N1.getValueType();
846 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
848 // fold (or c1, c2) -> c1|c2
850 return DAG.getConstant(N0C->getValue() | N1C->getValue(),
852 // canonicalize constant to RHS
857 // fold (or x, 0) -> x
858 if (N1C && N1C->isNullValue())
860 // fold (or x, -1) -> -1
861 if (N1C && N1C->isAllOnesValue())
863 // fold (or x, c) -> c iff (x & ~c) == 0
864 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
867 // fold (or (or x, c1), c2) -> (or x, c1|c2)
868 if (N1C && N0.getOpcode() == ISD::OR) {
869 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
870 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
872 return DAG.getNode(ISD::OR, VT, N0.getOperand(1),
873 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT));
875 return DAG.getNode(ISD::OR, VT, N0.getOperand(0),
876 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT));
878 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
879 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
880 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
881 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
883 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
884 MVT::isInteger(LL.getValueType())) {
885 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
886 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
887 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
888 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
889 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
890 WorkList.push_back(ORNode.Val);
891 return DAG.getSetCC(VT, ORNode, LR, Op1);
893 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
894 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
895 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
896 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
897 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
898 WorkList.push_back(ANDNode.Val);
899 return DAG.getSetCC(VT, ANDNode, LR, Op1);
902 // canonicalize equivalent to ll == rl
903 if (LL == RR && LR == RL) {
904 Op1 = ISD::getSetCCSwappedOperands(Op1);
907 if (LL == RL && LR == RR) {
908 bool isInteger = MVT::isInteger(LL.getValueType());
909 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
910 if (Result != ISD::SETCC_INVALID)
911 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
914 // fold (or (zext x), (zext y)) -> (zext (or x, y))
915 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
916 N1.getOpcode() == ISD::ZERO_EXTEND &&
917 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
918 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
919 N0.getOperand(0), N1.getOperand(0));
920 WorkList.push_back(ORNode.Val);
921 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
926 SDOperand DAGCombiner::visitXOR(SDNode *N) {
927 SDOperand N0 = N->getOperand(0);
928 SDOperand N1 = N->getOperand(1);
929 SDOperand LHS, RHS, CC;
930 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
931 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
932 MVT::ValueType VT = N0.getValueType();
934 // fold (xor c1, c2) -> c1^c2
936 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT);
937 // canonicalize constant to RHS
942 // fold (xor x, 0) -> x
943 if (N1C && N1C->isNullValue())
945 // fold !(x cc y) -> (x !cc y)
946 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
947 bool isInt = MVT::isInteger(LHS.getValueType());
948 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
950 if (N0.getOpcode() == ISD::SETCC)
951 return DAG.getSetCC(VT, LHS, RHS, NotCC);
952 if (N0.getOpcode() == ISD::SELECT_CC)
953 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
954 assert(0 && "Unhandled SetCC Equivalent!");
957 // fold !(x or y) -> (!x and !y) iff x or y are setcc
958 if (N1C && N1C->getValue() == 1 &&
959 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
960 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
961 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
962 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
963 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
964 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
965 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
966 return DAG.getNode(NewOpcode, VT, LHS, RHS);
969 // fold !(x or y) -> (!x and !y) iff x or y are constants
970 if (N1C && N1C->isAllOnesValue() &&
971 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
972 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
973 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
974 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
975 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
976 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
977 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
978 return DAG.getNode(NewOpcode, VT, LHS, RHS);
981 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
982 if (N1C && N0.getOpcode() == ISD::XOR) {
983 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
984 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
986 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
987 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
989 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
990 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
992 // fold (xor x, x) -> 0
994 return DAG.getConstant(0, VT);
995 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
996 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
997 N1.getOpcode() == ISD::ZERO_EXTEND &&
998 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
999 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1000 N0.getOperand(0), N1.getOperand(0));
1001 WorkList.push_back(XORNode.Val);
1002 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
1007 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1008 SDOperand N0 = N->getOperand(0);
1009 SDOperand N1 = N->getOperand(1);
1010 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1011 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1012 MVT::ValueType VT = N0.getValueType();
1013 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1015 // fold (shl c1, c2) -> c1<<c2
1017 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT);
1018 // fold (shl 0, x) -> 0
1019 if (N0C && N0C->isNullValue())
1021 // fold (shl x, c >= size(x)) -> undef
1022 if (N1C && N1C->getValue() >= OpSizeInBits)
1023 return DAG.getNode(ISD::UNDEF, VT);
1024 // fold (shl x, 0) -> x
1025 if (N1C && N1C->isNullValue())
1027 // if (shl x, c) is known to be zero, return 0
1028 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1029 return DAG.getConstant(0, VT);
1030 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1031 if (N1C && N0.getOpcode() == ISD::SHL &&
1032 N0.getOperand(1).getOpcode() == ISD::Constant) {
1033 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1034 uint64_t c2 = N1C->getValue();
1035 if (c1 + c2 > OpSizeInBits)
1036 return DAG.getConstant(0, VT);
1037 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1038 DAG.getConstant(c1 + c2, N1.getValueType()));
1040 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1041 // (srl (and x, -1 << c1), c1-c2)
1042 if (N1C && N0.getOpcode() == ISD::SRL &&
1043 N0.getOperand(1).getOpcode() == ISD::Constant) {
1044 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1045 uint64_t c2 = N1C->getValue();
1046 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1047 DAG.getConstant(~0ULL << c1, VT));
1049 return DAG.getNode(ISD::SHL, VT, Mask,
1050 DAG.getConstant(c2-c1, N1.getValueType()));
1052 return DAG.getNode(ISD::SRL, VT, Mask,
1053 DAG.getConstant(c1-c2, N1.getValueType()));
1055 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1056 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1057 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1058 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1062 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1063 SDOperand N0 = N->getOperand(0);
1064 SDOperand N1 = N->getOperand(1);
1065 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1066 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1067 MVT::ValueType VT = N0.getValueType();
1068 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1070 // fold (sra c1, c2) -> c1>>c2
1072 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT);
1073 // fold (sra 0, x) -> 0
1074 if (N0C && N0C->isNullValue())
1076 // fold (sra -1, x) -> -1
1077 if (N0C && N0C->isAllOnesValue())
1079 // fold (sra x, c >= size(x)) -> undef
1080 if (N1C && N1C->getValue() >= OpSizeInBits)
1081 return DAG.getNode(ISD::UNDEF, VT);
1082 // fold (sra x, 0) -> x
1083 if (N1C && N1C->isNullValue())
1085 // If the sign bit is known to be zero, switch this to a SRL.
1086 if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
1087 return DAG.getNode(ISD::SRL, VT, N0, N1);
1091 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1092 SDOperand N0 = N->getOperand(0);
1093 SDOperand N1 = N->getOperand(1);
1094 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1095 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1096 MVT::ValueType VT = N0.getValueType();
1097 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1099 // fold (srl c1, c2) -> c1 >>u c2
1101 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT);
1102 // fold (srl 0, x) -> 0
1103 if (N0C && N0C->isNullValue())
1105 // fold (srl x, c >= size(x)) -> undef
1106 if (N1C && N1C->getValue() >= OpSizeInBits)
1107 return DAG.getNode(ISD::UNDEF, VT);
1108 // fold (srl x, 0) -> x
1109 if (N1C && N1C->isNullValue())
1111 // if (srl x, c) is known to be zero, return 0
1112 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1113 return DAG.getConstant(0, VT);
1114 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1115 if (N1C && N0.getOpcode() == ISD::SRL &&
1116 N0.getOperand(1).getOpcode() == ISD::Constant) {
1117 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1118 uint64_t c2 = N1C->getValue();
1119 if (c1 + c2 > OpSizeInBits)
1120 return DAG.getConstant(0, VT);
1121 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1122 DAG.getConstant(c1 + c2, N1.getValueType()));
1127 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1128 SDOperand N0 = N->getOperand(0);
1129 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1131 // fold (ctlz c1) -> c2
1133 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()),
1138 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1139 SDOperand N0 = N->getOperand(0);
1140 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1142 // fold (cttz c1) -> c2
1144 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()),
1149 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1150 SDOperand N0 = N->getOperand(0);
1151 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1153 // fold (ctpop c1) -> c2
1155 return DAG.getConstant(CountPopulation_64(N0C->getValue()),
1160 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1161 SDOperand N0 = N->getOperand(0);
1162 SDOperand N1 = N->getOperand(1);
1163 SDOperand N2 = N->getOperand(2);
1164 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1165 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1166 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1167 MVT::ValueType VT = N->getValueType(0);
1169 // fold select C, X, X -> X
1172 // fold select true, X, Y -> X
1173 if (N0C && !N0C->isNullValue())
1175 // fold select false, X, Y -> Y
1176 if (N0C && N0C->isNullValue())
1178 // fold select C, 1, X -> C | X
1179 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1180 return DAG.getNode(ISD::OR, VT, N0, N2);
1181 // fold select C, 0, X -> ~C & X
1182 // FIXME: this should check for C type == X type, not i1?
1183 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1184 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1185 WorkList.push_back(XORNode.Val);
1186 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1188 // fold select C, X, 1 -> ~C | X
1189 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1190 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1191 WorkList.push_back(XORNode.Val);
1192 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1194 // fold select C, X, 0 -> C & X
1195 // FIXME: this should check for C type == X type, not i1?
1196 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1197 return DAG.getNode(ISD::AND, VT, N0, N1);
1198 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1199 if (MVT::i1 == VT && N0 == N1)
1200 return DAG.getNode(ISD::OR, VT, N0, N2);
1201 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1202 if (MVT::i1 == VT && N0 == N2)
1203 return DAG.getNode(ISD::AND, VT, N0, N1);
1204 // fold selects based on a setcc into other things, such as min/max/abs
1205 if (N0.getOpcode() == ISD::SETCC)
1206 return SimplifySelect(N0, N1, N2);
1210 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1211 SDOperand N0 = N->getOperand(0);
1212 SDOperand N1 = N->getOperand(1);
1213 SDOperand N2 = N->getOperand(2);
1214 SDOperand N3 = N->getOperand(3);
1215 SDOperand N4 = N->getOperand(4);
1216 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1217 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1218 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1219 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1221 // Determine if the condition we're dealing with is constant
1222 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1223 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1225 // fold select_cc lhs, rhs, x, x, cc -> x
1228 // fold select_cc into other things, such as min/max/abs
1229 return SimplifySelectCC(N0, N1, N2, N3, CC);
1232 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1233 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1234 cast<CondCodeSDNode>(N->getOperand(2))->get());
1237 SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
1238 SDOperand LHSLo = N->getOperand(0);
1239 SDOperand RHSLo = N->getOperand(2);
1240 MVT::ValueType VT = LHSLo.getValueType();
1242 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo)
1243 if (MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1244 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1246 WorkList.push_back(Hi.Val);
1247 CombineTo(N, RHSLo, Hi);
1250 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo)
1251 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1252 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1254 WorkList.push_back(Hi.Val);
1255 CombineTo(N, LHSLo, Hi);
1261 SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) {
1262 SDOperand LHSLo = N->getOperand(0);
1263 SDOperand RHSLo = N->getOperand(2);
1264 MVT::ValueType VT = LHSLo.getValueType();
1266 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo)
1267 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) {
1268 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1),
1270 WorkList.push_back(Hi.Val);
1271 CombineTo(N, LHSLo, Hi);
1277 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1278 SDOperand N0 = N->getOperand(0);
1279 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1280 MVT::ValueType VT = N->getValueType(0);
1282 // fold (sext c1) -> c1
1284 return DAG.getConstant(N0C->getSignExtended(), VT);
1285 // fold (sext (sext x)) -> (sext x)
1286 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1287 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1288 // fold (sext (sextload x)) -> (sextload x)
1289 if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType())
1291 // fold (sext (load x)) -> (sextload x)
1292 if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) {
1293 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1294 N0.getOperand(1), N0.getOperand(2),
1296 WorkList.push_back(N);
1297 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1298 ExtLoad.getValue(1));
1304 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1305 SDOperand N0 = N->getOperand(0);
1306 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1307 MVT::ValueType VT = N->getValueType(0);
1309 // fold (zext c1) -> c1
1311 return DAG.getConstant(N0C->getValue(), VT);
1312 // fold (zext (zext x)) -> (zext x)
1313 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1314 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1318 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1319 SDOperand N0 = N->getOperand(0);
1320 SDOperand N1 = N->getOperand(1);
1321 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1322 MVT::ValueType VT = N->getValueType(0);
1323 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1324 unsigned EVTBits = MVT::getSizeInBits(EVT);
1326 // fold (sext_in_reg c1) -> c1
1328 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1329 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1331 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1332 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1333 cast<VTSDNode>(N0.getOperand(1))->getVT() < EVT) {
1336 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1337 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1338 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1339 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1341 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1342 if (N0.getOpcode() == ISD::AssertSext &&
1343 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1346 // fold (sext_in_reg (sextload x)) -> (sextload x)
1347 if (N0.getOpcode() == ISD::SEXTLOAD &&
1348 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1351 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1352 if (N0.getOpcode() == ISD::SETCC &&
1353 TLI.getSetCCResultContents() ==
1354 TargetLowering::ZeroOrNegativeOneSetCCResult)
1356 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1357 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI))
1358 return DAG.getNode(ISD::AND, N0.getValueType(), N0,
1359 DAG.getConstant(~0ULL >> (64-EVTBits), VT));
1360 // fold (sext_in_reg (srl x)) -> sra x
1361 if (N0.getOpcode() == ISD::SRL &&
1362 N0.getOperand(1).getOpcode() == ISD::Constant &&
1363 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1364 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1367 // fold (sext_inreg (extload x)) -> (sextload x)
1368 if (N0.getOpcode() == ISD::EXTLOAD &&
1369 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1370 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1371 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1372 N0.getOperand(1), N0.getOperand(2),
1374 WorkList.push_back(N);
1375 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1378 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1379 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.Val->hasNUsesOfValue(1, 0) &&
1380 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1381 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1382 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1383 N0.getOperand(1), N0.getOperand(2),
1385 WorkList.push_back(N);
1386 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1392 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1393 SDOperand N0 = N->getOperand(0);
1394 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1395 MVT::ValueType VT = N->getValueType(0);
1398 if (N0.getValueType() == N->getValueType(0))
1400 // fold (truncate c1) -> c1
1402 return DAG.getConstant(N0C->getValue(), VT);
1403 // fold (truncate (truncate x)) -> (truncate x)
1404 if (N0.getOpcode() == ISD::TRUNCATE)
1405 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1406 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1407 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1408 if (N0.getValueType() < VT)
1409 // if the source is smaller than the dest, we still need an extend
1410 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1411 else if (N0.getValueType() > VT)
1412 // if the source is larger than the dest, than we just need the truncate
1413 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1415 // if the source and dest are the same type, we can drop both the extend
1417 return N0.getOperand(0);
1419 // fold (truncate (load x)) -> (smaller load x)
1420 if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) {
1421 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1422 "Cannot truncate to larger type!");
1423 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1424 // For big endian targets, we need to add an offset to the pointer to load
1425 // the correct bytes. For little endian systems, we merely need to read
1426 // fewer bytes from the same pointer.
1428 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1429 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1430 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1431 DAG.getConstant(PtrOff, PtrType));
1432 WorkList.push_back(NewPtr.Val);
1433 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1434 WorkList.push_back(N);
1435 CombineTo(N0.Val, Load, Load.getValue(1));
1441 SDOperand DAGCombiner::visitFADD(SDNode *N) {
1442 SDOperand N0 = N->getOperand(0);
1443 SDOperand N1 = N->getOperand(1);
1444 MVT::ValueType VT = N->getValueType(0);
1446 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1447 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1448 // fold floating point (fadd c1, c2)
1449 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(),
1450 N->getValueType(0));
1452 // fold (A + (-B)) -> A-B
1453 if (N1.getOpcode() == ISD::FNEG)
1454 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1456 // fold ((-A) + B) -> B-A
1457 if (N0.getOpcode() == ISD::FNEG)
1458 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1463 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1464 SDOperand N0 = N->getOperand(0);
1465 SDOperand N1 = N->getOperand(1);
1466 MVT::ValueType VT = N->getValueType(0);
1468 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1469 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1470 // fold floating point (fsub c1, c2)
1471 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(),
1472 N->getValueType(0));
1474 // fold (A-(-B)) -> A+B
1475 if (N1.getOpcode() == ISD::FNEG)
1476 return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0));
1481 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1482 SDOperand N0 = N->getOperand(0);
1483 SDOperand N1 = N->getOperand(1);
1484 MVT::ValueType VT = N->getValueType(0);
1486 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1487 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1488 // fold floating point (fmul c1, c2)
1489 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(),
1490 N->getValueType(0));
1495 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1496 SDOperand N0 = N->getOperand(0);
1497 SDOperand N1 = N->getOperand(1);
1498 MVT::ValueType VT = N->getValueType(0);
1500 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1501 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1502 // fold floating point (fdiv c1, c2)
1503 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(),
1504 N->getValueType(0));
1509 SDOperand DAGCombiner::visitFREM(SDNode *N) {
1510 SDOperand N0 = N->getOperand(0);
1511 SDOperand N1 = N->getOperand(1);
1512 MVT::ValueType VT = N->getValueType(0);
1514 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1515 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1516 // fold floating point (frem c1, c2) -> fmod(c1, c2)
1517 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()),
1518 N->getValueType(0));
1524 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1525 SDOperand N0 = N->getOperand(0);
1526 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1528 // fold (sint_to_fp c1) -> c1fp
1530 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0));
1534 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1535 SDOperand N0 = N->getOperand(0);
1536 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1538 // fold (uint_to_fp c1) -> c1fp
1540 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0));
1544 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1545 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1547 // fold (fp_to_sint c1fp) -> c1
1549 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0));
1553 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1554 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1556 // fold (fp_to_uint c1fp) -> c1
1558 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0));
1562 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1563 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1565 // fold (fp_round c1fp) -> c1fp
1567 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1571 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1572 SDOperand N0 = N->getOperand(0);
1573 MVT::ValueType VT = N->getValueType(0);
1574 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1575 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1577 // fold (fp_round_inreg c1fp) -> c1fp
1579 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1580 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1585 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1586 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1588 // fold (fp_extend c1fp) -> c1fp
1590 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1594 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1595 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1596 // fold (neg c1) -> -c1
1598 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0));
1599 // fold (neg (sub x, y)) -> (sub y, x)
1600 if (N->getOperand(0).getOpcode() == ISD::SUB)
1601 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1),
1603 // fold (neg (neg x)) -> x
1604 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1605 return N->getOperand(0).getOperand(0);
1609 SDOperand DAGCombiner::visitFABS(SDNode *N) {
1610 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1611 // fold (fabs c1) -> fabs(c1)
1613 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0));
1614 // fold (fabs (fabs x)) -> (fabs x)
1615 if (N->getOperand(0).getOpcode() == ISD::FABS)
1616 return N->getOperand(0);
1617 // fold (fabs (fneg x)) -> (fabs x)
1618 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1619 return DAG.getNode(ISD::FABS, N->getValueType(0),
1620 N->getOperand(0).getOperand(0));
1624 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
1625 SDOperand Chain = N->getOperand(0);
1626 SDOperand N1 = N->getOperand(1);
1627 SDOperand N2 = N->getOperand(2);
1628 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1630 // never taken branch, fold to chain
1631 if (N1C && N1C->isNullValue())
1633 // unconditional branch
1634 if (N1C && N1C->getValue() == 1)
1635 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1639 SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
1640 SDOperand Chain = N->getOperand(0);
1641 SDOperand N1 = N->getOperand(1);
1642 SDOperand N2 = N->getOperand(2);
1643 SDOperand N3 = N->getOperand(3);
1644 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1646 // unconditional branch to true mbb
1647 if (N1C && N1C->getValue() == 1)
1648 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1649 // unconditional branch to false mbb
1650 if (N1C && N1C->isNullValue())
1651 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
1655 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
1657 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
1658 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
1659 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
1661 // Use SimplifySetCC to simplify SETCC's.
1662 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
1663 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
1665 // fold br_cc true, dest -> br dest (unconditional branch)
1666 if (SCCC && SCCC->getValue())
1667 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
1669 // fold br_cc false, dest -> unconditional fall through
1670 if (SCCC && SCCC->isNullValue())
1671 return N->getOperand(0);
1672 // fold to a simpler setcc
1673 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
1674 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
1675 Simp.getOperand(2), Simp.getOperand(0),
1676 Simp.getOperand(1), N->getOperand(4));
1680 SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
1681 SDOperand Chain = N->getOperand(0);
1682 SDOperand CCN = N->getOperand(1);
1683 SDOperand LHS = N->getOperand(2);
1684 SDOperand RHS = N->getOperand(3);
1685 SDOperand N4 = N->getOperand(4);
1686 SDOperand N5 = N->getOperand(5);
1688 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
1689 cast<CondCodeSDNode>(CCN)->get(), false);
1690 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1692 // fold select_cc lhs, rhs, x, x, cc -> x
1694 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
1695 // fold select_cc true, x, y -> x
1696 if (SCCC && SCCC->getValue())
1697 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
1698 // fold select_cc false, x, y -> y
1699 if (SCCC && SCCC->isNullValue())
1700 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
1701 // fold to a simpler setcc
1702 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1703 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0),
1704 SCC.getOperand(1), N4, N5);
1708 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
1709 SDOperand Chain = N->getOperand(0);
1710 SDOperand Ptr = N->getOperand(1);
1711 SDOperand SrcValue = N->getOperand(2);
1713 // If this load is directly stored, replace the load value with the stored
1715 // TODO: Handle store large -> read small portion.
1716 // TODO: Handle TRUNCSTORE/EXTLOAD
1717 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
1718 Chain.getOperand(1).getValueType() == N->getValueType(0))
1719 return CombineTo(N, Chain.getOperand(1), Chain);
1724 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
1725 SDOperand Chain = N->getOperand(0);
1726 SDOperand Value = N->getOperand(1);
1727 SDOperand Ptr = N->getOperand(2);
1728 SDOperand SrcValue = N->getOperand(3);
1730 // If this is a store that kills a previous store, remove the previous store.
1731 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
1732 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */) {
1733 // Create a new store of Value that replaces both stores.
1734 SDNode *PrevStore = Chain.Val;
1735 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
1737 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
1738 PrevStore->getOperand(0), Value, Ptr,
1740 CombineTo(N, NewStore); // Nuke this store.
1741 CombineTo(PrevStore, NewStore); // Nuke the previous store.
1742 return SDOperand(N, 0);
1748 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
1749 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
1751 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
1752 cast<CondCodeSDNode>(N0.getOperand(2))->get());
1753 // If we got a simplified select_cc node back from SimplifySelectCC, then
1754 // break it down into a new SETCC node, and a new SELECT node, and then return
1755 // the SELECT node, since we were called with a SELECT node.
1757 // Check to see if we got a select_cc back (to turn into setcc/select).
1758 // Otherwise, just return whatever node we got back, like fabs.
1759 if (SCC.getOpcode() == ISD::SELECT_CC) {
1760 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
1761 SCC.getOperand(0), SCC.getOperand(1),
1763 WorkList.push_back(SETCC.Val);
1764 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
1765 SCC.getOperand(3), SETCC);
1772 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
1773 SDOperand N2, SDOperand N3,
1776 MVT::ValueType VT = N2.getValueType();
1777 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1778 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1779 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
1780 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
1782 // Determine if the condition we're dealing with is constant
1783 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1784 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1786 // fold select_cc true, x, y -> x
1787 if (SCCC && SCCC->getValue())
1789 // fold select_cc false, x, y -> y
1790 if (SCCC && SCCC->getValue() == 0)
1793 // Check to see if we can simplify the select into an fabs node
1794 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1795 // Allow either -0.0 or 0.0
1796 if (CFP->getValue() == 0.0) {
1797 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
1798 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
1799 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
1800 N2 == N3.getOperand(0))
1801 return DAG.getNode(ISD::FABS, VT, N0);
1803 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
1804 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
1805 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
1806 N2.getOperand(0) == N3)
1807 return DAG.getNode(ISD::FABS, VT, N3);
1811 // Check to see if we can perform the "gzip trick", transforming
1812 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
1813 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
1814 MVT::isInteger(N0.getValueType()) &&
1815 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
1816 MVT::ValueType XType = N0.getValueType();
1817 MVT::ValueType AType = N2.getValueType();
1818 if (XType >= AType) {
1819 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
1820 // single-bit constant.
1821 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
1822 unsigned ShCtV = Log2_64(N2C->getValue());
1823 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
1824 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
1825 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
1826 WorkList.push_back(Shift.Val);
1827 if (XType > AType) {
1828 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
1829 WorkList.push_back(Shift.Val);
1831 return DAG.getNode(ISD::AND, AType, Shift, N2);
1833 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
1834 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1835 TLI.getShiftAmountTy()));
1836 WorkList.push_back(Shift.Val);
1837 if (XType > AType) {
1838 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
1839 WorkList.push_back(Shift.Val);
1841 return DAG.getNode(ISD::AND, AType, Shift, N2);
1845 // fold select C, 16, 0 -> shl C, 4
1846 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
1847 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
1848 // Get a SetCC of the condition
1849 // FIXME: Should probably make sure that setcc is legal if we ever have a
1850 // target where it isn't.
1851 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
1852 WorkList.push_back(SCC.Val);
1853 // cast from setcc result type to select result type
1855 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
1857 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
1858 WorkList.push_back(Temp.Val);
1859 // shl setcc result by log2 n2c
1860 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
1861 DAG.getConstant(Log2_64(N2C->getValue()),
1862 TLI.getShiftAmountTy()));
1865 // Check to see if this is the equivalent of setcc
1866 // FIXME: Turn all of these into setcc if setcc if setcc is legal
1867 // otherwise, go ahead with the folds.
1868 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
1869 MVT::ValueType XType = N0.getValueType();
1870 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
1871 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
1872 if (Res.getValueType() != VT)
1873 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
1877 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
1878 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
1879 TLI.isOperationLegal(ISD::CTLZ, XType)) {
1880 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
1881 return DAG.getNode(ISD::SRL, XType, Ctlz,
1882 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
1883 TLI.getShiftAmountTy()));
1885 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
1886 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
1887 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
1889 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
1890 DAG.getConstant(~0ULL, XType));
1891 return DAG.getNode(ISD::SRL, XType,
1892 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
1893 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1894 TLI.getShiftAmountTy()));
1896 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
1897 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
1898 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
1899 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1900 TLI.getShiftAmountTy()));
1901 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
1905 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
1906 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
1907 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
1908 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
1909 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
1910 MVT::ValueType XType = N0.getValueType();
1911 if (SubC->isNullValue() && MVT::isInteger(XType)) {
1912 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
1913 DAG.getConstant(MVT::getSizeInBits(XType)-1,
1914 TLI.getShiftAmountTy()));
1915 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
1916 WorkList.push_back(Shift.Val);
1917 WorkList.push_back(Add.Val);
1918 return DAG.getNode(ISD::XOR, XType, Add, Shift);
1926 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
1927 SDOperand N1, ISD::CondCode Cond,
1928 bool foldBooleans) {
1929 // These setcc operations always fold.
1933 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1935 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1938 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
1939 uint64_t C1 = N1C->getValue();
1940 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
1941 uint64_t C0 = N0C->getValue();
1943 // Sign extend the operands if required
1944 if (ISD::isSignedIntSetCC(Cond)) {
1945 C0 = N0C->getSignExtended();
1946 C1 = N1C->getSignExtended();
1950 default: assert(0 && "Unknown integer setcc!");
1951 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
1952 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
1953 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
1954 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
1955 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
1956 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
1957 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
1958 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
1959 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
1960 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
1963 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1964 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1965 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
1967 // If the comparison constant has bits in the upper part, the
1968 // zero-extended value could never match.
1969 if (C1 & (~0ULL << InSize)) {
1970 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
1974 case ISD::SETEQ: return DAG.getConstant(0, VT);
1977 case ISD::SETNE: return DAG.getConstant(1, VT);
1980 // True if the sign bit of C1 is set.
1981 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
1984 // True if the sign bit of C1 isn't set.
1985 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
1991 // Otherwise, we can perform the comparison with the low bits.
1999 return DAG.getSetCC(VT, N0.getOperand(0),
2000 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
2003 break; // todo, be more careful with signed comparisons
2005 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2006 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2007 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2008 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
2009 MVT::ValueType ExtDstTy = N0.getValueType();
2010 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
2012 // If the extended part has any inconsistent bits, it cannot ever
2013 // compare equal. In other words, they have to be all ones or all
2016 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
2017 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
2018 return DAG.getConstant(Cond == ISD::SETNE, VT);
2021 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
2022 if (Op0Ty == ExtSrcTy) {
2023 ZextOp = N0.getOperand(0);
2025 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
2026 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
2027 DAG.getConstant(Imm, Op0Ty));
2029 WorkList.push_back(ZextOp.Val);
2030 // Otherwise, make this a use of a zext.
2031 return DAG.getSetCC(VT, ZextOp,
2032 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
2037 uint64_t MinVal, MaxVal;
2038 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
2039 if (ISD::isSignedIntSetCC(Cond)) {
2040 MinVal = 1ULL << (OperandBitSize-1);
2041 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
2042 MaxVal = ~0ULL >> (65-OperandBitSize);
2047 MaxVal = ~0ULL >> (64-OperandBitSize);
2050 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2051 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2052 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2053 --C1; // X >= C0 --> X > (C0-1)
2054 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2055 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2058 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2059 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2060 ++C1; // X <= C0 --> X < (C0+1)
2061 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2062 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2065 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2066 return DAG.getConstant(0, VT); // X < MIN --> false
2068 // Canonicalize setgt X, Min --> setne X, Min
2069 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2070 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2072 // If we have setult X, 1, turn it into seteq X, 0
2073 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2074 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
2076 // If we have setugt X, Max-1, turn it into seteq X, Max
2077 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2078 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
2081 // If we have "setcc X, C0", check to see if we can shrink the immediate
2084 // SETUGT X, SINTMAX -> SETLT X, 0
2085 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
2086 C1 == (~0ULL >> (65-OperandBitSize)))
2087 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
2090 // FIXME: Implement the rest of these.
2092 // Fold bit comparisons when we can.
2093 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2094 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
2095 if (ConstantSDNode *AndRHS =
2096 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2097 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2098 // Perform the xform if the AND RHS is a single bit.
2099 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
2100 return DAG.getNode(ISD::SRL, VT, N0,
2101 DAG.getConstant(Log2_64(AndRHS->getValue()),
2102 TLI.getShiftAmountTy()));
2104 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
2105 // (X & 8) == 8 --> (X & 8) >> 3
2106 // Perform the xform if C1 is a single bit.
2107 if ((C1 & (C1-1)) == 0) {
2108 return DAG.getNode(ISD::SRL, VT, N0,
2109 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
2114 } else if (isa<ConstantSDNode>(N0.Val)) {
2115 // Ensure that the constant occurs on the RHS.
2116 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2119 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
2120 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
2121 double C0 = N0C->getValue(), C1 = N1C->getValue();
2124 default: break; // FIXME: Implement the rest of these!
2125 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2126 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2127 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
2128 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
2129 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
2130 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
2133 // Ensure that the constant occurs on the RHS.
2134 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2138 // We can always fold X == Y for integer setcc's.
2139 if (MVT::isInteger(N0.getValueType()))
2140 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2141 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2142 if (UOF == 2) // FP operators that are undefined on NaNs.
2143 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2144 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2145 return DAG.getConstant(UOF, VT);
2146 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2147 // if it is not already.
2148 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO;
2149 if (NewCond != Cond)
2150 return DAG.getSetCC(VT, N0, N1, NewCond);
2153 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2154 MVT::isInteger(N0.getValueType())) {
2155 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2156 N0.getOpcode() == ISD::XOR) {
2157 // Simplify (X+Y) == (X+Z) --> Y == Z
2158 if (N0.getOpcode() == N1.getOpcode()) {
2159 if (N0.getOperand(0) == N1.getOperand(0))
2160 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2161 if (N0.getOperand(1) == N1.getOperand(1))
2162 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2163 if (isCommutativeBinOp(N0.getOpcode())) {
2164 // If X op Y == Y op X, try other combinations.
2165 if (N0.getOperand(0) == N1.getOperand(1))
2166 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2167 if (N0.getOperand(1) == N1.getOperand(0))
2168 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2172 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes.
2173 if (N0.getOpcode() == ISD::XOR)
2174 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2175 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2176 // If we know that all of the inverted bits are zero, don't bother
2177 // performing the inversion.
2178 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI))
2179 return DAG.getSetCC(VT, N0.getOperand(0),
2180 DAG.getConstant(XORC->getValue()^RHSC->getValue(),
2181 N0.getValueType()), Cond);
2184 // Simplify (X+Z) == X --> Z == 0
2185 if (N0.getOperand(0) == N1)
2186 return DAG.getSetCC(VT, N0.getOperand(1),
2187 DAG.getConstant(0, N0.getValueType()), Cond);
2188 if (N0.getOperand(1) == N1) {
2189 if (isCommutativeBinOp(N0.getOpcode()))
2190 return DAG.getSetCC(VT, N0.getOperand(0),
2191 DAG.getConstant(0, N0.getValueType()), Cond);
2193 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2194 // (Z-X) == X --> Z == X<<1
2195 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2197 DAG.getConstant(1,TLI.getShiftAmountTy()));
2198 WorkList.push_back(SH.Val);
2199 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2204 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2205 N1.getOpcode() == ISD::XOR) {
2206 // Simplify X == (X+Z) --> Z == 0
2207 if (N1.getOperand(0) == N0) {
2208 return DAG.getSetCC(VT, N1.getOperand(1),
2209 DAG.getConstant(0, N1.getValueType()), Cond);
2210 } else if (N1.getOperand(1) == N0) {
2211 if (isCommutativeBinOp(N1.getOpcode())) {
2212 return DAG.getSetCC(VT, N1.getOperand(0),
2213 DAG.getConstant(0, N1.getValueType()), Cond);
2215 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2216 // X == (Z-X) --> X<<1 == Z
2217 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2218 DAG.getConstant(1,TLI.getShiftAmountTy()));
2219 WorkList.push_back(SH.Val);
2220 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2226 // Fold away ALL boolean setcc's.
2228 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2230 default: assert(0 && "Unknown integer setcc!");
2231 case ISD::SETEQ: // X == Y -> (X^Y)^1
2232 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2233 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2234 WorkList.push_back(Temp.Val);
2236 case ISD::SETNE: // X != Y --> (X^Y)
2237 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2239 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
2240 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
2241 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2242 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2243 WorkList.push_back(Temp.Val);
2245 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
2246 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
2247 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2248 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2249 WorkList.push_back(Temp.Val);
2251 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
2252 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
2253 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2254 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2255 WorkList.push_back(Temp.Val);
2257 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
2258 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
2259 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2260 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2263 if (VT != MVT::i1) {
2264 WorkList.push_back(N0.Val);
2265 // FIXME: If running after legalize, we probably can't do this.
2266 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2271 // Could not fold it.
2275 // SelectionDAG::Combine - This is the entry point for the file.
2277 void SelectionDAG::Combine(bool RunningAfterLegalize) {
2278 /// run - This is the main entry point to this class.
2280 DAGCombiner(*this).Run(RunningAfterLegalize);