1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
43 #define DEBUG_TYPE "dagcombine"
45 STATISTIC(NodesCombined , "Number of dag nodes combined");
46 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
47 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
48 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
50 STATISTIC(SlicedLoads, "Number of load sliced");
54 CombinerAA("combiner-alias-analysis", cl::Hidden,
55 cl::desc("Enable DAG combiner alias-analysis heuristics"));
58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
59 cl::desc("Enable DAG combiner's use of IR alias analysis"));
62 UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
63 cl::desc("Enable DAG combiner's use of TBAA"));
66 static cl::opt<std::string>
67 CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
68 cl::desc("Only use DAG-combiner alias analysis in this"
72 /// Hidden option to stress test load slicing, i.e., when this option
73 /// is enabled, load slicing bypasses most of its profitability guards.
75 StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
76 cl::desc("Bypass the profitability model of load "
81 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
82 cl::desc("DAG combiner may split indexing from loads"));
84 //------------------------------ DAGCombiner ---------------------------------//
88 const TargetLowering &TLI;
90 CodeGenOpt::Level OptLevel;
95 /// \brief Worklist of all of the nodes that need to be simplified.
97 /// This must behave as a stack -- new nodes to process are pushed onto the
98 /// back and when processing we pop off of the back.
100 /// The worklist will not contain duplicates but may contain null entries
101 /// due to nodes being deleted from the underlying DAG.
102 SmallVector<SDNode *, 64> Worklist;
104 /// \brief Mapping from an SDNode to its position on the worklist.
106 /// This is used to find and remove nodes from the worklist (by nulling
107 /// them) when they are deleted from the underlying DAG. It relies on
108 /// stable indices of nodes within the worklist.
109 DenseMap<SDNode *, unsigned> WorklistMap;
111 /// \brief Set of nodes which have been combined (at least once).
113 /// This is used to allow us to reliably add any operands of a DAG node
114 /// which have not yet been combined to the worklist.
115 SmallPtrSet<SDNode *, 64> CombinedNodes;
117 // AA - Used for DAG load/store alias analysis.
120 /// When an instruction is simplified, add all users of the instruction to
121 /// the work lists because they might get more simplified now.
122 void AddUsersToWorklist(SDNode *N) {
123 for (SDNode *Node : N->uses())
127 /// Call the node-specific routine that folds each particular type of node.
128 SDValue visit(SDNode *N);
131 /// Add to the worklist making sure its instance is at the back (next to be
133 void AddToWorklist(SDNode *N) {
134 // Skip handle nodes as they can't usefully be combined and confuse the
135 // zero-use deletion strategy.
136 if (N->getOpcode() == ISD::HANDLENODE)
139 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
140 Worklist.push_back(N);
143 /// Remove all instances of N from the worklist.
144 void removeFromWorklist(SDNode *N) {
145 CombinedNodes.erase(N);
147 auto It = WorklistMap.find(N);
148 if (It == WorklistMap.end())
149 return; // Not in the worklist.
151 // Null out the entry rather than erasing it to avoid a linear operation.
152 Worklist[It->second] = nullptr;
153 WorklistMap.erase(It);
156 void deleteAndRecombine(SDNode *N);
157 bool recursivelyDeleteUnusedNodes(SDNode *N);
159 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
162 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
163 return CombineTo(N, &Res, 1, AddTo);
166 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
168 SDValue To[] = { Res0, Res1 };
169 return CombineTo(N, To, 2, AddTo);
172 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
176 /// Check the specified integer node value to see if it can be simplified or
177 /// if things it uses can be simplified by bit propagation.
178 /// If so, return true.
179 bool SimplifyDemandedBits(SDValue Op) {
180 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
181 APInt Demanded = APInt::getAllOnesValue(BitWidth);
182 return SimplifyDemandedBits(Op, Demanded);
185 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
187 bool CombineToPreIndexedLoadStore(SDNode *N);
188 bool CombineToPostIndexedLoadStore(SDNode *N);
189 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
190 bool SliceUpLoad(SDNode *N);
192 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
195 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
196 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
197 /// \param EltNo index of the vector element to load.
198 /// \param OriginalLoad load that EVE came from to be replaced.
199 /// \returns EVE on success SDValue() on failure.
200 SDValue ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
201 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad);
202 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
203 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
204 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
205 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
206 SDValue PromoteIntBinOp(SDValue Op);
207 SDValue PromoteIntShiftOp(SDValue Op);
208 SDValue PromoteExtend(SDValue Op);
209 bool PromoteLoad(SDValue Op);
211 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
212 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
213 ISD::NodeType ExtType);
215 /// Call the node-specific routine that knows how to fold each
216 /// particular type of node. If that doesn't do anything, try the
217 /// target-specific DAG combines.
218 SDValue combine(SDNode *N);
220 // Visitation implementation - Implement dag node combining for different
221 // node types. The semantics are as follows:
223 // SDValue.getNode() == 0 - No change was made
224 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
225 // otherwise - N should be replaced by the returned Operand.
227 SDValue visitTokenFactor(SDNode *N);
228 SDValue visitMERGE_VALUES(SDNode *N);
229 SDValue visitADD(SDNode *N);
230 SDValue visitSUB(SDNode *N);
231 SDValue visitADDC(SDNode *N);
232 SDValue visitSUBC(SDNode *N);
233 SDValue visitADDE(SDNode *N);
234 SDValue visitSUBE(SDNode *N);
235 SDValue visitMUL(SDNode *N);
236 SDValue visitSDIV(SDNode *N);
237 SDValue visitUDIV(SDNode *N);
238 SDValue visitSREM(SDNode *N);
239 SDValue visitUREM(SDNode *N);
240 SDValue visitMULHU(SDNode *N);
241 SDValue visitMULHS(SDNode *N);
242 SDValue visitSMUL_LOHI(SDNode *N);
243 SDValue visitUMUL_LOHI(SDNode *N);
244 SDValue visitSMULO(SDNode *N);
245 SDValue visitUMULO(SDNode *N);
246 SDValue visitSDIVREM(SDNode *N);
247 SDValue visitUDIVREM(SDNode *N);
248 SDValue visitAND(SDNode *N);
249 SDValue visitOR(SDNode *N);
250 SDValue visitXOR(SDNode *N);
251 SDValue SimplifyVBinOp(SDNode *N);
252 SDValue SimplifyVUnaryOp(SDNode *N);
253 SDValue visitSHL(SDNode *N);
254 SDValue visitSRA(SDNode *N);
255 SDValue visitSRL(SDNode *N);
256 SDValue visitRotate(SDNode *N);
257 SDValue visitCTLZ(SDNode *N);
258 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
259 SDValue visitCTTZ(SDNode *N);
260 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
261 SDValue visitCTPOP(SDNode *N);
262 SDValue visitSELECT(SDNode *N);
263 SDValue visitVSELECT(SDNode *N);
264 SDValue visitSELECT_CC(SDNode *N);
265 SDValue visitSETCC(SDNode *N);
266 SDValue visitSIGN_EXTEND(SDNode *N);
267 SDValue visitZERO_EXTEND(SDNode *N);
268 SDValue visitANY_EXTEND(SDNode *N);
269 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
270 SDValue visitTRUNCATE(SDNode *N);
271 SDValue visitBITCAST(SDNode *N);
272 SDValue visitBUILD_PAIR(SDNode *N);
273 SDValue visitFADD(SDNode *N);
274 SDValue visitFSUB(SDNode *N);
275 SDValue visitFMUL(SDNode *N);
276 SDValue visitFMA(SDNode *N);
277 SDValue visitFDIV(SDNode *N);
278 SDValue visitFREM(SDNode *N);
279 SDValue visitFCOPYSIGN(SDNode *N);
280 SDValue visitSINT_TO_FP(SDNode *N);
281 SDValue visitUINT_TO_FP(SDNode *N);
282 SDValue visitFP_TO_SINT(SDNode *N);
283 SDValue visitFP_TO_UINT(SDNode *N);
284 SDValue visitFP_ROUND(SDNode *N);
285 SDValue visitFP_ROUND_INREG(SDNode *N);
286 SDValue visitFP_EXTEND(SDNode *N);
287 SDValue visitFNEG(SDNode *N);
288 SDValue visitFABS(SDNode *N);
289 SDValue visitFCEIL(SDNode *N);
290 SDValue visitFTRUNC(SDNode *N);
291 SDValue visitFFLOOR(SDNode *N);
292 SDValue visitBRCOND(SDNode *N);
293 SDValue visitBR_CC(SDNode *N);
294 SDValue visitLOAD(SDNode *N);
295 SDValue visitSTORE(SDNode *N);
296 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
297 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
298 SDValue visitBUILD_VECTOR(SDNode *N);
299 SDValue visitCONCAT_VECTORS(SDNode *N);
300 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
301 SDValue visitVECTOR_SHUFFLE(SDNode *N);
302 SDValue visitINSERT_SUBVECTOR(SDNode *N);
304 SDValue XformToShuffleWithZero(SDNode *N);
305 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS);
307 SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
309 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
310 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
311 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
312 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
313 SDValue N3, ISD::CondCode CC,
314 bool NotExtCompare = false);
315 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
316 SDLoc DL, bool foldBooleans = true);
318 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
320 bool isOneUseSetCC(SDValue N) const;
322 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
324 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
325 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
326 SDValue BuildSDIV(SDNode *N);
327 SDValue BuildSDIVPow2(SDNode *N);
328 SDValue BuildUDIV(SDNode *N);
329 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
330 bool DemandHighBits = true);
331 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
332 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
333 SDValue InnerPos, SDValue InnerNeg,
334 unsigned PosOpcode, unsigned NegOpcode,
336 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL);
337 SDValue ReduceLoadWidth(SDNode *N);
338 SDValue ReduceLoadOpStoreWidth(SDNode *N);
339 SDValue TransformFPLoadStorePair(SDNode *N);
340 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
341 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
343 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
345 /// Walk up chain skipping non-aliasing memory nodes,
346 /// looking for aliasing nodes and adding them to the Aliases vector.
347 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
348 SmallVectorImpl<SDValue> &Aliases);
350 /// Return true if there is any possibility that the two addresses overlap.
351 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const;
353 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
354 /// chain (aliasing node.)
355 SDValue FindBetterChain(SDNode *N, SDValue Chain);
357 /// Merge consecutive store operations into a wide store.
358 /// This optimization uses wide integers or vectors when possible.
359 /// \return True if some memory operations were changed.
360 bool MergeConsecutiveStores(StoreSDNode *N);
362 /// \brief Try to transform a truncation where C is a constant:
363 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
365 /// \p N needs to be a truncation and its first operand an AND. Other
366 /// requirements are checked by the function (e.g. that trunc is
367 /// single-use) and if missed an empty SDValue is returned.
368 SDValue distributeTruncateThroughAnd(SDNode *N);
371 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
372 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
373 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {
374 AttributeSet FnAttrs =
375 DAG.getMachineFunction().getFunction()->getAttributes();
377 FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
378 Attribute::OptimizeForSize) ||
379 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
382 /// Runs the dag combiner on all nodes in the work list
383 void Run(CombineLevel AtLevel);
385 SelectionDAG &getDAG() const { return DAG; }
387 /// Returns a type large enough to hold any valid shift amount - before type
388 /// legalization these can be huge.
389 EVT getShiftAmountTy(EVT LHSTy) {
390 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
391 if (LHSTy.isVector())
393 return LegalTypes ? TLI.getScalarShiftAmountTy(LHSTy)
394 : TLI.getPointerTy();
397 /// This method returns true if we are running before type legalization or
398 /// if the specified VT is legal.
399 bool isTypeLegal(const EVT &VT) {
400 if (!LegalTypes) return true;
401 return TLI.isTypeLegal(VT);
404 /// Convenience wrapper around TargetLowering::getSetCCResultType
405 EVT getSetCCResultType(EVT VT) const {
406 return TLI.getSetCCResultType(*DAG.getContext(), VT);
413 /// This class is a DAGUpdateListener that removes any deleted
414 /// nodes from the worklist.
415 class WorklistRemover : public SelectionDAG::DAGUpdateListener {
418 explicit WorklistRemover(DAGCombiner &dc)
419 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
421 void NodeDeleted(SDNode *N, SDNode *E) override {
422 DC.removeFromWorklist(N);
427 //===----------------------------------------------------------------------===//
428 // TargetLowering::DAGCombinerInfo implementation
429 //===----------------------------------------------------------------------===//
431 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
432 ((DAGCombiner*)DC)->AddToWorklist(N);
435 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
436 ((DAGCombiner*)DC)->removeFromWorklist(N);
439 SDValue TargetLowering::DAGCombinerInfo::
440 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
441 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
444 SDValue TargetLowering::DAGCombinerInfo::
445 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
446 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
450 SDValue TargetLowering::DAGCombinerInfo::
451 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
452 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
455 void TargetLowering::DAGCombinerInfo::
456 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
457 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
460 //===----------------------------------------------------------------------===//
462 //===----------------------------------------------------------------------===//
464 void DAGCombiner::deleteAndRecombine(SDNode *N) {
465 removeFromWorklist(N);
467 // If the operands of this node are only used by the node, they will now be
468 // dead. Make sure to re-visit them and recursively delete dead nodes.
469 for (const SDValue &Op : N->ops())
470 // For an operand generating multiple values, one of the values may
471 // become dead allowing further simplification (e.g. split index
472 // arithmetic from an indexed load).
473 if (Op->hasOneUse() || Op->getNumValues() > 1)
474 AddToWorklist(Op.getNode());
479 /// Return 1 if we can compute the negated form of the specified expression for
480 /// the same cost as the expression itself, or 2 if we can compute the negated
481 /// form more cheaply than the expression itself.
482 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
483 const TargetLowering &TLI,
484 const TargetOptions *Options,
485 unsigned Depth = 0) {
486 // fneg is removable even if it has multiple uses.
487 if (Op.getOpcode() == ISD::FNEG) return 2;
489 // Don't allow anything with multiple uses.
490 if (!Op.hasOneUse()) return 0;
492 // Don't recurse exponentially.
493 if (Depth > 6) return 0;
495 switch (Op.getOpcode()) {
496 default: return false;
497 case ISD::ConstantFP:
498 // Don't invert constant FP values after legalize. The negated constant
499 // isn't necessarily legal.
500 return LegalOperations ? 0 : 1;
502 // FIXME: determine better conditions for this xform.
503 if (!Options->UnsafeFPMath) return 0;
505 // After operation legalization, it might not be legal to create new FSUBs.
506 if (LegalOperations &&
507 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
510 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
511 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
514 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
515 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
518 // We can't turn -(A-B) into B-A when we honor signed zeros.
519 if (!Options->UnsafeFPMath) return 0;
521 // fold (fneg (fsub A, B)) -> (fsub B, A)
526 if (Options->HonorSignDependentRoundingFPMath()) return 0;
528 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
529 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
533 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
539 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
544 /// If isNegatibleForFree returns true, return the newly negated expression.
545 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
546 bool LegalOperations, unsigned Depth = 0) {
547 const TargetOptions &Options = DAG.getTarget().Options;
548 // fneg is removable even if it has multiple uses.
549 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
551 // Don't allow anything with multiple uses.
552 assert(Op.hasOneUse() && "Unknown reuse!");
554 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
555 switch (Op.getOpcode()) {
556 default: llvm_unreachable("Unknown code");
557 case ISD::ConstantFP: {
558 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
560 return DAG.getConstantFP(V, Op.getValueType());
563 // FIXME: determine better conditions for this xform.
564 assert(Options.UnsafeFPMath);
566 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
567 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
568 DAG.getTargetLoweringInfo(), &Options, Depth+1))
569 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
570 GetNegatedExpression(Op.getOperand(0), DAG,
571 LegalOperations, Depth+1),
573 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
574 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
575 GetNegatedExpression(Op.getOperand(1), DAG,
576 LegalOperations, Depth+1),
579 // We can't turn -(A-B) into B-A when we honor signed zeros.
580 assert(Options.UnsafeFPMath);
582 // fold (fneg (fsub 0, B)) -> B
583 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
584 if (N0CFP->getValueAPF().isZero())
585 return Op.getOperand(1);
587 // fold (fneg (fsub A, B)) -> (fsub B, A)
588 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
589 Op.getOperand(1), Op.getOperand(0));
593 assert(!Options.HonorSignDependentRoundingFPMath());
595 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
596 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
597 DAG.getTargetLoweringInfo(), &Options, Depth+1))
598 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
599 GetNegatedExpression(Op.getOperand(0), DAG,
600 LegalOperations, Depth+1),
603 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
604 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
606 GetNegatedExpression(Op.getOperand(1), DAG,
607 LegalOperations, Depth+1));
611 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
612 GetNegatedExpression(Op.getOperand(0), DAG,
613 LegalOperations, Depth+1));
615 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
616 GetNegatedExpression(Op.getOperand(0), DAG,
617 LegalOperations, Depth+1),
622 // Return true if this node is a setcc, or is a select_cc
623 // that selects between the target values used for true and false, making it
624 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
625 // the appropriate nodes based on the type of node we are checking. This
626 // simplifies life a bit for the callers.
627 bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
629 if (N.getOpcode() == ISD::SETCC) {
630 LHS = N.getOperand(0);
631 RHS = N.getOperand(1);
632 CC = N.getOperand(2);
636 if (N.getOpcode() != ISD::SELECT_CC ||
637 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
638 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
641 LHS = N.getOperand(0);
642 RHS = N.getOperand(1);
643 CC = N.getOperand(4);
647 /// Return true if this is a SetCC-equivalent operation with only one use.
648 /// If this is true, it allows the users to invert the operation for free when
649 /// it is profitable to do so.
650 bool DAGCombiner::isOneUseSetCC(SDValue N) const {
652 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
657 /// Returns true if N is a BUILD_VECTOR node whose
658 /// elements are all the same constant or undefined.
659 static bool isConstantSplatVector(SDNode *N, APInt& SplatValue) {
660 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(N);
665 unsigned SplatBitSize;
667 EVT EltVT = N->getValueType(0).getVectorElementType();
668 return (C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
670 EltVT.getSizeInBits() >= SplatBitSize);
673 // \brief Returns the SDNode if it is a constant BuildVector or constant.
674 static SDNode *isConstantBuildVectorOrConstantInt(SDValue N) {
675 if (isa<ConstantSDNode>(N))
677 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
678 if (BV && BV->isConstant())
683 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
685 static ConstantSDNode *isConstOrConstSplat(SDValue N) {
686 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
689 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
690 BitVector UndefElements;
691 ConstantSDNode *CN = BV->getConstantSplatNode(&UndefElements);
693 // BuildVectors can truncate their operands. Ignore that case here.
694 // FIXME: We blindly ignore splats which include undef which is overly
696 if (CN && UndefElements.none() &&
697 CN->getValueType(0) == N.getValueType().getScalarType())
704 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
706 static ConstantFPSDNode *isConstOrConstSplatFP(SDValue N) {
707 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
710 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
711 BitVector UndefElements;
712 ConstantFPSDNode *CN = BV->getConstantFPSplatNode(&UndefElements);
714 if (CN && UndefElements.none())
721 SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL,
722 SDValue N0, SDValue N1) {
723 EVT VT = N0.getValueType();
724 if (N0.getOpcode() == Opc) {
725 if (SDNode *L = isConstantBuildVectorOrConstantInt(N0.getOperand(1))) {
726 if (SDNode *R = isConstantBuildVectorOrConstantInt(N1)) {
727 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
728 SDValue OpNode = DAG.FoldConstantArithmetic(Opc, VT, L, R);
729 if (!OpNode.getNode())
731 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
733 if (N0.hasOneUse()) {
734 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one
736 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
737 if (!OpNode.getNode())
739 AddToWorklist(OpNode.getNode());
740 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
745 if (N1.getOpcode() == Opc) {
746 if (SDNode *R = isConstantBuildVectorOrConstantInt(N1.getOperand(1))) {
747 if (SDNode *L = isConstantBuildVectorOrConstantInt(N0)) {
748 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
749 SDValue OpNode = DAG.FoldConstantArithmetic(Opc, VT, R, L);
750 if (!OpNode.getNode())
752 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
754 if (N1.hasOneUse()) {
755 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one
757 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N1.getOperand(0), N0);
758 if (!OpNode.getNode())
760 AddToWorklist(OpNode.getNode());
761 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
769 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
771 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
773 DEBUG(dbgs() << "\nReplacing.1 ";
775 dbgs() << "\nWith: ";
776 To[0].getNode()->dump(&DAG);
777 dbgs() << " and " << NumTo-1 << " other values\n";
778 for (unsigned i = 0, e = NumTo; i != e; ++i)
779 assert((!To[i].getNode() ||
780 N->getValueType(i) == To[i].getValueType()) &&
781 "Cannot combine value to value of different type!"));
782 WorklistRemover DeadNodes(*this);
783 DAG.ReplaceAllUsesWith(N, To);
785 // Push the new nodes and any users onto the worklist
786 for (unsigned i = 0, e = NumTo; i != e; ++i) {
787 if (To[i].getNode()) {
788 AddToWorklist(To[i].getNode());
789 AddUsersToWorklist(To[i].getNode());
794 // Finally, if the node is now dead, remove it from the graph. The node
795 // may not be dead if the replacement process recursively simplified to
796 // something else needing this node.
798 deleteAndRecombine(N);
799 return SDValue(N, 0);
803 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
804 // Replace all uses. If any nodes become isomorphic to other nodes and
805 // are deleted, make sure to remove them from our worklist.
806 WorklistRemover DeadNodes(*this);
807 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
809 // Push the new node and any (possibly new) users onto the worklist.
810 AddToWorklist(TLO.New.getNode());
811 AddUsersToWorklist(TLO.New.getNode());
813 // Finally, if the node is now dead, remove it from the graph. The node
814 // may not be dead if the replacement process recursively simplified to
815 // something else needing this node.
816 if (TLO.Old.getNode()->use_empty())
817 deleteAndRecombine(TLO.Old.getNode());
820 /// Check the specified integer node value to see if it can be simplified or if
821 /// things it uses can be simplified by bit propagation. If so, return true.
822 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
823 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
824 APInt KnownZero, KnownOne;
825 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
829 AddToWorklist(Op.getNode());
831 // Replace the old value with the new one.
833 DEBUG(dbgs() << "\nReplacing.2 ";
834 TLO.Old.getNode()->dump(&DAG);
835 dbgs() << "\nWith: ";
836 TLO.New.getNode()->dump(&DAG);
839 CommitTargetLoweringOpt(TLO);
843 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
845 EVT VT = Load->getValueType(0);
846 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
848 DEBUG(dbgs() << "\nReplacing.9 ";
850 dbgs() << "\nWith: ";
851 Trunc.getNode()->dump(&DAG);
853 WorklistRemover DeadNodes(*this);
854 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
855 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
856 deleteAndRecombine(Load);
857 AddToWorklist(Trunc.getNode());
860 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
863 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
864 EVT MemVT = LD->getMemoryVT();
865 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
866 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
868 : LD->getExtensionType();
870 return DAG.getExtLoad(ExtType, dl, PVT,
871 LD->getChain(), LD->getBasePtr(),
872 MemVT, LD->getMemOperand());
875 unsigned Opc = Op.getOpcode();
878 case ISD::AssertSext:
879 return DAG.getNode(ISD::AssertSext, dl, PVT,
880 SExtPromoteOperand(Op.getOperand(0), PVT),
882 case ISD::AssertZext:
883 return DAG.getNode(ISD::AssertZext, dl, PVT,
884 ZExtPromoteOperand(Op.getOperand(0), PVT),
886 case ISD::Constant: {
888 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
889 return DAG.getNode(ExtOpc, dl, PVT, Op);
893 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
895 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
898 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
899 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
901 EVT OldVT = Op.getValueType();
903 bool Replace = false;
904 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
905 if (!NewOp.getNode())
907 AddToWorklist(NewOp.getNode());
910 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
911 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
912 DAG.getValueType(OldVT));
915 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
916 EVT OldVT = Op.getValueType();
918 bool Replace = false;
919 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
920 if (!NewOp.getNode())
922 AddToWorklist(NewOp.getNode());
925 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
926 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
929 /// Promote the specified integer binary operation if the target indicates it is
930 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
931 /// i32 since i16 instructions are longer.
932 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
933 if (!LegalOperations)
936 EVT VT = Op.getValueType();
937 if (VT.isVector() || !VT.isInteger())
940 // If operation type is 'undesirable', e.g. i16 on x86, consider
942 unsigned Opc = Op.getOpcode();
943 if (TLI.isTypeDesirableForOp(Opc, VT))
947 // Consult target whether it is a good idea to promote this operation and
948 // what's the right type to promote it to.
949 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
950 assert(PVT != VT && "Don't know what type to promote to!");
952 bool Replace0 = false;
953 SDValue N0 = Op.getOperand(0);
954 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
958 bool Replace1 = false;
959 SDValue N1 = Op.getOperand(1);
964 NN1 = PromoteOperand(N1, PVT, Replace1);
969 AddToWorklist(NN0.getNode());
971 AddToWorklist(NN1.getNode());
974 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
976 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
978 DEBUG(dbgs() << "\nPromoting ";
979 Op.getNode()->dump(&DAG));
981 return DAG.getNode(ISD::TRUNCATE, dl, VT,
982 DAG.getNode(Opc, dl, PVT, NN0, NN1));
987 /// Promote the specified integer shift operation if the target indicates it is
988 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
989 /// i32 since i16 instructions are longer.
990 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
991 if (!LegalOperations)
994 EVT VT = Op.getValueType();
995 if (VT.isVector() || !VT.isInteger())
998 // If operation type is 'undesirable', e.g. i16 on x86, consider
1000 unsigned Opc = Op.getOpcode();
1001 if (TLI.isTypeDesirableForOp(Opc, VT))
1005 // Consult target whether it is a good idea to promote this operation and
1006 // what's the right type to promote it to.
1007 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1008 assert(PVT != VT && "Don't know what type to promote to!");
1010 bool Replace = false;
1011 SDValue N0 = Op.getOperand(0);
1012 if (Opc == ISD::SRA)
1013 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
1014 else if (Opc == ISD::SRL)
1015 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
1017 N0 = PromoteOperand(N0, PVT, Replace);
1021 AddToWorklist(N0.getNode());
1023 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1025 DEBUG(dbgs() << "\nPromoting ";
1026 Op.getNode()->dump(&DAG));
1028 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1029 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
1034 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1035 if (!LegalOperations)
1038 EVT VT = Op.getValueType();
1039 if (VT.isVector() || !VT.isInteger())
1042 // If operation type is 'undesirable', e.g. i16 on x86, consider
1044 unsigned Opc = Op.getOpcode();
1045 if (TLI.isTypeDesirableForOp(Opc, VT))
1049 // Consult target whether it is a good idea to promote this operation and
1050 // what's the right type to promote it to.
1051 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1052 assert(PVT != VT && "Don't know what type to promote to!");
1053 // fold (aext (aext x)) -> (aext x)
1054 // fold (aext (zext x)) -> (zext x)
1055 // fold (aext (sext x)) -> (sext x)
1056 DEBUG(dbgs() << "\nPromoting ";
1057 Op.getNode()->dump(&DAG));
1058 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1063 bool DAGCombiner::PromoteLoad(SDValue Op) {
1064 if (!LegalOperations)
1067 EVT VT = Op.getValueType();
1068 if (VT.isVector() || !VT.isInteger())
1071 // If operation type is 'undesirable', e.g. i16 on x86, consider
1073 unsigned Opc = Op.getOpcode();
1074 if (TLI.isTypeDesirableForOp(Opc, VT))
1078 // Consult target whether it is a good idea to promote this operation and
1079 // what's the right type to promote it to.
1080 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1081 assert(PVT != VT && "Don't know what type to promote to!");
1084 SDNode *N = Op.getNode();
1085 LoadSDNode *LD = cast<LoadSDNode>(N);
1086 EVT MemVT = LD->getMemoryVT();
1087 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
1088 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
1090 : LD->getExtensionType();
1091 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
1092 LD->getChain(), LD->getBasePtr(),
1093 MemVT, LD->getMemOperand());
1094 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
1096 DEBUG(dbgs() << "\nPromoting ";
1099 Result.getNode()->dump(&DAG);
1101 WorklistRemover DeadNodes(*this);
1102 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1103 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1104 deleteAndRecombine(N);
1105 AddToWorklist(Result.getNode());
1111 /// \brief Recursively delete a node which has no uses and any operands for
1112 /// which it is the only use.
1114 /// Note that this both deletes the nodes and removes them from the worklist.
1115 /// It also adds any nodes who have had a user deleted to the worklist as they
1116 /// may now have only one use and subject to other combines.
1117 bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1118 if (!N->use_empty())
1121 SmallSetVector<SDNode *, 16> Nodes;
1124 N = Nodes.pop_back_val();
1128 if (N->use_empty()) {
1129 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1130 Nodes.insert(N->getOperand(i).getNode());
1132 removeFromWorklist(N);
1137 } while (!Nodes.empty());
1141 //===----------------------------------------------------------------------===//
1142 // Main DAG Combiner implementation
1143 //===----------------------------------------------------------------------===//
1145 void DAGCombiner::Run(CombineLevel AtLevel) {
1146 // set the instance variables, so that the various visit routines may use it.
1148 LegalOperations = Level >= AfterLegalizeVectorOps;
1149 LegalTypes = Level >= AfterLegalizeTypes;
1151 // Add all the dag nodes to the worklist.
1152 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
1153 E = DAG.allnodes_end(); I != E; ++I)
1156 // Create a dummy node (which is not added to allnodes), that adds a reference
1157 // to the root node, preventing it from being deleted, and tracking any
1158 // changes of the root.
1159 HandleSDNode Dummy(DAG.getRoot());
1161 // while the worklist isn't empty, find a node and
1162 // try and combine it.
1163 while (!WorklistMap.empty()) {
1165 // The Worklist holds the SDNodes in order, but it may contain null entries.
1167 N = Worklist.pop_back_val();
1170 bool GoodWorklistEntry = WorklistMap.erase(N);
1171 (void)GoodWorklistEntry;
1172 assert(GoodWorklistEntry &&
1173 "Found a worklist entry without a corresponding map entry!");
1175 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1176 // N is deleted from the DAG, since they too may now be dead or may have a
1177 // reduced number of uses, allowing other xforms.
1178 if (recursivelyDeleteUnusedNodes(N))
1181 WorklistRemover DeadNodes(*this);
1183 // If this combine is running after legalizing the DAG, re-legalize any
1184 // nodes pulled off the worklist.
1185 if (Level == AfterLegalizeDAG) {
1186 SmallSetVector<SDNode *, 16> UpdatedNodes;
1187 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1189 for (SDNode *LN : UpdatedNodes) {
1191 AddUsersToWorklist(LN);
1197 DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG));
1199 // Add any operands of the new node which have not yet been combined to the
1200 // worklist as well. Because the worklist uniques things already, this
1201 // won't repeatedly process the same operand.
1202 CombinedNodes.insert(N);
1203 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1204 if (!CombinedNodes.count(N->getOperand(i).getNode()))
1205 AddToWorklist(N->getOperand(i).getNode());
1207 SDValue RV = combine(N);
1214 // If we get back the same node we passed in, rather than a new node or
1215 // zero, we know that the node must have defined multiple values and
1216 // CombineTo was used. Since CombineTo takes care of the worklist
1217 // mechanics for us, we have no work to do in this case.
1218 if (RV.getNode() == N)
1221 assert(N->getOpcode() != ISD::DELETED_NODE &&
1222 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1223 "Node was deleted but visit returned new node!");
1225 DEBUG(dbgs() << " ... into: ";
1226 RV.getNode()->dump(&DAG));
1228 // Transfer debug value.
1229 DAG.TransferDbgValues(SDValue(N, 0), RV);
1230 if (N->getNumValues() == RV.getNode()->getNumValues())
1231 DAG.ReplaceAllUsesWith(N, RV.getNode());
1233 assert(N->getValueType(0) == RV.getValueType() &&
1234 N->getNumValues() == 1 && "Type mismatch");
1236 DAG.ReplaceAllUsesWith(N, &OpV);
1239 // Push the new node and any users onto the worklist
1240 AddToWorklist(RV.getNode());
1241 AddUsersToWorklist(RV.getNode());
1243 // Finally, if the node is now dead, remove it from the graph. The node
1244 // may not be dead if the replacement process recursively simplified to
1245 // something else needing this node. This will also take care of adding any
1246 // operands which have lost a user to the worklist.
1247 recursivelyDeleteUnusedNodes(N);
1250 // If the root changed (e.g. it was a dead load, update the root).
1251 DAG.setRoot(Dummy.getValue());
1252 DAG.RemoveDeadNodes();
1255 SDValue DAGCombiner::visit(SDNode *N) {
1256 switch (N->getOpcode()) {
1258 case ISD::TokenFactor: return visitTokenFactor(N);
1259 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1260 case ISD::ADD: return visitADD(N);
1261 case ISD::SUB: return visitSUB(N);
1262 case ISD::ADDC: return visitADDC(N);
1263 case ISD::SUBC: return visitSUBC(N);
1264 case ISD::ADDE: return visitADDE(N);
1265 case ISD::SUBE: return visitSUBE(N);
1266 case ISD::MUL: return visitMUL(N);
1267 case ISD::SDIV: return visitSDIV(N);
1268 case ISD::UDIV: return visitUDIV(N);
1269 case ISD::SREM: return visitSREM(N);
1270 case ISD::UREM: return visitUREM(N);
1271 case ISD::MULHU: return visitMULHU(N);
1272 case ISD::MULHS: return visitMULHS(N);
1273 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1274 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1275 case ISD::SMULO: return visitSMULO(N);
1276 case ISD::UMULO: return visitUMULO(N);
1277 case ISD::SDIVREM: return visitSDIVREM(N);
1278 case ISD::UDIVREM: return visitUDIVREM(N);
1279 case ISD::AND: return visitAND(N);
1280 case ISD::OR: return visitOR(N);
1281 case ISD::XOR: return visitXOR(N);
1282 case ISD::SHL: return visitSHL(N);
1283 case ISD::SRA: return visitSRA(N);
1284 case ISD::SRL: return visitSRL(N);
1286 case ISD::ROTL: return visitRotate(N);
1287 case ISD::CTLZ: return visitCTLZ(N);
1288 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1289 case ISD::CTTZ: return visitCTTZ(N);
1290 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1291 case ISD::CTPOP: return visitCTPOP(N);
1292 case ISD::SELECT: return visitSELECT(N);
1293 case ISD::VSELECT: return visitVSELECT(N);
1294 case ISD::SELECT_CC: return visitSELECT_CC(N);
1295 case ISD::SETCC: return visitSETCC(N);
1296 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1297 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1298 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1299 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1300 case ISD::TRUNCATE: return visitTRUNCATE(N);
1301 case ISD::BITCAST: return visitBITCAST(N);
1302 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1303 case ISD::FADD: return visitFADD(N);
1304 case ISD::FSUB: return visitFSUB(N);
1305 case ISD::FMUL: return visitFMUL(N);
1306 case ISD::FMA: return visitFMA(N);
1307 case ISD::FDIV: return visitFDIV(N);
1308 case ISD::FREM: return visitFREM(N);
1309 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1310 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1311 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1312 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1313 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1314 case ISD::FP_ROUND: return visitFP_ROUND(N);
1315 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1316 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1317 case ISD::FNEG: return visitFNEG(N);
1318 case ISD::FABS: return visitFABS(N);
1319 case ISD::FFLOOR: return visitFFLOOR(N);
1320 case ISD::FCEIL: return visitFCEIL(N);
1321 case ISD::FTRUNC: return visitFTRUNC(N);
1322 case ISD::BRCOND: return visitBRCOND(N);
1323 case ISD::BR_CC: return visitBR_CC(N);
1324 case ISD::LOAD: return visitLOAD(N);
1325 case ISD::STORE: return visitSTORE(N);
1326 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1327 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1328 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1329 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1330 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1331 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1332 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1337 SDValue DAGCombiner::combine(SDNode *N) {
1338 SDValue RV = visit(N);
1340 // If nothing happened, try a target-specific DAG combine.
1341 if (!RV.getNode()) {
1342 assert(N->getOpcode() != ISD::DELETED_NODE &&
1343 "Node was deleted but visit returned NULL!");
1345 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1346 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1348 // Expose the DAG combiner to the target combiner impls.
1349 TargetLowering::DAGCombinerInfo
1350 DagCombineInfo(DAG, Level, false, this);
1352 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1356 // If nothing happened still, try promoting the operation.
1357 if (!RV.getNode()) {
1358 switch (N->getOpcode()) {
1366 RV = PromoteIntBinOp(SDValue(N, 0));
1371 RV = PromoteIntShiftOp(SDValue(N, 0));
1373 case ISD::SIGN_EXTEND:
1374 case ISD::ZERO_EXTEND:
1375 case ISD::ANY_EXTEND:
1376 RV = PromoteExtend(SDValue(N, 0));
1379 if (PromoteLoad(SDValue(N, 0)))
1385 // If N is a commutative binary node, try commuting it to enable more
1387 if (!RV.getNode() && SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1388 N->getNumValues() == 1) {
1389 SDValue N0 = N->getOperand(0);
1390 SDValue N1 = N->getOperand(1);
1392 // Constant operands are canonicalized to RHS.
1393 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1394 SDValue Ops[] = {N1, N0};
1396 if (const BinaryWithFlagsSDNode *BinNode =
1397 dyn_cast<BinaryWithFlagsSDNode>(N)) {
1398 CSENode = DAG.getNodeIfExists(
1399 N->getOpcode(), N->getVTList(), Ops, BinNode->hasNoUnsignedWrap(),
1400 BinNode->hasNoSignedWrap(), BinNode->isExact());
1402 CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops);
1405 return SDValue(CSENode, 0);
1412 /// Given a node, return its input chain if it has one, otherwise return a null
1414 static SDValue getInputChainForNode(SDNode *N) {
1415 if (unsigned NumOps = N->getNumOperands()) {
1416 if (N->getOperand(0).getValueType() == MVT::Other)
1417 return N->getOperand(0);
1418 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1419 return N->getOperand(NumOps-1);
1420 for (unsigned i = 1; i < NumOps-1; ++i)
1421 if (N->getOperand(i).getValueType() == MVT::Other)
1422 return N->getOperand(i);
1427 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1428 // If N has two operands, where one has an input chain equal to the other,
1429 // the 'other' chain is redundant.
1430 if (N->getNumOperands() == 2) {
1431 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1432 return N->getOperand(0);
1433 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1434 return N->getOperand(1);
1437 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1438 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1439 SmallPtrSet<SDNode*, 16> SeenOps;
1440 bool Changed = false; // If we should replace this token factor.
1442 // Start out with this token factor.
1445 // Iterate through token factors. The TFs grows when new token factors are
1447 for (unsigned i = 0; i < TFs.size(); ++i) {
1448 SDNode *TF = TFs[i];
1450 // Check each of the operands.
1451 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1452 SDValue Op = TF->getOperand(i);
1454 switch (Op.getOpcode()) {
1455 case ISD::EntryToken:
1456 // Entry tokens don't need to be added to the list. They are
1461 case ISD::TokenFactor:
1462 if (Op.hasOneUse() &&
1463 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1464 // Queue up for processing.
1465 TFs.push_back(Op.getNode());
1466 // Clean up in case the token factor is removed.
1467 AddToWorklist(Op.getNode());
1474 // Only add if it isn't already in the list.
1475 if (SeenOps.insert(Op.getNode()))
1486 // If we've change things around then replace token factor.
1489 // The entry token is the only possible outcome.
1490 Result = DAG.getEntryNode();
1492 // New and improved token factor.
1493 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Ops);
1496 // Don't add users to work list.
1497 return CombineTo(N, Result, false);
1503 /// MERGE_VALUES can always be eliminated.
1504 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1505 WorklistRemover DeadNodes(*this);
1506 // Replacing results may cause a different MERGE_VALUES to suddenly
1507 // be CSE'd with N, and carry its uses with it. Iterate until no
1508 // uses remain, to ensure that the node can be safely deleted.
1509 // First add the users of this node to the work list so that they
1510 // can be tried again once they have new operands.
1511 AddUsersToWorklist(N);
1513 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1514 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1515 } while (!N->use_empty());
1516 deleteAndRecombine(N);
1517 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1521 SDValue combineShlAddConstant(SDLoc DL, SDValue N0, SDValue N1,
1522 SelectionDAG &DAG) {
1523 EVT VT = N0.getValueType();
1524 SDValue N00 = N0.getOperand(0);
1525 SDValue N01 = N0.getOperand(1);
1526 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1528 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1529 isa<ConstantSDNode>(N00.getOperand(1))) {
1530 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1531 N0 = DAG.getNode(ISD::ADD, SDLoc(N0), VT,
1532 DAG.getNode(ISD::SHL, SDLoc(N00), VT,
1533 N00.getOperand(0), N01),
1534 DAG.getNode(ISD::SHL, SDLoc(N01), VT,
1535 N00.getOperand(1), N01));
1536 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1542 SDValue DAGCombiner::visitADD(SDNode *N) {
1543 SDValue N0 = N->getOperand(0);
1544 SDValue N1 = N->getOperand(1);
1545 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1546 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1547 EVT VT = N0.getValueType();
1550 if (VT.isVector()) {
1551 SDValue FoldedVOp = SimplifyVBinOp(N);
1552 if (FoldedVOp.getNode()) return FoldedVOp;
1554 // fold (add x, 0) -> x, vector edition
1555 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1557 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1561 // fold (add x, undef) -> undef
1562 if (N0.getOpcode() == ISD::UNDEF)
1564 if (N1.getOpcode() == ISD::UNDEF)
1566 // fold (add c1, c2) -> c1+c2
1568 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1569 // canonicalize constant to RHS
1571 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1572 // fold (add x, 0) -> x
1573 if (N1C && N1C->isNullValue())
1575 // fold (add Sym, c) -> Sym+c
1576 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1577 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1578 GA->getOpcode() == ISD::GlobalAddress)
1579 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1581 (uint64_t)N1C->getSExtValue());
1582 // fold ((c1-A)+c2) -> (c1+c2)-A
1583 if (N1C && N0.getOpcode() == ISD::SUB)
1584 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1585 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1586 DAG.getConstant(N1C->getAPIntValue()+
1587 N0C->getAPIntValue(), VT),
1590 SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1);
1593 // fold ((0-A) + B) -> B-A
1594 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1595 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1596 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1597 // fold (A + (0-B)) -> A-B
1598 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1599 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1600 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1601 // fold (A+(B-A)) -> B
1602 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1603 return N1.getOperand(0);
1604 // fold ((B-A)+A) -> B
1605 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1606 return N0.getOperand(0);
1607 // fold (A+(B-(A+C))) to (B-C)
1608 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1609 N0 == N1.getOperand(1).getOperand(0))
1610 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1611 N1.getOperand(1).getOperand(1));
1612 // fold (A+(B-(C+A))) to (B-C)
1613 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1614 N0 == N1.getOperand(1).getOperand(1))
1615 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1616 N1.getOperand(1).getOperand(0));
1617 // fold (A+((B-A)+or-C)) to (B+or-C)
1618 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1619 N1.getOperand(0).getOpcode() == ISD::SUB &&
1620 N0 == N1.getOperand(0).getOperand(1))
1621 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT,
1622 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1624 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1625 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1626 SDValue N00 = N0.getOperand(0);
1627 SDValue N01 = N0.getOperand(1);
1628 SDValue N10 = N1.getOperand(0);
1629 SDValue N11 = N1.getOperand(1);
1631 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1632 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1633 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1634 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
1637 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1638 return SDValue(N, 0);
1640 // fold (a+b) -> (a|b) iff a and b share no bits.
1641 if (VT.isInteger() && !VT.isVector()) {
1642 APInt LHSZero, LHSOne;
1643 APInt RHSZero, RHSOne;
1644 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1646 if (LHSZero.getBoolValue()) {
1647 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1649 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1650 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1651 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero){
1652 if (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT))
1653 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1658 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1659 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1660 SDValue Result = combineShlAddConstant(SDLoc(N), N0, N1, DAG);
1661 if (Result.getNode()) return Result;
1663 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1664 SDValue Result = combineShlAddConstant(SDLoc(N), N1, N0, DAG);
1665 if (Result.getNode()) return Result;
1668 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1669 if (N1.getOpcode() == ISD::SHL &&
1670 N1.getOperand(0).getOpcode() == ISD::SUB)
1671 if (ConstantSDNode *C =
1672 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1673 if (C->getAPIntValue() == 0)
1674 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1675 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1676 N1.getOperand(0).getOperand(1),
1678 if (N0.getOpcode() == ISD::SHL &&
1679 N0.getOperand(0).getOpcode() == ISD::SUB)
1680 if (ConstantSDNode *C =
1681 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1682 if (C->getAPIntValue() == 0)
1683 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1,
1684 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1685 N0.getOperand(0).getOperand(1),
1688 if (N1.getOpcode() == ISD::AND) {
1689 SDValue AndOp0 = N1.getOperand(0);
1690 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1691 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1692 unsigned DestBits = VT.getScalarType().getSizeInBits();
1694 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1695 // and similar xforms where the inner op is either ~0 or 0.
1696 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1698 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1702 // add (sext i1), X -> sub X, (zext i1)
1703 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1704 N0.getOperand(0).getValueType() == MVT::i1 &&
1705 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1707 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1708 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1714 SDValue DAGCombiner::visitADDC(SDNode *N) {
1715 SDValue N0 = N->getOperand(0);
1716 SDValue N1 = N->getOperand(1);
1717 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1718 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1719 EVT VT = N0.getValueType();
1721 // If the flag result is dead, turn this into an ADD.
1722 if (!N->hasAnyUseOfValue(1))
1723 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1724 DAG.getNode(ISD::CARRY_FALSE,
1725 SDLoc(N), MVT::Glue));
1727 // canonicalize constant to RHS.
1729 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1731 // fold (addc x, 0) -> x + no carry out
1732 if (N1C && N1C->isNullValue())
1733 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1734 SDLoc(N), MVT::Glue));
1736 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1737 APInt LHSZero, LHSOne;
1738 APInt RHSZero, RHSOne;
1739 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1741 if (LHSZero.getBoolValue()) {
1742 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1744 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1745 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1746 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1747 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1748 DAG.getNode(ISD::CARRY_FALSE,
1749 SDLoc(N), MVT::Glue));
1755 SDValue DAGCombiner::visitADDE(SDNode *N) {
1756 SDValue N0 = N->getOperand(0);
1757 SDValue N1 = N->getOperand(1);
1758 SDValue CarryIn = N->getOperand(2);
1759 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1760 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1762 // canonicalize constant to RHS
1764 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
1767 // fold (adde x, y, false) -> (addc x, y)
1768 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1769 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1774 // Since it may not be valid to emit a fold to zero for vector initializers
1775 // check if we can before folding.
1776 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT,
1778 bool LegalOperations, bool LegalTypes) {
1780 return DAG.getConstant(0, VT);
1781 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
1782 return DAG.getConstant(0, VT);
1786 SDValue DAGCombiner::visitSUB(SDNode *N) {
1787 SDValue N0 = N->getOperand(0);
1788 SDValue N1 = N->getOperand(1);
1789 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1790 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1791 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? nullptr :
1792 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1793 EVT VT = N0.getValueType();
1796 if (VT.isVector()) {
1797 SDValue FoldedVOp = SimplifyVBinOp(N);
1798 if (FoldedVOp.getNode()) return FoldedVOp;
1800 // fold (sub x, 0) -> x, vector edition
1801 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1805 // fold (sub x, x) -> 0
1806 // FIXME: Refactor this and xor and other similar operations together.
1808 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
1809 // fold (sub c1, c2) -> c1-c2
1811 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1812 // fold (sub x, c) -> (add x, -c)
1814 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0,
1815 DAG.getConstant(-N1C->getAPIntValue(), VT));
1816 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1817 if (N0C && N0C->isAllOnesValue())
1818 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1819 // fold A-(A-B) -> B
1820 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1821 return N1.getOperand(1);
1822 // fold (A+B)-A -> B
1823 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1824 return N0.getOperand(1);
1825 // fold (A+B)-B -> A
1826 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1827 return N0.getOperand(0);
1828 // fold C2-(A+C1) -> (C2-C1)-A
1829 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1830 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1832 return DAG.getNode(ISD::SUB, SDLoc(N), VT, NewC,
1835 // fold ((A+(B+or-C))-B) -> A+or-C
1836 if (N0.getOpcode() == ISD::ADD &&
1837 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1838 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1839 N0.getOperand(1).getOperand(0) == N1)
1840 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1841 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1842 // fold ((A+(C+B))-B) -> A+C
1843 if (N0.getOpcode() == ISD::ADD &&
1844 N0.getOperand(1).getOpcode() == ISD::ADD &&
1845 N0.getOperand(1).getOperand(1) == N1)
1846 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1847 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1848 // fold ((A-(B-C))-C) -> A-B
1849 if (N0.getOpcode() == ISD::SUB &&
1850 N0.getOperand(1).getOpcode() == ISD::SUB &&
1851 N0.getOperand(1).getOperand(1) == N1)
1852 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1853 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1855 // If either operand of a sub is undef, the result is undef
1856 if (N0.getOpcode() == ISD::UNDEF)
1858 if (N1.getOpcode() == ISD::UNDEF)
1861 // If the relocation model supports it, consider symbol offsets.
1862 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1863 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1864 // fold (sub Sym, c) -> Sym-c
1865 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1866 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1868 (uint64_t)N1C->getSExtValue());
1869 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1870 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1871 if (GA->getGlobal() == GB->getGlobal())
1872 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1879 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1880 SDValue N0 = N->getOperand(0);
1881 SDValue N1 = N->getOperand(1);
1882 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1883 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1884 EVT VT = N0.getValueType();
1886 // If the flag result is dead, turn this into an SUB.
1887 if (!N->hasAnyUseOfValue(1))
1888 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1),
1889 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1892 // fold (subc x, x) -> 0 + no borrow
1894 return CombineTo(N, DAG.getConstant(0, VT),
1895 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1898 // fold (subc x, 0) -> x + no borrow
1899 if (N1C && N1C->isNullValue())
1900 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1903 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1904 if (N0C && N0C->isAllOnesValue())
1905 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
1906 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1912 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1913 SDValue N0 = N->getOperand(0);
1914 SDValue N1 = N->getOperand(1);
1915 SDValue CarryIn = N->getOperand(2);
1917 // fold (sube x, y, false) -> (subc x, y)
1918 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1919 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
1924 SDValue DAGCombiner::visitMUL(SDNode *N) {
1925 SDValue N0 = N->getOperand(0);
1926 SDValue N1 = N->getOperand(1);
1927 EVT VT = N0.getValueType();
1929 // fold (mul x, undef) -> 0
1930 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1931 return DAG.getConstant(0, VT);
1933 bool N0IsConst = false;
1934 bool N1IsConst = false;
1935 APInt ConstValue0, ConstValue1;
1937 if (VT.isVector()) {
1938 SDValue FoldedVOp = SimplifyVBinOp(N);
1939 if (FoldedVOp.getNode()) return FoldedVOp;
1941 N0IsConst = isConstantSplatVector(N0.getNode(), ConstValue0);
1942 N1IsConst = isConstantSplatVector(N1.getNode(), ConstValue1);
1944 N0IsConst = dyn_cast<ConstantSDNode>(N0) != nullptr;
1945 ConstValue0 = N0IsConst ? (dyn_cast<ConstantSDNode>(N0))->getAPIntValue()
1947 N1IsConst = dyn_cast<ConstantSDNode>(N1) != nullptr;
1948 ConstValue1 = N1IsConst ? (dyn_cast<ConstantSDNode>(N1))->getAPIntValue()
1952 // fold (mul c1, c2) -> c1*c2
1953 if (N0IsConst && N1IsConst)
1954 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0.getNode(), N1.getNode());
1956 // canonicalize constant to RHS
1957 if (N0IsConst && !N1IsConst)
1958 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
1959 // fold (mul x, 0) -> 0
1960 if (N1IsConst && ConstValue1 == 0)
1962 // We require a splat of the entire scalar bit width for non-contiguous
1965 ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits();
1966 // fold (mul x, 1) -> x
1967 if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
1969 // fold (mul x, -1) -> 0-x
1970 if (N1IsConst && ConstValue1.isAllOnesValue())
1971 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1972 DAG.getConstant(0, VT), N0);
1973 // fold (mul x, (1 << c)) -> x << c
1974 if (N1IsConst && ConstValue1.isPowerOf2() && IsFullSplat)
1975 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1976 DAG.getConstant(ConstValue1.logBase2(),
1977 getShiftAmountTy(N0.getValueType())));
1978 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1979 if (N1IsConst && (-ConstValue1).isPowerOf2() && IsFullSplat) {
1980 unsigned Log2Val = (-ConstValue1).logBase2();
1981 // FIXME: If the input is something that is easily negated (e.g. a
1982 // single-use add), we should put the negate there.
1983 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1984 DAG.getConstant(0, VT),
1985 DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1986 DAG.getConstant(Log2Val,
1987 getShiftAmountTy(N0.getValueType()))));
1991 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1992 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
1993 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
1994 isa<ConstantSDNode>(N0.getOperand(1)))) {
1995 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT,
1996 N1, N0.getOperand(1));
1997 AddToWorklist(C3.getNode());
1998 return DAG.getNode(ISD::MUL, SDLoc(N), VT,
1999 N0.getOperand(0), C3);
2002 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
2005 SDValue Sh(nullptr,0), Y(nullptr,0);
2006 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
2007 if (N0.getOpcode() == ISD::SHL &&
2008 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2009 isa<ConstantSDNode>(N0.getOperand(1))) &&
2010 N0.getNode()->hasOneUse()) {
2012 } else if (N1.getOpcode() == ISD::SHL &&
2013 isa<ConstantSDNode>(N1.getOperand(1)) &&
2014 N1.getNode()->hasOneUse()) {
2019 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2020 Sh.getOperand(0), Y);
2021 return DAG.getNode(ISD::SHL, SDLoc(N), VT,
2022 Mul, Sh.getOperand(1));
2026 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
2027 if (N1IsConst && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
2028 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2029 isa<ConstantSDNode>(N0.getOperand(1))))
2030 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
2031 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
2032 N0.getOperand(0), N1),
2033 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
2034 N0.getOperand(1), N1));
2037 SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1);
2044 SDValue DAGCombiner::visitSDIV(SDNode *N) {
2045 SDValue N0 = N->getOperand(0);
2046 SDValue N1 = N->getOperand(1);
2047 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2048 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2049 EVT VT = N->getValueType(0);
2052 if (VT.isVector()) {
2053 SDValue FoldedVOp = SimplifyVBinOp(N);
2054 if (FoldedVOp.getNode()) return FoldedVOp;
2057 // fold (sdiv c1, c2) -> c1/c2
2058 if (N0C && N1C && !N1C->isNullValue())
2059 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
2060 // fold (sdiv X, 1) -> X
2061 if (N1C && N1C->getAPIntValue() == 1LL)
2063 // fold (sdiv X, -1) -> 0-X
2064 if (N1C && N1C->isAllOnesValue())
2065 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
2066 DAG.getConstant(0, VT), N0);
2067 // If we know the sign bits of both operands are zero, strength reduce to a
2068 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
2069 if (!VT.isVector()) {
2070 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2071 return DAG.getNode(ISD::UDIV, SDLoc(N), N1.getValueType(),
2075 // fold (sdiv X, pow2) -> simple ops after legalize
2076 if (N1C && !N1C->isNullValue() && (N1C->getAPIntValue().isPowerOf2() ||
2077 (-N1C->getAPIntValue()).isPowerOf2())) {
2078 // If dividing by powers of two is cheap, then don't perform the following
2080 if (TLI.isPow2SDivCheap())
2083 // Target-specific implementation of sdiv x, pow2.
2084 SDValue Res = BuildSDIVPow2(N);
2088 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
2090 // Splat the sign bit into the register
2092 DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
2093 DAG.getConstant(VT.getScalarSizeInBits() - 1,
2094 getShiftAmountTy(N0.getValueType())));
2095 AddToWorklist(SGN.getNode());
2097 // Add (N0 < 0) ? abs2 - 1 : 0;
2099 DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN,
2100 DAG.getConstant(VT.getScalarSizeInBits() - lg2,
2101 getShiftAmountTy(SGN.getValueType())));
2102 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL);
2103 AddToWorklist(SRL.getNode());
2104 AddToWorklist(ADD.getNode()); // Divide by pow2
2105 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD,
2106 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
2108 // If we're dividing by a positive value, we're done. Otherwise, we must
2109 // negate the result.
2110 if (N1C->getAPIntValue().isNonNegative())
2113 AddToWorklist(SRA.getNode());
2114 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), SRA);
2117 // if integer divide is expensive and we satisfy the requirements, emit an
2118 // alternate sequence.
2119 if (N1C && !TLI.isIntDivCheap()) {
2120 SDValue Op = BuildSDIV(N);
2121 if (Op.getNode()) return Op;
2125 if (N0.getOpcode() == ISD::UNDEF)
2126 return DAG.getConstant(0, VT);
2127 // X / undef -> undef
2128 if (N1.getOpcode() == ISD::UNDEF)
2134 SDValue DAGCombiner::visitUDIV(SDNode *N) {
2135 SDValue N0 = N->getOperand(0);
2136 SDValue N1 = N->getOperand(1);
2137 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2138 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2139 EVT VT = N->getValueType(0);
2142 if (VT.isVector()) {
2143 SDValue FoldedVOp = SimplifyVBinOp(N);
2144 if (FoldedVOp.getNode()) return FoldedVOp;
2147 // fold (udiv c1, c2) -> c1/c2
2148 if (N0C && N1C && !N1C->isNullValue())
2149 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
2150 // fold (udiv x, (1 << c)) -> x >>u c
2151 if (N1C && N1C->getAPIntValue().isPowerOf2())
2152 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
2153 DAG.getConstant(N1C->getAPIntValue().logBase2(),
2154 getShiftAmountTy(N0.getValueType())));
2155 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
2156 if (N1.getOpcode() == ISD::SHL) {
2157 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2158 if (SHC->getAPIntValue().isPowerOf2()) {
2159 EVT ADDVT = N1.getOperand(1).getValueType();
2160 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N), ADDVT,
2162 DAG.getConstant(SHC->getAPIntValue()
2165 AddToWorklist(Add.getNode());
2166 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add);
2170 // fold (udiv x, c) -> alternate
2171 if (N1C && !TLI.isIntDivCheap()) {
2172 SDValue Op = BuildUDIV(N);
2173 if (Op.getNode()) return Op;
2177 if (N0.getOpcode() == ISD::UNDEF)
2178 return DAG.getConstant(0, VT);
2179 // X / undef -> undef
2180 if (N1.getOpcode() == ISD::UNDEF)
2186 SDValue DAGCombiner::visitSREM(SDNode *N) {
2187 SDValue N0 = N->getOperand(0);
2188 SDValue N1 = N->getOperand(1);
2189 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2190 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2191 EVT VT = N->getValueType(0);
2193 // fold (srem c1, c2) -> c1%c2
2194 if (N0C && N1C && !N1C->isNullValue())
2195 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
2196 // If we know the sign bits of both operands are zero, strength reduce to a
2197 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
2198 if (!VT.isVector()) {
2199 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2200 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1);
2203 // If X/C can be simplified by the division-by-constant logic, lower
2204 // X%C to the equivalent of X-X/C*C.
2205 if (N1C && !N1C->isNullValue()) {
2206 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1);
2207 AddToWorklist(Div.getNode());
2208 SDValue OptimizedDiv = combine(Div.getNode());
2209 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2210 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2212 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2213 AddToWorklist(Mul.getNode());
2219 if (N0.getOpcode() == ISD::UNDEF)
2220 return DAG.getConstant(0, VT);
2221 // X % undef -> undef
2222 if (N1.getOpcode() == ISD::UNDEF)
2228 SDValue DAGCombiner::visitUREM(SDNode *N) {
2229 SDValue N0 = N->getOperand(0);
2230 SDValue N1 = N->getOperand(1);
2231 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2232 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2233 EVT VT = N->getValueType(0);
2235 // fold (urem c1, c2) -> c1%c2
2236 if (N0C && N1C && !N1C->isNullValue())
2237 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2238 // fold (urem x, pow2) -> (and x, pow2-1)
2239 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2240 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0,
2241 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2242 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2243 if (N1.getOpcode() == ISD::SHL) {
2244 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2245 if (SHC->getAPIntValue().isPowerOf2()) {
2247 DAG.getNode(ISD::ADD, SDLoc(N), VT, N1,
2248 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2250 AddToWorklist(Add.getNode());
2251 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, Add);
2256 // If X/C can be simplified by the division-by-constant logic, lower
2257 // X%C to the equivalent of X-X/C*C.
2258 if (N1C && !N1C->isNullValue()) {
2259 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1);
2260 AddToWorklist(Div.getNode());
2261 SDValue OptimizedDiv = combine(Div.getNode());
2262 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2263 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2265 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2266 AddToWorklist(Mul.getNode());
2272 if (N0.getOpcode() == ISD::UNDEF)
2273 return DAG.getConstant(0, VT);
2274 // X % undef -> undef
2275 if (N1.getOpcode() == ISD::UNDEF)
2281 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2282 SDValue N0 = N->getOperand(0);
2283 SDValue N1 = N->getOperand(1);
2284 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2285 EVT VT = N->getValueType(0);
2288 // fold (mulhs x, 0) -> 0
2289 if (N1C && N1C->isNullValue())
2291 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2292 if (N1C && N1C->getAPIntValue() == 1)
2293 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0,
2294 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2295 getShiftAmountTy(N0.getValueType())));
2296 // fold (mulhs x, undef) -> 0
2297 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2298 return DAG.getConstant(0, VT);
2300 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2302 if (VT.isSimple() && !VT.isVector()) {
2303 MVT Simple = VT.getSimpleVT();
2304 unsigned SimpleSize = Simple.getSizeInBits();
2305 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2306 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2307 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2308 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2309 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2310 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2311 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2312 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2319 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2320 SDValue N0 = N->getOperand(0);
2321 SDValue N1 = N->getOperand(1);
2322 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2323 EVT VT = N->getValueType(0);
2326 // fold (mulhu x, 0) -> 0
2327 if (N1C && N1C->isNullValue())
2329 // fold (mulhu x, 1) -> 0
2330 if (N1C && N1C->getAPIntValue() == 1)
2331 return DAG.getConstant(0, N0.getValueType());
2332 // fold (mulhu x, undef) -> 0
2333 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2334 return DAG.getConstant(0, VT);
2336 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2338 if (VT.isSimple() && !VT.isVector()) {
2339 MVT Simple = VT.getSimpleVT();
2340 unsigned SimpleSize = Simple.getSizeInBits();
2341 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2342 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2343 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2344 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2345 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2346 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2347 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2348 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2355 /// Perform optimizations common to nodes that compute two values. LoOp and HiOp
2356 /// give the opcodes for the two computations that are being performed. Return
2357 /// true if a simplification was made.
2358 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2360 // If the high half is not needed, just compute the low half.
2361 bool HiExists = N->hasAnyUseOfValue(1);
2363 (!LegalOperations ||
2364 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
2365 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2366 return CombineTo(N, Res, Res);
2369 // If the low half is not needed, just compute the high half.
2370 bool LoExists = N->hasAnyUseOfValue(0);
2372 (!LegalOperations ||
2373 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2374 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2375 return CombineTo(N, Res, Res);
2378 // If both halves are used, return as it is.
2379 if (LoExists && HiExists)
2382 // If the two computed results can be simplified separately, separate them.
2384 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2385 AddToWorklist(Lo.getNode());
2386 SDValue LoOpt = combine(Lo.getNode());
2387 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2388 (!LegalOperations ||
2389 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2390 return CombineTo(N, LoOpt, LoOpt);
2394 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2395 AddToWorklist(Hi.getNode());
2396 SDValue HiOpt = combine(Hi.getNode());
2397 if (HiOpt.getNode() && HiOpt != Hi &&
2398 (!LegalOperations ||
2399 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2400 return CombineTo(N, HiOpt, HiOpt);
2406 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2407 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2408 if (Res.getNode()) return Res;
2410 EVT VT = N->getValueType(0);
2413 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2415 if (VT.isSimple() && !VT.isVector()) {
2416 MVT Simple = VT.getSimpleVT();
2417 unsigned SimpleSize = Simple.getSizeInBits();
2418 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2419 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2420 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2421 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2422 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2423 // Compute the high part as N1.
2424 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2425 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2426 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2427 // Compute the low part as N0.
2428 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2429 return CombineTo(N, Lo, Hi);
2436 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2437 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2438 if (Res.getNode()) return Res;
2440 EVT VT = N->getValueType(0);
2443 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2445 if (VT.isSimple() && !VT.isVector()) {
2446 MVT Simple = VT.getSimpleVT();
2447 unsigned SimpleSize = Simple.getSizeInBits();
2448 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2449 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2450 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2451 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2452 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2453 // Compute the high part as N1.
2454 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2455 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2456 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2457 // Compute the low part as N0.
2458 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2459 return CombineTo(N, Lo, Hi);
2466 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2467 // (smulo x, 2) -> (saddo x, x)
2468 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2469 if (C2->getAPIntValue() == 2)
2470 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
2471 N->getOperand(0), N->getOperand(0));
2476 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2477 // (umulo x, 2) -> (uaddo x, x)
2478 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2479 if (C2->getAPIntValue() == 2)
2480 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
2481 N->getOperand(0), N->getOperand(0));
2486 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2487 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2488 if (Res.getNode()) return Res;
2493 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2494 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2495 if (Res.getNode()) return Res;
2500 /// If this is a binary operator with two operands of the same opcode, try to
2502 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2503 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2504 EVT VT = N0.getValueType();
2505 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2507 // Bail early if none of these transforms apply.
2508 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2510 // For each of OP in AND/OR/XOR:
2511 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2512 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2513 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2514 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2516 // do not sink logical op inside of a vector extend, since it may combine
2518 EVT Op0VT = N0.getOperand(0).getValueType();
2519 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2520 N0.getOpcode() == ISD::SIGN_EXTEND ||
2521 // Avoid infinite looping with PromoteIntBinOp.
2522 (N0.getOpcode() == ISD::ANY_EXTEND &&
2523 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2524 (N0.getOpcode() == ISD::TRUNCATE &&
2525 (!TLI.isZExtFree(VT, Op0VT) ||
2526 !TLI.isTruncateFree(Op0VT, VT)) &&
2527 TLI.isTypeLegal(Op0VT))) &&
2529 Op0VT == N1.getOperand(0).getValueType() &&
2530 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2531 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2532 N0.getOperand(0).getValueType(),
2533 N0.getOperand(0), N1.getOperand(0));
2534 AddToWorklist(ORNode.getNode());
2535 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2538 // For each of OP in SHL/SRL/SRA/AND...
2539 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2540 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2541 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2542 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2543 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2544 N0.getOperand(1) == N1.getOperand(1)) {
2545 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2546 N0.getOperand(0).getValueType(),
2547 N0.getOperand(0), N1.getOperand(0));
2548 AddToWorklist(ORNode.getNode());
2549 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2550 ORNode, N0.getOperand(1));
2553 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2554 // Only perform this optimization after type legalization and before
2555 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2556 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2557 // we don't want to undo this promotion.
2558 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2560 if ((N0.getOpcode() == ISD::BITCAST ||
2561 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2562 Level == AfterLegalizeTypes) {
2563 SDValue In0 = N0.getOperand(0);
2564 SDValue In1 = N1.getOperand(0);
2565 EVT In0Ty = In0.getValueType();
2566 EVT In1Ty = In1.getValueType();
2568 // If both incoming values are integers, and the original types are the
2570 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2571 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2572 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2573 AddToWorklist(Op.getNode());
2578 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2579 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2580 // If both shuffles use the same mask, and both shuffle within a single
2581 // vector, then it is worthwhile to move the swizzle after the operation.
2582 // The type-legalizer generates this pattern when loading illegal
2583 // vector types from memory. In many cases this allows additional shuffle
2585 // There are other cases where moving the shuffle after the xor/and/or
2586 // is profitable even if shuffles don't perform a swizzle.
2587 // If both shuffles use the same mask, and both shuffles have the same first
2588 // or second operand, then it might still be profitable to move the shuffle
2589 // after the xor/and/or operation.
2590 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
2591 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2592 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2594 assert(N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
2595 "Inputs to shuffles are not the same type");
2597 // Check that both shuffles use the same mask. The masks are known to be of
2598 // the same length because the result vector type is the same.
2599 // Check also that shuffles have only one use to avoid introducing extra
2601 if (SVN0->hasOneUse() && SVN1->hasOneUse() &&
2602 SVN0->getMask().equals(SVN1->getMask())) {
2603 SDValue ShOp = N0->getOperand(1);
2605 // Don't try to fold this node if it requires introducing a
2606 // build vector of all zeros that might be illegal at this stage.
2607 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2609 ShOp = DAG.getConstant(0, VT);
2614 // (AND (shuf (A, C), shuf (B, C)) -> shuf (AND (A, B), C)
2615 // (OR (shuf (A, C), shuf (B, C)) -> shuf (OR (A, B), C)
2616 // (XOR (shuf (A, C), shuf (B, C)) -> shuf (XOR (A, B), V_0)
2617 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
2618 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2619 N0->getOperand(0), N1->getOperand(0));
2620 AddToWorklist(NewNode.getNode());
2621 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp,
2622 &SVN0->getMask()[0]);
2625 // Don't try to fold this node if it requires introducing a
2626 // build vector of all zeros that might be illegal at this stage.
2627 ShOp = N0->getOperand(0);
2628 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2630 ShOp = DAG.getConstant(0, VT);
2635 // (AND (shuf (C, A), shuf (C, B)) -> shuf (C, AND (A, B))
2636 // (OR (shuf (C, A), shuf (C, B)) -> shuf (C, OR (A, B))
2637 // (XOR (shuf (C, A), shuf (C, B)) -> shuf (V_0, XOR (A, B))
2638 if (N0->getOperand(0) == N1->getOperand(0) && ShOp.getNode()) {
2639 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2640 N0->getOperand(1), N1->getOperand(1));
2641 AddToWorklist(NewNode.getNode());
2642 return DAG.getVectorShuffle(VT, SDLoc(N), ShOp, NewNode,
2643 &SVN0->getMask()[0]);
2651 SDValue DAGCombiner::visitAND(SDNode *N) {
2652 SDValue N0 = N->getOperand(0);
2653 SDValue N1 = N->getOperand(1);
2654 SDValue LL, LR, RL, RR, CC0, CC1;
2655 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2656 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2657 EVT VT = N1.getValueType();
2658 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2661 if (VT.isVector()) {
2662 SDValue FoldedVOp = SimplifyVBinOp(N);
2663 if (FoldedVOp.getNode()) return FoldedVOp;
2665 // fold (and x, 0) -> 0, vector edition
2666 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2668 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2671 // fold (and x, -1) -> x, vector edition
2672 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2674 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2678 // fold (and x, undef) -> 0
2679 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2680 return DAG.getConstant(0, VT);
2681 // fold (and c1, c2) -> c1&c2
2683 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2684 // canonicalize constant to RHS
2686 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
2687 // fold (and x, -1) -> x
2688 if (N1C && N1C->isAllOnesValue())
2690 // if (and x, c) is known to be zero, return 0
2691 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2692 APInt::getAllOnesValue(BitWidth)))
2693 return DAG.getConstant(0, VT);
2695 SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1);
2698 // fold (and (or x, C), D) -> D if (C & D) == D
2699 if (N1C && N0.getOpcode() == ISD::OR)
2700 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2701 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2703 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2704 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2705 SDValue N0Op0 = N0.getOperand(0);
2706 APInt Mask = ~N1C->getAPIntValue();
2707 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2708 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2709 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2710 N0.getValueType(), N0Op0);
2712 // Replace uses of the AND with uses of the Zero extend node.
2715 // We actually want to replace all uses of the any_extend with the
2716 // zero_extend, to avoid duplicating things. This will later cause this
2717 // AND to be folded.
2718 CombineTo(N0.getNode(), Zext);
2719 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2722 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2723 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2724 // already be zero by virtue of the width of the base type of the load.
2726 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2728 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2729 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2730 N0.getOpcode() == ISD::LOAD) {
2731 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2732 N0 : N0.getOperand(0) );
2734 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2735 // This can be a pure constant or a vector splat, in which case we treat the
2736 // vector as a scalar and use the splat value.
2737 APInt Constant = APInt::getNullValue(1);
2738 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2739 Constant = C->getAPIntValue();
2740 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2741 APInt SplatValue, SplatUndef;
2742 unsigned SplatBitSize;
2744 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2745 SplatBitSize, HasAnyUndefs);
2747 // Undef bits can contribute to a possible optimisation if set, so
2749 SplatValue |= SplatUndef;
2751 // The splat value may be something like "0x00FFFFFF", which means 0 for
2752 // the first vector value and FF for the rest, repeating. We need a mask
2753 // that will apply equally to all members of the vector, so AND all the
2754 // lanes of the constant together.
2755 EVT VT = Vector->getValueType(0);
2756 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2758 // If the splat value has been compressed to a bitlength lower
2759 // than the size of the vector lane, we need to re-expand it to
2761 if (BitWidth > SplatBitSize)
2762 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2763 SplatBitSize < BitWidth;
2764 SplatBitSize = SplatBitSize * 2)
2765 SplatValue |= SplatValue.shl(SplatBitSize);
2767 Constant = APInt::getAllOnesValue(BitWidth);
2768 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2769 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2773 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2774 // actually legal and isn't going to get expanded, else this is a false
2776 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2777 Load->getMemoryVT());
2779 // Resize the constant to the same size as the original memory access before
2780 // extension. If it is still the AllOnesValue then this AND is completely
2783 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2786 switch (Load->getExtensionType()) {
2787 default: B = false; break;
2788 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2790 case ISD::NON_EXTLOAD: B = true; break;
2793 if (B && Constant.isAllOnesValue()) {
2794 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2795 // preserve semantics once we get rid of the AND.
2796 SDValue NewLoad(Load, 0);
2797 if (Load->getExtensionType() == ISD::EXTLOAD) {
2798 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2799 Load->getValueType(0), SDLoc(Load),
2800 Load->getChain(), Load->getBasePtr(),
2801 Load->getOffset(), Load->getMemoryVT(),
2802 Load->getMemOperand());
2803 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2804 if (Load->getNumValues() == 3) {
2805 // PRE/POST_INC loads have 3 values.
2806 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2807 NewLoad.getValue(2) };
2808 CombineTo(Load, To, 3, true);
2810 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2814 // Fold the AND away, taking care not to fold to the old load node if we
2816 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2818 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2821 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2822 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2823 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2824 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2826 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2827 LL.getValueType().isInteger()) {
2828 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2829 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2830 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2831 LR.getValueType(), LL, RL);
2832 AddToWorklist(ORNode.getNode());
2833 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2835 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2836 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2837 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2838 LR.getValueType(), LL, RL);
2839 AddToWorklist(ANDNode.getNode());
2840 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
2842 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2843 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2844 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2845 LR.getValueType(), LL, RL);
2846 AddToWorklist(ORNode.getNode());
2847 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2850 // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
2851 if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
2852 Op0 == Op1 && LL.getValueType().isInteger() &&
2853 Op0 == ISD::SETNE && ((cast<ConstantSDNode>(LR)->isNullValue() &&
2854 cast<ConstantSDNode>(RR)->isAllOnesValue()) ||
2855 (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2856 cast<ConstantSDNode>(RR)->isNullValue()))) {
2857 SDValue ADDNode = DAG.getNode(ISD::ADD, SDLoc(N0), LL.getValueType(),
2858 LL, DAG.getConstant(1, LL.getValueType()));
2859 AddToWorklist(ADDNode.getNode());
2860 return DAG.getSetCC(SDLoc(N), VT, ADDNode,
2861 DAG.getConstant(2, LL.getValueType()), ISD::SETUGE);
2863 // canonicalize equivalent to ll == rl
2864 if (LL == RR && LR == RL) {
2865 Op1 = ISD::getSetCCSwappedOperands(Op1);
2868 if (LL == RL && LR == RR) {
2869 bool isInteger = LL.getValueType().isInteger();
2870 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2871 if (Result != ISD::SETCC_INVALID &&
2872 (!LegalOperations ||
2873 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
2874 TLI.isOperationLegal(ISD::SETCC,
2875 getSetCCResultType(N0.getSimpleValueType())))))
2876 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
2881 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2882 if (N0.getOpcode() == N1.getOpcode()) {
2883 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2884 if (Tmp.getNode()) return Tmp;
2887 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2888 // fold (and (sra)) -> (and (srl)) when possible.
2889 if (!VT.isVector() &&
2890 SimplifyDemandedBits(SDValue(N, 0)))
2891 return SDValue(N, 0);
2893 // fold (zext_inreg (extload x)) -> (zextload x)
2894 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2895 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2896 EVT MemVT = LN0->getMemoryVT();
2897 // If we zero all the possible extended bits, then we can turn this into
2898 // a zextload if we are running before legalize or the operation is legal.
2899 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2900 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2901 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2902 ((!LegalOperations && !LN0->isVolatile()) ||
2903 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2904 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2905 LN0->getChain(), LN0->getBasePtr(),
2906 MemVT, LN0->getMemOperand());
2908 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2909 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2912 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2913 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2915 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2916 EVT MemVT = LN0->getMemoryVT();
2917 // If we zero all the possible extended bits, then we can turn this into
2918 // a zextload if we are running before legalize or the operation is legal.
2919 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2920 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2921 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2922 ((!LegalOperations && !LN0->isVolatile()) ||
2923 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2924 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2925 LN0->getChain(), LN0->getBasePtr(),
2926 MemVT, LN0->getMemOperand());
2928 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2929 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2933 // fold (and (load x), 255) -> (zextload x, i8)
2934 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2935 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2936 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2937 (N0.getOpcode() == ISD::ANY_EXTEND &&
2938 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2939 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2940 LoadSDNode *LN0 = HasAnyExt
2941 ? cast<LoadSDNode>(N0.getOperand(0))
2942 : cast<LoadSDNode>(N0);
2943 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2944 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) {
2945 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2946 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2947 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2948 EVT LoadedVT = LN0->getMemoryVT();
2950 if (ExtVT == LoadedVT &&
2951 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2952 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2955 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2956 LN0->getChain(), LN0->getBasePtr(), ExtVT,
2957 LN0->getMemOperand());
2959 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2960 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2963 // Do not change the width of a volatile load.
2964 // Do not generate loads of non-round integer types since these can
2965 // be expensive (and would be wrong if the type is not byte sized).
2966 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2967 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2968 EVT PtrType = LN0->getOperand(1).getValueType();
2970 unsigned Alignment = LN0->getAlignment();
2971 SDValue NewPtr = LN0->getBasePtr();
2973 // For big endian targets, we need to add an offset to the pointer
2974 // to load the correct bytes. For little endian systems, we merely
2975 // need to read fewer bytes from the same pointer.
2976 if (TLI.isBigEndian()) {
2977 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2978 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2979 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2980 NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0), PtrType,
2981 NewPtr, DAG.getConstant(PtrOff, PtrType));
2982 Alignment = MinAlign(Alignment, PtrOff);
2985 AddToWorklist(NewPtr.getNode());
2987 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2989 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2990 LN0->getChain(), NewPtr,
2991 LN0->getPointerInfo(),
2992 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2993 LN0->isInvariant(), Alignment, LN0->getAAInfo());
2995 CombineTo(LN0, Load, Load.getValue(1));
2996 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3002 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
3003 VT.getSizeInBits() <= 64) {
3004 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3005 APInt ADDC = ADDI->getAPIntValue();
3006 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
3007 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
3008 // immediate for an add, but it is legal if its top c2 bits are set,
3009 // transform the ADD so the immediate doesn't need to be materialized
3011 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
3012 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3013 SRLI->getZExtValue());
3014 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
3016 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
3018 DAG.getNode(ISD::ADD, SDLoc(N0), VT,
3019 N0.getOperand(0), DAG.getConstant(ADDC, VT));
3020 CombineTo(N0.getNode(), NewAdd);
3021 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3029 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
3030 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
3031 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
3032 N0.getOperand(1), false);
3033 if (BSwap.getNode())
3040 /// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
3041 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
3042 bool DemandHighBits) {
3043 if (!LegalOperations)
3046 EVT VT = N->getValueType(0);
3047 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
3049 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3052 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
3053 bool LookPassAnd0 = false;
3054 bool LookPassAnd1 = false;
3055 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
3057 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
3059 if (N0.getOpcode() == ISD::AND) {
3060 if (!N0.getNode()->hasOneUse())
3062 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3063 if (!N01C || N01C->getZExtValue() != 0xFF00)
3065 N0 = N0.getOperand(0);
3066 LookPassAnd0 = true;
3069 if (N1.getOpcode() == ISD::AND) {
3070 if (!N1.getNode()->hasOneUse())
3072 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3073 if (!N11C || N11C->getZExtValue() != 0xFF)
3075 N1 = N1.getOperand(0);
3076 LookPassAnd1 = true;
3079 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
3081 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
3083 if (!N0.getNode()->hasOneUse() ||
3084 !N1.getNode()->hasOneUse())
3087 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3088 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3091 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
3094 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
3095 SDValue N00 = N0->getOperand(0);
3096 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
3097 if (!N00.getNode()->hasOneUse())
3099 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
3100 if (!N001C || N001C->getZExtValue() != 0xFF)
3102 N00 = N00.getOperand(0);
3103 LookPassAnd0 = true;
3106 SDValue N10 = N1->getOperand(0);
3107 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
3108 if (!N10.getNode()->hasOneUse())
3110 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
3111 if (!N101C || N101C->getZExtValue() != 0xFF00)
3113 N10 = N10.getOperand(0);
3114 LookPassAnd1 = true;
3120 // Make sure everything beyond the low halfword gets set to zero since the SRL
3121 // 16 will clear the top bits.
3122 unsigned OpSizeInBits = VT.getSizeInBits();
3123 if (DemandHighBits && OpSizeInBits > 16) {
3124 // If the left-shift isn't masked out then the only way this is a bswap is
3125 // if all bits beyond the low 8 are 0. In that case the entire pattern
3126 // reduces to a left shift anyway: leave it for other parts of the combiner.
3130 // However, if the right shift isn't masked out then it might be because
3131 // it's not needed. See if we can spot that too.
3132 if (!LookPassAnd1 &&
3133 !DAG.MaskedValueIsZero(
3134 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
3138 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
3139 if (OpSizeInBits > 16)
3140 Res = DAG.getNode(ISD::SRL, SDLoc(N), VT, Res,
3141 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
3145 /// Return true if the specified node is an element that makes up a 32-bit
3146 /// packed halfword byteswap.
3147 /// ((x & 0x000000ff) << 8) |
3148 /// ((x & 0x0000ff00) >> 8) |
3149 /// ((x & 0x00ff0000) << 8) |
3150 /// ((x & 0xff000000) >> 8)
3151 static bool isBSwapHWordElement(SDValue N, SmallVectorImpl<SDNode *> &Parts) {
3152 if (!N.getNode()->hasOneUse())
3155 unsigned Opc = N.getOpcode();
3156 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
3159 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3164 switch (N1C->getZExtValue()) {
3167 case 0xFF: Num = 0; break;
3168 case 0xFF00: Num = 1; break;
3169 case 0xFF0000: Num = 2; break;
3170 case 0xFF000000: Num = 3; break;
3173 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
3174 SDValue N0 = N.getOperand(0);
3175 if (Opc == ISD::AND) {
3176 if (Num == 0 || Num == 2) {
3178 // (x >> 8) & 0xff0000
3179 if (N0.getOpcode() != ISD::SRL)
3181 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3182 if (!C || C->getZExtValue() != 8)
3185 // (x << 8) & 0xff00
3186 // (x << 8) & 0xff000000
3187 if (N0.getOpcode() != ISD::SHL)
3189 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3190 if (!C || C->getZExtValue() != 8)
3193 } else if (Opc == ISD::SHL) {
3195 // (x & 0xff0000) << 8
3196 if (Num != 0 && Num != 2)
3198 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3199 if (!C || C->getZExtValue() != 8)
3201 } else { // Opc == ISD::SRL
3202 // (x & 0xff00) >> 8
3203 // (x & 0xff000000) >> 8
3204 if (Num != 1 && Num != 3)
3206 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3207 if (!C || C->getZExtValue() != 8)
3214 Parts[Num] = N0.getOperand(0).getNode();
3218 /// Match a 32-bit packed halfword bswap. That is
3219 /// ((x & 0x000000ff) << 8) |
3220 /// ((x & 0x0000ff00) >> 8) |
3221 /// ((x & 0x00ff0000) << 8) |
3222 /// ((x & 0xff000000) >> 8)
3223 /// => (rotl (bswap x), 16)
3224 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
3225 if (!LegalOperations)
3228 EVT VT = N->getValueType(0);
3231 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3234 SmallVector<SDNode*,4> Parts(4, (SDNode*)nullptr);
3236 // (or (or (and), (and)), (or (and), (and)))
3237 // (or (or (or (and), (and)), (and)), (and))
3238 if (N0.getOpcode() != ISD::OR)
3240 SDValue N00 = N0.getOperand(0);
3241 SDValue N01 = N0.getOperand(1);
3243 if (N1.getOpcode() == ISD::OR &&
3244 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
3245 // (or (or (and), (and)), (or (and), (and)))
3246 SDValue N000 = N00.getOperand(0);
3247 if (!isBSwapHWordElement(N000, Parts))
3250 SDValue N001 = N00.getOperand(1);
3251 if (!isBSwapHWordElement(N001, Parts))
3253 SDValue N010 = N01.getOperand(0);
3254 if (!isBSwapHWordElement(N010, Parts))
3256 SDValue N011 = N01.getOperand(1);
3257 if (!isBSwapHWordElement(N011, Parts))
3260 // (or (or (or (and), (and)), (and)), (and))
3261 if (!isBSwapHWordElement(N1, Parts))
3263 if (!isBSwapHWordElement(N01, Parts))
3265 if (N00.getOpcode() != ISD::OR)
3267 SDValue N000 = N00.getOperand(0);
3268 if (!isBSwapHWordElement(N000, Parts))
3270 SDValue N001 = N00.getOperand(1);
3271 if (!isBSwapHWordElement(N001, Parts))
3275 // Make sure the parts are all coming from the same node.
3276 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3279 SDValue BSwap = DAG.getNode(ISD::BSWAP, SDLoc(N), VT,
3280 SDValue(Parts[0],0));
3282 // Result of the bswap should be rotated by 16. If it's not legal, then
3283 // do (x << 16) | (x >> 16).
3284 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
3285 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3286 return DAG.getNode(ISD::ROTL, SDLoc(N), VT, BSwap, ShAmt);
3287 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3288 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, BSwap, ShAmt);
3289 return DAG.getNode(ISD::OR, SDLoc(N), VT,
3290 DAG.getNode(ISD::SHL, SDLoc(N), VT, BSwap, ShAmt),
3291 DAG.getNode(ISD::SRL, SDLoc(N), VT, BSwap, ShAmt));
3294 SDValue DAGCombiner::visitOR(SDNode *N) {
3295 SDValue N0 = N->getOperand(0);
3296 SDValue N1 = N->getOperand(1);
3297 SDValue LL, LR, RL, RR, CC0, CC1;
3298 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3299 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3300 EVT VT = N1.getValueType();
3303 if (VT.isVector()) {
3304 SDValue FoldedVOp = SimplifyVBinOp(N);
3305 if (FoldedVOp.getNode()) return FoldedVOp;
3307 // fold (or x, 0) -> x, vector edition
3308 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3310 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3313 // fold (or x, -1) -> -1, vector edition
3314 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3316 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3319 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
3320 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
3321 // Do this only if the resulting shuffle is legal.
3322 if (isa<ShuffleVectorSDNode>(N0) &&
3323 isa<ShuffleVectorSDNode>(N1) &&
3324 // Avoid folding a node with illegal type.
3325 TLI.isTypeLegal(VT) &&
3326 N0->getOperand(1) == N1->getOperand(1) &&
3327 ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode())) {
3328 bool CanFold = true;
3329 unsigned NumElts = VT.getVectorNumElements();
3330 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
3331 const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
3332 // We construct two shuffle masks:
3333 // - Mask1 is a shuffle mask for a shuffle with N0 as the first operand
3334 // and N1 as the second operand.
3335 // - Mask2 is a shuffle mask for a shuffle with N1 as the first operand
3336 // and N0 as the second operand.
3337 // We do this because OR is commutable and therefore there might be
3338 // two ways to fold this node into a shuffle.
3339 SmallVector<int,4> Mask1;
3340 SmallVector<int,4> Mask2;
3342 for (unsigned i = 0; i != NumElts && CanFold; ++i) {
3343 int M0 = SV0->getMaskElt(i);
3344 int M1 = SV1->getMaskElt(i);
3346 // Both shuffle indexes are undef. Propagate Undef.
3347 if (M0 < 0 && M1 < 0) {
3348 Mask1.push_back(M0);
3349 Mask2.push_back(M0);
3353 if (M0 < 0 || M1 < 0 ||
3354 (M0 < (int)NumElts && M1 < (int)NumElts) ||
3355 (M0 >= (int)NumElts && M1 >= (int)NumElts)) {
3360 Mask1.push_back(M0 < (int)NumElts ? M0 : M1 + NumElts);
3361 Mask2.push_back(M1 < (int)NumElts ? M1 : M0 + NumElts);
3365 // Fold this sequence only if the resulting shuffle is 'legal'.
3366 if (TLI.isShuffleMaskLegal(Mask1, VT))
3367 return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0),
3368 N1->getOperand(0), &Mask1[0]);
3369 if (TLI.isShuffleMaskLegal(Mask2, VT))
3370 return DAG.getVectorShuffle(VT, SDLoc(N), N1->getOperand(0),
3371 N0->getOperand(0), &Mask2[0]);
3376 // fold (or x, undef) -> -1
3377 if (!LegalOperations &&
3378 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3379 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3380 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3382 // fold (or c1, c2) -> c1|c2
3384 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3385 // canonicalize constant to RHS
3387 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3388 // fold (or x, 0) -> x
3389 if (N1C && N1C->isNullValue())
3391 // fold (or x, -1) -> -1
3392 if (N1C && N1C->isAllOnesValue())
3394 // fold (or x, c) -> c iff (x & ~c) == 0
3395 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3398 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3399 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3400 if (BSwap.getNode())
3402 BSwap = MatchBSwapHWordLow(N, N0, N1);
3403 if (BSwap.getNode())
3407 SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1);
3410 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3411 // iff (c1 & c2) == 0.
3412 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3413 isa<ConstantSDNode>(N0.getOperand(1))) {
3414 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3415 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) {
3416 SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1);
3419 return DAG.getNode(ISD::AND, SDLoc(N), VT,
3420 DAG.getNode(ISD::OR, SDLoc(N0), VT,
3421 N0.getOperand(0), N1), COR);
3424 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3425 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3426 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3427 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3429 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3430 LL.getValueType().isInteger()) {
3431 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3432 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3433 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3434 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3435 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR),
3436 LR.getValueType(), LL, RL);
3437 AddToWorklist(ORNode.getNode());
3438 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
3440 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3441 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3442 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3443 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3444 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR),
3445 LR.getValueType(), LL, RL);
3446 AddToWorklist(ANDNode.getNode());
3447 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
3450 // canonicalize equivalent to ll == rl
3451 if (LL == RR && LR == RL) {
3452 Op1 = ISD::getSetCCSwappedOperands(Op1);
3455 if (LL == RL && LR == RR) {
3456 bool isInteger = LL.getValueType().isInteger();
3457 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3458 if (Result != ISD::SETCC_INVALID &&
3459 (!LegalOperations ||
3460 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
3461 TLI.isOperationLegal(ISD::SETCC,
3462 getSetCCResultType(N0.getValueType())))))
3463 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
3468 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3469 if (N0.getOpcode() == N1.getOpcode()) {
3470 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3471 if (Tmp.getNode()) return Tmp;
3474 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3475 if (N0.getOpcode() == ISD::AND &&
3476 N1.getOpcode() == ISD::AND &&
3477 N0.getOperand(1).getOpcode() == ISD::Constant &&
3478 N1.getOperand(1).getOpcode() == ISD::Constant &&
3479 // Don't increase # computations.
3480 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3481 // We can only do this xform if we know that bits from X that are set in C2
3482 // but not in C1 are already zero. Likewise for Y.
3483 const APInt &LHSMask =
3484 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3485 const APInt &RHSMask =
3486 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3488 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3489 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3490 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3491 N0.getOperand(0), N1.getOperand(0));
3492 return DAG.getNode(ISD::AND, SDLoc(N), VT, X,
3493 DAG.getConstant(LHSMask | RHSMask, VT));
3497 // See if this is some rotate idiom.
3498 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
3499 return SDValue(Rot, 0);
3501 // Simplify the operands using demanded-bits information.
3502 if (!VT.isVector() &&
3503 SimplifyDemandedBits(SDValue(N, 0)))
3504 return SDValue(N, 0);
3509 /// Match "(X shl/srl V1) & V2" where V2 may not be present.
3510 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3511 if (Op.getOpcode() == ISD::AND) {
3512 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3513 Mask = Op.getOperand(1);
3514 Op = Op.getOperand(0);
3520 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3528 // Return true if we can prove that, whenever Neg and Pos are both in the
3529 // range [0, OpSize), Neg == (Pos == 0 ? 0 : OpSize - Pos). This means that
3530 // for two opposing shifts shift1 and shift2 and a value X with OpBits bits:
3532 // (or (shift1 X, Neg), (shift2 X, Pos))
3534 // reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate
3535 // in direction shift1 by Neg. The range [0, OpSize) means that we only need
3536 // to consider shift amounts with defined behavior.
3537 static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
3538 // If OpSize is a power of 2 then:
3540 // (a) (Pos == 0 ? 0 : OpSize - Pos) == (OpSize - Pos) & (OpSize - 1)
3541 // (b) Neg == Neg & (OpSize - 1) whenever Neg is in [0, OpSize).
3543 // So if OpSize is a power of 2 and Neg is (and Neg', OpSize-1), we check
3544 // for the stronger condition:
3546 // Neg & (OpSize - 1) == (OpSize - Pos) & (OpSize - 1) [A]
3548 // for all Neg and Pos. Since Neg & (OpSize - 1) == Neg' & (OpSize - 1)
3549 // we can just replace Neg with Neg' for the rest of the function.
3551 // In other cases we check for the even stronger condition:
3553 // Neg == OpSize - Pos [B]
3555 // for all Neg and Pos. Note that the (or ...) then invokes undefined
3556 // behavior if Pos == 0 (and consequently Neg == OpSize).
3558 // We could actually use [A] whenever OpSize is a power of 2, but the
3559 // only extra cases that it would match are those uninteresting ones
3560 // where Neg and Pos are never in range at the same time. E.g. for
3561 // OpSize == 32, using [A] would allow a Neg of the form (sub 64, Pos)
3562 // as well as (sub 32, Pos), but:
3564 // (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos))
3566 // always invokes undefined behavior for 32-bit X.
3568 // Below, Mask == OpSize - 1 when using [A] and is all-ones otherwise.
3569 unsigned MaskLoBits = 0;
3570 if (Neg.getOpcode() == ISD::AND &&
3571 isPowerOf2_64(OpSize) &&
3572 Neg.getOperand(1).getOpcode() == ISD::Constant &&
3573 cast<ConstantSDNode>(Neg.getOperand(1))->getAPIntValue() == OpSize - 1) {
3574 Neg = Neg.getOperand(0);
3575 MaskLoBits = Log2_64(OpSize);
3578 // Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
3579 if (Neg.getOpcode() != ISD::SUB)
3581 ConstantSDNode *NegC = dyn_cast<ConstantSDNode>(Neg.getOperand(0));
3584 SDValue NegOp1 = Neg.getOperand(1);
3586 // On the RHS of [A], if Pos is Pos' & (OpSize - 1), just replace Pos with
3587 // Pos'. The truncation is redundant for the purpose of the equality.
3589 Pos.getOpcode() == ISD::AND &&
3590 Pos.getOperand(1).getOpcode() == ISD::Constant &&
3591 cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() == OpSize - 1)
3592 Pos = Pos.getOperand(0);
3594 // The condition we need is now:
3596 // (NegC - NegOp1) & Mask == (OpSize - Pos) & Mask
3598 // If NegOp1 == Pos then we need:
3600 // OpSize & Mask == NegC & Mask
3602 // (because "x & Mask" is a truncation and distributes through subtraction).
3605 Width = NegC->getAPIntValue();
3606 // Check for cases where Pos has the form (add NegOp1, PosC) for some PosC.
3607 // Then the condition we want to prove becomes:
3609 // (NegC - NegOp1) & Mask == (OpSize - (NegOp1 + PosC)) & Mask
3611 // which, again because "x & Mask" is a truncation, becomes:
3613 // NegC & Mask == (OpSize - PosC) & Mask
3614 // OpSize & Mask == (NegC + PosC) & Mask
3615 else if (Pos.getOpcode() == ISD::ADD &&
3616 Pos.getOperand(0) == NegOp1 &&
3617 Pos.getOperand(1).getOpcode() == ISD::Constant)
3618 Width = (cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() +
3619 NegC->getAPIntValue());
3623 // Now we just need to check that OpSize & Mask == Width & Mask.
3625 // Opsize & Mask is 0 since Mask is Opsize - 1.
3626 return Width.getLoBits(MaskLoBits) == 0;
3627 return Width == OpSize;
3630 // A subroutine of MatchRotate used once we have found an OR of two opposite
3631 // shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
3632 // to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
3633 // former being preferred if supported. InnerPos and InnerNeg are Pos and
3634 // Neg with outer conversions stripped away.
3635 SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
3636 SDValue Neg, SDValue InnerPos,
3637 SDValue InnerNeg, unsigned PosOpcode,
3638 unsigned NegOpcode, SDLoc DL) {
3639 // fold (or (shl x, (*ext y)),
3640 // (srl x, (*ext (sub 32, y)))) ->
3641 // (rotl x, y) or (rotr x, (sub 32, y))
3643 // fold (or (shl x, (*ext (sub 32, y))),
3644 // (srl x, (*ext y))) ->
3645 // (rotr x, y) or (rotl x, (sub 32, y))
3646 EVT VT = Shifted.getValueType();
3647 if (matchRotateSub(InnerPos, InnerNeg, VT.getSizeInBits())) {
3648 bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
3649 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
3650 HasPos ? Pos : Neg).getNode();
3656 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3657 // idioms for rotate, and if the target supports rotation instructions, generate
3659 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
3660 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3661 EVT VT = LHS.getValueType();
3662 if (!TLI.isTypeLegal(VT)) return nullptr;
3664 // The target must have at least one rotate flavor.
3665 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3666 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3667 if (!HasROTL && !HasROTR) return nullptr;
3669 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3670 SDValue LHSShift; // The shift.
3671 SDValue LHSMask; // AND value if any.
3672 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3673 return nullptr; // Not part of a rotate.
3675 SDValue RHSShift; // The shift.
3676 SDValue RHSMask; // AND value if any.
3677 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3678 return nullptr; // Not part of a rotate.
3680 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3681 return nullptr; // Not shifting the same value.
3683 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3684 return nullptr; // Shifts must disagree.
3686 // Canonicalize shl to left side in a shl/srl pair.
3687 if (RHSShift.getOpcode() == ISD::SHL) {
3688 std::swap(LHS, RHS);
3689 std::swap(LHSShift, RHSShift);
3690 std::swap(LHSMask , RHSMask );
3693 unsigned OpSizeInBits = VT.getSizeInBits();
3694 SDValue LHSShiftArg = LHSShift.getOperand(0);
3695 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3696 SDValue RHSShiftArg = RHSShift.getOperand(0);
3697 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3699 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3700 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3701 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3702 RHSShiftAmt.getOpcode() == ISD::Constant) {
3703 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3704 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3705 if ((LShVal + RShVal) != OpSizeInBits)
3708 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3709 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3711 // If there is an AND of either shifted operand, apply it to the result.
3712 if (LHSMask.getNode() || RHSMask.getNode()) {
3713 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3715 if (LHSMask.getNode()) {
3716 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3717 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3719 if (RHSMask.getNode()) {
3720 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3721 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3724 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3727 return Rot.getNode();
3730 // If there is a mask here, and we have a variable shift, we can't be sure
3731 // that we're masking out the right stuff.
3732 if (LHSMask.getNode() || RHSMask.getNode())
3735 // If the shift amount is sign/zext/any-extended just peel it off.
3736 SDValue LExtOp0 = LHSShiftAmt;
3737 SDValue RExtOp0 = RHSShiftAmt;
3738 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3739 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3740 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3741 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3742 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3743 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3744 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3745 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3746 LExtOp0 = LHSShiftAmt.getOperand(0);
3747 RExtOp0 = RHSShiftAmt.getOperand(0);
3750 SDNode *TryL = MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt,
3751 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
3755 SDNode *TryR = MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
3756 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
3763 SDValue DAGCombiner::visitXOR(SDNode *N) {
3764 SDValue N0 = N->getOperand(0);
3765 SDValue N1 = N->getOperand(1);
3766 SDValue LHS, RHS, CC;
3767 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3768 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3769 EVT VT = N0.getValueType();
3772 if (VT.isVector()) {
3773 SDValue FoldedVOp = SimplifyVBinOp(N);
3774 if (FoldedVOp.getNode()) return FoldedVOp;
3776 // fold (xor x, 0) -> x, vector edition
3777 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3779 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3783 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3784 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3785 return DAG.getConstant(0, VT);
3786 // fold (xor x, undef) -> undef
3787 if (N0.getOpcode() == ISD::UNDEF)
3789 if (N1.getOpcode() == ISD::UNDEF)
3791 // fold (xor c1, c2) -> c1^c2
3793 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3794 // canonicalize constant to RHS
3796 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3797 // fold (xor x, 0) -> x
3798 if (N1C && N1C->isNullValue())
3801 SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1);
3805 // fold !(x cc y) -> (x !cc y)
3806 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3807 bool isInt = LHS.getValueType().isInteger();
3808 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3811 if (!LegalOperations ||
3812 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
3813 switch (N0.getOpcode()) {
3815 llvm_unreachable("Unhandled SetCC Equivalent!");
3817 return DAG.getSetCC(SDLoc(N), VT, LHS, RHS, NotCC);
3818 case ISD::SELECT_CC:
3819 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2),
3820 N0.getOperand(3), NotCC);
3825 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3826 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3827 N0.getNode()->hasOneUse() &&
3828 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3829 SDValue V = N0.getOperand(0);
3830 V = DAG.getNode(ISD::XOR, SDLoc(N0), V.getValueType(), V,
3831 DAG.getConstant(1, V.getValueType()));
3832 AddToWorklist(V.getNode());
3833 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V);
3836 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3837 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3838 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3839 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3840 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3841 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3842 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3843 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3844 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
3845 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3848 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3849 if (N1C && N1C->isAllOnesValue() &&
3850 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3851 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3852 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3853 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3854 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3855 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3856 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
3857 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3860 // fold (xor (and x, y), y) -> (and (not x), y)
3861 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3862 N0->getOperand(1) == N1) {
3863 SDValue X = N0->getOperand(0);
3864 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT);
3865 AddToWorklist(NotX.getNode());
3866 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1);
3868 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3869 if (N1C && N0.getOpcode() == ISD::XOR) {
3870 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3871 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3873 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(1),
3874 DAG.getConstant(N1C->getAPIntValue() ^
3875 N00C->getAPIntValue(), VT));
3877 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(0),
3878 DAG.getConstant(N1C->getAPIntValue() ^
3879 N01C->getAPIntValue(), VT));
3881 // fold (xor x, x) -> 0
3883 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
3885 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3886 if (N0.getOpcode() == N1.getOpcode()) {
3887 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3888 if (Tmp.getNode()) return Tmp;
3891 // Simplify the expression using non-local knowledge.
3892 if (!VT.isVector() &&
3893 SimplifyDemandedBits(SDValue(N, 0)))
3894 return SDValue(N, 0);
3899 /// Handle transforms common to the three shifts, when the shift amount is a
3901 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, ConstantSDNode *Amt) {
3902 // We can't and shouldn't fold opaque constants.
3903 if (Amt->isOpaque())
3906 SDNode *LHS = N->getOperand(0).getNode();
3907 if (!LHS->hasOneUse()) return SDValue();
3909 // We want to pull some binops through shifts, so that we have (and (shift))
3910 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3911 // thing happens with address calculations, so it's important to canonicalize
3913 bool HighBitSet = false; // Can we transform this if the high bit is set?
3915 switch (LHS->getOpcode()) {
3916 default: return SDValue();
3919 HighBitSet = false; // We can only transform sra if the high bit is clear.
3922 HighBitSet = true; // We can only transform sra if the high bit is set.
3925 if (N->getOpcode() != ISD::SHL)
3926 return SDValue(); // only shl(add) not sr[al](add).
3927 HighBitSet = false; // We can only transform sra if the high bit is clear.
3931 // We require the RHS of the binop to be a constant and not opaque as well.
3932 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3933 if (!BinOpCst || BinOpCst->isOpaque()) return SDValue();
3935 // FIXME: disable this unless the input to the binop is a shift by a constant.
3936 // If it is not a shift, it pessimizes some common cases like:
3938 // void foo(int *X, int i) { X[i & 1235] = 1; }
3939 // int bar(int *X, int i) { return X[i & 255]; }
3940 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3941 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3942 BinOpLHSVal->getOpcode() != ISD::SRA &&
3943 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3944 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3947 EVT VT = N->getValueType(0);
3949 // If this is a signed shift right, and the high bit is modified by the
3950 // logical operation, do not perform the transformation. The highBitSet
3951 // boolean indicates the value of the high bit of the constant which would
3952 // cause it to be modified for this operation.
3953 if (N->getOpcode() == ISD::SRA) {
3954 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3955 if (BinOpRHSSignSet != HighBitSet)
3959 if (!TLI.isDesirableToCommuteWithShift(LHS))
3962 // Fold the constants, shifting the binop RHS by the shift amount.
3963 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)),
3965 LHS->getOperand(1), N->getOperand(1));
3966 assert(isa<ConstantSDNode>(NewRHS) && "Folding was not successful!");
3968 // Create the new shift.
3969 SDValue NewShift = DAG.getNode(N->getOpcode(),
3970 SDLoc(LHS->getOperand(0)),
3971 VT, LHS->getOperand(0), N->getOperand(1));
3973 // Create the new binop.
3974 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS);
3977 SDValue DAGCombiner::distributeTruncateThroughAnd(SDNode *N) {
3978 assert(N->getOpcode() == ISD::TRUNCATE);
3979 assert(N->getOperand(0).getOpcode() == ISD::AND);
3981 // (truncate:TruncVT (and N00, N01C)) -> (and (truncate:TruncVT N00), TruncC)
3982 if (N->hasOneUse() && N->getOperand(0).hasOneUse()) {
3983 SDValue N01 = N->getOperand(0).getOperand(1);
3985 if (ConstantSDNode *N01C = isConstOrConstSplat(N01)) {
3986 EVT TruncVT = N->getValueType(0);
3987 SDValue N00 = N->getOperand(0).getOperand(0);
3988 APInt TruncC = N01C->getAPIntValue();
3989 TruncC = TruncC.trunc(TruncVT.getScalarSizeInBits());
3991 return DAG.getNode(ISD::AND, SDLoc(N), TruncVT,
3992 DAG.getNode(ISD::TRUNCATE, SDLoc(N), TruncVT, N00),
3993 DAG.getConstant(TruncC, TruncVT));
4000 SDValue DAGCombiner::visitRotate(SDNode *N) {
4001 // fold (rot* x, (trunc (and y, c))) -> (rot* x, (and (trunc y), (trunc c))).
4002 if (N->getOperand(1).getOpcode() == ISD::TRUNCATE &&
4003 N->getOperand(1).getOperand(0).getOpcode() == ISD::AND) {
4004 SDValue NewOp1 = distributeTruncateThroughAnd(N->getOperand(1).getNode());
4005 if (NewOp1.getNode())
4006 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
4007 N->getOperand(0), NewOp1);
4012 SDValue DAGCombiner::visitSHL(SDNode *N) {
4013 SDValue N0 = N->getOperand(0);
4014 SDValue N1 = N->getOperand(1);
4015 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4016 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4017 EVT VT = N0.getValueType();
4018 unsigned OpSizeInBits = VT.getScalarSizeInBits();
4021 if (VT.isVector()) {
4022 SDValue FoldedVOp = SimplifyVBinOp(N);
4023 if (FoldedVOp.getNode()) return FoldedVOp;
4025 BuildVectorSDNode *N1CV = dyn_cast<BuildVectorSDNode>(N1);
4026 // If setcc produces all-one true value then:
4027 // (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV)
4028 if (N1CV && N1CV->isConstant()) {
4029 if (N0.getOpcode() == ISD::AND) {
4030 SDValue N00 = N0->getOperand(0);
4031 SDValue N01 = N0->getOperand(1);
4032 BuildVectorSDNode *N01CV = dyn_cast<BuildVectorSDNode>(N01);
4034 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
4035 TLI.getBooleanContents(N00.getOperand(0).getValueType()) ==
4036 TargetLowering::ZeroOrNegativeOneBooleanContent) {
4037 SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, VT, N01CV, N1CV);
4039 return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C);
4042 N1C = isConstOrConstSplat(N1);
4047 // fold (shl c1, c2) -> c1<<c2
4049 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
4050 // fold (shl 0, x) -> 0
4051 if (N0C && N0C->isNullValue())
4053 // fold (shl x, c >= size(x)) -> undef
4054 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4055 return DAG.getUNDEF(VT);
4056 // fold (shl x, 0) -> x
4057 if (N1C && N1C->isNullValue())
4059 // fold (shl undef, x) -> 0
4060 if (N0.getOpcode() == ISD::UNDEF)
4061 return DAG.getConstant(0, VT);
4062 // if (shl x, c) is known to be zero, return 0
4063 if (DAG.MaskedValueIsZero(SDValue(N, 0),
4064 APInt::getAllOnesValue(OpSizeInBits)))
4065 return DAG.getConstant(0, VT);
4066 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
4067 if (N1.getOpcode() == ISD::TRUNCATE &&
4068 N1.getOperand(0).getOpcode() == ISD::AND) {
4069 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4070 if (NewOp1.getNode())
4071 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1);
4074 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4075 return SDValue(N, 0);
4077 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
4078 if (N1C && N0.getOpcode() == ISD::SHL) {
4079 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4080 uint64_t c1 = N0C1->getZExtValue();
4081 uint64_t c2 = N1C->getZExtValue();
4082 if (c1 + c2 >= OpSizeInBits)
4083 return DAG.getConstant(0, VT);
4084 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4085 DAG.getConstant(c1 + c2, N1.getValueType()));
4089 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
4090 // For this to be valid, the second form must not preserve any of the bits
4091 // that are shifted out by the inner shift in the first form. This means
4092 // the outer shift size must be >= the number of bits added by the ext.
4093 // As a corollary, we don't care what kind of ext it is.
4094 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
4095 N0.getOpcode() == ISD::ANY_EXTEND ||
4096 N0.getOpcode() == ISD::SIGN_EXTEND) &&
4097 N0.getOperand(0).getOpcode() == ISD::SHL) {
4098 SDValue N0Op0 = N0.getOperand(0);
4099 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4100 uint64_t c1 = N0Op0C1->getZExtValue();
4101 uint64_t c2 = N1C->getZExtValue();
4102 EVT InnerShiftVT = N0Op0.getValueType();
4103 uint64_t InnerShiftSize = InnerShiftVT.getScalarSizeInBits();
4104 if (c2 >= OpSizeInBits - InnerShiftSize) {
4105 if (c1 + c2 >= OpSizeInBits)
4106 return DAG.getConstant(0, VT);
4107 return DAG.getNode(ISD::SHL, SDLoc(N0), VT,
4108 DAG.getNode(N0.getOpcode(), SDLoc(N0), VT,
4109 N0Op0->getOperand(0)),
4110 DAG.getConstant(c1 + c2, N1.getValueType()));
4115 // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
4116 // Only fold this if the inner zext has no other uses to avoid increasing
4117 // the total number of instructions.
4118 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
4119 N0.getOperand(0).getOpcode() == ISD::SRL) {
4120 SDValue N0Op0 = N0.getOperand(0);
4121 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4122 uint64_t c1 = N0Op0C1->getZExtValue();
4123 if (c1 < VT.getScalarSizeInBits()) {
4124 uint64_t c2 = N1C->getZExtValue();
4126 SDValue NewOp0 = N0.getOperand(0);
4127 EVT CountVT = NewOp0.getOperand(1).getValueType();
4128 SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), NewOp0.getValueType(),
4129 NewOp0, DAG.getConstant(c2, CountVT));
4130 AddToWorklist(NewSHL.getNode());
4131 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
4137 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
4138 // (and (srl x, (sub c1, c2), MASK)
4139 // Only fold this if the inner shift has no other uses -- if it does, folding
4140 // this will increase the total number of instructions.
4141 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4142 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4143 uint64_t c1 = N0C1->getZExtValue();
4144 if (c1 < OpSizeInBits) {
4145 uint64_t c2 = N1C->getZExtValue();
4146 APInt Mask = APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - c1);
4149 Mask = Mask.shl(c2 - c1);
4150 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4151 DAG.getConstant(c2 - c1, N1.getValueType()));
4153 Mask = Mask.lshr(c1 - c2);
4154 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4155 DAG.getConstant(c1 - c2, N1.getValueType()));
4157 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift,
4158 DAG.getConstant(Mask, VT));
4162 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
4163 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
4164 unsigned BitSize = VT.getScalarSizeInBits();
4165 SDValue HiBitsMask =
4166 DAG.getConstant(APInt::getHighBitsSet(BitSize,
4167 BitSize - N1C->getZExtValue()), VT);
4168 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4173 SDValue NewSHL = visitShiftByConstant(N, N1C);
4174 if (NewSHL.getNode())
4181 SDValue DAGCombiner::visitSRA(SDNode *N) {
4182 SDValue N0 = N->getOperand(0);
4183 SDValue N1 = N->getOperand(1);
4184 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4185 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4186 EVT VT = N0.getValueType();
4187 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4190 if (VT.isVector()) {
4191 SDValue FoldedVOp = SimplifyVBinOp(N);
4192 if (FoldedVOp.getNode()) return FoldedVOp;
4194 N1C = isConstOrConstSplat(N1);
4197 // fold (sra c1, c2) -> (sra c1, c2)
4199 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
4200 // fold (sra 0, x) -> 0
4201 if (N0C && N0C->isNullValue())
4203 // fold (sra -1, x) -> -1
4204 if (N0C && N0C->isAllOnesValue())
4206 // fold (sra x, (setge c, size(x))) -> undef
4207 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4208 return DAG.getUNDEF(VT);
4209 // fold (sra x, 0) -> x
4210 if (N1C && N1C->isNullValue())
4212 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
4214 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
4215 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
4216 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
4218 ExtVT = EVT::getVectorVT(*DAG.getContext(),
4219 ExtVT, VT.getVectorNumElements());
4220 if ((!LegalOperations ||
4221 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
4222 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
4223 N0.getOperand(0), DAG.getValueType(ExtVT));
4226 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
4227 if (N1C && N0.getOpcode() == ISD::SRA) {
4228 if (ConstantSDNode *C1 = isConstOrConstSplat(N0.getOperand(1))) {
4229 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
4230 if (Sum >= OpSizeInBits)
4231 Sum = OpSizeInBits - 1;
4232 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
4233 DAG.getConstant(Sum, N1.getValueType()));
4237 // fold (sra (shl X, m), (sub result_size, n))
4238 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
4239 // result_size - n != m.
4240 // If truncate is free for the target sext(shl) is likely to result in better
4242 if (N0.getOpcode() == ISD::SHL && N1C) {
4243 // Get the two constanst of the shifts, CN0 = m, CN = n.
4244 const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
4246 LLVMContext &Ctx = *DAG.getContext();
4247 // Determine what the truncate's result bitsize and type would be.
4248 EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - N1C->getZExtValue());
4251 TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorNumElements());
4253 // Determine the residual right-shift amount.
4254 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
4256 // If the shift is not a no-op (in which case this should be just a sign
4257 // extend already), the truncated to type is legal, sign_extend is legal
4258 // on that type, and the truncate to that type is both legal and free,
4259 // perform the transform.
4260 if ((ShiftAmt > 0) &&
4261 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
4262 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
4263 TLI.isTruncateFree(VT, TruncVT)) {
4265 SDValue Amt = DAG.getConstant(ShiftAmt,
4266 getShiftAmountTy(N0.getOperand(0).getValueType()));
4267 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT,
4268 N0.getOperand(0), Amt);
4269 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), TruncVT,
4271 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N),
4272 N->getValueType(0), Trunc);
4277 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
4278 if (N1.getOpcode() == ISD::TRUNCATE &&
4279 N1.getOperand(0).getOpcode() == ISD::AND) {
4280 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4281 if (NewOp1.getNode())
4282 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
4285 // fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
4286 // if c1 is equal to the number of bits the trunc removes
4287 if (N0.getOpcode() == ISD::TRUNCATE &&
4288 (N0.getOperand(0).getOpcode() == ISD::SRL ||
4289 N0.getOperand(0).getOpcode() == ISD::SRA) &&
4290 N0.getOperand(0).hasOneUse() &&
4291 N0.getOperand(0).getOperand(1).hasOneUse() &&
4293 SDValue N0Op0 = N0.getOperand(0);
4294 if (ConstantSDNode *LargeShift = isConstOrConstSplat(N0Op0.getOperand(1))) {
4295 unsigned LargeShiftVal = LargeShift->getZExtValue();
4296 EVT LargeVT = N0Op0.getValueType();
4298 if (LargeVT.getScalarSizeInBits() - OpSizeInBits == LargeShiftVal) {
4300 DAG.getConstant(LargeShiftVal + N1C->getZExtValue(),
4301 getShiftAmountTy(N0Op0.getOperand(0).getValueType()));
4302 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), LargeVT,
4303 N0Op0.getOperand(0), Amt);
4304 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, SRA);
4309 // Simplify, based on bits shifted out of the LHS.
4310 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4311 return SDValue(N, 0);
4314 // If the sign bit is known to be zero, switch this to a SRL.
4315 if (DAG.SignBitIsZero(N0))
4316 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
4319 SDValue NewSRA = visitShiftByConstant(N, N1C);
4320 if (NewSRA.getNode())
4327 SDValue DAGCombiner::visitSRL(SDNode *N) {
4328 SDValue N0 = N->getOperand(0);
4329 SDValue N1 = N->getOperand(1);
4330 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4331 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4332 EVT VT = N0.getValueType();
4333 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4336 if (VT.isVector()) {
4337 SDValue FoldedVOp = SimplifyVBinOp(N);
4338 if (FoldedVOp.getNode()) return FoldedVOp;
4340 N1C = isConstOrConstSplat(N1);
4343 // fold (srl c1, c2) -> c1 >>u c2
4345 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
4346 // fold (srl 0, x) -> 0
4347 if (N0C && N0C->isNullValue())
4349 // fold (srl x, c >= size(x)) -> undef
4350 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4351 return DAG.getUNDEF(VT);
4352 // fold (srl x, 0) -> x
4353 if (N1C && N1C->isNullValue())
4355 // if (srl x, c) is known to be zero, return 0
4356 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
4357 APInt::getAllOnesValue(OpSizeInBits)))
4358 return DAG.getConstant(0, VT);
4360 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
4361 if (N1C && N0.getOpcode() == ISD::SRL) {
4362 if (ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1))) {
4363 uint64_t c1 = N01C->getZExtValue();
4364 uint64_t c2 = N1C->getZExtValue();
4365 if (c1 + c2 >= OpSizeInBits)
4366 return DAG.getConstant(0, VT);
4367 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4368 DAG.getConstant(c1 + c2, N1.getValueType()));
4372 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
4373 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
4374 N0.getOperand(0).getOpcode() == ISD::SRL &&
4375 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
4377 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
4378 uint64_t c2 = N1C->getZExtValue();
4379 EVT InnerShiftVT = N0.getOperand(0).getValueType();
4380 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
4381 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
4382 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
4383 if (c1 + OpSizeInBits == InnerShiftSize) {
4384 if (c1 + c2 >= InnerShiftSize)
4385 return DAG.getConstant(0, VT);
4386 return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT,
4387 DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT,
4388 N0.getOperand(0)->getOperand(0),
4389 DAG.getConstant(c1 + c2, ShiftCountVT)));
4393 // fold (srl (shl x, c), c) -> (and x, cst2)
4394 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
4395 unsigned BitSize = N0.getScalarValueSizeInBits();
4396 if (BitSize <= 64) {
4397 uint64_t ShAmt = N1C->getZExtValue() + 64 - BitSize;
4398 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4399 DAG.getConstant(~0ULL >> ShAmt, VT));
4403 // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask)
4404 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4405 // Shifting in all undef bits?
4406 EVT SmallVT = N0.getOperand(0).getValueType();
4407 unsigned BitSize = SmallVT.getScalarSizeInBits();
4408 if (N1C->getZExtValue() >= BitSize)
4409 return DAG.getUNDEF(VT);
4411 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
4412 uint64_t ShiftAmt = N1C->getZExtValue();
4413 SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT,
4415 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
4416 AddToWorklist(SmallShift.getNode());
4417 APInt Mask = APInt::getAllOnesValue(OpSizeInBits).lshr(ShiftAmt);
4418 return DAG.getNode(ISD::AND, SDLoc(N), VT,
4419 DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift),
4420 DAG.getConstant(Mask, VT));
4424 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
4425 // bit, which is unmodified by sra.
4426 if (N1C && N1C->getZExtValue() + 1 == OpSizeInBits) {
4427 if (N0.getOpcode() == ISD::SRA)
4428 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
4431 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
4432 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4433 N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
4434 APInt KnownZero, KnownOne;
4435 DAG.computeKnownBits(N0.getOperand(0), KnownZero, KnownOne);
4437 // If any of the input bits are KnownOne, then the input couldn't be all
4438 // zeros, thus the result of the srl will always be zero.
4439 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
4441 // If all of the bits input the to ctlz node are known to be zero, then
4442 // the result of the ctlz is "32" and the result of the shift is one.
4443 APInt UnknownBits = ~KnownZero;
4444 if (UnknownBits == 0) return DAG.getConstant(1, VT);
4446 // Otherwise, check to see if there is exactly one bit input to the ctlz.
4447 if ((UnknownBits & (UnknownBits - 1)) == 0) {
4448 // Okay, we know that only that the single bit specified by UnknownBits
4449 // could be set on input to the CTLZ node. If this bit is set, the SRL
4450 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
4451 // to an SRL/XOR pair, which is likely to simplify more.
4452 unsigned ShAmt = UnknownBits.countTrailingZeros();
4453 SDValue Op = N0.getOperand(0);
4456 Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op,
4457 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
4458 AddToWorklist(Op.getNode());
4461 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
4462 Op, DAG.getConstant(1, VT));
4466 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
4467 if (N1.getOpcode() == ISD::TRUNCATE &&
4468 N1.getOperand(0).getOpcode() == ISD::AND) {
4469 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4470 if (NewOp1.getNode())
4471 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
4474 // fold operands of srl based on knowledge that the low bits are not
4476 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4477 return SDValue(N, 0);
4480 SDValue NewSRL = visitShiftByConstant(N, N1C);
4481 if (NewSRL.getNode())
4485 // Attempt to convert a srl of a load into a narrower zero-extending load.
4486 SDValue NarrowLoad = ReduceLoadWidth(N);
4487 if (NarrowLoad.getNode())
4490 // Here is a common situation. We want to optimize:
4493 // %b = and i32 %a, 2
4494 // %c = srl i32 %b, 1
4495 // brcond i32 %c ...
4501 // %c = setcc eq %b, 0
4504 // However when after the source operand of SRL is optimized into AND, the SRL
4505 // itself may not be optimized further. Look for it and add the BRCOND into
4507 if (N->hasOneUse()) {
4508 SDNode *Use = *N->use_begin();
4509 if (Use->getOpcode() == ISD::BRCOND)
4511 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4512 // Also look pass the truncate.
4513 Use = *Use->use_begin();
4514 if (Use->getOpcode() == ISD::BRCOND)
4522 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
4523 SDValue N0 = N->getOperand(0);
4524 EVT VT = N->getValueType(0);
4526 // fold (ctlz c1) -> c2
4527 if (isa<ConstantSDNode>(N0))
4528 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
4532 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
4533 SDValue N0 = N->getOperand(0);
4534 EVT VT = N->getValueType(0);
4536 // fold (ctlz_zero_undef c1) -> c2
4537 if (isa<ConstantSDNode>(N0))
4538 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4542 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4543 SDValue N0 = N->getOperand(0);
4544 EVT VT = N->getValueType(0);
4546 // fold (cttz c1) -> c2
4547 if (isa<ConstantSDNode>(N0))
4548 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
4552 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4553 SDValue N0 = N->getOperand(0);
4554 EVT VT = N->getValueType(0);
4556 // fold (cttz_zero_undef c1) -> c2
4557 if (isa<ConstantSDNode>(N0))
4558 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4562 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4563 SDValue N0 = N->getOperand(0);
4564 EVT VT = N->getValueType(0);
4566 // fold (ctpop c1) -> c2
4567 if (isa<ConstantSDNode>(N0))
4568 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
4572 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4573 SDValue N0 = N->getOperand(0);
4574 SDValue N1 = N->getOperand(1);
4575 SDValue N2 = N->getOperand(2);
4576 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4577 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4578 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4579 EVT VT = N->getValueType(0);
4580 EVT VT0 = N0.getValueType();
4582 // fold (select C, X, X) -> X
4585 // fold (select true, X, Y) -> X
4586 if (N0C && !N0C->isNullValue())
4588 // fold (select false, X, Y) -> Y
4589 if (N0C && N0C->isNullValue())
4591 // fold (select C, 1, X) -> (or C, X)
4592 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4593 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4594 // fold (select C, 0, 1) -> (xor C, 1)
4595 // We can't do this reliably if integer based booleans have different contents
4596 // to floating point based booleans. This is because we can't tell whether we
4597 // have an integer-based boolean or a floating-point-based boolean unless we
4598 // can find the SETCC that produced it and inspect its operands. This is
4599 // fairly easy if C is the SETCC node, but it can potentially be
4600 // undiscoverable (or not reasonably discoverable). For example, it could be
4601 // in another basic block or it could require searching a complicated
4603 if (VT.isInteger() &&
4604 (VT0 == MVT::i1 || (VT0.isInteger() &&
4605 TLI.getBooleanContents(false, false) ==
4606 TLI.getBooleanContents(false, true) &&
4607 TLI.getBooleanContents(false, false) ==
4608 TargetLowering::ZeroOrOneBooleanContent)) &&
4609 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4612 return DAG.getNode(ISD::XOR, SDLoc(N), VT0,
4613 N0, DAG.getConstant(1, VT0));
4614 XORNode = DAG.getNode(ISD::XOR, SDLoc(N0), VT0,
4615 N0, DAG.getConstant(1, VT0));
4616 AddToWorklist(XORNode.getNode());
4618 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, XORNode);
4619 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, XORNode);
4621 // fold (select C, 0, X) -> (and (not C), X)
4622 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4623 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4624 AddToWorklist(NOTNode.getNode());
4625 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2);
4627 // fold (select C, X, 1) -> (or (not C), X)
4628 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4629 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4630 AddToWorklist(NOTNode.getNode());
4631 return DAG.getNode(ISD::OR, SDLoc(N), VT, NOTNode, N1);
4633 // fold (select C, X, 0) -> (and C, X)
4634 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4635 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4636 // fold (select X, X, Y) -> (or X, Y)
4637 // fold (select X, 1, Y) -> (or X, Y)
4638 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4639 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4640 // fold (select X, Y, X) -> (and X, Y)
4641 // fold (select X, Y, 0) -> (and X, Y)
4642 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4643 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4645 // If we can fold this based on the true/false value, do so.
4646 if (SimplifySelectOps(N, N1, N2))
4647 return SDValue(N, 0); // Don't revisit N.
4649 // fold selects based on a setcc into other things, such as min/max/abs
4650 if (N0.getOpcode() == ISD::SETCC) {
4651 if ((!LegalOperations &&
4652 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) ||
4653 TLI.isOperationLegal(ISD::SELECT_CC, VT))
4654 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT,
4655 N0.getOperand(0), N0.getOperand(1),
4656 N1, N2, N0.getOperand(2));
4657 return SimplifySelect(SDLoc(N), N0, N1, N2);
4664 std::pair<SDValue, SDValue> SplitVSETCC(const SDNode *N, SelectionDAG &DAG) {
4667 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
4669 // Split the inputs.
4670 SDValue Lo, Hi, LL, LH, RL, RH;
4671 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
4672 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
4674 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
4675 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
4677 return std::make_pair(Lo, Hi);
4680 // This function assumes all the vselect's arguments are CONCAT_VECTOR
4681 // nodes and that the condition is a BV of ConstantSDNodes (or undefs).
4682 static SDValue ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) {
4684 SDValue Cond = N->getOperand(0);
4685 SDValue LHS = N->getOperand(1);
4686 SDValue RHS = N->getOperand(2);
4687 EVT VT = N->getValueType(0);
4688 int NumElems = VT.getVectorNumElements();
4689 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
4690 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
4691 Cond.getOpcode() == ISD::BUILD_VECTOR);
4693 // CONCAT_VECTOR can take an arbitrary number of arguments. We only care about
4694 // binary ones here.
4695 if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2)
4698 // We're sure we have an even number of elements due to the
4699 // concat_vectors we have as arguments to vselect.
4700 // Skip BV elements until we find one that's not an UNDEF
4701 // After we find an UNDEF element, keep looping until we get to half the
4702 // length of the BV and see if all the non-undef nodes are the same.
4703 ConstantSDNode *BottomHalf = nullptr;
4704 for (int i = 0; i < NumElems / 2; ++i) {
4705 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
4708 if (BottomHalf == nullptr)
4709 BottomHalf = cast<ConstantSDNode>(Cond.getOperand(i));
4710 else if (Cond->getOperand(i).getNode() != BottomHalf)
4714 // Do the same for the second half of the BuildVector
4715 ConstantSDNode *TopHalf = nullptr;
4716 for (int i = NumElems / 2; i < NumElems; ++i) {
4717 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
4720 if (TopHalf == nullptr)
4721 TopHalf = cast<ConstantSDNode>(Cond.getOperand(i));
4722 else if (Cond->getOperand(i).getNode() != TopHalf)
4726 assert(TopHalf && BottomHalf &&
4727 "One half of the selector was all UNDEFs and the other was all the "
4728 "same value. This should have been addressed before this function.");
4730 ISD::CONCAT_VECTORS, dl, VT,
4731 BottomHalf->isNullValue() ? RHS->getOperand(0) : LHS->getOperand(0),
4732 TopHalf->isNullValue() ? RHS->getOperand(1) : LHS->getOperand(1));
4735 SDValue DAGCombiner::visitVSELECT(SDNode *N) {
4736 SDValue N0 = N->getOperand(0);
4737 SDValue N1 = N->getOperand(1);
4738 SDValue N2 = N->getOperand(2);
4741 // Canonicalize integer abs.
4742 // vselect (setg[te] X, 0), X, -X ->
4743 // vselect (setgt X, -1), X, -X ->
4744 // vselect (setl[te] X, 0), -X, X ->
4745 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4746 if (N0.getOpcode() == ISD::SETCC) {
4747 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
4748 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4750 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
4752 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
4753 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) &&
4754 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
4755 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode());
4756 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) &&
4757 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
4758 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
4761 EVT VT = LHS.getValueType();
4762 SDValue Shift = DAG.getNode(
4763 ISD::SRA, DL, VT, LHS,
4764 DAG.getConstant(VT.getScalarType().getSizeInBits() - 1, VT));
4765 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);
4766 AddToWorklist(Shift.getNode());
4767 AddToWorklist(Add.getNode());
4768 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift);
4772 // If the VSELECT result requires splitting and the mask is provided by a
4773 // SETCC, then split both nodes and its operands before legalization. This
4774 // prevents the type legalizer from unrolling SETCC into scalar comparisons
4775 // and enables future optimizations (e.g. min/max pattern matching on X86).
4776 if (N0.getOpcode() == ISD::SETCC) {
4777 EVT VT = N->getValueType(0);
4779 // Check if any splitting is required.
4780 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
4781 TargetLowering::TypeSplitVector)
4784 SDValue Lo, Hi, CCLo, CCHi, LL, LH, RL, RH;
4785 std::tie(CCLo, CCHi) = SplitVSETCC(N0.getNode(), DAG);
4786 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 1);
4787 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 2);
4789 Lo = DAG.getNode(N->getOpcode(), DL, LL.getValueType(), CCLo, LL, RL);
4790 Hi = DAG.getNode(N->getOpcode(), DL, LH.getValueType(), CCHi, LH, RH);
4792 // Add the new VSELECT nodes to the work list in case they need to be split
4794 AddToWorklist(Lo.getNode());
4795 AddToWorklist(Hi.getNode());
4797 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
4800 // Fold (vselect (build_vector all_ones), N1, N2) -> N1
4801 if (ISD::isBuildVectorAllOnes(N0.getNode()))
4803 // Fold (vselect (build_vector all_zeros), N1, N2) -> N2
4804 if (ISD::isBuildVectorAllZeros(N0.getNode()))
4807 // The ConvertSelectToConcatVector function is assuming both the above
4808 // checks for (vselect (build_vector all{ones,zeros) ...) have been made
4810 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
4811 N2.getOpcode() == ISD::CONCAT_VECTORS &&
4812 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
4813 SDValue CV = ConvertSelectToConcatVector(N, DAG);
4821 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4822 SDValue N0 = N->getOperand(0);
4823 SDValue N1 = N->getOperand(1);
4824 SDValue N2 = N->getOperand(2);
4825 SDValue N3 = N->getOperand(3);
4826 SDValue N4 = N->getOperand(4);
4827 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4829 // fold select_cc lhs, rhs, x, x, cc -> x
4833 // Determine if the condition we're dealing with is constant
4834 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
4835 N0, N1, CC, SDLoc(N), false);
4836 if (SCC.getNode()) {
4837 AddToWorklist(SCC.getNode());
4839 if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) {
4840 if (!SCCC->isNullValue())
4841 return N2; // cond always true -> true val
4843 return N3; // cond always false -> false val
4846 // Fold to a simpler select_cc
4847 if (SCC.getOpcode() == ISD::SETCC)
4848 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(),
4849 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4853 // If we can fold this based on the true/false value, do so.
4854 if (SimplifySelectOps(N, N2, N3))
4855 return SDValue(N, 0); // Don't revisit N.
4857 // fold select_cc into other things, such as min/max/abs
4858 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
4861 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4862 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4863 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4867 // tryToFoldExtendOfConstant - Try to fold a sext/zext/aext
4868 // dag node into a ConstantSDNode or a build_vector of constants.
4869 // This function is called by the DAGCombiner when visiting sext/zext/aext
4870 // dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
4871 // Vector extends are not folded if operations are legal; this is to
4872 // avoid introducing illegal build_vector dag nodes.
4873 static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
4874 SelectionDAG &DAG, bool LegalTypes,
4875 bool LegalOperations) {
4876 unsigned Opcode = N->getOpcode();
4877 SDValue N0 = N->getOperand(0);
4878 EVT VT = N->getValueType(0);
4880 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
4881 Opcode == ISD::ANY_EXTEND) && "Expected EXTEND dag node in input!");
4883 // fold (sext c1) -> c1
4884 // fold (zext c1) -> c1
4885 // fold (aext c1) -> c1
4886 if (isa<ConstantSDNode>(N0))
4887 return DAG.getNode(Opcode, SDLoc(N), VT, N0).getNode();
4889 // fold (sext (build_vector AllConstants) -> (build_vector AllConstants)
4890 // fold (zext (build_vector AllConstants) -> (build_vector AllConstants)
4891 // fold (aext (build_vector AllConstants) -> (build_vector AllConstants)
4892 EVT SVT = VT.getScalarType();
4893 if (!(VT.isVector() &&
4894 (!LegalTypes || (!LegalOperations && TLI.isTypeLegal(SVT))) &&
4895 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
4898 // We can fold this node into a build_vector.
4899 unsigned VTBits = SVT.getSizeInBits();
4900 unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
4901 unsigned ShAmt = VTBits - EVTBits;
4902 SmallVector<SDValue, 8> Elts;
4903 unsigned NumElts = N0->getNumOperands();
4906 for (unsigned i=0; i != NumElts; ++i) {
4907 SDValue Op = N0->getOperand(i);
4908 if (Op->getOpcode() == ISD::UNDEF) {
4909 Elts.push_back(DAG.getUNDEF(SVT));
4913 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
4914 const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
4915 if (Opcode == ISD::SIGN_EXTEND)
4916 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
4919 Elts.push_back(DAG.getConstant(C.shl(ShAmt).lshr(ShAmt).getZExtValue(),
4923 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts).getNode();
4926 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4927 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4928 // transformation. Returns true if extension are possible and the above
4929 // mentioned transformation is profitable.
4930 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4932 SmallVectorImpl<SDNode *> &ExtendNodes,
4933 const TargetLowering &TLI) {
4934 bool HasCopyToRegUses = false;
4935 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4936 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4937 UE = N0.getNode()->use_end();
4942 if (UI.getUse().getResNo() != N0.getResNo())
4944 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4945 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4946 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4947 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4948 // Sign bits will be lost after a zext.
4951 for (unsigned i = 0; i != 2; ++i) {
4952 SDValue UseOp = User->getOperand(i);
4955 if (!isa<ConstantSDNode>(UseOp))
4960 ExtendNodes.push_back(User);
4963 // If truncates aren't free and there are users we can't
4964 // extend, it isn't worthwhile.
4967 // Remember if this value is live-out.
4968 if (User->getOpcode() == ISD::CopyToReg)
4969 HasCopyToRegUses = true;
4972 if (HasCopyToRegUses) {
4973 bool BothLiveOut = false;
4974 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4976 SDUse &Use = UI.getUse();
4977 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4983 // Both unextended and extended values are live out. There had better be
4984 // a good reason for the transformation.
4985 return ExtendNodes.size();
4990 void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
4991 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
4992 ISD::NodeType ExtType) {
4993 // Extend SetCC uses if necessary.
4994 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4995 SDNode *SetCC = SetCCs[i];
4996 SmallVector<SDValue, 4> Ops;
4998 for (unsigned j = 0; j != 2; ++j) {
4999 SDValue SOp = SetCC->getOperand(j);
5001 Ops.push_back(ExtLoad);
5003 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
5006 Ops.push_back(SetCC->getOperand(2));
5007 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops));
5011 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
5012 SDValue N0 = N->getOperand(0);
5013 EVT VT = N->getValueType(0);
5015 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5017 return SDValue(Res, 0);
5019 // fold (sext (sext x)) -> (sext x)
5020 // fold (sext (aext x)) -> (sext x)
5021 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5022 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT,
5025 if (N0.getOpcode() == ISD::TRUNCATE) {
5026 // fold (sext (truncate (load x))) -> (sext (smaller load x))
5027 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
5028 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5029 if (NarrowLoad.getNode()) {
5030 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5031 if (NarrowLoad.getNode() != N0.getNode()) {
5032 CombineTo(N0.getNode(), NarrowLoad);
5033 // CombineTo deleted the truncate, if needed, but not what's under it.
5036 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5039 // See if the value being truncated is already sign extended. If so, just
5040 // eliminate the trunc/sext pair.
5041 SDValue Op = N0.getOperand(0);
5042 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
5043 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
5044 unsigned DestBits = VT.getScalarType().getSizeInBits();
5045 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
5047 if (OpBits == DestBits) {
5048 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
5049 // bits, it is already ready.
5050 if (NumSignBits > DestBits-MidBits)
5052 } else if (OpBits < DestBits) {
5053 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
5054 // bits, just sext from i32.
5055 if (NumSignBits > OpBits-MidBits)
5056 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, Op);
5058 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
5059 // bits, just truncate to i32.
5060 if (NumSignBits > OpBits-MidBits)
5061 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5064 // fold (sext (truncate x)) -> (sextinreg x).
5065 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
5066 N0.getValueType())) {
5067 if (OpBits < DestBits)
5068 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
5069 else if (OpBits > DestBits)
5070 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
5071 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op,
5072 DAG.getValueType(N0.getValueType()));
5076 // fold (sext (load x)) -> (sext (truncate (sextload x)))
5077 // None of the supported targets knows how to perform load and sign extend
5078 // on vectors in one instruction. We only perform this transformation on
5080 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5081 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5082 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5083 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
5084 bool DoXform = true;
5085 SmallVector<SDNode*, 4> SetCCs;
5086 if (!N0.hasOneUse())
5087 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
5089 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5090 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5092 LN0->getBasePtr(), N0.getValueType(),
5093 LN0->getMemOperand());
5094 CombineTo(N, ExtLoad);
5095 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5096 N0.getValueType(), ExtLoad);
5097 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5098 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5100 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5104 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
5105 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
5106 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5107 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5108 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5109 EVT MemVT = LN0->getMemoryVT();
5110 if ((!LegalOperations && !LN0->isVolatile()) ||
5111 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
5112 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5114 LN0->getBasePtr(), MemVT,
5115 LN0->getMemOperand());
5116 CombineTo(N, ExtLoad);
5117 CombineTo(N0.getNode(),
5118 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5119 N0.getValueType(), ExtLoad),
5120 ExtLoad.getValue(1));
5121 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5125 // fold (sext (and/or/xor (load x), cst)) ->
5126 // (and/or/xor (sextload x), (sext cst))
5127 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5128 N0.getOpcode() == ISD::XOR) &&
5129 isa<LoadSDNode>(N0.getOperand(0)) &&
5130 N0.getOperand(1).getOpcode() == ISD::Constant &&
5131 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
5132 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5133 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5134 if (LN0->getExtensionType() != ISD::ZEXTLOAD && LN0->isUnindexed()) {
5135 bool DoXform = true;
5136 SmallVector<SDNode*, 4> SetCCs;
5137 if (!N0.hasOneUse())
5138 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
5141 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT,
5142 LN0->getChain(), LN0->getBasePtr(),
5144 LN0->getMemOperand());
5145 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5146 Mask = Mask.sext(VT.getSizeInBits());
5147 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5148 ExtLoad, DAG.getConstant(Mask, VT));
5149 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5150 SDLoc(N0.getOperand(0)),
5151 N0.getOperand(0).getValueType(), ExtLoad);
5153 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5154 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5156 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5161 if (N0.getOpcode() == ISD::SETCC) {
5162 EVT N0VT = N0.getOperand(0).getValueType();
5163 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
5164 // Only do this before legalize for now.
5165 if (VT.isVector() && !LegalOperations &&
5166 TLI.getBooleanContents(N0VT) ==
5167 TargetLowering::ZeroOrNegativeOneBooleanContent) {
5168 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
5169 // of the same size as the compared operands. Only optimize sext(setcc())
5170 // if this is the case.
5171 EVT SVT = getSetCCResultType(N0VT);
5173 // We know that the # elements of the results is the same as the
5174 // # elements of the compare (and the # elements of the compare result
5175 // for that matter). Check to see that they are the same size. If so,
5176 // we know that the element size of the sext'd result matches the
5177 // element size of the compare operands.
5178 if (VT.getSizeInBits() == SVT.getSizeInBits())
5179 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5181 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5183 // If the desired elements are smaller or larger than the source
5184 // elements we can use a matching integer vector type and then
5185 // truncate/sign extend
5186 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
5187 if (SVT == MatchingVectorType) {
5188 SDValue VsetCC = DAG.getSetCC(SDLoc(N), MatchingVectorType,
5189 N0.getOperand(0), N0.getOperand(1),
5190 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5191 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT);
5195 // sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)
5196 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
5198 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
5200 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5201 NegOne, DAG.getConstant(0, VT),
5202 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5203 if (SCC.getNode()) return SCC;
5205 if (!VT.isVector()) {
5206 EVT SetCCVT = getSetCCResultType(N0.getOperand(0).getValueType());
5207 if (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, SetCCVT)) {
5209 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
5210 SDValue SetCC = DAG.getSetCC(DL,
5212 N0.getOperand(0), N0.getOperand(1), CC);
5213 EVT SelectVT = getSetCCResultType(VT);
5214 return DAG.getSelect(DL, VT,
5215 DAG.getSExtOrTrunc(SetCC, DL, SelectVT),
5216 NegOne, DAG.getConstant(0, VT));
5222 // fold (sext x) -> (zext x) if the sign bit is known zero.
5223 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
5224 DAG.SignBitIsZero(N0))
5225 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
5230 // isTruncateOf - If N is a truncate of some other value, return true, record
5231 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
5232 // This function computes KnownZero to avoid a duplicated call to
5233 // computeKnownBits in the caller.
5234 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
5237 if (N->getOpcode() == ISD::TRUNCATE) {
5238 Op = N->getOperand(0);
5239 DAG.computeKnownBits(Op, KnownZero, KnownOne);
5243 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
5244 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
5247 SDValue Op0 = N->getOperand(0);
5248 SDValue Op1 = N->getOperand(1);
5249 assert(Op0.getValueType() == Op1.getValueType());
5251 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
5252 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
5253 if (COp0 && COp0->isNullValue())
5255 else if (COp1 && COp1->isNullValue())
5260 DAG.computeKnownBits(Op, KnownZero, KnownOne);
5262 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
5268 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
5269 SDValue N0 = N->getOperand(0);
5270 EVT VT = N->getValueType(0);
5272 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5274 return SDValue(Res, 0);
5276 // fold (zext (zext x)) -> (zext x)
5277 // fold (zext (aext x)) -> (zext x)
5278 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5279 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
5282 // fold (zext (truncate x)) -> (zext x) or
5283 // (zext (truncate x)) -> (truncate x)
5284 // This is valid when the truncated bits of x are already zero.
5285 // FIXME: We should extend this to work for vectors too.
5288 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
5289 APInt TruncatedBits =
5290 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
5291 APInt(Op.getValueSizeInBits(), 0) :
5292 APInt::getBitsSet(Op.getValueSizeInBits(),
5293 N0.getValueSizeInBits(),
5294 std::min(Op.getValueSizeInBits(),
5295 VT.getSizeInBits()));
5296 if (TruncatedBits == (KnownZero & TruncatedBits)) {
5297 if (VT.bitsGT(Op.getValueType()))
5298 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op);
5299 if (VT.bitsLT(Op.getValueType()))
5300 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5306 // fold (zext (truncate (load x))) -> (zext (smaller load x))
5307 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
5308 if (N0.getOpcode() == ISD::TRUNCATE) {
5309 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5310 if (NarrowLoad.getNode()) {
5311 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5312 if (NarrowLoad.getNode() != N0.getNode()) {
5313 CombineTo(N0.getNode(), NarrowLoad);
5314 // CombineTo deleted the truncate, if needed, but not what's under it.
5317 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5321 // fold (zext (truncate x)) -> (and x, mask)
5322 if (N0.getOpcode() == ISD::TRUNCATE &&
5323 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
5325 // fold (zext (truncate (load x))) -> (zext (smaller load x))
5326 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
5327 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5328 if (NarrowLoad.getNode()) {
5329 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5330 if (NarrowLoad.getNode() != N0.getNode()) {
5331 CombineTo(N0.getNode(), NarrowLoad);
5332 // CombineTo deleted the truncate, if needed, but not what's under it.
5335 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5338 SDValue Op = N0.getOperand(0);
5339 if (Op.getValueType().bitsLT(VT)) {
5340 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Op);
5341 AddToWorklist(Op.getNode());
5342 } else if (Op.getValueType().bitsGT(VT)) {
5343 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5344 AddToWorklist(Op.getNode());
5346 return DAG.getZeroExtendInReg(Op, SDLoc(N),
5347 N0.getValueType().getScalarType());
5350 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
5351 // if either of the casts is not free.
5352 if (N0.getOpcode() == ISD::AND &&
5353 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5354 N0.getOperand(1).getOpcode() == ISD::Constant &&
5355 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
5356 N0.getValueType()) ||
5357 !TLI.isZExtFree(N0.getValueType(), VT))) {
5358 SDValue X = N0.getOperand(0).getOperand(0);
5359 if (X.getValueType().bitsLT(VT)) {
5360 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(X), VT, X);
5361 } else if (X.getValueType().bitsGT(VT)) {
5362 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
5364 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5365 Mask = Mask.zext(VT.getSizeInBits());
5366 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5367 X, DAG.getConstant(Mask, VT));
5370 // fold (zext (load x)) -> (zext (truncate (zextload x)))
5371 // None of the supported targets knows how to perform load and vector_zext
5372 // on vectors in one instruction. We only perform this transformation on
5374 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5375 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5376 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5377 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
5378 bool DoXform = true;
5379 SmallVector<SDNode*, 4> SetCCs;
5380 if (!N0.hasOneUse())
5381 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
5383 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5384 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
5386 LN0->getBasePtr(), N0.getValueType(),
5387 LN0->getMemOperand());
5388 CombineTo(N, ExtLoad);
5389 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5390 N0.getValueType(), ExtLoad);
5391 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5393 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5395 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5399 // fold (zext (and/or/xor (load x), cst)) ->
5400 // (and/or/xor (zextload x), (zext cst))
5401 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5402 N0.getOpcode() == ISD::XOR) &&
5403 isa<LoadSDNode>(N0.getOperand(0)) &&
5404 N0.getOperand(1).getOpcode() == ISD::Constant &&
5405 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
5406 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5407 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5408 if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) {
5409 bool DoXform = true;
5410 SmallVector<SDNode*, 4> SetCCs;
5411 if (!N0.hasOneUse())
5412 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
5415 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT,
5416 LN0->getChain(), LN0->getBasePtr(),
5418 LN0->getMemOperand());
5419 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5420 Mask = Mask.zext(VT.getSizeInBits());
5421 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5422 ExtLoad, DAG.getConstant(Mask, VT));
5423 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5424 SDLoc(N0.getOperand(0)),
5425 N0.getOperand(0).getValueType(), ExtLoad);
5427 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5428 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5430 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5435 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
5436 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
5437 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5438 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5439 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5440 EVT MemVT = LN0->getMemoryVT();
5441 if ((!LegalOperations && !LN0->isVolatile()) ||
5442 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
5443 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
5445 LN0->getBasePtr(), MemVT,
5446 LN0->getMemOperand());
5447 CombineTo(N, ExtLoad);
5448 CombineTo(N0.getNode(),
5449 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
5451 ExtLoad.getValue(1));
5452 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5456 if (N0.getOpcode() == ISD::SETCC) {
5457 if (!LegalOperations && VT.isVector() &&
5458 N0.getValueType().getVectorElementType() == MVT::i1) {
5459 EVT N0VT = N0.getOperand(0).getValueType();
5460 if (getSetCCResultType(N0VT) == N0.getValueType())
5463 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
5464 // Only do this before legalize for now.
5465 EVT EltVT = VT.getVectorElementType();
5466 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
5467 DAG.getConstant(1, EltVT));
5468 if (VT.getSizeInBits() == N0VT.getSizeInBits())
5469 // We know that the # elements of the results is the same as the
5470 // # elements of the compare (and the # elements of the compare result
5471 // for that matter). Check to see that they are the same size. If so,
5472 // we know that the element size of the sext'd result matches the
5473 // element size of the compare operands.
5474 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5475 DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5477 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
5478 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT,
5481 // If the desired elements are smaller or larger than the source
5482 // elements we can use a matching integer vector type and then
5483 // truncate/sign extend
5484 EVT MatchingElementType =
5485 EVT::getIntegerVT(*DAG.getContext(),
5486 N0VT.getScalarType().getSizeInBits());
5487 EVT MatchingVectorType =
5488 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
5489 N0VT.getVectorNumElements());
5491 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5493 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5494 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5495 DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT),
5496 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, OneOps));
5499 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5501 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5502 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
5503 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5504 if (SCC.getNode()) return SCC;
5507 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
5508 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
5509 isa<ConstantSDNode>(N0.getOperand(1)) &&
5510 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
5512 SDValue ShAmt = N0.getOperand(1);
5513 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5514 if (N0.getOpcode() == ISD::SHL) {
5515 SDValue InnerZExt = N0.getOperand(0);
5516 // If the original shl may be shifting out bits, do not perform this
5518 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
5519 InnerZExt.getOperand(0).getValueType().getSizeInBits();
5520 if (ShAmtVal > KnownZeroBits)
5526 // Ensure that the shift amount is wide enough for the shifted value.
5527 if (VT.getSizeInBits() >= 256)
5528 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
5530 return DAG.getNode(N0.getOpcode(), DL, VT,
5531 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
5538 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
5539 SDValue N0 = N->getOperand(0);
5540 EVT VT = N->getValueType(0);
5542 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5544 return SDValue(Res, 0);
5546 // fold (aext (aext x)) -> (aext x)
5547 // fold (aext (zext x)) -> (zext x)
5548 // fold (aext (sext x)) -> (sext x)
5549 if (N0.getOpcode() == ISD::ANY_EXTEND ||
5550 N0.getOpcode() == ISD::ZERO_EXTEND ||
5551 N0.getOpcode() == ISD::SIGN_EXTEND)
5552 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
5554 // fold (aext (truncate (load x))) -> (aext (smaller load x))
5555 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
5556 if (N0.getOpcode() == ISD::TRUNCATE) {
5557 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5558 if (NarrowLoad.getNode()) {
5559 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5560 if (NarrowLoad.getNode() != N0.getNode()) {
5561 CombineTo(N0.getNode(), NarrowLoad);
5562 // CombineTo deleted the truncate, if needed, but not what's under it.
5565 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5569 // fold (aext (truncate x))
5570 if (N0.getOpcode() == ISD::TRUNCATE) {
5571 SDValue TruncOp = N0.getOperand(0);
5572 if (TruncOp.getValueType() == VT)
5573 return TruncOp; // x iff x size == zext size.
5574 if (TruncOp.getValueType().bitsGT(VT))
5575 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, TruncOp);
5576 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, TruncOp);
5579 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
5580 // if the trunc is not free.
5581 if (N0.getOpcode() == ISD::AND &&
5582 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5583 N0.getOperand(1).getOpcode() == ISD::Constant &&
5584 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
5585 N0.getValueType())) {
5586 SDValue X = N0.getOperand(0).getOperand(0);
5587 if (X.getValueType().bitsLT(VT)) {
5588 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, X);
5589 } else if (X.getValueType().bitsGT(VT)) {
5590 X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X);
5592 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5593 Mask = Mask.zext(VT.getSizeInBits());
5594 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5595 X, DAG.getConstant(Mask, VT));
5598 // fold (aext (load x)) -> (aext (truncate (extload x)))
5599 // None of the supported targets knows how to perform load and any_ext
5600 // on vectors in one instruction. We only perform this transformation on
5602 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5603 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5604 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType())) {
5605 bool DoXform = true;
5606 SmallVector<SDNode*, 4> SetCCs;
5607 if (!N0.hasOneUse())
5608 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
5610 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5611 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
5613 LN0->getBasePtr(), N0.getValueType(),
5614 LN0->getMemOperand());
5615 CombineTo(N, ExtLoad);
5616 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5617 N0.getValueType(), ExtLoad);
5618 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5619 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5621 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5625 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
5626 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
5627 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
5628 if (N0.getOpcode() == ISD::LOAD &&
5629 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5631 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5632 ISD::LoadExtType ExtType = LN0->getExtensionType();
5633 EVT MemVT = LN0->getMemoryVT();
5634 if (!LegalOperations || TLI.isLoadExtLegal(ExtType, MemVT)) {
5635 SDValue ExtLoad = DAG.getExtLoad(ExtType, SDLoc(N),
5636 VT, LN0->getChain(), LN0->getBasePtr(),
5637 MemVT, LN0->getMemOperand());
5638 CombineTo(N, ExtLoad);
5639 CombineTo(N0.getNode(),
5640 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5641 N0.getValueType(), ExtLoad),
5642 ExtLoad.getValue(1));
5643 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5647 if (N0.getOpcode() == ISD::SETCC) {
5649 // aext(setcc) -> vsetcc
5650 // aext(setcc) -> truncate(vsetcc)
5651 // aext(setcc) -> aext(vsetcc)
5652 // Only do this before legalize for now.
5653 if (VT.isVector() && !LegalOperations) {
5654 EVT N0VT = N0.getOperand(0).getValueType();
5655 // We know that the # elements of the results is the same as the
5656 // # elements of the compare (and the # elements of the compare result
5657 // for that matter). Check to see that they are the same size. If so,
5658 // we know that the element size of the sext'd result matches the
5659 // element size of the compare operands.
5660 if (VT.getSizeInBits() == N0VT.getSizeInBits())
5661 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5663 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5664 // If the desired elements are smaller or larger than the source
5665 // elements we can use a matching integer vector type and then
5666 // truncate/any extend
5668 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
5670 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5672 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5673 return DAG.getAnyExtOrTrunc(VsetCC, SDLoc(N), VT);
5677 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5679 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5680 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
5681 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5689 /// See if the specified operand can be simplified with the knowledge that only
5690 /// the bits specified by Mask are used. If so, return the simpler operand,
5691 /// otherwise return a null SDValue.
5692 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
5693 switch (V.getOpcode()) {
5695 case ISD::Constant: {
5696 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
5697 assert(CV && "Const value should be ConstSDNode.");
5698 const APInt &CVal = CV->getAPIntValue();
5699 APInt NewVal = CVal & Mask;
5701 return DAG.getConstant(NewVal, V.getValueType());
5706 // If the LHS or RHS don't contribute bits to the or, drop them.
5707 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
5708 return V.getOperand(1);
5709 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
5710 return V.getOperand(0);
5713 // Only look at single-use SRLs.
5714 if (!V.getNode()->hasOneUse())
5716 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
5717 // See if we can recursively simplify the LHS.
5718 unsigned Amt = RHSC->getZExtValue();
5720 // Watch out for shift count overflow though.
5721 if (Amt >= Mask.getBitWidth()) break;
5722 APInt NewMask = Mask << Amt;
5723 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
5724 if (SimplifyLHS.getNode())
5725 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
5726 SimplifyLHS, V.getOperand(1));
5732 /// If the result of a wider load is shifted to right of N bits and then
5733 /// truncated to a narrower type and where N is a multiple of number of bits of
5734 /// the narrower type, transform it to a narrower load from address + N / num of
5735 /// bits of new type. If the result is to be extended, also fold the extension
5736 /// to form a extending load.
5737 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
5738 unsigned Opc = N->getOpcode();
5740 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
5741 SDValue N0 = N->getOperand(0);
5742 EVT VT = N->getValueType(0);
5745 // This transformation isn't valid for vector loads.
5749 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
5751 if (Opc == ISD::SIGN_EXTEND_INREG) {
5752 ExtType = ISD::SEXTLOAD;
5753 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5754 } else if (Opc == ISD::SRL) {
5755 // Another special-case: SRL is basically zero-extending a narrower value.
5756 ExtType = ISD::ZEXTLOAD;
5758 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5759 if (!N01) return SDValue();
5760 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
5761 VT.getSizeInBits() - N01->getZExtValue());
5763 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
5766 unsigned EVTBits = ExtVT.getSizeInBits();
5768 // Do not generate loads of non-round integer types since these can
5769 // be expensive (and would be wrong if the type is not byte sized).
5770 if (!ExtVT.isRound())
5774 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5775 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5776 ShAmt = N01->getZExtValue();
5777 // Is the shift amount a multiple of size of VT?
5778 if ((ShAmt & (EVTBits-1)) == 0) {
5779 N0 = N0.getOperand(0);
5780 // Is the load width a multiple of size of VT?
5781 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5785 // At this point, we must have a load or else we can't do the transform.
5786 if (!isa<LoadSDNode>(N0)) return SDValue();
5788 // Because a SRL must be assumed to *need* to zero-extend the high bits
5789 // (as opposed to anyext the high bits), we can't combine the zextload
5790 // lowering of SRL and an sextload.
5791 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
5794 // If the shift amount is larger than the input type then we're not
5795 // accessing any of the loaded bytes. If the load was a zextload/extload
5796 // then the result of the shift+trunc is zero/undef (handled elsewhere).
5797 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
5802 // If the load is shifted left (and the result isn't shifted back right),
5803 // we can fold the truncate through the shift.
5804 unsigned ShLeftAmt = 0;
5805 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5806 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
5807 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5808 ShLeftAmt = N01->getZExtValue();
5809 N0 = N0.getOperand(0);
5813 // If we haven't found a load, we can't narrow it. Don't transform one with
5814 // multiple uses, this would require adding a new load.
5815 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
5818 // Don't change the width of a volatile load.
5819 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5820 if (LN0->isVolatile())
5823 // Verify that we are actually reducing a load width here.
5824 if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
5827 // For the transform to be legal, the load must produce only two values
5828 // (the value loaded and the chain). Don't transform a pre-increment
5829 // load, for example, which produces an extra value. Otherwise the
5830 // transformation is not equivalent, and the downstream logic to replace
5831 // uses gets things wrong.
5832 if (LN0->getNumValues() > 2)
5835 // If the load that we're shrinking is an extload and we're not just
5836 // discarding the extension we can't simply shrink the load. Bail.
5837 // TODO: It would be possible to merge the extensions in some cases.
5838 if (LN0->getExtensionType() != ISD::NON_EXTLOAD &&
5839 LN0->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
5842 EVT PtrType = N0.getOperand(1).getValueType();
5844 if (PtrType == MVT::Untyped || PtrType.isExtended())
5845 // It's not possible to generate a constant of extended or untyped type.
5848 // For big endian targets, we need to adjust the offset to the pointer to
5849 // load the correct bytes.
5850 if (TLI.isBigEndian()) {
5851 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
5852 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
5853 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
5856 uint64_t PtrOff = ShAmt / 8;
5857 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
5858 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0),
5859 PtrType, LN0->getBasePtr(),
5860 DAG.getConstant(PtrOff, PtrType));
5861 AddToWorklist(NewPtr.getNode());
5864 if (ExtType == ISD::NON_EXTLOAD)
5865 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr,
5866 LN0->getPointerInfo().getWithOffset(PtrOff),
5867 LN0->isVolatile(), LN0->isNonTemporal(),
5868 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
5870 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr,
5871 LN0->getPointerInfo().getWithOffset(PtrOff),
5872 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
5873 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
5875 // Replace the old load's chain with the new load's chain.
5876 WorklistRemover DeadNodes(*this);
5877 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
5879 // Shift the result left, if we've swallowed a left shift.
5880 SDValue Result = Load;
5881 if (ShLeftAmt != 0) {
5882 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
5883 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
5885 // If the shift amount is as large as the result size (but, presumably,
5886 // no larger than the source) then the useful bits of the result are
5887 // zero; we can't simply return the shortened shift, because the result
5888 // of that operation is undefined.
5889 if (ShLeftAmt >= VT.getSizeInBits())
5890 Result = DAG.getConstant(0, VT);
5892 Result = DAG.getNode(ISD::SHL, SDLoc(N0), VT,
5893 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
5896 // Return the new loaded value.
5900 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
5901 SDValue N0 = N->getOperand(0);
5902 SDValue N1 = N->getOperand(1);
5903 EVT VT = N->getValueType(0);
5904 EVT EVT = cast<VTSDNode>(N1)->getVT();
5905 unsigned VTBits = VT.getScalarType().getSizeInBits();
5906 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
5908 // fold (sext_in_reg c1) -> c1
5909 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5910 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
5912 // If the input is already sign extended, just drop the extension.
5913 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
5916 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
5917 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5918 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
5919 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
5920 N0.getOperand(0), N1);
5922 // fold (sext_in_reg (sext x)) -> (sext x)
5923 // fold (sext_in_reg (aext x)) -> (sext x)
5924 // if x is small enough.
5925 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5926 SDValue N00 = N0.getOperand(0);
5927 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
5928 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5929 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
5932 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
5933 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
5934 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);
5936 // fold operands of sext_in_reg based on knowledge that the top bits are not
5938 if (SimplifyDemandedBits(SDValue(N, 0)))
5939 return SDValue(N, 0);
5941 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5942 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5943 SDValue NarrowLoad = ReduceLoadWidth(N);
5944 if (NarrowLoad.getNode())
5947 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5948 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5949 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5950 if (N0.getOpcode() == ISD::SRL) {
5951 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5952 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5953 // We can turn this into an SRA iff the input to the SRL is already sign
5955 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5956 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5957 return DAG.getNode(ISD::SRA, SDLoc(N), VT,
5958 N0.getOperand(0), N0.getOperand(1));
5962 // fold (sext_inreg (extload x)) -> (sextload x)
5963 if (ISD::isEXTLoad(N0.getNode()) &&
5964 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5965 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5966 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5967 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5968 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5969 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5971 LN0->getBasePtr(), EVT,
5972 LN0->getMemOperand());
5973 CombineTo(N, ExtLoad);
5974 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5975 AddToWorklist(ExtLoad.getNode());
5976 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5978 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5979 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5981 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5982 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5983 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5984 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5985 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5987 LN0->getBasePtr(), EVT,
5988 LN0->getMemOperand());
5989 CombineTo(N, ExtLoad);
5990 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5991 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5994 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5995 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5996 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5997 N0.getOperand(1), false);
5998 if (BSwap.getNode())
5999 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6003 // Fold a sext_inreg of a build_vector of ConstantSDNodes or undefs
6004 // into a build_vector.
6005 if (ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
6006 SmallVector<SDValue, 8> Elts;
6007 unsigned NumElts = N0->getNumOperands();
6008 unsigned ShAmt = VTBits - EVTBits;
6010 for (unsigned i = 0; i != NumElts; ++i) {
6011 SDValue Op = N0->getOperand(i);
6012 if (Op->getOpcode() == ISD::UNDEF) {
6017 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
6018 const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
6019 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
6020 Op.getValueType()));
6023 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Elts);
6029 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
6030 SDValue N0 = N->getOperand(0);
6031 EVT VT = N->getValueType(0);
6032 bool isLE = TLI.isLittleEndian();
6035 if (N0.getValueType() == N->getValueType(0))
6037 // fold (truncate c1) -> c1
6038 if (isa<ConstantSDNode>(N0))
6039 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0);
6040 // fold (truncate (truncate x)) -> (truncate x)
6041 if (N0.getOpcode() == ISD::TRUNCATE)
6042 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6043 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
6044 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
6045 N0.getOpcode() == ISD::SIGN_EXTEND ||
6046 N0.getOpcode() == ISD::ANY_EXTEND) {
6047 if (N0.getOperand(0).getValueType().bitsLT(VT))
6048 // if the source is smaller than the dest, we still need an extend
6049 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
6051 if (N0.getOperand(0).getValueType().bitsGT(VT))
6052 // if the source is larger than the dest, than we just need the truncate
6053 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6054 // if the source and dest are the same type, we can drop both the extend
6055 // and the truncate.
6056 return N0.getOperand(0);
6059 // Fold extract-and-trunc into a narrow extract. For example:
6060 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
6061 // i32 y = TRUNCATE(i64 x)
6063 // v16i8 b = BITCAST (v2i64 val)
6064 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
6066 // Note: We only run this optimization after type legalization (which often
6067 // creates this pattern) and before operation legalization after which
6068 // we need to be more careful about the vector instructions that we generate.
6069 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6070 LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) {
6072 EVT VecTy = N0.getOperand(0).getValueType();
6073 EVT ExTy = N0.getValueType();
6074 EVT TrTy = N->getValueType(0);
6076 unsigned NumElem = VecTy.getVectorNumElements();
6077 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
6079 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
6080 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
6082 SDValue EltNo = N0->getOperand(1);
6083 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
6084 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6085 EVT IndexTy = TLI.getVectorIdxTy();
6086 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
6088 SDValue V = DAG.getNode(ISD::BITCAST, SDLoc(N),
6089 NVT, N0.getOperand(0));
6091 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
6093 DAG.getConstant(Index, IndexTy));
6097 // trunc (select c, a, b) -> select c, (trunc a), (trunc b)
6098 if (N0.getOpcode() == ISD::SELECT) {
6099 EVT SrcVT = N0.getValueType();
6100 if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
6101 TLI.isTruncateFree(SrcVT, VT)) {
6103 SDValue Cond = N0.getOperand(0);
6104 SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
6105 SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2));
6106 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, Cond, TruncOp0, TruncOp1);
6110 // Fold a series of buildvector, bitcast, and truncate if possible.
6112 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to
6113 // (2xi32 (buildvector x, y)).
6114 if (Level == AfterLegalizeVectorOps && VT.isVector() &&
6115 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
6116 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
6117 N0.getOperand(0).hasOneUse()) {
6119 SDValue BuildVect = N0.getOperand(0);
6120 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType();
6121 EVT TruncVecEltTy = VT.getVectorElementType();
6123 // Check that the element types match.
6124 if (BuildVectEltTy == TruncVecEltTy) {
6125 // Now we only need to compute the offset of the truncated elements.
6126 unsigned BuildVecNumElts = BuildVect.getNumOperands();
6127 unsigned TruncVecNumElts = VT.getVectorNumElements();
6128 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts;
6130 assert((BuildVecNumElts % TruncVecNumElts) == 0 &&
6131 "Invalid number of elements");
6133 SmallVector<SDValue, 8> Opnds;
6134 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
6135 Opnds.push_back(BuildVect.getOperand(i));
6137 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
6141 // See if we can simplify the input to this truncate through knowledge that
6142 // only the low bits are being used.
6143 // For example "trunc (or (shl x, 8), y)" // -> trunc y
6144 // Currently we only perform this optimization on scalars because vectors
6145 // may have different active low bits.
6146 if (!VT.isVector()) {
6148 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
6149 VT.getSizeInBits()));
6150 if (Shorter.getNode())
6151 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter);
6153 // fold (truncate (load x)) -> (smaller load x)
6154 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
6155 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
6156 SDValue Reduced = ReduceLoadWidth(N);
6157 if (Reduced.getNode())
6159 // Handle the case where the load remains an extending load even
6160 // after truncation.
6161 if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) {
6162 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6163 if (!LN0->isVolatile() &&
6164 LN0->getMemoryVT().getStoreSizeInBits() < VT.getSizeInBits()) {
6165 SDValue NewLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(LN0),
6166 VT, LN0->getChain(), LN0->getBasePtr(),
6168 LN0->getMemOperand());
6169 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1));
6174 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
6175 // where ... are all 'undef'.
6176 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
6177 SmallVector<EVT, 8> VTs;
6180 unsigned NumDefs = 0;
6182 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
6183 SDValue X = N0.getOperand(i);
6184 if (X.getOpcode() != ISD::UNDEF) {
6189 // Stop if more than one members are non-undef.
6192 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
6193 VT.getVectorElementType(),
6194 X.getValueType().getVectorNumElements()));
6198 return DAG.getUNDEF(VT);
6201 assert(V.getNode() && "The single defined operand is empty!");
6202 SmallVector<SDValue, 8> Opnds;
6203 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
6205 Opnds.push_back(DAG.getUNDEF(VTs[i]));
6208 SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V);
6209 AddToWorklist(NV.getNode());
6210 Opnds.push_back(NV);
6212 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds);
6216 // Simplify the operands using demanded-bits information.
6217 if (!VT.isVector() &&
6218 SimplifyDemandedBits(SDValue(N, 0)))
6219 return SDValue(N, 0);
6224 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
6225 SDValue Elt = N->getOperand(i);
6226 if (Elt.getOpcode() != ISD::MERGE_VALUES)
6227 return Elt.getNode();
6228 return Elt.getOperand(Elt.getResNo()).getNode();
6231 /// build_pair (load, load) -> load
6232 /// if load locations are consecutive.
6233 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
6234 assert(N->getOpcode() == ISD::BUILD_PAIR);
6236 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
6237 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
6238 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
6239 LD1->getAddressSpace() != LD2->getAddressSpace())
6241 EVT LD1VT = LD1->getValueType(0);
6243 if (ISD::isNON_EXTLoad(LD2) &&
6245 // If both are volatile this would reduce the number of volatile loads.
6246 // If one is volatile it might be ok, but play conservative and bail out.
6247 !LD1->isVolatile() &&
6248 !LD2->isVolatile() &&
6249 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
6250 unsigned Align = LD1->getAlignment();
6251 unsigned NewAlign = TLI.getDataLayout()->
6252 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
6254 if (NewAlign <= Align &&
6255 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
6256 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(),
6257 LD1->getBasePtr(), LD1->getPointerInfo(),
6258 false, false, false, Align);
6264 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
6265 SDValue N0 = N->getOperand(0);
6266 EVT VT = N->getValueType(0);
6268 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
6269 // Only do this before legalize, since afterward the target may be depending
6270 // on the bitconvert.
6271 // First check to see if this is all constant.
6273 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
6275 bool isSimple = cast<BuildVectorSDNode>(N0)->isConstant();
6277 EVT DestEltVT = N->getValueType(0).getVectorElementType();
6278 assert(!DestEltVT.isVector() &&
6279 "Element type of vector ValueType must not be vector!");
6281 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
6284 // If the input is a constant, let getNode fold it.
6285 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
6286 SDValue Res = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0);
6287 if (Res.getNode() != N) {
6288 if (!LegalOperations ||
6289 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
6292 // Folding it resulted in an illegal node, and it's too late to
6293 // do that. Clean up the old node and forego the transformation.
6294 // Ideally this won't happen very often, because instcombine
6295 // and the earlier dagcombine runs (where illegal nodes are
6296 // permitted) should have folded most of them already.
6297 deleteAndRecombine(Res.getNode());
6301 // (conv (conv x, t1), t2) -> (conv x, t2)
6302 if (N0.getOpcode() == ISD::BITCAST)
6303 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT,
6306 // fold (conv (load x)) -> (load (conv*)x)
6307 // If the resultant load doesn't need a higher alignment than the original!
6308 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6309 // Do not change the width of a volatile load.
6310 !cast<LoadSDNode>(N0)->isVolatile() &&
6311 // Do not remove the cast if the types differ in endian layout.
6312 TLI.hasBigEndianPartOrdering(N0.getValueType()) ==
6313 TLI.hasBigEndianPartOrdering(VT) &&
6314 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) &&
6315 TLI.isLoadBitCastBeneficial(N0.getValueType(), VT)) {
6316 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6317 unsigned Align = TLI.getDataLayout()->
6318 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
6319 unsigned OrigAlign = LN0->getAlignment();
6321 if (Align <= OrigAlign) {
6322 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(),
6323 LN0->getBasePtr(), LN0->getPointerInfo(),
6324 LN0->isVolatile(), LN0->isNonTemporal(),
6325 LN0->isInvariant(), OrigAlign,
6327 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
6332 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
6333 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
6334 // This often reduces constant pool loads.
6335 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
6336 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
6337 N0.getNode()->hasOneUse() && VT.isInteger() &&
6338 !VT.isVector() && !N0.getValueType().isVector()) {
6339 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
6341 AddToWorklist(NewConv.getNode());
6343 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
6344 if (N0.getOpcode() == ISD::FNEG)
6345 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
6346 NewConv, DAG.getConstant(SignBit, VT));
6347 assert(N0.getOpcode() == ISD::FABS);
6348 return DAG.getNode(ISD::AND, SDLoc(N), VT,
6349 NewConv, DAG.getConstant(~SignBit, VT));
6352 // fold (bitconvert (fcopysign cst, x)) ->
6353 // (or (and (bitconvert x), sign), (and cst, (not sign)))
6354 // Note that we don't handle (copysign x, cst) because this can always be
6355 // folded to an fneg or fabs.
6356 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
6357 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
6358 VT.isInteger() && !VT.isVector()) {
6359 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
6360 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
6361 if (isTypeLegal(IntXVT)) {
6362 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6363 IntXVT, N0.getOperand(1));
6364 AddToWorklist(X.getNode());
6366 // If X has a different width than the result/lhs, sext it or truncate it.
6367 unsigned VTWidth = VT.getSizeInBits();
6368 if (OrigXWidth < VTWidth) {
6369 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X);
6370 AddToWorklist(X.getNode());
6371 } else if (OrigXWidth > VTWidth) {
6372 // To get the sign bit in the right place, we have to shift it right
6373 // before truncating.
6374 X = DAG.getNode(ISD::SRL, SDLoc(X),
6375 X.getValueType(), X,
6376 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
6377 AddToWorklist(X.getNode());
6378 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
6379 AddToWorklist(X.getNode());
6382 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
6383 X = DAG.getNode(ISD::AND, SDLoc(X), VT,
6384 X, DAG.getConstant(SignBit, VT));
6385 AddToWorklist(X.getNode());
6387 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6388 VT, N0.getOperand(0));
6389 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT,
6390 Cst, DAG.getConstant(~SignBit, VT));
6391 AddToWorklist(Cst.getNode());
6393 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst);
6397 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
6398 if (N0.getOpcode() == ISD::BUILD_PAIR) {
6399 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
6400 if (CombineLD.getNode())
6407 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
6408 EVT VT = N->getValueType(0);
6409 return CombineConsecutiveLoads(N, VT);
6412 /// We know that BV is a build_vector node with Constant, ConstantFP or Undef
6413 /// operands. DstEltVT indicates the destination element value type.
6414 SDValue DAGCombiner::
6415 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
6416 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
6418 // If this is already the right type, we're done.
6419 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
6421 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
6422 unsigned DstBitSize = DstEltVT.getSizeInBits();
6424 // If this is a conversion of N elements of one type to N elements of another
6425 // type, convert each element. This handles FP<->INT cases.
6426 if (SrcBitSize == DstBitSize) {
6427 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
6428 BV->getValueType(0).getVectorNumElements());
6430 // Due to the FP element handling below calling this routine recursively,
6431 // we can end up with a scalar-to-vector node here.
6432 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
6433 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
6434 DAG.getNode(ISD::BITCAST, SDLoc(BV),
6435 DstEltVT, BV->getOperand(0)));
6437 SmallVector<SDValue, 8> Ops;
6438 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
6439 SDValue Op = BV->getOperand(i);
6440 // If the vector element type is not legal, the BUILD_VECTOR operands
6441 // are promoted and implicitly truncated. Make that explicit here.
6442 if (Op.getValueType() != SrcEltVT)
6443 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op);
6444 Ops.push_back(DAG.getNode(ISD::BITCAST, SDLoc(BV),
6446 AddToWorklist(Ops.back().getNode());
6448 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6451 // Otherwise, we're growing or shrinking the elements. To avoid having to
6452 // handle annoying details of growing/shrinking FP values, we convert them to
6454 if (SrcEltVT.isFloatingPoint()) {
6455 // Convert the input float vector to a int vector where the elements are the
6457 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
6458 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
6459 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
6463 // Now we know the input is an integer vector. If the output is a FP type,
6464 // convert to integer first, then to FP of the right size.
6465 if (DstEltVT.isFloatingPoint()) {
6466 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
6467 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
6468 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
6470 // Next, convert to FP elements of the same size.
6471 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
6474 // Okay, we know the src/dst types are both integers of differing types.
6475 // Handling growing first.
6476 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
6477 if (SrcBitSize < DstBitSize) {
6478 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
6480 SmallVector<SDValue, 8> Ops;
6481 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
6482 i += NumInputsPerOutput) {
6483 bool isLE = TLI.isLittleEndian();
6484 APInt NewBits = APInt(DstBitSize, 0);
6485 bool EltIsUndef = true;
6486 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
6487 // Shift the previously computed bits over.
6488 NewBits <<= SrcBitSize;
6489 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
6490 if (Op.getOpcode() == ISD::UNDEF) continue;
6493 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
6494 zextOrTrunc(SrcBitSize).zext(DstBitSize);
6498 Ops.push_back(DAG.getUNDEF(DstEltVT));
6500 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
6503 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
6504 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6507 // Finally, this must be the case where we are shrinking elements: each input
6508 // turns into multiple outputs.
6509 bool isS2V = ISD::isScalarToVector(BV);
6510 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
6511 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
6512 NumOutputsPerInput*BV->getNumOperands());
6513 SmallVector<SDValue, 8> Ops;
6515 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
6516 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
6517 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
6518 Ops.push_back(DAG.getUNDEF(DstEltVT));
6522 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
6523 getAPIntValue().zextOrTrunc(SrcBitSize);
6525 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
6526 APInt ThisVal = OpVal.trunc(DstBitSize);
6527 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
6528 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
6529 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
6530 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
6532 OpVal = OpVal.lshr(DstBitSize);
6535 // For big endian targets, swap the order of the pieces of each element.
6536 if (TLI.isBigEndian())
6537 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
6540 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6543 SDValue DAGCombiner::visitFADD(SDNode *N) {
6544 SDValue N0 = N->getOperand(0);
6545 SDValue N1 = N->getOperand(1);
6546 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6547 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6548 EVT VT = N->getValueType(0);
6549 const TargetOptions &Options = DAG.getTarget().Options;
6552 if (VT.isVector()) {
6553 SDValue FoldedVOp = SimplifyVBinOp(N);
6554 if (FoldedVOp.getNode()) return FoldedVOp;
6557 // fold (fadd c1, c2) -> c1 + c2
6559 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N1);
6561 // canonicalize constant to RHS
6562 if (N0CFP && !N1CFP)
6563 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N0);
6565 // fold (fadd A, (fneg B)) -> (fsub A, B)
6566 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6567 isNegatibleForFree(N1, LegalOperations, TLI, &Options) == 2)
6568 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0,
6569 GetNegatedExpression(N1, DAG, LegalOperations));
6571 // fold (fadd (fneg A), B) -> (fsub B, A)
6572 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6573 isNegatibleForFree(N0, LegalOperations, TLI, &Options) == 2)
6574 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N1,
6575 GetNegatedExpression(N0, DAG, LegalOperations));
6577 // If 'unsafe math' is enabled, fold lots of things.
6578 if (Options.UnsafeFPMath) {
6579 // No FP constant should be created after legalization as Instruction
6580 // Selection pass has a hard time dealing with FP constants.
6581 bool AllowNewConst = (Level < AfterLegalizeDAG);
6583 // fold (fadd A, 0) -> A
6584 if (N1CFP && N1CFP->getValueAPF().isZero())
6587 // fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
6588 if (N1CFP && N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
6589 isa<ConstantFPSDNode>(N0.getOperand(1)))
6590 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0),
6591 DAG.getNode(ISD::FADD, SDLoc(N), VT,
6592 N0.getOperand(1), N1));
6594 // If allowed, fold (fadd (fneg x), x) -> 0.0
6595 if (AllowNewConst && N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
6596 return DAG.getConstantFP(0.0, VT);
6598 // If allowed, fold (fadd x, (fneg x)) -> 0.0
6599 if (AllowNewConst && N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
6600 return DAG.getConstantFP(0.0, VT);
6602 // We can fold chains of FADD's of the same value into multiplications.
6603 // This transform is not safe in general because we are reducing the number
6604 // of rounding steps.
6605 if (TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && !N0CFP && !N1CFP) {
6606 if (N0.getOpcode() == ISD::FMUL) {
6607 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6608 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6610 // (fadd (fmul x, c), x) -> (fmul x, c+1)
6611 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
6612 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6614 DAG.getConstantFP(1.0, VT));
6615 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, NewCFP);
6618 // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2)
6619 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
6620 N1.getOperand(0) == N1.getOperand(1) &&
6621 N0.getOperand(0) == N1.getOperand(0)) {
6622 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6624 DAG.getConstantFP(2.0, VT));
6625 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6626 N0.getOperand(0), NewCFP);
6630 if (N1.getOpcode() == ISD::FMUL) {
6631 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
6632 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
6634 // (fadd x, (fmul x, c)) -> (fmul x, c+1)
6635 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
6636 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6638 DAG.getConstantFP(1.0, VT));
6639 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, NewCFP);
6642 // (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2)
6643 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
6644 N0.getOperand(0) == N0.getOperand(1) &&
6645 N1.getOperand(0) == N0.getOperand(0)) {
6646 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6648 DAG.getConstantFP(2.0, VT));
6649 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1.getOperand(0), NewCFP);
6653 if (N0.getOpcode() == ISD::FADD && AllowNewConst) {
6654 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6655 // (fadd (fadd x, x), x) -> (fmul x, 3.0)
6656 if (!CFP && N0.getOperand(0) == N0.getOperand(1) &&
6657 (N0.getOperand(0) == N1))
6658 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6659 N1, DAG.getConstantFP(3.0, VT));
6662 if (N1.getOpcode() == ISD::FADD && AllowNewConst) {
6663 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
6664 // (fadd x, (fadd x, x)) -> (fmul x, 3.0)
6665 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) &&
6666 N1.getOperand(0) == N0)
6667 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6668 N0, DAG.getConstantFP(3.0, VT));
6671 // (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0)
6672 if (AllowNewConst &&
6673 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
6674 N0.getOperand(0) == N0.getOperand(1) &&
6675 N1.getOperand(0) == N1.getOperand(1) &&
6676 N0.getOperand(0) == N1.getOperand(0))
6677 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6678 N0.getOperand(0), DAG.getConstantFP(4.0, VT));
6680 } // enable-unsafe-fp-math
6682 // FADD -> FMA combines:
6683 if ((Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath) &&
6686 ->getTargetLowering()
6687 ->isFMAFasterThanFMulAndFAdd(VT) &&
6688 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
6690 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
6691 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse())
6692 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6693 N0.getOperand(0), N0.getOperand(1), N1);
6695 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
6696 // Note: Commutes FADD operands.
6697 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse())
6698 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6699 N1.getOperand(0), N1.getOperand(1), N0);
6705 SDValue DAGCombiner::visitFSUB(SDNode *N) {
6706 SDValue N0 = N->getOperand(0);
6707 SDValue N1 = N->getOperand(1);
6708 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
6709 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
6710 EVT VT = N->getValueType(0);
6712 const TargetOptions &Options = DAG.getTarget().Options;
6715 if (VT.isVector()) {
6716 SDValue FoldedVOp = SimplifyVBinOp(N);
6717 if (FoldedVOp.getNode()) return FoldedVOp;
6720 // fold (fsub c1, c2) -> c1-c2
6722 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, N1);
6724 // fold (fsub A, (fneg B)) -> (fadd A, B)
6725 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
6726 return DAG.getNode(ISD::FADD, dl, VT, N0,
6727 GetNegatedExpression(N1, DAG, LegalOperations));
6729 // If 'unsafe math' is enabled, fold lots of things.
6730 if (Options.UnsafeFPMath) {
6732 if (N1CFP && N1CFP->getValueAPF().isZero())
6735 // (fsub 0, B) -> -B
6736 if (N0CFP && N0CFP->getValueAPF().isZero()) {
6737 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
6738 return GetNegatedExpression(N1, DAG, LegalOperations);
6739 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6740 return DAG.getNode(ISD::FNEG, dl, VT, N1);
6743 // (fsub x, x) -> 0.0
6745 return DAG.getConstantFP(0.0f, VT);
6747 // (fsub x, (fadd x, y)) -> (fneg y)
6748 // (fsub x, (fadd y, x)) -> (fneg y)
6749 if (N1.getOpcode() == ISD::FADD) {
6750 SDValue N10 = N1->getOperand(0);
6751 SDValue N11 = N1->getOperand(1);
6753 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, &Options))
6754 return GetNegatedExpression(N11, DAG, LegalOperations);
6756 if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, &Options))
6757 return GetNegatedExpression(N10, DAG, LegalOperations);
6761 // FSUB -> FMA combines:
6762 if ((Options.AllowFPOpFusion == FPOpFusion::Fast || Options.UnsafeFPMath) &&
6763 DAG.getTarget().getSubtargetImpl()
6764 ->getTargetLowering()
6765 ->isFMAFasterThanFMulAndFAdd(VT) &&
6766 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
6768 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
6769 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse())
6770 return DAG.getNode(ISD::FMA, dl, VT,
6771 N0.getOperand(0), N0.getOperand(1),
6772 DAG.getNode(ISD::FNEG, dl, VT, N1));
6774 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
6775 // Note: Commutes FSUB operands.
6776 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse())
6777 return DAG.getNode(ISD::FMA, dl, VT,
6778 DAG.getNode(ISD::FNEG, dl, VT,
6780 N1.getOperand(1), N0);
6782 // fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
6783 if (N0.getOpcode() == ISD::FNEG &&
6784 N0.getOperand(0).getOpcode() == ISD::FMUL &&
6785 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) {
6786 SDValue N00 = N0.getOperand(0).getOperand(0);
6787 SDValue N01 = N0.getOperand(0).getOperand(1);
6788 return DAG.getNode(ISD::FMA, dl, VT,
6789 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
6790 DAG.getNode(ISD::FNEG, dl, VT, N1));
6797 SDValue DAGCombiner::visitFMUL(SDNode *N) {
6798 SDValue N0 = N->getOperand(0);
6799 SDValue N1 = N->getOperand(1);
6800 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
6801 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
6802 EVT VT = N->getValueType(0);
6803 const TargetOptions &Options = DAG.getTarget().Options;
6806 if (VT.isVector()) {
6807 SDValue FoldedVOp = SimplifyVBinOp(N);
6808 if (FoldedVOp.getNode()) return FoldedVOp;
6811 // fold (fmul c1, c2) -> c1*c2
6813 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, N1);
6815 // canonicalize constant to RHS
6816 if (N0CFP && !N1CFP)
6817 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, N0);
6819 // fold (fmul A, 1.0) -> A
6820 if (N1CFP && N1CFP->isExactlyValue(1.0))
6823 if (Options.UnsafeFPMath) {
6824 // fold (fmul A, 0) -> 0
6825 if (N1CFP && N1CFP->getValueAPF().isZero())
6828 // fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
6829 if (N1CFP && N0.getOpcode() == ISD::FMUL &&
6830 N0.getNode()->hasOneUse() && isConstOrConstSplatFP(N0.getOperand(1))) {
6832 SDValue MulConsts = DAG.getNode(ISD::FMUL, SL, VT, N0.getOperand(1), N1);
6833 return DAG.getNode(ISD::FMUL, SL, VT, N0.getOperand(0), MulConsts);
6836 // fold (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c))
6837 // Undo the fmul 2.0, x -> fadd x, x transformation, since if it occurs
6838 // during an early run of DAGCombiner can prevent folding with fmuls
6839 // inserted during lowering.
6840 if (N0.getOpcode() == ISD::FADD && N0.getOperand(0) == N0.getOperand(1)) {
6842 const SDValue Two = DAG.getConstantFP(2.0, VT);
6843 SDValue MulConsts = DAG.getNode(ISD::FMUL, SL, VT, Two, N1);
6844 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0), MulConsts);
6848 // fold (fmul X, 2.0) -> (fadd X, X)
6849 if (N1CFP && N1CFP->isExactlyValue(+2.0))
6850 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0);
6852 // fold (fmul X, -1.0) -> (fneg X)
6853 if (N1CFP && N1CFP->isExactlyValue(-1.0))
6854 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6855 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
6857 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
6858 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
6859 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
6860 // Both can be negated for free, check to see if at least one is cheaper
6862 if (LHSNeg == 2 || RHSNeg == 2)
6863 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6864 GetNegatedExpression(N0, DAG, LegalOperations),
6865 GetNegatedExpression(N1, DAG, LegalOperations));
6872 SDValue DAGCombiner::visitFMA(SDNode *N) {
6873 SDValue N0 = N->getOperand(0);
6874 SDValue N1 = N->getOperand(1);
6875 SDValue N2 = N->getOperand(2);
6876 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6877 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6878 EVT VT = N->getValueType(0);
6880 const TargetOptions &Options = DAG.getTarget().Options;
6882 // Constant fold FMA.
6883 if (isa<ConstantFPSDNode>(N0) &&
6884 isa<ConstantFPSDNode>(N1) &&
6885 isa<ConstantFPSDNode>(N2)) {
6886 return DAG.getNode(ISD::FMA, dl, VT, N0, N1, N2);
6889 if (Options.UnsafeFPMath) {
6890 if (N0CFP && N0CFP->isZero())
6892 if (N1CFP && N1CFP->isZero())
6895 if (N0CFP && N0CFP->isExactlyValue(1.0))
6896 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2);
6897 if (N1CFP && N1CFP->isExactlyValue(1.0))
6898 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
6900 // Canonicalize (fma c, x, y) -> (fma x, c, y)
6901 if (N0CFP && !N1CFP)
6902 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
6904 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
6905 if (Options.UnsafeFPMath && N1CFP &&
6906 N2.getOpcode() == ISD::FMUL &&
6907 N0 == N2.getOperand(0) &&
6908 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
6909 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6910 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
6914 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
6915 if (Options.UnsafeFPMath &&
6916 N0.getOpcode() == ISD::FMUL && N1CFP &&
6917 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
6918 return DAG.getNode(ISD::FMA, dl, VT,
6920 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
6924 // (fma x, 1, y) -> (fadd x, y)
6925 // (fma x, -1, y) -> (fadd (fneg x), y)
6927 if (N1CFP->isExactlyValue(1.0))
6928 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
6930 if (N1CFP->isExactlyValue(-1.0) &&
6931 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
6932 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
6933 AddToWorklist(RHSNeg.getNode());
6934 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
6938 // (fma x, c, x) -> (fmul x, (c+1))
6939 if (Options.UnsafeFPMath && N1CFP && N0 == N2)
6940 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6941 DAG.getNode(ISD::FADD, dl, VT,
6942 N1, DAG.getConstantFP(1.0, VT)));
6944 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
6945 if (Options.UnsafeFPMath && N1CFP &&
6946 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0)
6947 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6948 DAG.getNode(ISD::FADD, dl, VT,
6949 N1, DAG.getConstantFP(-1.0, VT)));
6955 SDValue DAGCombiner::visitFDIV(SDNode *N) {
6956 SDValue N0 = N->getOperand(0);
6957 SDValue N1 = N->getOperand(1);
6958 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6959 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6960 EVT VT = N->getValueType(0);
6961 const TargetOptions &Options = DAG.getTarget().Options;
6964 if (VT.isVector()) {
6965 SDValue FoldedVOp = SimplifyVBinOp(N);
6966 if (FoldedVOp.getNode()) return FoldedVOp;
6969 // fold (fdiv c1, c2) -> c1/c2
6971 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1);
6973 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
6974 if (N1CFP && Options.UnsafeFPMath) {
6975 // Compute the reciprocal 1.0 / c2.
6976 APFloat N1APF = N1CFP->getValueAPF();
6977 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
6978 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
6979 // Only do the transform if the reciprocal is a legal fp immediate that
6980 // isn't too nasty (eg NaN, denormal, ...).
6981 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
6982 (!LegalOperations ||
6983 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
6984 // backend)... we should handle this gracefully after Legalize.
6985 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
6986 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
6987 TLI.isFPImmLegal(Recip, VT)))
6988 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0,
6989 DAG.getConstantFP(Recip, VT));
6992 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
6993 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
6994 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
6995 // Both can be negated for free, check to see if at least one is cheaper
6997 if (LHSNeg == 2 || RHSNeg == 2)
6998 return DAG.getNode(ISD::FDIV, SDLoc(N), VT,
6999 GetNegatedExpression(N0, DAG, LegalOperations),
7000 GetNegatedExpression(N1, DAG, LegalOperations));
7007 SDValue DAGCombiner::visitFREM(SDNode *N) {
7008 SDValue N0 = N->getOperand(0);
7009 SDValue N1 = N->getOperand(1);
7010 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7011 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7012 EVT VT = N->getValueType(0);
7014 // fold (frem c1, c2) -> fmod(c1,c2)
7016 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1);
7021 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
7022 SDValue N0 = N->getOperand(0);
7023 SDValue N1 = N->getOperand(1);
7024 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7025 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7026 EVT VT = N->getValueType(0);
7028 if (N0CFP && N1CFP) // Constant fold
7029 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
7032 const APFloat& V = N1CFP->getValueAPF();
7033 // copysign(x, c1) -> fabs(x) iff ispos(c1)
7034 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
7035 if (!V.isNegative()) {
7036 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
7037 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7039 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
7040 return DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7041 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
7045 // copysign(fabs(x), y) -> copysign(x, y)
7046 // copysign(fneg(x), y) -> copysign(x, y)
7047 // copysign(copysign(x,z), y) -> copysign(x, y)
7048 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
7049 N0.getOpcode() == ISD::FCOPYSIGN)
7050 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7051 N0.getOperand(0), N1);
7053 // copysign(x, abs(y)) -> abs(x)
7054 if (N1.getOpcode() == ISD::FABS)
7055 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7057 // copysign(x, copysign(y,z)) -> copysign(x, z)
7058 if (N1.getOpcode() == ISD::FCOPYSIGN)
7059 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7060 N0, N1.getOperand(1));
7062 // copysign(x, fp_extend(y)) -> copysign(x, y)
7063 // copysign(x, fp_round(y)) -> copysign(x, y)
7064 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
7065 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7066 N0, N1.getOperand(0));
7071 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
7072 SDValue N0 = N->getOperand(0);
7073 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
7074 EVT VT = N->getValueType(0);
7075 EVT OpVT = N0.getValueType();
7077 // fold (sint_to_fp c1) -> c1fp
7079 // ...but only if the target supports immediate floating-point values
7080 (!LegalOperations ||
7081 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
7082 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
7084 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
7085 // but UINT_TO_FP is legal on this target, try to convert.
7086 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
7087 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
7088 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
7089 if (DAG.SignBitIsZero(N0))
7090 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
7093 // The next optimizations are desirable only if SELECT_CC can be lowered.
7094 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
7095 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
7096 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
7098 (!LegalOperations ||
7099 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7101 { N0.getOperand(0), N0.getOperand(1),
7102 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
7104 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7107 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
7108 // (select_cc x, y, 1.0, 0.0,, cc)
7109 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
7110 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
7111 (!LegalOperations ||
7112 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7114 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
7115 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
7116 N0.getOperand(0).getOperand(2) };
7117 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7124 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
7125 SDValue N0 = N->getOperand(0);
7126 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
7127 EVT VT = N->getValueType(0);
7128 EVT OpVT = N0.getValueType();
7130 // fold (uint_to_fp c1) -> c1fp
7132 // ...but only if the target supports immediate floating-point values
7133 (!LegalOperations ||
7134 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
7135 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
7137 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
7138 // but SINT_TO_FP is legal on this target, try to convert.
7139 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
7140 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
7141 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
7142 if (DAG.SignBitIsZero(N0))
7143 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
7146 // The next optimizations are desirable only if SELECT_CC can be lowered.
7147 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
7148 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
7150 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
7151 (!LegalOperations ||
7152 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7154 { N0.getOperand(0), N0.getOperand(1),
7155 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
7157 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7164 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
7165 SDValue N0 = N->getOperand(0);
7166 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7167 EVT VT = N->getValueType(0);
7169 // fold (fp_to_sint c1fp) -> c1
7171 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
7176 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
7177 SDValue N0 = N->getOperand(0);
7178 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7179 EVT VT = N->getValueType(0);
7181 // fold (fp_to_uint c1fp) -> c1
7183 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
7188 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
7189 SDValue N0 = N->getOperand(0);
7190 SDValue N1 = N->getOperand(1);
7191 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7192 EVT VT = N->getValueType(0);
7194 // fold (fp_round c1fp) -> c1fp
7196 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
7198 // fold (fp_round (fp_extend x)) -> x
7199 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
7200 return N0.getOperand(0);
7202 // fold (fp_round (fp_round x)) -> (fp_round x)
7203 if (N0.getOpcode() == ISD::FP_ROUND) {
7204 // This is a value preserving truncation if both round's are.
7205 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
7206 N0.getNode()->getConstantOperandVal(1) == 1;
7207 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0.getOperand(0),
7208 DAG.getIntPtrConstant(IsTrunc));
7211 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
7212 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
7213 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
7214 N0.getOperand(0), N1);
7215 AddToWorklist(Tmp.getNode());
7216 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7217 Tmp, N0.getOperand(1));
7223 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
7224 SDValue N0 = N->getOperand(0);
7225 EVT VT = N->getValueType(0);
7226 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
7227 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7229 // fold (fp_round_inreg c1fp) -> c1fp
7230 if (N0CFP && isTypeLegal(EVT)) {
7231 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
7232 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Round);
7238 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
7239 SDValue N0 = N->getOperand(0);
7240 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7241 EVT VT = N->getValueType(0);
7243 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
7244 if (N->hasOneUse() &&
7245 N->use_begin()->getOpcode() == ISD::FP_ROUND)
7248 // fold (fp_extend c1fp) -> c1fp
7250 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
7252 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
7254 if (N0.getOpcode() == ISD::FP_ROUND
7255 && N0.getNode()->getConstantOperandVal(1) == 1) {
7256 SDValue In = N0.getOperand(0);
7257 if (In.getValueType() == VT) return In;
7258 if (VT.bitsLT(In.getValueType()))
7259 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT,
7260 In, N0.getOperand(1));
7261 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In);
7264 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
7265 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7266 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType())) {
7267 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7268 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
7270 LN0->getBasePtr(), N0.getValueType(),
7271 LN0->getMemOperand());
7272 CombineTo(N, ExtLoad);
7273 CombineTo(N0.getNode(),
7274 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
7275 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
7276 ExtLoad.getValue(1));
7277 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7283 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
7284 SDValue N0 = N->getOperand(0);
7285 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7286 EVT VT = N->getValueType(0);
7288 // fold (fceil c1) -> fceil(c1)
7290 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
7295 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
7296 SDValue N0 = N->getOperand(0);
7297 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7298 EVT VT = N->getValueType(0);
7300 // fold (ftrunc c1) -> ftrunc(c1)
7302 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
7307 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
7308 SDValue N0 = N->getOperand(0);
7309 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7310 EVT VT = N->getValueType(0);
7312 // fold (ffloor c1) -> ffloor(c1)
7314 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
7319 // FIXME: FNEG and FABS have a lot in common; refactor.
7320 SDValue DAGCombiner::visitFNEG(SDNode *N) {
7321 SDValue N0 = N->getOperand(0);
7322 EVT VT = N->getValueType(0);
7324 if (VT.isVector()) {
7325 SDValue FoldedVOp = SimplifyVUnaryOp(N);
7326 if (FoldedVOp.getNode()) return FoldedVOp;
7329 // Constant fold FNEG.
7330 if (isa<ConstantFPSDNode>(N0))
7331 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N->getOperand(0));
7333 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
7334 &DAG.getTarget().Options))
7335 return GetNegatedExpression(N0, DAG, LegalOperations);
7337 // Transform fneg(bitconvert(x)) -> bitconvert(x ^ sign) to avoid loading
7338 // constant pool values.
7339 if (!TLI.isFNegFree(VT) &&
7340 N0.getOpcode() == ISD::BITCAST &&
7341 N0.getNode()->hasOneUse()) {
7342 SDValue Int = N0.getOperand(0);
7343 EVT IntVT = Int.getValueType();
7344 if (IntVT.isInteger() && !IntVT.isVector()) {
7346 if (N0.getValueType().isVector()) {
7347 // For a vector, get a mask such as 0x80... per scalar element
7349 SignMask = APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
7350 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
7352 // For a scalar, just generate 0x80...
7353 SignMask = APInt::getSignBit(IntVT.getSizeInBits());
7355 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int,
7356 DAG.getConstant(SignMask, IntVT));
7357 AddToWorklist(Int.getNode());
7358 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Int);
7362 // (fneg (fmul c, x)) -> (fmul -c, x)
7363 if (N0.getOpcode() == ISD::FMUL) {
7364 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
7366 APFloat CVal = CFP1->getValueAPF();
7368 if (Level >= AfterLegalizeDAG &&
7369 (TLI.isFPImmLegal(CVal, N->getValueType(0)) ||
7370 TLI.isOperationLegal(ISD::ConstantFP, N->getValueType(0))))
7372 ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
7373 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0.getOperand(1)));
7380 SDValue DAGCombiner::visitFABS(SDNode *N) {
7381 SDValue N0 = N->getOperand(0);
7382 EVT VT = N->getValueType(0);
7384 if (VT.isVector()) {
7385 SDValue FoldedVOp = SimplifyVUnaryOp(N);
7386 if (FoldedVOp.getNode()) return FoldedVOp;
7389 // fold (fabs c1) -> fabs(c1)
7390 if (isa<ConstantFPSDNode>(N0))
7391 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7393 // fold (fabs (fabs x)) -> (fabs x)
7394 if (N0.getOpcode() == ISD::FABS)
7395 return N->getOperand(0);
7397 // fold (fabs (fneg x)) -> (fabs x)
7398 // fold (fabs (fcopysign x, y)) -> (fabs x)
7399 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
7400 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
7402 // Transform fabs(bitconvert(x)) -> bitconvert(x & ~sign) to avoid loading
7403 // constant pool values.
7404 if (!TLI.isFAbsFree(VT) &&
7405 N0.getOpcode() == ISD::BITCAST &&
7406 N0.getNode()->hasOneUse()) {
7407 SDValue Int = N0.getOperand(0);
7408 EVT IntVT = Int.getValueType();
7409 if (IntVT.isInteger() && !IntVT.isVector()) {
7411 if (N0.getValueType().isVector()) {
7412 // For a vector, get a mask such as 0x7f... per scalar element
7414 SignMask = ~APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
7415 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
7417 // For a scalar, just generate 0x7f...
7418 SignMask = ~APInt::getSignBit(IntVT.getSizeInBits());
7420 Int = DAG.getNode(ISD::AND, SDLoc(N0), IntVT, Int,
7421 DAG.getConstant(SignMask, IntVT));
7422 AddToWorklist(Int.getNode());
7423 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Int);
7430 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
7431 SDValue Chain = N->getOperand(0);
7432 SDValue N1 = N->getOperand(1);
7433 SDValue N2 = N->getOperand(2);
7435 // If N is a constant we could fold this into a fallthrough or unconditional
7436 // branch. However that doesn't happen very often in normal code, because
7437 // Instcombine/SimplifyCFG should have handled the available opportunities.
7438 // If we did this folding here, it would be necessary to update the
7439 // MachineBasicBlock CFG, which is awkward.
7441 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
7443 if (N1.getOpcode() == ISD::SETCC &&
7444 TLI.isOperationLegalOrCustom(ISD::BR_CC,
7445 N1.getOperand(0).getValueType())) {
7446 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
7447 Chain, N1.getOperand(2),
7448 N1.getOperand(0), N1.getOperand(1), N2);
7451 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
7452 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
7453 (N1.getOperand(0).hasOneUse() &&
7454 N1.getOperand(0).getOpcode() == ISD::SRL))) {
7455 SDNode *Trunc = nullptr;
7456 if (N1.getOpcode() == ISD::TRUNCATE) {
7457 // Look pass the truncate.
7458 Trunc = N1.getNode();
7459 N1 = N1.getOperand(0);
7462 // Match this pattern so that we can generate simpler code:
7465 // %b = and i32 %a, 2
7466 // %c = srl i32 %b, 1
7467 // brcond i32 %c ...
7472 // %b = and i32 %a, 2
7473 // %c = setcc eq %b, 0
7476 // This applies only when the AND constant value has one bit set and the
7477 // SRL constant is equal to the log2 of the AND constant. The back-end is
7478 // smart enough to convert the result into a TEST/JMP sequence.
7479 SDValue Op0 = N1.getOperand(0);
7480 SDValue Op1 = N1.getOperand(1);
7482 if (Op0.getOpcode() == ISD::AND &&
7483 Op1.getOpcode() == ISD::Constant) {
7484 SDValue AndOp1 = Op0.getOperand(1);
7486 if (AndOp1.getOpcode() == ISD::Constant) {
7487 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
7489 if (AndConst.isPowerOf2() &&
7490 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
7492 DAG.getSetCC(SDLoc(N),
7493 getSetCCResultType(Op0.getValueType()),
7494 Op0, DAG.getConstant(0, Op0.getValueType()),
7497 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, SDLoc(N),
7498 MVT::Other, Chain, SetCC, N2);
7499 // Don't add the new BRCond into the worklist or else SimplifySelectCC
7500 // will convert it back to (X & C1) >> C2.
7501 CombineTo(N, NewBRCond, false);
7502 // Truncate is dead.
7504 deleteAndRecombine(Trunc);
7505 // Replace the uses of SRL with SETCC
7506 WorklistRemover DeadNodes(*this);
7507 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
7508 deleteAndRecombine(N1.getNode());
7509 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7515 // Restore N1 if the above transformation doesn't match.
7516 N1 = N->getOperand(1);
7519 // Transform br(xor(x, y)) -> br(x != y)
7520 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
7521 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
7522 SDNode *TheXor = N1.getNode();
7523 SDValue Op0 = TheXor->getOperand(0);
7524 SDValue Op1 = TheXor->getOperand(1);
7525 if (Op0.getOpcode() == Op1.getOpcode()) {
7526 // Avoid missing important xor optimizations.
7527 SDValue Tmp = visitXOR(TheXor);
7528 if (Tmp.getNode()) {
7529 if (Tmp.getNode() != TheXor) {
7530 DEBUG(dbgs() << "\nReplacing.8 ";
7532 dbgs() << "\nWith: ";
7533 Tmp.getNode()->dump(&DAG);
7535 WorklistRemover DeadNodes(*this);
7536 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
7537 deleteAndRecombine(TheXor);
7538 return DAG.getNode(ISD::BRCOND, SDLoc(N),
7539 MVT::Other, Chain, Tmp, N2);
7542 // visitXOR has changed XOR's operands or replaced the XOR completely,
7544 return SDValue(N, 0);
7548 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
7550 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
7551 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
7552 Op0.getOpcode() == ISD::XOR) {
7553 TheXor = Op0.getNode();
7557 EVT SetCCVT = N1.getValueType();
7559 SetCCVT = getSetCCResultType(SetCCVT);
7560 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor),
7563 Equal ? ISD::SETEQ : ISD::SETNE);
7564 // Replace the uses of XOR with SETCC
7565 WorklistRemover DeadNodes(*this);
7566 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
7567 deleteAndRecombine(N1.getNode());
7568 return DAG.getNode(ISD::BRCOND, SDLoc(N),
7569 MVT::Other, Chain, SetCC, N2);
7576 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
7578 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
7579 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
7580 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
7582 // If N is a constant we could fold this into a fallthrough or unconditional
7583 // branch. However that doesn't happen very often in normal code, because
7584 // Instcombine/SimplifyCFG should have handled the available opportunities.
7585 // If we did this folding here, it would be necessary to update the
7586 // MachineBasicBlock CFG, which is awkward.
7588 // Use SimplifySetCC to simplify SETCC's.
7589 SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()),
7590 CondLHS, CondRHS, CC->get(), SDLoc(N),
7592 if (Simp.getNode()) AddToWorklist(Simp.getNode());
7594 // fold to a simpler setcc
7595 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
7596 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
7597 N->getOperand(0), Simp.getOperand(2),
7598 Simp.getOperand(0), Simp.getOperand(1),
7604 /// Return true if 'Use' is a load or a store that uses N as its base pointer
7605 /// and that N may be folded in the load / store addressing mode.
7606 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
7608 const TargetLowering &TLI) {
7610 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
7611 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
7613 VT = Use->getValueType(0);
7614 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
7615 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
7617 VT = ST->getValue().getValueType();
7621 TargetLowering::AddrMode AM;
7622 if (N->getOpcode() == ISD::ADD) {
7623 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
7626 AM.BaseOffs = Offset->getSExtValue();
7630 } else if (N->getOpcode() == ISD::SUB) {
7631 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
7634 AM.BaseOffs = -Offset->getSExtValue();
7641 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
7644 /// Try turning a load/store into a pre-indexed load/store when the base
7645 /// pointer is an add or subtract and it has other uses besides the load/store.
7646 /// After the transformation, the new indexed load/store has effectively folded
7647 /// the add/subtract in and all of its other uses are redirected to the
7649 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
7650 if (Level < AfterLegalizeDAG)
7656 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7657 if (LD->isIndexed())
7659 VT = LD->getMemoryVT();
7660 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
7661 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
7663 Ptr = LD->getBasePtr();
7664 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7665 if (ST->isIndexed())
7667 VT = ST->getMemoryVT();
7668 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
7669 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
7671 Ptr = ST->getBasePtr();
7677 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
7678 // out. There is no reason to make this a preinc/predec.
7679 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
7680 Ptr.getNode()->hasOneUse())
7683 // Ask the target to do addressing mode selection.
7686 ISD::MemIndexedMode AM = ISD::UNINDEXED;
7687 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
7690 // Backends without true r+i pre-indexed forms may need to pass a
7691 // constant base with a variable offset so that constant coercion
7692 // will work with the patterns in canonical form.
7693 bool Swapped = false;
7694 if (isa<ConstantSDNode>(BasePtr)) {
7695 std::swap(BasePtr, Offset);
7699 // Don't create a indexed load / store with zero offset.
7700 if (isa<ConstantSDNode>(Offset) &&
7701 cast<ConstantSDNode>(Offset)->isNullValue())
7704 // Try turning it into a pre-indexed load / store except when:
7705 // 1) The new base ptr is a frame index.
7706 // 2) If N is a store and the new base ptr is either the same as or is a
7707 // predecessor of the value being stored.
7708 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
7709 // that would create a cycle.
7710 // 4) All uses are load / store ops that use it as old base ptr.
7712 // Check #1. Preinc'ing a frame index would require copying the stack pointer
7713 // (plus the implicit offset) to a register to preinc anyway.
7714 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
7719 SDValue Val = cast<StoreSDNode>(N)->getValue();
7720 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
7724 // If the offset is a constant, there may be other adds of constants that
7725 // can be folded with this one. We should do this to avoid having to keep
7726 // a copy of the original base pointer.
7727 SmallVector<SDNode *, 16> OtherUses;
7728 if (isa<ConstantSDNode>(Offset))
7729 for (SDNode *Use : BasePtr.getNode()->uses()) {
7730 if (Use == Ptr.getNode())
7733 if (Use->isPredecessorOf(N))
7736 if (Use->getOpcode() != ISD::ADD && Use->getOpcode() != ISD::SUB) {
7741 SDValue Op0 = Use->getOperand(0), Op1 = Use->getOperand(1);
7742 if (Op1.getNode() == BasePtr.getNode())
7743 std::swap(Op0, Op1);
7744 assert(Op0.getNode() == BasePtr.getNode() &&
7745 "Use of ADD/SUB but not an operand");
7747 if (!isa<ConstantSDNode>(Op1)) {
7752 // FIXME: In some cases, we can be smarter about this.
7753 if (Op1.getValueType() != Offset.getValueType()) {
7758 OtherUses.push_back(Use);
7762 std::swap(BasePtr, Offset);
7764 // Now check for #3 and #4.
7765 bool RealUse = false;
7767 // Caches for hasPredecessorHelper
7768 SmallPtrSet<const SDNode *, 32> Visited;
7769 SmallVector<const SDNode *, 16> Worklist;
7771 for (SDNode *Use : Ptr.getNode()->uses()) {
7774 if (N->hasPredecessorHelper(Use, Visited, Worklist))
7777 // If Ptr may be folded in addressing mode of other use, then it's
7778 // not profitable to do this transformation.
7779 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
7788 Result = DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
7789 BasePtr, Offset, AM);
7791 Result = DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
7792 BasePtr, Offset, AM);
7795 DEBUG(dbgs() << "\nReplacing.4 ";
7797 dbgs() << "\nWith: ";
7798 Result.getNode()->dump(&DAG);
7800 WorklistRemover DeadNodes(*this);
7802 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
7803 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
7805 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
7808 // Finally, since the node is now dead, remove it from the graph.
7809 deleteAndRecombine(N);
7812 std::swap(BasePtr, Offset);
7814 // Replace other uses of BasePtr that can be updated to use Ptr
7815 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) {
7816 unsigned OffsetIdx = 1;
7817 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode())
7819 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() ==
7820 BasePtr.getNode() && "Expected BasePtr operand");
7822 // We need to replace ptr0 in the following expression:
7823 // x0 * offset0 + y0 * ptr0 = t0
7825 // x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store)
7827 // where x0, x1, y0 and y1 in {-1, 1} are given by the types of the
7828 // indexed load/store and the expresion that needs to be re-written.
7830 // Therefore, we have:
7831 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
7833 ConstantSDNode *CN =
7834 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
7836 APInt Offset0 = CN->getAPIntValue();
7837 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
7839 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
7840 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
7841 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1;
7842 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1;
7844 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD;
7846 APInt CNV = Offset0;
7847 if (X0 < 0) CNV = -CNV;
7848 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1;
7849 else CNV = CNV - Offset1;
7851 // We can now generate the new expression.
7852 SDValue NewOp1 = DAG.getConstant(CNV, CN->getValueType(0));
7853 SDValue NewOp2 = Result.getValue(isLoad ? 1 : 0);
7855 SDValue NewUse = DAG.getNode(Opcode,
7856 SDLoc(OtherUses[i]),
7857 OtherUses[i]->getValueType(0), NewOp1, NewOp2);
7858 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse);
7859 deleteAndRecombine(OtherUses[i]);
7862 // Replace the uses of Ptr with uses of the updated base value.
7863 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
7864 deleteAndRecombine(Ptr.getNode());
7869 /// Try to combine a load/store with a add/sub of the base pointer node into a
7870 /// post-indexed load/store. The transformation folded the add/subtract into the
7871 /// new indexed load/store effectively and all of its uses are redirected to the
7873 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
7874 if (Level < AfterLegalizeDAG)
7880 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7881 if (LD->isIndexed())
7883 VT = LD->getMemoryVT();
7884 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
7885 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
7887 Ptr = LD->getBasePtr();
7888 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7889 if (ST->isIndexed())
7891 VT = ST->getMemoryVT();
7892 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
7893 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
7895 Ptr = ST->getBasePtr();
7901 if (Ptr.getNode()->hasOneUse())
7904 for (SDNode *Op : Ptr.getNode()->uses()) {
7906 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
7911 ISD::MemIndexedMode AM = ISD::UNINDEXED;
7912 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
7913 // Don't create a indexed load / store with zero offset.
7914 if (isa<ConstantSDNode>(Offset) &&
7915 cast<ConstantSDNode>(Offset)->isNullValue())
7918 // Try turning it into a post-indexed load / store except when
7919 // 1) All uses are load / store ops that use it as base ptr (and
7920 // it may be folded as addressing mmode).
7921 // 2) Op must be independent of N, i.e. Op is neither a predecessor
7922 // nor a successor of N. Otherwise, if Op is folded that would
7925 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
7929 bool TryNext = false;
7930 for (SDNode *Use : BasePtr.getNode()->uses()) {
7931 if (Use == Ptr.getNode())
7934 // If all the uses are load / store addresses, then don't do the
7936 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
7937 bool RealUse = false;
7938 for (SDNode *UseUse : Use->uses()) {
7939 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
7954 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
7955 SDValue Result = isLoad
7956 ? DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
7957 BasePtr, Offset, AM)
7958 : DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
7959 BasePtr, Offset, AM);
7962 DEBUG(dbgs() << "\nReplacing.5 ";
7964 dbgs() << "\nWith: ";
7965 Result.getNode()->dump(&DAG);
7967 WorklistRemover DeadNodes(*this);
7969 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
7970 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
7972 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
7975 // Finally, since the node is now dead, remove it from the graph.
7976 deleteAndRecombine(N);
7978 // Replace the uses of Use with uses of the updated base value.
7979 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
7980 Result.getValue(isLoad ? 1 : 0));
7981 deleteAndRecombine(Op);
7990 /// \brief Return the base-pointer arithmetic from an indexed \p LD.
7991 SDValue DAGCombiner::SplitIndexingFromLoad(LoadSDNode *LD) {
7992 ISD::MemIndexedMode AM = LD->getAddressingMode();
7993 assert(AM != ISD::UNINDEXED);
7994 SDValue BP = LD->getOperand(1);
7995 SDValue Inc = LD->getOperand(2);
7997 // Some backends use TargetConstants for load offsets, but don't expect
7998 // TargetConstants in general ADD nodes. We can convert these constants into
7999 // regular Constants (if the constant is not opaque).
8000 assert((Inc.getOpcode() != ISD::TargetConstant ||
8001 !cast<ConstantSDNode>(Inc)->isOpaque()) &&
8002 "Cannot split out indexing using opaque target constants");
8003 if (Inc.getOpcode() == ISD::TargetConstant) {
8004 ConstantSDNode *ConstInc = cast<ConstantSDNode>(Inc);
8005 Inc = DAG.getConstant(*ConstInc->getConstantIntValue(),
8006 ConstInc->getValueType(0));
8010 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB);
8011 return DAG.getNode(Opc, SDLoc(LD), BP.getSimpleValueType(), BP, Inc);
8014 SDValue DAGCombiner::visitLOAD(SDNode *N) {
8015 LoadSDNode *LD = cast<LoadSDNode>(N);
8016 SDValue Chain = LD->getChain();
8017 SDValue Ptr = LD->getBasePtr();
8019 // If load is not volatile and there are no uses of the loaded value (and
8020 // the updated indexed value in case of indexed loads), change uses of the
8021 // chain value into uses of the chain input (i.e. delete the dead load).
8022 if (!LD->isVolatile()) {
8023 if (N->getValueType(1) == MVT::Other) {
8025 if (!N->hasAnyUseOfValue(0)) {
8026 // It's not safe to use the two value CombineTo variant here. e.g.
8027 // v1, chain2 = load chain1, loc
8028 // v2, chain3 = load chain2, loc
8030 // Now we replace use of chain2 with chain1. This makes the second load
8031 // isomorphic to the one we are deleting, and thus makes this load live.
8032 DEBUG(dbgs() << "\nReplacing.6 ";
8034 dbgs() << "\nWith chain: ";
8035 Chain.getNode()->dump(&DAG);
8037 WorklistRemover DeadNodes(*this);
8038 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
8041 deleteAndRecombine(N);
8043 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8047 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
8049 // If this load has an opaque TargetConstant offset, then we cannot split
8050 // the indexing into an add/sub directly (that TargetConstant may not be
8051 // valid for a different type of node, and we cannot convert an opaque
8052 // target constant into a regular constant).
8053 bool HasOTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant &&
8054 cast<ConstantSDNode>(LD->getOperand(2))->isOpaque();
8056 if (!N->hasAnyUseOfValue(0) &&
8057 ((MaySplitLoadIndex && !HasOTCInc) || !N->hasAnyUseOfValue(1))) {
8058 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
8060 if (N->hasAnyUseOfValue(1) && MaySplitLoadIndex && !HasOTCInc) {
8061 Index = SplitIndexingFromLoad(LD);
8062 // Try to fold the base pointer arithmetic into subsequent loads and
8064 AddUsersToWorklist(N);
8066 Index = DAG.getUNDEF(N->getValueType(1));
8067 DEBUG(dbgs() << "\nReplacing.7 ";
8069 dbgs() << "\nWith: ";
8070 Undef.getNode()->dump(&DAG);
8071 dbgs() << " and 2 other values\n");
8072 WorklistRemover DeadNodes(*this);
8073 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
8074 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Index);
8075 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
8076 deleteAndRecombine(N);
8077 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8082 // If this load is directly stored, replace the load value with the stored
8084 // TODO: Handle store large -> read small portion.
8085 // TODO: Handle TRUNCSTORE/LOADEXT
8086 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
8087 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
8088 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
8089 if (PrevST->getBasePtr() == Ptr &&
8090 PrevST->getValue().getValueType() == N->getValueType(0))
8091 return CombineTo(N, Chain.getOperand(1), Chain);
8095 // Try to infer better alignment information than the load already has.
8096 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
8097 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
8098 if (Align > LD->getMemOperand()->getBaseAlignment()) {
8100 DAG.getExtLoad(LD->getExtensionType(), SDLoc(N),
8101 LD->getValueType(0),
8102 Chain, Ptr, LD->getPointerInfo(),
8104 LD->isVolatile(), LD->isNonTemporal(),
8105 LD->isInvariant(), Align, LD->getAAInfo());
8106 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
8111 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA :
8112 TLI.getTargetMachine().getSubtarget<TargetSubtargetInfo>().useAA();
8114 if (CombinerAAOnlyFunc.getNumOccurrences() &&
8115 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
8118 if (UseAA && LD->isUnindexed()) {
8119 // Walk up chain skipping non-aliasing memory nodes.
8120 SDValue BetterChain = FindBetterChain(N, Chain);
8122 // If there is a better chain.
8123 if (Chain != BetterChain) {
8126 // Replace the chain to void dependency.
8127 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
8128 ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD),
8129 BetterChain, Ptr, LD->getMemOperand());
8131 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD),
8132 LD->getValueType(0),
8133 BetterChain, Ptr, LD->getMemoryVT(),
8134 LD->getMemOperand());
8137 // Create token factor to keep old chain connected.
8138 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
8139 MVT::Other, Chain, ReplLoad.getValue(1));
8141 // Make sure the new and old chains are cleaned up.
8142 AddToWorklist(Token.getNode());
8144 // Replace uses with load result and token factor. Don't add users
8146 return CombineTo(N, ReplLoad.getValue(0), Token, false);
8150 // Try transforming N to an indexed load.
8151 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
8152 return SDValue(N, 0);
8154 // Try to slice up N to more direct loads if the slices are mapped to
8155 // different register banks or pairing can take place.
8157 return SDValue(N, 0);
8163 /// \brief Helper structure used to slice a load in smaller loads.
8164 /// Basically a slice is obtained from the following sequence:
8165 /// Origin = load Ty1, Base
8166 /// Shift = srl Ty1 Origin, CstTy Amount
8167 /// Inst = trunc Shift to Ty2
8169 /// Then, it will be rewriten into:
8170 /// Slice = load SliceTy, Base + SliceOffset
8171 /// [Inst = zext Slice to Ty2], only if SliceTy <> Ty2
8173 /// SliceTy is deduced from the number of bits that are actually used to
8175 struct LoadedSlice {
8176 /// \brief Helper structure used to compute the cost of a slice.
8178 /// Are we optimizing for code size.
8183 unsigned CrossRegisterBanksCopies;
8187 Cost(bool ForCodeSize = false)
8188 : ForCodeSize(ForCodeSize), Loads(0), Truncates(0),
8189 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {}
8191 /// \brief Get the cost of one isolated slice.
8192 Cost(const LoadedSlice &LS, bool ForCodeSize = false)
8193 : ForCodeSize(ForCodeSize), Loads(1), Truncates(0),
8194 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {
8195 EVT TruncType = LS.Inst->getValueType(0);
8196 EVT LoadedType = LS.getLoadedType();
8197 if (TruncType != LoadedType &&
8198 !LS.DAG->getTargetLoweringInfo().isZExtFree(LoadedType, TruncType))
8202 /// \brief Account for slicing gain in the current cost.
8203 /// Slicing provide a few gains like removing a shift or a
8204 /// truncate. This method allows to grow the cost of the original
8205 /// load with the gain from this slice.
8206 void addSliceGain(const LoadedSlice &LS) {
8207 // Each slice saves a truncate.
8208 const TargetLowering &TLI = LS.DAG->getTargetLoweringInfo();
8209 if (!TLI.isTruncateFree(LS.Inst->getValueType(0),
8210 LS.Inst->getOperand(0).getValueType()))
8212 // If there is a shift amount, this slice gets rid of it.
8215 // If this slice can merge a cross register bank copy, account for it.
8216 if (LS.canMergeExpensiveCrossRegisterBankCopy())
8217 ++CrossRegisterBanksCopies;
8220 Cost &operator+=(const Cost &RHS) {
8222 Truncates += RHS.Truncates;
8223 CrossRegisterBanksCopies += RHS.CrossRegisterBanksCopies;
8229 bool operator==(const Cost &RHS) const {
8230 return Loads == RHS.Loads && Truncates == RHS.Truncates &&
8231 CrossRegisterBanksCopies == RHS.CrossRegisterBanksCopies &&
8232 ZExts == RHS.ZExts && Shift == RHS.Shift;
8235 bool operator!=(const Cost &RHS) const { return !(*this == RHS); }
8237 bool operator<(const Cost &RHS) const {
8238 // Assume cross register banks copies are as expensive as loads.
8239 // FIXME: Do we want some more target hooks?
8240 unsigned ExpensiveOpsLHS = Loads + CrossRegisterBanksCopies;
8241 unsigned ExpensiveOpsRHS = RHS.Loads + RHS.CrossRegisterBanksCopies;
8242 // Unless we are optimizing for code size, consider the
8243 // expensive operation first.
8244 if (!ForCodeSize && ExpensiveOpsLHS != ExpensiveOpsRHS)
8245 return ExpensiveOpsLHS < ExpensiveOpsRHS;
8246 return (Truncates + ZExts + Shift + ExpensiveOpsLHS) <
8247 (RHS.Truncates + RHS.ZExts + RHS.Shift + ExpensiveOpsRHS);
8250 bool operator>(const Cost &RHS) const { return RHS < *this; }
8252 bool operator<=(const Cost &RHS) const { return !(RHS < *this); }
8254 bool operator>=(const Cost &RHS) const { return !(*this < RHS); }
8256 // The last instruction that represent the slice. This should be a
8257 // truncate instruction.
8259 // The original load instruction.
8261 // The right shift amount in bits from the original load.
8263 // The DAG from which Origin came from.
8264 // This is used to get some contextual information about legal types, etc.
8267 LoadedSlice(SDNode *Inst = nullptr, LoadSDNode *Origin = nullptr,
8268 unsigned Shift = 0, SelectionDAG *DAG = nullptr)
8269 : Inst(Inst), Origin(Origin), Shift(Shift), DAG(DAG) {}
8271 LoadedSlice(const LoadedSlice &LS)
8272 : Inst(LS.Inst), Origin(LS.Origin), Shift(LS.Shift), DAG(LS.DAG) {}
8274 /// \brief Get the bits used in a chunk of bits \p BitWidth large.
8275 /// \return Result is \p BitWidth and has used bits set to 1 and
8276 /// not used bits set to 0.
8277 APInt getUsedBits() const {
8278 // Reproduce the trunc(lshr) sequence:
8279 // - Start from the truncated value.
8280 // - Zero extend to the desired bit width.
8282 assert(Origin && "No original load to compare against.");
8283 unsigned BitWidth = Origin->getValueSizeInBits(0);
8284 assert(Inst && "This slice is not bound to an instruction");
8285 assert(Inst->getValueSizeInBits(0) <= BitWidth &&
8286 "Extracted slice is bigger than the whole type!");
8287 APInt UsedBits(Inst->getValueSizeInBits(0), 0);
8288 UsedBits.setAllBits();
8289 UsedBits = UsedBits.zext(BitWidth);
8294 /// \brief Get the size of the slice to be loaded in bytes.
8295 unsigned getLoadedSize() const {
8296 unsigned SliceSize = getUsedBits().countPopulation();
8297 assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte.");
8298 return SliceSize / 8;
8301 /// \brief Get the type that will be loaded for this slice.
8302 /// Note: This may not be the final type for the slice.
8303 EVT getLoadedType() const {
8304 assert(DAG && "Missing context");
8305 LLVMContext &Ctxt = *DAG->getContext();
8306 return EVT::getIntegerVT(Ctxt, getLoadedSize() * 8);
8309 /// \brief Get the alignment of the load used for this slice.
8310 unsigned getAlignment() const {
8311 unsigned Alignment = Origin->getAlignment();
8312 unsigned Offset = getOffsetFromBase();
8314 Alignment = MinAlign(Alignment, Alignment + Offset);
8318 /// \brief Check if this slice can be rewritten with legal operations.
8319 bool isLegal() const {
8320 // An invalid slice is not legal.
8321 if (!Origin || !Inst || !DAG)
8324 // Offsets are for indexed load only, we do not handle that.
8325 if (Origin->getOffset().getOpcode() != ISD::UNDEF)
8328 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
8330 // Check that the type is legal.
8331 EVT SliceType = getLoadedType();
8332 if (!TLI.isTypeLegal(SliceType))
8335 // Check that the load is legal for this type.
8336 if (!TLI.isOperationLegal(ISD::LOAD, SliceType))
8339 // Check that the offset can be computed.
8340 // 1. Check its type.
8341 EVT PtrType = Origin->getBasePtr().getValueType();
8342 if (PtrType == MVT::Untyped || PtrType.isExtended())
8345 // 2. Check that it fits in the immediate.
8346 if (!TLI.isLegalAddImmediate(getOffsetFromBase()))
8349 // 3. Check that the computation is legal.
8350 if (!TLI.isOperationLegal(ISD::ADD, PtrType))
8353 // Check that the zext is legal if it needs one.
8354 EVT TruncateType = Inst->getValueType(0);
8355 if (TruncateType != SliceType &&
8356 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType))
8362 /// \brief Get the offset in bytes of this slice in the original chunk of
8364 /// \pre DAG != nullptr.
8365 uint64_t getOffsetFromBase() const {
8366 assert(DAG && "Missing context.");
8368 DAG->getTargetLoweringInfo().getDataLayout()->isBigEndian();
8369 assert(!(Shift & 0x7) && "Shifts not aligned on Bytes are not supported.");
8370 uint64_t Offset = Shift / 8;
8371 unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / 8;
8372 assert(!(Origin->getValueSizeInBits(0) & 0x7) &&
8373 "The size of the original loaded type is not a multiple of a"
8375 // If Offset is bigger than TySizeInBytes, it means we are loading all
8376 // zeros. This should have been optimized before in the process.
8377 assert(TySizeInBytes > Offset &&
8378 "Invalid shift amount for given loaded size");
8380 Offset = TySizeInBytes - Offset - getLoadedSize();
8384 /// \brief Generate the sequence of instructions to load the slice
8385 /// represented by this object and redirect the uses of this slice to
8386 /// this new sequence of instructions.
8387 /// \pre this->Inst && this->Origin are valid Instructions and this
8388 /// object passed the legal check: LoadedSlice::isLegal returned true.
8389 /// \return The last instruction of the sequence used to load the slice.
8390 SDValue loadSlice() const {
8391 assert(Inst && Origin && "Unable to replace a non-existing slice.");
8392 const SDValue &OldBaseAddr = Origin->getBasePtr();
8393 SDValue BaseAddr = OldBaseAddr;
8394 // Get the offset in that chunk of bytes w.r.t. the endianess.
8395 int64_t Offset = static_cast<int64_t>(getOffsetFromBase());
8396 assert(Offset >= 0 && "Offset too big to fit in int64_t!");
8398 // BaseAddr = BaseAddr + Offset.
8399 EVT ArithType = BaseAddr.getValueType();
8400 BaseAddr = DAG->getNode(ISD::ADD, SDLoc(Origin), ArithType, BaseAddr,
8401 DAG->getConstant(Offset, ArithType));
8404 // Create the type of the loaded slice according to its size.
8405 EVT SliceType = getLoadedType();
8407 // Create the load for the slice.
8408 SDValue LastInst = DAG->getLoad(
8409 SliceType, SDLoc(Origin), Origin->getChain(), BaseAddr,
8410 Origin->getPointerInfo().getWithOffset(Offset), Origin->isVolatile(),
8411 Origin->isNonTemporal(), Origin->isInvariant(), getAlignment());
8412 // If the final type is not the same as the loaded type, this means that
8413 // we have to pad with zero. Create a zero extend for that.
8414 EVT FinalType = Inst->getValueType(0);
8415 if (SliceType != FinalType)
8417 DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst);
8421 /// \brief Check if this slice can be merged with an expensive cross register
8422 /// bank copy. E.g.,
8424 /// f = bitcast i32 i to float
8425 bool canMergeExpensiveCrossRegisterBankCopy() const {
8426 if (!Inst || !Inst->hasOneUse())
8428 SDNode *Use = *Inst->use_begin();
8429 if (Use->getOpcode() != ISD::BITCAST)
8431 assert(DAG && "Missing context");
8432 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
8433 EVT ResVT = Use->getValueType(0);
8434 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT());
8435 const TargetRegisterClass *ArgRC =
8436 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT());
8437 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
8440 // At this point, we know that we perform a cross-register-bank copy.
8441 // Check if it is expensive.
8442 const TargetRegisterInfo *TRI =
8443 TLI.getTargetMachine().getSubtargetImpl()->getRegisterInfo();
8444 // Assume bitcasts are cheap, unless both register classes do not
8445 // explicitly share a common sub class.
8446 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC))
8449 // Check if it will be merged with the load.
8450 // 1. Check the alignment constraint.
8451 unsigned RequiredAlignment = TLI.getDataLayout()->getABITypeAlignment(
8452 ResVT.getTypeForEVT(*DAG->getContext()));
8454 if (RequiredAlignment > getAlignment())
8457 // 2. Check that the load is a legal operation for that type.
8458 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
8461 // 3. Check that we do not have a zext in the way.
8462 if (Inst->getValueType(0) != getLoadedType())
8470 /// \brief Check that all bits set in \p UsedBits form a dense region, i.e.,
8471 /// \p UsedBits looks like 0..0 1..1 0..0.
8472 static bool areUsedBitsDense(const APInt &UsedBits) {
8473 // If all the bits are one, this is dense!
8474 if (UsedBits.isAllOnesValue())
8477 // Get rid of the unused bits on the right.
8478 APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countTrailingZeros());
8479 // Get rid of the unused bits on the left.
8480 if (NarrowedUsedBits.countLeadingZeros())
8481 NarrowedUsedBits = NarrowedUsedBits.trunc(NarrowedUsedBits.getActiveBits());
8482 // Check that the chunk of bits is completely used.
8483 return NarrowedUsedBits.isAllOnesValue();
8486 /// \brief Check whether or not \p First and \p Second are next to each other
8487 /// in memory. This means that there is no hole between the bits loaded
8488 /// by \p First and the bits loaded by \p Second.
8489 static bool areSlicesNextToEachOther(const LoadedSlice &First,
8490 const LoadedSlice &Second) {
8491 assert(First.Origin == Second.Origin && First.Origin &&
8492 "Unable to match different memory origins.");
8493 APInt UsedBits = First.getUsedBits();
8494 assert((UsedBits & Second.getUsedBits()) == 0 &&
8495 "Slices are not supposed to overlap.");
8496 UsedBits |= Second.getUsedBits();
8497 return areUsedBitsDense(UsedBits);
8500 /// \brief Adjust the \p GlobalLSCost according to the target
8501 /// paring capabilities and the layout of the slices.
8502 /// \pre \p GlobalLSCost should account for at least as many loads as
8503 /// there is in the slices in \p LoadedSlices.
8504 static void adjustCostForPairing(SmallVectorImpl<LoadedSlice> &LoadedSlices,
8505 LoadedSlice::Cost &GlobalLSCost) {
8506 unsigned NumberOfSlices = LoadedSlices.size();
8507 // If there is less than 2 elements, no pairing is possible.
8508 if (NumberOfSlices < 2)
8511 // Sort the slices so that elements that are likely to be next to each
8512 // other in memory are next to each other in the list.
8513 std::sort(LoadedSlices.begin(), LoadedSlices.end(),
8514 [](const LoadedSlice &LHS, const LoadedSlice &RHS) {
8515 assert(LHS.Origin == RHS.Origin && "Different bases not implemented.");
8516 return LHS.getOffsetFromBase() < RHS.getOffsetFromBase();
8518 const TargetLowering &TLI = LoadedSlices[0].DAG->getTargetLoweringInfo();
8519 // First (resp. Second) is the first (resp. Second) potentially candidate
8520 // to be placed in a paired load.
8521 const LoadedSlice *First = nullptr;
8522 const LoadedSlice *Second = nullptr;
8523 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice,
8524 // Set the beginning of the pair.
8527 Second = &LoadedSlices[CurrSlice];
8529 // If First is NULL, it means we start a new pair.
8530 // Get to the next slice.
8534 EVT LoadedType = First->getLoadedType();
8536 // If the types of the slices are different, we cannot pair them.
8537 if (LoadedType != Second->getLoadedType())
8540 // Check if the target supplies paired loads for this type.
8541 unsigned RequiredAlignment = 0;
8542 if (!TLI.hasPairedLoad(LoadedType, RequiredAlignment)) {
8543 // move to the next pair, this type is hopeless.
8547 // Check if we meet the alignment requirement.
8548 if (RequiredAlignment > First->getAlignment())
8551 // Check that both loads are next to each other in memory.
8552 if (!areSlicesNextToEachOther(*First, *Second))
8555 assert(GlobalLSCost.Loads > 0 && "We save more loads than we created!");
8556 --GlobalLSCost.Loads;
8557 // Move to the next pair.
8562 /// \brief Check the profitability of all involved LoadedSlice.
8563 /// Currently, it is considered profitable if there is exactly two
8564 /// involved slices (1) which are (2) next to each other in memory, and
8565 /// whose cost (\see LoadedSlice::Cost) is smaller than the original load (3).
8567 /// Note: The order of the elements in \p LoadedSlices may be modified, but not
8568 /// the elements themselves.
8570 /// FIXME: When the cost model will be mature enough, we can relax
8571 /// constraints (1) and (2).
8572 static bool isSlicingProfitable(SmallVectorImpl<LoadedSlice> &LoadedSlices,
8573 const APInt &UsedBits, bool ForCodeSize) {
8574 unsigned NumberOfSlices = LoadedSlices.size();
8575 if (StressLoadSlicing)
8576 return NumberOfSlices > 1;
8579 if (NumberOfSlices != 2)
8583 if (!areUsedBitsDense(UsedBits))
8587 LoadedSlice::Cost OrigCost(ForCodeSize), GlobalSlicingCost(ForCodeSize);
8588 // The original code has one big load.
8590 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice) {
8591 const LoadedSlice &LS = LoadedSlices[CurrSlice];
8592 // Accumulate the cost of all the slices.
8593 LoadedSlice::Cost SliceCost(LS, ForCodeSize);
8594 GlobalSlicingCost += SliceCost;
8596 // Account as cost in the original configuration the gain obtained
8597 // with the current slices.
8598 OrigCost.addSliceGain(LS);
8601 // If the target supports paired load, adjust the cost accordingly.
8602 adjustCostForPairing(LoadedSlices, GlobalSlicingCost);
8603 return OrigCost > GlobalSlicingCost;
8606 /// \brief If the given load, \p LI, is used only by trunc or trunc(lshr)
8607 /// operations, split it in the various pieces being extracted.
8609 /// This sort of thing is introduced by SROA.
8610 /// This slicing takes care not to insert overlapping loads.
8611 /// \pre LI is a simple load (i.e., not an atomic or volatile load).
8612 bool DAGCombiner::SliceUpLoad(SDNode *N) {
8613 if (Level < AfterLegalizeDAG)
8616 LoadSDNode *LD = cast<LoadSDNode>(N);
8617 if (LD->isVolatile() || !ISD::isNormalLoad(LD) ||
8618 !LD->getValueType(0).isInteger())
8621 // Keep track of already used bits to detect overlapping values.
8622 // In that case, we will just abort the transformation.
8623 APInt UsedBits(LD->getValueSizeInBits(0), 0);
8625 SmallVector<LoadedSlice, 4> LoadedSlices;
8627 // Check if this load is used as several smaller chunks of bits.
8628 // Basically, look for uses in trunc or trunc(lshr) and record a new chain
8629 // of computation for each trunc.
8630 for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end();
8631 UI != UIEnd; ++UI) {
8632 // Skip the uses of the chain.
8633 if (UI.getUse().getResNo() != 0)
8639 // Check if this is a trunc(lshr).
8640 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
8641 isa<ConstantSDNode>(User->getOperand(1))) {
8642 Shift = cast<ConstantSDNode>(User->getOperand(1))->getZExtValue();
8643 User = *User->use_begin();
8646 // At this point, User is a Truncate, iff we encountered, trunc or
8648 if (User->getOpcode() != ISD::TRUNCATE)
8651 // The width of the type must be a power of 2 and greater than 8-bits.
8652 // Otherwise the load cannot be represented in LLVM IR.
8653 // Moreover, if we shifted with a non-8-bits multiple, the slice
8654 // will be across several bytes. We do not support that.
8655 unsigned Width = User->getValueSizeInBits(0);
8656 if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7))
8659 // Build the slice for this chain of computations.
8660 LoadedSlice LS(User, LD, Shift, &DAG);
8661 APInt CurrentUsedBits = LS.getUsedBits();
8663 // Check if this slice overlaps with another.
8664 if ((CurrentUsedBits & UsedBits) != 0)
8666 // Update the bits used globally.
8667 UsedBits |= CurrentUsedBits;
8669 // Check if the new slice would be legal.
8673 // Record the slice.
8674 LoadedSlices.push_back(LS);
8677 // Abort slicing if it does not seem to be profitable.
8678 if (!isSlicingProfitable(LoadedSlices, UsedBits, ForCodeSize))
8683 // Rewrite each chain to use an independent load.
8684 // By construction, each chain can be represented by a unique load.
8686 // Prepare the argument for the new token factor for all the slices.
8687 SmallVector<SDValue, 8> ArgChains;
8688 for (SmallVectorImpl<LoadedSlice>::const_iterator
8689 LSIt = LoadedSlices.begin(),
8690 LSItEnd = LoadedSlices.end();
8691 LSIt != LSItEnd; ++LSIt) {
8692 SDValue SliceInst = LSIt->loadSlice();
8693 CombineTo(LSIt->Inst, SliceInst, true);
8694 if (SliceInst.getNode()->getOpcode() != ISD::LOAD)
8695 SliceInst = SliceInst.getOperand(0);
8696 assert(SliceInst->getOpcode() == ISD::LOAD &&
8697 "It takes more than a zext to get to the loaded slice!!");
8698 ArgChains.push_back(SliceInst.getValue(1));
8701 SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,
8703 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
8707 /// Check to see if V is (and load (ptr), imm), where the load is having
8708 /// specific bytes cleared out. If so, return the byte size being masked out
8709 /// and the shift amount.
8710 static std::pair<unsigned, unsigned>
8711 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
8712 std::pair<unsigned, unsigned> Result(0, 0);
8714 // Check for the structure we're looking for.
8715 if (V->getOpcode() != ISD::AND ||
8716 !isa<ConstantSDNode>(V->getOperand(1)) ||
8717 !ISD::isNormalLoad(V->getOperand(0).getNode()))
8720 // Check the chain and pointer.
8721 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
8722 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
8724 // The store should be chained directly to the load or be an operand of a
8726 if (LD == Chain.getNode())
8728 else if (Chain->getOpcode() != ISD::TokenFactor)
8729 return Result; // Fail.
8732 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
8733 if (Chain->getOperand(i).getNode() == LD) {
8737 if (!isOk) return Result;
8740 // This only handles simple types.
8741 if (V.getValueType() != MVT::i16 &&
8742 V.getValueType() != MVT::i32 &&
8743 V.getValueType() != MVT::i64)
8746 // Check the constant mask. Invert it so that the bits being masked out are
8747 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
8748 // follow the sign bit for uniformity.
8749 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
8750 unsigned NotMaskLZ = countLeadingZeros(NotMask);
8751 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
8752 unsigned NotMaskTZ = countTrailingZeros(NotMask);
8753 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
8754 if (NotMaskLZ == 64) return Result; // All zero mask.
8756 // See if we have a continuous run of bits. If so, we have 0*1+0*
8757 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
8760 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
8761 if (V.getValueType() != MVT::i64 && NotMaskLZ)
8762 NotMaskLZ -= 64-V.getValueSizeInBits();
8764 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
8765 switch (MaskedBytes) {
8769 default: return Result; // All one mask, or 5-byte mask.
8772 // Verify that the first bit starts at a multiple of mask so that the access
8773 // is aligned the same as the access width.
8774 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
8776 Result.first = MaskedBytes;
8777 Result.second = NotMaskTZ/8;
8782 /// Check to see if IVal is something that provides a value as specified by
8783 /// MaskInfo. If so, replace the specified store with a narrower store of
8786 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
8787 SDValue IVal, StoreSDNode *St,
8789 unsigned NumBytes = MaskInfo.first;
8790 unsigned ByteShift = MaskInfo.second;
8791 SelectionDAG &DAG = DC->getDAG();
8793 // Check to see if IVal is all zeros in the part being masked in by the 'or'
8794 // that uses this. If not, this is not a replacement.
8795 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
8796 ByteShift*8, (ByteShift+NumBytes)*8);
8797 if (!DAG.MaskedValueIsZero(IVal, Mask)) return nullptr;
8799 // Check that it is legal on the target to do this. It is legal if the new
8800 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
8802 MVT VT = MVT::getIntegerVT(NumBytes*8);
8803 if (!DC->isTypeLegal(VT))
8806 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
8807 // shifted by ByteShift and truncated down to NumBytes.
8809 IVal = DAG.getNode(ISD::SRL, SDLoc(IVal), IVal.getValueType(), IVal,
8810 DAG.getConstant(ByteShift*8,
8811 DC->getShiftAmountTy(IVal.getValueType())));
8813 // Figure out the offset for the store and the alignment of the access.
8815 unsigned NewAlign = St->getAlignment();
8817 if (DAG.getTargetLoweringInfo().isLittleEndian())
8818 StOffset = ByteShift;
8820 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
8822 SDValue Ptr = St->getBasePtr();
8824 Ptr = DAG.getNode(ISD::ADD, SDLoc(IVal), Ptr.getValueType(),
8825 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
8826 NewAlign = MinAlign(NewAlign, StOffset);
8829 // Truncate down to the new size.
8830 IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
8833 return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
8834 St->getPointerInfo().getWithOffset(StOffset),
8835 false, false, NewAlign).getNode();
8839 /// Look for sequence of load / op / store where op is one of 'or', 'xor', and
8840 /// 'and' of immediates. If 'op' is only touching some of the loaded bits, try
8841 /// narrowing the load and store if it would end up being a win for performance
8843 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
8844 StoreSDNode *ST = cast<StoreSDNode>(N);
8845 if (ST->isVolatile())
8848 SDValue Chain = ST->getChain();
8849 SDValue Value = ST->getValue();
8850 SDValue Ptr = ST->getBasePtr();
8851 EVT VT = Value.getValueType();
8853 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
8856 unsigned Opc = Value.getOpcode();
8858 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
8859 // is a byte mask indicating a consecutive number of bytes, check to see if
8860 // Y is known to provide just those bytes. If so, we try to replace the
8861 // load + replace + store sequence with a single (narrower) store, which makes
8863 if (Opc == ISD::OR) {
8864 std::pair<unsigned, unsigned> MaskedLoad;
8865 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
8866 if (MaskedLoad.first)
8867 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
8868 Value.getOperand(1), ST,this))
8869 return SDValue(NewST, 0);
8871 // Or is commutative, so try swapping X and Y.
8872 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
8873 if (MaskedLoad.first)
8874 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
8875 Value.getOperand(0), ST,this))
8876 return SDValue(NewST, 0);
8879 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
8880 Value.getOperand(1).getOpcode() != ISD::Constant)
8883 SDValue N0 = Value.getOperand(0);
8884 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
8885 Chain == SDValue(N0.getNode(), 1)) {
8886 LoadSDNode *LD = cast<LoadSDNode>(N0);
8887 if (LD->getBasePtr() != Ptr ||
8888 LD->getPointerInfo().getAddrSpace() !=
8889 ST->getPointerInfo().getAddrSpace())
8892 // Find the type to narrow it the load / op / store to.
8893 SDValue N1 = Value.getOperand(1);
8894 unsigned BitWidth = N1.getValueSizeInBits();
8895 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
8896 if (Opc == ISD::AND)
8897 Imm ^= APInt::getAllOnesValue(BitWidth);
8898 if (Imm == 0 || Imm.isAllOnesValue())
8900 unsigned ShAmt = Imm.countTrailingZeros();
8901 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
8902 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
8903 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
8904 while (NewBW < BitWidth &&
8905 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
8906 TLI.isNarrowingProfitable(VT, NewVT))) {
8907 NewBW = NextPowerOf2(NewBW);
8908 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
8910 if (NewBW >= BitWidth)
8913 // If the lsb changed does not start at the type bitwidth boundary,
8914 // start at the previous one.
8916 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
8917 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt,
8918 std::min(BitWidth, ShAmt + NewBW));
8919 if ((Imm & Mask) == Imm) {
8920 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
8921 if (Opc == ISD::AND)
8922 NewImm ^= APInt::getAllOnesValue(NewBW);
8923 uint64_t PtrOff = ShAmt / 8;
8924 // For big endian targets, we need to adjust the offset to the pointer to
8925 // load the correct bytes.
8926 if (TLI.isBigEndian())
8927 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
8929 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
8930 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
8931 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy))
8934 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD),
8935 Ptr.getValueType(), Ptr,
8936 DAG.getConstant(PtrOff, Ptr.getValueType()));
8937 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0),
8938 LD->getChain(), NewPtr,
8939 LD->getPointerInfo().getWithOffset(PtrOff),
8940 LD->isVolatile(), LD->isNonTemporal(),
8941 LD->isInvariant(), NewAlign,
8943 SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD,
8944 DAG.getConstant(NewImm, NewVT));
8945 SDValue NewST = DAG.getStore(Chain, SDLoc(N),
8947 ST->getPointerInfo().getWithOffset(PtrOff),
8948 false, false, NewAlign);
8950 AddToWorklist(NewPtr.getNode());
8951 AddToWorklist(NewLD.getNode());
8952 AddToWorklist(NewVal.getNode());
8953 WorklistRemover DeadNodes(*this);
8954 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
8963 /// For a given floating point load / store pair, if the load value isn't used
8964 /// by any other operations, then consider transforming the pair to integer
8965 /// load / store operations if the target deems the transformation profitable.
8966 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
8967 StoreSDNode *ST = cast<StoreSDNode>(N);
8968 SDValue Chain = ST->getChain();
8969 SDValue Value = ST->getValue();
8970 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
8971 Value.hasOneUse() &&
8972 Chain == SDValue(Value.getNode(), 1)) {
8973 LoadSDNode *LD = cast<LoadSDNode>(Value);
8974 EVT VT = LD->getMemoryVT();
8975 if (!VT.isFloatingPoint() ||
8976 VT != ST->getMemoryVT() ||
8977 LD->isNonTemporal() ||
8978 ST->isNonTemporal() ||
8979 LD->getPointerInfo().getAddrSpace() != 0 ||
8980 ST->getPointerInfo().getAddrSpace() != 0)
8983 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
8984 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
8985 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
8986 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
8987 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
8990 unsigned LDAlign = LD->getAlignment();
8991 unsigned STAlign = ST->getAlignment();
8992 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
8993 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy);
8994 if (LDAlign < ABIAlign || STAlign < ABIAlign)
8997 SDValue NewLD = DAG.getLoad(IntVT, SDLoc(Value),
8998 LD->getChain(), LD->getBasePtr(),
8999 LD->getPointerInfo(),
9000 false, false, false, LDAlign);
9002 SDValue NewST = DAG.getStore(NewLD.getValue(1), SDLoc(N),
9003 NewLD, ST->getBasePtr(),
9004 ST->getPointerInfo(),
9005 false, false, STAlign);
9007 AddToWorklist(NewLD.getNode());
9008 AddToWorklist(NewST.getNode());
9009 WorklistRemover DeadNodes(*this);
9010 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
9018 /// Helper struct to parse and store a memory address as base + index + offset.
9019 /// We ignore sign extensions when it is safe to do so.
9020 /// The following two expressions are not equivalent. To differentiate we need
9021 /// to store whether there was a sign extension involved in the index
9023 /// (load (i64 add (i64 copyfromreg %c)
9024 /// (i64 signextend (add (i8 load %index)
9028 /// (load (i64 add (i64 copyfromreg %c)
9029 /// (i64 signextend (i32 add (i32 signextend (i8 load %index))
9031 struct BaseIndexOffset {
9035 bool IsIndexSignExt;
9037 BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
9039 BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
9040 bool IsIndexSignExt) :
9041 Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {}
9043 bool equalBaseIndex(const BaseIndexOffset &Other) {
9044 return Other.Base == Base && Other.Index == Index &&
9045 Other.IsIndexSignExt == IsIndexSignExt;
9048 /// Parses tree in Ptr for base, index, offset addresses.
9049 static BaseIndexOffset match(SDValue Ptr) {
9050 bool IsIndexSignExt = false;
9052 // We only can pattern match BASE + INDEX + OFFSET. If Ptr is not an ADD
9053 // instruction, then it could be just the BASE or everything else we don't
9054 // know how to handle. Just use Ptr as BASE and give up.
9055 if (Ptr->getOpcode() != ISD::ADD)
9056 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9058 // We know that we have at least an ADD instruction. Try to pattern match
9059 // the simple case of BASE + OFFSET.
9060 if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
9061 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
9062 return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
9066 // Inside a loop the current BASE pointer is calculated using an ADD and a
9067 // MUL instruction. In this case Ptr is the actual BASE pointer.
9068 // (i64 add (i64 %array_ptr)
9069 // (i64 mul (i64 %induction_var)
9070 // (i64 %element_size)))
9071 if (Ptr->getOperand(1)->getOpcode() == ISD::MUL)
9072 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9074 // Look at Base + Index + Offset cases.
9075 SDValue Base = Ptr->getOperand(0);
9076 SDValue IndexOffset = Ptr->getOperand(1);
9078 // Skip signextends.
9079 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
9080 IndexOffset = IndexOffset->getOperand(0);
9081 IsIndexSignExt = true;
9084 // Either the case of Base + Index (no offset) or something else.
9085 if (IndexOffset->getOpcode() != ISD::ADD)
9086 return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt);
9088 // Now we have the case of Base + Index + offset.
9089 SDValue Index = IndexOffset->getOperand(0);
9090 SDValue Offset = IndexOffset->getOperand(1);
9092 if (!isa<ConstantSDNode>(Offset))
9093 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9095 // Ignore signextends.
9096 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
9097 Index = Index->getOperand(0);
9098 IsIndexSignExt = true;
9099 } else IsIndexSignExt = false;
9101 int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
9102 return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
9106 /// Holds a pointer to an LSBaseSDNode as well as information on where it
9107 /// is located in a sequence of memory operations connected by a chain.
9109 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
9110 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
9111 // Ptr to the mem node.
9112 LSBaseSDNode *MemNode;
9113 // Offset from the base ptr.
9114 int64_t OffsetFromBase;
9115 // What is the sequence number of this mem node.
9116 // Lowest mem operand in the DAG starts at zero.
9117 unsigned SequenceNum;
9120 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
9121 EVT MemVT = St->getMemoryVT();
9122 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;
9123 bool NoVectors = DAG.getMachineFunction().getFunction()->getAttributes().
9124 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
9126 // Don't merge vectors into wider inputs.
9127 if (MemVT.isVector() || !MemVT.isSimple())
9130 // Perform an early exit check. Do not bother looking at stored values that
9131 // are not constants or loads.
9132 SDValue StoredVal = St->getValue();
9133 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
9134 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) &&
9138 // Only look at ends of store sequences.
9139 SDValue Chain = SDValue(St, 0);
9140 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
9143 // This holds the base pointer, index, and the offset in bytes from the base
9145 BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr());
9147 // We must have a base and an offset.
9148 if (!BasePtr.Base.getNode())
9151 // Do not handle stores to undef base pointers.
9152 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
9155 // Save the LoadSDNodes that we find in the chain.
9156 // We need to make sure that these nodes do not interfere with
9157 // any of the store nodes.
9158 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
9160 // Save the StoreSDNodes that we find in the chain.
9161 SmallVector<MemOpLink, 8> StoreNodes;
9163 // Walk up the chain and look for nodes with offsets from the same
9164 // base pointer. Stop when reaching an instruction with a different kind
9165 // or instruction which has a different base pointer.
9167 StoreSDNode *Index = St;
9169 // If the chain has more than one use, then we can't reorder the mem ops.
9170 if (Index != St && !SDValue(Index, 0)->hasOneUse())
9173 // Find the base pointer and offset for this memory node.
9174 BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr());
9176 // Check that the base pointer is the same as the original one.
9177 if (!Ptr.equalBaseIndex(BasePtr))
9180 // Check that the alignment is the same.
9181 if (Index->getAlignment() != St->getAlignment())
9184 // The memory operands must not be volatile.
9185 if (Index->isVolatile() || Index->isIndexed())
9189 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
9190 if (St->isTruncatingStore())
9193 // The stored memory type must be the same.
9194 if (Index->getMemoryVT() != MemVT)
9197 // We do not allow unaligned stores because we want to prevent overriding
9199 if (Index->getAlignment()*8 != MemVT.getSizeInBits())
9202 // We found a potential memory operand to merge.
9203 StoreNodes.push_back(MemOpLink(Index, Ptr.Offset, Seq++));
9205 // Find the next memory operand in the chain. If the next operand in the
9206 // chain is a store then move up and continue the scan with the next
9207 // memory operand. If the next operand is a load save it and use alias
9208 // information to check if it interferes with anything.
9209 SDNode *NextInChain = Index->getChain().getNode();
9211 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
9212 // We found a store node. Use it for the next iteration.
9215 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
9216 if (Ldn->isVolatile()) {
9221 // Save the load node for later. Continue the scan.
9222 AliasLoadNodes.push_back(Ldn);
9223 NextInChain = Ldn->getChain().getNode();
9232 // Check if there is anything to merge.
9233 if (StoreNodes.size() < 2)
9236 // Sort the memory operands according to their distance from the base pointer.
9237 std::sort(StoreNodes.begin(), StoreNodes.end(),
9238 [](MemOpLink LHS, MemOpLink RHS) {
9239 return LHS.OffsetFromBase < RHS.OffsetFromBase ||
9240 (LHS.OffsetFromBase == RHS.OffsetFromBase &&
9241 LHS.SequenceNum > RHS.SequenceNum);
9244 // Scan the memory operations on the chain and find the first non-consecutive
9245 // store memory address.
9246 unsigned LastConsecutiveStore = 0;
9247 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
9248 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {
9250 // Check that the addresses are consecutive starting from the second
9251 // element in the list of stores.
9253 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
9254 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
9259 // Check if this store interferes with any of the loads that we found.
9260 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
9261 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
9265 // We found a load that alias with this store. Stop the sequence.
9269 // Mark this node as useful.
9270 LastConsecutiveStore = i;
9273 // The node with the lowest store address.
9274 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
9276 // Store the constants into memory as one consecutive store.
9278 unsigned LastLegalType = 0;
9279 unsigned LastLegalVectorType = 0;
9280 bool NonZero = false;
9281 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
9282 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9283 SDValue StoredVal = St->getValue();
9285 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
9286 NonZero |= !C->isNullValue();
9287 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
9288 NonZero |= !C->getConstantFPValue()->isNullValue();
9294 // Find a legal type for the constant store.
9295 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
9296 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9297 if (TLI.isTypeLegal(StoreTy))
9298 LastLegalType = i+1;
9299 // Or check whether a truncstore is legal.
9300 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
9301 TargetLowering::TypePromoteInteger) {
9302 EVT LegalizedStoredValueTy =
9303 TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType());
9304 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy))
9305 LastLegalType = i+1;
9308 // Find a legal type for the vector store.
9309 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
9310 if (TLI.isTypeLegal(Ty))
9311 LastLegalVectorType = i + 1;
9314 // We only use vectors if the constant is known to be zero and the
9315 // function is not marked with the noimplicitfloat attribute.
9316 if (NonZero || NoVectors)
9317 LastLegalVectorType = 0;
9319 // Check if we found a legal integer type to store.
9320 if (LastLegalType == 0 && LastLegalVectorType == 0)
9323 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors;
9324 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
9326 // Make sure we have something to merge.
9330 unsigned EarliestNodeUsed = 0;
9331 for (unsigned i=0; i < NumElem; ++i) {
9332 // Find a chain for the new wide-store operand. Notice that some
9333 // of the store nodes that we found may not be selected for inclusion
9334 // in the wide store. The chain we use needs to be the chain of the
9335 // earliest store node which is *used* and replaced by the wide store.
9336 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
9337 EarliestNodeUsed = i;
9340 // The earliest Node in the DAG.
9341 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
9342 SDLoc DL(StoreNodes[0].MemNode);
9346 // Find a legal type for the vector store.
9347 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
9348 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
9349 StoredVal = DAG.getConstant(0, Ty);
9351 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
9352 APInt StoreInt(StoreBW, 0);
9354 // Construct a single integer constant which is made of the smaller
9356 bool IsLE = TLI.isLittleEndian();
9357 for (unsigned i = 0; i < NumElem ; ++i) {
9358 unsigned Idx = IsLE ?(NumElem - 1 - i) : i;
9359 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
9360 SDValue Val = St->getValue();
9361 StoreInt<<=ElementSizeBytes*8;
9362 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
9363 StoreInt|=C->getAPIntValue().zext(StoreBW);
9364 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
9365 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
9367 assert(false && "Invalid constant element type");
9371 // Create the new Load and Store operations.
9372 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9373 StoredVal = DAG.getConstant(StoreInt, StoreTy);
9376 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal,
9377 FirstInChain->getBasePtr(),
9378 FirstInChain->getPointerInfo(),
9380 FirstInChain->getAlignment());
9382 // Replace the first store with the new store
9383 CombineTo(EarliestOp, NewStore);
9384 // Erase all other stores.
9385 for (unsigned i = 0; i < NumElem ; ++i) {
9386 if (StoreNodes[i].MemNode == EarliestOp)
9388 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9389 // ReplaceAllUsesWith will replace all uses that existed when it was
9390 // called, but graph optimizations may cause new ones to appear. For
9391 // example, the case in pr14333 looks like
9393 // St's chain -> St -> another store -> X
9395 // And the only difference from St to the other store is the chain.
9396 // When we change it's chain to be St's chain they become identical,
9397 // get CSEed and the net result is that X is now a use of St.
9398 // Since we know that St is redundant, just iterate.
9399 while (!St->use_empty())
9400 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
9401 deleteAndRecombine(St);
9407 // Below we handle the case of multiple consecutive stores that
9408 // come from multiple consecutive loads. We merge them into a single
9409 // wide load and a single wide store.
9411 // Look for load nodes which are used by the stored values.
9412 SmallVector<MemOpLink, 8> LoadNodes;
9414 // Find acceptable loads. Loads need to have the same chain (token factor),
9415 // must not be zext, volatile, indexed, and they must be consecutive.
9416 BaseIndexOffset LdBasePtr;
9417 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
9418 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9419 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
9422 // Loads must only have one use.
9423 if (!Ld->hasNUsesOfValue(1, 0))
9426 // Check that the alignment is the same as the stores.
9427 if (Ld->getAlignment() != St->getAlignment())
9430 // The memory operands must not be volatile.
9431 if (Ld->isVolatile() || Ld->isIndexed())
9434 // We do not accept ext loads.
9435 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
9438 // The stored memory type must be the same.
9439 if (Ld->getMemoryVT() != MemVT)
9442 BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld->getBasePtr());
9443 // If this is not the first ptr that we check.
9444 if (LdBasePtr.Base.getNode()) {
9445 // The base ptr must be the same.
9446 if (!LdPtr.equalBaseIndex(LdBasePtr))
9449 // Check that all other base pointers are the same as this one.
9453 // We found a potential memory operand to merge.
9454 LoadNodes.push_back(MemOpLink(Ld, LdPtr.Offset, 0));
9457 if (LoadNodes.size() < 2)
9460 // If we have load/store pair instructions and we only have two values,
9462 unsigned RequiredAlignment;
9463 if (LoadNodes.size() == 2 && TLI.hasPairedLoad(MemVT, RequiredAlignment) &&
9464 St->getAlignment() >= RequiredAlignment)
9467 // Scan the memory operations on the chain and find the first non-consecutive
9468 // load memory address. These variables hold the index in the store node
9470 unsigned LastConsecutiveLoad = 0;
9471 // This variable refers to the size and not index in the array.
9472 unsigned LastLegalVectorType = 0;
9473 unsigned LastLegalIntegerType = 0;
9474 StartAddress = LoadNodes[0].OffsetFromBase;
9475 SDValue FirstChain = LoadNodes[0].MemNode->getChain();
9476 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
9477 // All loads much share the same chain.
9478 if (LoadNodes[i].MemNode->getChain() != FirstChain)
9481 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
9482 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
9484 LastConsecutiveLoad = i;
9486 // Find a legal type for the vector store.
9487 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
9488 if (TLI.isTypeLegal(StoreTy))
9489 LastLegalVectorType = i + 1;
9491 // Find a legal type for the integer store.
9492 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
9493 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9494 if (TLI.isTypeLegal(StoreTy))
9495 LastLegalIntegerType = i + 1;
9496 // Or check whether a truncstore and extload is legal.
9497 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
9498 TargetLowering::TypePromoteInteger) {
9499 EVT LegalizedStoredValueTy =
9500 TLI.getTypeToTransformTo(*DAG.getContext(), StoreTy);
9501 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
9502 TLI.isLoadExtLegal(ISD::ZEXTLOAD, StoreTy) &&
9503 TLI.isLoadExtLegal(ISD::SEXTLOAD, StoreTy) &&
9504 TLI.isLoadExtLegal(ISD::EXTLOAD, StoreTy))
9505 LastLegalIntegerType = i+1;
9509 // Only use vector types if the vector type is larger than the integer type.
9510 // If they are the same, use integers.
9511 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors;
9512 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
9514 // We add +1 here because the LastXXX variables refer to location while
9515 // the NumElem refers to array/index size.
9516 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
9517 NumElem = std::min(LastLegalType, NumElem);
9522 // The earliest Node in the DAG.
9523 unsigned EarliestNodeUsed = 0;
9524 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
9525 for (unsigned i=1; i<NumElem; ++i) {
9526 // Find a chain for the new wide-store operand. Notice that some
9527 // of the store nodes that we found may not be selected for inclusion
9528 // in the wide store. The chain we use needs to be the chain of the
9529 // earliest store node which is *used* and replaced by the wide store.
9530 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
9531 EarliestNodeUsed = i;
9534 // Find if it is better to use vectors or integers to load and store
9538 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
9540 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
9541 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9544 SDLoc LoadDL(LoadNodes[0].MemNode);
9545 SDLoc StoreDL(StoreNodes[0].MemNode);
9547 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
9548 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL,
9549 FirstLoad->getChain(),
9550 FirstLoad->getBasePtr(),
9551 FirstLoad->getPointerInfo(),
9552 false, false, false,
9553 FirstLoad->getAlignment());
9555 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad,
9556 FirstInChain->getBasePtr(),
9557 FirstInChain->getPointerInfo(), false, false,
9558 FirstInChain->getAlignment());
9560 // Replace one of the loads with the new load.
9561 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
9562 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
9563 SDValue(NewLoad.getNode(), 1));
9565 // Remove the rest of the load chains.
9566 for (unsigned i = 1; i < NumElem ; ++i) {
9567 // Replace all chain users of the old load nodes with the chain of the new
9569 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
9570 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
9573 // Replace the first store with the new store.
9574 CombineTo(EarliestOp, NewStore);
9575 // Erase all other stores.
9576 for (unsigned i = 0; i < NumElem ; ++i) {
9577 // Remove all Store nodes.
9578 if (StoreNodes[i].MemNode == EarliestOp)
9580 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9581 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
9582 deleteAndRecombine(St);
9588 SDValue DAGCombiner::visitSTORE(SDNode *N) {
9589 StoreSDNode *ST = cast<StoreSDNode>(N);
9590 SDValue Chain = ST->getChain();
9591 SDValue Value = ST->getValue();
9592 SDValue Ptr = ST->getBasePtr();
9594 // If this is a store of a bit convert, store the input value if the
9595 // resultant store does not need a higher alignment than the original.
9596 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
9597 ST->isUnindexed()) {
9598 unsigned OrigAlign = ST->getAlignment();
9599 EVT SVT = Value.getOperand(0).getValueType();
9600 unsigned Align = TLI.getDataLayout()->
9601 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
9602 if (Align <= OrigAlign &&
9603 ((!LegalOperations && !ST->isVolatile()) ||
9604 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
9605 return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0),
9606 Ptr, ST->getPointerInfo(), ST->isVolatile(),
9607 ST->isNonTemporal(), OrigAlign,
9611 // Turn 'store undef, Ptr' -> nothing.
9612 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
9615 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
9616 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
9617 // NOTE: If the original store is volatile, this transform must not increase
9618 // the number of stores. For example, on x86-32 an f64 can be stored in one
9619 // processor operation but an i64 (which is not legal) requires two. So the
9620 // transform should not be done in this case.
9621 if (Value.getOpcode() != ISD::TargetConstantFP) {
9623 switch (CFP->getSimpleValueType(0).SimpleTy) {
9624 default: llvm_unreachable("Unknown FP type");
9625 case MVT::f16: // We don't do this for these yet.
9631 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
9632 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
9633 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
9634 bitcastToAPInt().getZExtValue(), MVT::i32);
9635 return DAG.getStore(Chain, SDLoc(N), Tmp,
9636 Ptr, ST->getMemOperand());
9640 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
9641 !ST->isVolatile()) ||
9642 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
9643 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
9644 getZExtValue(), MVT::i64);
9645 return DAG.getStore(Chain, SDLoc(N), Tmp,
9646 Ptr, ST->getMemOperand());
9649 if (!ST->isVolatile() &&
9650 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
9651 // Many FP stores are not made apparent until after legalize, e.g. for
9652 // argument passing. Since this is so common, custom legalize the
9653 // 64-bit integer store into two 32-bit stores.
9654 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
9655 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
9656 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
9657 if (TLI.isBigEndian()) std::swap(Lo, Hi);
9659 unsigned Alignment = ST->getAlignment();
9660 bool isVolatile = ST->isVolatile();
9661 bool isNonTemporal = ST->isNonTemporal();
9662 AAMDNodes AAInfo = ST->getAAInfo();
9664 SDValue St0 = DAG.getStore(Chain, SDLoc(ST), Lo,
9665 Ptr, ST->getPointerInfo(),
9666 isVolatile, isNonTemporal,
9667 ST->getAlignment(), AAInfo);
9668 Ptr = DAG.getNode(ISD::ADD, SDLoc(N), Ptr.getValueType(), Ptr,
9669 DAG.getConstant(4, Ptr.getValueType()));
9670 Alignment = MinAlign(Alignment, 4U);
9671 SDValue St1 = DAG.getStore(Chain, SDLoc(ST), Hi,
9672 Ptr, ST->getPointerInfo().getWithOffset(4),
9673 isVolatile, isNonTemporal,
9675 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other,
9684 // Try to infer better alignment information than the store already has.
9685 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
9686 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
9687 if (Align > ST->getAlignment())
9688 return DAG.getTruncStore(Chain, SDLoc(N), Value,
9689 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
9690 ST->isVolatile(), ST->isNonTemporal(), Align,
9695 // Try transforming a pair floating point load / store ops to integer
9696 // load / store ops.
9697 SDValue NewST = TransformFPLoadStorePair(N);
9698 if (NewST.getNode())
9701 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA :
9702 TLI.getTargetMachine().getSubtarget<TargetSubtargetInfo>().useAA();
9704 if (CombinerAAOnlyFunc.getNumOccurrences() &&
9705 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
9708 if (UseAA && ST->isUnindexed()) {
9709 // Walk up chain skipping non-aliasing memory nodes.
9710 SDValue BetterChain = FindBetterChain(N, Chain);
9712 // If there is a better chain.
9713 if (Chain != BetterChain) {
9716 // Replace the chain to avoid dependency.
9717 if (ST->isTruncatingStore()) {
9718 ReplStore = DAG.getTruncStore(BetterChain, SDLoc(N), Value, Ptr,
9719 ST->getMemoryVT(), ST->getMemOperand());
9721 ReplStore = DAG.getStore(BetterChain, SDLoc(N), Value, Ptr,
9722 ST->getMemOperand());
9725 // Create token to keep both nodes around.
9726 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
9727 MVT::Other, Chain, ReplStore);
9729 // Make sure the new and old chains are cleaned up.
9730 AddToWorklist(Token.getNode());
9732 // Don't add users to work list.
9733 return CombineTo(N, Token, false);
9737 // Try transforming N to an indexed store.
9738 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
9739 return SDValue(N, 0);
9741 // FIXME: is there such a thing as a truncating indexed store?
9742 if (ST->isTruncatingStore() && ST->isUnindexed() &&
9743 Value.getValueType().isInteger()) {
9744 // See if we can simplify the input to this truncstore with knowledge that
9745 // only the low bits are being used. For example:
9746 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
9748 GetDemandedBits(Value,
9749 APInt::getLowBitsSet(
9750 Value.getValueType().getScalarType().getSizeInBits(),
9751 ST->getMemoryVT().getScalarType().getSizeInBits()));
9752 AddToWorklist(Value.getNode());
9753 if (Shorter.getNode())
9754 return DAG.getTruncStore(Chain, SDLoc(N), Shorter,
9755 Ptr, ST->getMemoryVT(), ST->getMemOperand());
9757 // Otherwise, see if we can simplify the operation with
9758 // SimplifyDemandedBits, which only works if the value has a single use.
9759 if (SimplifyDemandedBits(Value,
9760 APInt::getLowBitsSet(
9761 Value.getValueType().getScalarType().getSizeInBits(),
9762 ST->getMemoryVT().getScalarType().getSizeInBits())))
9763 return SDValue(N, 0);
9766 // If this is a load followed by a store to the same location, then the store
9768 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
9769 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
9770 ST->isUnindexed() && !ST->isVolatile() &&
9771 // There can't be any side effects between the load and store, such as
9773 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
9774 // The store is dead, remove it.
9779 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
9780 // truncating store. We can do this even if this is already a truncstore.
9781 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
9782 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
9783 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
9784 ST->getMemoryVT())) {
9785 return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0),
9786 Ptr, ST->getMemoryVT(), ST->getMemOperand());
9789 // Only perform this optimization before the types are legal, because we
9790 // don't want to perform this optimization on every DAGCombine invocation.
9792 bool EverChanged = false;
9795 // There can be multiple store sequences on the same chain.
9796 // Keep trying to merge store sequences until we are unable to do so
9797 // or until we merge the last store on the chain.
9798 bool Changed = MergeConsecutiveStores(ST);
9799 EverChanged |= Changed;
9800 if (!Changed) break;
9801 } while (ST->getOpcode() != ISD::DELETED_NODE);
9804 return SDValue(N, 0);
9807 return ReduceLoadOpStoreWidth(N);
9810 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
9811 SDValue InVec = N->getOperand(0);
9812 SDValue InVal = N->getOperand(1);
9813 SDValue EltNo = N->getOperand(2);
9816 // If the inserted element is an UNDEF, just use the input vector.
9817 if (InVal.getOpcode() == ISD::UNDEF)
9820 EVT VT = InVec.getValueType();
9822 // If we can't generate a legal BUILD_VECTOR, exit
9823 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
9826 // Check that we know which element is being inserted
9827 if (!isa<ConstantSDNode>(EltNo))
9829 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
9831 // Canonicalize insert_vector_elt dag nodes.
9833 // (insert_vector_elt (insert_vector_elt A, Idx0), Idx1)
9834 // -> (insert_vector_elt (insert_vector_elt A, Idx1), Idx0)
9836 // Do this only if the child insert_vector node has one use; also
9837 // do this only if indices are both constants and Idx1 < Idx0.
9838 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
9839 && isa<ConstantSDNode>(InVec.getOperand(2))) {
9841 cast<ConstantSDNode>(InVec.getOperand(2))->getZExtValue();
9842 if (Elt < OtherElt) {
9844 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VT,
9845 InVec.getOperand(0), InVal, EltNo);
9846 AddToWorklist(NewOp.getNode());
9847 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()),
9848 VT, NewOp, InVec.getOperand(1), InVec.getOperand(2));
9852 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
9853 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
9855 SmallVector<SDValue, 8> Ops;
9856 // Do not combine these two vectors if the output vector will not replace
9857 // the input vector.
9858 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) {
9859 Ops.append(InVec.getNode()->op_begin(),
9860 InVec.getNode()->op_end());
9861 } else if (InVec.getOpcode() == ISD::UNDEF) {
9862 unsigned NElts = VT.getVectorNumElements();
9863 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
9868 // Insert the element
9869 if (Elt < Ops.size()) {
9870 // All the operands of BUILD_VECTOR must have the same type;
9871 // we enforce that here.
9872 EVT OpVT = Ops[0].getValueType();
9873 if (InVal.getValueType() != OpVT)
9874 InVal = OpVT.bitsGT(InVal.getValueType()) ?
9875 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
9876 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
9880 // Return the new vector
9881 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
9884 SDValue DAGCombiner::ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
9885 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad) {
9886 EVT ResultVT = EVE->getValueType(0);
9887 EVT VecEltVT = InVecVT.getVectorElementType();
9888 unsigned Align = OriginalLoad->getAlignment();
9889 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
9890 VecEltVT.getTypeForEVT(*DAG.getContext()));
9892 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT))
9897 SDValue NewPtr = OriginalLoad->getBasePtr();
9899 EVT PtrType = NewPtr.getValueType();
9900 MachinePointerInfo MPI;
9901 if (auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo)) {
9902 int Elt = ConstEltNo->getZExtValue();
9903 unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / 8;
9904 if (TLI.isBigEndian())
9905 PtrOff = InVecVT.getSizeInBits() / 8 - PtrOff;
9906 Offset = DAG.getConstant(PtrOff, PtrType);
9907 MPI = OriginalLoad->getPointerInfo().getWithOffset(PtrOff);
9909 Offset = DAG.getNode(
9910 ISD::MUL, SDLoc(EVE), EltNo.getValueType(), EltNo,
9911 DAG.getConstant(VecEltVT.getStoreSize(), EltNo.getValueType()));
9912 if (TLI.isBigEndian())
9913 Offset = DAG.getNode(
9914 ISD::SUB, SDLoc(EVE), EltNo.getValueType(),
9915 DAG.getConstant(InVecVT.getStoreSize(), EltNo.getValueType()), Offset);
9916 MPI = OriginalLoad->getPointerInfo();
9918 NewPtr = DAG.getNode(ISD::ADD, SDLoc(EVE), PtrType, NewPtr, Offset);
9920 // The replacement we need to do here is a little tricky: we need to
9921 // replace an extractelement of a load with a load.
9922 // Use ReplaceAllUsesOfValuesWith to do the replacement.
9923 // Note that this replacement assumes that the extractvalue is the only
9924 // use of the load; that's okay because we don't want to perform this
9925 // transformation in other cases anyway.
9928 if (ResultVT.bitsGT(VecEltVT)) {
9929 // If the result type of vextract is wider than the load, then issue an
9930 // extending load instead.
9931 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, VecEltVT)
9934 Load = DAG.getExtLoad(
9935 ExtType, SDLoc(EVE), ResultVT, OriginalLoad->getChain(), NewPtr, MPI,
9936 VecEltVT, OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
9937 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
9938 Chain = Load.getValue(1);
9941 VecEltVT, SDLoc(EVE), OriginalLoad->getChain(), NewPtr, MPI,
9942 OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
9943 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
9944 Chain = Load.getValue(1);
9945 if (ResultVT.bitsLT(VecEltVT))
9946 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(EVE), ResultVT, Load);
9948 Load = DAG.getNode(ISD::BITCAST, SDLoc(EVE), ResultVT, Load);
9950 WorklistRemover DeadNodes(*this);
9951 SDValue From[] = { SDValue(EVE, 0), SDValue(OriginalLoad, 1) };
9952 SDValue To[] = { Load, Chain };
9953 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
9954 // Since we're explicitly calling ReplaceAllUses, add the new node to the
9955 // worklist explicitly as well.
9956 AddToWorklist(Load.getNode());
9957 AddUsersToWorklist(Load.getNode()); // Add users too
9958 // Make sure to revisit this node to clean it up; it will usually be dead.
9961 return SDValue(EVE, 0);
9964 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
9965 // (vextract (scalar_to_vector val, 0) -> val
9966 SDValue InVec = N->getOperand(0);
9967 EVT VT = InVec.getValueType();
9968 EVT NVT = N->getValueType(0);
9970 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
9971 // Check if the result type doesn't match the inserted element type. A
9972 // SCALAR_TO_VECTOR may truncate the inserted element and the
9973 // EXTRACT_VECTOR_ELT may widen the extracted vector.
9974 SDValue InOp = InVec.getOperand(0);
9975 if (InOp.getValueType() != NVT) {
9976 assert(InOp.getValueType().isInteger() && NVT.isInteger());
9977 return DAG.getSExtOrTrunc(InOp, SDLoc(InVec), NVT);
9982 SDValue EltNo = N->getOperand(1);
9983 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
9985 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
9986 // We only perform this optimization before the op legalization phase because
9987 // we may introduce new vector instructions which are not backed by TD
9988 // patterns. For example on AVX, extracting elements from a wide vector
9989 // without using extract_subvector. However, if we can find an underlying
9990 // scalar value, then we can always use that.
9991 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
9993 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
9994 int NumElem = VT.getVectorNumElements();
9995 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
9996 // Find the new index to extract from.
9997 int OrigElt = SVOp->getMaskElt(Elt);
9999 // Extracting an undef index is undef.
10001 return DAG.getUNDEF(NVT);
10003 // Select the right vector half to extract from.
10005 if (OrigElt < NumElem) {
10006 SVInVec = InVec->getOperand(0);
10008 SVInVec = InVec->getOperand(1);
10009 OrigElt -= NumElem;
10012 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
10013 SDValue InOp = SVInVec.getOperand(OrigElt);
10014 if (InOp.getValueType() != NVT) {
10015 assert(InOp.getValueType().isInteger() && NVT.isInteger());
10016 InOp = DAG.getSExtOrTrunc(InOp, SDLoc(SVInVec), NVT);
10022 // FIXME: We should handle recursing on other vector shuffles and
10023 // scalar_to_vector here as well.
10025 if (!LegalOperations) {
10026 EVT IndexTy = TLI.getVectorIdxTy();
10027 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT,
10028 SVInVec, DAG.getConstant(OrigElt, IndexTy));
10032 bool BCNumEltsChanged = false;
10033 EVT ExtVT = VT.getVectorElementType();
10036 // If the result of load has to be truncated, then it's not necessarily
10038 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
10041 if (InVec.getOpcode() == ISD::BITCAST) {
10042 // Don't duplicate a load with other uses.
10043 if (!InVec.hasOneUse())
10046 EVT BCVT = InVec.getOperand(0).getValueType();
10047 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
10049 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
10050 BCNumEltsChanged = true;
10051 InVec = InVec.getOperand(0);
10052 ExtVT = BCVT.getVectorElementType();
10055 // (vextract (vN[if]M load $addr), i) -> ([if]M load $addr + i * size)
10056 if (!LegalOperations && !ConstEltNo && InVec.hasOneUse() &&
10057 ISD::isNormalLoad(InVec.getNode()) &&
10058 !N->getOperand(1)->hasPredecessor(InVec.getNode())) {
10059 SDValue Index = N->getOperand(1);
10060 if (LoadSDNode *OrigLoad = dyn_cast<LoadSDNode>(InVec))
10061 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, Index,
10065 // Perform only after legalization to ensure build_vector / vector_shuffle
10066 // optimizations have already been done.
10067 if (!LegalOperations) return SDValue();
10069 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
10070 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
10071 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
10074 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
10076 LoadSDNode *LN0 = nullptr;
10077 const ShuffleVectorSDNode *SVN = nullptr;
10078 if (ISD::isNormalLoad(InVec.getNode())) {
10079 LN0 = cast<LoadSDNode>(InVec);
10080 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10081 InVec.getOperand(0).getValueType() == ExtVT &&
10082 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
10083 // Don't duplicate a load with other uses.
10084 if (!InVec.hasOneUse())
10087 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
10088 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
10089 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
10091 // (load $addr+1*size)
10093 // Don't duplicate a load with other uses.
10094 if (!InVec.hasOneUse())
10097 // If the bit convert changed the number of elements, it is unsafe
10098 // to examine the mask.
10099 if (BCNumEltsChanged)
10102 // Select the input vector, guarding against out of range extract vector.
10103 unsigned NumElems = VT.getVectorNumElements();
10104 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
10105 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
10107 if (InVec.getOpcode() == ISD::BITCAST) {
10108 // Don't duplicate a load with other uses.
10109 if (!InVec.hasOneUse())
10112 InVec = InVec.getOperand(0);
10114 if (ISD::isNormalLoad(InVec.getNode())) {
10115 LN0 = cast<LoadSDNode>(InVec);
10116 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
10117 EltNo = DAG.getConstant(Elt, EltNo.getValueType());
10121 // Make sure we found a non-volatile load and the extractelement is
10123 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
10126 // If Idx was -1 above, Elt is going to be -1, so just return undef.
10128 return DAG.getUNDEF(LVT);
10130 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, EltNo, LN0);
10136 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
10137 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
10138 // We perform this optimization post type-legalization because
10139 // the type-legalizer often scalarizes integer-promoted vectors.
10140 // Performing this optimization before may create bit-casts which
10141 // will be type-legalized to complex code sequences.
10142 // We perform this optimization only before the operation legalizer because we
10143 // may introduce illegal operations.
10144 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
10147 unsigned NumInScalars = N->getNumOperands();
10149 EVT VT = N->getValueType(0);
10151 // Check to see if this is a BUILD_VECTOR of a bunch of values
10152 // which come from any_extend or zero_extend nodes. If so, we can create
10153 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
10154 // optimizations. We do not handle sign-extend because we can't fill the sign
10156 EVT SourceType = MVT::Other;
10157 bool AllAnyExt = true;
10159 for (unsigned i = 0; i != NumInScalars; ++i) {
10160 SDValue In = N->getOperand(i);
10161 // Ignore undef inputs.
10162 if (In.getOpcode() == ISD::UNDEF) continue;
10164 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
10165 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
10167 // Abort if the element is not an extension.
10168 if (!ZeroExt && !AnyExt) {
10169 SourceType = MVT::Other;
10173 // The input is a ZeroExt or AnyExt. Check the original type.
10174 EVT InTy = In.getOperand(0).getValueType();
10176 // Check that all of the widened source types are the same.
10177 if (SourceType == MVT::Other)
10180 else if (InTy != SourceType) {
10181 // Multiple income types. Abort.
10182 SourceType = MVT::Other;
10186 // Check if all of the extends are ANY_EXTENDs.
10187 AllAnyExt &= AnyExt;
10190 // In order to have valid types, all of the inputs must be extended from the
10191 // same source type and all of the inputs must be any or zero extend.
10192 // Scalar sizes must be a power of two.
10193 EVT OutScalarTy = VT.getScalarType();
10194 bool ValidTypes = SourceType != MVT::Other &&
10195 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
10196 isPowerOf2_32(SourceType.getSizeInBits());
10198 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
10199 // turn into a single shuffle instruction.
10203 bool isLE = TLI.isLittleEndian();
10204 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
10205 assert(ElemRatio > 1 && "Invalid element size ratio");
10206 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
10207 DAG.getConstant(0, SourceType);
10209 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
10210 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
10212 // Populate the new build_vector
10213 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
10214 SDValue Cast = N->getOperand(i);
10215 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
10216 Cast.getOpcode() == ISD::ZERO_EXTEND ||
10217 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
10219 if (Cast.getOpcode() == ISD::UNDEF)
10220 In = DAG.getUNDEF(SourceType);
10222 In = Cast->getOperand(0);
10223 unsigned Index = isLE ? (i * ElemRatio) :
10224 (i * ElemRatio + (ElemRatio - 1));
10226 assert(Index < Ops.size() && "Invalid index");
10230 // The type of the new BUILD_VECTOR node.
10231 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
10232 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
10233 "Invalid vector size");
10234 // Check if the new vector type is legal.
10235 if (!isTypeLegal(VecVT)) return SDValue();
10237 // Make the new BUILD_VECTOR.
10238 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
10240 // The new BUILD_VECTOR node has the potential to be further optimized.
10241 AddToWorklist(BV.getNode());
10242 // Bitcast to the desired type.
10243 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
10246 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
10247 EVT VT = N->getValueType(0);
10249 unsigned NumInScalars = N->getNumOperands();
10252 EVT SrcVT = MVT::Other;
10253 unsigned Opcode = ISD::DELETED_NODE;
10254 unsigned NumDefs = 0;
10256 for (unsigned i = 0; i != NumInScalars; ++i) {
10257 SDValue In = N->getOperand(i);
10258 unsigned Opc = In.getOpcode();
10260 if (Opc == ISD::UNDEF)
10263 // If all scalar values are floats and converted from integers.
10264 if (Opcode == ISD::DELETED_NODE &&
10265 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
10272 EVT InVT = In.getOperand(0).getValueType();
10274 // If all scalar values are typed differently, bail out. It's chosen to
10275 // simplify BUILD_VECTOR of integer types.
10276 if (SrcVT == MVT::Other)
10283 // If the vector has just one element defined, it's not worth to fold it into
10284 // a vectorized one.
10288 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
10289 && "Should only handle conversion from integer to float.");
10290 assert(SrcVT != MVT::Other && "Cannot determine source type!");
10292 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
10294 if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
10297 SmallVector<SDValue, 8> Opnds;
10298 for (unsigned i = 0; i != NumInScalars; ++i) {
10299 SDValue In = N->getOperand(i);
10301 if (In.getOpcode() == ISD::UNDEF)
10302 Opnds.push_back(DAG.getUNDEF(SrcVT));
10304 Opnds.push_back(In.getOperand(0));
10306 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Opnds);
10307 AddToWorklist(BV.getNode());
10309 return DAG.getNode(Opcode, dl, VT, BV);
10312 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
10313 unsigned NumInScalars = N->getNumOperands();
10315 EVT VT = N->getValueType(0);
10317 // A vector built entirely of undefs is undef.
10318 if (ISD::allOperandsUndef(N))
10319 return DAG.getUNDEF(VT);
10321 SDValue V = reduceBuildVecExtToExtBuildVec(N);
10325 V = reduceBuildVecConvertToConvertBuildVec(N);
10329 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
10330 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
10331 // at most two distinct vectors, turn this into a shuffle node.
10333 // May only combine to shuffle after legalize if shuffle is legal.
10334 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT))
10337 SDValue VecIn1, VecIn2;
10338 for (unsigned i = 0; i != NumInScalars; ++i) {
10339 // Ignore undef inputs.
10340 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
10342 // If this input is something other than a EXTRACT_VECTOR_ELT with a
10343 // constant index, bail out.
10344 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
10345 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
10346 VecIn1 = VecIn2 = SDValue(nullptr, 0);
10350 // We allow up to two distinct input vectors.
10351 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
10352 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
10355 if (!VecIn1.getNode()) {
10356 VecIn1 = ExtractedFromVec;
10357 } else if (!VecIn2.getNode()) {
10358 VecIn2 = ExtractedFromVec;
10360 // Too many inputs.
10361 VecIn1 = VecIn2 = SDValue(nullptr, 0);
10366 // If everything is good, we can make a shuffle operation.
10367 if (VecIn1.getNode()) {
10368 SmallVector<int, 8> Mask;
10369 for (unsigned i = 0; i != NumInScalars; ++i) {
10370 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
10371 Mask.push_back(-1);
10375 // If extracting from the first vector, just use the index directly.
10376 SDValue Extract = N->getOperand(i);
10377 SDValue ExtVal = Extract.getOperand(1);
10378 if (Extract.getOperand(0) == VecIn1) {
10379 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
10380 if (ExtIndex > VT.getVectorNumElements())
10383 Mask.push_back(ExtIndex);
10387 // Otherwise, use InIdx + VecSize
10388 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
10389 Mask.push_back(Idx+NumInScalars);
10392 // We can't generate a shuffle node with mismatched input and output types.
10393 // Attempt to transform a single input vector to the correct type.
10394 if ((VT != VecIn1.getValueType())) {
10395 // We don't support shuffeling between TWO values of different types.
10396 if (VecIn2.getNode())
10399 // We only support widening of vectors which are half the size of the
10400 // output registers. For example XMM->YMM widening on X86 with AVX.
10401 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
10404 // If the input vector type has a different base type to the output
10405 // vector type, bail out.
10406 if (VecIn1.getValueType().getVectorElementType() !=
10407 VT.getVectorElementType())
10410 // Widen the input vector by adding undef values.
10411 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10412 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
10415 // If VecIn2 is unused then change it to undef.
10416 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
10418 // Check that we were able to transform all incoming values to the same
10420 if (VecIn2.getValueType() != VecIn1.getValueType() ||
10421 VecIn1.getValueType() != VT)
10424 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
10425 if (!isTypeLegal(VT))
10428 // Return the new VECTOR_SHUFFLE node.
10432 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
10438 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
10439 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
10440 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
10441 // inputs come from at most two distinct vectors, turn this into a shuffle
10444 // If we only have one input vector, we don't need to do any concatenation.
10445 if (N->getNumOperands() == 1)
10446 return N->getOperand(0);
10448 // Check if all of the operands are undefs.
10449 EVT VT = N->getValueType(0);
10450 if (ISD::allOperandsUndef(N))
10451 return DAG.getUNDEF(VT);
10453 // Optimize concat_vectors where one of the vectors is undef.
10454 if (N->getNumOperands() == 2 &&
10455 N->getOperand(1)->getOpcode() == ISD::UNDEF) {
10456 SDValue In = N->getOperand(0);
10457 assert(In.getValueType().isVector() && "Must concat vectors");
10459 // Transform: concat_vectors(scalar, undef) -> scalar_to_vector(sclr).
10460 if (In->getOpcode() == ISD::BITCAST &&
10461 !In->getOperand(0)->getValueType(0).isVector()) {
10462 SDValue Scalar = In->getOperand(0);
10463 EVT SclTy = Scalar->getValueType(0);
10465 if (!SclTy.isFloatingPoint() && !SclTy.isInteger())
10468 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy,
10469 VT.getSizeInBits() / SclTy.getSizeInBits());
10470 if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType()))
10473 SDLoc dl = SDLoc(N);
10474 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar);
10475 return DAG.getNode(ISD::BITCAST, dl, VT, Res);
10479 // fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
10480 // -> (BUILD_VECTOR A, B, ..., C, D, ...)
10481 if (N->getNumOperands() == 2 &&
10482 N->getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
10483 N->getOperand(1).getOpcode() == ISD::BUILD_VECTOR) {
10484 EVT VT = N->getValueType(0);
10485 SDValue N0 = N->getOperand(0);
10486 SDValue N1 = N->getOperand(1);
10487 SmallVector<SDValue, 8> Opnds;
10488 unsigned BuildVecNumElts = N0.getNumOperands();
10490 EVT SclTy0 = N0.getOperand(0)->getValueType(0);
10491 EVT SclTy1 = N1.getOperand(0)->getValueType(0);
10492 if (SclTy0.isFloatingPoint()) {
10493 for (unsigned i = 0; i != BuildVecNumElts; ++i)
10494 Opnds.push_back(N0.getOperand(i));
10495 for (unsigned i = 0; i != BuildVecNumElts; ++i)
10496 Opnds.push_back(N1.getOperand(i));
10498 // If BUILD_VECTOR are from built from integer, they may have different
10499 // operand types. Get the smaller type and truncate all operands to it.
10500 EVT MinTy = SclTy0.bitsLE(SclTy1) ? SclTy0 : SclTy1;
10501 for (unsigned i = 0; i != BuildVecNumElts; ++i)
10502 Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
10503 N0.getOperand(i)));
10504 for (unsigned i = 0; i != BuildVecNumElts; ++i)
10505 Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
10506 N1.getOperand(i)));
10509 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
10512 // Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
10513 // nodes often generate nop CONCAT_VECTOR nodes.
10514 // Scan the CONCAT_VECTOR operands and look for a CONCAT operations that
10515 // place the incoming vectors at the exact same location.
10516 SDValue SingleSource = SDValue();
10517 unsigned PartNumElem = N->getOperand(0).getValueType().getVectorNumElements();
10519 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
10520 SDValue Op = N->getOperand(i);
10522 if (Op.getOpcode() == ISD::UNDEF)
10525 // Check if this is the identity extract:
10526 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
10529 // Find the single incoming vector for the extract_subvector.
10530 if (SingleSource.getNode()) {
10531 if (Op.getOperand(0) != SingleSource)
10534 SingleSource = Op.getOperand(0);
10536 // Check the source type is the same as the type of the result.
10537 // If not, this concat may extend the vector, so we can not
10538 // optimize it away.
10539 if (SingleSource.getValueType() != N->getValueType(0))
10543 unsigned IdentityIndex = i * PartNumElem;
10544 ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10545 // The extract index must be constant.
10549 // Check that we are reading from the identity index.
10550 if (CS->getZExtValue() != IdentityIndex)
10554 if (SingleSource.getNode())
10555 return SingleSource;
10560 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
10561 EVT NVT = N->getValueType(0);
10562 SDValue V = N->getOperand(0);
10564 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
10566 // (extract_subvec (concat V1, V2, ...), i)
10569 // Only operand 0 is checked as 'concat' assumes all inputs of the same
10571 if (V->getOperand(0).getValueType() != NVT)
10573 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
10574 unsigned NumElems = NVT.getVectorNumElements();
10575 assert((Idx % NumElems) == 0 &&
10576 "IDX in concat is not a multiple of the result vector length.");
10577 return V->getOperand(Idx / NumElems);
10581 if (V->getOpcode() == ISD::BITCAST)
10582 V = V.getOperand(0);
10584 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
10586 // Handle only simple case where vector being inserted and vector
10587 // being extracted are of same type, and are half size of larger vectors.
10588 EVT BigVT = V->getOperand(0).getValueType();
10589 EVT SmallVT = V->getOperand(1).getValueType();
10590 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
10593 // Only handle cases where both indexes are constants with the same type.
10594 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
10595 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
10597 if (InsIdx && ExtIdx &&
10598 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
10599 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
10601 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
10603 // indices are equal or bit offsets are equal => V1
10604 // otherwise => (extract_subvec V1, ExtIdx)
10605 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() ==
10606 ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits())
10607 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1));
10608 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT,
10609 DAG.getNode(ISD::BITCAST, dl,
10610 N->getOperand(0).getValueType(),
10611 V->getOperand(0)), N->getOperand(1));
10618 // Tries to turn a shuffle of two CONCAT_VECTORS into a single concat.
10619 static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
10620 EVT VT = N->getValueType(0);
10621 unsigned NumElts = VT.getVectorNumElements();
10623 SDValue N0 = N->getOperand(0);
10624 SDValue N1 = N->getOperand(1);
10625 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
10627 SmallVector<SDValue, 4> Ops;
10628 EVT ConcatVT = N0.getOperand(0).getValueType();
10629 unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements();
10630 unsigned NumConcats = NumElts / NumElemsPerConcat;
10632 // Look at every vector that's inserted. We're looking for exact
10633 // subvector-sized copies from a concatenated vector
10634 for (unsigned I = 0; I != NumConcats; ++I) {
10635 // Make sure we're dealing with a copy.
10636 unsigned Begin = I * NumElemsPerConcat;
10637 bool AllUndef = true, NoUndef = true;
10638 for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) {
10639 if (SVN->getMaskElt(J) >= 0)
10646 if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0)
10649 for (unsigned J = 1; J != NumElemsPerConcat; ++J)
10650 if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J))
10653 unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat;
10654 if (FirstElt < N0.getNumOperands())
10655 Ops.push_back(N0.getOperand(FirstElt));
10657 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
10659 } else if (AllUndef) {
10660 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType()));
10661 } else { // Mixed with general masks and undefs, can't do optimization.
10666 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
10669 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
10670 EVT VT = N->getValueType(0);
10671 unsigned NumElts = VT.getVectorNumElements();
10673 SDValue N0 = N->getOperand(0);
10674 SDValue N1 = N->getOperand(1);
10676 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
10678 // Canonicalize shuffle undef, undef -> undef
10679 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
10680 return DAG.getUNDEF(VT);
10682 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
10684 // Canonicalize shuffle v, v -> v, undef
10686 SmallVector<int, 8> NewMask;
10687 for (unsigned i = 0; i != NumElts; ++i) {
10688 int Idx = SVN->getMaskElt(i);
10689 if (Idx >= (int)NumElts) Idx -= NumElts;
10690 NewMask.push_back(Idx);
10692 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
10696 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
10697 if (N0.getOpcode() == ISD::UNDEF) {
10698 SmallVector<int, 8> NewMask;
10699 for (unsigned i = 0; i != NumElts; ++i) {
10700 int Idx = SVN->getMaskElt(i);
10702 if (Idx >= (int)NumElts)
10705 Idx = -1; // remove reference to lhs
10707 NewMask.push_back(Idx);
10709 return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT),
10713 // Remove references to rhs if it is undef
10714 if (N1.getOpcode() == ISD::UNDEF) {
10715 bool Changed = false;
10716 SmallVector<int, 8> NewMask;
10717 for (unsigned i = 0; i != NumElts; ++i) {
10718 int Idx = SVN->getMaskElt(i);
10719 if (Idx >= (int)NumElts) {
10723 NewMask.push_back(Idx);
10726 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
10729 // If it is a splat, check if the argument vector is another splat or a
10730 // build_vector with all scalar elements the same.
10731 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
10732 SDNode *V = N0.getNode();
10734 // If this is a bit convert that changes the element type of the vector but
10735 // not the number of vector elements, look through it. Be careful not to
10736 // look though conversions that change things like v4f32 to v2f64.
10737 if (V->getOpcode() == ISD::BITCAST) {
10738 SDValue ConvInput = V->getOperand(0);
10739 if (ConvInput.getValueType().isVector() &&
10740 ConvInput.getValueType().getVectorNumElements() == NumElts)
10741 V = ConvInput.getNode();
10744 if (V->getOpcode() == ISD::BUILD_VECTOR) {
10745 assert(V->getNumOperands() == NumElts &&
10746 "BUILD_VECTOR has wrong number of operands");
10748 bool AllSame = true;
10749 for (unsigned i = 0; i != NumElts; ++i) {
10750 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
10751 Base = V->getOperand(i);
10755 // Splat of <u, u, u, u>, return <u, u, u, u>
10756 if (!Base.getNode())
10758 for (unsigned i = 0; i != NumElts; ++i) {
10759 if (V->getOperand(i) != Base) {
10764 // Splat of <x, x, x, x>, return <x, x, x, x>
10770 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
10771 Level < AfterLegalizeVectorOps &&
10772 (N1.getOpcode() == ISD::UNDEF ||
10773 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
10774 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
10775 SDValue V = partitionShuffleOfConcats(N, DAG);
10781 // If this shuffle node is simply a swizzle of another shuffle node,
10782 // then try to simplify it.
10783 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
10784 N1.getOpcode() == ISD::UNDEF) {
10786 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
10788 // The incoming shuffle must be of the same type as the result of the
10789 // current shuffle.
10790 assert(OtherSV->getOperand(0).getValueType() == VT &&
10791 "Shuffle types don't match");
10793 SmallVector<int, 4> Mask;
10794 // Compute the combined shuffle mask.
10795 for (unsigned i = 0; i != NumElts; ++i) {
10796 int Idx = SVN->getMaskElt(i);
10797 assert(Idx < (int)NumElts && "Index references undef operand");
10798 // Next, this index comes from the first value, which is the incoming
10799 // shuffle. Adopt the incoming index.
10801 Idx = OtherSV->getMaskElt(Idx);
10802 Mask.push_back(Idx);
10805 // Check if all indices in Mask are Undef. In case, propagate Undef.
10806 bool isUndefMask = true;
10807 for (unsigned i = 0; i != NumElts && isUndefMask; ++i)
10808 isUndefMask &= Mask[i] < 0;
10811 return DAG.getUNDEF(VT);
10813 bool CommuteOperands = false;
10814 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) {
10815 // To be valid, the combine shuffle mask should only reference elements
10816 // from one of the two vectors in input to the inner shufflevector.
10817 bool IsValidMask = true;
10818 for (unsigned i = 0; i != NumElts && IsValidMask; ++i)
10819 // See if the combined mask only reference undefs or elements coming
10820 // from the first shufflevector operand.
10821 IsValidMask = Mask[i] < 0 || (unsigned)Mask[i] < NumElts;
10823 if (!IsValidMask) {
10824 IsValidMask = true;
10825 for (unsigned i = 0; i != NumElts && IsValidMask; ++i)
10826 // Check that all the elements come from the second shuffle operand.
10827 IsValidMask = Mask[i] < 0 || (unsigned)Mask[i] >= NumElts;
10828 CommuteOperands = IsValidMask;
10831 // Early exit if the combined shuffle mask is not valid.
10836 // See if this pair of shuffles can be safely folded according to either
10837 // of the following rules:
10838 // shuffle(shuffle(x, y), undef) -> x
10839 // shuffle(shuffle(x, undef), undef) -> x
10840 // shuffle(shuffle(x, y), undef) -> y
10841 bool IsIdentityMask = true;
10842 unsigned BaseMaskIndex = CommuteOperands ? NumElts : 0;
10843 for (unsigned i = 0; i != NumElts && IsIdentityMask; ++i) {
10848 // The combined shuffle must map each index to itself.
10849 IsIdentityMask = (unsigned)Mask[i] == i + BaseMaskIndex;
10852 if (IsIdentityMask) {
10853 if (CommuteOperands)
10854 // optimize shuffle(shuffle(x, y), undef) -> y.
10855 return OtherSV->getOperand(1);
10857 // optimize shuffle(shuffle(x, undef), undef) -> x
10858 // optimize shuffle(shuffle(x, y), undef) -> x
10859 return OtherSV->getOperand(0);
10862 // It may still be beneficial to combine the two shuffles if the
10863 // resulting shuffle is legal.
10864 if (TLI.isTypeLegal(VT)) {
10865 if (!CommuteOperands) {
10866 if (TLI.isShuffleMaskLegal(Mask, VT))
10867 // shuffle(shuffle(x, undef, M1), undef, M2) -> shuffle(x, undef, M3).
10868 // shuffle(shuffle(x, y, M1), undef, M2) -> shuffle(x, undef, M3)
10869 return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0), N1,
10872 // Compute the commuted shuffle mask.
10873 for (unsigned i = 0; i != NumElts; ++i) {
10877 else if (idx < (int)NumElts)
10878 Mask[i] = idx + NumElts;
10880 Mask[i] = idx - NumElts;
10883 if (TLI.isShuffleMaskLegal(Mask, VT))
10884 // shuffle(shuffle(x, y, M1), undef, M2) -> shuffle(y, undef, M3)
10885 return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(1), N1,
10891 // Canonicalize shuffles according to rules:
10892 // shuffle(A, shuffle(A, B)) -> shuffle(shuffle(A,B), A)
10893 // shuffle(B, shuffle(A, B)) -> shuffle(shuffle(A,B), B)
10894 // shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
10895 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && N0.getOpcode() != ISD::UNDEF &&
10896 N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
10897 TLI.isTypeLegal(VT)) {
10898 // The incoming shuffle must be of the same type as the result of the
10899 // current shuffle.
10900 assert(N1->getOperand(0).getValueType() == VT &&
10901 "Shuffle types don't match");
10903 SDValue SV0 = N1->getOperand(0);
10904 SDValue SV1 = N1->getOperand(1);
10905 bool HasSameOp0 = N0 == SV0;
10906 bool IsSV1Undef = SV1.getOpcode() == ISD::UNDEF;
10907 if (HasSameOp0 || IsSV1Undef || N0 == SV1)
10908 // Commute the operands of this shuffle so that next rule
10910 return DAG.getCommutedVectorShuffle(*SVN);
10913 // Try to fold according to rules:
10914 // shuffle(shuffle(A, B, M0), B, M1) -> shuffle(A, B, M2)
10915 // shuffle(shuffle(A, B, M0), A, M1) -> shuffle(A, B, M2)
10916 // shuffle(shuffle(A, Undef, M0), B, M1) -> shuffle(A, B, M2)
10917 // shuffle(shuffle(A, Undef, M0), A, M1) -> shuffle(A, Undef, M2)
10918 // Don't try to fold shuffles with illegal type.
10919 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
10920 N1.getOpcode() != ISD::UNDEF && TLI.isTypeLegal(VT)) {
10921 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
10923 // The incoming shuffle must be of the same type as the result of the
10924 // current shuffle.
10925 assert(OtherSV->getOperand(0).getValueType() == VT &&
10926 "Shuffle types don't match");
10928 SDValue SV0 = OtherSV->getOperand(0);
10929 SDValue SV1 = OtherSV->getOperand(1);
10930 bool HasSameOp0 = N1 == SV0;
10931 bool IsSV1Undef = SV1.getOpcode() == ISD::UNDEF;
10932 if (!HasSameOp0 && !IsSV1Undef && N1 != SV1)
10936 SmallVector<int, 4> Mask;
10937 // Compute the combined shuffle mask for a shuffle with SV0 as the first
10938 // operand, and SV1 as the second operand.
10939 for (unsigned i = 0; i != NumElts; ++i) {
10940 int Idx = SVN->getMaskElt(i);
10942 // Propagate Undef.
10943 Mask.push_back(Idx);
10947 if (Idx < (int)NumElts) {
10948 Idx = OtherSV->getMaskElt(Idx);
10949 if (IsSV1Undef && Idx >= (int) NumElts)
10950 Idx = -1; // Propagate Undef.
10952 Idx = HasSameOp0 ? Idx - NumElts : Idx;
10954 Mask.push_back(Idx);
10957 // Check if all indices in Mask are Undef. In case, propagate Undef.
10958 bool isUndefMask = true;
10959 for (unsigned i = 0; i != NumElts && isUndefMask; ++i)
10960 isUndefMask &= Mask[i] < 0;
10963 return DAG.getUNDEF(VT);
10965 // Avoid introducing shuffles with illegal mask.
10966 if (TLI.isShuffleMaskLegal(Mask, VT)) {
10968 // shuffle(shuffle(A, Undef, M0), B, M1) -> shuffle(A, B, M2)
10969 // shuffle(shuffle(A, Undef, M0), A, M1) -> shuffle(A, Undef, M2)
10970 return DAG.getVectorShuffle(VT, SDLoc(N), SV0, N1, &Mask[0]);
10971 return DAG.getVectorShuffle(VT, SDLoc(N), SV0, SV1, &Mask[0]);
10978 SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
10979 SDValue N0 = N->getOperand(0);
10980 SDValue N2 = N->getOperand(2);
10982 // If the input vector is a concatenation, and the insert replaces
10983 // one of the halves, we can optimize into a single concat_vectors.
10984 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
10985 N0->getNumOperands() == 2 && N2.getOpcode() == ISD::Constant) {
10986 APInt InsIdx = cast<ConstantSDNode>(N2)->getAPIntValue();
10987 EVT VT = N->getValueType(0);
10989 // Lower half: fold (insert_subvector (concat_vectors X, Y), Z) ->
10990 // (concat_vectors Z, Y)
10992 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
10993 N->getOperand(1), N0.getOperand(1));
10995 // Upper half: fold (insert_subvector (concat_vectors X, Y), Z) ->
10996 // (concat_vectors X, Z)
10997 if (InsIdx == VT.getVectorNumElements()/2)
10998 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
10999 N0.getOperand(0), N->getOperand(1));
11005 /// Returns a vector_shuffle if it able to transform an AND to a vector_shuffle
11006 /// with the destination vector and a zero vector.
11007 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
11008 /// vector_shuffle V, Zero, <0, 4, 2, 4>
11009 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
11010 EVT VT = N->getValueType(0);
11012 SDValue LHS = N->getOperand(0);
11013 SDValue RHS = N->getOperand(1);
11014 if (N->getOpcode() == ISD::AND) {
11015 if (RHS.getOpcode() == ISD::BITCAST)
11016 RHS = RHS.getOperand(0);
11017 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
11018 SmallVector<int, 8> Indices;
11019 unsigned NumElts = RHS.getNumOperands();
11020 for (unsigned i = 0; i != NumElts; ++i) {
11021 SDValue Elt = RHS.getOperand(i);
11022 if (!isa<ConstantSDNode>(Elt))
11025 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
11026 Indices.push_back(i);
11027 else if (cast<ConstantSDNode>(Elt)->isNullValue())
11028 Indices.push_back(NumElts);
11033 // Let's see if the target supports this vector_shuffle.
11034 EVT RVT = RHS.getValueType();
11035 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
11038 // Return the new VECTOR_SHUFFLE node.
11039 EVT EltVT = RVT.getVectorElementType();
11040 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
11041 DAG.getConstant(0, EltVT));
11042 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), RVT, ZeroOps);
11043 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
11044 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
11045 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
11052 /// Visit a binary vector operation, like ADD.
11053 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
11054 assert(N->getValueType(0).isVector() &&
11055 "SimplifyVBinOp only works on vectors!");
11057 SDValue LHS = N->getOperand(0);
11058 SDValue RHS = N->getOperand(1);
11059 SDValue Shuffle = XformToShuffleWithZero(N);
11060 if (Shuffle.getNode()) return Shuffle;
11062 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
11064 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
11065 RHS.getOpcode() == ISD::BUILD_VECTOR) {
11066 // Check if both vectors are constants. If not bail out.
11067 if (!(cast<BuildVectorSDNode>(LHS)->isConstant() &&
11068 cast<BuildVectorSDNode>(RHS)->isConstant()))
11071 SmallVector<SDValue, 8> Ops;
11072 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
11073 SDValue LHSOp = LHS.getOperand(i);
11074 SDValue RHSOp = RHS.getOperand(i);
11076 // Can't fold divide by zero.
11077 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
11078 N->getOpcode() == ISD::FDIV) {
11079 if ((RHSOp.getOpcode() == ISD::Constant &&
11080 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
11081 (RHSOp.getOpcode() == ISD::ConstantFP &&
11082 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
11086 EVT VT = LHSOp.getValueType();
11087 EVT RVT = RHSOp.getValueType();
11089 // Integer BUILD_VECTOR operands may have types larger than the element
11090 // size (e.g., when the element type is not legal). Prior to type
11091 // legalization, the types may not match between the two BUILD_VECTORS.
11092 // Truncate one of the operands to make them match.
11093 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
11094 RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, RHSOp);
11096 LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), RVT, LHSOp);
11100 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(LHS), VT,
11102 if (FoldOp.getOpcode() != ISD::UNDEF &&
11103 FoldOp.getOpcode() != ISD::Constant &&
11104 FoldOp.getOpcode() != ISD::ConstantFP)
11106 Ops.push_back(FoldOp);
11107 AddToWorklist(FoldOp.getNode());
11110 if (Ops.size() == LHS.getNumOperands())
11111 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), LHS.getValueType(), Ops);
11114 // Type legalization might introduce new shuffles in the DAG.
11115 // Fold (VBinOp (shuffle (A, Undef, Mask)), (shuffle (B, Undef, Mask)))
11116 // -> (shuffle (VBinOp (A, B)), Undef, Mask).
11117 if (LegalTypes && isa<ShuffleVectorSDNode>(LHS) &&
11118 isa<ShuffleVectorSDNode>(RHS) && LHS.hasOneUse() && RHS.hasOneUse() &&
11119 LHS.getOperand(1).getOpcode() == ISD::UNDEF &&
11120 RHS.getOperand(1).getOpcode() == ISD::UNDEF) {
11121 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(LHS);
11122 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(RHS);
11124 if (SVN0->getMask().equals(SVN1->getMask())) {
11125 EVT VT = N->getValueType(0);
11126 SDValue UndefVector = LHS.getOperand(1);
11127 SDValue NewBinOp = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
11128 LHS.getOperand(0), RHS.getOperand(0));
11129 AddUsersToWorklist(N);
11130 return DAG.getVectorShuffle(VT, SDLoc(N), NewBinOp, UndefVector,
11131 &SVN0->getMask()[0]);
11138 /// Visit a binary vector operation, like FABS/FNEG.
11139 SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
11140 assert(N->getValueType(0).isVector() &&
11141 "SimplifyVUnaryOp only works on vectors!");
11143 SDValue N0 = N->getOperand(0);
11145 if (N0.getOpcode() != ISD::BUILD_VECTOR)
11148 // Operand is a BUILD_VECTOR node, see if we can constant fold it.
11149 SmallVector<SDValue, 8> Ops;
11150 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
11151 SDValue Op = N0.getOperand(i);
11152 if (Op.getOpcode() != ISD::UNDEF &&
11153 Op.getOpcode() != ISD::ConstantFP)
11155 EVT EltVT = Op.getValueType();
11156 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(N0), EltVT, Op);
11157 if (FoldOp.getOpcode() != ISD::UNDEF &&
11158 FoldOp.getOpcode() != ISD::ConstantFP)
11160 Ops.push_back(FoldOp);
11161 AddToWorklist(FoldOp.getNode());
11164 if (Ops.size() != N0.getNumOperands())
11167 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N0.getValueType(), Ops);
11170 SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
11171 SDValue N1, SDValue N2){
11172 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
11174 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
11175 cast<CondCodeSDNode>(N0.getOperand(2))->get());
11177 // If we got a simplified select_cc node back from SimplifySelectCC, then
11178 // break it down into a new SETCC node, and a new SELECT node, and then return
11179 // the SELECT node, since we were called with a SELECT node.
11180 if (SCC.getNode()) {
11181 // Check to see if we got a select_cc back (to turn into setcc/select).
11182 // Otherwise, just return whatever node we got back, like fabs.
11183 if (SCC.getOpcode() == ISD::SELECT_CC) {
11184 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
11186 SCC.getOperand(0), SCC.getOperand(1),
11187 SCC.getOperand(4));
11188 AddToWorklist(SETCC.getNode());
11189 return DAG.getSelect(SDLoc(SCC), SCC.getValueType(), SETCC,
11190 SCC.getOperand(2), SCC.getOperand(3));
11198 /// Given a SELECT or a SELECT_CC node, where LHS and RHS are the two values
11199 /// being selected between, see if we can simplify the select. Callers of this
11200 /// should assume that TheSelect is deleted if this returns true. As such, they
11201 /// should return the appropriate thing (e.g. the node) back to the top-level of
11202 /// the DAG combiner loop to avoid it being looked at.
11203 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
11206 // Cannot simplify select with vector condition
11207 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
11209 // If this is a select from two identical things, try to pull the operation
11210 // through the select.
11211 if (LHS.getOpcode() != RHS.getOpcode() ||
11212 !LHS.hasOneUse() || !RHS.hasOneUse())
11215 // If this is a load and the token chain is identical, replace the select
11216 // of two loads with a load through a select of the address to load from.
11217 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
11218 // constants have been dropped into the constant pool.
11219 if (LHS.getOpcode() == ISD::LOAD) {
11220 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
11221 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
11223 // Token chains must be identical.
11224 if (LHS.getOperand(0) != RHS.getOperand(0) ||
11225 // Do not let this transformation reduce the number of volatile loads.
11226 LLD->isVolatile() || RLD->isVolatile() ||
11227 // If this is an EXTLOAD, the VT's must match.
11228 LLD->getMemoryVT() != RLD->getMemoryVT() ||
11229 // If this is an EXTLOAD, the kind of extension must match.
11230 (LLD->getExtensionType() != RLD->getExtensionType() &&
11231 // The only exception is if one of the extensions is anyext.
11232 LLD->getExtensionType() != ISD::EXTLOAD &&
11233 RLD->getExtensionType() != ISD::EXTLOAD) ||
11234 // FIXME: this discards src value information. This is
11235 // over-conservative. It would be beneficial to be able to remember
11236 // both potential memory locations. Since we are discarding
11237 // src value info, don't do the transformation if the memory
11238 // locations are not in the default address space.
11239 LLD->getPointerInfo().getAddrSpace() != 0 ||
11240 RLD->getPointerInfo().getAddrSpace() != 0 ||
11241 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
11242 LLD->getBasePtr().getValueType()))
11245 // Check that the select condition doesn't reach either load. If so,
11246 // folding this will induce a cycle into the DAG. If not, this is safe to
11247 // xform, so create a select of the addresses.
11249 if (TheSelect->getOpcode() == ISD::SELECT) {
11250 SDNode *CondNode = TheSelect->getOperand(0).getNode();
11251 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
11252 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
11254 // The loads must not depend on one another.
11255 if (LLD->isPredecessorOf(RLD) ||
11256 RLD->isPredecessorOf(LLD))
11258 Addr = DAG.getSelect(SDLoc(TheSelect),
11259 LLD->getBasePtr().getValueType(),
11260 TheSelect->getOperand(0), LLD->getBasePtr(),
11261 RLD->getBasePtr());
11262 } else { // Otherwise SELECT_CC
11263 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
11264 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
11266 if ((LLD->hasAnyUseOfValue(1) &&
11267 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
11268 (RLD->hasAnyUseOfValue(1) &&
11269 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
11272 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect),
11273 LLD->getBasePtr().getValueType(),
11274 TheSelect->getOperand(0),
11275 TheSelect->getOperand(1),
11276 LLD->getBasePtr(), RLD->getBasePtr(),
11277 TheSelect->getOperand(4));
11281 // It is safe to replace the two loads if they have different alignments,
11282 // but the new load must be the minimum (most restrictive) alignment of the
11284 bool isInvariant = LLD->getAlignment() & RLD->getAlignment();
11285 unsigned Alignment = std::min(LLD->getAlignment(), RLD->getAlignment());
11286 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
11287 Load = DAG.getLoad(TheSelect->getValueType(0),
11289 // FIXME: Discards pointer and AA info.
11290 LLD->getChain(), Addr, MachinePointerInfo(),
11291 LLD->isVolatile(), LLD->isNonTemporal(),
11292 isInvariant, Alignment);
11294 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
11295 RLD->getExtensionType() : LLD->getExtensionType(),
11297 TheSelect->getValueType(0),
11298 // FIXME: Discards pointer and AA info.
11299 LLD->getChain(), Addr, MachinePointerInfo(),
11300 LLD->getMemoryVT(), LLD->isVolatile(),
11301 LLD->isNonTemporal(), isInvariant, Alignment);
11304 // Users of the select now use the result of the load.
11305 CombineTo(TheSelect, Load);
11307 // Users of the old loads now use the new load's chain. We know the
11308 // old-load value is dead now.
11309 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
11310 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
11317 /// Simplify an expression of the form (N0 cond N1) ? N2 : N3
11318 /// where 'cond' is the comparison specified by CC.
11319 SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
11320 SDValue N2, SDValue N3,
11321 ISD::CondCode CC, bool NotExtCompare) {
11322 // (x ? y : y) -> y.
11323 if (N2 == N3) return N2;
11325 EVT VT = N2.getValueType();
11326 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
11327 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
11328 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
11330 // Determine if the condition we're dealing with is constant
11331 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
11332 N0, N1, CC, DL, false);
11333 if (SCC.getNode()) AddToWorklist(SCC.getNode());
11334 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
11336 // fold select_cc true, x, y -> x
11337 if (SCCC && !SCCC->isNullValue())
11339 // fold select_cc false, x, y -> y
11340 if (SCCC && SCCC->isNullValue())
11343 // Check to see if we can simplify the select into an fabs node
11344 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
11345 // Allow either -0.0 or 0.0
11346 if (CFP->getValueAPF().isZero()) {
11347 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
11348 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
11349 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
11350 N2 == N3.getOperand(0))
11351 return DAG.getNode(ISD::FABS, DL, VT, N0);
11353 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
11354 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
11355 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
11356 N2.getOperand(0) == N3)
11357 return DAG.getNode(ISD::FABS, DL, VT, N3);
11361 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
11362 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
11363 // in it. This is a win when the constant is not otherwise available because
11364 // it replaces two constant pool loads with one. We only do this if the FP
11365 // type is known to be legal, because if it isn't, then we are before legalize
11366 // types an we want the other legalization to happen first (e.g. to avoid
11367 // messing with soft float) and if the ConstantFP is not legal, because if
11368 // it is legal, we may not need to store the FP constant in a constant pool.
11369 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
11370 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
11371 if (TLI.isTypeLegal(N2.getValueType()) &&
11372 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
11373 TargetLowering::Legal &&
11374 !TLI.isFPImmLegal(TV->getValueAPF(), TV->getValueType(0)) &&
11375 !TLI.isFPImmLegal(FV->getValueAPF(), FV->getValueType(0))) &&
11376 // If both constants have multiple uses, then we won't need to do an
11377 // extra load, they are likely around in registers for other users.
11378 (TV->hasOneUse() || FV->hasOneUse())) {
11379 Constant *Elts[] = {
11380 const_cast<ConstantFP*>(FV->getConstantFPValue()),
11381 const_cast<ConstantFP*>(TV->getConstantFPValue())
11383 Type *FPTy = Elts[0]->getType();
11384 const DataLayout &TD = *TLI.getDataLayout();
11386 // Create a ConstantArray of the two constants.
11387 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
11388 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
11389 TD.getPrefTypeAlignment(FPTy));
11390 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11392 // Get the offsets to the 0 and 1 element of the array so that we can
11393 // select between them.
11394 SDValue Zero = DAG.getIntPtrConstant(0);
11395 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
11396 SDValue One = DAG.getIntPtrConstant(EltSize);
11398 SDValue Cond = DAG.getSetCC(DL,
11399 getSetCCResultType(N0.getValueType()),
11401 AddToWorklist(Cond.getNode());
11402 SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(),
11404 AddToWorklist(CstOffset.getNode());
11405 CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx,
11407 AddToWorklist(CPIdx.getNode());
11408 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
11409 MachinePointerInfo::getConstantPool(), false,
11410 false, false, Alignment);
11415 // Check to see if we can perform the "gzip trick", transforming
11416 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
11417 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
11418 (N1C->isNullValue() || // (a < 0) ? b : 0
11419 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
11420 EVT XType = N0.getValueType();
11421 EVT AType = N2.getValueType();
11422 if (XType.bitsGE(AType)) {
11423 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
11424 // single-bit constant.
11425 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
11426 unsigned ShCtV = N2C->getAPIntValue().logBase2();
11427 ShCtV = XType.getSizeInBits()-ShCtV-1;
11428 SDValue ShCt = DAG.getConstant(ShCtV,
11429 getShiftAmountTy(N0.getValueType()));
11430 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
11432 AddToWorklist(Shift.getNode());
11434 if (XType.bitsGT(AType)) {
11435 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
11436 AddToWorklist(Shift.getNode());
11439 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
11442 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
11444 DAG.getConstant(XType.getSizeInBits()-1,
11445 getShiftAmountTy(N0.getValueType())));
11446 AddToWorklist(Shift.getNode());
11448 if (XType.bitsGT(AType)) {
11449 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
11450 AddToWorklist(Shift.getNode());
11453 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
11457 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
11458 // where y is has a single bit set.
11459 // A plaintext description would be, we can turn the SELECT_CC into an AND
11460 // when the condition can be materialized as an all-ones register. Any
11461 // single bit-test can be materialized as an all-ones register with
11462 // shift-left and shift-right-arith.
11463 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
11464 N0->getValueType(0) == VT &&
11465 N1C && N1C->isNullValue() &&
11466 N2C && N2C->isNullValue()) {
11467 SDValue AndLHS = N0->getOperand(0);
11468 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
11469 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
11470 // Shift the tested bit over the sign bit.
11471 APInt AndMask = ConstAndRHS->getAPIntValue();
11473 DAG.getConstant(AndMask.countLeadingZeros(),
11474 getShiftAmountTy(AndLHS.getValueType()));
11475 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
11477 // Now arithmetic right shift it all the way over, so the result is either
11478 // all-ones, or zero.
11480 DAG.getConstant(AndMask.getBitWidth()-1,
11481 getShiftAmountTy(Shl.getValueType()));
11482 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
11484 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
11488 // fold select C, 16, 0 -> shl C, 4
11489 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
11490 TLI.getBooleanContents(N0.getValueType()) ==
11491 TargetLowering::ZeroOrOneBooleanContent) {
11493 // If the caller doesn't want us to simplify this into a zext of a compare,
11495 if (NotExtCompare && N2C->getAPIntValue() == 1)
11498 // Get a SetCC of the condition
11499 // NOTE: Don't create a SETCC if it's not legal on this target.
11500 if (!LegalOperations ||
11501 TLI.isOperationLegal(ISD::SETCC,
11502 LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) {
11504 // cast from setcc result type to select result type
11506 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
11508 if (N2.getValueType().bitsLT(SCC.getValueType()))
11509 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2),
11510 N2.getValueType());
11512 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
11513 N2.getValueType(), SCC);
11515 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
11516 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
11517 N2.getValueType(), SCC);
11520 AddToWorklist(SCC.getNode());
11521 AddToWorklist(Temp.getNode());
11523 if (N2C->getAPIntValue() == 1)
11526 // shl setcc result by log2 n2c
11527 return DAG.getNode(
11528 ISD::SHL, DL, N2.getValueType(), Temp,
11529 DAG.getConstant(N2C->getAPIntValue().logBase2(),
11530 getShiftAmountTy(Temp.getValueType())));
11534 // Check to see if this is the equivalent of setcc
11535 // FIXME: Turn all of these into setcc if setcc if setcc is legal
11536 // otherwise, go ahead with the folds.
11537 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
11538 EVT XType = N0.getValueType();
11539 if (!LegalOperations ||
11540 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) {
11541 SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC);
11542 if (Res.getValueType() != VT)
11543 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
11547 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
11548 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
11549 (!LegalOperations ||
11550 TLI.isOperationLegal(ISD::CTLZ, XType))) {
11551 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0);
11552 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
11553 DAG.getConstant(Log2_32(XType.getSizeInBits()),
11554 getShiftAmountTy(Ctlz.getValueType())));
11556 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
11557 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
11558 SDValue NegN0 = DAG.getNode(ISD::SUB, SDLoc(N0),
11559 XType, DAG.getConstant(0, XType), N0);
11560 SDValue NotN0 = DAG.getNOT(SDLoc(N0), N0, XType);
11561 return DAG.getNode(ISD::SRL, DL, XType,
11562 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
11563 DAG.getConstant(XType.getSizeInBits()-1,
11564 getShiftAmountTy(XType)));
11566 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
11567 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
11568 SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0,
11569 DAG.getConstant(XType.getSizeInBits()-1,
11570 getShiftAmountTy(N0.getValueType())));
11571 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
11575 // Check to see if this is an integer abs.
11576 // select_cc setg[te] X, 0, X, -X ->
11577 // select_cc setgt X, -1, X, -X ->
11578 // select_cc setl[te] X, 0, -X, X ->
11579 // select_cc setlt X, 1, -X, X ->
11580 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
11582 ConstantSDNode *SubC = nullptr;
11583 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
11584 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
11585 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
11586 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
11587 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
11588 (N1C->isOne() && CC == ISD::SETLT)) &&
11589 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
11590 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
11592 EVT XType = N0.getValueType();
11593 if (SubC && SubC->isNullValue() && XType.isInteger()) {
11594 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType,
11596 DAG.getConstant(XType.getSizeInBits()-1,
11597 getShiftAmountTy(N0.getValueType())));
11598 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0),
11600 AddToWorklist(Shift.getNode());
11601 AddToWorklist(Add.getNode());
11602 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
11609 /// This is a stub for TargetLowering::SimplifySetCC.
11610 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
11611 SDValue N1, ISD::CondCode Cond,
11612 SDLoc DL, bool foldBooleans) {
11613 TargetLowering::DAGCombinerInfo
11614 DagCombineInfo(DAG, Level, false, this);
11615 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
11618 /// Given an ISD::SDIV node expressing a divide by constant, return
11619 /// a DAG expression to select that will generate the same value by multiplying
11620 /// by a magic number. See:
11621 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
11622 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
11623 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
11627 // Avoid division by zero.
11628 if (!C->getAPIntValue())
11631 std::vector<SDNode*> Built;
11633 TLI.BuildSDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
11635 for (SDNode *N : Built)
11640 /// Given an ISD::SDIV node expressing a divide by constant power of 2, return a
11641 /// DAG expression that will generate the same value by right shifting.
11642 SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) {
11643 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
11647 // Avoid division by zero.
11648 if (!C->getAPIntValue())
11651 std::vector<SDNode *> Built;
11652 SDValue S = TLI.BuildSDIVPow2(N, C->getAPIntValue(), DAG, &Built);
11654 for (SDNode *N : Built)
11659 /// Given an ISD::UDIV node expressing a divide by constant, return a DAG
11660 /// expression that will generate the same value by multiplying by a magic
11662 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
11663 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
11664 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
11668 // Avoid division by zero.
11669 if (!C->getAPIntValue())
11672 std::vector<SDNode*> Built;
11674 TLI.BuildUDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
11676 for (SDNode *N : Built)
11681 /// Return true if base is a frame index, which is known not to alias with
11682 /// anything but itself. Provides base object and offset as results.
11683 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
11684 const GlobalValue *&GV, const void *&CV) {
11685 // Assume it is a primitive operation.
11686 Base = Ptr; Offset = 0; GV = nullptr; CV = nullptr;
11688 // If it's an adding a simple constant then integrate the offset.
11689 if (Base.getOpcode() == ISD::ADD) {
11690 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
11691 Base = Base.getOperand(0);
11692 Offset += C->getZExtValue();
11696 // Return the underlying GlobalValue, and update the Offset. Return false
11697 // for GlobalAddressSDNode since the same GlobalAddress may be represented
11698 // by multiple nodes with different offsets.
11699 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
11700 GV = G->getGlobal();
11701 Offset += G->getOffset();
11705 // Return the underlying Constant value, and update the Offset. Return false
11706 // for ConstantSDNodes since the same constant pool entry may be represented
11707 // by multiple nodes with different offsets.
11708 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
11709 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
11710 : (const void *)C->getConstVal();
11711 Offset += C->getOffset();
11714 // If it's any of the following then it can't alias with anything but itself.
11715 return isa<FrameIndexSDNode>(Base);
11718 /// Return true if there is any possibility that the two addresses overlap.
11719 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
11720 // If they are the same then they must be aliases.
11721 if (Op0->getBasePtr() == Op1->getBasePtr()) return true;
11723 // If they are both volatile then they cannot be reordered.
11724 if (Op0->isVolatile() && Op1->isVolatile()) return true;
11726 // Gather base node and offset information.
11727 SDValue Base1, Base2;
11728 int64_t Offset1, Offset2;
11729 const GlobalValue *GV1, *GV2;
11730 const void *CV1, *CV2;
11731 bool isFrameIndex1 = FindBaseOffset(Op0->getBasePtr(),
11732 Base1, Offset1, GV1, CV1);
11733 bool isFrameIndex2 = FindBaseOffset(Op1->getBasePtr(),
11734 Base2, Offset2, GV2, CV2);
11736 // If they have a same base address then check to see if they overlap.
11737 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
11738 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
11739 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
11741 // It is possible for different frame indices to alias each other, mostly
11742 // when tail call optimization reuses return address slots for arguments.
11743 // To catch this case, look up the actual index of frame indices to compute
11744 // the real alias relationship.
11745 if (isFrameIndex1 && isFrameIndex2) {
11746 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11747 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
11748 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
11749 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
11750 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
11753 // Otherwise, if we know what the bases are, and they aren't identical, then
11754 // we know they cannot alias.
11755 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
11758 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
11759 // compared to the size and offset of the access, we may be able to prove they
11760 // do not alias. This check is conservative for now to catch cases created by
11761 // splitting vector types.
11762 if ((Op0->getOriginalAlignment() == Op1->getOriginalAlignment()) &&
11763 (Op0->getSrcValueOffset() != Op1->getSrcValueOffset()) &&
11764 (Op0->getMemoryVT().getSizeInBits() >> 3 ==
11765 Op1->getMemoryVT().getSizeInBits() >> 3) &&
11766 (Op0->getOriginalAlignment() > Op0->getMemoryVT().getSizeInBits()) >> 3) {
11767 int64_t OffAlign1 = Op0->getSrcValueOffset() % Op0->getOriginalAlignment();
11768 int64_t OffAlign2 = Op1->getSrcValueOffset() % Op1->getOriginalAlignment();
11770 // There is no overlap between these relatively aligned accesses of similar
11771 // size, return no alias.
11772 if ((OffAlign1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign2 ||
11773 (OffAlign2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign1)
11777 bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0 ? CombinerGlobalAA :
11778 TLI.getTargetMachine().getSubtarget<TargetSubtargetInfo>().useAA();
11780 if (CombinerAAOnlyFunc.getNumOccurrences() &&
11781 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
11785 Op0->getMemOperand()->getValue() && Op1->getMemOperand()->getValue()) {
11786 // Use alias analysis information.
11787 int64_t MinOffset = std::min(Op0->getSrcValueOffset(),
11788 Op1->getSrcValueOffset());
11789 int64_t Overlap1 = (Op0->getMemoryVT().getSizeInBits() >> 3) +
11790 Op0->getSrcValueOffset() - MinOffset;
11791 int64_t Overlap2 = (Op1->getMemoryVT().getSizeInBits() >> 3) +
11792 Op1->getSrcValueOffset() - MinOffset;
11793 AliasAnalysis::AliasResult AAResult =
11794 AA.alias(AliasAnalysis::Location(Op0->getMemOperand()->getValue(),
11796 UseTBAA ? Op0->getAAInfo() : AAMDNodes()),
11797 AliasAnalysis::Location(Op1->getMemOperand()->getValue(),
11799 UseTBAA ? Op1->getAAInfo() : AAMDNodes()));
11800 if (AAResult == AliasAnalysis::NoAlias)
11804 // Otherwise we have to assume they alias.
11808 /// Walk up chain skipping non-aliasing memory nodes,
11809 /// looking for aliasing nodes and adding them to the Aliases vector.
11810 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
11811 SmallVectorImpl<SDValue> &Aliases) {
11812 SmallVector<SDValue, 8> Chains; // List of chains to visit.
11813 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
11815 // Get alias information for node.
11816 bool IsLoad = isa<LoadSDNode>(N) && !cast<LSBaseSDNode>(N)->isVolatile();
11819 Chains.push_back(OriginalChain);
11820 unsigned Depth = 0;
11822 // Look at each chain and determine if it is an alias. If so, add it to the
11823 // aliases list. If not, then continue up the chain looking for the next
11825 while (!Chains.empty()) {
11826 SDValue Chain = Chains.back();
11829 // For TokenFactor nodes, look at each operand and only continue up the
11830 // chain until we find two aliases. If we've seen two aliases, assume we'll
11831 // find more and revert to original chain since the xform is unlikely to be
11834 // FIXME: The depth check could be made to return the last non-aliasing
11835 // chain we found before we hit a tokenfactor rather than the original
11837 if (Depth > 6 || Aliases.size() == 2) {
11839 Aliases.push_back(OriginalChain);
11843 // Don't bother if we've been before.
11844 if (!Visited.insert(Chain.getNode()))
11847 switch (Chain.getOpcode()) {
11848 case ISD::EntryToken:
11849 // Entry token is ideal chain operand, but handled in FindBetterChain.
11854 // Get alias information for Chain.
11855 bool IsOpLoad = isa<LoadSDNode>(Chain.getNode()) &&
11856 !cast<LSBaseSDNode>(Chain.getNode())->isVolatile();
11858 // If chain is alias then stop here.
11859 if (!(IsLoad && IsOpLoad) &&
11860 isAlias(cast<LSBaseSDNode>(N), cast<LSBaseSDNode>(Chain.getNode()))) {
11861 Aliases.push_back(Chain);
11863 // Look further up the chain.
11864 Chains.push_back(Chain.getOperand(0));
11870 case ISD::TokenFactor:
11871 // We have to check each of the operands of the token factor for "small"
11872 // token factors, so we queue them up. Adding the operands to the queue
11873 // (stack) in reverse order maintains the original order and increases the
11874 // likelihood that getNode will find a matching token factor (CSE.)
11875 if (Chain.getNumOperands() > 16) {
11876 Aliases.push_back(Chain);
11879 for (unsigned n = Chain.getNumOperands(); n;)
11880 Chains.push_back(Chain.getOperand(--n));
11885 // For all other instructions we will just have to take what we can get.
11886 Aliases.push_back(Chain);
11891 // We need to be careful here to also search for aliases through the
11892 // value operand of a store, etc. Consider the following situation:
11894 // L1 = load Token1, %52
11895 // S1 = store Token1, L1, %51
11896 // L2 = load Token1, %52+8
11897 // S2 = store Token1, L2, %51+8
11898 // Token2 = Token(S1, S2)
11899 // L3 = load Token2, %53
11900 // S3 = store Token2, L3, %52
11901 // L4 = load Token2, %53+8
11902 // S4 = store Token2, L4, %52+8
11903 // If we search for aliases of S3 (which loads address %52), and we look
11904 // only through the chain, then we'll miss the trivial dependence on L1
11905 // (which also loads from %52). We then might change all loads and
11906 // stores to use Token1 as their chain operand, which could result in
11907 // copying %53 into %52 before copying %52 into %51 (which should
11910 // The problem is, however, that searching for such data dependencies
11911 // can become expensive, and the cost is not directly related to the
11912 // chain depth. Instead, we'll rule out such configurations here by
11913 // insisting that we've visited all chain users (except for users
11914 // of the original chain, which is not necessary). When doing this,
11915 // we need to look through nodes we don't care about (otherwise, things
11916 // like register copies will interfere with trivial cases).
11918 SmallVector<const SDNode *, 16> Worklist;
11919 for (const SDNode *N : Visited)
11920 if (N != OriginalChain.getNode())
11921 Worklist.push_back(N);
11923 while (!Worklist.empty()) {
11924 const SDNode *M = Worklist.pop_back_val();
11926 // We have already visited M, and want to make sure we've visited any uses
11927 // of M that we care about. For uses that we've not visisted, and don't
11928 // care about, queue them to the worklist.
11930 for (SDNode::use_iterator UI = M->use_begin(),
11931 UIE = M->use_end(); UI != UIE; ++UI)
11932 if (UI.getUse().getValueType() == MVT::Other && Visited.insert(*UI)) {
11933 if (isa<MemIntrinsicSDNode>(*UI) || isa<MemSDNode>(*UI)) {
11934 // We've not visited this use, and we care about it (it could have an
11935 // ordering dependency with the original node).
11937 Aliases.push_back(OriginalChain);
11941 // We've not visited this use, but we don't care about it. Mark it as
11942 // visited and enqueue it to the worklist.
11943 Worklist.push_back(*UI);
11948 /// Walk up chain skipping non-aliasing memory nodes, looking for a better chain
11949 /// (aliasing node.)
11950 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
11951 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
11953 // Accumulate all the aliases to this node.
11954 GatherAllAliases(N, OldChain, Aliases);
11956 // If no operands then chain to entry token.
11957 if (Aliases.size() == 0)
11958 return DAG.getEntryNode();
11960 // If a single operand then chain to it. We don't need to revisit it.
11961 if (Aliases.size() == 1)
11964 // Construct a custom tailored token factor.
11965 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Aliases);
11968 /// This is the entry point for the file.
11969 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
11970 CodeGenOpt::Level OptLevel) {
11971 /// This is the main entry point to this class.
11972 DAGCombiner(*this, AA, OptLevel).Run(Level);