1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/Target/TargetData.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/SmallPtrSet.h"
39 #include "llvm/ADT/Statistic.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/MathExtras.h"
47 STATISTIC(NodesCombined , "Number of dag nodes combined");
48 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
49 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
55 cl::desc("Pop up a window to show dags before the first "
58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
59 cl::desc("Pop up a window to show dags before the second "
62 static const bool ViewDAGCombine1 = false;
63 static const bool ViewDAGCombine2 = false;
67 CombinerAA("combiner-alias-analysis", cl::Hidden,
68 cl::desc("Turn on alias analysis during testing"));
71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
72 cl::desc("Include global information in alias analysis"));
74 //------------------------------ DAGCombiner ---------------------------------//
76 class VISIBILITY_HIDDEN DAGCombiner {
81 // Worklist of all of the nodes that need to be simplified.
82 std::vector<SDNode*> WorkList;
84 // AA - Used for DAG load/store alias analysis.
87 /// AddUsersToWorkList - When an instruction is simplified, add all users of
88 /// the instruction to the work lists because they might get more simplified
91 void AddUsersToWorkList(SDNode *N) {
92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
97 /// removeFromWorkList - remove all instances of N from the worklist.
99 void removeFromWorkList(SDNode *N) {
100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
105 /// AddToWorkList - Add to the work list making sure it's instance is at the
106 /// the back (next to be processed.)
107 void AddToWorkList(SDNode *N) {
108 removeFromWorkList(N);
109 WorkList.push_back(N);
112 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
114 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
116 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
117 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
118 DOUT << " and " << NumTo-1 << " other values\n";
119 std::vector<SDNode*> NowDead;
120 DAG.ReplaceAllUsesWith(N, To, &NowDead);
123 // Push the new nodes and any users onto the worklist
124 for (unsigned i = 0, e = NumTo; i != e; ++i) {
125 AddToWorkList(To[i].Val);
126 AddUsersToWorkList(To[i].Val);
130 // Nodes can be reintroduced into the worklist. Make sure we do not
131 // process a node that has been replaced.
132 removeFromWorkList(N);
133 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
134 removeFromWorkList(NowDead[i]);
136 // Finally, since the node is now dead, remove it from the graph.
138 return SDOperand(N, 0);
141 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
142 return CombineTo(N, &Res, 1, AddTo);
145 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
147 SDOperand To[] = { Res0, Res1 };
148 return CombineTo(N, To, 2, AddTo);
152 /// SimplifyDemandedBits - Check the specified integer node value to see if
153 /// it can be simplified or if things it uses can be simplified by bit
154 /// propagation. If so, return true.
155 bool SimplifyDemandedBits(SDOperand Op) {
156 TargetLowering::TargetLoweringOpt TLO(DAG);
157 uint64_t KnownZero, KnownOne;
158 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
159 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
163 AddToWorkList(Op.Val);
165 // Replace the old value with the new one.
167 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
168 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
171 std::vector<SDNode*> NowDead;
172 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
174 // Push the new node and any (possibly new) users onto the worklist.
175 AddToWorkList(TLO.New.Val);
176 AddUsersToWorkList(TLO.New.Val);
178 // Nodes can end up on the worklist more than once. Make sure we do
179 // not process a node that has been replaced.
180 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
181 removeFromWorkList(NowDead[i]);
183 // Finally, if the node is now dead, remove it from the graph. The node
184 // may not be dead if the replacement process recursively simplified to
185 // something else needing this node.
186 if (TLO.Old.Val->use_empty()) {
187 removeFromWorkList(TLO.Old.Val);
189 // If the operands of this node are only used by the node, they will now
190 // be dead. Make sure to visit them first to delete dead nodes early.
191 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
192 if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
193 AddToWorkList(TLO.Old.Val->getOperand(i).Val);
195 DAG.DeleteNode(TLO.Old.Val);
200 bool CombineToPreIndexedLoadStore(SDNode *N);
201 bool CombineToPostIndexedLoadStore(SDNode *N);
204 /// visit - call the node-specific routine that knows how to fold each
205 /// particular type of node.
206 SDOperand visit(SDNode *N);
208 // Visitation implementation - Implement dag node combining for different
209 // node types. The semantics are as follows:
211 // SDOperand.Val == 0 - No change was made
212 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
213 // otherwise - N should be replaced by the returned Operand.
215 SDOperand visitTokenFactor(SDNode *N);
216 SDOperand visitADD(SDNode *N);
217 SDOperand visitSUB(SDNode *N);
218 SDOperand visitADDC(SDNode *N);
219 SDOperand visitADDE(SDNode *N);
220 SDOperand visitMUL(SDNode *N);
221 SDOperand visitSDIV(SDNode *N);
222 SDOperand visitUDIV(SDNode *N);
223 SDOperand visitSREM(SDNode *N);
224 SDOperand visitUREM(SDNode *N);
225 SDOperand visitMULHU(SDNode *N);
226 SDOperand visitMULHS(SDNode *N);
227 SDOperand visitAND(SDNode *N);
228 SDOperand visitOR(SDNode *N);
229 SDOperand visitXOR(SDNode *N);
230 SDOperand SimplifyVBinOp(SDNode *N);
231 SDOperand visitSHL(SDNode *N);
232 SDOperand visitSRA(SDNode *N);
233 SDOperand visitSRL(SDNode *N);
234 SDOperand visitCTLZ(SDNode *N);
235 SDOperand visitCTTZ(SDNode *N);
236 SDOperand visitCTPOP(SDNode *N);
237 SDOperand visitSELECT(SDNode *N);
238 SDOperand visitSELECT_CC(SDNode *N);
239 SDOperand visitSETCC(SDNode *N);
240 SDOperand visitSIGN_EXTEND(SDNode *N);
241 SDOperand visitZERO_EXTEND(SDNode *N);
242 SDOperand visitANY_EXTEND(SDNode *N);
243 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
244 SDOperand visitTRUNCATE(SDNode *N);
245 SDOperand visitBIT_CONVERT(SDNode *N);
246 SDOperand visitFADD(SDNode *N);
247 SDOperand visitFSUB(SDNode *N);
248 SDOperand visitFMUL(SDNode *N);
249 SDOperand visitFDIV(SDNode *N);
250 SDOperand visitFREM(SDNode *N);
251 SDOperand visitFCOPYSIGN(SDNode *N);
252 SDOperand visitSINT_TO_FP(SDNode *N);
253 SDOperand visitUINT_TO_FP(SDNode *N);
254 SDOperand visitFP_TO_SINT(SDNode *N);
255 SDOperand visitFP_TO_UINT(SDNode *N);
256 SDOperand visitFP_ROUND(SDNode *N);
257 SDOperand visitFP_ROUND_INREG(SDNode *N);
258 SDOperand visitFP_EXTEND(SDNode *N);
259 SDOperand visitFNEG(SDNode *N);
260 SDOperand visitFABS(SDNode *N);
261 SDOperand visitBRCOND(SDNode *N);
262 SDOperand visitBR_CC(SDNode *N);
263 SDOperand visitLOAD(SDNode *N);
264 SDOperand visitSTORE(SDNode *N);
265 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
266 SDOperand visitBUILD_VECTOR(SDNode *N);
267 SDOperand visitCONCAT_VECTORS(SDNode *N);
268 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
270 SDOperand XformToShuffleWithZero(SDNode *N);
271 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
273 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
274 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
275 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
276 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
277 SDOperand N3, ISD::CondCode CC,
278 bool NotExtCompare = false);
279 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
280 ISD::CondCode Cond, bool foldBooleans = true);
281 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
282 SDOperand BuildSDIV(SDNode *N);
283 SDOperand BuildUDIV(SDNode *N);
284 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
285 SDOperand ReduceLoadWidth(SDNode *N);
287 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
288 /// looking for aliasing nodes and adding them to the Aliases vector.
289 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
290 SmallVector<SDOperand, 8> &Aliases);
292 /// isAlias - Return true if there is any possibility that the two addresses
294 bool isAlias(SDOperand Ptr1, int64_t Size1,
295 const Value *SrcValue1, int SrcValueOffset1,
296 SDOperand Ptr2, int64_t Size2,
297 const Value *SrcValue2, int SrcValueOffset2);
299 /// FindAliasInfo - Extracts the relevant alias information from the memory
300 /// node. Returns true if the operand was a load.
301 bool FindAliasInfo(SDNode *N,
302 SDOperand &Ptr, int64_t &Size,
303 const Value *&SrcValue, int &SrcValueOffset);
305 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
306 /// looking for a better chain (aliasing node.)
307 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
310 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
312 TLI(D.getTargetLoweringInfo()),
313 AfterLegalize(false),
316 /// Run - runs the dag combiner on all nodes in the work list
317 void Run(bool RunningAfterLegalize);
321 //===----------------------------------------------------------------------===//
322 // TargetLowering::DAGCombinerInfo implementation
323 //===----------------------------------------------------------------------===//
325 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
326 ((DAGCombiner*)DC)->AddToWorkList(N);
329 SDOperand TargetLowering::DAGCombinerInfo::
330 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
331 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
334 SDOperand TargetLowering::DAGCombinerInfo::
335 CombineTo(SDNode *N, SDOperand Res) {
336 return ((DAGCombiner*)DC)->CombineTo(N, Res);
340 SDOperand TargetLowering::DAGCombinerInfo::
341 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
342 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
346 //===----------------------------------------------------------------------===//
348 //===----------------------------------------------------------------------===//
350 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
351 /// specified expression for the same cost as the expression itself, or 2 if we
352 /// can compute the negated form more cheaply than the expression itself.
353 static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
354 // fneg is removable even if it has multiple uses.
355 if (Op.getOpcode() == ISD::FNEG) return 2;
357 // Don't allow anything with multiple uses.
358 if (!Op.hasOneUse()) return 0;
360 // Don't recurse exponentially.
361 if (Depth > 6) return 0;
363 switch (Op.getOpcode()) {
364 default: return false;
365 case ISD::ConstantFP:
368 // FIXME: determine better conditions for this xform.
369 if (!UnsafeFPMath) return 0;
372 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
375 return isNegatibleForFree(Op.getOperand(1), Depth+1);
377 // We can't turn -(A-B) into B-A when we honor signed zeros.
378 if (!UnsafeFPMath) return 0;
385 if (HonorSignDependentRoundingFPMath()) return 0;
387 // -(X*Y) -> (-X * Y) or (X*-Y)
388 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
391 return isNegatibleForFree(Op.getOperand(1), Depth+1);
396 return isNegatibleForFree(Op.getOperand(0), Depth+1);
400 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
401 /// returns the newly negated expression.
402 static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
403 unsigned Depth = 0) {
404 // fneg is removable even if it has multiple uses.
405 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
407 // Don't allow anything with multiple uses.
408 assert(Op.hasOneUse() && "Unknown reuse!");
410 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
411 switch (Op.getOpcode()) {
412 default: assert(0 && "Unknown code");
413 case ISD::ConstantFP: {
414 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
416 return DAG.getConstantFP(V, Op.getValueType());
419 // FIXME: determine better conditions for this xform.
420 assert(UnsafeFPMath);
423 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
424 return DAG.getNode(ISD::FSUB, Op.getValueType(),
425 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
428 return DAG.getNode(ISD::FSUB, Op.getValueType(),
429 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1),
432 // We can't turn -(A-B) into B-A when we honor signed zeros.
433 assert(UnsafeFPMath);
436 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
437 if (N0CFP->getValueAPF().isZero())
438 return Op.getOperand(1);
441 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
446 assert(!HonorSignDependentRoundingFPMath());
449 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
450 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
451 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
455 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
457 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
462 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
463 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
468 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
469 // that selects between the values 1 and 0, making it equivalent to a setcc.
470 // Also, set the incoming LHS, RHS, and CC references to the appropriate
471 // nodes based on the type of node we are checking. This simplifies life a
472 // bit for the callers.
473 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
475 if (N.getOpcode() == ISD::SETCC) {
476 LHS = N.getOperand(0);
477 RHS = N.getOperand(1);
478 CC = N.getOperand(2);
481 if (N.getOpcode() == ISD::SELECT_CC &&
482 N.getOperand(2).getOpcode() == ISD::Constant &&
483 N.getOperand(3).getOpcode() == ISD::Constant &&
484 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
485 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
486 LHS = N.getOperand(0);
487 RHS = N.getOperand(1);
488 CC = N.getOperand(4);
494 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
495 // one use. If this is true, it allows the users to invert the operation for
496 // free when it is profitable to do so.
497 static bool isOneUseSetCC(SDOperand N) {
498 SDOperand N0, N1, N2;
499 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
504 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
505 MVT::ValueType VT = N0.getValueType();
506 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
507 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
508 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
509 if (isa<ConstantSDNode>(N1)) {
510 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
511 AddToWorkList(OpNode.Val);
512 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
513 } else if (N0.hasOneUse()) {
514 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
515 AddToWorkList(OpNode.Val);
516 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
519 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
520 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
521 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
522 if (isa<ConstantSDNode>(N0)) {
523 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
524 AddToWorkList(OpNode.Val);
525 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
526 } else if (N1.hasOneUse()) {
527 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
528 AddToWorkList(OpNode.Val);
529 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
535 //===----------------------------------------------------------------------===//
536 // Main DAG Combiner implementation
537 //===----------------------------------------------------------------------===//
539 void DAGCombiner::Run(bool RunningAfterLegalize) {
540 // set the instance variable, so that the various visit routines may use it.
541 AfterLegalize = RunningAfterLegalize;
543 // Add all the dag nodes to the worklist.
544 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
545 E = DAG.allnodes_end(); I != E; ++I)
546 WorkList.push_back(I);
548 // Create a dummy node (which is not added to allnodes), that adds a reference
549 // to the root node, preventing it from being deleted, and tracking any
550 // changes of the root.
551 HandleSDNode Dummy(DAG.getRoot());
553 // The root of the dag may dangle to deleted nodes until the dag combiner is
554 // done. Set it to null to avoid confusion.
555 DAG.setRoot(SDOperand());
557 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
558 TargetLowering::DAGCombinerInfo
559 DagCombineInfo(DAG, !RunningAfterLegalize, false, this);
561 // while the worklist isn't empty, inspect the node on the end of it and
562 // try and combine it.
563 while (!WorkList.empty()) {
564 SDNode *N = WorkList.back();
567 // If N has no uses, it is dead. Make sure to revisit all N's operands once
568 // N is deleted from the DAG, since they too may now be dead or may have a
569 // reduced number of uses, allowing other xforms.
570 if (N->use_empty() && N != &Dummy) {
571 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
572 AddToWorkList(N->getOperand(i).Val);
578 SDOperand RV = visit(N);
580 // If nothing happened, try a target-specific DAG combine.
582 assert(N->getOpcode() != ISD::DELETED_NODE &&
583 "Node was deleted but visit returned NULL!");
584 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
585 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
586 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
591 // If we get back the same node we passed in, rather than a new node or
592 // zero, we know that the node must have defined multiple values and
593 // CombineTo was used. Since CombineTo takes care of the worklist
594 // mechanics for us, we have no work to do in this case.
596 assert(N->getOpcode() != ISD::DELETED_NODE &&
597 RV.Val->getOpcode() != ISD::DELETED_NODE &&
598 "Node was deleted but visit returned new node!");
600 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
601 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
603 std::vector<SDNode*> NowDead;
604 if (N->getNumValues() == RV.Val->getNumValues())
605 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
607 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
609 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
612 // Push the new node and any users onto the worklist
613 AddToWorkList(RV.Val);
614 AddUsersToWorkList(RV.Val);
616 // Nodes can be reintroduced into the worklist. Make sure we do not
617 // process a node that has been replaced.
618 removeFromWorkList(N);
619 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
620 removeFromWorkList(NowDead[i]);
622 // Finally, since the node is now dead, remove it from the graph.
628 // If the root changed (e.g. it was a dead load, update the root).
629 DAG.setRoot(Dummy.getValue());
632 SDOperand DAGCombiner::visit(SDNode *N) {
633 switch(N->getOpcode()) {
635 case ISD::TokenFactor: return visitTokenFactor(N);
636 case ISD::ADD: return visitADD(N);
637 case ISD::SUB: return visitSUB(N);
638 case ISD::ADDC: return visitADDC(N);
639 case ISD::ADDE: return visitADDE(N);
640 case ISD::MUL: return visitMUL(N);
641 case ISD::SDIV: return visitSDIV(N);
642 case ISD::UDIV: return visitUDIV(N);
643 case ISD::SREM: return visitSREM(N);
644 case ISD::UREM: return visitUREM(N);
645 case ISD::MULHU: return visitMULHU(N);
646 case ISD::MULHS: return visitMULHS(N);
647 case ISD::AND: return visitAND(N);
648 case ISD::OR: return visitOR(N);
649 case ISD::XOR: return visitXOR(N);
650 case ISD::SHL: return visitSHL(N);
651 case ISD::SRA: return visitSRA(N);
652 case ISD::SRL: return visitSRL(N);
653 case ISD::CTLZ: return visitCTLZ(N);
654 case ISD::CTTZ: return visitCTTZ(N);
655 case ISD::CTPOP: return visitCTPOP(N);
656 case ISD::SELECT: return visitSELECT(N);
657 case ISD::SELECT_CC: return visitSELECT_CC(N);
658 case ISD::SETCC: return visitSETCC(N);
659 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
660 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
661 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
662 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
663 case ISD::TRUNCATE: return visitTRUNCATE(N);
664 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
665 case ISD::FADD: return visitFADD(N);
666 case ISD::FSUB: return visitFSUB(N);
667 case ISD::FMUL: return visitFMUL(N);
668 case ISD::FDIV: return visitFDIV(N);
669 case ISD::FREM: return visitFREM(N);
670 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
671 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
672 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
673 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
674 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
675 case ISD::FP_ROUND: return visitFP_ROUND(N);
676 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
677 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
678 case ISD::FNEG: return visitFNEG(N);
679 case ISD::FABS: return visitFABS(N);
680 case ISD::BRCOND: return visitBRCOND(N);
681 case ISD::BR_CC: return visitBR_CC(N);
682 case ISD::LOAD: return visitLOAD(N);
683 case ISD::STORE: return visitSTORE(N);
684 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
685 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
686 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
687 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
692 /// getInputChainForNode - Given a node, return its input chain if it has one,
693 /// otherwise return a null sd operand.
694 static SDOperand getInputChainForNode(SDNode *N) {
695 if (unsigned NumOps = N->getNumOperands()) {
696 if (N->getOperand(0).getValueType() == MVT::Other)
697 return N->getOperand(0);
698 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
699 return N->getOperand(NumOps-1);
700 for (unsigned i = 1; i < NumOps-1; ++i)
701 if (N->getOperand(i).getValueType() == MVT::Other)
702 return N->getOperand(i);
704 return SDOperand(0, 0);
707 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
708 // If N has two operands, where one has an input chain equal to the other,
709 // the 'other' chain is redundant.
710 if (N->getNumOperands() == 2) {
711 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
712 return N->getOperand(0);
713 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
714 return N->getOperand(1);
717 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
718 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
719 SmallPtrSet<SDNode*, 16> SeenOps;
720 bool Changed = false; // If we should replace this token factor.
722 // Start out with this token factor.
725 // Iterate through token factors. The TFs grows when new token factors are
727 for (unsigned i = 0; i < TFs.size(); ++i) {
730 // Check each of the operands.
731 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
732 SDOperand Op = TF->getOperand(i);
734 switch (Op.getOpcode()) {
735 case ISD::EntryToken:
736 // Entry tokens don't need to be added to the list. They are
741 case ISD::TokenFactor:
742 if ((CombinerAA || Op.hasOneUse()) &&
743 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
744 // Queue up for processing.
745 TFs.push_back(Op.Val);
746 // Clean up in case the token factor is removed.
747 AddToWorkList(Op.Val);
754 // Only add if it isn't already in the list.
755 if (SeenOps.insert(Op.Val))
766 // If we've change things around then replace token factor.
768 if (Ops.size() == 0) {
769 // The entry token is the only possible outcome.
770 Result = DAG.getEntryNode();
772 // New and improved token factor.
773 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
776 // Don't add users to work list.
777 return CombineTo(N, Result, false);
784 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
785 MVT::ValueType VT = N0.getValueType();
786 SDOperand N00 = N0.getOperand(0);
787 SDOperand N01 = N0.getOperand(1);
788 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
789 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
790 isa<ConstantSDNode>(N00.getOperand(1))) {
791 N0 = DAG.getNode(ISD::ADD, VT,
792 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
793 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
794 return DAG.getNode(ISD::ADD, VT, N0, N1);
800 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
802 MVT::ValueType VT = N->getValueType(0);
803 unsigned Opc = N->getOpcode();
804 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
805 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
806 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
807 ISD::CondCode CC = ISD::SETCC_INVALID;
809 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
811 SDOperand CCOp = Slct.getOperand(0);
812 if (CCOp.getOpcode() == ISD::SETCC)
813 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
816 bool DoXform = false;
818 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
820 if (LHS.getOpcode() == ISD::Constant &&
821 cast<ConstantSDNode>(LHS)->isNullValue())
823 else if (CC != ISD::SETCC_INVALID &&
824 RHS.getOpcode() == ISD::Constant &&
825 cast<ConstantSDNode>(RHS)->isNullValue()) {
827 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType()
828 : Slct.getOperand(0).getOperand(0).getValueType());
829 CC = ISD::getSetCCInverse(CC, isInt);
835 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
837 return DAG.getSelectCC(OtherOp, Result,
838 Slct.getOperand(0), Slct.getOperand(1), CC);
839 SDOperand CCOp = Slct.getOperand(0);
841 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
842 CCOp.getOperand(1), CC);
843 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
848 SDOperand DAGCombiner::visitADD(SDNode *N) {
849 SDOperand N0 = N->getOperand(0);
850 SDOperand N1 = N->getOperand(1);
851 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
852 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
853 MVT::ValueType VT = N0.getValueType();
856 if (MVT::isVector(VT)) {
857 SDOperand FoldedVOp = SimplifyVBinOp(N);
858 if (FoldedVOp.Val) return FoldedVOp;
861 // fold (add x, undef) -> undef
862 if (N0.getOpcode() == ISD::UNDEF)
864 if (N1.getOpcode() == ISD::UNDEF)
866 // fold (add c1, c2) -> c1+c2
868 return DAG.getNode(ISD::ADD, VT, N0, N1);
869 // canonicalize constant to RHS
871 return DAG.getNode(ISD::ADD, VT, N1, N0);
872 // fold (add x, 0) -> x
873 if (N1C && N1C->isNullValue())
875 // fold ((c1-A)+c2) -> (c1+c2)-A
876 if (N1C && N0.getOpcode() == ISD::SUB)
877 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
878 return DAG.getNode(ISD::SUB, VT,
879 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
882 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
885 // fold ((0-A) + B) -> B-A
886 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
887 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
888 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
889 // fold (A + (0-B)) -> A-B
890 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
891 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
892 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
893 // fold (A+(B-A)) -> B
894 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
895 return N1.getOperand(0);
897 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
898 return SDOperand(N, 0);
900 // fold (a+b) -> (a|b) iff a and b share no bits.
901 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
902 uint64_t LHSZero, LHSOne;
903 uint64_t RHSZero, RHSOne;
904 uint64_t Mask = MVT::getIntVTBitMask(VT);
905 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
907 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
909 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
910 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
911 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
912 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
913 return DAG.getNode(ISD::OR, VT, N0, N1);
917 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
918 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
919 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
920 if (Result.Val) return Result;
922 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
923 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
924 if (Result.Val) return Result;
927 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
928 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
929 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
930 if (Result.Val) return Result;
932 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
933 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
934 if (Result.Val) return Result;
940 SDOperand DAGCombiner::visitADDC(SDNode *N) {
941 SDOperand N0 = N->getOperand(0);
942 SDOperand N1 = N->getOperand(1);
943 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
944 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
945 MVT::ValueType VT = N0.getValueType();
947 // If the flag result is dead, turn this into an ADD.
948 if (N->hasNUsesOfValue(0, 1))
949 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
950 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
952 // canonicalize constant to RHS.
954 SDOperand Ops[] = { N1, N0 };
955 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
958 // fold (addc x, 0) -> x + no carry out
959 if (N1C && N1C->isNullValue())
960 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
962 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
963 uint64_t LHSZero, LHSOne;
964 uint64_t RHSZero, RHSOne;
965 uint64_t Mask = MVT::getIntVTBitMask(VT);
966 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
968 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
970 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
971 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
972 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
973 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
974 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
975 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
981 SDOperand DAGCombiner::visitADDE(SDNode *N) {
982 SDOperand N0 = N->getOperand(0);
983 SDOperand N1 = N->getOperand(1);
984 SDOperand CarryIn = N->getOperand(2);
985 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
986 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
987 //MVT::ValueType VT = N0.getValueType();
989 // canonicalize constant to RHS
991 SDOperand Ops[] = { N1, N0, CarryIn };
992 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
995 // fold (adde x, y, false) -> (addc x, y)
996 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
997 SDOperand Ops[] = { N1, N0 };
998 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1006 SDOperand DAGCombiner::visitSUB(SDNode *N) {
1007 SDOperand N0 = N->getOperand(0);
1008 SDOperand N1 = N->getOperand(1);
1009 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1010 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1011 MVT::ValueType VT = N0.getValueType();
1014 if (MVT::isVector(VT)) {
1015 SDOperand FoldedVOp = SimplifyVBinOp(N);
1016 if (FoldedVOp.Val) return FoldedVOp;
1019 // fold (sub x, x) -> 0
1021 return DAG.getConstant(0, N->getValueType(0));
1022 // fold (sub c1, c2) -> c1-c2
1024 return DAG.getNode(ISD::SUB, VT, N0, N1);
1025 // fold (sub x, c) -> (add x, -c)
1027 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
1028 // fold (A+B)-A -> B
1029 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1030 return N0.getOperand(1);
1031 // fold (A+B)-B -> A
1032 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1033 return N0.getOperand(0);
1034 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1035 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1036 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1037 if (Result.Val) return Result;
1039 // If either operand of a sub is undef, the result is undef
1040 if (N0.getOpcode() == ISD::UNDEF)
1042 if (N1.getOpcode() == ISD::UNDEF)
1048 SDOperand DAGCombiner::visitMUL(SDNode *N) {
1049 SDOperand N0 = N->getOperand(0);
1050 SDOperand N1 = N->getOperand(1);
1051 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1052 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1053 MVT::ValueType VT = N0.getValueType();
1056 if (MVT::isVector(VT)) {
1057 SDOperand FoldedVOp = SimplifyVBinOp(N);
1058 if (FoldedVOp.Val) return FoldedVOp;
1061 // fold (mul x, undef) -> 0
1062 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1063 return DAG.getConstant(0, VT);
1064 // fold (mul c1, c2) -> c1*c2
1066 return DAG.getNode(ISD::MUL, VT, N0, N1);
1067 // canonicalize constant to RHS
1069 return DAG.getNode(ISD::MUL, VT, N1, N0);
1070 // fold (mul x, 0) -> 0
1071 if (N1C && N1C->isNullValue())
1073 // fold (mul x, -1) -> 0-x
1074 if (N1C && N1C->isAllOnesValue())
1075 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1076 // fold (mul x, (1 << c)) -> x << c
1077 if (N1C && isPowerOf2_64(N1C->getValue()))
1078 return DAG.getNode(ISD::SHL, VT, N0,
1079 DAG.getConstant(Log2_64(N1C->getValue()),
1080 TLI.getShiftAmountTy()));
1081 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1082 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1083 // FIXME: If the input is something that is easily negated (e.g. a
1084 // single-use add), we should put the negate there.
1085 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1086 DAG.getNode(ISD::SHL, VT, N0,
1087 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1088 TLI.getShiftAmountTy())));
1091 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1092 if (N1C && N0.getOpcode() == ISD::SHL &&
1093 isa<ConstantSDNode>(N0.getOperand(1))) {
1094 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1095 AddToWorkList(C3.Val);
1096 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1099 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1102 SDOperand Sh(0,0), Y(0,0);
1103 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1104 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1105 N0.Val->hasOneUse()) {
1107 } else if (N1.getOpcode() == ISD::SHL &&
1108 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
1112 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1113 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1116 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1117 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1118 isa<ConstantSDNode>(N0.getOperand(1))) {
1119 return DAG.getNode(ISD::ADD, VT,
1120 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1121 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1125 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
1132 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
1133 SDOperand N0 = N->getOperand(0);
1134 SDOperand N1 = N->getOperand(1);
1135 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1136 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1137 MVT::ValueType VT = N->getValueType(0);
1140 if (MVT::isVector(VT)) {
1141 SDOperand FoldedVOp = SimplifyVBinOp(N);
1142 if (FoldedVOp.Val) return FoldedVOp;
1145 // fold (sdiv c1, c2) -> c1/c2
1146 if (N0C && N1C && !N1C->isNullValue())
1147 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1148 // fold (sdiv X, 1) -> X
1149 if (N1C && N1C->getSignExtended() == 1LL)
1151 // fold (sdiv X, -1) -> 0-X
1152 if (N1C && N1C->isAllOnesValue())
1153 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1154 // If we know the sign bits of both operands are zero, strength reduce to a
1155 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1156 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1157 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1158 DAG.MaskedValueIsZero(N0, SignBit))
1159 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1160 // fold (sdiv X, pow2) -> simple ops after legalize
1161 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
1162 (isPowerOf2_64(N1C->getSignExtended()) ||
1163 isPowerOf2_64(-N1C->getSignExtended()))) {
1164 // If dividing by powers of two is cheap, then don't perform the following
1166 if (TLI.isPow2DivCheap())
1168 int64_t pow2 = N1C->getSignExtended();
1169 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1170 unsigned lg2 = Log2_64(abs2);
1171 // Splat the sign bit into the register
1172 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1173 DAG.getConstant(MVT::getSizeInBits(VT)-1,
1174 TLI.getShiftAmountTy()));
1175 AddToWorkList(SGN.Val);
1176 // Add (N0 < 0) ? abs2 - 1 : 0;
1177 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1178 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
1179 TLI.getShiftAmountTy()));
1180 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1181 AddToWorkList(SRL.Val);
1182 AddToWorkList(ADD.Val); // Divide by pow2
1183 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
1184 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1185 // If we're dividing by a positive value, we're done. Otherwise, we must
1186 // negate the result.
1189 AddToWorkList(SRA.Val);
1190 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1192 // if integer divide is expensive and we satisfy the requirements, emit an
1193 // alternate sequence.
1194 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1195 !TLI.isIntDivCheap()) {
1196 SDOperand Op = BuildSDIV(N);
1197 if (Op.Val) return Op;
1201 if (N0.getOpcode() == ISD::UNDEF)
1202 return DAG.getConstant(0, VT);
1203 // X / undef -> undef
1204 if (N1.getOpcode() == ISD::UNDEF)
1210 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
1211 SDOperand N0 = N->getOperand(0);
1212 SDOperand N1 = N->getOperand(1);
1213 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1214 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1215 MVT::ValueType VT = N->getValueType(0);
1218 if (MVT::isVector(VT)) {
1219 SDOperand FoldedVOp = SimplifyVBinOp(N);
1220 if (FoldedVOp.Val) return FoldedVOp;
1223 // fold (udiv c1, c2) -> c1/c2
1224 if (N0C && N1C && !N1C->isNullValue())
1225 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1226 // fold (udiv x, (1 << c)) -> x >>u c
1227 if (N1C && isPowerOf2_64(N1C->getValue()))
1228 return DAG.getNode(ISD::SRL, VT, N0,
1229 DAG.getConstant(Log2_64(N1C->getValue()),
1230 TLI.getShiftAmountTy()));
1231 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1232 if (N1.getOpcode() == ISD::SHL) {
1233 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1234 if (isPowerOf2_64(SHC->getValue())) {
1235 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1236 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1237 DAG.getConstant(Log2_64(SHC->getValue()),
1239 AddToWorkList(Add.Val);
1240 return DAG.getNode(ISD::SRL, VT, N0, Add);
1244 // fold (udiv x, c) -> alternate
1245 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1246 SDOperand Op = BuildUDIV(N);
1247 if (Op.Val) return Op;
1251 if (N0.getOpcode() == ISD::UNDEF)
1252 return DAG.getConstant(0, VT);
1253 // X / undef -> undef
1254 if (N1.getOpcode() == ISD::UNDEF)
1260 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1261 SDOperand N0 = N->getOperand(0);
1262 SDOperand N1 = N->getOperand(1);
1263 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1264 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1265 MVT::ValueType VT = N->getValueType(0);
1267 // fold (srem c1, c2) -> c1%c2
1268 if (N0C && N1C && !N1C->isNullValue())
1269 return DAG.getNode(ISD::SREM, VT, N0, N1);
1270 // If we know the sign bits of both operands are zero, strength reduce to a
1271 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1272 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1273 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1274 DAG.MaskedValueIsZero(N0, SignBit))
1275 return DAG.getNode(ISD::UREM, VT, N0, N1);
1277 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1278 // the remainder operation.
1279 if (N1C && !N1C->isNullValue()) {
1280 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1281 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1282 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1283 AddToWorkList(Div.Val);
1284 AddToWorkList(Mul.Val);
1289 if (N0.getOpcode() == ISD::UNDEF)
1290 return DAG.getConstant(0, VT);
1291 // X % undef -> undef
1292 if (N1.getOpcode() == ISD::UNDEF)
1298 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1299 SDOperand N0 = N->getOperand(0);
1300 SDOperand N1 = N->getOperand(1);
1301 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1302 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1303 MVT::ValueType VT = N->getValueType(0);
1305 // fold (urem c1, c2) -> c1%c2
1306 if (N0C && N1C && !N1C->isNullValue())
1307 return DAG.getNode(ISD::UREM, VT, N0, N1);
1308 // fold (urem x, pow2) -> (and x, pow2-1)
1309 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1310 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1311 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1312 if (N1.getOpcode() == ISD::SHL) {
1313 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1314 if (isPowerOf2_64(SHC->getValue())) {
1315 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1316 AddToWorkList(Add.Val);
1317 return DAG.getNode(ISD::AND, VT, N0, Add);
1322 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1323 // the remainder operation.
1324 if (N1C && !N1C->isNullValue()) {
1325 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1326 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1327 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1328 AddToWorkList(Div.Val);
1329 AddToWorkList(Mul.Val);
1334 if (N0.getOpcode() == ISD::UNDEF)
1335 return DAG.getConstant(0, VT);
1336 // X % undef -> undef
1337 if (N1.getOpcode() == ISD::UNDEF)
1343 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1344 SDOperand N0 = N->getOperand(0);
1345 SDOperand N1 = N->getOperand(1);
1346 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1347 MVT::ValueType VT = N->getValueType(0);
1349 // fold (mulhs x, 0) -> 0
1350 if (N1C && N1C->isNullValue())
1352 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1353 if (N1C && N1C->getValue() == 1)
1354 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1355 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1356 TLI.getShiftAmountTy()));
1357 // fold (mulhs x, undef) -> 0
1358 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1359 return DAG.getConstant(0, VT);
1364 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1365 SDOperand N0 = N->getOperand(0);
1366 SDOperand N1 = N->getOperand(1);
1367 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1368 MVT::ValueType VT = N->getValueType(0);
1370 // fold (mulhu x, 0) -> 0
1371 if (N1C && N1C->isNullValue())
1373 // fold (mulhu x, 1) -> 0
1374 if (N1C && N1C->getValue() == 1)
1375 return DAG.getConstant(0, N0.getValueType());
1376 // fold (mulhu x, undef) -> 0
1377 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1378 return DAG.getConstant(0, VT);
1383 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1384 /// two operands of the same opcode, try to simplify it.
1385 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1386 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1387 MVT::ValueType VT = N0.getValueType();
1388 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1390 // For each of OP in AND/OR/XOR:
1391 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1392 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1393 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1394 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1395 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1396 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1397 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1398 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1399 N0.getOperand(0).getValueType(),
1400 N0.getOperand(0), N1.getOperand(0));
1401 AddToWorkList(ORNode.Val);
1402 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1405 // For each of OP in SHL/SRL/SRA/AND...
1406 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1407 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1408 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1409 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1410 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1411 N0.getOperand(1) == N1.getOperand(1)) {
1412 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1413 N0.getOperand(0).getValueType(),
1414 N0.getOperand(0), N1.getOperand(0));
1415 AddToWorkList(ORNode.Val);
1416 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1422 SDOperand DAGCombiner::visitAND(SDNode *N) {
1423 SDOperand N0 = N->getOperand(0);
1424 SDOperand N1 = N->getOperand(1);
1425 SDOperand LL, LR, RL, RR, CC0, CC1;
1426 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1427 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1428 MVT::ValueType VT = N1.getValueType();
1431 if (MVT::isVector(VT)) {
1432 SDOperand FoldedVOp = SimplifyVBinOp(N);
1433 if (FoldedVOp.Val) return FoldedVOp;
1436 // fold (and x, undef) -> 0
1437 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1438 return DAG.getConstant(0, VT);
1439 // fold (and c1, c2) -> c1&c2
1441 return DAG.getNode(ISD::AND, VT, N0, N1);
1442 // canonicalize constant to RHS
1444 return DAG.getNode(ISD::AND, VT, N1, N0);
1445 // fold (and x, -1) -> x
1446 if (N1C && N1C->isAllOnesValue())
1448 // if (and x, c) is known to be zero, return 0
1449 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1450 return DAG.getConstant(0, VT);
1452 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1455 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1456 if (N1C && N0.getOpcode() == ISD::OR)
1457 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1458 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1460 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1461 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1462 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1463 if (DAG.MaskedValueIsZero(N0.getOperand(0),
1464 ~N1C->getValue() & InMask)) {
1465 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1468 // Replace uses of the AND with uses of the Zero extend node.
1471 // We actually want to replace all uses of the any_extend with the
1472 // zero_extend, to avoid duplicating things. This will later cause this
1473 // AND to be folded.
1474 CombineTo(N0.Val, Zext);
1475 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1478 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1479 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1480 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1481 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1483 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1484 MVT::isInteger(LL.getValueType())) {
1485 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1486 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1487 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1488 AddToWorkList(ORNode.Val);
1489 return DAG.getSetCC(VT, ORNode, LR, Op1);
1491 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1492 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1493 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1494 AddToWorkList(ANDNode.Val);
1495 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1497 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1498 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1499 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1500 AddToWorkList(ORNode.Val);
1501 return DAG.getSetCC(VT, ORNode, LR, Op1);
1504 // canonicalize equivalent to ll == rl
1505 if (LL == RR && LR == RL) {
1506 Op1 = ISD::getSetCCSwappedOperands(Op1);
1509 if (LL == RL && LR == RR) {
1510 bool isInteger = MVT::isInteger(LL.getValueType());
1511 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1512 if (Result != ISD::SETCC_INVALID)
1513 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1517 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1518 if (N0.getOpcode() == N1.getOpcode()) {
1519 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1520 if (Tmp.Val) return Tmp;
1523 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1524 // fold (and (sra)) -> (and (srl)) when possible.
1525 if (!MVT::isVector(VT) &&
1526 SimplifyDemandedBits(SDOperand(N, 0)))
1527 return SDOperand(N, 0);
1528 // fold (zext_inreg (extload x)) -> (zextload x)
1529 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1530 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1531 MVT::ValueType EVT = LN0->getLoadedVT();
1532 // If we zero all the possible extended bits, then we can turn this into
1533 // a zextload if we are running before legalize or the operation is legal.
1534 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1535 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1536 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1537 LN0->getBasePtr(), LN0->getSrcValue(),
1538 LN0->getSrcValueOffset(), EVT,
1540 LN0->getAlignment());
1542 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1543 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1546 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1547 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1549 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1550 MVT::ValueType EVT = LN0->getLoadedVT();
1551 // If we zero all the possible extended bits, then we can turn this into
1552 // a zextload if we are running before legalize or the operation is legal.
1553 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1554 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1555 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1556 LN0->getBasePtr(), LN0->getSrcValue(),
1557 LN0->getSrcValueOffset(), EVT,
1559 LN0->getAlignment());
1561 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1562 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1566 // fold (and (load x), 255) -> (zextload x, i8)
1567 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1568 if (N1C && N0.getOpcode() == ISD::LOAD) {
1569 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1570 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1571 LN0->getAddressingMode() == ISD::UNINDEXED &&
1573 MVT::ValueType EVT, LoadedVT;
1574 if (N1C->getValue() == 255)
1576 else if (N1C->getValue() == 65535)
1578 else if (N1C->getValue() == ~0U)
1583 LoadedVT = LN0->getLoadedVT();
1584 if (EVT != MVT::Other && LoadedVT > EVT &&
1585 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1586 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1587 // For big endian targets, we need to add an offset to the pointer to
1588 // load the correct bytes. For little endian systems, we merely need to
1589 // read fewer bytes from the same pointer.
1591 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1592 SDOperand NewPtr = LN0->getBasePtr();
1593 if (!TLI.isLittleEndian())
1594 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1595 DAG.getConstant(PtrOff, PtrType));
1596 AddToWorkList(NewPtr.Val);
1598 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1599 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1600 LN0->isVolatile(), LN0->getAlignment());
1602 CombineTo(N0.Val, Load, Load.getValue(1));
1603 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1611 SDOperand DAGCombiner::visitOR(SDNode *N) {
1612 SDOperand N0 = N->getOperand(0);
1613 SDOperand N1 = N->getOperand(1);
1614 SDOperand LL, LR, RL, RR, CC0, CC1;
1615 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1616 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1617 MVT::ValueType VT = N1.getValueType();
1618 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1621 if (MVT::isVector(VT)) {
1622 SDOperand FoldedVOp = SimplifyVBinOp(N);
1623 if (FoldedVOp.Val) return FoldedVOp;
1626 // fold (or x, undef) -> -1
1627 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1628 return DAG.getConstant(~0ULL, VT);
1629 // fold (or c1, c2) -> c1|c2
1631 return DAG.getNode(ISD::OR, VT, N0, N1);
1632 // canonicalize constant to RHS
1634 return DAG.getNode(ISD::OR, VT, N1, N0);
1635 // fold (or x, 0) -> x
1636 if (N1C && N1C->isNullValue())
1638 // fold (or x, -1) -> -1
1639 if (N1C && N1C->isAllOnesValue())
1641 // fold (or x, c) -> c iff (x & ~c) == 0
1643 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1646 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1649 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1650 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1651 isa<ConstantSDNode>(N0.getOperand(1))) {
1652 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1653 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1655 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1657 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1658 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1659 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1660 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1662 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1663 MVT::isInteger(LL.getValueType())) {
1664 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1665 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1666 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1667 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1668 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1669 AddToWorkList(ORNode.Val);
1670 return DAG.getSetCC(VT, ORNode, LR, Op1);
1672 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1673 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1674 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1675 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1676 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1677 AddToWorkList(ANDNode.Val);
1678 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1681 // canonicalize equivalent to ll == rl
1682 if (LL == RR && LR == RL) {
1683 Op1 = ISD::getSetCCSwappedOperands(Op1);
1686 if (LL == RL && LR == RR) {
1687 bool isInteger = MVT::isInteger(LL.getValueType());
1688 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1689 if (Result != ISD::SETCC_INVALID)
1690 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1694 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1695 if (N0.getOpcode() == N1.getOpcode()) {
1696 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1697 if (Tmp.Val) return Tmp;
1700 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1701 if (N0.getOpcode() == ISD::AND &&
1702 N1.getOpcode() == ISD::AND &&
1703 N0.getOperand(1).getOpcode() == ISD::Constant &&
1704 N1.getOperand(1).getOpcode() == ISD::Constant &&
1705 // Don't increase # computations.
1706 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1707 // We can only do this xform if we know that bits from X that are set in C2
1708 // but not in C1 are already zero. Likewise for Y.
1709 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1710 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1712 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1713 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1714 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1715 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1720 // See if this is some rotate idiom.
1721 if (SDNode *Rot = MatchRotate(N0, N1))
1722 return SDOperand(Rot, 0);
1728 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1729 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1730 if (Op.getOpcode() == ISD::AND) {
1731 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1732 Mask = Op.getOperand(1);
1733 Op = Op.getOperand(0);
1739 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1747 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1748 // idioms for rotate, and if the target supports rotation instructions, generate
1750 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1751 // Must be a legal type. Expanded an promoted things won't work with rotates.
1752 MVT::ValueType VT = LHS.getValueType();
1753 if (!TLI.isTypeLegal(VT)) return 0;
1755 // The target must have at least one rotate flavor.
1756 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1757 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1758 if (!HasROTL && !HasROTR) return 0;
1760 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1761 SDOperand LHSShift; // The shift.
1762 SDOperand LHSMask; // AND value if any.
1763 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1764 return 0; // Not part of a rotate.
1766 SDOperand RHSShift; // The shift.
1767 SDOperand RHSMask; // AND value if any.
1768 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1769 return 0; // Not part of a rotate.
1771 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1772 return 0; // Not shifting the same value.
1774 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1775 return 0; // Shifts must disagree.
1777 // Canonicalize shl to left side in a shl/srl pair.
1778 if (RHSShift.getOpcode() == ISD::SHL) {
1779 std::swap(LHS, RHS);
1780 std::swap(LHSShift, RHSShift);
1781 std::swap(LHSMask , RHSMask );
1784 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1785 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1786 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1787 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1789 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1790 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1791 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1792 RHSShiftAmt.getOpcode() == ISD::Constant) {
1793 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1794 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1795 if ((LShVal + RShVal) != OpSizeInBits)
1800 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1802 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1804 // If there is an AND of either shifted operand, apply it to the result.
1805 if (LHSMask.Val || RHSMask.Val) {
1806 uint64_t Mask = MVT::getIntVTBitMask(VT);
1809 uint64_t RHSBits = (1ULL << LShVal)-1;
1810 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1813 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1814 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1817 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1823 // If there is a mask here, and we have a variable shift, we can't be sure
1824 // that we're masking out the right stuff.
1825 if (LHSMask.Val || RHSMask.Val)
1828 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1829 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1830 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1831 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1832 if (ConstantSDNode *SUBC =
1833 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1834 if (SUBC->getValue() == OpSizeInBits)
1836 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1838 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1842 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1843 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1844 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
1845 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
1846 if (ConstantSDNode *SUBC =
1847 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
1848 if (SUBC->getValue() == OpSizeInBits)
1850 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1852 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1856 // Look for sign/zext/any-extended cases:
1857 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1858 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1859 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
1860 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1861 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1862 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
1863 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
1864 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
1865 if (RExtOp0.getOpcode() == ISD::SUB &&
1866 RExtOp0.getOperand(1) == LExtOp0) {
1867 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1869 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1870 // (rotl x, (sub 32, y))
1871 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
1872 if (SUBC->getValue() == OpSizeInBits) {
1874 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1876 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1879 } else if (LExtOp0.getOpcode() == ISD::SUB &&
1880 RExtOp0 == LExtOp0.getOperand(1)) {
1881 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
1883 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
1884 // (rotr x, (sub 32, y))
1885 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
1886 if (SUBC->getValue() == OpSizeInBits) {
1888 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
1890 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1900 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1901 SDOperand N0 = N->getOperand(0);
1902 SDOperand N1 = N->getOperand(1);
1903 SDOperand LHS, RHS, CC;
1904 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1905 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1906 MVT::ValueType VT = N0.getValueType();
1909 if (MVT::isVector(VT)) {
1910 SDOperand FoldedVOp = SimplifyVBinOp(N);
1911 if (FoldedVOp.Val) return FoldedVOp;
1914 // fold (xor x, undef) -> undef
1915 if (N0.getOpcode() == ISD::UNDEF)
1917 if (N1.getOpcode() == ISD::UNDEF)
1919 // fold (xor c1, c2) -> c1^c2
1921 return DAG.getNode(ISD::XOR, VT, N0, N1);
1922 // canonicalize constant to RHS
1924 return DAG.getNode(ISD::XOR, VT, N1, N0);
1925 // fold (xor x, 0) -> x
1926 if (N1C && N1C->isNullValue())
1929 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1932 // fold !(x cc y) -> (x !cc y)
1933 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1934 bool isInt = MVT::isInteger(LHS.getValueType());
1935 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1937 if (N0.getOpcode() == ISD::SETCC)
1938 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1939 if (N0.getOpcode() == ISD::SELECT_CC)
1940 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1941 assert(0 && "Unhandled SetCC Equivalent!");
1944 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
1945 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
1946 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
1947 SDOperand V = N0.getOperand(0);
1948 V = DAG.getNode(ISD::XOR, V.getValueType(), V,
1949 DAG.getConstant(V.getValueType(), 1));
1950 AddToWorkList(V.Val);
1951 return DAG.getNode(ISD::ZERO_EXTEND, VT, V);
1954 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1955 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
1956 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1957 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1958 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1959 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1960 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1961 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1962 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1963 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1966 // fold !(x or y) -> (!x and !y) iff x or y are constants
1967 if (N1C && N1C->isAllOnesValue() &&
1968 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1969 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1970 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1971 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1972 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1973 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1974 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1975 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1978 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1979 if (N1C && N0.getOpcode() == ISD::XOR) {
1980 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1981 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1983 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1984 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1986 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1987 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1989 // fold (xor x, x) -> 0
1991 if (!MVT::isVector(VT)) {
1992 return DAG.getConstant(0, VT);
1993 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1994 // Produce a vector of zeros.
1995 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
1996 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1997 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2001 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2002 if (N0.getOpcode() == N1.getOpcode()) {
2003 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2004 if (Tmp.Val) return Tmp;
2007 // Simplify the expression using non-local knowledge.
2008 if (!MVT::isVector(VT) &&
2009 SimplifyDemandedBits(SDOperand(N, 0)))
2010 return SDOperand(N, 0);
2015 SDOperand DAGCombiner::visitSHL(SDNode *N) {
2016 SDOperand N0 = N->getOperand(0);
2017 SDOperand N1 = N->getOperand(1);
2018 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2019 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2020 MVT::ValueType VT = N0.getValueType();
2021 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2023 // fold (shl c1, c2) -> c1<<c2
2025 return DAG.getNode(ISD::SHL, VT, N0, N1);
2026 // fold (shl 0, x) -> 0
2027 if (N0C && N0C->isNullValue())
2029 // fold (shl x, c >= size(x)) -> undef
2030 if (N1C && N1C->getValue() >= OpSizeInBits)
2031 return DAG.getNode(ISD::UNDEF, VT);
2032 // fold (shl x, 0) -> x
2033 if (N1C && N1C->isNullValue())
2035 // if (shl x, c) is known to be zero, return 0
2036 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
2037 return DAG.getConstant(0, VT);
2038 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2039 return SDOperand(N, 0);
2040 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2041 if (N1C && N0.getOpcode() == ISD::SHL &&
2042 N0.getOperand(1).getOpcode() == ISD::Constant) {
2043 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2044 uint64_t c2 = N1C->getValue();
2045 if (c1 + c2 > OpSizeInBits)
2046 return DAG.getConstant(0, VT);
2047 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2048 DAG.getConstant(c1 + c2, N1.getValueType()));
2050 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2051 // (srl (and x, -1 << c1), c1-c2)
2052 if (N1C && N0.getOpcode() == ISD::SRL &&
2053 N0.getOperand(1).getOpcode() == ISD::Constant) {
2054 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2055 uint64_t c2 = N1C->getValue();
2056 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2057 DAG.getConstant(~0ULL << c1, VT));
2059 return DAG.getNode(ISD::SHL, VT, Mask,
2060 DAG.getConstant(c2-c1, N1.getValueType()));
2062 return DAG.getNode(ISD::SRL, VT, Mask,
2063 DAG.getConstant(c1-c2, N1.getValueType()));
2065 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2066 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2067 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2068 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2072 SDOperand DAGCombiner::visitSRA(SDNode *N) {
2073 SDOperand N0 = N->getOperand(0);
2074 SDOperand N1 = N->getOperand(1);
2075 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2076 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2077 MVT::ValueType VT = N0.getValueType();
2079 // fold (sra c1, c2) -> c1>>c2
2081 return DAG.getNode(ISD::SRA, VT, N0, N1);
2082 // fold (sra 0, x) -> 0
2083 if (N0C && N0C->isNullValue())
2085 // fold (sra -1, x) -> -1
2086 if (N0C && N0C->isAllOnesValue())
2088 // fold (sra x, c >= size(x)) -> undef
2089 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
2090 return DAG.getNode(ISD::UNDEF, VT);
2091 // fold (sra x, 0) -> x
2092 if (N1C && N1C->isNullValue())
2094 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2096 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2097 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
2100 default: EVT = MVT::Other; break;
2101 case 1: EVT = MVT::i1; break;
2102 case 8: EVT = MVT::i8; break;
2103 case 16: EVT = MVT::i16; break;
2104 case 32: EVT = MVT::i32; break;
2106 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2107 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2108 DAG.getValueType(EVT));
2111 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2112 if (N1C && N0.getOpcode() == ISD::SRA) {
2113 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2114 unsigned Sum = N1C->getValue() + C1->getValue();
2115 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
2116 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2117 DAG.getConstant(Sum, N1C->getValueType(0)));
2121 // Simplify, based on bits shifted out of the LHS.
2122 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2123 return SDOperand(N, 0);
2126 // If the sign bit is known to be zero, switch this to a SRL.
2127 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
2128 return DAG.getNode(ISD::SRL, VT, N0, N1);
2132 SDOperand DAGCombiner::visitSRL(SDNode *N) {
2133 SDOperand N0 = N->getOperand(0);
2134 SDOperand N1 = N->getOperand(1);
2135 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2136 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2137 MVT::ValueType VT = N0.getValueType();
2138 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2140 // fold (srl c1, c2) -> c1 >>u c2
2142 return DAG.getNode(ISD::SRL, VT, N0, N1);
2143 // fold (srl 0, x) -> 0
2144 if (N0C && N0C->isNullValue())
2146 // fold (srl x, c >= size(x)) -> undef
2147 if (N1C && N1C->getValue() >= OpSizeInBits)
2148 return DAG.getNode(ISD::UNDEF, VT);
2149 // fold (srl x, 0) -> x
2150 if (N1C && N1C->isNullValue())
2152 // if (srl x, c) is known to be zero, return 0
2153 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
2154 return DAG.getConstant(0, VT);
2156 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2157 if (N1C && N0.getOpcode() == ISD::SRL &&
2158 N0.getOperand(1).getOpcode() == ISD::Constant) {
2159 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2160 uint64_t c2 = N1C->getValue();
2161 if (c1 + c2 > OpSizeInBits)
2162 return DAG.getConstant(0, VT);
2163 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2164 DAG.getConstant(c1 + c2, N1.getValueType()));
2167 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2168 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2169 // Shifting in all undef bits?
2170 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
2171 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
2172 return DAG.getNode(ISD::UNDEF, VT);
2174 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2175 AddToWorkList(SmallShift.Val);
2176 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2179 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2180 // bit, which is unmodified by sra.
2181 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
2182 if (N0.getOpcode() == ISD::SRA)
2183 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2186 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2187 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2188 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
2189 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
2190 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2192 // If any of the input bits are KnownOne, then the input couldn't be all
2193 // zeros, thus the result of the srl will always be zero.
2194 if (KnownOne) return DAG.getConstant(0, VT);
2196 // If all of the bits input the to ctlz node are known to be zero, then
2197 // the result of the ctlz is "32" and the result of the shift is one.
2198 uint64_t UnknownBits = ~KnownZero & Mask;
2199 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2201 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2202 if ((UnknownBits & (UnknownBits-1)) == 0) {
2203 // Okay, we know that only that the single bit specified by UnknownBits
2204 // could be set on input to the CTLZ node. If this bit is set, the SRL
2205 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2206 // to an SRL,XOR pair, which is likely to simplify more.
2207 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
2208 SDOperand Op = N0.getOperand(0);
2210 Op = DAG.getNode(ISD::SRL, VT, Op,
2211 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2212 AddToWorkList(Op.Val);
2214 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2218 // fold operands of srl based on knowledge that the low bits are not
2220 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2221 return SDOperand(N, 0);
2226 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
2227 SDOperand N0 = N->getOperand(0);
2228 MVT::ValueType VT = N->getValueType(0);
2230 // fold (ctlz c1) -> c2
2231 if (isa<ConstantSDNode>(N0))
2232 return DAG.getNode(ISD::CTLZ, VT, N0);
2236 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
2237 SDOperand N0 = N->getOperand(0);
2238 MVT::ValueType VT = N->getValueType(0);
2240 // fold (cttz c1) -> c2
2241 if (isa<ConstantSDNode>(N0))
2242 return DAG.getNode(ISD::CTTZ, VT, N0);
2246 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
2247 SDOperand N0 = N->getOperand(0);
2248 MVT::ValueType VT = N->getValueType(0);
2250 // fold (ctpop c1) -> c2
2251 if (isa<ConstantSDNode>(N0))
2252 return DAG.getNode(ISD::CTPOP, VT, N0);
2256 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
2257 SDOperand N0 = N->getOperand(0);
2258 SDOperand N1 = N->getOperand(1);
2259 SDOperand N2 = N->getOperand(2);
2260 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2261 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2262 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2263 MVT::ValueType VT = N->getValueType(0);
2264 MVT::ValueType VT0 = N0.getValueType();
2266 // fold select C, X, X -> X
2269 // fold select true, X, Y -> X
2270 if (N0C && !N0C->isNullValue())
2272 // fold select false, X, Y -> Y
2273 if (N0C && N0C->isNullValue())
2275 // fold select C, 1, X -> C | X
2276 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
2277 return DAG.getNode(ISD::OR, VT, N0, N2);
2278 // fold select C, 0, 1 -> ~C
2279 if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
2280 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) {
2281 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
2284 AddToWorkList(XORNode.Val);
2285 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0))
2286 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
2287 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
2289 // fold select C, 0, X -> ~C & X
2290 if (VT == VT0 && N1C && N1C->isNullValue()) {
2291 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2292 AddToWorkList(XORNode.Val);
2293 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2295 // fold select C, X, 1 -> ~C | X
2296 if (VT == VT0 && N2C && N2C->getValue() == 1) {
2297 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2298 AddToWorkList(XORNode.Val);
2299 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2301 // fold select C, X, 0 -> C & X
2302 // FIXME: this should check for C type == X type, not i1?
2303 if (MVT::i1 == VT && N2C && N2C->isNullValue())
2304 return DAG.getNode(ISD::AND, VT, N0, N1);
2305 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2306 if (MVT::i1 == VT && N0 == N1)
2307 return DAG.getNode(ISD::OR, VT, N0, N2);
2308 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2309 if (MVT::i1 == VT && N0 == N2)
2310 return DAG.getNode(ISD::AND, VT, N0, N1);
2312 // If we can fold this based on the true/false value, do so.
2313 if (SimplifySelectOps(N, N1, N2))
2314 return SDOperand(N, 0); // Don't revisit N.
2316 // fold selects based on a setcc into other things, such as min/max/abs
2317 if (N0.getOpcode() == ISD::SETCC)
2319 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2320 // having to say they don't support SELECT_CC on every type the DAG knows
2321 // about, since there is no way to mark an opcode illegal at all value types
2322 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2323 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2324 N1, N2, N0.getOperand(2));
2326 return SimplifySelect(N0, N1, N2);
2330 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2331 SDOperand N0 = N->getOperand(0);
2332 SDOperand N1 = N->getOperand(1);
2333 SDOperand N2 = N->getOperand(2);
2334 SDOperand N3 = N->getOperand(3);
2335 SDOperand N4 = N->getOperand(4);
2336 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2338 // fold select_cc lhs, rhs, x, x, cc -> x
2342 // Determine if the condition we're dealing with is constant
2343 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2344 if (SCC.Val) AddToWorkList(SCC.Val);
2346 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2347 if (SCCC->getValue())
2348 return N2; // cond always true -> true val
2350 return N3; // cond always false -> false val
2353 // Fold to a simpler select_cc
2354 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2355 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2356 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2359 // If we can fold this based on the true/false value, do so.
2360 if (SimplifySelectOps(N, N2, N3))
2361 return SDOperand(N, 0); // Don't revisit N.
2363 // fold select_cc into other things, such as min/max/abs
2364 return SimplifySelectCC(N0, N1, N2, N3, CC);
2367 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2368 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2369 cast<CondCodeSDNode>(N->getOperand(2))->get());
2372 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2373 SDOperand N0 = N->getOperand(0);
2374 MVT::ValueType VT = N->getValueType(0);
2376 // fold (sext c1) -> c1
2377 if (isa<ConstantSDNode>(N0))
2378 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2380 // fold (sext (sext x)) -> (sext x)
2381 // fold (sext (aext x)) -> (sext x)
2382 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2383 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2385 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2386 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2387 if (N0.getOpcode() == ISD::TRUNCATE) {
2388 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2389 if (NarrowLoad.Val) {
2390 if (NarrowLoad.Val != N0.Val)
2391 CombineTo(N0.Val, NarrowLoad);
2392 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2396 // See if the value being truncated is already sign extended. If so, just
2397 // eliminate the trunc/sext pair.
2398 if (N0.getOpcode() == ISD::TRUNCATE) {
2399 SDOperand Op = N0.getOperand(0);
2400 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2401 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2402 unsigned DestBits = MVT::getSizeInBits(VT);
2403 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2405 if (OpBits == DestBits) {
2406 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2407 // bits, it is already ready.
2408 if (NumSignBits > DestBits-MidBits)
2410 } else if (OpBits < DestBits) {
2411 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2412 // bits, just sext from i32.
2413 if (NumSignBits > OpBits-MidBits)
2414 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2416 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2417 // bits, just truncate to i32.
2418 if (NumSignBits > OpBits-MidBits)
2419 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2422 // fold (sext (truncate x)) -> (sextinreg x).
2423 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2424 N0.getValueType())) {
2425 if (Op.getValueType() < VT)
2426 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2427 else if (Op.getValueType() > VT)
2428 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2429 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2430 DAG.getValueType(N0.getValueType()));
2434 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2435 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2436 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2437 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2438 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2439 LN0->getBasePtr(), LN0->getSrcValue(),
2440 LN0->getSrcValueOffset(),
2443 LN0->getAlignment());
2444 CombineTo(N, ExtLoad);
2445 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2446 ExtLoad.getValue(1));
2447 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2450 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2451 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2452 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2453 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2454 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2455 MVT::ValueType EVT = LN0->getLoadedVT();
2456 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2457 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2458 LN0->getBasePtr(), LN0->getSrcValue(),
2459 LN0->getSrcValueOffset(), EVT,
2461 LN0->getAlignment());
2462 CombineTo(N, ExtLoad);
2463 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2464 ExtLoad.getValue(1));
2465 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2469 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2470 if (N0.getOpcode() == ISD::SETCC) {
2472 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2473 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2474 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2475 if (SCC.Val) return SCC;
2481 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2482 SDOperand N0 = N->getOperand(0);
2483 MVT::ValueType VT = N->getValueType(0);
2485 // fold (zext c1) -> c1
2486 if (isa<ConstantSDNode>(N0))
2487 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2488 // fold (zext (zext x)) -> (zext x)
2489 // fold (zext (aext x)) -> (zext x)
2490 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2491 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2493 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2494 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2495 if (N0.getOpcode() == ISD::TRUNCATE) {
2496 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2497 if (NarrowLoad.Val) {
2498 if (NarrowLoad.Val != N0.Val)
2499 CombineTo(N0.Val, NarrowLoad);
2500 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2504 // fold (zext (truncate x)) -> (and x, mask)
2505 if (N0.getOpcode() == ISD::TRUNCATE &&
2506 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2507 SDOperand Op = N0.getOperand(0);
2508 if (Op.getValueType() < VT) {
2509 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2510 } else if (Op.getValueType() > VT) {
2511 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2513 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2516 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2517 if (N0.getOpcode() == ISD::AND &&
2518 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2519 N0.getOperand(1).getOpcode() == ISD::Constant) {
2520 SDOperand X = N0.getOperand(0).getOperand(0);
2521 if (X.getValueType() < VT) {
2522 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2523 } else if (X.getValueType() > VT) {
2524 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2526 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2527 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2530 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2531 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2532 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2533 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2534 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2535 LN0->getBasePtr(), LN0->getSrcValue(),
2536 LN0->getSrcValueOffset(),
2539 LN0->getAlignment());
2540 CombineTo(N, ExtLoad);
2541 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2542 ExtLoad.getValue(1));
2543 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2546 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2547 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2548 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2549 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2550 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2551 MVT::ValueType EVT = LN0->getLoadedVT();
2552 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2553 LN0->getBasePtr(), LN0->getSrcValue(),
2554 LN0->getSrcValueOffset(), EVT,
2556 LN0->getAlignment());
2557 CombineTo(N, ExtLoad);
2558 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2559 ExtLoad.getValue(1));
2560 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2563 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2564 if (N0.getOpcode() == ISD::SETCC) {
2566 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2567 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2568 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2569 if (SCC.Val) return SCC;
2575 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2576 SDOperand N0 = N->getOperand(0);
2577 MVT::ValueType VT = N->getValueType(0);
2579 // fold (aext c1) -> c1
2580 if (isa<ConstantSDNode>(N0))
2581 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2582 // fold (aext (aext x)) -> (aext x)
2583 // fold (aext (zext x)) -> (zext x)
2584 // fold (aext (sext x)) -> (sext x)
2585 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2586 N0.getOpcode() == ISD::ZERO_EXTEND ||
2587 N0.getOpcode() == ISD::SIGN_EXTEND)
2588 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2590 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2591 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2592 if (N0.getOpcode() == ISD::TRUNCATE) {
2593 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2594 if (NarrowLoad.Val) {
2595 if (NarrowLoad.Val != N0.Val)
2596 CombineTo(N0.Val, NarrowLoad);
2597 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2601 // fold (aext (truncate x))
2602 if (N0.getOpcode() == ISD::TRUNCATE) {
2603 SDOperand TruncOp = N0.getOperand(0);
2604 if (TruncOp.getValueType() == VT)
2605 return TruncOp; // x iff x size == zext size.
2606 if (TruncOp.getValueType() > VT)
2607 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2608 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2611 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2612 if (N0.getOpcode() == ISD::AND &&
2613 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2614 N0.getOperand(1).getOpcode() == ISD::Constant) {
2615 SDOperand X = N0.getOperand(0).getOperand(0);
2616 if (X.getValueType() < VT) {
2617 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2618 } else if (X.getValueType() > VT) {
2619 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2621 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2622 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2625 // fold (aext (load x)) -> (aext (truncate (extload x)))
2626 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2627 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2628 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2629 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2630 LN0->getBasePtr(), LN0->getSrcValue(),
2631 LN0->getSrcValueOffset(),
2634 LN0->getAlignment());
2635 CombineTo(N, ExtLoad);
2636 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2637 ExtLoad.getValue(1));
2638 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2641 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2642 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2643 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2644 if (N0.getOpcode() == ISD::LOAD &&
2645 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2647 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2648 MVT::ValueType EVT = LN0->getLoadedVT();
2649 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2650 LN0->getChain(), LN0->getBasePtr(),
2652 LN0->getSrcValueOffset(), EVT,
2654 LN0->getAlignment());
2655 CombineTo(N, ExtLoad);
2656 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2657 ExtLoad.getValue(1));
2658 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2661 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2662 if (N0.getOpcode() == ISD::SETCC) {
2664 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2665 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2666 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2674 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
2675 /// bits and then truncated to a narrower type and where N is a multiple
2676 /// of number of bits of the narrower type, transform it to a narrower load
2677 /// from address + N / num of bits of new type. If the result is to be
2678 /// extended, also fold the extension to form a extending load.
2679 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
2680 unsigned Opc = N->getOpcode();
2681 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2682 SDOperand N0 = N->getOperand(0);
2683 MVT::ValueType VT = N->getValueType(0);
2684 MVT::ValueType EVT = N->getValueType(0);
2686 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
2688 if (Opc == ISD::SIGN_EXTEND_INREG) {
2689 ExtType = ISD::SEXTLOAD;
2690 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2691 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
2695 unsigned EVTBits = MVT::getSizeInBits(EVT);
2697 bool CombineSRL = false;
2698 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
2699 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2700 ShAmt = N01->getValue();
2701 // Is the shift amount a multiple of size of VT?
2702 if ((ShAmt & (EVTBits-1)) == 0) {
2703 N0 = N0.getOperand(0);
2704 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
2711 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2712 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
2713 // zero extended form: by shrinking the load, we lose track of the fact
2714 // that it is already zero extended.
2715 // FIXME: This should be reevaluated.
2717 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
2718 "Cannot truncate to larger type!");
2719 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2720 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2721 // For big endian targets, we need to adjust the offset to the pointer to
2722 // load the correct bytes.
2723 if (!TLI.isLittleEndian())
2724 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits;
2725 uint64_t PtrOff = ShAmt / 8;
2726 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2727 DAG.getConstant(PtrOff, PtrType));
2728 AddToWorkList(NewPtr.Val);
2729 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
2730 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
2731 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2732 LN0->isVolatile(), LN0->getAlignment())
2733 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
2734 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
2735 LN0->isVolatile(), LN0->getAlignment());
2738 std::vector<SDNode*> NowDead;
2739 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead);
2740 CombineTo(N->getOperand(0).Val, Load);
2742 CombineTo(N0.Val, Load, Load.getValue(1));
2744 if (Opc == ISD::SIGN_EXTEND_INREG)
2745 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
2747 return DAG.getNode(Opc, VT, Load);
2749 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2756 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2757 SDOperand N0 = N->getOperand(0);
2758 SDOperand N1 = N->getOperand(1);
2759 MVT::ValueType VT = N->getValueType(0);
2760 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2761 unsigned EVTBits = MVT::getSizeInBits(EVT);
2763 // fold (sext_in_reg c1) -> c1
2764 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2765 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2767 // If the input is already sign extended, just drop the extension.
2768 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2771 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2772 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2773 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2774 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2777 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
2778 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2779 return DAG.getZeroExtendInReg(N0, EVT);
2781 // fold operands of sext_in_reg based on knowledge that the top bits are not
2783 if (SimplifyDemandedBits(SDOperand(N, 0)))
2784 return SDOperand(N, 0);
2786 // fold (sext_in_reg (load x)) -> (smaller sextload x)
2787 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
2788 SDOperand NarrowLoad = ReduceLoadWidth(N);
2792 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2793 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2794 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2795 if (N0.getOpcode() == ISD::SRL) {
2796 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2797 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2798 // We can turn this into an SRA iff the input to the SRL is already sign
2800 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
2801 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2802 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2806 // fold (sext_inreg (extload x)) -> (sextload x)
2807 if (ISD::isEXTLoad(N0.Val) &&
2808 ISD::isUNINDEXEDLoad(N0.Val) &&
2809 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2810 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2811 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2812 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2813 LN0->getBasePtr(), LN0->getSrcValue(),
2814 LN0->getSrcValueOffset(), EVT,
2816 LN0->getAlignment());
2817 CombineTo(N, ExtLoad);
2818 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2819 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2821 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2822 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2824 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2825 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2826 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2827 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2828 LN0->getBasePtr(), LN0->getSrcValue(),
2829 LN0->getSrcValueOffset(), EVT,
2831 LN0->getAlignment());
2832 CombineTo(N, ExtLoad);
2833 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2834 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2839 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2840 SDOperand N0 = N->getOperand(0);
2841 MVT::ValueType VT = N->getValueType(0);
2844 if (N0.getValueType() == N->getValueType(0))
2846 // fold (truncate c1) -> c1
2847 if (isa<ConstantSDNode>(N0))
2848 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2849 // fold (truncate (truncate x)) -> (truncate x)
2850 if (N0.getOpcode() == ISD::TRUNCATE)
2851 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2852 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2853 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2854 N0.getOpcode() == ISD::ANY_EXTEND) {
2855 if (N0.getOperand(0).getValueType() < VT)
2856 // if the source is smaller than the dest, we still need an extend
2857 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2858 else if (N0.getOperand(0).getValueType() > VT)
2859 // if the source is larger than the dest, than we just need the truncate
2860 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2862 // if the source and dest are the same type, we can drop both the extend
2864 return N0.getOperand(0);
2867 // fold (truncate (load x)) -> (smaller load x)
2868 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
2869 return ReduceLoadWidth(N);
2872 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2873 SDOperand N0 = N->getOperand(0);
2874 MVT::ValueType VT = N->getValueType(0);
2876 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
2877 // Only do this before legalize, since afterward the target may be depending
2878 // on the bitconvert.
2879 // First check to see if this is all constant.
2880 if (!AfterLegalize &&
2881 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
2882 MVT::isVector(VT)) {
2883 bool isSimple = true;
2884 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
2885 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2886 N0.getOperand(i).getOpcode() != ISD::Constant &&
2887 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2892 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
2893 assert(!MVT::isVector(DestEltVT) &&
2894 "Element type of vector ValueType must not be vector!");
2896 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
2900 // If the input is a constant, let getNode() fold it.
2901 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2902 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2903 if (Res.Val != N) return Res;
2906 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2907 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2909 // fold (conv (load x)) -> (load (conv*)x)
2910 // If the resultant load doesn't need a higher alignment than the original!
2911 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2912 ISD::isUNINDEXEDLoad(N0.Val) &&
2913 TLI.isOperationLegal(ISD::LOAD, VT)) {
2914 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2915 unsigned Align = TLI.getTargetMachine().getTargetData()->
2916 getABITypeAlignment(MVT::getTypeForValueType(VT));
2917 unsigned OrigAlign = LN0->getAlignment();
2918 if (Align <= OrigAlign) {
2919 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2920 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2921 LN0->isVolatile(), Align);
2923 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2932 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
2933 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2934 /// destination element value type.
2935 SDOperand DAGCombiner::
2936 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2937 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2939 // If this is already the right type, we're done.
2940 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2942 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2943 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2945 // If this is a conversion of N elements of one type to N elements of another
2946 // type, convert each element. This handles FP<->INT cases.
2947 if (SrcBitSize == DstBitSize) {
2948 SmallVector<SDOperand, 8> Ops;
2949 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2950 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2951 AddToWorkList(Ops.back().Val);
2954 MVT::getVectorType(DstEltVT,
2955 MVT::getVectorNumElements(BV->getValueType(0)));
2956 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2959 // Otherwise, we're growing or shrinking the elements. To avoid having to
2960 // handle annoying details of growing/shrinking FP values, we convert them to
2962 if (MVT::isFloatingPoint(SrcEltVT)) {
2963 // Convert the input float vector to a int vector where the elements are the
2965 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2966 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2967 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
2971 // Now we know the input is an integer vector. If the output is a FP type,
2972 // convert to integer first, then to FP of the right size.
2973 if (MVT::isFloatingPoint(DstEltVT)) {
2974 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2975 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2976 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
2978 // Next, convert to FP elements of the same size.
2979 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
2982 // Okay, we know the src/dst types are both integers of differing types.
2983 // Handling growing first.
2984 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2985 if (SrcBitSize < DstBitSize) {
2986 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2988 SmallVector<SDOperand, 8> Ops;
2989 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
2990 i += NumInputsPerOutput) {
2991 bool isLE = TLI.isLittleEndian();
2992 uint64_t NewBits = 0;
2993 bool EltIsUndef = true;
2994 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2995 // Shift the previously computed bits over.
2996 NewBits <<= SrcBitSize;
2997 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2998 if (Op.getOpcode() == ISD::UNDEF) continue;
3001 NewBits |= cast<ConstantSDNode>(Op)->getValue();
3005 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3007 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3010 MVT::ValueType VT = MVT::getVectorType(DstEltVT,
3012 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3015 // Finally, this must be the case where we are shrinking elements: each input
3016 // turns into multiple outputs.
3017 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3018 SmallVector<SDOperand, 8> Ops;
3019 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3020 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3021 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3022 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3025 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
3027 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3028 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
3029 OpVal >>= DstBitSize;
3030 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3033 // For big endian targets, swap the order of the pieces of each element.
3034 if (!TLI.isLittleEndian())
3035 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3037 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
3038 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3043 SDOperand DAGCombiner::visitFADD(SDNode *N) {
3044 SDOperand N0 = N->getOperand(0);
3045 SDOperand N1 = N->getOperand(1);
3046 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3047 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3048 MVT::ValueType VT = N->getValueType(0);
3051 if (MVT::isVector(VT)) {
3052 SDOperand FoldedVOp = SimplifyVBinOp(N);
3053 if (FoldedVOp.Val) return FoldedVOp;
3056 // fold (fadd c1, c2) -> c1+c2
3058 return DAG.getNode(ISD::FADD, VT, N0, N1);
3059 // canonicalize constant to RHS
3060 if (N0CFP && !N1CFP)
3061 return DAG.getNode(ISD::FADD, VT, N1, N0);
3062 // fold (A + (-B)) -> A-B
3063 if (isNegatibleForFree(N1) == 2)
3064 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG));
3065 // fold ((-A) + B) -> B-A
3066 if (isNegatibleForFree(N0) == 2)
3067 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG));
3069 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3070 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3071 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3072 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3073 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3078 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
3079 SDOperand N0 = N->getOperand(0);
3080 SDOperand N1 = N->getOperand(1);
3081 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3082 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3083 MVT::ValueType VT = N->getValueType(0);
3086 if (MVT::isVector(VT)) {
3087 SDOperand FoldedVOp = SimplifyVBinOp(N);
3088 if (FoldedVOp.Val) return FoldedVOp;
3091 // fold (fsub c1, c2) -> c1-c2
3093 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3095 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3096 if (isNegatibleForFree(N1))
3097 return GetNegatedExpression(N1, DAG);
3098 return DAG.getNode(ISD::FNEG, VT, N1);
3100 // fold (A-(-B)) -> A+B
3101 if (isNegatibleForFree(N1))
3102 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG));
3107 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
3108 SDOperand N0 = N->getOperand(0);
3109 SDOperand N1 = N->getOperand(1);
3110 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3111 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3112 MVT::ValueType VT = N->getValueType(0);
3115 if (MVT::isVector(VT)) {
3116 SDOperand FoldedVOp = SimplifyVBinOp(N);
3117 if (FoldedVOp.Val) return FoldedVOp;
3120 // fold (fmul c1, c2) -> c1*c2
3122 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3123 // canonicalize constant to RHS
3124 if (N0CFP && !N1CFP)
3125 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3126 // fold (fmul X, 2.0) -> (fadd X, X)
3127 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3128 return DAG.getNode(ISD::FADD, VT, N0, N0);
3129 // fold (fmul X, -1.0) -> (fneg X)
3130 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3131 return DAG.getNode(ISD::FNEG, VT, N0);
3134 if (char LHSNeg = isNegatibleForFree(N0)) {
3135 if (char RHSNeg = isNegatibleForFree(N1)) {
3136 // Both can be negated for free, check to see if at least one is cheaper
3138 if (LHSNeg == 2 || RHSNeg == 2)
3139 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG),
3140 GetNegatedExpression(N1, DAG));
3144 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3145 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3146 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3147 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3148 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3153 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
3154 SDOperand N0 = N->getOperand(0);
3155 SDOperand N1 = N->getOperand(1);
3156 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3157 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3158 MVT::ValueType VT = N->getValueType(0);
3161 if (MVT::isVector(VT)) {
3162 SDOperand FoldedVOp = SimplifyVBinOp(N);
3163 if (FoldedVOp.Val) return FoldedVOp;
3166 // fold (fdiv c1, c2) -> c1/c2
3168 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3172 if (char LHSNeg = isNegatibleForFree(N0)) {
3173 if (char RHSNeg = isNegatibleForFree(N1)) {
3174 // Both can be negated for free, check to see if at least one is cheaper
3176 if (LHSNeg == 2 || RHSNeg == 2)
3177 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG),
3178 GetNegatedExpression(N1, DAG));
3185 SDOperand DAGCombiner::visitFREM(SDNode *N) {
3186 SDOperand N0 = N->getOperand(0);
3187 SDOperand N1 = N->getOperand(1);
3188 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3189 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3190 MVT::ValueType VT = N->getValueType(0);
3192 // fold (frem c1, c2) -> fmod(c1,c2)
3194 return DAG.getNode(ISD::FREM, VT, N0, N1);
3199 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3200 SDOperand N0 = N->getOperand(0);
3201 SDOperand N1 = N->getOperand(1);
3202 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3203 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3204 MVT::ValueType VT = N->getValueType(0);
3206 if (N0CFP && N1CFP) // Constant fold
3207 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3210 const APFloat& V = N1CFP->getValueAPF();
3211 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3212 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3213 if (!V.isNegative())
3214 return DAG.getNode(ISD::FABS, VT, N0);
3216 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3219 // copysign(fabs(x), y) -> copysign(x, y)
3220 // copysign(fneg(x), y) -> copysign(x, y)
3221 // copysign(copysign(x,z), y) -> copysign(x, y)
3222 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3223 N0.getOpcode() == ISD::FCOPYSIGN)
3224 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3226 // copysign(x, abs(y)) -> abs(x)
3227 if (N1.getOpcode() == ISD::FABS)
3228 return DAG.getNode(ISD::FABS, VT, N0);
3230 // copysign(x, copysign(y,z)) -> copysign(x, z)
3231 if (N1.getOpcode() == ISD::FCOPYSIGN)
3232 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3234 // copysign(x, fp_extend(y)) -> copysign(x, y)
3235 // copysign(x, fp_round(y)) -> copysign(x, y)
3236 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3237 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3244 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3245 SDOperand N0 = N->getOperand(0);
3246 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3247 MVT::ValueType VT = N->getValueType(0);
3249 // fold (sint_to_fp c1) -> c1fp
3251 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3255 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3256 SDOperand N0 = N->getOperand(0);
3257 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3258 MVT::ValueType VT = N->getValueType(0);
3260 // fold (uint_to_fp c1) -> c1fp
3262 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3266 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3267 SDOperand N0 = N->getOperand(0);
3268 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3269 MVT::ValueType VT = N->getValueType(0);
3271 // fold (fp_to_sint c1fp) -> c1
3273 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3277 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3278 SDOperand N0 = N->getOperand(0);
3279 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3280 MVT::ValueType VT = N->getValueType(0);
3282 // fold (fp_to_uint c1fp) -> c1
3284 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3288 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
3289 SDOperand N0 = N->getOperand(0);
3290 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3291 MVT::ValueType VT = N->getValueType(0);
3293 // fold (fp_round c1fp) -> c1fp
3295 return DAG.getNode(ISD::FP_ROUND, VT, N0);
3297 // fold (fp_round (fp_extend x)) -> x
3298 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3299 return N0.getOperand(0);
3301 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3302 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
3303 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
3304 AddToWorkList(Tmp.Val);
3305 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3311 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3312 SDOperand N0 = N->getOperand(0);
3313 MVT::ValueType VT = N->getValueType(0);
3314 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3315 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3317 // fold (fp_round_inreg c1fp) -> c1fp
3319 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT);
3320 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3325 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
3326 SDOperand N0 = N->getOperand(0);
3327 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3328 MVT::ValueType VT = N->getValueType(0);
3330 // fold (fp_extend c1fp) -> c1fp
3332 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3334 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
3335 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3336 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3337 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3338 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3339 LN0->getBasePtr(), LN0->getSrcValue(),
3340 LN0->getSrcValueOffset(),
3343 LN0->getAlignment());
3344 CombineTo(N, ExtLoad);
3345 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
3346 ExtLoad.getValue(1));
3347 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3354 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
3355 SDOperand N0 = N->getOperand(0);
3357 if (isNegatibleForFree(N0))
3358 return GetNegatedExpression(N0, DAG);
3363 SDOperand DAGCombiner::visitFABS(SDNode *N) {
3364 SDOperand N0 = N->getOperand(0);
3365 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3366 MVT::ValueType VT = N->getValueType(0);
3368 // fold (fabs c1) -> fabs(c1)
3370 return DAG.getNode(ISD::FABS, VT, N0);
3371 // fold (fabs (fabs x)) -> (fabs x)
3372 if (N0.getOpcode() == ISD::FABS)
3373 return N->getOperand(0);
3374 // fold (fabs (fneg x)) -> (fabs x)
3375 // fold (fabs (fcopysign x, y)) -> (fabs x)
3376 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
3377 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
3382 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
3383 SDOperand Chain = N->getOperand(0);
3384 SDOperand N1 = N->getOperand(1);
3385 SDOperand N2 = N->getOperand(2);
3386 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3388 // never taken branch, fold to chain
3389 if (N1C && N1C->isNullValue())
3391 // unconditional branch
3392 if (N1C && N1C->getValue() == 1)
3393 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
3394 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
3396 if (N1.getOpcode() == ISD::SETCC &&
3397 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
3398 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
3399 N1.getOperand(0), N1.getOperand(1), N2);
3404 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
3406 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
3407 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
3408 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3410 // Use SimplifySetCC to simplify SETCC's.
3411 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3412 if (Simp.Val) AddToWorkList(Simp.Val);
3414 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3416 // fold br_cc true, dest -> br dest (unconditional branch)
3417 if (SCCC && SCCC->getValue())
3418 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3420 // fold br_cc false, dest -> unconditional fall through
3421 if (SCCC && SCCC->isNullValue())
3422 return N->getOperand(0);
3424 // fold to a simpler setcc
3425 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3426 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3427 Simp.getOperand(2), Simp.getOperand(0),
3428 Simp.getOperand(1), N->getOperand(4));
3433 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3434 /// pre-indexed load / store when the base pointer is a add or subtract
3435 /// and it has other uses besides the load / store. After the
3436 /// transformation, the new indexed load / store has effectively folded
3437 /// the add / subtract in and all of its other uses are redirected to the
3438 /// new load / store.
3439 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3446 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3447 if (LD->getAddressingMode() != ISD::UNINDEXED)
3449 VT = LD->getLoadedVT();
3450 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3451 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3453 Ptr = LD->getBasePtr();
3454 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3455 if (ST->getAddressingMode() != ISD::UNINDEXED)
3457 VT = ST->getStoredVT();
3458 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3459 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3461 Ptr = ST->getBasePtr();
3466 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3467 // out. There is no reason to make this a preinc/predec.
3468 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3469 Ptr.Val->hasOneUse())
3472 // Ask the target to do addressing mode selection.
3475 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3476 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3478 // Don't create a indexed load / store with zero offset.
3479 if (isa<ConstantSDNode>(Offset) &&
3480 cast<ConstantSDNode>(Offset)->getValue() == 0)
3483 // Try turning it into a pre-indexed load / store except when:
3484 // 1) The new base ptr is a frame index.
3485 // 2) If N is a store and the new base ptr is either the same as or is a
3486 // predecessor of the value being stored.
3487 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
3488 // that would create a cycle.
3489 // 4) All uses are load / store ops that use it as old base ptr.
3491 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3492 // (plus the implicit offset) to a register to preinc anyway.
3493 if (isa<FrameIndexSDNode>(BasePtr))
3498 SDOperand Val = cast<StoreSDNode>(N)->getValue();
3499 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val))
3503 // Now check for #3 and #4.
3504 bool RealUse = false;
3505 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3506 E = Ptr.Val->use_end(); I != E; ++I) {
3510 if (Use->isPredecessor(N))
3513 if (!((Use->getOpcode() == ISD::LOAD &&
3514 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
3515 (Use->getOpcode() == ISD::STORE) &&
3516 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
3524 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
3526 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3529 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
3530 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3532 std::vector<SDNode*> NowDead;
3534 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3536 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3539 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3543 // Nodes can end up on the worklist more than once. Make sure we do
3544 // not process a node that has been replaced.
3545 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3546 removeFromWorkList(NowDead[i]);
3547 // Finally, since the node is now dead, remove it from the graph.
3550 // Replace the uses of Ptr with uses of the updated base value.
3551 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
3553 removeFromWorkList(Ptr.Val);
3554 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3555 removeFromWorkList(NowDead[i]);
3556 DAG.DeleteNode(Ptr.Val);
3561 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
3562 /// add / sub of the base pointer node into a post-indexed load / store.
3563 /// The transformation folded the add / subtract into the new indexed
3564 /// load / store effectively and all of its uses are redirected to the
3565 /// new load / store.
3566 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
3573 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3574 if (LD->getAddressingMode() != ISD::UNINDEXED)
3576 VT = LD->getLoadedVT();
3577 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
3578 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
3580 Ptr = LD->getBasePtr();
3581 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3582 if (ST->getAddressingMode() != ISD::UNINDEXED)
3584 VT = ST->getStoredVT();
3585 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3586 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3588 Ptr = ST->getBasePtr();
3593 if (Ptr.Val->hasOneUse())
3596 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3597 E = Ptr.Val->use_end(); I != E; ++I) {
3600 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3605 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3606 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3608 std::swap(BasePtr, Offset);
3611 // Don't create a indexed load / store with zero offset.
3612 if (isa<ConstantSDNode>(Offset) &&
3613 cast<ConstantSDNode>(Offset)->getValue() == 0)
3616 // Try turning it into a post-indexed load / store except when
3617 // 1) All uses are load / store ops that use it as base ptr.
3618 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3619 // nor a successor of N. Otherwise, if Op is folded that would
3623 bool TryNext = false;
3624 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
3625 EE = BasePtr.Val->use_end(); II != EE; ++II) {
3630 // If all the uses are load / store addresses, then don't do the
3632 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
3633 bool RealUse = false;
3634 for (SDNode::use_iterator III = Use->use_begin(),
3635 EEE = Use->use_end(); III != EEE; ++III) {
3636 SDNode *UseUse = *III;
3637 if (!((UseUse->getOpcode() == ISD::LOAD &&
3638 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
3639 (UseUse->getOpcode() == ISD::STORE) &&
3640 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
3654 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
3655 SDOperand Result = isLoad
3656 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
3657 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3660 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
3661 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3663 std::vector<SDNode*> NowDead;
3665 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3667 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3670 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3674 // Nodes can end up on the worklist more than once. Make sure we do
3675 // not process a node that has been replaced.
3676 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3677 removeFromWorkList(NowDead[i]);
3678 // Finally, since the node is now dead, remove it from the graph.
3681 // Replace the uses of Use with uses of the updated base value.
3682 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
3683 Result.getValue(isLoad ? 1 : 0),
3685 removeFromWorkList(Op);
3686 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3687 removeFromWorkList(NowDead[i]);
3698 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
3699 LoadSDNode *LD = cast<LoadSDNode>(N);
3700 SDOperand Chain = LD->getChain();
3701 SDOperand Ptr = LD->getBasePtr();
3703 // If load is not volatile and there are no uses of the loaded value (and
3704 // the updated indexed value in case of indexed loads), change uses of the
3705 // chain value into uses of the chain input (i.e. delete the dead load).
3706 if (!LD->isVolatile()) {
3707 if (N->getValueType(1) == MVT::Other) {
3709 if (N->hasNUsesOfValue(0, 0))
3710 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
3713 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
3714 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
3715 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0));
3716 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1));
3717 SDOperand To[] = { Undef0, Undef1, Chain };
3718 return CombineTo(N, To, 3);
3723 // If this load is directly stored, replace the load value with the stored
3725 // TODO: Handle store large -> read small portion.
3726 // TODO: Handle TRUNCSTORE/LOADEXT
3727 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3728 if (ISD::isNON_TRUNCStore(Chain.Val)) {
3729 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
3730 if (PrevST->getBasePtr() == Ptr &&
3731 PrevST->getValue().getValueType() == N->getValueType(0))
3732 return CombineTo(N, Chain.getOperand(1), Chain);
3737 // Walk up chain skipping non-aliasing memory nodes.
3738 SDOperand BetterChain = FindBetterChain(N, Chain);
3740 // If there is a better chain.
3741 if (Chain != BetterChain) {
3744 // Replace the chain to void dependency.
3745 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3746 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
3747 LD->getSrcValue(), LD->getSrcValueOffset(),
3748 LD->isVolatile(), LD->getAlignment());
3750 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
3751 LD->getValueType(0),
3752 BetterChain, Ptr, LD->getSrcValue(),
3753 LD->getSrcValueOffset(),
3756 LD->getAlignment());
3759 // Create token factor to keep old chain connected.
3760 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
3761 Chain, ReplLoad.getValue(1));
3763 // Replace uses with load result and token factor. Don't add users
3765 return CombineTo(N, ReplLoad.getValue(0), Token, false);
3769 // Try transforming N to an indexed load.
3770 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3771 return SDOperand(N, 0);
3776 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
3777 StoreSDNode *ST = cast<StoreSDNode>(N);
3778 SDOperand Chain = ST->getChain();
3779 SDOperand Value = ST->getValue();
3780 SDOperand Ptr = ST->getBasePtr();
3782 // If this is a store of a bit convert, store the input value if the
3783 // resultant store does not need a higher alignment than the original.
3784 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
3785 ST->getAddressingMode() == ISD::UNINDEXED) {
3786 unsigned Align = ST->getAlignment();
3787 MVT::ValueType SVT = Value.getOperand(0).getValueType();
3788 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
3789 getABITypeAlignment(MVT::getTypeForValueType(SVT));
3790 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
3791 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
3792 ST->getSrcValueOffset(), ST->isVolatile(), Align);
3795 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
3796 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
3797 if (Value.getOpcode() != ISD::TargetConstantFP) {
3799 switch (CFP->getValueType(0)) {
3800 default: assert(0 && "Unknown FP type");
3801 case MVT::f80: // We don't do this for these yet.
3806 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
3807 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
3808 convertToAPInt().getZExtValue(), MVT::i32);
3809 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3810 ST->getSrcValueOffset(), ST->isVolatile(),
3811 ST->getAlignment());
3815 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
3816 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
3817 getZExtValue(), MVT::i64);
3818 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3819 ST->getSrcValueOffset(), ST->isVolatile(),
3820 ST->getAlignment());
3821 } else if (TLI.isTypeLegal(MVT::i32)) {
3822 // Many FP stores are not make apparent until after legalize, e.g. for
3823 // argument passing. Since this is so common, custom legalize the
3824 // 64-bit integer store into two 32-bit stores.
3825 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue();
3826 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
3827 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
3828 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
3830 int SVOffset = ST->getSrcValueOffset();
3831 unsigned Alignment = ST->getAlignment();
3832 bool isVolatile = ST->isVolatile();
3834 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
3835 ST->getSrcValueOffset(),
3836 isVolatile, ST->getAlignment());
3837 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3838 DAG.getConstant(4, Ptr.getValueType()));
3842 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
3843 SVOffset, isVolatile, Alignment);
3844 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
3852 // Walk up chain skipping non-aliasing memory nodes.
3853 SDOperand BetterChain = FindBetterChain(N, Chain);
3855 // If there is a better chain.
3856 if (Chain != BetterChain) {
3857 // Replace the chain to avoid dependency.
3858 SDOperand ReplStore;
3859 if (ST->isTruncatingStore()) {
3860 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
3861 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(),
3862 ST->isVolatile(), ST->getAlignment());
3864 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
3865 ST->getSrcValue(), ST->getSrcValueOffset(),
3866 ST->isVolatile(), ST->getAlignment());
3869 // Create token to keep both nodes around.
3871 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
3873 // Don't add users to work list.
3874 return CombineTo(N, Token, false);
3878 // Try transforming N to an indexed store.
3879 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3880 return SDOperand(N, 0);
3885 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
3886 SDOperand InVec = N->getOperand(0);
3887 SDOperand InVal = N->getOperand(1);
3888 SDOperand EltNo = N->getOperand(2);
3890 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
3891 // vector with the inserted element.
3892 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3893 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3894 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3895 if (Elt < Ops.size())
3897 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
3898 &Ops[0], Ops.size());
3904 SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
3905 unsigned NumInScalars = N->getNumOperands();
3906 MVT::ValueType VT = N->getValueType(0);
3907 unsigned NumElts = MVT::getVectorNumElements(VT);
3908 MVT::ValueType EltType = MVT::getVectorElementType(VT);
3910 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
3911 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
3912 // at most two distinct vectors, turn this into a shuffle node.
3913 SDOperand VecIn1, VecIn2;
3914 for (unsigned i = 0; i != NumInScalars; ++i) {
3915 // Ignore undef inputs.
3916 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3918 // If this input is something other than a EXTRACT_VECTOR_ELT with a
3919 // constant index, bail out.
3920 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
3921 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
3922 VecIn1 = VecIn2 = SDOperand(0, 0);
3926 // If the input vector type disagrees with the result of the build_vector,
3927 // we can't make a shuffle.
3928 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
3929 if (ExtractedFromVec.getValueType() != VT) {
3930 VecIn1 = VecIn2 = SDOperand(0, 0);
3934 // Otherwise, remember this. We allow up to two distinct input vectors.
3935 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
3938 if (VecIn1.Val == 0) {
3939 VecIn1 = ExtractedFromVec;
3940 } else if (VecIn2.Val == 0) {
3941 VecIn2 = ExtractedFromVec;
3944 VecIn1 = VecIn2 = SDOperand(0, 0);
3949 // If everything is good, we can make a shuffle operation.
3951 SmallVector<SDOperand, 8> BuildVecIndices;
3952 for (unsigned i = 0; i != NumInScalars; ++i) {
3953 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
3954 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
3958 SDOperand Extract = N->getOperand(i);
3960 // If extracting from the first vector, just use the index directly.
3961 if (Extract.getOperand(0) == VecIn1) {
3962 BuildVecIndices.push_back(Extract.getOperand(1));
3966 // Otherwise, use InIdx + VecSize
3967 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
3968 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
3969 TLI.getPointerTy()));
3972 // Add count and size info.
3973 MVT::ValueType BuildVecVT =
3974 MVT::getVectorType(TLI.getPointerTy(), NumElts);
3976 // Return the new VECTOR_SHUFFLE node.
3982 // Use an undef build_vector as input for the second operand.
3983 std::vector<SDOperand> UnOps(NumInScalars,
3984 DAG.getNode(ISD::UNDEF,
3986 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
3987 &UnOps[0], UnOps.size());
3988 AddToWorkList(Ops[1].Val);
3990 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
3991 &BuildVecIndices[0], BuildVecIndices.size());
3992 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
3998 SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
3999 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
4000 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
4001 // inputs come from at most two distinct vectors, turn this into a shuffle
4004 // If we only have one input vector, we don't need to do any concatenation.
4005 if (N->getNumOperands() == 1) {
4006 return N->getOperand(0);
4012 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
4013 SDOperand ShufMask = N->getOperand(2);
4014 unsigned NumElts = ShufMask.getNumOperands();
4016 // If the shuffle mask is an identity operation on the LHS, return the LHS.
4017 bool isIdentity = true;
4018 for (unsigned i = 0; i != NumElts; ++i) {
4019 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4020 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
4025 if (isIdentity) return N->getOperand(0);
4027 // If the shuffle mask is an identity operation on the RHS, return the RHS.
4029 for (unsigned i = 0; i != NumElts; ++i) {
4030 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4031 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
4036 if (isIdentity) return N->getOperand(1);
4038 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
4040 bool isUnary = true;
4041 bool isSplat = true;
4043 unsigned BaseIdx = 0;
4044 for (unsigned i = 0; i != NumElts; ++i)
4045 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
4046 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
4047 int V = (Idx < NumElts) ? 0 : 1;
4061 SDOperand N0 = N->getOperand(0);
4062 SDOperand N1 = N->getOperand(1);
4063 // Normalize unary shuffle so the RHS is undef.
4064 if (isUnary && VecNum == 1)
4067 // If it is a splat, check if the argument vector is a build_vector with
4068 // all scalar elements the same.
4072 // If this is a bit convert that changes the element type of the vector but
4073 // not the number of vector elements, look through it. Be careful not to
4074 // look though conversions that change things like v4f32 to v2f64.
4075 if (V->getOpcode() == ISD::BIT_CONVERT) {
4076 SDOperand ConvInput = V->getOperand(0);
4077 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts)
4081 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4082 unsigned NumElems = V->getNumOperands();
4083 if (NumElems > BaseIdx) {
4085 bool AllSame = true;
4086 for (unsigned i = 0; i != NumElems; ++i) {
4087 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4088 Base = V->getOperand(i);
4092 // Splat of <u, u, u, u>, return <u, u, u, u>
4095 for (unsigned i = 0; i != NumElems; ++i) {
4096 if (V->getOperand(i) != Base) {
4101 // Splat of <x, x, x, x>, return <x, x, x, x>
4108 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
4110 if (isUnary || N0 == N1) {
4111 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
4113 SmallVector<SDOperand, 8> MappedOps;
4114 for (unsigned i = 0; i != NumElts; ++i) {
4115 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
4116 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
4117 MappedOps.push_back(ShufMask.getOperand(i));
4120 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
4121 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
4124 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
4125 &MappedOps[0], MappedOps.size());
4126 AddToWorkList(ShufMask.Val);
4127 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
4129 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
4136 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
4137 /// an AND to a vector_shuffle with the destination vector and a zero vector.
4138 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
4139 /// vector_shuffle V, Zero, <0, 4, 2, 4>
4140 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
4141 SDOperand LHS = N->getOperand(0);
4142 SDOperand RHS = N->getOperand(1);
4143 if (N->getOpcode() == ISD::AND) {
4144 if (RHS.getOpcode() == ISD::BIT_CONVERT)
4145 RHS = RHS.getOperand(0);
4146 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
4147 std::vector<SDOperand> IdxOps;
4148 unsigned NumOps = RHS.getNumOperands();
4149 unsigned NumElts = NumOps;
4150 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType());
4151 for (unsigned i = 0; i != NumElts; ++i) {
4152 SDOperand Elt = RHS.getOperand(i);
4153 if (!isa<ConstantSDNode>(Elt))
4155 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
4156 IdxOps.push_back(DAG.getConstant(i, EVT));
4157 else if (cast<ConstantSDNode>(Elt)->isNullValue())
4158 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
4163 // Let's see if the target supports this vector_shuffle.
4164 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
4167 // Return the new VECTOR_SHUFFLE node.
4168 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts);
4169 std::vector<SDOperand> Ops;
4170 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
4172 AddToWorkList(LHS.Val);
4173 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
4174 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4175 &ZeroOps[0], ZeroOps.size()));
4176 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4177 &IdxOps[0], IdxOps.size()));
4178 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
4179 &Ops[0], Ops.size());
4180 if (VT != LHS.getValueType()) {
4181 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result);
4189 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
4190 SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
4191 // After legalize, the target may be depending on adds and other
4192 // binary ops to provide legal ways to construct constants or other
4193 // things. Simplifying them may result in a loss of legality.
4194 if (AfterLegalize) return SDOperand();
4196 MVT::ValueType VT = N->getValueType(0);
4197 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!");
4199 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4200 SDOperand LHS = N->getOperand(0);
4201 SDOperand RHS = N->getOperand(1);
4202 SDOperand Shuffle = XformToShuffleWithZero(N);
4203 if (Shuffle.Val) return Shuffle;
4205 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
4207 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
4208 RHS.getOpcode() == ISD::BUILD_VECTOR) {
4209 SmallVector<SDOperand, 8> Ops;
4210 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
4211 SDOperand LHSOp = LHS.getOperand(i);
4212 SDOperand RHSOp = RHS.getOperand(i);
4213 // If these two elements can't be folded, bail out.
4214 if ((LHSOp.getOpcode() != ISD::UNDEF &&
4215 LHSOp.getOpcode() != ISD::Constant &&
4216 LHSOp.getOpcode() != ISD::ConstantFP) ||
4217 (RHSOp.getOpcode() != ISD::UNDEF &&
4218 RHSOp.getOpcode() != ISD::Constant &&
4219 RHSOp.getOpcode() != ISD::ConstantFP))
4221 // Can't fold divide by zero.
4222 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
4223 N->getOpcode() == ISD::FDIV) {
4224 if ((RHSOp.getOpcode() == ISD::Constant &&
4225 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
4226 (RHSOp.getOpcode() == ISD::ConstantFP &&
4227 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero()))
4230 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
4231 AddToWorkList(Ops.back().Val);
4232 assert((Ops.back().getOpcode() == ISD::UNDEF ||
4233 Ops.back().getOpcode() == ISD::Constant ||
4234 Ops.back().getOpcode() == ISD::ConstantFP) &&
4235 "Scalar binop didn't fold!");
4238 if (Ops.size() == LHS.getNumOperands()) {
4239 MVT::ValueType VT = LHS.getValueType();
4240 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
4247 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
4248 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
4250 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
4251 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4252 // If we got a simplified select_cc node back from SimplifySelectCC, then
4253 // break it down into a new SETCC node, and a new SELECT node, and then return
4254 // the SELECT node, since we were called with a SELECT node.
4256 // Check to see if we got a select_cc back (to turn into setcc/select).
4257 // Otherwise, just return whatever node we got back, like fabs.
4258 if (SCC.getOpcode() == ISD::SELECT_CC) {
4259 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
4260 SCC.getOperand(0), SCC.getOperand(1),
4262 AddToWorkList(SETCC.Val);
4263 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
4264 SCC.getOperand(3), SETCC);
4271 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
4272 /// are the two values being selected between, see if we can simplify the
4273 /// select. Callers of this should assume that TheSelect is deleted if this
4274 /// returns true. As such, they should return the appropriate thing (e.g. the
4275 /// node) back to the top-level of the DAG combiner loop to avoid it being
4278 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
4281 // If this is a select from two identical things, try to pull the operation
4282 // through the select.
4283 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
4284 // If this is a load and the token chain is identical, replace the select
4285 // of two loads with a load through a select of the address to load from.
4286 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
4287 // constants have been dropped into the constant pool.
4288 if (LHS.getOpcode() == ISD::LOAD &&
4289 // Token chains must be identical.
4290 LHS.getOperand(0) == RHS.getOperand(0)) {
4291 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
4292 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
4294 // If this is an EXTLOAD, the VT's must match.
4295 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
4296 // FIXME: this conflates two src values, discarding one. This is not
4297 // the right thing to do, but nothing uses srcvalues now. When they do,
4298 // turn SrcValue into a list of locations.
4300 if (TheSelect->getOpcode() == ISD::SELECT) {
4301 // Check that the condition doesn't reach either load. If so, folding
4302 // this will induce a cycle into the DAG.
4303 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4304 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
4305 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4306 TheSelect->getOperand(0), LLD->getBasePtr(),
4310 // Check that the condition doesn't reach either load. If so, folding
4311 // this will induce a cycle into the DAG.
4312 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4313 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4314 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4315 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4316 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4317 TheSelect->getOperand(0),
4318 TheSelect->getOperand(1),
4319 LLD->getBasePtr(), RLD->getBasePtr(),
4320 TheSelect->getOperand(4));
4326 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4327 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4328 Addr,LLD->getSrcValue(),
4329 LLD->getSrcValueOffset(),
4331 LLD->getAlignment());
4333 Load = DAG.getExtLoad(LLD->getExtensionType(),
4334 TheSelect->getValueType(0),
4335 LLD->getChain(), Addr, LLD->getSrcValue(),
4336 LLD->getSrcValueOffset(),
4339 LLD->getAlignment());
4341 // Users of the select now use the result of the load.
4342 CombineTo(TheSelect, Load);
4344 // Users of the old loads now use the new load's chain. We know the
4345 // old-load value is dead now.
4346 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
4347 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
4357 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
4358 SDOperand N2, SDOperand N3,
4359 ISD::CondCode CC, bool NotExtCompare) {
4361 MVT::ValueType VT = N2.getValueType();
4362 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
4363 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
4364 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
4366 // Determine if the condition we're dealing with is constant
4367 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
4368 if (SCC.Val) AddToWorkList(SCC.Val);
4369 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
4371 // fold select_cc true, x, y -> x
4372 if (SCCC && SCCC->getValue())
4374 // fold select_cc false, x, y -> y
4375 if (SCCC && SCCC->getValue() == 0)
4378 // Check to see if we can simplify the select into an fabs node
4379 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
4380 // Allow either -0.0 or 0.0
4381 if (CFP->getValueAPF().isZero()) {
4382 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
4383 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
4384 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
4385 N2 == N3.getOperand(0))
4386 return DAG.getNode(ISD::FABS, VT, N0);
4388 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
4389 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
4390 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
4391 N2.getOperand(0) == N3)
4392 return DAG.getNode(ISD::FABS, VT, N3);
4396 // Check to see if we can perform the "gzip trick", transforming
4397 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
4398 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
4399 MVT::isInteger(N0.getValueType()) &&
4400 MVT::isInteger(N2.getValueType()) &&
4401 (N1C->isNullValue() || // (a < 0) ? b : 0
4402 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
4403 MVT::ValueType XType = N0.getValueType();
4404 MVT::ValueType AType = N2.getValueType();
4405 if (XType >= AType) {
4406 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
4407 // single-bit constant.
4408 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
4409 unsigned ShCtV = Log2_64(N2C->getValue());
4410 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
4411 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
4412 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
4413 AddToWorkList(Shift.Val);
4414 if (XType > AType) {
4415 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4416 AddToWorkList(Shift.Val);
4418 return DAG.getNode(ISD::AND, AType, Shift, N2);
4420 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4421 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4422 TLI.getShiftAmountTy()));
4423 AddToWorkList(Shift.Val);
4424 if (XType > AType) {
4425 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4426 AddToWorkList(Shift.Val);
4428 return DAG.getNode(ISD::AND, AType, Shift, N2);
4432 // fold select C, 16, 0 -> shl C, 4
4433 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
4434 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
4436 // If the caller doesn't want us to simplify this into a zext of a compare,
4438 if (NotExtCompare && N2C->getValue() == 1)
4441 // Get a SetCC of the condition
4442 // FIXME: Should probably make sure that setcc is legal if we ever have a
4443 // target where it isn't.
4444 SDOperand Temp, SCC;
4445 // cast from setcc result type to select result type
4446 if (AfterLegalize) {
4447 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4448 if (N2.getValueType() < SCC.getValueType())
4449 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
4451 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4453 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
4454 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4456 AddToWorkList(SCC.Val);
4457 AddToWorkList(Temp.Val);
4459 if (N2C->getValue() == 1)
4461 // shl setcc result by log2 n2c
4462 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
4463 DAG.getConstant(Log2_64(N2C->getValue()),
4464 TLI.getShiftAmountTy()));
4467 // Check to see if this is the equivalent of setcc
4468 // FIXME: Turn all of these into setcc if setcc if setcc is legal
4469 // otherwise, go ahead with the folds.
4470 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
4471 MVT::ValueType XType = N0.getValueType();
4472 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
4473 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4474 if (Res.getValueType() != VT)
4475 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
4479 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
4480 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
4481 TLI.isOperationLegal(ISD::CTLZ, XType)) {
4482 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
4483 return DAG.getNode(ISD::SRL, XType, Ctlz,
4484 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
4485 TLI.getShiftAmountTy()));
4487 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4488 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4489 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
4491 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
4492 DAG.getConstant(~0ULL, XType));
4493 return DAG.getNode(ISD::SRL, XType,
4494 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
4495 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4496 TLI.getShiftAmountTy()));
4498 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
4499 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
4500 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
4501 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4502 TLI.getShiftAmountTy()));
4503 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
4507 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
4508 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4509 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
4510 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
4511 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
4512 MVT::ValueType XType = N0.getValueType();
4513 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4514 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4515 TLI.getShiftAmountTy()));
4516 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4517 AddToWorkList(Shift.Val);
4518 AddToWorkList(Add.Val);
4519 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4521 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
4522 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4523 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
4524 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
4525 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
4526 MVT::ValueType XType = N0.getValueType();
4527 if (SubC->isNullValue() && MVT::isInteger(XType)) {
4528 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4529 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4530 TLI.getShiftAmountTy()));
4531 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4532 AddToWorkList(Shift.Val);
4533 AddToWorkList(Add.Val);
4534 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4542 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
4543 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
4544 SDOperand N1, ISD::CondCode Cond,
4545 bool foldBooleans) {
4546 TargetLowering::DAGCombinerInfo
4547 DagCombineInfo(DAG, !AfterLegalize, false, this);
4548 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
4551 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4552 /// return a DAG expression to select that will generate the same value by
4553 /// multiplying by a magic number. See:
4554 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4555 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4556 std::vector<SDNode*> Built;
4557 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4559 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4565 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4566 /// return a DAG expression to select that will generate the same value by
4567 /// multiplying by a magic number. See:
4568 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4569 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4570 std::vector<SDNode*> Built;
4571 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4573 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4579 /// FindBaseOffset - Return true if base is known not to alias with anything
4580 /// but itself. Provides base object and offset as results.
4581 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4582 // Assume it is a primitive operation.
4583 Base = Ptr; Offset = 0;
4585 // If it's an adding a simple constant then integrate the offset.
4586 if (Base.getOpcode() == ISD::ADD) {
4587 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4588 Base = Base.getOperand(0);
4589 Offset += C->getValue();
4593 // If it's any of the following then it can't alias with anything but itself.
4594 return isa<FrameIndexSDNode>(Base) ||
4595 isa<ConstantPoolSDNode>(Base) ||
4596 isa<GlobalAddressSDNode>(Base);
4599 /// isAlias - Return true if there is any possibility that the two addresses
4601 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4602 const Value *SrcValue1, int SrcValueOffset1,
4603 SDOperand Ptr2, int64_t Size2,
4604 const Value *SrcValue2, int SrcValueOffset2)
4606 // If they are the same then they must be aliases.
4607 if (Ptr1 == Ptr2) return true;
4609 // Gather base node and offset information.
4610 SDOperand Base1, Base2;
4611 int64_t Offset1, Offset2;
4612 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4613 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4615 // If they have a same base address then...
4616 if (Base1 == Base2) {
4617 // Check to see if the addresses overlap.
4618 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4621 // If we know both bases then they can't alias.
4622 if (KnownBase1 && KnownBase2) return false;
4624 if (CombinerGlobalAA) {
4625 // Use alias analysis information.
4626 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
4627 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
4628 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
4629 AliasAnalysis::AliasResult AAResult =
4630 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4631 if (AAResult == AliasAnalysis::NoAlias)
4635 // Otherwise we have to assume they alias.
4639 /// FindAliasInfo - Extracts the relevant alias information from the memory
4640 /// node. Returns true if the operand was a load.
4641 bool DAGCombiner::FindAliasInfo(SDNode *N,
4642 SDOperand &Ptr, int64_t &Size,
4643 const Value *&SrcValue, int &SrcValueOffset) {
4644 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4645 Ptr = LD->getBasePtr();
4646 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4647 SrcValue = LD->getSrcValue();
4648 SrcValueOffset = LD->getSrcValueOffset();
4650 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4651 Ptr = ST->getBasePtr();
4652 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4653 SrcValue = ST->getSrcValue();
4654 SrcValueOffset = ST->getSrcValueOffset();
4656 assert(0 && "FindAliasInfo expected a memory operand");
4662 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4663 /// looking for aliasing nodes and adding them to the Aliases vector.
4664 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4665 SmallVector<SDOperand, 8> &Aliases) {
4666 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4667 std::set<SDNode *> Visited; // Visited node set.
4669 // Get alias information for node.
4672 const Value *SrcValue;
4674 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4677 Chains.push_back(OriginalChain);
4679 // Look at each chain and determine if it is an alias. If so, add it to the
4680 // aliases list. If not, then continue up the chain looking for the next
4682 while (!Chains.empty()) {
4683 SDOperand Chain = Chains.back();
4686 // Don't bother if we've been before.
4687 if (Visited.find(Chain.Val) != Visited.end()) continue;
4688 Visited.insert(Chain.Val);
4690 switch (Chain.getOpcode()) {
4691 case ISD::EntryToken:
4692 // Entry token is ideal chain operand, but handled in FindBetterChain.
4697 // Get alias information for Chain.
4700 const Value *OpSrcValue;
4701 int OpSrcValueOffset;
4702 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4703 OpSrcValue, OpSrcValueOffset);
4705 // If chain is alias then stop here.
4706 if (!(IsLoad && IsOpLoad) &&
4707 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4708 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4709 Aliases.push_back(Chain);
4711 // Look further up the chain.
4712 Chains.push_back(Chain.getOperand(0));
4713 // Clean up old chain.
4714 AddToWorkList(Chain.Val);
4719 case ISD::TokenFactor:
4720 // We have to check each of the operands of the token factor, so we queue
4721 // then up. Adding the operands to the queue (stack) in reverse order
4722 // maintains the original order and increases the likelihood that getNode
4723 // will find a matching token factor (CSE.)
4724 for (unsigned n = Chain.getNumOperands(); n;)
4725 Chains.push_back(Chain.getOperand(--n));
4726 // Eliminate the token factor if we can.
4727 AddToWorkList(Chain.Val);
4731 // For all other instructions we will just have to take what we can get.
4732 Aliases.push_back(Chain);
4738 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4739 /// for a better chain (aliasing node.)
4740 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4741 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4743 // Accumulate all the aliases to this node.
4744 GatherAllAliases(N, OldChain, Aliases);
4746 if (Aliases.size() == 0) {
4747 // If no operands then chain to entry token.
4748 return DAG.getEntryNode();
4749 } else if (Aliases.size() == 1) {
4750 // If a single operand then chain to it. We don't need to revisit it.
4754 // Construct a custom tailored token factor.
4755 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4756 &Aliases[0], Aliases.size());
4758 // Make sure the old chain gets cleaned up.
4759 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4764 // SelectionDAG::Combine - This is the entry point for the file.
4766 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4767 if (!RunningAfterLegalize && ViewDAGCombine1)
4769 if (RunningAfterLegalize && ViewDAGCombine2)
4771 /// run - This is the main entry point to this class.
4773 DAGCombiner(*this, AA).Run(RunningAfterLegalize);