1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SetVector.h"
22 #include "llvm/ADT/Statistic.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
43 #define DEBUG_TYPE "dagcombine"
45 STATISTIC(NodesCombined , "Number of dag nodes combined");
46 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
47 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
48 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
50 STATISTIC(SlicedLoads, "Number of load sliced");
54 CombinerAA("combiner-alias-analysis", cl::Hidden,
55 cl::desc("Enable DAG combiner alias-analysis heuristics"));
58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
59 cl::desc("Enable DAG combiner's use of IR alias analysis"));
62 UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
63 cl::desc("Enable DAG combiner's use of TBAA"));
66 static cl::opt<std::string>
67 CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
68 cl::desc("Only use DAG-combiner alias analysis in this"
72 /// Hidden option to stress test load slicing, i.e., when this option
73 /// is enabled, load slicing bypasses most of its profitability guards.
75 StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
76 cl::desc("Bypass the profitability model of load "
80 //------------------------------ DAGCombiner ---------------------------------//
84 const TargetLowering &TLI;
86 CodeGenOpt::Level OptLevel;
91 /// \brief Worklist of all of the nodes that need to be simplified.
93 /// This must behave as a stack -- new nodes to process are pushed onto the
94 /// back and when processing we pop off of the back.
96 /// The worklist will not contain duplicates but may contain null entries
97 /// due to nodes being deleted from the underlying DAG.
98 SmallVector<SDNode *, 64> Worklist;
100 /// \brief Mapping from an SDNode to its position on the worklist.
102 /// This is used to find and remove nodes from the worklist (by nulling
103 /// them) when they are deleted from the underlying DAG. It relies on
104 /// stable indices of nodes within the worklist.
105 DenseMap<SDNode *, unsigned> WorklistMap;
107 /// \brief Set of nodes which have been combined (at least once).
109 /// This is used to allow us to reliably add any operands of a DAG node
110 /// which have not yet been combined to the worklist.
111 SmallPtrSet<SDNode *, 64> CombinedNodes;
113 // AA - Used for DAG load/store alias analysis.
116 /// AddUsersToWorklist - When an instruction is simplified, add all users of
117 /// the instruction to the work lists because they might get more simplified
120 void AddUsersToWorklist(SDNode *N) {
121 for (SDNode *Node : N->uses())
125 /// visit - call the node-specific routine that knows how to fold each
126 /// particular type of node.
127 SDValue visit(SDNode *N);
130 /// AddToWorklist - Add to the work list making sure its instance is at the
131 /// back (next to be processed.)
132 void AddToWorklist(SDNode *N) {
133 // Skip handle nodes as they can't usefully be combined and confuse the
134 // zero-use deletion strategy.
135 if (N->getOpcode() == ISD::HANDLENODE)
138 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
139 Worklist.push_back(N);
142 /// removeFromWorklist - remove all instances of N from the worklist.
144 void removeFromWorklist(SDNode *N) {
145 CombinedNodes.erase(N);
147 auto It = WorklistMap.find(N);
148 if (It == WorklistMap.end())
149 return; // Not in the worklist.
151 // Null out the entry rather than erasing it to avoid a linear operation.
152 Worklist[It->second] = nullptr;
153 WorklistMap.erase(It);
156 void deleteAndRecombine(SDNode *N);
157 bool recursivelyDeleteUnusedNodes(SDNode *N);
159 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
162 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
163 return CombineTo(N, &Res, 1, AddTo);
166 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
168 SDValue To[] = { Res0, Res1 };
169 return CombineTo(N, To, 2, AddTo);
172 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
176 /// SimplifyDemandedBits - Check the specified integer node value to see if
177 /// it can be simplified or if things it uses can be simplified by bit
178 /// propagation. If so, return true.
179 bool SimplifyDemandedBits(SDValue Op) {
180 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
181 APInt Demanded = APInt::getAllOnesValue(BitWidth);
182 return SimplifyDemandedBits(Op, Demanded);
185 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
187 bool CombineToPreIndexedLoadStore(SDNode *N);
188 bool CombineToPostIndexedLoadStore(SDNode *N);
189 bool SliceUpLoad(SDNode *N);
191 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
194 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
195 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
196 /// \param EltNo index of the vector element to load.
197 /// \param OriginalLoad load that EVE came from to be replaced.
198 /// \returns EVE on success SDValue() on failure.
199 SDValue ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
200 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad);
201 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
202 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
203 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
204 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
205 SDValue PromoteIntBinOp(SDValue Op);
206 SDValue PromoteIntShiftOp(SDValue Op);
207 SDValue PromoteExtend(SDValue Op);
208 bool PromoteLoad(SDValue Op);
210 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
211 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
212 ISD::NodeType ExtType);
214 /// combine - call the node-specific routine that knows how to fold each
215 /// particular type of node. If that doesn't do anything, try the
216 /// target-specific DAG combines.
217 SDValue combine(SDNode *N);
219 // Visitation implementation - Implement dag node combining for different
220 // node types. The semantics are as follows:
222 // SDValue.getNode() == 0 - No change was made
223 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
224 // otherwise - N should be replaced by the returned Operand.
226 SDValue visitTokenFactor(SDNode *N);
227 SDValue visitMERGE_VALUES(SDNode *N);
228 SDValue visitADD(SDNode *N);
229 SDValue visitSUB(SDNode *N);
230 SDValue visitADDC(SDNode *N);
231 SDValue visitSUBC(SDNode *N);
232 SDValue visitADDE(SDNode *N);
233 SDValue visitSUBE(SDNode *N);
234 SDValue visitMUL(SDNode *N);
235 SDValue visitSDIV(SDNode *N);
236 SDValue visitUDIV(SDNode *N);
237 SDValue visitSREM(SDNode *N);
238 SDValue visitUREM(SDNode *N);
239 SDValue visitMULHU(SDNode *N);
240 SDValue visitMULHS(SDNode *N);
241 SDValue visitSMUL_LOHI(SDNode *N);
242 SDValue visitUMUL_LOHI(SDNode *N);
243 SDValue visitSMULO(SDNode *N);
244 SDValue visitUMULO(SDNode *N);
245 SDValue visitSDIVREM(SDNode *N);
246 SDValue visitUDIVREM(SDNode *N);
247 SDValue visitAND(SDNode *N);
248 SDValue visitOR(SDNode *N);
249 SDValue visitXOR(SDNode *N);
250 SDValue SimplifyVBinOp(SDNode *N);
251 SDValue SimplifyVUnaryOp(SDNode *N);
252 SDValue visitSHL(SDNode *N);
253 SDValue visitSRA(SDNode *N);
254 SDValue visitSRL(SDNode *N);
255 SDValue visitRotate(SDNode *N);
256 SDValue visitCTLZ(SDNode *N);
257 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
258 SDValue visitCTTZ(SDNode *N);
259 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
260 SDValue visitCTPOP(SDNode *N);
261 SDValue visitSELECT(SDNode *N);
262 SDValue visitVSELECT(SDNode *N);
263 SDValue visitSELECT_CC(SDNode *N);
264 SDValue visitSETCC(SDNode *N);
265 SDValue visitSIGN_EXTEND(SDNode *N);
266 SDValue visitZERO_EXTEND(SDNode *N);
267 SDValue visitANY_EXTEND(SDNode *N);
268 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
269 SDValue visitTRUNCATE(SDNode *N);
270 SDValue visitBITCAST(SDNode *N);
271 SDValue visitBUILD_PAIR(SDNode *N);
272 SDValue visitFADD(SDNode *N);
273 SDValue visitFSUB(SDNode *N);
274 SDValue visitFMUL(SDNode *N);
275 SDValue visitFMA(SDNode *N);
276 SDValue visitFDIV(SDNode *N);
277 SDValue visitFREM(SDNode *N);
278 SDValue visitFCOPYSIGN(SDNode *N);
279 SDValue visitSINT_TO_FP(SDNode *N);
280 SDValue visitUINT_TO_FP(SDNode *N);
281 SDValue visitFP_TO_SINT(SDNode *N);
282 SDValue visitFP_TO_UINT(SDNode *N);
283 SDValue visitFP_ROUND(SDNode *N);
284 SDValue visitFP_ROUND_INREG(SDNode *N);
285 SDValue visitFP_EXTEND(SDNode *N);
286 SDValue visitFNEG(SDNode *N);
287 SDValue visitFABS(SDNode *N);
288 SDValue visitFCEIL(SDNode *N);
289 SDValue visitFTRUNC(SDNode *N);
290 SDValue visitFFLOOR(SDNode *N);
291 SDValue visitBRCOND(SDNode *N);
292 SDValue visitBR_CC(SDNode *N);
293 SDValue visitLOAD(SDNode *N);
294 SDValue visitSTORE(SDNode *N);
295 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
296 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
297 SDValue visitBUILD_VECTOR(SDNode *N);
298 SDValue visitCONCAT_VECTORS(SDNode *N);
299 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
300 SDValue visitVECTOR_SHUFFLE(SDNode *N);
301 SDValue visitINSERT_SUBVECTOR(SDNode *N);
303 SDValue XformToShuffleWithZero(SDNode *N);
304 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS);
306 SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
308 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
309 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
310 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
311 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
312 SDValue N3, ISD::CondCode CC,
313 bool NotExtCompare = false);
314 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
315 SDLoc DL, bool foldBooleans = true);
317 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
319 bool isOneUseSetCC(SDValue N) const;
321 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
323 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
324 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
325 SDValue BuildSDIV(SDNode *N);
326 SDValue BuildSDIVPow2(SDNode *N);
327 SDValue BuildUDIV(SDNode *N);
328 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
329 bool DemandHighBits = true);
330 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
331 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
332 SDValue InnerPos, SDValue InnerNeg,
333 unsigned PosOpcode, unsigned NegOpcode,
335 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL);
336 SDValue ReduceLoadWidth(SDNode *N);
337 SDValue ReduceLoadOpStoreWidth(SDNode *N);
338 SDValue TransformFPLoadStorePair(SDNode *N);
339 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
340 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
342 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
344 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
345 /// looking for aliasing nodes and adding them to the Aliases vector.
346 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
347 SmallVectorImpl<SDValue> &Aliases);
349 /// isAlias - Return true if there is any possibility that the two addresses
351 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const;
353 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
354 /// looking for a better chain (aliasing node.)
355 SDValue FindBetterChain(SDNode *N, SDValue Chain);
357 /// Merge consecutive store operations into a wide store.
358 /// This optimization uses wide integers or vectors when possible.
359 /// \return True if some memory operations were changed.
360 bool MergeConsecutiveStores(StoreSDNode *N);
362 /// \brief Try to transform a truncation where C is a constant:
363 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
365 /// \p N needs to be a truncation and its first operand an AND. Other
366 /// requirements are checked by the function (e.g. that trunc is
367 /// single-use) and if missed an empty SDValue is returned.
368 SDValue distributeTruncateThroughAnd(SDNode *N);
371 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
372 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
373 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {
374 AttributeSet FnAttrs =
375 DAG.getMachineFunction().getFunction()->getAttributes();
377 FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
378 Attribute::OptimizeForSize) ||
379 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
382 /// Run - runs the dag combiner on all nodes in the work list
383 void Run(CombineLevel AtLevel);
385 SelectionDAG &getDAG() const { return DAG; }
387 /// getShiftAmountTy - Returns a type large enough to hold any valid
388 /// shift amount - before type legalization these can be huge.
389 EVT getShiftAmountTy(EVT LHSTy) {
390 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
391 if (LHSTy.isVector())
393 return LegalTypes ? TLI.getScalarShiftAmountTy(LHSTy)
394 : TLI.getPointerTy();
397 /// isTypeLegal - This method returns true if we are running before type
398 /// legalization or if the specified VT is legal.
399 bool isTypeLegal(const EVT &VT) {
400 if (!LegalTypes) return true;
401 return TLI.isTypeLegal(VT);
404 /// getSetCCResultType - Convenience wrapper around
405 /// TargetLowering::getSetCCResultType
406 EVT getSetCCResultType(EVT VT) const {
407 return TLI.getSetCCResultType(*DAG.getContext(), VT);
414 /// WorklistRemover - This class is a DAGUpdateListener that removes any deleted
415 /// nodes from the worklist.
416 class WorklistRemover : public SelectionDAG::DAGUpdateListener {
419 explicit WorklistRemover(DAGCombiner &dc)
420 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
422 void NodeDeleted(SDNode *N, SDNode *E) override {
423 DC.removeFromWorklist(N);
428 //===----------------------------------------------------------------------===//
429 // TargetLowering::DAGCombinerInfo implementation
430 //===----------------------------------------------------------------------===//
432 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
433 ((DAGCombiner*)DC)->AddToWorklist(N);
436 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
437 ((DAGCombiner*)DC)->removeFromWorklist(N);
440 SDValue TargetLowering::DAGCombinerInfo::
441 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
442 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
445 SDValue TargetLowering::DAGCombinerInfo::
446 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
447 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
451 SDValue TargetLowering::DAGCombinerInfo::
452 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
453 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
456 void TargetLowering::DAGCombinerInfo::
457 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
458 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
461 //===----------------------------------------------------------------------===//
463 //===----------------------------------------------------------------------===//
465 void DAGCombiner::deleteAndRecombine(SDNode *N) {
466 removeFromWorklist(N);
468 // If the operands of this node are only used by the node, they will now be
469 // dead. Make sure to re-visit them and recursively delete dead nodes.
470 for (const SDValue &Op : N->ops())
472 AddToWorklist(Op.getNode());
477 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
478 /// specified expression for the same cost as the expression itself, or 2 if we
479 /// can compute the negated form more cheaply than the expression itself.
480 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
481 const TargetLowering &TLI,
482 const TargetOptions *Options,
483 unsigned Depth = 0) {
484 // fneg is removable even if it has multiple uses.
485 if (Op.getOpcode() == ISD::FNEG) return 2;
487 // Don't allow anything with multiple uses.
488 if (!Op.hasOneUse()) return 0;
490 // Don't recurse exponentially.
491 if (Depth > 6) return 0;
493 switch (Op.getOpcode()) {
494 default: return false;
495 case ISD::ConstantFP:
496 // Don't invert constant FP values after legalize. The negated constant
497 // isn't necessarily legal.
498 return LegalOperations ? 0 : 1;
500 // FIXME: determine better conditions for this xform.
501 if (!Options->UnsafeFPMath) return 0;
503 // After operation legalization, it might not be legal to create new FSUBs.
504 if (LegalOperations &&
505 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
508 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
509 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
512 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
513 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
516 // We can't turn -(A-B) into B-A when we honor signed zeros.
517 if (!Options->UnsafeFPMath) return 0;
519 // fold (fneg (fsub A, B)) -> (fsub B, A)
524 if (Options->HonorSignDependentRoundingFPMath()) return 0;
526 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
527 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
531 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
537 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
542 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
543 /// returns the newly negated expression.
544 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
545 bool LegalOperations, unsigned Depth = 0) {
546 // fneg is removable even if it has multiple uses.
547 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
549 // Don't allow anything with multiple uses.
550 assert(Op.hasOneUse() && "Unknown reuse!");
552 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
553 switch (Op.getOpcode()) {
554 default: llvm_unreachable("Unknown code");
555 case ISD::ConstantFP: {
556 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
558 return DAG.getConstantFP(V, Op.getValueType());
561 // FIXME: determine better conditions for this xform.
562 assert(DAG.getTarget().Options.UnsafeFPMath);
564 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
565 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
566 DAG.getTargetLoweringInfo(),
567 &DAG.getTarget().Options, Depth+1))
568 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
569 GetNegatedExpression(Op.getOperand(0), DAG,
570 LegalOperations, Depth+1),
572 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
573 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
574 GetNegatedExpression(Op.getOperand(1), DAG,
575 LegalOperations, Depth+1),
578 // We can't turn -(A-B) into B-A when we honor signed zeros.
579 assert(DAG.getTarget().Options.UnsafeFPMath);
581 // fold (fneg (fsub 0, B)) -> B
582 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
583 if (N0CFP->getValueAPF().isZero())
584 return Op.getOperand(1);
586 // fold (fneg (fsub A, B)) -> (fsub B, A)
587 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
588 Op.getOperand(1), Op.getOperand(0));
592 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
594 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
595 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
596 DAG.getTargetLoweringInfo(),
597 &DAG.getTarget().Options, Depth+1))
598 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
599 GetNegatedExpression(Op.getOperand(0), DAG,
600 LegalOperations, Depth+1),
603 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
604 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
606 GetNegatedExpression(Op.getOperand(1), DAG,
607 LegalOperations, Depth+1));
611 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
612 GetNegatedExpression(Op.getOperand(0), DAG,
613 LegalOperations, Depth+1));
615 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
616 GetNegatedExpression(Op.getOperand(0), DAG,
617 LegalOperations, Depth+1),
622 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
623 // that selects between the target values used for true and false, making it
624 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
625 // the appropriate nodes based on the type of node we are checking. This
626 // simplifies life a bit for the callers.
627 bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
629 if (N.getOpcode() == ISD::SETCC) {
630 LHS = N.getOperand(0);
631 RHS = N.getOperand(1);
632 CC = N.getOperand(2);
636 if (N.getOpcode() != ISD::SELECT_CC ||
637 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
638 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
641 LHS = N.getOperand(0);
642 RHS = N.getOperand(1);
643 CC = N.getOperand(4);
647 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
648 // one use. If this is true, it allows the users to invert the operation for
649 // free when it is profitable to do so.
650 bool DAGCombiner::isOneUseSetCC(SDValue N) const {
652 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
657 /// isConstantSplatVector - Returns true if N is a BUILD_VECTOR node whose
658 /// elements are all the same constant or undefined.
659 static bool isConstantSplatVector(SDNode *N, APInt& SplatValue) {
660 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(N);
665 unsigned SplatBitSize;
667 EVT EltVT = N->getValueType(0).getVectorElementType();
668 return (C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
670 EltVT.getSizeInBits() >= SplatBitSize);
673 // \brief Returns the SDNode if it is a constant BuildVector or constant.
674 static SDNode *isConstantBuildVectorOrConstantInt(SDValue N) {
675 if (isa<ConstantSDNode>(N))
677 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
678 if(BV && BV->isConstant())
683 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
685 static ConstantSDNode *isConstOrConstSplat(SDValue N) {
686 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
689 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
690 BitVector UndefElements;
691 ConstantSDNode *CN = BV->getConstantSplatNode(&UndefElements);
693 // BuildVectors can truncate their operands. Ignore that case here.
694 // FIXME: We blindly ignore splats which include undef which is overly
696 if (CN && UndefElements.none() &&
697 CN->getValueType(0) == N.getValueType().getScalarType())
704 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
706 static ConstantFPSDNode *isConstOrConstSplatFP(SDValue N) {
707 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
710 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
711 BitVector UndefElements;
712 ConstantFPSDNode *CN = BV->getConstantFPSplatNode(&UndefElements);
714 // BuildVectors can truncate their operands. Ignore that case here.
715 // FIXME: We blindly ignore splats which include undef which is overly
717 if (CN && UndefElements.none() &&
718 CN->getValueType(0) == N.getValueType().getScalarType())
725 SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL,
726 SDValue N0, SDValue N1) {
727 EVT VT = N0.getValueType();
728 if (N0.getOpcode() == Opc) {
729 if (SDNode *L = isConstantBuildVectorOrConstantInt(N0.getOperand(1))) {
730 if (SDNode *R = isConstantBuildVectorOrConstantInt(N1)) {
731 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
732 SDValue OpNode = DAG.FoldConstantArithmetic(Opc, VT, L, R);
733 if (!OpNode.getNode())
735 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
737 if (N0.hasOneUse()) {
738 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one
740 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
741 if (!OpNode.getNode())
743 AddToWorklist(OpNode.getNode());
744 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
749 if (N1.getOpcode() == Opc) {
750 if (SDNode *R = isConstantBuildVectorOrConstantInt(N1.getOperand(1))) {
751 if (SDNode *L = isConstantBuildVectorOrConstantInt(N0)) {
752 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
753 SDValue OpNode = DAG.FoldConstantArithmetic(Opc, VT, R, L);
754 if (!OpNode.getNode())
756 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
758 if (N1.hasOneUse()) {
759 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one
761 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N1.getOperand(0), N0);
762 if (!OpNode.getNode())
764 AddToWorklist(OpNode.getNode());
765 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
773 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
775 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
777 DEBUG(dbgs() << "\nReplacing.1 ";
779 dbgs() << "\nWith: ";
780 To[0].getNode()->dump(&DAG);
781 dbgs() << " and " << NumTo-1 << " other values\n";
782 for (unsigned i = 0, e = NumTo; i != e; ++i)
783 assert((!To[i].getNode() ||
784 N->getValueType(i) == To[i].getValueType()) &&
785 "Cannot combine value to value of different type!"));
786 WorklistRemover DeadNodes(*this);
787 DAG.ReplaceAllUsesWith(N, To);
789 // Push the new nodes and any users onto the worklist
790 for (unsigned i = 0, e = NumTo; i != e; ++i) {
791 if (To[i].getNode()) {
792 AddToWorklist(To[i].getNode());
793 AddUsersToWorklist(To[i].getNode());
798 // Finally, if the node is now dead, remove it from the graph. The node
799 // may not be dead if the replacement process recursively simplified to
800 // something else needing this node.
802 deleteAndRecombine(N);
803 return SDValue(N, 0);
807 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
808 // Replace all uses. If any nodes become isomorphic to other nodes and
809 // are deleted, make sure to remove them from our worklist.
810 WorklistRemover DeadNodes(*this);
811 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
813 // Push the new node and any (possibly new) users onto the worklist.
814 AddToWorklist(TLO.New.getNode());
815 AddUsersToWorklist(TLO.New.getNode());
817 // Finally, if the node is now dead, remove it from the graph. The node
818 // may not be dead if the replacement process recursively simplified to
819 // something else needing this node.
820 if (TLO.Old.getNode()->use_empty())
821 deleteAndRecombine(TLO.Old.getNode());
824 /// SimplifyDemandedBits - Check the specified integer node value to see if
825 /// it can be simplified or if things it uses can be simplified by bit
826 /// propagation. If so, return true.
827 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
828 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
829 APInt KnownZero, KnownOne;
830 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
834 AddToWorklist(Op.getNode());
836 // Replace the old value with the new one.
838 DEBUG(dbgs() << "\nReplacing.2 ";
839 TLO.Old.getNode()->dump(&DAG);
840 dbgs() << "\nWith: ";
841 TLO.New.getNode()->dump(&DAG);
844 CommitTargetLoweringOpt(TLO);
848 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
850 EVT VT = Load->getValueType(0);
851 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
853 DEBUG(dbgs() << "\nReplacing.9 ";
855 dbgs() << "\nWith: ";
856 Trunc.getNode()->dump(&DAG);
858 WorklistRemover DeadNodes(*this);
859 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
860 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
861 deleteAndRecombine(Load);
862 AddToWorklist(Trunc.getNode());
865 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
868 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
869 EVT MemVT = LD->getMemoryVT();
870 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
871 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
873 : LD->getExtensionType();
875 return DAG.getExtLoad(ExtType, dl, PVT,
876 LD->getChain(), LD->getBasePtr(),
877 MemVT, LD->getMemOperand());
880 unsigned Opc = Op.getOpcode();
883 case ISD::AssertSext:
884 return DAG.getNode(ISD::AssertSext, dl, PVT,
885 SExtPromoteOperand(Op.getOperand(0), PVT),
887 case ISD::AssertZext:
888 return DAG.getNode(ISD::AssertZext, dl, PVT,
889 ZExtPromoteOperand(Op.getOperand(0), PVT),
891 case ISD::Constant: {
893 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
894 return DAG.getNode(ExtOpc, dl, PVT, Op);
898 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
900 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
903 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
904 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
906 EVT OldVT = Op.getValueType();
908 bool Replace = false;
909 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
910 if (!NewOp.getNode())
912 AddToWorklist(NewOp.getNode());
915 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
916 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
917 DAG.getValueType(OldVT));
920 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
921 EVT OldVT = Op.getValueType();
923 bool Replace = false;
924 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
925 if (!NewOp.getNode())
927 AddToWorklist(NewOp.getNode());
930 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
931 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
934 /// PromoteIntBinOp - Promote the specified integer binary operation if the
935 /// target indicates it is beneficial. e.g. On x86, it's usually better to
936 /// promote i16 operations to i32 since i16 instructions are longer.
937 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
938 if (!LegalOperations)
941 EVT VT = Op.getValueType();
942 if (VT.isVector() || !VT.isInteger())
945 // If operation type is 'undesirable', e.g. i16 on x86, consider
947 unsigned Opc = Op.getOpcode();
948 if (TLI.isTypeDesirableForOp(Opc, VT))
952 // Consult target whether it is a good idea to promote this operation and
953 // what's the right type to promote it to.
954 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
955 assert(PVT != VT && "Don't know what type to promote to!");
957 bool Replace0 = false;
958 SDValue N0 = Op.getOperand(0);
959 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
963 bool Replace1 = false;
964 SDValue N1 = Op.getOperand(1);
969 NN1 = PromoteOperand(N1, PVT, Replace1);
974 AddToWorklist(NN0.getNode());
976 AddToWorklist(NN1.getNode());
979 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
981 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
983 DEBUG(dbgs() << "\nPromoting ";
984 Op.getNode()->dump(&DAG));
986 return DAG.getNode(ISD::TRUNCATE, dl, VT,
987 DAG.getNode(Opc, dl, PVT, NN0, NN1));
992 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
993 /// target indicates it is beneficial. e.g. On x86, it's usually better to
994 /// promote i16 operations to i32 since i16 instructions are longer.
995 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
996 if (!LegalOperations)
999 EVT VT = Op.getValueType();
1000 if (VT.isVector() || !VT.isInteger())
1003 // If operation type is 'undesirable', e.g. i16 on x86, consider
1005 unsigned Opc = Op.getOpcode();
1006 if (TLI.isTypeDesirableForOp(Opc, VT))
1010 // Consult target whether it is a good idea to promote this operation and
1011 // what's the right type to promote it to.
1012 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1013 assert(PVT != VT && "Don't know what type to promote to!");
1015 bool Replace = false;
1016 SDValue N0 = Op.getOperand(0);
1017 if (Opc == ISD::SRA)
1018 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
1019 else if (Opc == ISD::SRL)
1020 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
1022 N0 = PromoteOperand(N0, PVT, Replace);
1026 AddToWorklist(N0.getNode());
1028 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1030 DEBUG(dbgs() << "\nPromoting ";
1031 Op.getNode()->dump(&DAG));
1033 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1034 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
1039 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1040 if (!LegalOperations)
1043 EVT VT = Op.getValueType();
1044 if (VT.isVector() || !VT.isInteger())
1047 // If operation type is 'undesirable', e.g. i16 on x86, consider
1049 unsigned Opc = Op.getOpcode();
1050 if (TLI.isTypeDesirableForOp(Opc, VT))
1054 // Consult target whether it is a good idea to promote this operation and
1055 // what's the right type to promote it to.
1056 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1057 assert(PVT != VT && "Don't know what type to promote to!");
1058 // fold (aext (aext x)) -> (aext x)
1059 // fold (aext (zext x)) -> (zext x)
1060 // fold (aext (sext x)) -> (sext x)
1061 DEBUG(dbgs() << "\nPromoting ";
1062 Op.getNode()->dump(&DAG));
1063 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1068 bool DAGCombiner::PromoteLoad(SDValue Op) {
1069 if (!LegalOperations)
1072 EVT VT = Op.getValueType();
1073 if (VT.isVector() || !VT.isInteger())
1076 // If operation type is 'undesirable', e.g. i16 on x86, consider
1078 unsigned Opc = Op.getOpcode();
1079 if (TLI.isTypeDesirableForOp(Opc, VT))
1083 // Consult target whether it is a good idea to promote this operation and
1084 // what's the right type to promote it to.
1085 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1086 assert(PVT != VT && "Don't know what type to promote to!");
1089 SDNode *N = Op.getNode();
1090 LoadSDNode *LD = cast<LoadSDNode>(N);
1091 EVT MemVT = LD->getMemoryVT();
1092 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
1093 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
1095 : LD->getExtensionType();
1096 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
1097 LD->getChain(), LD->getBasePtr(),
1098 MemVT, LD->getMemOperand());
1099 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
1101 DEBUG(dbgs() << "\nPromoting ";
1104 Result.getNode()->dump(&DAG);
1106 WorklistRemover DeadNodes(*this);
1107 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1108 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1109 deleteAndRecombine(N);
1110 AddToWorklist(Result.getNode());
1116 /// \brief Recursively delete a node which has no uses and any operands for
1117 /// which it is the only use.
1119 /// Note that this both deletes the nodes and removes them from the worklist.
1120 /// It also adds any nodes who have had a user deleted to the worklist as they
1121 /// may now have only one use and subject to other combines.
1122 bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1123 if (!N->use_empty())
1126 SmallSetVector<SDNode *, 16> Nodes;
1129 N = Nodes.pop_back_val();
1133 if (N->use_empty()) {
1134 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1135 Nodes.insert(N->getOperand(i).getNode());
1137 removeFromWorklist(N);
1142 } while (!Nodes.empty());
1146 //===----------------------------------------------------------------------===//
1147 // Main DAG Combiner implementation
1148 //===----------------------------------------------------------------------===//
1150 void DAGCombiner::Run(CombineLevel AtLevel) {
1151 // set the instance variables, so that the various visit routines may use it.
1153 LegalOperations = Level >= AfterLegalizeVectorOps;
1154 LegalTypes = Level >= AfterLegalizeTypes;
1156 // Add all the dag nodes to the worklist.
1157 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
1158 E = DAG.allnodes_end(); I != E; ++I)
1161 // Create a dummy node (which is not added to allnodes), that adds a reference
1162 // to the root node, preventing it from being deleted, and tracking any
1163 // changes of the root.
1164 HandleSDNode Dummy(DAG.getRoot());
1166 // while the worklist isn't empty, find a node and
1167 // try and combine it.
1168 while (!WorklistMap.empty()) {
1170 // The Worklist holds the SDNodes in order, but it may contain null entries.
1172 N = Worklist.pop_back_val();
1175 bool GoodWorklistEntry = WorklistMap.erase(N);
1176 (void)GoodWorklistEntry;
1177 assert(GoodWorklistEntry &&
1178 "Found a worklist entry without a corresponding map entry!");
1180 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1181 // N is deleted from the DAG, since they too may now be dead or may have a
1182 // reduced number of uses, allowing other xforms.
1183 if (recursivelyDeleteUnusedNodes(N))
1186 WorklistRemover DeadNodes(*this);
1188 // If this combine is running after legalizing the DAG, re-legalize any
1189 // nodes pulled off the worklist.
1190 if (Level == AfterLegalizeDAG) {
1191 SmallSetVector<SDNode *, 16> UpdatedNodes;
1192 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1194 for (SDNode *LN : UpdatedNodes) {
1196 AddUsersToWorklist(LN);
1202 DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG));
1204 // Add any operands of the new node which have not yet been combined to the
1205 // worklist as well. Because the worklist uniques things already, this
1206 // won't repeatedly process the same operand.
1207 CombinedNodes.insert(N);
1208 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1209 if (!CombinedNodes.count(N->getOperand(i).getNode()))
1210 AddToWorklist(N->getOperand(i).getNode());
1212 SDValue RV = combine(N);
1219 // If we get back the same node we passed in, rather than a new node or
1220 // zero, we know that the node must have defined multiple values and
1221 // CombineTo was used. Since CombineTo takes care of the worklist
1222 // mechanics for us, we have no work to do in this case.
1223 if (RV.getNode() == N)
1226 assert(N->getOpcode() != ISD::DELETED_NODE &&
1227 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1228 "Node was deleted but visit returned new node!");
1230 DEBUG(dbgs() << " ... into: ";
1231 RV.getNode()->dump(&DAG));
1233 // Transfer debug value.
1234 DAG.TransferDbgValues(SDValue(N, 0), RV);
1235 if (N->getNumValues() == RV.getNode()->getNumValues())
1236 DAG.ReplaceAllUsesWith(N, RV.getNode());
1238 assert(N->getValueType(0) == RV.getValueType() &&
1239 N->getNumValues() == 1 && "Type mismatch");
1241 DAG.ReplaceAllUsesWith(N, &OpV);
1244 // Push the new node and any users onto the worklist
1245 AddToWorklist(RV.getNode());
1246 AddUsersToWorklist(RV.getNode());
1248 // Finally, if the node is now dead, remove it from the graph. The node
1249 // may not be dead if the replacement process recursively simplified to
1250 // something else needing this node. This will also take care of adding any
1251 // operands which have lost a user to the worklist.
1252 recursivelyDeleteUnusedNodes(N);
1255 // If the root changed (e.g. it was a dead load, update the root).
1256 DAG.setRoot(Dummy.getValue());
1257 DAG.RemoveDeadNodes();
1260 SDValue DAGCombiner::visit(SDNode *N) {
1261 switch (N->getOpcode()) {
1263 case ISD::TokenFactor: return visitTokenFactor(N);
1264 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1265 case ISD::ADD: return visitADD(N);
1266 case ISD::SUB: return visitSUB(N);
1267 case ISD::ADDC: return visitADDC(N);
1268 case ISD::SUBC: return visitSUBC(N);
1269 case ISD::ADDE: return visitADDE(N);
1270 case ISD::SUBE: return visitSUBE(N);
1271 case ISD::MUL: return visitMUL(N);
1272 case ISD::SDIV: return visitSDIV(N);
1273 case ISD::UDIV: return visitUDIV(N);
1274 case ISD::SREM: return visitSREM(N);
1275 case ISD::UREM: return visitUREM(N);
1276 case ISD::MULHU: return visitMULHU(N);
1277 case ISD::MULHS: return visitMULHS(N);
1278 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1279 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1280 case ISD::SMULO: return visitSMULO(N);
1281 case ISD::UMULO: return visitUMULO(N);
1282 case ISD::SDIVREM: return visitSDIVREM(N);
1283 case ISD::UDIVREM: return visitUDIVREM(N);
1284 case ISD::AND: return visitAND(N);
1285 case ISD::OR: return visitOR(N);
1286 case ISD::XOR: return visitXOR(N);
1287 case ISD::SHL: return visitSHL(N);
1288 case ISD::SRA: return visitSRA(N);
1289 case ISD::SRL: return visitSRL(N);
1291 case ISD::ROTL: return visitRotate(N);
1292 case ISD::CTLZ: return visitCTLZ(N);
1293 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1294 case ISD::CTTZ: return visitCTTZ(N);
1295 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1296 case ISD::CTPOP: return visitCTPOP(N);
1297 case ISD::SELECT: return visitSELECT(N);
1298 case ISD::VSELECT: return visitVSELECT(N);
1299 case ISD::SELECT_CC: return visitSELECT_CC(N);
1300 case ISD::SETCC: return visitSETCC(N);
1301 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1302 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1303 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1304 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1305 case ISD::TRUNCATE: return visitTRUNCATE(N);
1306 case ISD::BITCAST: return visitBITCAST(N);
1307 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1308 case ISD::FADD: return visitFADD(N);
1309 case ISD::FSUB: return visitFSUB(N);
1310 case ISD::FMUL: return visitFMUL(N);
1311 case ISD::FMA: return visitFMA(N);
1312 case ISD::FDIV: return visitFDIV(N);
1313 case ISD::FREM: return visitFREM(N);
1314 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1315 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1316 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1317 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1318 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1319 case ISD::FP_ROUND: return visitFP_ROUND(N);
1320 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1321 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1322 case ISD::FNEG: return visitFNEG(N);
1323 case ISD::FABS: return visitFABS(N);
1324 case ISD::FFLOOR: return visitFFLOOR(N);
1325 case ISD::FCEIL: return visitFCEIL(N);
1326 case ISD::FTRUNC: return visitFTRUNC(N);
1327 case ISD::BRCOND: return visitBRCOND(N);
1328 case ISD::BR_CC: return visitBR_CC(N);
1329 case ISD::LOAD: return visitLOAD(N);
1330 case ISD::STORE: return visitSTORE(N);
1331 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1332 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1333 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1334 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1335 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1336 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1337 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1342 SDValue DAGCombiner::combine(SDNode *N) {
1343 SDValue RV = visit(N);
1345 // If nothing happened, try a target-specific DAG combine.
1346 if (!RV.getNode()) {
1347 assert(N->getOpcode() != ISD::DELETED_NODE &&
1348 "Node was deleted but visit returned NULL!");
1350 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1351 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1353 // Expose the DAG combiner to the target combiner impls.
1354 TargetLowering::DAGCombinerInfo
1355 DagCombineInfo(DAG, Level, false, this);
1357 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1361 // If nothing happened still, try promoting the operation.
1362 if (!RV.getNode()) {
1363 switch (N->getOpcode()) {
1371 RV = PromoteIntBinOp(SDValue(N, 0));
1376 RV = PromoteIntShiftOp(SDValue(N, 0));
1378 case ISD::SIGN_EXTEND:
1379 case ISD::ZERO_EXTEND:
1380 case ISD::ANY_EXTEND:
1381 RV = PromoteExtend(SDValue(N, 0));
1384 if (PromoteLoad(SDValue(N, 0)))
1390 // If N is a commutative binary node, try commuting it to enable more
1392 if (!RV.getNode() && SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1393 N->getNumValues() == 1) {
1394 SDValue N0 = N->getOperand(0);
1395 SDValue N1 = N->getOperand(1);
1397 // Constant operands are canonicalized to RHS.
1398 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1399 SDValue Ops[] = {N1, N0};
1401 if (const BinaryWithFlagsSDNode *BinNode =
1402 dyn_cast<BinaryWithFlagsSDNode>(N)) {
1403 CSENode = DAG.getNodeIfExists(
1404 N->getOpcode(), N->getVTList(), Ops, BinNode->hasNoUnsignedWrap(),
1405 BinNode->hasNoSignedWrap(), BinNode->isExact());
1407 CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops);
1410 return SDValue(CSENode, 0);
1417 /// getInputChainForNode - Given a node, return its input chain if it has one,
1418 /// otherwise return a null sd operand.
1419 static SDValue getInputChainForNode(SDNode *N) {
1420 if (unsigned NumOps = N->getNumOperands()) {
1421 if (N->getOperand(0).getValueType() == MVT::Other)
1422 return N->getOperand(0);
1423 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1424 return N->getOperand(NumOps-1);
1425 for (unsigned i = 1; i < NumOps-1; ++i)
1426 if (N->getOperand(i).getValueType() == MVT::Other)
1427 return N->getOperand(i);
1432 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1433 // If N has two operands, where one has an input chain equal to the other,
1434 // the 'other' chain is redundant.
1435 if (N->getNumOperands() == 2) {
1436 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1437 return N->getOperand(0);
1438 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1439 return N->getOperand(1);
1442 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1443 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1444 SmallPtrSet<SDNode*, 16> SeenOps;
1445 bool Changed = false; // If we should replace this token factor.
1447 // Start out with this token factor.
1450 // Iterate through token factors. The TFs grows when new token factors are
1452 for (unsigned i = 0; i < TFs.size(); ++i) {
1453 SDNode *TF = TFs[i];
1455 // Check each of the operands.
1456 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1457 SDValue Op = TF->getOperand(i);
1459 switch (Op.getOpcode()) {
1460 case ISD::EntryToken:
1461 // Entry tokens don't need to be added to the list. They are
1466 case ISD::TokenFactor:
1467 if (Op.hasOneUse() &&
1468 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1469 // Queue up for processing.
1470 TFs.push_back(Op.getNode());
1471 // Clean up in case the token factor is removed.
1472 AddToWorklist(Op.getNode());
1479 // Only add if it isn't already in the list.
1480 if (SeenOps.insert(Op.getNode()))
1491 // If we've change things around then replace token factor.
1494 // The entry token is the only possible outcome.
1495 Result = DAG.getEntryNode();
1497 // New and improved token factor.
1498 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Ops);
1501 // Don't add users to work list.
1502 return CombineTo(N, Result, false);
1508 /// MERGE_VALUES can always be eliminated.
1509 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1510 WorklistRemover DeadNodes(*this);
1511 // Replacing results may cause a different MERGE_VALUES to suddenly
1512 // be CSE'd with N, and carry its uses with it. Iterate until no
1513 // uses remain, to ensure that the node can be safely deleted.
1514 // First add the users of this node to the work list so that they
1515 // can be tried again once they have new operands.
1516 AddUsersToWorklist(N);
1518 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1519 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1520 } while (!N->use_empty());
1521 deleteAndRecombine(N);
1522 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1526 SDValue combineShlAddConstant(SDLoc DL, SDValue N0, SDValue N1,
1527 SelectionDAG &DAG) {
1528 EVT VT = N0.getValueType();
1529 SDValue N00 = N0.getOperand(0);
1530 SDValue N01 = N0.getOperand(1);
1531 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1533 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1534 isa<ConstantSDNode>(N00.getOperand(1))) {
1535 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1536 N0 = DAG.getNode(ISD::ADD, SDLoc(N0), VT,
1537 DAG.getNode(ISD::SHL, SDLoc(N00), VT,
1538 N00.getOperand(0), N01),
1539 DAG.getNode(ISD::SHL, SDLoc(N01), VT,
1540 N00.getOperand(1), N01));
1541 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1547 SDValue DAGCombiner::visitADD(SDNode *N) {
1548 SDValue N0 = N->getOperand(0);
1549 SDValue N1 = N->getOperand(1);
1550 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1551 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1552 EVT VT = N0.getValueType();
1555 if (VT.isVector()) {
1556 SDValue FoldedVOp = SimplifyVBinOp(N);
1557 if (FoldedVOp.getNode()) return FoldedVOp;
1559 // fold (add x, 0) -> x, vector edition
1560 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1562 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1566 // fold (add x, undef) -> undef
1567 if (N0.getOpcode() == ISD::UNDEF)
1569 if (N1.getOpcode() == ISD::UNDEF)
1571 // fold (add c1, c2) -> c1+c2
1573 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1574 // canonicalize constant to RHS
1576 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1577 // fold (add x, 0) -> x
1578 if (N1C && N1C->isNullValue())
1580 // fold (add Sym, c) -> Sym+c
1581 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1582 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1583 GA->getOpcode() == ISD::GlobalAddress)
1584 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1586 (uint64_t)N1C->getSExtValue());
1587 // fold ((c1-A)+c2) -> (c1+c2)-A
1588 if (N1C && N0.getOpcode() == ISD::SUB)
1589 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1590 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1591 DAG.getConstant(N1C->getAPIntValue()+
1592 N0C->getAPIntValue(), VT),
1595 SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1);
1598 // fold ((0-A) + B) -> B-A
1599 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1600 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1601 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1602 // fold (A + (0-B)) -> A-B
1603 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1604 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1605 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1606 // fold (A+(B-A)) -> B
1607 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1608 return N1.getOperand(0);
1609 // fold ((B-A)+A) -> B
1610 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1611 return N0.getOperand(0);
1612 // fold (A+(B-(A+C))) to (B-C)
1613 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1614 N0 == N1.getOperand(1).getOperand(0))
1615 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1616 N1.getOperand(1).getOperand(1));
1617 // fold (A+(B-(C+A))) to (B-C)
1618 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1619 N0 == N1.getOperand(1).getOperand(1))
1620 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1621 N1.getOperand(1).getOperand(0));
1622 // fold (A+((B-A)+or-C)) to (B+or-C)
1623 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1624 N1.getOperand(0).getOpcode() == ISD::SUB &&
1625 N0 == N1.getOperand(0).getOperand(1))
1626 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT,
1627 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1629 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1630 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1631 SDValue N00 = N0.getOperand(0);
1632 SDValue N01 = N0.getOperand(1);
1633 SDValue N10 = N1.getOperand(0);
1634 SDValue N11 = N1.getOperand(1);
1636 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1637 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1638 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1639 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
1642 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1643 return SDValue(N, 0);
1645 // fold (a+b) -> (a|b) iff a and b share no bits.
1646 if (VT.isInteger() && !VT.isVector()) {
1647 APInt LHSZero, LHSOne;
1648 APInt RHSZero, RHSOne;
1649 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1651 if (LHSZero.getBoolValue()) {
1652 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1654 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1655 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1656 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero){
1657 if (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT))
1658 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1663 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1664 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1665 SDValue Result = combineShlAddConstant(SDLoc(N), N0, N1, DAG);
1666 if (Result.getNode()) return Result;
1668 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1669 SDValue Result = combineShlAddConstant(SDLoc(N), N1, N0, DAG);
1670 if (Result.getNode()) return Result;
1673 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1674 if (N1.getOpcode() == ISD::SHL &&
1675 N1.getOperand(0).getOpcode() == ISD::SUB)
1676 if (ConstantSDNode *C =
1677 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1678 if (C->getAPIntValue() == 0)
1679 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1680 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1681 N1.getOperand(0).getOperand(1),
1683 if (N0.getOpcode() == ISD::SHL &&
1684 N0.getOperand(0).getOpcode() == ISD::SUB)
1685 if (ConstantSDNode *C =
1686 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1687 if (C->getAPIntValue() == 0)
1688 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1,
1689 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1690 N0.getOperand(0).getOperand(1),
1693 if (N1.getOpcode() == ISD::AND) {
1694 SDValue AndOp0 = N1.getOperand(0);
1695 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1696 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1697 unsigned DestBits = VT.getScalarType().getSizeInBits();
1699 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1700 // and similar xforms where the inner op is either ~0 or 0.
1701 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1703 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1707 // add (sext i1), X -> sub X, (zext i1)
1708 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1709 N0.getOperand(0).getValueType() == MVT::i1 &&
1710 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1712 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1713 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1719 SDValue DAGCombiner::visitADDC(SDNode *N) {
1720 SDValue N0 = N->getOperand(0);
1721 SDValue N1 = N->getOperand(1);
1722 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1723 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1724 EVT VT = N0.getValueType();
1726 // If the flag result is dead, turn this into an ADD.
1727 if (!N->hasAnyUseOfValue(1))
1728 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1729 DAG.getNode(ISD::CARRY_FALSE,
1730 SDLoc(N), MVT::Glue));
1732 // canonicalize constant to RHS.
1734 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1736 // fold (addc x, 0) -> x + no carry out
1737 if (N1C && N1C->isNullValue())
1738 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1739 SDLoc(N), MVT::Glue));
1741 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1742 APInt LHSZero, LHSOne;
1743 APInt RHSZero, RHSOne;
1744 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1746 if (LHSZero.getBoolValue()) {
1747 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1749 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1750 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1751 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1752 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1753 DAG.getNode(ISD::CARRY_FALSE,
1754 SDLoc(N), MVT::Glue));
1760 SDValue DAGCombiner::visitADDE(SDNode *N) {
1761 SDValue N0 = N->getOperand(0);
1762 SDValue N1 = N->getOperand(1);
1763 SDValue CarryIn = N->getOperand(2);
1764 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1765 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1767 // canonicalize constant to RHS
1769 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
1772 // fold (adde x, y, false) -> (addc x, y)
1773 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1774 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1779 // Since it may not be valid to emit a fold to zero for vector initializers
1780 // check if we can before folding.
1781 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT,
1783 bool LegalOperations, bool LegalTypes) {
1785 return DAG.getConstant(0, VT);
1786 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
1787 return DAG.getConstant(0, VT);
1791 SDValue DAGCombiner::visitSUB(SDNode *N) {
1792 SDValue N0 = N->getOperand(0);
1793 SDValue N1 = N->getOperand(1);
1794 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1796 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? nullptr :
1797 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1798 EVT VT = N0.getValueType();
1801 if (VT.isVector()) {
1802 SDValue FoldedVOp = SimplifyVBinOp(N);
1803 if (FoldedVOp.getNode()) return FoldedVOp;
1805 // fold (sub x, 0) -> x, vector edition
1806 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1810 // fold (sub x, x) -> 0
1811 // FIXME: Refactor this and xor and other similar operations together.
1813 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
1814 // fold (sub c1, c2) -> c1-c2
1816 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1817 // fold (sub x, c) -> (add x, -c)
1819 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0,
1820 DAG.getConstant(-N1C->getAPIntValue(), VT));
1821 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1822 if (N0C && N0C->isAllOnesValue())
1823 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1824 // fold A-(A-B) -> B
1825 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1826 return N1.getOperand(1);
1827 // fold (A+B)-A -> B
1828 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1829 return N0.getOperand(1);
1830 // fold (A+B)-B -> A
1831 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1832 return N0.getOperand(0);
1833 // fold C2-(A+C1) -> (C2-C1)-A
1834 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1835 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1837 return DAG.getNode(ISD::SUB, SDLoc(N), VT, NewC,
1840 // fold ((A+(B+or-C))-B) -> A+or-C
1841 if (N0.getOpcode() == ISD::ADD &&
1842 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1843 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1844 N0.getOperand(1).getOperand(0) == N1)
1845 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1846 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1847 // fold ((A+(C+B))-B) -> A+C
1848 if (N0.getOpcode() == ISD::ADD &&
1849 N0.getOperand(1).getOpcode() == ISD::ADD &&
1850 N0.getOperand(1).getOperand(1) == N1)
1851 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1852 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1853 // fold ((A-(B-C))-C) -> A-B
1854 if (N0.getOpcode() == ISD::SUB &&
1855 N0.getOperand(1).getOpcode() == ISD::SUB &&
1856 N0.getOperand(1).getOperand(1) == N1)
1857 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1858 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1860 // If either operand of a sub is undef, the result is undef
1861 if (N0.getOpcode() == ISD::UNDEF)
1863 if (N1.getOpcode() == ISD::UNDEF)
1866 // If the relocation model supports it, consider symbol offsets.
1867 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1868 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1869 // fold (sub Sym, c) -> Sym-c
1870 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1871 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1873 (uint64_t)N1C->getSExtValue());
1874 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1875 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1876 if (GA->getGlobal() == GB->getGlobal())
1877 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1884 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1885 SDValue N0 = N->getOperand(0);
1886 SDValue N1 = N->getOperand(1);
1887 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1888 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1889 EVT VT = N0.getValueType();
1891 // If the flag result is dead, turn this into an SUB.
1892 if (!N->hasAnyUseOfValue(1))
1893 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1),
1894 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1897 // fold (subc x, x) -> 0 + no borrow
1899 return CombineTo(N, DAG.getConstant(0, VT),
1900 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1903 // fold (subc x, 0) -> x + no borrow
1904 if (N1C && N1C->isNullValue())
1905 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1908 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1909 if (N0C && N0C->isAllOnesValue())
1910 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
1911 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1917 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1918 SDValue N0 = N->getOperand(0);
1919 SDValue N1 = N->getOperand(1);
1920 SDValue CarryIn = N->getOperand(2);
1922 // fold (sube x, y, false) -> (subc x, y)
1923 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1924 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
1929 SDValue DAGCombiner::visitMUL(SDNode *N) {
1930 SDValue N0 = N->getOperand(0);
1931 SDValue N1 = N->getOperand(1);
1932 EVT VT = N0.getValueType();
1934 // fold (mul x, undef) -> 0
1935 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1936 return DAG.getConstant(0, VT);
1938 bool N0IsConst = false;
1939 bool N1IsConst = false;
1940 APInt ConstValue0, ConstValue1;
1942 if (VT.isVector()) {
1943 SDValue FoldedVOp = SimplifyVBinOp(N);
1944 if (FoldedVOp.getNode()) return FoldedVOp;
1946 N0IsConst = isConstantSplatVector(N0.getNode(), ConstValue0);
1947 N1IsConst = isConstantSplatVector(N1.getNode(), ConstValue1);
1949 N0IsConst = dyn_cast<ConstantSDNode>(N0) != nullptr;
1950 ConstValue0 = N0IsConst ? (dyn_cast<ConstantSDNode>(N0))->getAPIntValue()
1952 N1IsConst = dyn_cast<ConstantSDNode>(N1) != nullptr;
1953 ConstValue1 = N1IsConst ? (dyn_cast<ConstantSDNode>(N1))->getAPIntValue()
1957 // fold (mul c1, c2) -> c1*c2
1958 if (N0IsConst && N1IsConst)
1959 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0.getNode(), N1.getNode());
1961 // canonicalize constant to RHS
1962 if (N0IsConst && !N1IsConst)
1963 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
1964 // fold (mul x, 0) -> 0
1965 if (N1IsConst && ConstValue1 == 0)
1967 // We require a splat of the entire scalar bit width for non-contiguous
1970 ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits();
1971 // fold (mul x, 1) -> x
1972 if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
1974 // fold (mul x, -1) -> 0-x
1975 if (N1IsConst && ConstValue1.isAllOnesValue())
1976 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1977 DAG.getConstant(0, VT), N0);
1978 // fold (mul x, (1 << c)) -> x << c
1979 if (N1IsConst && ConstValue1.isPowerOf2() && IsFullSplat)
1980 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1981 DAG.getConstant(ConstValue1.logBase2(),
1982 getShiftAmountTy(N0.getValueType())));
1983 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1984 if (N1IsConst && (-ConstValue1).isPowerOf2() && IsFullSplat) {
1985 unsigned Log2Val = (-ConstValue1).logBase2();
1986 // FIXME: If the input is something that is easily negated (e.g. a
1987 // single-use add), we should put the negate there.
1988 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1989 DAG.getConstant(0, VT),
1990 DAG.getNode(ISD::SHL, SDLoc(N), VT, N0,
1991 DAG.getConstant(Log2Val,
1992 getShiftAmountTy(N0.getValueType()))));
1996 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1997 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
1998 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
1999 isa<ConstantSDNode>(N0.getOperand(1)))) {
2000 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT,
2001 N1, N0.getOperand(1));
2002 AddToWorklist(C3.getNode());
2003 return DAG.getNode(ISD::MUL, SDLoc(N), VT,
2004 N0.getOperand(0), C3);
2007 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
2010 SDValue Sh(nullptr,0), Y(nullptr,0);
2011 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
2012 if (N0.getOpcode() == ISD::SHL &&
2013 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2014 isa<ConstantSDNode>(N0.getOperand(1))) &&
2015 N0.getNode()->hasOneUse()) {
2017 } else if (N1.getOpcode() == ISD::SHL &&
2018 isa<ConstantSDNode>(N1.getOperand(1)) &&
2019 N1.getNode()->hasOneUse()) {
2024 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2025 Sh.getOperand(0), Y);
2026 return DAG.getNode(ISD::SHL, SDLoc(N), VT,
2027 Mul, Sh.getOperand(1));
2031 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
2032 if (N1IsConst && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
2033 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2034 isa<ConstantSDNode>(N0.getOperand(1))))
2035 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
2036 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
2037 N0.getOperand(0), N1),
2038 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
2039 N0.getOperand(1), N1));
2042 SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1);
2049 SDValue DAGCombiner::visitSDIV(SDNode *N) {
2050 SDValue N0 = N->getOperand(0);
2051 SDValue N1 = N->getOperand(1);
2052 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2053 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2054 EVT VT = N->getValueType(0);
2057 if (VT.isVector()) {
2058 SDValue FoldedVOp = SimplifyVBinOp(N);
2059 if (FoldedVOp.getNode()) return FoldedVOp;
2062 // fold (sdiv c1, c2) -> c1/c2
2063 if (N0C && N1C && !N1C->isNullValue())
2064 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
2065 // fold (sdiv X, 1) -> X
2066 if (N1C && N1C->getAPIntValue() == 1LL)
2068 // fold (sdiv X, -1) -> 0-X
2069 if (N1C && N1C->isAllOnesValue())
2070 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
2071 DAG.getConstant(0, VT), N0);
2072 // If we know the sign bits of both operands are zero, strength reduce to a
2073 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
2074 if (!VT.isVector()) {
2075 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2076 return DAG.getNode(ISD::UDIV, SDLoc(N), N1.getValueType(),
2080 // fold (sdiv X, pow2) -> simple ops after legalize
2081 if (N1C && !N1C->isNullValue() && (N1C->getAPIntValue().isPowerOf2() ||
2082 (-N1C->getAPIntValue()).isPowerOf2())) {
2083 // If dividing by powers of two is cheap, then don't perform the following
2085 if (TLI.isPow2SDivCheap())
2088 // Target-specific implementation of sdiv x, pow2.
2089 SDValue Res = BuildSDIVPow2(N);
2093 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
2095 // Splat the sign bit into the register
2097 DAG.getNode(ISD::SRA, SDLoc(N), VT, N0,
2098 DAG.getConstant(VT.getScalarSizeInBits() - 1,
2099 getShiftAmountTy(N0.getValueType())));
2100 AddToWorklist(SGN.getNode());
2102 // Add (N0 < 0) ? abs2 - 1 : 0;
2104 DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN,
2105 DAG.getConstant(VT.getScalarSizeInBits() - lg2,
2106 getShiftAmountTy(SGN.getValueType())));
2107 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL);
2108 AddToWorklist(SRL.getNode());
2109 AddToWorklist(ADD.getNode()); // Divide by pow2
2110 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD,
2111 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
2113 // If we're dividing by a positive value, we're done. Otherwise, we must
2114 // negate the result.
2115 if (N1C->getAPIntValue().isNonNegative())
2118 AddToWorklist(SRA.getNode());
2119 return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), SRA);
2122 // if integer divide is expensive and we satisfy the requirements, emit an
2123 // alternate sequence.
2124 if (N1C && !TLI.isIntDivCheap()) {
2125 SDValue Op = BuildSDIV(N);
2126 if (Op.getNode()) return Op;
2130 if (N0.getOpcode() == ISD::UNDEF)
2131 return DAG.getConstant(0, VT);
2132 // X / undef -> undef
2133 if (N1.getOpcode() == ISD::UNDEF)
2139 SDValue DAGCombiner::visitUDIV(SDNode *N) {
2140 SDValue N0 = N->getOperand(0);
2141 SDValue N1 = N->getOperand(1);
2142 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2143 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2144 EVT VT = N->getValueType(0);
2147 if (VT.isVector()) {
2148 SDValue FoldedVOp = SimplifyVBinOp(N);
2149 if (FoldedVOp.getNode()) return FoldedVOp;
2152 // fold (udiv c1, c2) -> c1/c2
2153 if (N0C && N1C && !N1C->isNullValue())
2154 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
2155 // fold (udiv x, (1 << c)) -> x >>u c
2156 if (N1C && N1C->getAPIntValue().isPowerOf2())
2157 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0,
2158 DAG.getConstant(N1C->getAPIntValue().logBase2(),
2159 getShiftAmountTy(N0.getValueType())));
2160 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
2161 if (N1.getOpcode() == ISD::SHL) {
2162 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2163 if (SHC->getAPIntValue().isPowerOf2()) {
2164 EVT ADDVT = N1.getOperand(1).getValueType();
2165 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N), ADDVT,
2167 DAG.getConstant(SHC->getAPIntValue()
2170 AddToWorklist(Add.getNode());
2171 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add);
2175 // fold (udiv x, c) -> alternate
2176 if (N1C && !TLI.isIntDivCheap()) {
2177 SDValue Op = BuildUDIV(N);
2178 if (Op.getNode()) return Op;
2182 if (N0.getOpcode() == ISD::UNDEF)
2183 return DAG.getConstant(0, VT);
2184 // X / undef -> undef
2185 if (N1.getOpcode() == ISD::UNDEF)
2191 SDValue DAGCombiner::visitSREM(SDNode *N) {
2192 SDValue N0 = N->getOperand(0);
2193 SDValue N1 = N->getOperand(1);
2194 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2195 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2196 EVT VT = N->getValueType(0);
2198 // fold (srem c1, c2) -> c1%c2
2199 if (N0C && N1C && !N1C->isNullValue())
2200 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
2201 // If we know the sign bits of both operands are zero, strength reduce to a
2202 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
2203 if (!VT.isVector()) {
2204 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2205 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1);
2208 // If X/C can be simplified by the division-by-constant logic, lower
2209 // X%C to the equivalent of X-X/C*C.
2210 if (N1C && !N1C->isNullValue()) {
2211 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1);
2212 AddToWorklist(Div.getNode());
2213 SDValue OptimizedDiv = combine(Div.getNode());
2214 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2215 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2217 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2218 AddToWorklist(Mul.getNode());
2224 if (N0.getOpcode() == ISD::UNDEF)
2225 return DAG.getConstant(0, VT);
2226 // X % undef -> undef
2227 if (N1.getOpcode() == ISD::UNDEF)
2233 SDValue DAGCombiner::visitUREM(SDNode *N) {
2234 SDValue N0 = N->getOperand(0);
2235 SDValue N1 = N->getOperand(1);
2236 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2237 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2238 EVT VT = N->getValueType(0);
2240 // fold (urem c1, c2) -> c1%c2
2241 if (N0C && N1C && !N1C->isNullValue())
2242 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2243 // fold (urem x, pow2) -> (and x, pow2-1)
2244 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2245 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0,
2246 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2247 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2248 if (N1.getOpcode() == ISD::SHL) {
2249 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2250 if (SHC->getAPIntValue().isPowerOf2()) {
2252 DAG.getNode(ISD::ADD, SDLoc(N), VT, N1,
2253 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2255 AddToWorklist(Add.getNode());
2256 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, Add);
2261 // If X/C can be simplified by the division-by-constant logic, lower
2262 // X%C to the equivalent of X-X/C*C.
2263 if (N1C && !N1C->isNullValue()) {
2264 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1);
2265 AddToWorklist(Div.getNode());
2266 SDValue OptimizedDiv = combine(Div.getNode());
2267 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2268 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2270 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2271 AddToWorklist(Mul.getNode());
2277 if (N0.getOpcode() == ISD::UNDEF)
2278 return DAG.getConstant(0, VT);
2279 // X % undef -> undef
2280 if (N1.getOpcode() == ISD::UNDEF)
2286 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2287 SDValue N0 = N->getOperand(0);
2288 SDValue N1 = N->getOperand(1);
2289 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2290 EVT VT = N->getValueType(0);
2293 // fold (mulhs x, 0) -> 0
2294 if (N1C && N1C->isNullValue())
2296 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2297 if (N1C && N1C->getAPIntValue() == 1)
2298 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0,
2299 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2300 getShiftAmountTy(N0.getValueType())));
2301 // fold (mulhs x, undef) -> 0
2302 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2303 return DAG.getConstant(0, VT);
2305 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2307 if (VT.isSimple() && !VT.isVector()) {
2308 MVT Simple = VT.getSimpleVT();
2309 unsigned SimpleSize = Simple.getSizeInBits();
2310 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2311 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2312 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2313 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2314 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2315 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2316 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2317 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2324 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2325 SDValue N0 = N->getOperand(0);
2326 SDValue N1 = N->getOperand(1);
2327 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2328 EVT VT = N->getValueType(0);
2331 // fold (mulhu x, 0) -> 0
2332 if (N1C && N1C->isNullValue())
2334 // fold (mulhu x, 1) -> 0
2335 if (N1C && N1C->getAPIntValue() == 1)
2336 return DAG.getConstant(0, N0.getValueType());
2337 // fold (mulhu x, undef) -> 0
2338 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2339 return DAG.getConstant(0, VT);
2341 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2343 if (VT.isSimple() && !VT.isVector()) {
2344 MVT Simple = VT.getSimpleVT();
2345 unsigned SimpleSize = Simple.getSizeInBits();
2346 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2347 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2348 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2349 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2350 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2351 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2352 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2353 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2360 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2361 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2362 /// that are being performed. Return true if a simplification was made.
2364 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2366 // If the high half is not needed, just compute the low half.
2367 bool HiExists = N->hasAnyUseOfValue(1);
2369 (!LegalOperations ||
2370 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
2371 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2372 return CombineTo(N, Res, Res);
2375 // If the low half is not needed, just compute the high half.
2376 bool LoExists = N->hasAnyUseOfValue(0);
2378 (!LegalOperations ||
2379 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2380 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2381 return CombineTo(N, Res, Res);
2384 // If both halves are used, return as it is.
2385 if (LoExists && HiExists)
2388 // If the two computed results can be simplified separately, separate them.
2390 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2391 AddToWorklist(Lo.getNode());
2392 SDValue LoOpt = combine(Lo.getNode());
2393 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2394 (!LegalOperations ||
2395 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2396 return CombineTo(N, LoOpt, LoOpt);
2400 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2401 AddToWorklist(Hi.getNode());
2402 SDValue HiOpt = combine(Hi.getNode());
2403 if (HiOpt.getNode() && HiOpt != Hi &&
2404 (!LegalOperations ||
2405 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2406 return CombineTo(N, HiOpt, HiOpt);
2412 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2413 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2414 if (Res.getNode()) return Res;
2416 EVT VT = N->getValueType(0);
2419 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2421 if (VT.isSimple() && !VT.isVector()) {
2422 MVT Simple = VT.getSimpleVT();
2423 unsigned SimpleSize = Simple.getSizeInBits();
2424 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2425 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2426 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2427 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2428 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2429 // Compute the high part as N1.
2430 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2431 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2432 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2433 // Compute the low part as N0.
2434 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2435 return CombineTo(N, Lo, Hi);
2442 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2443 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2444 if (Res.getNode()) return Res;
2446 EVT VT = N->getValueType(0);
2449 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2451 if (VT.isSimple() && !VT.isVector()) {
2452 MVT Simple = VT.getSimpleVT();
2453 unsigned SimpleSize = Simple.getSizeInBits();
2454 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2455 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2456 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2457 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2458 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2459 // Compute the high part as N1.
2460 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2461 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2462 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2463 // Compute the low part as N0.
2464 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2465 return CombineTo(N, Lo, Hi);
2472 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2473 // (smulo x, 2) -> (saddo x, x)
2474 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2475 if (C2->getAPIntValue() == 2)
2476 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
2477 N->getOperand(0), N->getOperand(0));
2482 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2483 // (umulo x, 2) -> (uaddo x, x)
2484 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2485 if (C2->getAPIntValue() == 2)
2486 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
2487 N->getOperand(0), N->getOperand(0));
2492 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2493 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2494 if (Res.getNode()) return Res;
2499 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2500 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2501 if (Res.getNode()) return Res;
2506 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2507 /// two operands of the same opcode, try to simplify it.
2508 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2509 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2510 EVT VT = N0.getValueType();
2511 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2513 // Bail early if none of these transforms apply.
2514 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2516 // For each of OP in AND/OR/XOR:
2517 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2518 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2519 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2520 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2522 // do not sink logical op inside of a vector extend, since it may combine
2524 EVT Op0VT = N0.getOperand(0).getValueType();
2525 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2526 N0.getOpcode() == ISD::SIGN_EXTEND ||
2527 // Avoid infinite looping with PromoteIntBinOp.
2528 (N0.getOpcode() == ISD::ANY_EXTEND &&
2529 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2530 (N0.getOpcode() == ISD::TRUNCATE &&
2531 (!TLI.isZExtFree(VT, Op0VT) ||
2532 !TLI.isTruncateFree(Op0VT, VT)) &&
2533 TLI.isTypeLegal(Op0VT))) &&
2535 Op0VT == N1.getOperand(0).getValueType() &&
2536 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2537 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2538 N0.getOperand(0).getValueType(),
2539 N0.getOperand(0), N1.getOperand(0));
2540 AddToWorklist(ORNode.getNode());
2541 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2544 // For each of OP in SHL/SRL/SRA/AND...
2545 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2546 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2547 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2548 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2549 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2550 N0.getOperand(1) == N1.getOperand(1)) {
2551 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2552 N0.getOperand(0).getValueType(),
2553 N0.getOperand(0), N1.getOperand(0));
2554 AddToWorklist(ORNode.getNode());
2555 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2556 ORNode, N0.getOperand(1));
2559 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2560 // Only perform this optimization after type legalization and before
2561 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2562 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2563 // we don't want to undo this promotion.
2564 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2566 if ((N0.getOpcode() == ISD::BITCAST ||
2567 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2568 Level == AfterLegalizeTypes) {
2569 SDValue In0 = N0.getOperand(0);
2570 SDValue In1 = N1.getOperand(0);
2571 EVT In0Ty = In0.getValueType();
2572 EVT In1Ty = In1.getValueType();
2574 // If both incoming values are integers, and the original types are the
2576 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2577 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2578 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2579 AddToWorklist(Op.getNode());
2584 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2585 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2586 // If both shuffles use the same mask, and both shuffle within a single
2587 // vector, then it is worthwhile to move the swizzle after the operation.
2588 // The type-legalizer generates this pattern when loading illegal
2589 // vector types from memory. In many cases this allows additional shuffle
2591 // There are other cases where moving the shuffle after the xor/and/or
2592 // is profitable even if shuffles don't perform a swizzle.
2593 // If both shuffles use the same mask, and both shuffles have the same first
2594 // or second operand, then it might still be profitable to move the shuffle
2595 // after the xor/and/or operation.
2596 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
2597 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2598 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2600 assert(N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
2601 "Inputs to shuffles are not the same type");
2603 // Check that both shuffles use the same mask. The masks are known to be of
2604 // the same length because the result vector type is the same.
2605 // Check also that shuffles have only one use to avoid introducing extra
2607 if (SVN0->hasOneUse() && SVN1->hasOneUse() &&
2608 SVN0->getMask().equals(SVN1->getMask())) {
2609 SDValue ShOp = N0->getOperand(1);
2611 // Don't try to fold this node if it requires introducing a
2612 // build vector of all zeros that might be illegal at this stage.
2613 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2615 ShOp = DAG.getConstant(0, VT);
2620 // (AND (shuf (A, C), shuf (B, C)) -> shuf (AND (A, B), C)
2621 // (OR (shuf (A, C), shuf (B, C)) -> shuf (OR (A, B), C)
2622 // (XOR (shuf (A, C), shuf (B, C)) -> shuf (XOR (A, B), V_0)
2623 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
2624 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2625 N0->getOperand(0), N1->getOperand(0));
2626 AddToWorklist(NewNode.getNode());
2627 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp,
2628 &SVN0->getMask()[0]);
2631 // Don't try to fold this node if it requires introducing a
2632 // build vector of all zeros that might be illegal at this stage.
2633 ShOp = N0->getOperand(0);
2634 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2636 ShOp = DAG.getConstant(0, VT);
2641 // (AND (shuf (C, A), shuf (C, B)) -> shuf (C, AND (A, B))
2642 // (OR (shuf (C, A), shuf (C, B)) -> shuf (C, OR (A, B))
2643 // (XOR (shuf (C, A), shuf (C, B)) -> shuf (V_0, XOR (A, B))
2644 if (N0->getOperand(0) == N1->getOperand(0) && ShOp.getNode()) {
2645 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2646 N0->getOperand(1), N1->getOperand(1));
2647 AddToWorklist(NewNode.getNode());
2648 return DAG.getVectorShuffle(VT, SDLoc(N), ShOp, NewNode,
2649 &SVN0->getMask()[0]);
2657 SDValue DAGCombiner::visitAND(SDNode *N) {
2658 SDValue N0 = N->getOperand(0);
2659 SDValue N1 = N->getOperand(1);
2660 SDValue LL, LR, RL, RR, CC0, CC1;
2661 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2662 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2663 EVT VT = N1.getValueType();
2664 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2667 if (VT.isVector()) {
2668 SDValue FoldedVOp = SimplifyVBinOp(N);
2669 if (FoldedVOp.getNode()) return FoldedVOp;
2671 // fold (and x, 0) -> 0, vector edition
2672 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2674 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2677 // fold (and x, -1) -> x, vector edition
2678 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2680 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2684 // fold (and x, undef) -> 0
2685 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2686 return DAG.getConstant(0, VT);
2687 // fold (and c1, c2) -> c1&c2
2689 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2690 // canonicalize constant to RHS
2692 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
2693 // fold (and x, -1) -> x
2694 if (N1C && N1C->isAllOnesValue())
2696 // if (and x, c) is known to be zero, return 0
2697 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2698 APInt::getAllOnesValue(BitWidth)))
2699 return DAG.getConstant(0, VT);
2701 SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1);
2704 // fold (and (or x, C), D) -> D if (C & D) == D
2705 if (N1C && N0.getOpcode() == ISD::OR)
2706 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2707 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2709 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2710 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2711 SDValue N0Op0 = N0.getOperand(0);
2712 APInt Mask = ~N1C->getAPIntValue();
2713 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2714 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2715 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2716 N0.getValueType(), N0Op0);
2718 // Replace uses of the AND with uses of the Zero extend node.
2721 // We actually want to replace all uses of the any_extend with the
2722 // zero_extend, to avoid duplicating things. This will later cause this
2723 // AND to be folded.
2724 CombineTo(N0.getNode(), Zext);
2725 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2728 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2729 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2730 // already be zero by virtue of the width of the base type of the load.
2732 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2734 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2735 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2736 N0.getOpcode() == ISD::LOAD) {
2737 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2738 N0 : N0.getOperand(0) );
2740 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2741 // This can be a pure constant or a vector splat, in which case we treat the
2742 // vector as a scalar and use the splat value.
2743 APInt Constant = APInt::getNullValue(1);
2744 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2745 Constant = C->getAPIntValue();
2746 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2747 APInt SplatValue, SplatUndef;
2748 unsigned SplatBitSize;
2750 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2751 SplatBitSize, HasAnyUndefs);
2753 // Undef bits can contribute to a possible optimisation if set, so
2755 SplatValue |= SplatUndef;
2757 // The splat value may be something like "0x00FFFFFF", which means 0 for
2758 // the first vector value and FF for the rest, repeating. We need a mask
2759 // that will apply equally to all members of the vector, so AND all the
2760 // lanes of the constant together.
2761 EVT VT = Vector->getValueType(0);
2762 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2764 // If the splat value has been compressed to a bitlength lower
2765 // than the size of the vector lane, we need to re-expand it to
2767 if (BitWidth > SplatBitSize)
2768 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
2769 SplatBitSize < BitWidth;
2770 SplatBitSize = SplatBitSize * 2)
2771 SplatValue |= SplatValue.shl(SplatBitSize);
2773 Constant = APInt::getAllOnesValue(BitWidth);
2774 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
2775 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2779 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2780 // actually legal and isn't going to get expanded, else this is a false
2782 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2783 Load->getMemoryVT());
2785 // Resize the constant to the same size as the original memory access before
2786 // extension. If it is still the AllOnesValue then this AND is completely
2789 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2792 switch (Load->getExtensionType()) {
2793 default: B = false; break;
2794 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2796 case ISD::NON_EXTLOAD: B = true; break;
2799 if (B && Constant.isAllOnesValue()) {
2800 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2801 // preserve semantics once we get rid of the AND.
2802 SDValue NewLoad(Load, 0);
2803 if (Load->getExtensionType() == ISD::EXTLOAD) {
2804 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2805 Load->getValueType(0), SDLoc(Load),
2806 Load->getChain(), Load->getBasePtr(),
2807 Load->getOffset(), Load->getMemoryVT(),
2808 Load->getMemOperand());
2809 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2810 if (Load->getNumValues() == 3) {
2811 // PRE/POST_INC loads have 3 values.
2812 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
2813 NewLoad.getValue(2) };
2814 CombineTo(Load, To, 3, true);
2816 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2820 // Fold the AND away, taking care not to fold to the old load node if we
2822 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2824 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2827 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2828 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2829 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2830 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2832 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2833 LL.getValueType().isInteger()) {
2834 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2835 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2836 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2837 LR.getValueType(), LL, RL);
2838 AddToWorklist(ORNode.getNode());
2839 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2841 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2842 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2843 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2844 LR.getValueType(), LL, RL);
2845 AddToWorklist(ANDNode.getNode());
2846 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
2848 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2849 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2850 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2851 LR.getValueType(), LL, RL);
2852 AddToWorklist(ORNode.getNode());
2853 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
2856 // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
2857 if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
2858 Op0 == Op1 && LL.getValueType().isInteger() &&
2859 Op0 == ISD::SETNE && ((cast<ConstantSDNode>(LR)->isNullValue() &&
2860 cast<ConstantSDNode>(RR)->isAllOnesValue()) ||
2861 (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2862 cast<ConstantSDNode>(RR)->isNullValue()))) {
2863 SDValue ADDNode = DAG.getNode(ISD::ADD, SDLoc(N0), LL.getValueType(),
2864 LL, DAG.getConstant(1, LL.getValueType()));
2865 AddToWorklist(ADDNode.getNode());
2866 return DAG.getSetCC(SDLoc(N), VT, ADDNode,
2867 DAG.getConstant(2, LL.getValueType()), ISD::SETUGE);
2869 // canonicalize equivalent to ll == rl
2870 if (LL == RR && LR == RL) {
2871 Op1 = ISD::getSetCCSwappedOperands(Op1);
2874 if (LL == RL && LR == RR) {
2875 bool isInteger = LL.getValueType().isInteger();
2876 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2877 if (Result != ISD::SETCC_INVALID &&
2878 (!LegalOperations ||
2879 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
2880 TLI.isOperationLegal(ISD::SETCC,
2881 getSetCCResultType(N0.getSimpleValueType())))))
2882 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
2887 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2888 if (N0.getOpcode() == N1.getOpcode()) {
2889 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2890 if (Tmp.getNode()) return Tmp;
2893 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2894 // fold (and (sra)) -> (and (srl)) when possible.
2895 if (!VT.isVector() &&
2896 SimplifyDemandedBits(SDValue(N, 0)))
2897 return SDValue(N, 0);
2899 // fold (zext_inreg (extload x)) -> (zextload x)
2900 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2901 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2902 EVT MemVT = LN0->getMemoryVT();
2903 // If we zero all the possible extended bits, then we can turn this into
2904 // a zextload if we are running before legalize or the operation is legal.
2905 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2906 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2907 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2908 ((!LegalOperations && !LN0->isVolatile()) ||
2909 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2910 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2911 LN0->getChain(), LN0->getBasePtr(),
2912 MemVT, LN0->getMemOperand());
2914 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2915 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2918 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2919 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2921 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2922 EVT MemVT = LN0->getMemoryVT();
2923 // If we zero all the possible extended bits, then we can turn this into
2924 // a zextload if we are running before legalize or the operation is legal.
2925 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2926 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2927 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2928 ((!LegalOperations && !LN0->isVolatile()) ||
2929 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2930 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
2931 LN0->getChain(), LN0->getBasePtr(),
2932 MemVT, LN0->getMemOperand());
2934 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2935 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2939 // fold (and (load x), 255) -> (zextload x, i8)
2940 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2941 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2942 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2943 (N0.getOpcode() == ISD::ANY_EXTEND &&
2944 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2945 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2946 LoadSDNode *LN0 = HasAnyExt
2947 ? cast<LoadSDNode>(N0.getOperand(0))
2948 : cast<LoadSDNode>(N0);
2949 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2950 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) {
2951 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2952 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2953 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2954 EVT LoadedVT = LN0->getMemoryVT();
2956 if (ExtVT == LoadedVT &&
2957 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2958 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2961 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2962 LN0->getChain(), LN0->getBasePtr(), ExtVT,
2963 LN0->getMemOperand());
2965 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2966 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2969 // Do not change the width of a volatile load.
2970 // Do not generate loads of non-round integer types since these can
2971 // be expensive (and would be wrong if the type is not byte sized).
2972 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2973 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2974 EVT PtrType = LN0->getOperand(1).getValueType();
2976 unsigned Alignment = LN0->getAlignment();
2977 SDValue NewPtr = LN0->getBasePtr();
2979 // For big endian targets, we need to add an offset to the pointer
2980 // to load the correct bytes. For little endian systems, we merely
2981 // need to read fewer bytes from the same pointer.
2982 if (TLI.isBigEndian()) {
2983 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2984 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2985 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2986 NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0), PtrType,
2987 NewPtr, DAG.getConstant(PtrOff, PtrType));
2988 Alignment = MinAlign(Alignment, PtrOff);
2991 AddToWorklist(NewPtr.getNode());
2993 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2995 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
2996 LN0->getChain(), NewPtr,
2997 LN0->getPointerInfo(),
2998 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2999 LN0->isInvariant(), Alignment, LN0->getAAInfo());
3001 CombineTo(LN0, Load, Load.getValue(1));
3002 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3008 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
3009 VT.getSizeInBits() <= 64) {
3010 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3011 APInt ADDC = ADDI->getAPIntValue();
3012 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
3013 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
3014 // immediate for an add, but it is legal if its top c2 bits are set,
3015 // transform the ADD so the immediate doesn't need to be materialized
3017 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
3018 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3019 SRLI->getZExtValue());
3020 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
3022 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
3024 DAG.getNode(ISD::ADD, SDLoc(N0), VT,
3025 N0.getOperand(0), DAG.getConstant(ADDC, VT));
3026 CombineTo(N0.getNode(), NewAdd);
3027 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3035 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
3036 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
3037 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
3038 N0.getOperand(1), false);
3039 if (BSwap.getNode())
3046 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
3048 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
3049 bool DemandHighBits) {
3050 if (!LegalOperations)
3053 EVT VT = N->getValueType(0);
3054 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
3056 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3059 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
3060 bool LookPassAnd0 = false;
3061 bool LookPassAnd1 = false;
3062 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
3064 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
3066 if (N0.getOpcode() == ISD::AND) {
3067 if (!N0.getNode()->hasOneUse())
3069 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3070 if (!N01C || N01C->getZExtValue() != 0xFF00)
3072 N0 = N0.getOperand(0);
3073 LookPassAnd0 = true;
3076 if (N1.getOpcode() == ISD::AND) {
3077 if (!N1.getNode()->hasOneUse())
3079 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3080 if (!N11C || N11C->getZExtValue() != 0xFF)
3082 N1 = N1.getOperand(0);
3083 LookPassAnd1 = true;
3086 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
3088 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
3090 if (!N0.getNode()->hasOneUse() ||
3091 !N1.getNode()->hasOneUse())
3094 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3095 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3098 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
3101 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
3102 SDValue N00 = N0->getOperand(0);
3103 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
3104 if (!N00.getNode()->hasOneUse())
3106 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
3107 if (!N001C || N001C->getZExtValue() != 0xFF)
3109 N00 = N00.getOperand(0);
3110 LookPassAnd0 = true;
3113 SDValue N10 = N1->getOperand(0);
3114 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
3115 if (!N10.getNode()->hasOneUse())
3117 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
3118 if (!N101C || N101C->getZExtValue() != 0xFF00)
3120 N10 = N10.getOperand(0);
3121 LookPassAnd1 = true;
3127 // Make sure everything beyond the low halfword gets set to zero since the SRL
3128 // 16 will clear the top bits.
3129 unsigned OpSizeInBits = VT.getSizeInBits();
3130 if (DemandHighBits && OpSizeInBits > 16) {
3131 // If the left-shift isn't masked out then the only way this is a bswap is
3132 // if all bits beyond the low 8 are 0. In that case the entire pattern
3133 // reduces to a left shift anyway: leave it for other parts of the combiner.
3137 // However, if the right shift isn't masked out then it might be because
3138 // it's not needed. See if we can spot that too.
3139 if (!LookPassAnd1 &&
3140 !DAG.MaskedValueIsZero(
3141 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
3145 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
3146 if (OpSizeInBits > 16)
3147 Res = DAG.getNode(ISD::SRL, SDLoc(N), VT, Res,
3148 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
3152 /// isBSwapHWordElement - Return true if the specified node is an element
3153 /// that makes up a 32-bit packed halfword byteswap. i.e.
3154 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
3155 static bool isBSwapHWordElement(SDValue N, SmallVectorImpl<SDNode *> &Parts) {
3156 if (!N.getNode()->hasOneUse())
3159 unsigned Opc = N.getOpcode();
3160 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
3163 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3168 switch (N1C->getZExtValue()) {
3171 case 0xFF: Num = 0; break;
3172 case 0xFF00: Num = 1; break;
3173 case 0xFF0000: Num = 2; break;
3174 case 0xFF000000: Num = 3; break;
3177 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
3178 SDValue N0 = N.getOperand(0);
3179 if (Opc == ISD::AND) {
3180 if (Num == 0 || Num == 2) {
3182 // (x >> 8) & 0xff0000
3183 if (N0.getOpcode() != ISD::SRL)
3185 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3186 if (!C || C->getZExtValue() != 8)
3189 // (x << 8) & 0xff00
3190 // (x << 8) & 0xff000000
3191 if (N0.getOpcode() != ISD::SHL)
3193 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3194 if (!C || C->getZExtValue() != 8)
3197 } else if (Opc == ISD::SHL) {
3199 // (x & 0xff0000) << 8
3200 if (Num != 0 && Num != 2)
3202 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3203 if (!C || C->getZExtValue() != 8)
3205 } else { // Opc == ISD::SRL
3206 // (x & 0xff00) >> 8
3207 // (x & 0xff000000) >> 8
3208 if (Num != 1 && Num != 3)
3210 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3211 if (!C || C->getZExtValue() != 8)
3218 Parts[Num] = N0.getOperand(0).getNode();
3222 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
3223 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
3224 /// => (rotl (bswap x), 16)
3225 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
3226 if (!LegalOperations)
3229 EVT VT = N->getValueType(0);
3232 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3235 SmallVector<SDNode*,4> Parts(4, (SDNode*)nullptr);
3237 // (or (or (and), (and)), (or (and), (and)))
3238 // (or (or (or (and), (and)), (and)), (and))
3239 if (N0.getOpcode() != ISD::OR)
3241 SDValue N00 = N0.getOperand(0);
3242 SDValue N01 = N0.getOperand(1);
3244 if (N1.getOpcode() == ISD::OR &&
3245 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
3246 // (or (or (and), (and)), (or (and), (and)))
3247 SDValue N000 = N00.getOperand(0);
3248 if (!isBSwapHWordElement(N000, Parts))
3251 SDValue N001 = N00.getOperand(1);
3252 if (!isBSwapHWordElement(N001, Parts))
3254 SDValue N010 = N01.getOperand(0);
3255 if (!isBSwapHWordElement(N010, Parts))
3257 SDValue N011 = N01.getOperand(1);
3258 if (!isBSwapHWordElement(N011, Parts))
3261 // (or (or (or (and), (and)), (and)), (and))
3262 if (!isBSwapHWordElement(N1, Parts))
3264 if (!isBSwapHWordElement(N01, Parts))
3266 if (N00.getOpcode() != ISD::OR)
3268 SDValue N000 = N00.getOperand(0);
3269 if (!isBSwapHWordElement(N000, Parts))
3271 SDValue N001 = N00.getOperand(1);
3272 if (!isBSwapHWordElement(N001, Parts))
3276 // Make sure the parts are all coming from the same node.
3277 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3280 SDValue BSwap = DAG.getNode(ISD::BSWAP, SDLoc(N), VT,
3281 SDValue(Parts[0],0));
3283 // Result of the bswap should be rotated by 16. If it's not legal, then
3284 // do (x << 16) | (x >> 16).
3285 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
3286 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3287 return DAG.getNode(ISD::ROTL, SDLoc(N), VT, BSwap, ShAmt);
3288 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3289 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, BSwap, ShAmt);
3290 return DAG.getNode(ISD::OR, SDLoc(N), VT,
3291 DAG.getNode(ISD::SHL, SDLoc(N), VT, BSwap, ShAmt),
3292 DAG.getNode(ISD::SRL, SDLoc(N), VT, BSwap, ShAmt));
3295 SDValue DAGCombiner::visitOR(SDNode *N) {
3296 SDValue N0 = N->getOperand(0);
3297 SDValue N1 = N->getOperand(1);
3298 SDValue LL, LR, RL, RR, CC0, CC1;
3299 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3300 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3301 EVT VT = N1.getValueType();
3304 if (VT.isVector()) {
3305 SDValue FoldedVOp = SimplifyVBinOp(N);
3306 if (FoldedVOp.getNode()) return FoldedVOp;
3308 // fold (or x, 0) -> x, vector edition
3309 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3311 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3314 // fold (or x, -1) -> -1, vector edition
3315 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3317 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3320 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
3321 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
3322 // Do this only if the resulting shuffle is legal.
3323 if (isa<ShuffleVectorSDNode>(N0) &&
3324 isa<ShuffleVectorSDNode>(N1) &&
3325 // Avoid folding a node with illegal type.
3326 TLI.isTypeLegal(VT) &&
3327 N0->getOperand(1) == N1->getOperand(1) &&
3328 ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode())) {
3329 bool CanFold = true;
3330 unsigned NumElts = VT.getVectorNumElements();
3331 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
3332 const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
3333 // We construct two shuffle masks:
3334 // - Mask1 is a shuffle mask for a shuffle with N0 as the first operand
3335 // and N1 as the second operand.
3336 // - Mask2 is a shuffle mask for a shuffle with N1 as the first operand
3337 // and N0 as the second operand.
3338 // We do this because OR is commutable and therefore there might be
3339 // two ways to fold this node into a shuffle.
3340 SmallVector<int,4> Mask1;
3341 SmallVector<int,4> Mask2;
3343 for (unsigned i = 0; i != NumElts && CanFold; ++i) {
3344 int M0 = SV0->getMaskElt(i);
3345 int M1 = SV1->getMaskElt(i);
3347 // Both shuffle indexes are undef. Propagate Undef.
3348 if (M0 < 0 && M1 < 0) {
3349 Mask1.push_back(M0);
3350 Mask2.push_back(M0);
3354 if (M0 < 0 || M1 < 0 ||
3355 (M0 < (int)NumElts && M1 < (int)NumElts) ||
3356 (M0 >= (int)NumElts && M1 >= (int)NumElts)) {
3361 Mask1.push_back(M0 < (int)NumElts ? M0 : M1 + NumElts);
3362 Mask2.push_back(M1 < (int)NumElts ? M1 : M0 + NumElts);
3366 // Fold this sequence only if the resulting shuffle is 'legal'.
3367 if (TLI.isShuffleMaskLegal(Mask1, VT))
3368 return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0),
3369 N1->getOperand(0), &Mask1[0]);
3370 if (TLI.isShuffleMaskLegal(Mask2, VT))
3371 return DAG.getVectorShuffle(VT, SDLoc(N), N1->getOperand(0),
3372 N0->getOperand(0), &Mask2[0]);
3377 // fold (or x, undef) -> -1
3378 if (!LegalOperations &&
3379 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3380 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3381 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
3383 // fold (or c1, c2) -> c1|c2
3385 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
3386 // canonicalize constant to RHS
3388 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3389 // fold (or x, 0) -> x
3390 if (N1C && N1C->isNullValue())
3392 // fold (or x, -1) -> -1
3393 if (N1C && N1C->isAllOnesValue())
3395 // fold (or x, c) -> c iff (x & ~c) == 0
3396 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3399 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3400 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
3401 if (BSwap.getNode())
3403 BSwap = MatchBSwapHWordLow(N, N0, N1);
3404 if (BSwap.getNode())
3408 SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1);
3411 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3412 // iff (c1 & c2) == 0.
3413 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3414 isa<ConstantSDNode>(N0.getOperand(1))) {
3415 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3416 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) {
3417 SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1);
3420 return DAG.getNode(ISD::AND, SDLoc(N), VT,
3421 DAG.getNode(ISD::OR, SDLoc(N0), VT,
3422 N0.getOperand(0), N1), COR);
3425 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3426 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3427 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3428 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3430 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
3431 LL.getValueType().isInteger()) {
3432 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3433 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3434 if (cast<ConstantSDNode>(LR)->isNullValue() &&
3435 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3436 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR),
3437 LR.getValueType(), LL, RL);
3438 AddToWorklist(ORNode.getNode());
3439 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1);
3441 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3442 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3443 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
3444 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3445 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR),
3446 LR.getValueType(), LL, RL);
3447 AddToWorklist(ANDNode.getNode());
3448 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1);
3451 // canonicalize equivalent to ll == rl
3452 if (LL == RR && LR == RL) {
3453 Op1 = ISD::getSetCCSwappedOperands(Op1);
3456 if (LL == RL && LR == RR) {
3457 bool isInteger = LL.getValueType().isInteger();
3458 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3459 if (Result != ISD::SETCC_INVALID &&
3460 (!LegalOperations ||
3461 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
3462 TLI.isOperationLegal(ISD::SETCC,
3463 getSetCCResultType(N0.getValueType())))))
3464 return DAG.getSetCC(SDLoc(N), N0.getValueType(),
3469 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3470 if (N0.getOpcode() == N1.getOpcode()) {
3471 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3472 if (Tmp.getNode()) return Tmp;
3475 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3476 if (N0.getOpcode() == ISD::AND &&
3477 N1.getOpcode() == ISD::AND &&
3478 N0.getOperand(1).getOpcode() == ISD::Constant &&
3479 N1.getOperand(1).getOpcode() == ISD::Constant &&
3480 // Don't increase # computations.
3481 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3482 // We can only do this xform if we know that bits from X that are set in C2
3483 // but not in C1 are already zero. Likewise for Y.
3484 const APInt &LHSMask =
3485 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3486 const APInt &RHSMask =
3487 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3489 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3490 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3491 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3492 N0.getOperand(0), N1.getOperand(0));
3493 return DAG.getNode(ISD::AND, SDLoc(N), VT, X,
3494 DAG.getConstant(LHSMask | RHSMask, VT));
3498 // See if this is some rotate idiom.
3499 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
3500 return SDValue(Rot, 0);
3502 // Simplify the operands using demanded-bits information.
3503 if (!VT.isVector() &&
3504 SimplifyDemandedBits(SDValue(N, 0)))
3505 return SDValue(N, 0);
3510 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3511 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3512 if (Op.getOpcode() == ISD::AND) {
3513 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3514 Mask = Op.getOperand(1);
3515 Op = Op.getOperand(0);
3521 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3529 // Return true if we can prove that, whenever Neg and Pos are both in the
3530 // range [0, OpSize), Neg == (Pos == 0 ? 0 : OpSize - Pos). This means that
3531 // for two opposing shifts shift1 and shift2 and a value X with OpBits bits:
3533 // (or (shift1 X, Neg), (shift2 X, Pos))
3535 // reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate
3536 // in direction shift1 by Neg. The range [0, OpSize) means that we only need
3537 // to consider shift amounts with defined behavior.
3538 static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
3539 // If OpSize is a power of 2 then:
3541 // (a) (Pos == 0 ? 0 : OpSize - Pos) == (OpSize - Pos) & (OpSize - 1)
3542 // (b) Neg == Neg & (OpSize - 1) whenever Neg is in [0, OpSize).
3544 // So if OpSize is a power of 2 and Neg is (and Neg', OpSize-1), we check
3545 // for the stronger condition:
3547 // Neg & (OpSize - 1) == (OpSize - Pos) & (OpSize - 1) [A]
3549 // for all Neg and Pos. Since Neg & (OpSize - 1) == Neg' & (OpSize - 1)
3550 // we can just replace Neg with Neg' for the rest of the function.
3552 // In other cases we check for the even stronger condition:
3554 // Neg == OpSize - Pos [B]
3556 // for all Neg and Pos. Note that the (or ...) then invokes undefined
3557 // behavior if Pos == 0 (and consequently Neg == OpSize).
3559 // We could actually use [A] whenever OpSize is a power of 2, but the
3560 // only extra cases that it would match are those uninteresting ones
3561 // where Neg and Pos are never in range at the same time. E.g. for
3562 // OpSize == 32, using [A] would allow a Neg of the form (sub 64, Pos)
3563 // as well as (sub 32, Pos), but:
3565 // (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos))
3567 // always invokes undefined behavior for 32-bit X.
3569 // Below, Mask == OpSize - 1 when using [A] and is all-ones otherwise.
3570 unsigned MaskLoBits = 0;
3571 if (Neg.getOpcode() == ISD::AND &&
3572 isPowerOf2_64(OpSize) &&
3573 Neg.getOperand(1).getOpcode() == ISD::Constant &&
3574 cast<ConstantSDNode>(Neg.getOperand(1))->getAPIntValue() == OpSize - 1) {
3575 Neg = Neg.getOperand(0);
3576 MaskLoBits = Log2_64(OpSize);
3579 // Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
3580 if (Neg.getOpcode() != ISD::SUB)
3582 ConstantSDNode *NegC = dyn_cast<ConstantSDNode>(Neg.getOperand(0));
3585 SDValue NegOp1 = Neg.getOperand(1);
3587 // On the RHS of [A], if Pos is Pos' & (OpSize - 1), just replace Pos with
3588 // Pos'. The truncation is redundant for the purpose of the equality.
3590 Pos.getOpcode() == ISD::AND &&
3591 Pos.getOperand(1).getOpcode() == ISD::Constant &&
3592 cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() == OpSize - 1)
3593 Pos = Pos.getOperand(0);
3595 // The condition we need is now:
3597 // (NegC - NegOp1) & Mask == (OpSize - Pos) & Mask
3599 // If NegOp1 == Pos then we need:
3601 // OpSize & Mask == NegC & Mask
3603 // (because "x & Mask" is a truncation and distributes through subtraction).
3606 Width = NegC->getAPIntValue();
3607 // Check for cases where Pos has the form (add NegOp1, PosC) for some PosC.
3608 // Then the condition we want to prove becomes:
3610 // (NegC - NegOp1) & Mask == (OpSize - (NegOp1 + PosC)) & Mask
3612 // which, again because "x & Mask" is a truncation, becomes:
3614 // NegC & Mask == (OpSize - PosC) & Mask
3615 // OpSize & Mask == (NegC + PosC) & Mask
3616 else if (Pos.getOpcode() == ISD::ADD &&
3617 Pos.getOperand(0) == NegOp1 &&
3618 Pos.getOperand(1).getOpcode() == ISD::Constant)
3619 Width = (cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() +
3620 NegC->getAPIntValue());
3624 // Now we just need to check that OpSize & Mask == Width & Mask.
3626 // Opsize & Mask is 0 since Mask is Opsize - 1.
3627 return Width.getLoBits(MaskLoBits) == 0;
3628 return Width == OpSize;
3631 // A subroutine of MatchRotate used once we have found an OR of two opposite
3632 // shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
3633 // to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
3634 // former being preferred if supported. InnerPos and InnerNeg are Pos and
3635 // Neg with outer conversions stripped away.
3636 SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
3637 SDValue Neg, SDValue InnerPos,
3638 SDValue InnerNeg, unsigned PosOpcode,
3639 unsigned NegOpcode, SDLoc DL) {
3640 // fold (or (shl x, (*ext y)),
3641 // (srl x, (*ext (sub 32, y)))) ->
3642 // (rotl x, y) or (rotr x, (sub 32, y))
3644 // fold (or (shl x, (*ext (sub 32, y))),
3645 // (srl x, (*ext y))) ->
3646 // (rotr x, y) or (rotl x, (sub 32, y))
3647 EVT VT = Shifted.getValueType();
3648 if (matchRotateSub(InnerPos, InnerNeg, VT.getSizeInBits())) {
3649 bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
3650 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
3651 HasPos ? Pos : Neg).getNode();
3657 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3658 // idioms for rotate, and if the target supports rotation instructions, generate
3660 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
3661 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3662 EVT VT = LHS.getValueType();
3663 if (!TLI.isTypeLegal(VT)) return nullptr;
3665 // The target must have at least one rotate flavor.
3666 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3667 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3668 if (!HasROTL && !HasROTR) return nullptr;
3670 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3671 SDValue LHSShift; // The shift.
3672 SDValue LHSMask; // AND value if any.
3673 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3674 return nullptr; // Not part of a rotate.
3676 SDValue RHSShift; // The shift.
3677 SDValue RHSMask; // AND value if any.
3678 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3679 return nullptr; // Not part of a rotate.
3681 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3682 return nullptr; // Not shifting the same value.
3684 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3685 return nullptr; // Shifts must disagree.
3687 // Canonicalize shl to left side in a shl/srl pair.
3688 if (RHSShift.getOpcode() == ISD::SHL) {
3689 std::swap(LHS, RHS);
3690 std::swap(LHSShift, RHSShift);
3691 std::swap(LHSMask , RHSMask );
3694 unsigned OpSizeInBits = VT.getSizeInBits();
3695 SDValue LHSShiftArg = LHSShift.getOperand(0);
3696 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3697 SDValue RHSShiftArg = RHSShift.getOperand(0);
3698 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3700 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3701 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3702 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3703 RHSShiftAmt.getOpcode() == ISD::Constant) {
3704 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3705 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3706 if ((LShVal + RShVal) != OpSizeInBits)
3709 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3710 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3712 // If there is an AND of either shifted operand, apply it to the result.
3713 if (LHSMask.getNode() || RHSMask.getNode()) {
3714 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3716 if (LHSMask.getNode()) {
3717 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3718 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3720 if (RHSMask.getNode()) {
3721 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3722 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3725 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3728 return Rot.getNode();
3731 // If there is a mask here, and we have a variable shift, we can't be sure
3732 // that we're masking out the right stuff.
3733 if (LHSMask.getNode() || RHSMask.getNode())
3736 // If the shift amount is sign/zext/any-extended just peel it off.
3737 SDValue LExtOp0 = LHSShiftAmt;
3738 SDValue RExtOp0 = RHSShiftAmt;
3739 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3740 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3741 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3742 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3743 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3744 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3745 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3746 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3747 LExtOp0 = LHSShiftAmt.getOperand(0);
3748 RExtOp0 = RHSShiftAmt.getOperand(0);
3751 SDNode *TryL = MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt,
3752 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
3756 SDNode *TryR = MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
3757 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
3764 SDValue DAGCombiner::visitXOR(SDNode *N) {
3765 SDValue N0 = N->getOperand(0);
3766 SDValue N1 = N->getOperand(1);
3767 SDValue LHS, RHS, CC;
3768 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3769 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3770 EVT VT = N0.getValueType();
3773 if (VT.isVector()) {
3774 SDValue FoldedVOp = SimplifyVBinOp(N);
3775 if (FoldedVOp.getNode()) return FoldedVOp;
3777 // fold (xor x, 0) -> x, vector edition
3778 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3780 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3784 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3785 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3786 return DAG.getConstant(0, VT);
3787 // fold (xor x, undef) -> undef
3788 if (N0.getOpcode() == ISD::UNDEF)
3790 if (N1.getOpcode() == ISD::UNDEF)
3792 // fold (xor c1, c2) -> c1^c2
3794 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3795 // canonicalize constant to RHS
3797 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3798 // fold (xor x, 0) -> x
3799 if (N1C && N1C->isNullValue())
3802 SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1);
3806 // fold !(x cc y) -> (x !cc y)
3807 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3808 bool isInt = LHS.getValueType().isInteger();
3809 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3812 if (!LegalOperations ||
3813 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
3814 switch (N0.getOpcode()) {
3816 llvm_unreachable("Unhandled SetCC Equivalent!");
3818 return DAG.getSetCC(SDLoc(N), VT, LHS, RHS, NotCC);
3819 case ISD::SELECT_CC:
3820 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2),
3821 N0.getOperand(3), NotCC);
3826 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3827 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3828 N0.getNode()->hasOneUse() &&
3829 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3830 SDValue V = N0.getOperand(0);
3831 V = DAG.getNode(ISD::XOR, SDLoc(N0), V.getValueType(), V,
3832 DAG.getConstant(1, V.getValueType()));
3833 AddToWorklist(V.getNode());
3834 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V);
3837 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3838 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3839 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3840 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3841 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3842 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3843 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3844 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3845 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
3846 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3849 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3850 if (N1C && N1C->isAllOnesValue() &&
3851 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3852 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3853 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3854 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3855 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
3856 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
3857 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
3858 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
3861 // fold (xor (and x, y), y) -> (and (not x), y)
3862 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3863 N0->getOperand(1) == N1) {
3864 SDValue X = N0->getOperand(0);
3865 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT);
3866 AddToWorklist(NotX.getNode());
3867 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1);
3869 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3870 if (N1C && N0.getOpcode() == ISD::XOR) {
3871 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3872 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3874 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(1),
3875 DAG.getConstant(N1C->getAPIntValue() ^
3876 N00C->getAPIntValue(), VT));
3878 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(0),
3879 DAG.getConstant(N1C->getAPIntValue() ^
3880 N01C->getAPIntValue(), VT));
3882 // fold (xor x, x) -> 0
3884 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
3886 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3887 if (N0.getOpcode() == N1.getOpcode()) {
3888 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3889 if (Tmp.getNode()) return Tmp;
3892 // Simplify the expression using non-local knowledge.
3893 if (!VT.isVector() &&
3894 SimplifyDemandedBits(SDValue(N, 0)))
3895 return SDValue(N, 0);
3900 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3901 /// the shift amount is a constant.
3902 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, ConstantSDNode *Amt) {
3903 // We can't and shouldn't fold opaque constants.
3904 if (Amt->isOpaque())
3907 SDNode *LHS = N->getOperand(0).getNode();
3908 if (!LHS->hasOneUse()) return SDValue();
3910 // We want to pull some binops through shifts, so that we have (and (shift))
3911 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3912 // thing happens with address calculations, so it's important to canonicalize
3914 bool HighBitSet = false; // Can we transform this if the high bit is set?
3916 switch (LHS->getOpcode()) {
3917 default: return SDValue();
3920 HighBitSet = false; // We can only transform sra if the high bit is clear.
3923 HighBitSet = true; // We can only transform sra if the high bit is set.
3926 if (N->getOpcode() != ISD::SHL)
3927 return SDValue(); // only shl(add) not sr[al](add).
3928 HighBitSet = false; // We can only transform sra if the high bit is clear.
3932 // We require the RHS of the binop to be a constant and not opaque as well.
3933 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3934 if (!BinOpCst || BinOpCst->isOpaque()) return SDValue();
3936 // FIXME: disable this unless the input to the binop is a shift by a constant.
3937 // If it is not a shift, it pessimizes some common cases like:
3939 // void foo(int *X, int i) { X[i & 1235] = 1; }
3940 // int bar(int *X, int i) { return X[i & 255]; }
3941 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3942 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3943 BinOpLHSVal->getOpcode() != ISD::SRA &&
3944 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3945 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3948 EVT VT = N->getValueType(0);
3950 // If this is a signed shift right, and the high bit is modified by the
3951 // logical operation, do not perform the transformation. The highBitSet
3952 // boolean indicates the value of the high bit of the constant which would
3953 // cause it to be modified for this operation.
3954 if (N->getOpcode() == ISD::SRA) {
3955 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3956 if (BinOpRHSSignSet != HighBitSet)
3960 if (!TLI.isDesirableToCommuteWithShift(LHS))
3963 // Fold the constants, shifting the binop RHS by the shift amount.
3964 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)),
3966 LHS->getOperand(1), N->getOperand(1));
3967 assert(isa<ConstantSDNode>(NewRHS) && "Folding was not successful!");
3969 // Create the new shift.
3970 SDValue NewShift = DAG.getNode(N->getOpcode(),
3971 SDLoc(LHS->getOperand(0)),
3972 VT, LHS->getOperand(0), N->getOperand(1));
3974 // Create the new binop.
3975 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS);
3978 SDValue DAGCombiner::distributeTruncateThroughAnd(SDNode *N) {
3979 assert(N->getOpcode() == ISD::TRUNCATE);
3980 assert(N->getOperand(0).getOpcode() == ISD::AND);
3982 // (truncate:TruncVT (and N00, N01C)) -> (and (truncate:TruncVT N00), TruncC)
3983 if (N->hasOneUse() && N->getOperand(0).hasOneUse()) {
3984 SDValue N01 = N->getOperand(0).getOperand(1);
3986 if (ConstantSDNode *N01C = isConstOrConstSplat(N01)) {
3987 EVT TruncVT = N->getValueType(0);
3988 SDValue N00 = N->getOperand(0).getOperand(0);
3989 APInt TruncC = N01C->getAPIntValue();
3990 TruncC = TruncC.trunc(TruncVT.getScalarSizeInBits());
3992 return DAG.getNode(ISD::AND, SDLoc(N), TruncVT,
3993 DAG.getNode(ISD::TRUNCATE, SDLoc(N), TruncVT, N00),
3994 DAG.getConstant(TruncC, TruncVT));
4001 SDValue DAGCombiner::visitRotate(SDNode *N) {
4002 // fold (rot* x, (trunc (and y, c))) -> (rot* x, (and (trunc y), (trunc c))).
4003 if (N->getOperand(1).getOpcode() == ISD::TRUNCATE &&
4004 N->getOperand(1).getOperand(0).getOpcode() == ISD::AND) {
4005 SDValue NewOp1 = distributeTruncateThroughAnd(N->getOperand(1).getNode());
4006 if (NewOp1.getNode())
4007 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
4008 N->getOperand(0), NewOp1);
4013 SDValue DAGCombiner::visitSHL(SDNode *N) {
4014 SDValue N0 = N->getOperand(0);
4015 SDValue N1 = N->getOperand(1);
4016 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4017 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4018 EVT VT = N0.getValueType();
4019 unsigned OpSizeInBits = VT.getScalarSizeInBits();
4022 if (VT.isVector()) {
4023 SDValue FoldedVOp = SimplifyVBinOp(N);
4024 if (FoldedVOp.getNode()) return FoldedVOp;
4026 BuildVectorSDNode *N1CV = dyn_cast<BuildVectorSDNode>(N1);
4027 // If setcc produces all-one true value then:
4028 // (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV)
4029 if (N1CV && N1CV->isConstant()) {
4030 if (N0.getOpcode() == ISD::AND) {
4031 SDValue N00 = N0->getOperand(0);
4032 SDValue N01 = N0->getOperand(1);
4033 BuildVectorSDNode *N01CV = dyn_cast<BuildVectorSDNode>(N01);
4035 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
4036 TLI.getBooleanContents(N00.getOperand(0).getValueType()) ==
4037 TargetLowering::ZeroOrNegativeOneBooleanContent) {
4038 SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, VT, N01CV, N1CV);
4040 return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C);
4043 N1C = isConstOrConstSplat(N1);
4048 // fold (shl c1, c2) -> c1<<c2
4050 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
4051 // fold (shl 0, x) -> 0
4052 if (N0C && N0C->isNullValue())
4054 // fold (shl x, c >= size(x)) -> undef
4055 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4056 return DAG.getUNDEF(VT);
4057 // fold (shl x, 0) -> x
4058 if (N1C && N1C->isNullValue())
4060 // fold (shl undef, x) -> 0
4061 if (N0.getOpcode() == ISD::UNDEF)
4062 return DAG.getConstant(0, VT);
4063 // if (shl x, c) is known to be zero, return 0
4064 if (DAG.MaskedValueIsZero(SDValue(N, 0),
4065 APInt::getAllOnesValue(OpSizeInBits)))
4066 return DAG.getConstant(0, VT);
4067 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
4068 if (N1.getOpcode() == ISD::TRUNCATE &&
4069 N1.getOperand(0).getOpcode() == ISD::AND) {
4070 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4071 if (NewOp1.getNode())
4072 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1);
4075 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4076 return SDValue(N, 0);
4078 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
4079 if (N1C && N0.getOpcode() == ISD::SHL) {
4080 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4081 uint64_t c1 = N0C1->getZExtValue();
4082 uint64_t c2 = N1C->getZExtValue();
4083 if (c1 + c2 >= OpSizeInBits)
4084 return DAG.getConstant(0, VT);
4085 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4086 DAG.getConstant(c1 + c2, N1.getValueType()));
4090 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
4091 // For this to be valid, the second form must not preserve any of the bits
4092 // that are shifted out by the inner shift in the first form. This means
4093 // the outer shift size must be >= the number of bits added by the ext.
4094 // As a corollary, we don't care what kind of ext it is.
4095 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
4096 N0.getOpcode() == ISD::ANY_EXTEND ||
4097 N0.getOpcode() == ISD::SIGN_EXTEND) &&
4098 N0.getOperand(0).getOpcode() == ISD::SHL) {
4099 SDValue N0Op0 = N0.getOperand(0);
4100 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4101 uint64_t c1 = N0Op0C1->getZExtValue();
4102 uint64_t c2 = N1C->getZExtValue();
4103 EVT InnerShiftVT = N0Op0.getValueType();
4104 uint64_t InnerShiftSize = InnerShiftVT.getScalarSizeInBits();
4105 if (c2 >= OpSizeInBits - InnerShiftSize) {
4106 if (c1 + c2 >= OpSizeInBits)
4107 return DAG.getConstant(0, VT);
4108 return DAG.getNode(ISD::SHL, SDLoc(N0), VT,
4109 DAG.getNode(N0.getOpcode(), SDLoc(N0), VT,
4110 N0Op0->getOperand(0)),
4111 DAG.getConstant(c1 + c2, N1.getValueType()));
4116 // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
4117 // Only fold this if the inner zext has no other uses to avoid increasing
4118 // the total number of instructions.
4119 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
4120 N0.getOperand(0).getOpcode() == ISD::SRL) {
4121 SDValue N0Op0 = N0.getOperand(0);
4122 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4123 uint64_t c1 = N0Op0C1->getZExtValue();
4124 if (c1 < VT.getScalarSizeInBits()) {
4125 uint64_t c2 = N1C->getZExtValue();
4127 SDValue NewOp0 = N0.getOperand(0);
4128 EVT CountVT = NewOp0.getOperand(1).getValueType();
4129 SDValue NewSHL = DAG.getNode(ISD::SHL, SDLoc(N), NewOp0.getValueType(),
4130 NewOp0, DAG.getConstant(c2, CountVT));
4131 AddToWorklist(NewSHL.getNode());
4132 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
4138 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
4139 // (and (srl x, (sub c1, c2), MASK)
4140 // Only fold this if the inner shift has no other uses -- if it does, folding
4141 // this will increase the total number of instructions.
4142 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4143 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4144 uint64_t c1 = N0C1->getZExtValue();
4145 if (c1 < OpSizeInBits) {
4146 uint64_t c2 = N1C->getZExtValue();
4147 APInt Mask = APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - c1);
4150 Mask = Mask.shl(c2 - c1);
4151 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0),
4152 DAG.getConstant(c2 - c1, N1.getValueType()));
4154 Mask = Mask.lshr(c1 - c2);
4155 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4156 DAG.getConstant(c1 - c2, N1.getValueType()));
4158 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift,
4159 DAG.getConstant(Mask, VT));
4163 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
4164 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
4165 unsigned BitSize = VT.getScalarSizeInBits();
4166 SDValue HiBitsMask =
4167 DAG.getConstant(APInt::getHighBitsSet(BitSize,
4168 BitSize - N1C->getZExtValue()), VT);
4169 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4174 SDValue NewSHL = visitShiftByConstant(N, N1C);
4175 if (NewSHL.getNode())
4182 SDValue DAGCombiner::visitSRA(SDNode *N) {
4183 SDValue N0 = N->getOperand(0);
4184 SDValue N1 = N->getOperand(1);
4185 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4186 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4187 EVT VT = N0.getValueType();
4188 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4191 if (VT.isVector()) {
4192 SDValue FoldedVOp = SimplifyVBinOp(N);
4193 if (FoldedVOp.getNode()) return FoldedVOp;
4195 N1C = isConstOrConstSplat(N1);
4198 // fold (sra c1, c2) -> (sra c1, c2)
4200 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
4201 // fold (sra 0, x) -> 0
4202 if (N0C && N0C->isNullValue())
4204 // fold (sra -1, x) -> -1
4205 if (N0C && N0C->isAllOnesValue())
4207 // fold (sra x, (setge c, size(x))) -> undef
4208 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4209 return DAG.getUNDEF(VT);
4210 // fold (sra x, 0) -> x
4211 if (N1C && N1C->isNullValue())
4213 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
4215 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
4216 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
4217 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
4219 ExtVT = EVT::getVectorVT(*DAG.getContext(),
4220 ExtVT, VT.getVectorNumElements());
4221 if ((!LegalOperations ||
4222 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
4223 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
4224 N0.getOperand(0), DAG.getValueType(ExtVT));
4227 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
4228 if (N1C && N0.getOpcode() == ISD::SRA) {
4229 if (ConstantSDNode *C1 = isConstOrConstSplat(N0.getOperand(1))) {
4230 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
4231 if (Sum >= OpSizeInBits)
4232 Sum = OpSizeInBits - 1;
4233 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
4234 DAG.getConstant(Sum, N1.getValueType()));
4238 // fold (sra (shl X, m), (sub result_size, n))
4239 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
4240 // result_size - n != m.
4241 // If truncate is free for the target sext(shl) is likely to result in better
4243 if (N0.getOpcode() == ISD::SHL && N1C) {
4244 // Get the two constanst of the shifts, CN0 = m, CN = n.
4245 const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
4247 LLVMContext &Ctx = *DAG.getContext();
4248 // Determine what the truncate's result bitsize and type would be.
4249 EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - N1C->getZExtValue());
4252 TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorNumElements());
4254 // Determine the residual right-shift amount.
4255 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
4257 // If the shift is not a no-op (in which case this should be just a sign
4258 // extend already), the truncated to type is legal, sign_extend is legal
4259 // on that type, and the truncate to that type is both legal and free,
4260 // perform the transform.
4261 if ((ShiftAmt > 0) &&
4262 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
4263 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
4264 TLI.isTruncateFree(VT, TruncVT)) {
4266 SDValue Amt = DAG.getConstant(ShiftAmt,
4267 getShiftAmountTy(N0.getOperand(0).getValueType()));
4268 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT,
4269 N0.getOperand(0), Amt);
4270 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), TruncVT,
4272 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N),
4273 N->getValueType(0), Trunc);
4278 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
4279 if (N1.getOpcode() == ISD::TRUNCATE &&
4280 N1.getOperand(0).getOpcode() == ISD::AND) {
4281 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4282 if (NewOp1.getNode())
4283 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
4286 // fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
4287 // if c1 is equal to the number of bits the trunc removes
4288 if (N0.getOpcode() == ISD::TRUNCATE &&
4289 (N0.getOperand(0).getOpcode() == ISD::SRL ||
4290 N0.getOperand(0).getOpcode() == ISD::SRA) &&
4291 N0.getOperand(0).hasOneUse() &&
4292 N0.getOperand(0).getOperand(1).hasOneUse() &&
4294 SDValue N0Op0 = N0.getOperand(0);
4295 if (ConstantSDNode *LargeShift = isConstOrConstSplat(N0Op0.getOperand(1))) {
4296 unsigned LargeShiftVal = LargeShift->getZExtValue();
4297 EVT LargeVT = N0Op0.getValueType();
4299 if (LargeVT.getScalarSizeInBits() - OpSizeInBits == LargeShiftVal) {
4301 DAG.getConstant(LargeShiftVal + N1C->getZExtValue(),
4302 getShiftAmountTy(N0Op0.getOperand(0).getValueType()));
4303 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), LargeVT,
4304 N0Op0.getOperand(0), Amt);
4305 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, SRA);
4310 // Simplify, based on bits shifted out of the LHS.
4311 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4312 return SDValue(N, 0);
4315 // If the sign bit is known to be zero, switch this to a SRL.
4316 if (DAG.SignBitIsZero(N0))
4317 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
4320 SDValue NewSRA = visitShiftByConstant(N, N1C);
4321 if (NewSRA.getNode())
4328 SDValue DAGCombiner::visitSRL(SDNode *N) {
4329 SDValue N0 = N->getOperand(0);
4330 SDValue N1 = N->getOperand(1);
4331 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4332 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4333 EVT VT = N0.getValueType();
4334 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4337 if (VT.isVector()) {
4338 SDValue FoldedVOp = SimplifyVBinOp(N);
4339 if (FoldedVOp.getNode()) return FoldedVOp;
4341 N1C = isConstOrConstSplat(N1);
4344 // fold (srl c1, c2) -> c1 >>u c2
4346 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
4347 // fold (srl 0, x) -> 0
4348 if (N0C && N0C->isNullValue())
4350 // fold (srl x, c >= size(x)) -> undef
4351 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4352 return DAG.getUNDEF(VT);
4353 // fold (srl x, 0) -> x
4354 if (N1C && N1C->isNullValue())
4356 // if (srl x, c) is known to be zero, return 0
4357 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
4358 APInt::getAllOnesValue(OpSizeInBits)))
4359 return DAG.getConstant(0, VT);
4361 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
4362 if (N1C && N0.getOpcode() == ISD::SRL) {
4363 if (ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1))) {
4364 uint64_t c1 = N01C->getZExtValue();
4365 uint64_t c2 = N1C->getZExtValue();
4366 if (c1 + c2 >= OpSizeInBits)
4367 return DAG.getConstant(0, VT);
4368 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0),
4369 DAG.getConstant(c1 + c2, N1.getValueType()));
4373 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
4374 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
4375 N0.getOperand(0).getOpcode() == ISD::SRL &&
4376 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
4378 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
4379 uint64_t c2 = N1C->getZExtValue();
4380 EVT InnerShiftVT = N0.getOperand(0).getValueType();
4381 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
4382 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
4383 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
4384 if (c1 + OpSizeInBits == InnerShiftSize) {
4385 if (c1 + c2 >= InnerShiftSize)
4386 return DAG.getConstant(0, VT);
4387 return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT,
4388 DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT,
4389 N0.getOperand(0)->getOperand(0),
4390 DAG.getConstant(c1 + c2, ShiftCountVT)));
4394 // fold (srl (shl x, c), c) -> (and x, cst2)
4395 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
4396 unsigned BitSize = N0.getScalarValueSizeInBits();
4397 if (BitSize <= 64) {
4398 uint64_t ShAmt = N1C->getZExtValue() + 64 - BitSize;
4399 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0),
4400 DAG.getConstant(~0ULL >> ShAmt, VT));
4404 // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask)
4405 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4406 // Shifting in all undef bits?
4407 EVT SmallVT = N0.getOperand(0).getValueType();
4408 unsigned BitSize = SmallVT.getScalarSizeInBits();
4409 if (N1C->getZExtValue() >= BitSize)
4410 return DAG.getUNDEF(VT);
4412 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
4413 uint64_t ShiftAmt = N1C->getZExtValue();
4414 SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT,
4416 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
4417 AddToWorklist(SmallShift.getNode());
4418 APInt Mask = APInt::getAllOnesValue(OpSizeInBits).lshr(ShiftAmt);
4419 return DAG.getNode(ISD::AND, SDLoc(N), VT,
4420 DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift),
4421 DAG.getConstant(Mask, VT));
4425 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
4426 // bit, which is unmodified by sra.
4427 if (N1C && N1C->getZExtValue() + 1 == OpSizeInBits) {
4428 if (N0.getOpcode() == ISD::SRA)
4429 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
4432 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
4433 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4434 N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
4435 APInt KnownZero, KnownOne;
4436 DAG.computeKnownBits(N0.getOperand(0), KnownZero, KnownOne);
4438 // If any of the input bits are KnownOne, then the input couldn't be all
4439 // zeros, thus the result of the srl will always be zero.
4440 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
4442 // If all of the bits input the to ctlz node are known to be zero, then
4443 // the result of the ctlz is "32" and the result of the shift is one.
4444 APInt UnknownBits = ~KnownZero;
4445 if (UnknownBits == 0) return DAG.getConstant(1, VT);
4447 // Otherwise, check to see if there is exactly one bit input to the ctlz.
4448 if ((UnknownBits & (UnknownBits - 1)) == 0) {
4449 // Okay, we know that only that the single bit specified by UnknownBits
4450 // could be set on input to the CTLZ node. If this bit is set, the SRL
4451 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
4452 // to an SRL/XOR pair, which is likely to simplify more.
4453 unsigned ShAmt = UnknownBits.countTrailingZeros();
4454 SDValue Op = N0.getOperand(0);
4457 Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op,
4458 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
4459 AddToWorklist(Op.getNode());
4462 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
4463 Op, DAG.getConstant(1, VT));
4467 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
4468 if (N1.getOpcode() == ISD::TRUNCATE &&
4469 N1.getOperand(0).getOpcode() == ISD::AND) {
4470 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4471 if (NewOp1.getNode())
4472 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
4475 // fold operands of srl based on knowledge that the low bits are not
4477 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4478 return SDValue(N, 0);
4481 SDValue NewSRL = visitShiftByConstant(N, N1C);
4482 if (NewSRL.getNode())
4486 // Attempt to convert a srl of a load into a narrower zero-extending load.
4487 SDValue NarrowLoad = ReduceLoadWidth(N);
4488 if (NarrowLoad.getNode())
4491 // Here is a common situation. We want to optimize:
4494 // %b = and i32 %a, 2
4495 // %c = srl i32 %b, 1
4496 // brcond i32 %c ...
4502 // %c = setcc eq %b, 0
4505 // However when after the source operand of SRL is optimized into AND, the SRL
4506 // itself may not be optimized further. Look for it and add the BRCOND into
4508 if (N->hasOneUse()) {
4509 SDNode *Use = *N->use_begin();
4510 if (Use->getOpcode() == ISD::BRCOND)
4512 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4513 // Also look pass the truncate.
4514 Use = *Use->use_begin();
4515 if (Use->getOpcode() == ISD::BRCOND)
4523 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
4524 SDValue N0 = N->getOperand(0);
4525 EVT VT = N->getValueType(0);
4527 // fold (ctlz c1) -> c2
4528 if (isa<ConstantSDNode>(N0))
4529 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
4533 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
4534 SDValue N0 = N->getOperand(0);
4535 EVT VT = N->getValueType(0);
4537 // fold (ctlz_zero_undef c1) -> c2
4538 if (isa<ConstantSDNode>(N0))
4539 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4543 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4544 SDValue N0 = N->getOperand(0);
4545 EVT VT = N->getValueType(0);
4547 // fold (cttz c1) -> c2
4548 if (isa<ConstantSDNode>(N0))
4549 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
4553 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4554 SDValue N0 = N->getOperand(0);
4555 EVT VT = N->getValueType(0);
4557 // fold (cttz_zero_undef c1) -> c2
4558 if (isa<ConstantSDNode>(N0))
4559 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4563 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4564 SDValue N0 = N->getOperand(0);
4565 EVT VT = N->getValueType(0);
4567 // fold (ctpop c1) -> c2
4568 if (isa<ConstantSDNode>(N0))
4569 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
4573 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4574 SDValue N0 = N->getOperand(0);
4575 SDValue N1 = N->getOperand(1);
4576 SDValue N2 = N->getOperand(2);
4577 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4578 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4579 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
4580 EVT VT = N->getValueType(0);
4581 EVT VT0 = N0.getValueType();
4583 // fold (select C, X, X) -> X
4586 // fold (select true, X, Y) -> X
4587 if (N0C && !N0C->isNullValue())
4589 // fold (select false, X, Y) -> Y
4590 if (N0C && N0C->isNullValue())
4592 // fold (select C, 1, X) -> (or C, X)
4593 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4594 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4595 // fold (select C, 0, 1) -> (xor C, 1)
4596 // We can't do this reliably if integer based booleans have different contents
4597 // to floating point based booleans. This is because we can't tell whether we
4598 // have an integer-based boolean or a floating-point-based boolean unless we
4599 // can find the SETCC that produced it and inspect its operands. This is
4600 // fairly easy if C is the SETCC node, but it can potentially be
4601 // undiscoverable (or not reasonably discoverable). For example, it could be
4602 // in another basic block or it could require searching a complicated
4604 if (VT.isInteger() &&
4605 (VT0 == MVT::i1 || (VT0.isInteger() &&
4606 TLI.getBooleanContents(false, false) ==
4607 TLI.getBooleanContents(false, true) &&
4608 TLI.getBooleanContents(false, false) ==
4609 TargetLowering::ZeroOrOneBooleanContent)) &&
4610 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
4613 return DAG.getNode(ISD::XOR, SDLoc(N), VT0,
4614 N0, DAG.getConstant(1, VT0));
4615 XORNode = DAG.getNode(ISD::XOR, SDLoc(N0), VT0,
4616 N0, DAG.getConstant(1, VT0));
4617 AddToWorklist(XORNode.getNode());
4619 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, XORNode);
4620 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, XORNode);
4622 // fold (select C, 0, X) -> (and (not C), X)
4623 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4624 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4625 AddToWorklist(NOTNode.getNode());
4626 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2);
4628 // fold (select C, X, 1) -> (or (not C), X)
4629 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4630 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4631 AddToWorklist(NOTNode.getNode());
4632 return DAG.getNode(ISD::OR, SDLoc(N), VT, NOTNode, N1);
4634 // fold (select C, X, 0) -> (and C, X)
4635 if (VT == MVT::i1 && N2C && N2C->isNullValue())
4636 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4637 // fold (select X, X, Y) -> (or X, Y)
4638 // fold (select X, 1, Y) -> (or X, Y)
4639 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
4640 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4641 // fold (select X, Y, X) -> (and X, Y)
4642 // fold (select X, Y, 0) -> (and X, Y)
4643 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
4644 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4646 // If we can fold this based on the true/false value, do so.
4647 if (SimplifySelectOps(N, N1, N2))
4648 return SDValue(N, 0); // Don't revisit N.
4650 // fold selects based on a setcc into other things, such as min/max/abs
4651 if (N0.getOpcode() == ISD::SETCC) {
4652 if ((!LegalOperations &&
4653 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) ||
4654 TLI.isOperationLegal(ISD::SELECT_CC, VT))
4655 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT,
4656 N0.getOperand(0), N0.getOperand(1),
4657 N1, N2, N0.getOperand(2));
4658 return SimplifySelect(SDLoc(N), N0, N1, N2);
4665 std::pair<SDValue, SDValue> SplitVSETCC(const SDNode *N, SelectionDAG &DAG) {
4668 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
4670 // Split the inputs.
4671 SDValue Lo, Hi, LL, LH, RL, RH;
4672 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
4673 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
4675 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
4676 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
4678 return std::make_pair(Lo, Hi);
4681 // This function assumes all the vselect's arguments are CONCAT_VECTOR
4682 // nodes and that the condition is a BV of ConstantSDNodes (or undefs).
4683 static SDValue ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) {
4685 SDValue Cond = N->getOperand(0);
4686 SDValue LHS = N->getOperand(1);
4687 SDValue RHS = N->getOperand(2);
4688 EVT VT = N->getValueType(0);
4689 int NumElems = VT.getVectorNumElements();
4690 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
4691 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
4692 Cond.getOpcode() == ISD::BUILD_VECTOR);
4694 // CONCAT_VECTOR can take an arbitrary number of arguments. We only care about
4695 // binary ones here.
4696 if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2)
4699 // We're sure we have an even number of elements due to the
4700 // concat_vectors we have as arguments to vselect.
4701 // Skip BV elements until we find one that's not an UNDEF
4702 // After we find an UNDEF element, keep looping until we get to half the
4703 // length of the BV and see if all the non-undef nodes are the same.
4704 ConstantSDNode *BottomHalf = nullptr;
4705 for (int i = 0; i < NumElems / 2; ++i) {
4706 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
4709 if (BottomHalf == nullptr)
4710 BottomHalf = cast<ConstantSDNode>(Cond.getOperand(i));
4711 else if (Cond->getOperand(i).getNode() != BottomHalf)
4715 // Do the same for the second half of the BuildVector
4716 ConstantSDNode *TopHalf = nullptr;
4717 for (int i = NumElems / 2; i < NumElems; ++i) {
4718 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
4721 if (TopHalf == nullptr)
4722 TopHalf = cast<ConstantSDNode>(Cond.getOperand(i));
4723 else if (Cond->getOperand(i).getNode() != TopHalf)
4727 assert(TopHalf && BottomHalf &&
4728 "One half of the selector was all UNDEFs and the other was all the "
4729 "same value. This should have been addressed before this function.");
4731 ISD::CONCAT_VECTORS, dl, VT,
4732 BottomHalf->isNullValue() ? RHS->getOperand(0) : LHS->getOperand(0),
4733 TopHalf->isNullValue() ? RHS->getOperand(1) : LHS->getOperand(1));
4736 SDValue DAGCombiner::visitVSELECT(SDNode *N) {
4737 SDValue N0 = N->getOperand(0);
4738 SDValue N1 = N->getOperand(1);
4739 SDValue N2 = N->getOperand(2);
4742 // Canonicalize integer abs.
4743 // vselect (setg[te] X, 0), X, -X ->
4744 // vselect (setgt X, -1), X, -X ->
4745 // vselect (setl[te] X, 0), -X, X ->
4746 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4747 if (N0.getOpcode() == ISD::SETCC) {
4748 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
4749 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4751 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
4753 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
4754 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) &&
4755 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
4756 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode());
4757 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) &&
4758 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
4759 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
4762 EVT VT = LHS.getValueType();
4763 SDValue Shift = DAG.getNode(
4764 ISD::SRA, DL, VT, LHS,
4765 DAG.getConstant(VT.getScalarType().getSizeInBits() - 1, VT));
4766 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);
4767 AddToWorklist(Shift.getNode());
4768 AddToWorklist(Add.getNode());
4769 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift);
4773 // If the VSELECT result requires splitting and the mask is provided by a
4774 // SETCC, then split both nodes and its operands before legalization. This
4775 // prevents the type legalizer from unrolling SETCC into scalar comparisons
4776 // and enables future optimizations (e.g. min/max pattern matching on X86).
4777 if (N0.getOpcode() == ISD::SETCC) {
4778 EVT VT = N->getValueType(0);
4780 // Check if any splitting is required.
4781 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
4782 TargetLowering::TypeSplitVector)
4785 SDValue Lo, Hi, CCLo, CCHi, LL, LH, RL, RH;
4786 std::tie(CCLo, CCHi) = SplitVSETCC(N0.getNode(), DAG);
4787 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 1);
4788 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 2);
4790 Lo = DAG.getNode(N->getOpcode(), DL, LL.getValueType(), CCLo, LL, RL);
4791 Hi = DAG.getNode(N->getOpcode(), DL, LH.getValueType(), CCHi, LH, RH);
4793 // Add the new VSELECT nodes to the work list in case they need to be split
4795 AddToWorklist(Lo.getNode());
4796 AddToWorklist(Hi.getNode());
4798 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
4801 // Fold (vselect (build_vector all_ones), N1, N2) -> N1
4802 if (ISD::isBuildVectorAllOnes(N0.getNode()))
4804 // Fold (vselect (build_vector all_zeros), N1, N2) -> N2
4805 if (ISD::isBuildVectorAllZeros(N0.getNode()))
4808 // The ConvertSelectToConcatVector function is assuming both the above
4809 // checks for (vselect (build_vector all{ones,zeros) ...) have been made
4811 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
4812 N2.getOpcode() == ISD::CONCAT_VECTORS &&
4813 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
4814 SDValue CV = ConvertSelectToConcatVector(N, DAG);
4822 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4823 SDValue N0 = N->getOperand(0);
4824 SDValue N1 = N->getOperand(1);
4825 SDValue N2 = N->getOperand(2);
4826 SDValue N3 = N->getOperand(3);
4827 SDValue N4 = N->getOperand(4);
4828 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4830 // fold select_cc lhs, rhs, x, x, cc -> x
4834 // Determine if the condition we're dealing with is constant
4835 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
4836 N0, N1, CC, SDLoc(N), false);
4837 if (SCC.getNode()) {
4838 AddToWorklist(SCC.getNode());
4840 if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) {
4841 if (!SCCC->isNullValue())
4842 return N2; // cond always true -> true val
4844 return N3; // cond always false -> false val
4847 // Fold to a simpler select_cc
4848 if (SCC.getOpcode() == ISD::SETCC)
4849 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(),
4850 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4854 // If we can fold this based on the true/false value, do so.
4855 if (SimplifySelectOps(N, N2, N3))
4856 return SDValue(N, 0); // Don't revisit N.
4858 // fold select_cc into other things, such as min/max/abs
4859 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
4862 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4863 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4864 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4868 // tryToFoldExtendOfConstant - Try to fold a sext/zext/aext
4869 // dag node into a ConstantSDNode or a build_vector of constants.
4870 // This function is called by the DAGCombiner when visiting sext/zext/aext
4871 // dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
4872 // Vector extends are not folded if operations are legal; this is to
4873 // avoid introducing illegal build_vector dag nodes.
4874 static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
4875 SelectionDAG &DAG, bool LegalTypes,
4876 bool LegalOperations) {
4877 unsigned Opcode = N->getOpcode();
4878 SDValue N0 = N->getOperand(0);
4879 EVT VT = N->getValueType(0);
4881 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
4882 Opcode == ISD::ANY_EXTEND) && "Expected EXTEND dag node in input!");
4884 // fold (sext c1) -> c1
4885 // fold (zext c1) -> c1
4886 // fold (aext c1) -> c1
4887 if (isa<ConstantSDNode>(N0))
4888 return DAG.getNode(Opcode, SDLoc(N), VT, N0).getNode();
4890 // fold (sext (build_vector AllConstants) -> (build_vector AllConstants)
4891 // fold (zext (build_vector AllConstants) -> (build_vector AllConstants)
4892 // fold (aext (build_vector AllConstants) -> (build_vector AllConstants)
4893 EVT SVT = VT.getScalarType();
4894 if (!(VT.isVector() &&
4895 (!LegalTypes || (!LegalOperations && TLI.isTypeLegal(SVT))) &&
4896 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
4899 // We can fold this node into a build_vector.
4900 unsigned VTBits = SVT.getSizeInBits();
4901 unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
4902 unsigned ShAmt = VTBits - EVTBits;
4903 SmallVector<SDValue, 8> Elts;
4904 unsigned NumElts = N0->getNumOperands();
4907 for (unsigned i=0; i != NumElts; ++i) {
4908 SDValue Op = N0->getOperand(i);
4909 if (Op->getOpcode() == ISD::UNDEF) {
4910 Elts.push_back(DAG.getUNDEF(SVT));
4914 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
4915 const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
4916 if (Opcode == ISD::SIGN_EXTEND)
4917 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
4920 Elts.push_back(DAG.getConstant(C.shl(ShAmt).lshr(ShAmt).getZExtValue(),
4924 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts).getNode();
4927 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4928 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4929 // transformation. Returns true if extension are possible and the above
4930 // mentioned transformation is profitable.
4931 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4933 SmallVectorImpl<SDNode *> &ExtendNodes,
4934 const TargetLowering &TLI) {
4935 bool HasCopyToRegUses = false;
4936 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4937 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4938 UE = N0.getNode()->use_end();
4943 if (UI.getUse().getResNo() != N0.getResNo())
4945 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4946 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4947 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4948 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4949 // Sign bits will be lost after a zext.
4952 for (unsigned i = 0; i != 2; ++i) {
4953 SDValue UseOp = User->getOperand(i);
4956 if (!isa<ConstantSDNode>(UseOp))
4961 ExtendNodes.push_back(User);
4964 // If truncates aren't free and there are users we can't
4965 // extend, it isn't worthwhile.
4968 // Remember if this value is live-out.
4969 if (User->getOpcode() == ISD::CopyToReg)
4970 HasCopyToRegUses = true;
4973 if (HasCopyToRegUses) {
4974 bool BothLiveOut = false;
4975 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4977 SDUse &Use = UI.getUse();
4978 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4984 // Both unextended and extended values are live out. There had better be
4985 // a good reason for the transformation.
4986 return ExtendNodes.size();
4991 void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
4992 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
4993 ISD::NodeType ExtType) {
4994 // Extend SetCC uses if necessary.
4995 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4996 SDNode *SetCC = SetCCs[i];
4997 SmallVector<SDValue, 4> Ops;
4999 for (unsigned j = 0; j != 2; ++j) {
5000 SDValue SOp = SetCC->getOperand(j);
5002 Ops.push_back(ExtLoad);
5004 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
5007 Ops.push_back(SetCC->getOperand(2));
5008 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops));
5012 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
5013 SDValue N0 = N->getOperand(0);
5014 EVT VT = N->getValueType(0);
5016 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5018 return SDValue(Res, 0);
5020 // fold (sext (sext x)) -> (sext x)
5021 // fold (sext (aext x)) -> (sext x)
5022 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5023 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT,
5026 if (N0.getOpcode() == ISD::TRUNCATE) {
5027 // fold (sext (truncate (load x))) -> (sext (smaller load x))
5028 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
5029 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5030 if (NarrowLoad.getNode()) {
5031 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5032 if (NarrowLoad.getNode() != N0.getNode()) {
5033 CombineTo(N0.getNode(), NarrowLoad);
5034 // CombineTo deleted the truncate, if needed, but not what's under it.
5037 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5040 // See if the value being truncated is already sign extended. If so, just
5041 // eliminate the trunc/sext pair.
5042 SDValue Op = N0.getOperand(0);
5043 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
5044 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
5045 unsigned DestBits = VT.getScalarType().getSizeInBits();
5046 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
5048 if (OpBits == DestBits) {
5049 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
5050 // bits, it is already ready.
5051 if (NumSignBits > DestBits-MidBits)
5053 } else if (OpBits < DestBits) {
5054 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
5055 // bits, just sext from i32.
5056 if (NumSignBits > OpBits-MidBits)
5057 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, Op);
5059 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
5060 // bits, just truncate to i32.
5061 if (NumSignBits > OpBits-MidBits)
5062 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5065 // fold (sext (truncate x)) -> (sextinreg x).
5066 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
5067 N0.getValueType())) {
5068 if (OpBits < DestBits)
5069 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
5070 else if (OpBits > DestBits)
5071 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
5072 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op,
5073 DAG.getValueType(N0.getValueType()));
5077 // fold (sext (load x)) -> (sext (truncate (sextload x)))
5078 // None of the supported targets knows how to perform load and sign extend
5079 // on vectors in one instruction. We only perform this transformation on
5081 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5082 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5083 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5084 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
5085 bool DoXform = true;
5086 SmallVector<SDNode*, 4> SetCCs;
5087 if (!N0.hasOneUse())
5088 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
5090 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5091 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5093 LN0->getBasePtr(), N0.getValueType(),
5094 LN0->getMemOperand());
5095 CombineTo(N, ExtLoad);
5096 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5097 N0.getValueType(), ExtLoad);
5098 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5099 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5101 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5105 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
5106 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
5107 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5108 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5109 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5110 EVT MemVT = LN0->getMemoryVT();
5111 if ((!LegalOperations && !LN0->isVolatile()) ||
5112 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
5113 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5115 LN0->getBasePtr(), MemVT,
5116 LN0->getMemOperand());
5117 CombineTo(N, ExtLoad);
5118 CombineTo(N0.getNode(),
5119 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5120 N0.getValueType(), ExtLoad),
5121 ExtLoad.getValue(1));
5122 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5126 // fold (sext (and/or/xor (load x), cst)) ->
5127 // (and/or/xor (sextload x), (sext cst))
5128 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5129 N0.getOpcode() == ISD::XOR) &&
5130 isa<LoadSDNode>(N0.getOperand(0)) &&
5131 N0.getOperand(1).getOpcode() == ISD::Constant &&
5132 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
5133 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5134 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5135 if (LN0->getExtensionType() != ISD::ZEXTLOAD && LN0->isUnindexed()) {
5136 bool DoXform = true;
5137 SmallVector<SDNode*, 4> SetCCs;
5138 if (!N0.hasOneUse())
5139 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
5142 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT,
5143 LN0->getChain(), LN0->getBasePtr(),
5145 LN0->getMemOperand());
5146 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5147 Mask = Mask.sext(VT.getSizeInBits());
5148 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5149 ExtLoad, DAG.getConstant(Mask, VT));
5150 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5151 SDLoc(N0.getOperand(0)),
5152 N0.getOperand(0).getValueType(), ExtLoad);
5154 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5155 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5157 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5162 if (N0.getOpcode() == ISD::SETCC) {
5163 EVT N0VT = N0.getOperand(0).getValueType();
5164 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
5165 // Only do this before legalize for now.
5166 if (VT.isVector() && !LegalOperations &&
5167 TLI.getBooleanContents(N0VT) ==
5168 TargetLowering::ZeroOrNegativeOneBooleanContent) {
5169 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
5170 // of the same size as the compared operands. Only optimize sext(setcc())
5171 // if this is the case.
5172 EVT SVT = getSetCCResultType(N0VT);
5174 // We know that the # elements of the results is the same as the
5175 // # elements of the compare (and the # elements of the compare result
5176 // for that matter). Check to see that they are the same size. If so,
5177 // we know that the element size of the sext'd result matches the
5178 // element size of the compare operands.
5179 if (VT.getSizeInBits() == SVT.getSizeInBits())
5180 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5182 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5184 // If the desired elements are smaller or larger than the source
5185 // elements we can use a matching integer vector type and then
5186 // truncate/sign extend
5187 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
5188 if (SVT == MatchingVectorType) {
5189 SDValue VsetCC = DAG.getSetCC(SDLoc(N), MatchingVectorType,
5190 N0.getOperand(0), N0.getOperand(1),
5191 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5192 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT);
5196 // sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)
5197 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
5199 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
5201 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5202 NegOne, DAG.getConstant(0, VT),
5203 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5204 if (SCC.getNode()) return SCC;
5206 if (!VT.isVector()) {
5207 EVT SetCCVT = getSetCCResultType(N0.getOperand(0).getValueType());
5208 if (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, SetCCVT)) {
5210 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
5211 SDValue SetCC = DAG.getSetCC(DL,
5213 N0.getOperand(0), N0.getOperand(1), CC);
5214 EVT SelectVT = getSetCCResultType(VT);
5215 return DAG.getSelect(DL, VT,
5216 DAG.getSExtOrTrunc(SetCC, DL, SelectVT),
5217 NegOne, DAG.getConstant(0, VT));
5223 // fold (sext x) -> (zext x) if the sign bit is known zero.
5224 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
5225 DAG.SignBitIsZero(N0))
5226 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
5231 // isTruncateOf - If N is a truncate of some other value, return true, record
5232 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
5233 // This function computes KnownZero to avoid a duplicated call to
5234 // computeKnownBits in the caller.
5235 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
5238 if (N->getOpcode() == ISD::TRUNCATE) {
5239 Op = N->getOperand(0);
5240 DAG.computeKnownBits(Op, KnownZero, KnownOne);
5244 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
5245 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
5248 SDValue Op0 = N->getOperand(0);
5249 SDValue Op1 = N->getOperand(1);
5250 assert(Op0.getValueType() == Op1.getValueType());
5252 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0);
5253 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
5254 if (COp0 && COp0->isNullValue())
5256 else if (COp1 && COp1->isNullValue())
5261 DAG.computeKnownBits(Op, KnownZero, KnownOne);
5263 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
5269 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
5270 SDValue N0 = N->getOperand(0);
5271 EVT VT = N->getValueType(0);
5273 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5275 return SDValue(Res, 0);
5277 // fold (zext (zext x)) -> (zext x)
5278 // fold (zext (aext x)) -> (zext x)
5279 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5280 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
5283 // fold (zext (truncate x)) -> (zext x) or
5284 // (zext (truncate x)) -> (truncate x)
5285 // This is valid when the truncated bits of x are already zero.
5286 // FIXME: We should extend this to work for vectors too.
5289 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
5290 APInt TruncatedBits =
5291 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
5292 APInt(Op.getValueSizeInBits(), 0) :
5293 APInt::getBitsSet(Op.getValueSizeInBits(),
5294 N0.getValueSizeInBits(),
5295 std::min(Op.getValueSizeInBits(),
5296 VT.getSizeInBits()));
5297 if (TruncatedBits == (KnownZero & TruncatedBits)) {
5298 if (VT.bitsGT(Op.getValueType()))
5299 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op);
5300 if (VT.bitsLT(Op.getValueType()))
5301 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5307 // fold (zext (truncate (load x))) -> (zext (smaller load x))
5308 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
5309 if (N0.getOpcode() == ISD::TRUNCATE) {
5310 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5311 if (NarrowLoad.getNode()) {
5312 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5313 if (NarrowLoad.getNode() != N0.getNode()) {
5314 CombineTo(N0.getNode(), NarrowLoad);
5315 // CombineTo deleted the truncate, if needed, but not what's under it.
5318 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5322 // fold (zext (truncate x)) -> (and x, mask)
5323 if (N0.getOpcode() == ISD::TRUNCATE &&
5324 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
5326 // fold (zext (truncate (load x))) -> (zext (smaller load x))
5327 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
5328 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5329 if (NarrowLoad.getNode()) {
5330 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5331 if (NarrowLoad.getNode() != N0.getNode()) {
5332 CombineTo(N0.getNode(), NarrowLoad);
5333 // CombineTo deleted the truncate, if needed, but not what's under it.
5336 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5339 SDValue Op = N0.getOperand(0);
5340 if (Op.getValueType().bitsLT(VT)) {
5341 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Op);
5342 AddToWorklist(Op.getNode());
5343 } else if (Op.getValueType().bitsGT(VT)) {
5344 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5345 AddToWorklist(Op.getNode());
5347 return DAG.getZeroExtendInReg(Op, SDLoc(N),
5348 N0.getValueType().getScalarType());
5351 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
5352 // if either of the casts is not free.
5353 if (N0.getOpcode() == ISD::AND &&
5354 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5355 N0.getOperand(1).getOpcode() == ISD::Constant &&
5356 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
5357 N0.getValueType()) ||
5358 !TLI.isZExtFree(N0.getValueType(), VT))) {
5359 SDValue X = N0.getOperand(0).getOperand(0);
5360 if (X.getValueType().bitsLT(VT)) {
5361 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(X), VT, X);
5362 } else if (X.getValueType().bitsGT(VT)) {
5363 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
5365 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5366 Mask = Mask.zext(VT.getSizeInBits());
5367 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5368 X, DAG.getConstant(Mask, VT));
5371 // fold (zext (load x)) -> (zext (truncate (zextload x)))
5372 // None of the supported targets knows how to perform load and vector_zext
5373 // on vectors in one instruction. We only perform this transformation on
5375 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5376 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5377 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5378 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
5379 bool DoXform = true;
5380 SmallVector<SDNode*, 4> SetCCs;
5381 if (!N0.hasOneUse())
5382 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
5384 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5385 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
5387 LN0->getBasePtr(), N0.getValueType(),
5388 LN0->getMemOperand());
5389 CombineTo(N, ExtLoad);
5390 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5391 N0.getValueType(), ExtLoad);
5392 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5394 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5396 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5400 // fold (zext (and/or/xor (load x), cst)) ->
5401 // (and/or/xor (zextload x), (zext cst))
5402 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5403 N0.getOpcode() == ISD::XOR) &&
5404 isa<LoadSDNode>(N0.getOperand(0)) &&
5405 N0.getOperand(1).getOpcode() == ISD::Constant &&
5406 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
5407 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5408 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5409 if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) {
5410 bool DoXform = true;
5411 SmallVector<SDNode*, 4> SetCCs;
5412 if (!N0.hasOneUse())
5413 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
5416 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT,
5417 LN0->getChain(), LN0->getBasePtr(),
5419 LN0->getMemOperand());
5420 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5421 Mask = Mask.zext(VT.getSizeInBits());
5422 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
5423 ExtLoad, DAG.getConstant(Mask, VT));
5424 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5425 SDLoc(N0.getOperand(0)),
5426 N0.getOperand(0).getValueType(), ExtLoad);
5428 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5429 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5431 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5436 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
5437 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
5438 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5439 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5440 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5441 EVT MemVT = LN0->getMemoryVT();
5442 if ((!LegalOperations && !LN0->isVolatile()) ||
5443 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
5444 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
5446 LN0->getBasePtr(), MemVT,
5447 LN0->getMemOperand());
5448 CombineTo(N, ExtLoad);
5449 CombineTo(N0.getNode(),
5450 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
5452 ExtLoad.getValue(1));
5453 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5457 if (N0.getOpcode() == ISD::SETCC) {
5458 if (!LegalOperations && VT.isVector() &&
5459 N0.getValueType().getVectorElementType() == MVT::i1) {
5460 EVT N0VT = N0.getOperand(0).getValueType();
5461 if (getSetCCResultType(N0VT) == N0.getValueType())
5464 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
5465 // Only do this before legalize for now.
5466 EVT EltVT = VT.getVectorElementType();
5467 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
5468 DAG.getConstant(1, EltVT));
5469 if (VT.getSizeInBits() == N0VT.getSizeInBits())
5470 // We know that the # elements of the results is the same as the
5471 // # elements of the compare (and the # elements of the compare result
5472 // for that matter). Check to see that they are the same size. If so,
5473 // we know that the element size of the sext'd result matches the
5474 // element size of the compare operands.
5475 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5476 DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5478 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
5479 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT,
5482 // If the desired elements are smaller or larger than the source
5483 // elements we can use a matching integer vector type and then
5484 // truncate/sign extend
5485 EVT MatchingElementType =
5486 EVT::getIntegerVT(*DAG.getContext(),
5487 N0VT.getScalarType().getSizeInBits());
5488 EVT MatchingVectorType =
5489 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
5490 N0VT.getVectorNumElements());
5492 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5494 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5495 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5496 DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT),
5497 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, OneOps));
5500 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5502 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5503 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
5504 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5505 if (SCC.getNode()) return SCC;
5508 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
5509 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
5510 isa<ConstantSDNode>(N0.getOperand(1)) &&
5511 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
5513 SDValue ShAmt = N0.getOperand(1);
5514 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5515 if (N0.getOpcode() == ISD::SHL) {
5516 SDValue InnerZExt = N0.getOperand(0);
5517 // If the original shl may be shifting out bits, do not perform this
5519 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
5520 InnerZExt.getOperand(0).getValueType().getSizeInBits();
5521 if (ShAmtVal > KnownZeroBits)
5527 // Ensure that the shift amount is wide enough for the shifted value.
5528 if (VT.getSizeInBits() >= 256)
5529 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
5531 return DAG.getNode(N0.getOpcode(), DL, VT,
5532 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
5539 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
5540 SDValue N0 = N->getOperand(0);
5541 EVT VT = N->getValueType(0);
5543 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5545 return SDValue(Res, 0);
5547 // fold (aext (aext x)) -> (aext x)
5548 // fold (aext (zext x)) -> (zext x)
5549 // fold (aext (sext x)) -> (sext x)
5550 if (N0.getOpcode() == ISD::ANY_EXTEND ||
5551 N0.getOpcode() == ISD::ZERO_EXTEND ||
5552 N0.getOpcode() == ISD::SIGN_EXTEND)
5553 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
5555 // fold (aext (truncate (load x))) -> (aext (smaller load x))
5556 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
5557 if (N0.getOpcode() == ISD::TRUNCATE) {
5558 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
5559 if (NarrowLoad.getNode()) {
5560 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5561 if (NarrowLoad.getNode() != N0.getNode()) {
5562 CombineTo(N0.getNode(), NarrowLoad);
5563 // CombineTo deleted the truncate, if needed, but not what's under it.
5566 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5570 // fold (aext (truncate x))
5571 if (N0.getOpcode() == ISD::TRUNCATE) {
5572 SDValue TruncOp = N0.getOperand(0);
5573 if (TruncOp.getValueType() == VT)
5574 return TruncOp; // x iff x size == zext size.
5575 if (TruncOp.getValueType().bitsGT(VT))
5576 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, TruncOp);
5577 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, TruncOp);
5580 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
5581 // if the trunc is not free.
5582 if (N0.getOpcode() == ISD::AND &&
5583 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
5584 N0.getOperand(1).getOpcode() == ISD::Constant &&
5585 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
5586 N0.getValueType())) {
5587 SDValue X = N0.getOperand(0).getOperand(0);
5588 if (X.getValueType().bitsLT(VT)) {
5589 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, X);
5590 } else if (X.getValueType().bitsGT(VT)) {
5591 X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X);
5593 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5594 Mask = Mask.zext(VT.getSizeInBits());
5595 return DAG.getNode(ISD::AND, SDLoc(N), VT,
5596 X, DAG.getConstant(Mask, VT));
5599 // fold (aext (load x)) -> (aext (truncate (extload x)))
5600 // None of the supported targets knows how to perform load and any_ext
5601 // on vectors in one instruction. We only perform this transformation on
5603 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
5604 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5605 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType())) {
5606 bool DoXform = true;
5607 SmallVector<SDNode*, 4> SetCCs;
5608 if (!N0.hasOneUse())
5609 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
5611 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5612 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
5614 LN0->getBasePtr(), N0.getValueType(),
5615 LN0->getMemOperand());
5616 CombineTo(N, ExtLoad);
5617 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5618 N0.getValueType(), ExtLoad);
5619 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5620 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5622 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5626 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
5627 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
5628 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
5629 if (N0.getOpcode() == ISD::LOAD &&
5630 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5632 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5633 ISD::LoadExtType ExtType = LN0->getExtensionType();
5634 EVT MemVT = LN0->getMemoryVT();
5635 if (!LegalOperations || TLI.isLoadExtLegal(ExtType, MemVT)) {
5636 SDValue ExtLoad = DAG.getExtLoad(ExtType, SDLoc(N),
5637 VT, LN0->getChain(), LN0->getBasePtr(),
5638 MemVT, LN0->getMemOperand());
5639 CombineTo(N, ExtLoad);
5640 CombineTo(N0.getNode(),
5641 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5642 N0.getValueType(), ExtLoad),
5643 ExtLoad.getValue(1));
5644 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5648 if (N0.getOpcode() == ISD::SETCC) {
5650 // aext(setcc) -> vsetcc
5651 // aext(setcc) -> truncate(vsetcc)
5652 // aext(setcc) -> aext(vsetcc)
5653 // Only do this before legalize for now.
5654 if (VT.isVector() && !LegalOperations) {
5655 EVT N0VT = N0.getOperand(0).getValueType();
5656 // We know that the # elements of the results is the same as the
5657 // # elements of the compare (and the # elements of the compare result
5658 // for that matter). Check to see that they are the same size. If so,
5659 // we know that the element size of the sext'd result matches the
5660 // element size of the compare operands.
5661 if (VT.getSizeInBits() == N0VT.getSizeInBits())
5662 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5664 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5665 // If the desired elements are smaller or larger than the source
5666 // elements we can use a matching integer vector type and then
5667 // truncate/any extend
5669 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
5671 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
5673 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5674 return DAG.getAnyExtOrTrunc(VsetCC, SDLoc(N), VT);
5678 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
5680 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1),
5681 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
5682 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
5690 /// GetDemandedBits - See if the specified operand can be simplified with the
5691 /// knowledge that only the bits specified by Mask are used. If so, return the
5692 /// simpler operand, otherwise return a null SDValue.
5693 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
5694 switch (V.getOpcode()) {
5696 case ISD::Constant: {
5697 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
5698 assert(CV && "Const value should be ConstSDNode.");
5699 const APInt &CVal = CV->getAPIntValue();
5700 APInt NewVal = CVal & Mask;
5702 return DAG.getConstant(NewVal, V.getValueType());
5707 // If the LHS or RHS don't contribute bits to the or, drop them.
5708 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
5709 return V.getOperand(1);
5710 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
5711 return V.getOperand(0);
5714 // Only look at single-use SRLs.
5715 if (!V.getNode()->hasOneUse())
5717 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
5718 // See if we can recursively simplify the LHS.
5719 unsigned Amt = RHSC->getZExtValue();
5721 // Watch out for shift count overflow though.
5722 if (Amt >= Mask.getBitWidth()) break;
5723 APInt NewMask = Mask << Amt;
5724 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
5725 if (SimplifyLHS.getNode())
5726 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
5727 SimplifyLHS, V.getOperand(1));
5733 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
5734 /// bits and then truncated to a narrower type and where N is a multiple
5735 /// of number of bits of the narrower type, transform it to a narrower load
5736 /// from address + N / num of bits of new type. If the result is to be
5737 /// extended, also fold the extension to form a extending load.
5738 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
5739 unsigned Opc = N->getOpcode();
5741 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
5742 SDValue N0 = N->getOperand(0);
5743 EVT VT = N->getValueType(0);
5746 // This transformation isn't valid for vector loads.
5750 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
5752 if (Opc == ISD::SIGN_EXTEND_INREG) {
5753 ExtType = ISD::SEXTLOAD;
5754 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5755 } else if (Opc == ISD::SRL) {
5756 // Another special-case: SRL is basically zero-extending a narrower value.
5757 ExtType = ISD::ZEXTLOAD;
5759 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
5760 if (!N01) return SDValue();
5761 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
5762 VT.getSizeInBits() - N01->getZExtValue());
5764 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
5767 unsigned EVTBits = ExtVT.getSizeInBits();
5769 // Do not generate loads of non-round integer types since these can
5770 // be expensive (and would be wrong if the type is not byte sized).
5771 if (!ExtVT.isRound())
5775 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
5776 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5777 ShAmt = N01->getZExtValue();
5778 // Is the shift amount a multiple of size of VT?
5779 if ((ShAmt & (EVTBits-1)) == 0) {
5780 N0 = N0.getOperand(0);
5781 // Is the load width a multiple of size of VT?
5782 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
5786 // At this point, we must have a load or else we can't do the transform.
5787 if (!isa<LoadSDNode>(N0)) return SDValue();
5789 // Because a SRL must be assumed to *need* to zero-extend the high bits
5790 // (as opposed to anyext the high bits), we can't combine the zextload
5791 // lowering of SRL and an sextload.
5792 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
5795 // If the shift amount is larger than the input type then we're not
5796 // accessing any of the loaded bytes. If the load was a zextload/extload
5797 // then the result of the shift+trunc is zero/undef (handled elsewhere).
5798 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
5803 // If the load is shifted left (and the result isn't shifted back right),
5804 // we can fold the truncate through the shift.
5805 unsigned ShLeftAmt = 0;
5806 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
5807 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
5808 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
5809 ShLeftAmt = N01->getZExtValue();
5810 N0 = N0.getOperand(0);
5814 // If we haven't found a load, we can't narrow it. Don't transform one with
5815 // multiple uses, this would require adding a new load.
5816 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
5819 // Don't change the width of a volatile load.
5820 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5821 if (LN0->isVolatile())
5824 // Verify that we are actually reducing a load width here.
5825 if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
5828 // For the transform to be legal, the load must produce only two values
5829 // (the value loaded and the chain). Don't transform a pre-increment
5830 // load, for example, which produces an extra value. Otherwise the
5831 // transformation is not equivalent, and the downstream logic to replace
5832 // uses gets things wrong.
5833 if (LN0->getNumValues() > 2)
5836 // If the load that we're shrinking is an extload and we're not just
5837 // discarding the extension we can't simply shrink the load. Bail.
5838 // TODO: It would be possible to merge the extensions in some cases.
5839 if (LN0->getExtensionType() != ISD::NON_EXTLOAD &&
5840 LN0->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
5843 EVT PtrType = N0.getOperand(1).getValueType();
5845 if (PtrType == MVT::Untyped || PtrType.isExtended())
5846 // It's not possible to generate a constant of extended or untyped type.
5849 // For big endian targets, we need to adjust the offset to the pointer to
5850 // load the correct bytes.
5851 if (TLI.isBigEndian()) {
5852 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
5853 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
5854 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
5857 uint64_t PtrOff = ShAmt / 8;
5858 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
5859 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0),
5860 PtrType, LN0->getBasePtr(),
5861 DAG.getConstant(PtrOff, PtrType));
5862 AddToWorklist(NewPtr.getNode());
5865 if (ExtType == ISD::NON_EXTLOAD)
5866 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr,
5867 LN0->getPointerInfo().getWithOffset(PtrOff),
5868 LN0->isVolatile(), LN0->isNonTemporal(),
5869 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
5871 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr,
5872 LN0->getPointerInfo().getWithOffset(PtrOff),
5873 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
5874 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
5876 // Replace the old load's chain with the new load's chain.
5877 WorklistRemover DeadNodes(*this);
5878 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
5880 // Shift the result left, if we've swallowed a left shift.
5881 SDValue Result = Load;
5882 if (ShLeftAmt != 0) {
5883 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
5884 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
5886 // If the shift amount is as large as the result size (but, presumably,
5887 // no larger than the source) then the useful bits of the result are
5888 // zero; we can't simply return the shortened shift, because the result
5889 // of that operation is undefined.
5890 if (ShLeftAmt >= VT.getSizeInBits())
5891 Result = DAG.getConstant(0, VT);
5893 Result = DAG.getNode(ISD::SHL, SDLoc(N0), VT,
5894 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
5897 // Return the new loaded value.
5901 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
5902 SDValue N0 = N->getOperand(0);
5903 SDValue N1 = N->getOperand(1);
5904 EVT VT = N->getValueType(0);
5905 EVT EVT = cast<VTSDNode>(N1)->getVT();
5906 unsigned VTBits = VT.getScalarType().getSizeInBits();
5907 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
5909 // fold (sext_in_reg c1) -> c1
5910 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
5911 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
5913 // If the input is already sign extended, just drop the extension.
5914 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
5917 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
5918 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
5919 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
5920 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
5921 N0.getOperand(0), N1);
5923 // fold (sext_in_reg (sext x)) -> (sext x)
5924 // fold (sext_in_reg (aext x)) -> (sext x)
5925 // if x is small enough.
5926 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
5927 SDValue N00 = N0.getOperand(0);
5928 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
5929 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
5930 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
5933 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
5934 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
5935 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);
5937 // fold operands of sext_in_reg based on knowledge that the top bits are not
5939 if (SimplifyDemandedBits(SDValue(N, 0)))
5940 return SDValue(N, 0);
5942 // fold (sext_in_reg (load x)) -> (smaller sextload x)
5943 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
5944 SDValue NarrowLoad = ReduceLoadWidth(N);
5945 if (NarrowLoad.getNode())
5948 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5949 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5950 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5951 if (N0.getOpcode() == ISD::SRL) {
5952 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5953 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5954 // We can turn this into an SRA iff the input to the SRL is already sign
5956 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5957 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5958 return DAG.getNode(ISD::SRA, SDLoc(N), VT,
5959 N0.getOperand(0), N0.getOperand(1));
5963 // fold (sext_inreg (extload x)) -> (sextload x)
5964 if (ISD::isEXTLoad(N0.getNode()) &&
5965 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5966 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5967 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5968 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5969 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5970 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5972 LN0->getBasePtr(), EVT,
5973 LN0->getMemOperand());
5974 CombineTo(N, ExtLoad);
5975 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5976 AddToWorklist(ExtLoad.getNode());
5977 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5979 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5980 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5982 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5983 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5984 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5985 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5986 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5988 LN0->getBasePtr(), EVT,
5989 LN0->getMemOperand());
5990 CombineTo(N, ExtLoad);
5991 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5992 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5995 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5996 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5997 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5998 N0.getOperand(1), false);
5999 if (BSwap.getNode())
6000 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6004 // Fold a sext_inreg of a build_vector of ConstantSDNodes or undefs
6005 // into a build_vector.
6006 if (ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
6007 SmallVector<SDValue, 8> Elts;
6008 unsigned NumElts = N0->getNumOperands();
6009 unsigned ShAmt = VTBits - EVTBits;
6011 for (unsigned i = 0; i != NumElts; ++i) {
6012 SDValue Op = N0->getOperand(i);
6013 if (Op->getOpcode() == ISD::UNDEF) {
6018 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
6019 const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
6020 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
6021 Op.getValueType()));
6024 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Elts);
6030 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
6031 SDValue N0 = N->getOperand(0);
6032 EVT VT = N->getValueType(0);
6033 bool isLE = TLI.isLittleEndian();
6036 if (N0.getValueType() == N->getValueType(0))
6038 // fold (truncate c1) -> c1
6039 if (isa<ConstantSDNode>(N0))
6040 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0);
6041 // fold (truncate (truncate x)) -> (truncate x)
6042 if (N0.getOpcode() == ISD::TRUNCATE)
6043 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6044 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
6045 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
6046 N0.getOpcode() == ISD::SIGN_EXTEND ||
6047 N0.getOpcode() == ISD::ANY_EXTEND) {
6048 if (N0.getOperand(0).getValueType().bitsLT(VT))
6049 // if the source is smaller than the dest, we still need an extend
6050 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
6052 if (N0.getOperand(0).getValueType().bitsGT(VT))
6053 // if the source is larger than the dest, than we just need the truncate
6054 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6055 // if the source and dest are the same type, we can drop both the extend
6056 // and the truncate.
6057 return N0.getOperand(0);
6060 // Fold extract-and-trunc into a narrow extract. For example:
6061 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
6062 // i32 y = TRUNCATE(i64 x)
6064 // v16i8 b = BITCAST (v2i64 val)
6065 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
6067 // Note: We only run this optimization after type legalization (which often
6068 // creates this pattern) and before operation legalization after which
6069 // we need to be more careful about the vector instructions that we generate.
6070 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6071 LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) {
6073 EVT VecTy = N0.getOperand(0).getValueType();
6074 EVT ExTy = N0.getValueType();
6075 EVT TrTy = N->getValueType(0);
6077 unsigned NumElem = VecTy.getVectorNumElements();
6078 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
6080 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
6081 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
6083 SDValue EltNo = N0->getOperand(1);
6084 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
6085 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6086 EVT IndexTy = TLI.getVectorIdxTy();
6087 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
6089 SDValue V = DAG.getNode(ISD::BITCAST, SDLoc(N),
6090 NVT, N0.getOperand(0));
6092 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
6094 DAG.getConstant(Index, IndexTy));
6098 // trunc (select c, a, b) -> select c, (trunc a), (trunc b)
6099 if (N0.getOpcode() == ISD::SELECT) {
6100 EVT SrcVT = N0.getValueType();
6101 if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
6102 TLI.isTruncateFree(SrcVT, VT)) {
6104 SDValue Cond = N0.getOperand(0);
6105 SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
6106 SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2));
6107 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, Cond, TruncOp0, TruncOp1);
6111 // Fold a series of buildvector, bitcast, and truncate if possible.
6113 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to
6114 // (2xi32 (buildvector x, y)).
6115 if (Level == AfterLegalizeVectorOps && VT.isVector() &&
6116 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
6117 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
6118 N0.getOperand(0).hasOneUse()) {
6120 SDValue BuildVect = N0.getOperand(0);
6121 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType();
6122 EVT TruncVecEltTy = VT.getVectorElementType();
6124 // Check that the element types match.
6125 if (BuildVectEltTy == TruncVecEltTy) {
6126 // Now we only need to compute the offset of the truncated elements.
6127 unsigned BuildVecNumElts = BuildVect.getNumOperands();
6128 unsigned TruncVecNumElts = VT.getVectorNumElements();
6129 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts;
6131 assert((BuildVecNumElts % TruncVecNumElts) == 0 &&
6132 "Invalid number of elements");
6134 SmallVector<SDValue, 8> Opnds;
6135 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
6136 Opnds.push_back(BuildVect.getOperand(i));
6138 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
6142 // See if we can simplify the input to this truncate through knowledge that
6143 // only the low bits are being used.
6144 // For example "trunc (or (shl x, 8), y)" // -> trunc y
6145 // Currently we only perform this optimization on scalars because vectors
6146 // may have different active low bits.
6147 if (!VT.isVector()) {
6149 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
6150 VT.getSizeInBits()));
6151 if (Shorter.getNode())
6152 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter);
6154 // fold (truncate (load x)) -> (smaller load x)
6155 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
6156 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
6157 SDValue Reduced = ReduceLoadWidth(N);
6158 if (Reduced.getNode())
6160 // Handle the case where the load remains an extending load even
6161 // after truncation.
6162 if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) {
6163 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6164 if (!LN0->isVolatile() &&
6165 LN0->getMemoryVT().getStoreSizeInBits() < VT.getSizeInBits()) {
6166 SDValue NewLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(LN0),
6167 VT, LN0->getChain(), LN0->getBasePtr(),
6169 LN0->getMemOperand());
6170 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1));
6175 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
6176 // where ... are all 'undef'.
6177 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
6178 SmallVector<EVT, 8> VTs;
6181 unsigned NumDefs = 0;
6183 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
6184 SDValue X = N0.getOperand(i);
6185 if (X.getOpcode() != ISD::UNDEF) {
6190 // Stop if more than one members are non-undef.
6193 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
6194 VT.getVectorElementType(),
6195 X.getValueType().getVectorNumElements()));
6199 return DAG.getUNDEF(VT);
6202 assert(V.getNode() && "The single defined operand is empty!");
6203 SmallVector<SDValue, 8> Opnds;
6204 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
6206 Opnds.push_back(DAG.getUNDEF(VTs[i]));
6209 SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V);
6210 AddToWorklist(NV.getNode());
6211 Opnds.push_back(NV);
6213 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds);
6217 // Simplify the operands using demanded-bits information.
6218 if (!VT.isVector() &&
6219 SimplifyDemandedBits(SDValue(N, 0)))
6220 return SDValue(N, 0);
6225 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
6226 SDValue Elt = N->getOperand(i);
6227 if (Elt.getOpcode() != ISD::MERGE_VALUES)
6228 return Elt.getNode();
6229 return Elt.getOperand(Elt.getResNo()).getNode();
6232 /// CombineConsecutiveLoads - build_pair (load, load) -> load
6233 /// if load locations are consecutive.
6234 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
6235 assert(N->getOpcode() == ISD::BUILD_PAIR);
6237 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
6238 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
6239 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
6240 LD1->getAddressSpace() != LD2->getAddressSpace())
6242 EVT LD1VT = LD1->getValueType(0);
6244 if (ISD::isNON_EXTLoad(LD2) &&
6246 // If both are volatile this would reduce the number of volatile loads.
6247 // If one is volatile it might be ok, but play conservative and bail out.
6248 !LD1->isVolatile() &&
6249 !LD2->isVolatile() &&
6250 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
6251 unsigned Align = LD1->getAlignment();
6252 unsigned NewAlign = TLI.getDataLayout()->
6253 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
6255 if (NewAlign <= Align &&
6256 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
6257 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(),
6258 LD1->getBasePtr(), LD1->getPointerInfo(),
6259 false, false, false, Align);
6265 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
6266 SDValue N0 = N->getOperand(0);
6267 EVT VT = N->getValueType(0);
6269 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
6270 // Only do this before legalize, since afterward the target may be depending
6271 // on the bitconvert.
6272 // First check to see if this is all constant.
6274 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
6276 bool isSimple = cast<BuildVectorSDNode>(N0)->isConstant();
6278 EVT DestEltVT = N->getValueType(0).getVectorElementType();
6279 assert(!DestEltVT.isVector() &&
6280 "Element type of vector ValueType must not be vector!");
6282 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
6285 // If the input is a constant, let getNode fold it.
6286 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
6287 SDValue Res = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0);
6288 if (Res.getNode() != N) {
6289 if (!LegalOperations ||
6290 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
6293 // Folding it resulted in an illegal node, and it's too late to
6294 // do that. Clean up the old node and forego the transformation.
6295 // Ideally this won't happen very often, because instcombine
6296 // and the earlier dagcombine runs (where illegal nodes are
6297 // permitted) should have folded most of them already.
6298 deleteAndRecombine(Res.getNode());
6302 // (conv (conv x, t1), t2) -> (conv x, t2)
6303 if (N0.getOpcode() == ISD::BITCAST)
6304 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT,
6307 // fold (conv (load x)) -> (load (conv*)x)
6308 // If the resultant load doesn't need a higher alignment than the original!
6309 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6310 // Do not change the width of a volatile load.
6311 !cast<LoadSDNode>(N0)->isVolatile() &&
6312 // Do not remove the cast if the types differ in endian layout.
6313 TLI.hasBigEndianPartOrdering(N0.getValueType()) ==
6314 TLI.hasBigEndianPartOrdering(VT) &&
6315 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) &&
6316 TLI.isLoadBitCastBeneficial(N0.getValueType(), VT)) {
6317 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6318 unsigned Align = TLI.getDataLayout()->
6319 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
6320 unsigned OrigAlign = LN0->getAlignment();
6322 if (Align <= OrigAlign) {
6323 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(),
6324 LN0->getBasePtr(), LN0->getPointerInfo(),
6325 LN0->isVolatile(), LN0->isNonTemporal(),
6326 LN0->isInvariant(), OrigAlign,
6328 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
6333 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
6334 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
6335 // This often reduces constant pool loads.
6336 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
6337 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
6338 N0.getNode()->hasOneUse() && VT.isInteger() &&
6339 !VT.isVector() && !N0.getValueType().isVector()) {
6340 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
6342 AddToWorklist(NewConv.getNode());
6344 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
6345 if (N0.getOpcode() == ISD::FNEG)
6346 return DAG.getNode(ISD::XOR, SDLoc(N), VT,
6347 NewConv, DAG.getConstant(SignBit, VT));
6348 assert(N0.getOpcode() == ISD::FABS);
6349 return DAG.getNode(ISD::AND, SDLoc(N), VT,
6350 NewConv, DAG.getConstant(~SignBit, VT));
6353 // fold (bitconvert (fcopysign cst, x)) ->
6354 // (or (and (bitconvert x), sign), (and cst, (not sign)))
6355 // Note that we don't handle (copysign x, cst) because this can always be
6356 // folded to an fneg or fabs.
6357 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
6358 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
6359 VT.isInteger() && !VT.isVector()) {
6360 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
6361 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
6362 if (isTypeLegal(IntXVT)) {
6363 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6364 IntXVT, N0.getOperand(1));
6365 AddToWorklist(X.getNode());
6367 // If X has a different width than the result/lhs, sext it or truncate it.
6368 unsigned VTWidth = VT.getSizeInBits();
6369 if (OrigXWidth < VTWidth) {
6370 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X);
6371 AddToWorklist(X.getNode());
6372 } else if (OrigXWidth > VTWidth) {
6373 // To get the sign bit in the right place, we have to shift it right
6374 // before truncating.
6375 X = DAG.getNode(ISD::SRL, SDLoc(X),
6376 X.getValueType(), X,
6377 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
6378 AddToWorklist(X.getNode());
6379 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
6380 AddToWorklist(X.getNode());
6383 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
6384 X = DAG.getNode(ISD::AND, SDLoc(X), VT,
6385 X, DAG.getConstant(SignBit, VT));
6386 AddToWorklist(X.getNode());
6388 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0),
6389 VT, N0.getOperand(0));
6390 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT,
6391 Cst, DAG.getConstant(~SignBit, VT));
6392 AddToWorklist(Cst.getNode());
6394 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst);
6398 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
6399 if (N0.getOpcode() == ISD::BUILD_PAIR) {
6400 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
6401 if (CombineLD.getNode())
6408 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
6409 EVT VT = N->getValueType(0);
6410 return CombineConsecutiveLoads(N, VT);
6413 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
6414 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
6415 /// destination element value type.
6416 SDValue DAGCombiner::
6417 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
6418 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
6420 // If this is already the right type, we're done.
6421 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
6423 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
6424 unsigned DstBitSize = DstEltVT.getSizeInBits();
6426 // If this is a conversion of N elements of one type to N elements of another
6427 // type, convert each element. This handles FP<->INT cases.
6428 if (SrcBitSize == DstBitSize) {
6429 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
6430 BV->getValueType(0).getVectorNumElements());
6432 // Due to the FP element handling below calling this routine recursively,
6433 // we can end up with a scalar-to-vector node here.
6434 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
6435 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
6436 DAG.getNode(ISD::BITCAST, SDLoc(BV),
6437 DstEltVT, BV->getOperand(0)));
6439 SmallVector<SDValue, 8> Ops;
6440 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
6441 SDValue Op = BV->getOperand(i);
6442 // If the vector element type is not legal, the BUILD_VECTOR operands
6443 // are promoted and implicitly truncated. Make that explicit here.
6444 if (Op.getValueType() != SrcEltVT)
6445 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op);
6446 Ops.push_back(DAG.getNode(ISD::BITCAST, SDLoc(BV),
6448 AddToWorklist(Ops.back().getNode());
6450 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6453 // Otherwise, we're growing or shrinking the elements. To avoid having to
6454 // handle annoying details of growing/shrinking FP values, we convert them to
6456 if (SrcEltVT.isFloatingPoint()) {
6457 // Convert the input float vector to a int vector where the elements are the
6459 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
6460 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
6461 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
6465 // Now we know the input is an integer vector. If the output is a FP type,
6466 // convert to integer first, then to FP of the right size.
6467 if (DstEltVT.isFloatingPoint()) {
6468 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
6469 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
6470 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
6472 // Next, convert to FP elements of the same size.
6473 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
6476 // Okay, we know the src/dst types are both integers of differing types.
6477 // Handling growing first.
6478 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
6479 if (SrcBitSize < DstBitSize) {
6480 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
6482 SmallVector<SDValue, 8> Ops;
6483 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
6484 i += NumInputsPerOutput) {
6485 bool isLE = TLI.isLittleEndian();
6486 APInt NewBits = APInt(DstBitSize, 0);
6487 bool EltIsUndef = true;
6488 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
6489 // Shift the previously computed bits over.
6490 NewBits <<= SrcBitSize;
6491 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
6492 if (Op.getOpcode() == ISD::UNDEF) continue;
6495 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
6496 zextOrTrunc(SrcBitSize).zext(DstBitSize);
6500 Ops.push_back(DAG.getUNDEF(DstEltVT));
6502 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
6505 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
6506 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6509 // Finally, this must be the case where we are shrinking elements: each input
6510 // turns into multiple outputs.
6511 bool isS2V = ISD::isScalarToVector(BV);
6512 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
6513 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
6514 NumOutputsPerInput*BV->getNumOperands());
6515 SmallVector<SDValue, 8> Ops;
6517 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
6518 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
6519 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
6520 Ops.push_back(DAG.getUNDEF(DstEltVT));
6524 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
6525 getAPIntValue().zextOrTrunc(SrcBitSize);
6527 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
6528 APInt ThisVal = OpVal.trunc(DstBitSize);
6529 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
6530 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
6531 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
6532 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
6534 OpVal = OpVal.lshr(DstBitSize);
6537 // For big endian targets, swap the order of the pieces of each element.
6538 if (TLI.isBigEndian())
6539 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
6542 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
6545 SDValue DAGCombiner::visitFADD(SDNode *N) {
6546 SDValue N0 = N->getOperand(0);
6547 SDValue N1 = N->getOperand(1);
6548 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6549 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6550 EVT VT = N->getValueType(0);
6553 if (VT.isVector()) {
6554 SDValue FoldedVOp = SimplifyVBinOp(N);
6555 if (FoldedVOp.getNode()) return FoldedVOp;
6558 // fold (fadd c1, c2) -> c1 + c2
6560 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N1);
6561 // canonicalize constant to RHS
6562 if (N0CFP && !N1CFP)
6563 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N0);
6564 // fold (fadd A, 0) -> A
6565 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6566 N1CFP->getValueAPF().isZero())
6568 // fold (fadd A, (fneg B)) -> (fsub A, B)
6569 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6570 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
6571 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0,
6572 GetNegatedExpression(N1, DAG, LegalOperations));
6573 // fold (fadd (fneg A), B) -> (fsub B, A)
6574 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
6575 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2)
6576 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N1,
6577 GetNegatedExpression(N0, DAG, LegalOperations));
6579 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
6580 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6581 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
6582 isa<ConstantFPSDNode>(N0.getOperand(1)))
6583 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0),
6584 DAG.getNode(ISD::FADD, SDLoc(N), VT,
6585 N0.getOperand(1), N1));
6587 // No FP constant should be created after legalization as Instruction
6588 // Selection pass has hard time in dealing with FP constant.
6590 // We don't need test this condition for transformation like following, as
6591 // the DAG being transformed implies it is legal to take FP constant as
6594 // (fadd (fmul c, x), x) -> (fmul c+1, x)
6596 bool AllowNewFpConst = (Level < AfterLegalizeDAG);
6598 // If allow, fold (fadd (fneg x), x) -> 0.0
6599 if (AllowNewFpConst && DAG.getTarget().Options.UnsafeFPMath &&
6600 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
6601 return DAG.getConstantFP(0.0, VT);
6603 // If allow, fold (fadd x, (fneg x)) -> 0.0
6604 if (AllowNewFpConst && DAG.getTarget().Options.UnsafeFPMath &&
6605 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
6606 return DAG.getConstantFP(0.0, VT);
6608 // In unsafe math mode, we can fold chains of FADD's of the same value
6609 // into multiplications. This transform is not safe in general because
6610 // we are reducing the number of rounding steps.
6611 if (DAG.getTarget().Options.UnsafeFPMath &&
6612 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) &&
6614 if (N0.getOpcode() == ISD::FMUL) {
6615 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6616 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
6618 // (fadd (fmul c, x), x) -> (fmul x, c+1)
6619 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) {
6620 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6622 DAG.getConstantFP(1.0, VT));
6623 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6627 // (fadd (fmul x, c), x) -> (fmul x, c+1)
6628 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
6629 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6631 DAG.getConstantFP(1.0, VT));
6632 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6636 // (fadd (fmul c, x), (fadd x, x)) -> (fmul x, c+2)
6637 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD &&
6638 N1.getOperand(0) == N1.getOperand(1) &&
6639 N0.getOperand(1) == N1.getOperand(0)) {
6640 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6642 DAG.getConstantFP(2.0, VT));
6643 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6644 N0.getOperand(1), NewCFP);
6647 // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2)
6648 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
6649 N1.getOperand(0) == N1.getOperand(1) &&
6650 N0.getOperand(0) == N1.getOperand(0)) {
6651 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6653 DAG.getConstantFP(2.0, VT));
6654 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6655 N0.getOperand(0), NewCFP);
6659 if (N1.getOpcode() == ISD::FMUL) {
6660 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
6661 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
6663 // (fadd x, (fmul c, x)) -> (fmul x, c+1)
6664 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) {
6665 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6667 DAG.getConstantFP(1.0, VT));
6668 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6672 // (fadd x, (fmul x, c)) -> (fmul x, c+1)
6673 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
6674 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6676 DAG.getConstantFP(1.0, VT));
6677 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6682 // (fadd (fadd x, x), (fmul c, x)) -> (fmul x, c+2)
6683 if (CFP10 && !CFP11 && N0.getOpcode() == ISD::FADD &&
6684 N0.getOperand(0) == N0.getOperand(1) &&
6685 N1.getOperand(1) == N0.getOperand(0)) {
6686 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6688 DAG.getConstantFP(2.0, VT));
6689 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6690 N1.getOperand(1), NewCFP);
6693 // (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2)
6694 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
6695 N0.getOperand(0) == N0.getOperand(1) &&
6696 N1.getOperand(0) == N0.getOperand(0)) {
6697 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT,
6699 DAG.getConstantFP(2.0, VT));
6700 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6701 N1.getOperand(0), NewCFP);
6705 if (N0.getOpcode() == ISD::FADD && AllowNewFpConst) {
6706 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
6707 // (fadd (fadd x, x), x) -> (fmul x, 3.0)
6708 if (!CFP && N0.getOperand(0) == N0.getOperand(1) &&
6709 (N0.getOperand(0) == N1))
6710 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6711 N1, DAG.getConstantFP(3.0, VT));
6714 if (N1.getOpcode() == ISD::FADD && AllowNewFpConst) {
6715 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
6716 // (fadd x, (fadd x, x)) -> (fmul x, 3.0)
6717 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) &&
6718 N1.getOperand(0) == N0)
6719 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6720 N0, DAG.getConstantFP(3.0, VT));
6723 // (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0)
6724 if (AllowNewFpConst &&
6725 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
6726 N0.getOperand(0) == N0.getOperand(1) &&
6727 N1.getOperand(0) == N1.getOperand(1) &&
6728 N0.getOperand(0) == N1.getOperand(0))
6729 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6731 DAG.getConstantFP(4.0, VT));
6734 // FADD -> FMA combines:
6735 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast ||
6736 DAG.getTarget().Options.UnsafeFPMath) &&
6739 ->getTargetLowering()
6740 ->isFMAFasterThanFMulAndFAdd(VT) &&
6741 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
6743 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
6744 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse())
6745 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6746 N0.getOperand(0), N0.getOperand(1), N1);
6748 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
6749 // Note: Commutes FADD operands.
6750 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse())
6751 return DAG.getNode(ISD::FMA, SDLoc(N), VT,
6752 N1.getOperand(0), N1.getOperand(1), N0);
6758 SDValue DAGCombiner::visitFSUB(SDNode *N) {
6759 SDValue N0 = N->getOperand(0);
6760 SDValue N1 = N->getOperand(1);
6761 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6762 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6763 EVT VT = N->getValueType(0);
6765 const TargetOptions *Options = &DAG.getTarget().Options;
6768 if (VT.isVector()) {
6769 SDValue FoldedVOp = SimplifyVBinOp(N);
6770 if (FoldedVOp.getNode()) return FoldedVOp;
6773 // fold (fsub c1, c2) -> c1-c2
6775 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, N1);
6776 // fold (fsub A, 0) -> A
6777 if (Options->UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
6779 // fold (fsub 0, B) -> -B
6780 if (Options->UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
6781 if (isNegatibleForFree(N1, LegalOperations, TLI, Options))
6782 return GetNegatedExpression(N1, DAG, LegalOperations);
6783 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6784 return DAG.getNode(ISD::FNEG, dl, VT, N1);
6786 // fold (fsub A, (fneg B)) -> (fadd A, B)
6787 if (isNegatibleForFree(N1, LegalOperations, TLI, Options))
6788 return DAG.getNode(ISD::FADD, dl, VT, N0,
6789 GetNegatedExpression(N1, DAG, LegalOperations));
6791 // If 'unsafe math' is enabled, fold
6792 // (fsub x, x) -> 0.0 &
6793 // (fsub x, (fadd x, y)) -> (fneg y) &
6794 // (fsub x, (fadd y, x)) -> (fneg y)
6795 if (Options->UnsafeFPMath) {
6797 return DAG.getConstantFP(0.0f, VT);
6799 if (N1.getOpcode() == ISD::FADD) {
6800 SDValue N10 = N1->getOperand(0);
6801 SDValue N11 = N1->getOperand(1);
6803 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, Options))
6804 return GetNegatedExpression(N11, DAG, LegalOperations);
6806 if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, Options))
6807 return GetNegatedExpression(N10, DAG, LegalOperations);
6811 // FSUB -> FMA combines:
6812 if ((Options->AllowFPOpFusion == FPOpFusion::Fast || Options->UnsafeFPMath) &&
6813 DAG.getTarget().getSubtargetImpl()
6814 ->getTargetLowering()
6815 ->isFMAFasterThanFMulAndFAdd(VT) &&
6816 (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FMA, VT))) {
6818 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
6819 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse())
6820 return DAG.getNode(ISD::FMA, dl, VT,
6821 N0.getOperand(0), N0.getOperand(1),
6822 DAG.getNode(ISD::FNEG, dl, VT, N1));
6824 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
6825 // Note: Commutes FSUB operands.
6826 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse())
6827 return DAG.getNode(ISD::FMA, dl, VT,
6828 DAG.getNode(ISD::FNEG, dl, VT,
6830 N1.getOperand(1), N0);
6832 // fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
6833 if (N0.getOpcode() == ISD::FNEG &&
6834 N0.getOperand(0).getOpcode() == ISD::FMUL &&
6835 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) {
6836 SDValue N00 = N0.getOperand(0).getOperand(0);
6837 SDValue N01 = N0.getOperand(0).getOperand(1);
6838 return DAG.getNode(ISD::FMA, dl, VT,
6839 DAG.getNode(ISD::FNEG, dl, VT, N00), N01,
6840 DAG.getNode(ISD::FNEG, dl, VT, N1));
6847 SDValue DAGCombiner::visitFMUL(SDNode *N) {
6848 SDValue N0 = N->getOperand(0);
6849 SDValue N1 = N->getOperand(1);
6850 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
6851 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
6852 EVT VT = N->getValueType(0);
6853 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6856 if (VT.isVector()) {
6857 SDValue FoldedVOp = SimplifyVBinOp(N);
6858 if (FoldedVOp.getNode()) return FoldedVOp;
6861 // fold (fmul c1, c2) -> c1*c2
6863 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, N1);
6864 // canonicalize constant to RHS
6865 if (N0CFP && !N1CFP)
6866 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, N0);
6867 // fold (fmul A, 0) -> 0
6868 if (DAG.getTarget().Options.UnsafeFPMath &&
6869 N1CFP && N1CFP->getValueAPF().isZero())
6871 // fold (fmul A, 1.0) -> A
6872 if (N1CFP && N1CFP->isExactlyValue(1.0))
6875 // fold (fmul X, 2.0) -> (fadd X, X)
6876 if (N1CFP && N1CFP->isExactlyValue(+2.0))
6877 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0);
6878 // fold (fmul X, -1.0) -> (fneg X)
6879 if (N1CFP && N1CFP->isExactlyValue(-1.0))
6880 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
6881 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
6883 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
6884 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
6885 &DAG.getTarget().Options)) {
6886 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
6887 &DAG.getTarget().Options)) {
6888 // Both can be negated for free, check to see if at least one is cheaper
6890 if (LHSNeg == 2 || RHSNeg == 2)
6891 return DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6892 GetNegatedExpression(N0, DAG, LegalOperations),
6893 GetNegatedExpression(N1, DAG, LegalOperations));
6897 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
6898 if (DAG.getTarget().Options.UnsafeFPMath &&
6899 N1CFP && N0.getOpcode() == ISD::FMUL &&
6900 N0.getNode()->hasOneUse() && isConstOrConstSplatFP(N0.getOperand(1))) {
6901 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
6902 DAG.getNode(ISD::FMUL, SDLoc(N), VT,
6903 N0.getOperand(1), N1));
6909 SDValue DAGCombiner::visitFMA(SDNode *N) {
6910 SDValue N0 = N->getOperand(0);
6911 SDValue N1 = N->getOperand(1);
6912 SDValue N2 = N->getOperand(2);
6913 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6914 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6915 EVT VT = N->getValueType(0);
6919 // Constant fold FMA.
6920 if (isa<ConstantFPSDNode>(N0) &&
6921 isa<ConstantFPSDNode>(N1) &&
6922 isa<ConstantFPSDNode>(N2)) {
6923 return DAG.getNode(ISD::FMA, dl, VT, N0, N1, N2);
6926 if (DAG.getTarget().Options.UnsafeFPMath) {
6927 if (N0CFP && N0CFP->isZero())
6929 if (N1CFP && N1CFP->isZero())
6932 if (N0CFP && N0CFP->isExactlyValue(1.0))
6933 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2);
6934 if (N1CFP && N1CFP->isExactlyValue(1.0))
6935 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
6937 // Canonicalize (fma c, x, y) -> (fma x, c, y)
6938 if (N0CFP && !N1CFP)
6939 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
6941 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
6942 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6943 N2.getOpcode() == ISD::FMUL &&
6944 N0 == N2.getOperand(0) &&
6945 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
6946 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6947 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
6951 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
6952 if (DAG.getTarget().Options.UnsafeFPMath &&
6953 N0.getOpcode() == ISD::FMUL && N1CFP &&
6954 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
6955 return DAG.getNode(ISD::FMA, dl, VT,
6957 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
6961 // (fma x, 1, y) -> (fadd x, y)
6962 // (fma x, -1, y) -> (fadd (fneg x), y)
6964 if (N1CFP->isExactlyValue(1.0))
6965 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
6967 if (N1CFP->isExactlyValue(-1.0) &&
6968 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
6969 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
6970 AddToWorklist(RHSNeg.getNode());
6971 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
6975 // (fma x, c, x) -> (fmul x, (c+1))
6976 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2)
6977 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6978 DAG.getNode(ISD::FADD, dl, VT,
6979 N1, DAG.getConstantFP(1.0, VT)));
6981 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
6982 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
6983 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0)
6984 return DAG.getNode(ISD::FMUL, dl, VT, N0,
6985 DAG.getNode(ISD::FADD, dl, VT,
6986 N1, DAG.getConstantFP(-1.0, VT)));
6992 SDValue DAGCombiner::visitFDIV(SDNode *N) {
6993 SDValue N0 = N->getOperand(0);
6994 SDValue N1 = N->getOperand(1);
6995 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
6996 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
6997 EVT VT = N->getValueType(0);
6998 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7001 if (VT.isVector()) {
7002 SDValue FoldedVOp = SimplifyVBinOp(N);
7003 if (FoldedVOp.getNode()) return FoldedVOp;
7006 // fold (fdiv c1, c2) -> c1/c2
7008 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1);
7010 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
7011 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) {
7012 // Compute the reciprocal 1.0 / c2.
7013 APFloat N1APF = N1CFP->getValueAPF();
7014 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
7015 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
7016 // Only do the transform if the reciprocal is a legal fp immediate that
7017 // isn't too nasty (eg NaN, denormal, ...).
7018 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
7019 (!LegalOperations ||
7020 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
7021 // backend)... we should handle this gracefully after Legalize.
7022 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
7023 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
7024 TLI.isFPImmLegal(Recip, VT)))
7025 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0,
7026 DAG.getConstantFP(Recip, VT));
7029 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
7030 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI,
7031 &DAG.getTarget().Options)) {
7032 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI,
7033 &DAG.getTarget().Options)) {
7034 // Both can be negated for free, check to see if at least one is cheaper
7036 if (LHSNeg == 2 || RHSNeg == 2)
7037 return DAG.getNode(ISD::FDIV, SDLoc(N), VT,
7038 GetNegatedExpression(N0, DAG, LegalOperations),
7039 GetNegatedExpression(N1, DAG, LegalOperations));
7046 SDValue DAGCombiner::visitFREM(SDNode *N) {
7047 SDValue N0 = N->getOperand(0);
7048 SDValue N1 = N->getOperand(1);
7049 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7050 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7051 EVT VT = N->getValueType(0);
7053 // fold (frem c1, c2) -> fmod(c1,c2)
7055 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1);
7060 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
7061 SDValue N0 = N->getOperand(0);
7062 SDValue N1 = N->getOperand(1);
7063 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7064 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7065 EVT VT = N->getValueType(0);
7067 if (N0CFP && N1CFP) // Constant fold
7068 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
7071 const APFloat& V = N1CFP->getValueAPF();
7072 // copysign(x, c1) -> fabs(x) iff ispos(c1)
7073 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
7074 if (!V.isNegative()) {
7075 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
7076 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7078 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
7079 return DAG.getNode(ISD::FNEG, SDLoc(N), VT,
7080 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
7084 // copysign(fabs(x), y) -> copysign(x, y)
7085 // copysign(fneg(x), y) -> copysign(x, y)
7086 // copysign(copysign(x,z), y) -> copysign(x, y)
7087 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
7088 N0.getOpcode() == ISD::FCOPYSIGN)
7089 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7090 N0.getOperand(0), N1);
7092 // copysign(x, abs(y)) -> abs(x)
7093 if (N1.getOpcode() == ISD::FABS)
7094 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7096 // copysign(x, copysign(y,z)) -> copysign(x, z)
7097 if (N1.getOpcode() == ISD::FCOPYSIGN)
7098 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7099 N0, N1.getOperand(1));
7101 // copysign(x, fp_extend(y)) -> copysign(x, y)
7102 // copysign(x, fp_round(y)) -> copysign(x, y)
7103 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
7104 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7105 N0, N1.getOperand(0));
7110 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
7111 SDValue N0 = N->getOperand(0);
7112 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
7113 EVT VT = N->getValueType(0);
7114 EVT OpVT = N0.getValueType();
7116 // fold (sint_to_fp c1) -> c1fp
7118 // ...but only if the target supports immediate floating-point values
7119 (!LegalOperations ||
7120 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
7121 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
7123 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
7124 // but UINT_TO_FP is legal on this target, try to convert.
7125 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
7126 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
7127 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
7128 if (DAG.SignBitIsZero(N0))
7129 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
7132 // The next optimizations are desirable only if SELECT_CC can be lowered.
7133 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
7134 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
7135 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
7137 (!LegalOperations ||
7138 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7140 { N0.getOperand(0), N0.getOperand(1),
7141 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT),
7143 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7146 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
7147 // (select_cc x, y, 1.0, 0.0,, cc)
7148 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
7149 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
7150 (!LegalOperations ||
7151 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7153 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
7154 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT),
7155 N0.getOperand(0).getOperand(2) };
7156 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7163 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
7164 SDValue N0 = N->getOperand(0);
7165 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
7166 EVT VT = N->getValueType(0);
7167 EVT OpVT = N0.getValueType();
7169 // fold (uint_to_fp c1) -> c1fp
7171 // ...but only if the target supports immediate floating-point values
7172 (!LegalOperations ||
7173 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
7174 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
7176 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
7177 // but SINT_TO_FP is legal on this target, try to convert.
7178 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
7179 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
7180 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
7181 if (DAG.SignBitIsZero(N0))
7182 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
7185 // The next optimizations are desirable only if SELECT_CC can be lowered.
7186 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
7187 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
7189 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
7190 (!LegalOperations ||
7191 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
7193 { N0.getOperand(0), N0.getOperand(1),
7194 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT),
7196 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops);
7203 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
7204 SDValue N0 = N->getOperand(0);
7205 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7206 EVT VT = N->getValueType(0);
7208 // fold (fp_to_sint c1fp) -> c1
7210 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
7215 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
7216 SDValue N0 = N->getOperand(0);
7217 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7218 EVT VT = N->getValueType(0);
7220 // fold (fp_to_uint c1fp) -> c1
7222 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
7227 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
7228 SDValue N0 = N->getOperand(0);
7229 SDValue N1 = N->getOperand(1);
7230 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7231 EVT VT = N->getValueType(0);
7233 // fold (fp_round c1fp) -> c1fp
7235 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
7237 // fold (fp_round (fp_extend x)) -> x
7238 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
7239 return N0.getOperand(0);
7241 // fold (fp_round (fp_round x)) -> (fp_round x)
7242 if (N0.getOpcode() == ISD::FP_ROUND) {
7243 // This is a value preserving truncation if both round's are.
7244 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
7245 N0.getNode()->getConstantOperandVal(1) == 1;
7246 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0.getOperand(0),
7247 DAG.getIntPtrConstant(IsTrunc));
7250 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
7251 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
7252 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
7253 N0.getOperand(0), N1);
7254 AddToWorklist(Tmp.getNode());
7255 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
7256 Tmp, N0.getOperand(1));
7262 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
7263 SDValue N0 = N->getOperand(0);
7264 EVT VT = N->getValueType(0);
7265 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
7266 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7268 // fold (fp_round_inreg c1fp) -> c1fp
7269 if (N0CFP && isTypeLegal(EVT)) {
7270 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
7271 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Round);
7277 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
7278 SDValue N0 = N->getOperand(0);
7279 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7280 EVT VT = N->getValueType(0);
7282 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
7283 if (N->hasOneUse() &&
7284 N->use_begin()->getOpcode() == ISD::FP_ROUND)
7287 // fold (fp_extend c1fp) -> c1fp
7289 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
7291 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
7293 if (N0.getOpcode() == ISD::FP_ROUND
7294 && N0.getNode()->getConstantOperandVal(1) == 1) {
7295 SDValue In = N0.getOperand(0);
7296 if (In.getValueType() == VT) return In;
7297 if (VT.bitsLT(In.getValueType()))
7298 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT,
7299 In, N0.getOperand(1));
7300 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In);
7303 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
7304 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7305 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType())) {
7306 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7307 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
7309 LN0->getBasePtr(), N0.getValueType(),
7310 LN0->getMemOperand());
7311 CombineTo(N, ExtLoad);
7312 CombineTo(N0.getNode(),
7313 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
7314 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
7315 ExtLoad.getValue(1));
7316 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7322 SDValue DAGCombiner::visitFNEG(SDNode *N) {
7323 SDValue N0 = N->getOperand(0);
7324 EVT VT = N->getValueType(0);
7326 // Constant fold FNEG.
7327 if (isa<ConstantFPSDNode>(N0))
7328 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N->getOperand(0));
7330 if (VT.isVector()) {
7331 SDValue FoldedVOp = SimplifyVUnaryOp(N);
7332 if (FoldedVOp.getNode()) return FoldedVOp;
7335 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
7336 &DAG.getTarget().Options))
7337 return GetNegatedExpression(N0, DAG, LegalOperations);
7339 // Transform fneg(bitconvert(x)) -> bitconvert(x ^ sign) to avoid loading
7340 // constant pool values.
7341 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST &&
7342 N0.getNode()->hasOneUse()) {
7343 SDValue Int = N0.getOperand(0);
7344 EVT IntVT = Int.getValueType();
7345 if (IntVT.isInteger() && !IntVT.isVector()) {
7347 if (N0.getValueType().isVector()) {
7348 // For a vector, get a mask such as 0x80... per scalar element
7350 SignMask = APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
7351 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
7353 // For a scalar, just generate 0x80...
7354 SignMask = APInt::getSignBit(IntVT.getSizeInBits());
7356 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int,
7357 DAG.getConstant(SignMask, IntVT));
7358 AddToWorklist(Int.getNode());
7359 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Int);
7363 // (fneg (fmul c, x)) -> (fmul -c, x)
7364 if (N0.getOpcode() == ISD::FMUL) {
7365 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
7367 APFloat CVal = CFP1->getValueAPF();
7369 if (Level >= AfterLegalizeDAG &&
7370 (TLI.isFPImmLegal(CVal, N->getValueType(0)) ||
7371 TLI.isOperationLegal(ISD::ConstantFP, N->getValueType(0))))
7373 ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
7374 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0.getOperand(1)));
7381 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
7382 SDValue N0 = N->getOperand(0);
7383 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7384 EVT VT = N->getValueType(0);
7386 // fold (fceil c1) -> fceil(c1)
7388 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
7393 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
7394 SDValue N0 = N->getOperand(0);
7395 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7396 EVT VT = N->getValueType(0);
7398 // fold (ftrunc c1) -> ftrunc(c1)
7400 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
7405 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
7406 SDValue N0 = N->getOperand(0);
7407 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7408 EVT VT = N->getValueType(0);
7410 // fold (ffloor c1) -> ffloor(c1)
7412 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
7417 SDValue DAGCombiner::visitFABS(SDNode *N) {
7418 SDValue N0 = N->getOperand(0);
7419 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7420 EVT VT = N->getValueType(0);
7422 if (VT.isVector()) {
7423 SDValue FoldedVOp = SimplifyVUnaryOp(N);
7424 if (FoldedVOp.getNode()) return FoldedVOp;
7427 // fold (fabs c1) -> fabs(c1)
7429 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
7430 // fold (fabs (fabs x)) -> (fabs x)
7431 if (N0.getOpcode() == ISD::FABS)
7432 return N->getOperand(0);
7433 // fold (fabs (fneg x)) -> (fabs x)
7434 // fold (fabs (fcopysign x, y)) -> (fabs x)
7435 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
7436 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
7438 // Transform fabs(bitconvert(x)) -> bitconvert(x & ~sign) to avoid loading
7439 // constant pool values.
7440 if (!TLI.isFAbsFree(VT) &&
7441 N0.getOpcode() == ISD::BITCAST &&
7442 N0.getNode()->hasOneUse()) {
7443 SDValue Int = N0.getOperand(0);
7444 EVT IntVT = Int.getValueType();
7445 if (IntVT.isInteger() && !IntVT.isVector()) {
7447 if (N0.getValueType().isVector()) {
7448 // For a vector, get a mask such as 0x7f... per scalar element
7450 SignMask = ~APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
7451 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
7453 // For a scalar, just generate 0x7f...
7454 SignMask = ~APInt::getSignBit(IntVT.getSizeInBits());
7456 Int = DAG.getNode(ISD::AND, SDLoc(N0), IntVT, Int,
7457 DAG.getConstant(SignMask, IntVT));
7458 AddToWorklist(Int.getNode());
7459 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Int);
7466 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
7467 SDValue Chain = N->getOperand(0);
7468 SDValue N1 = N->getOperand(1);
7469 SDValue N2 = N->getOperand(2);
7471 // If N is a constant we could fold this into a fallthrough or unconditional
7472 // branch. However that doesn't happen very often in normal code, because
7473 // Instcombine/SimplifyCFG should have handled the available opportunities.
7474 // If we did this folding here, it would be necessary to update the
7475 // MachineBasicBlock CFG, which is awkward.
7477 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
7479 if (N1.getOpcode() == ISD::SETCC &&
7480 TLI.isOperationLegalOrCustom(ISD::BR_CC,
7481 N1.getOperand(0).getValueType())) {
7482 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
7483 Chain, N1.getOperand(2),
7484 N1.getOperand(0), N1.getOperand(1), N2);
7487 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
7488 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
7489 (N1.getOperand(0).hasOneUse() &&
7490 N1.getOperand(0).getOpcode() == ISD::SRL))) {
7491 SDNode *Trunc = nullptr;
7492 if (N1.getOpcode() == ISD::TRUNCATE) {
7493 // Look pass the truncate.
7494 Trunc = N1.getNode();
7495 N1 = N1.getOperand(0);
7498 // Match this pattern so that we can generate simpler code:
7501 // %b = and i32 %a, 2
7502 // %c = srl i32 %b, 1
7503 // brcond i32 %c ...
7508 // %b = and i32 %a, 2
7509 // %c = setcc eq %b, 0
7512 // This applies only when the AND constant value has one bit set and the
7513 // SRL constant is equal to the log2 of the AND constant. The back-end is
7514 // smart enough to convert the result into a TEST/JMP sequence.
7515 SDValue Op0 = N1.getOperand(0);
7516 SDValue Op1 = N1.getOperand(1);
7518 if (Op0.getOpcode() == ISD::AND &&
7519 Op1.getOpcode() == ISD::Constant) {
7520 SDValue AndOp1 = Op0.getOperand(1);
7522 if (AndOp1.getOpcode() == ISD::Constant) {
7523 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
7525 if (AndConst.isPowerOf2() &&
7526 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
7528 DAG.getSetCC(SDLoc(N),
7529 getSetCCResultType(Op0.getValueType()),
7530 Op0, DAG.getConstant(0, Op0.getValueType()),
7533 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, SDLoc(N),
7534 MVT::Other, Chain, SetCC, N2);
7535 // Don't add the new BRCond into the worklist or else SimplifySelectCC
7536 // will convert it back to (X & C1) >> C2.
7537 CombineTo(N, NewBRCond, false);
7538 // Truncate is dead.
7540 deleteAndRecombine(Trunc);
7541 // Replace the uses of SRL with SETCC
7542 WorklistRemover DeadNodes(*this);
7543 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
7544 deleteAndRecombine(N1.getNode());
7545 return SDValue(N, 0); // Return N so it doesn't get rechecked!
7551 // Restore N1 if the above transformation doesn't match.
7552 N1 = N->getOperand(1);
7555 // Transform br(xor(x, y)) -> br(x != y)
7556 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
7557 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
7558 SDNode *TheXor = N1.getNode();
7559 SDValue Op0 = TheXor->getOperand(0);
7560 SDValue Op1 = TheXor->getOperand(1);
7561 if (Op0.getOpcode() == Op1.getOpcode()) {
7562 // Avoid missing important xor optimizations.
7563 SDValue Tmp = visitXOR(TheXor);
7564 if (Tmp.getNode()) {
7565 if (Tmp.getNode() != TheXor) {
7566 DEBUG(dbgs() << "\nReplacing.8 ";
7568 dbgs() << "\nWith: ";
7569 Tmp.getNode()->dump(&DAG);
7571 WorklistRemover DeadNodes(*this);
7572 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
7573 deleteAndRecombine(TheXor);
7574 return DAG.getNode(ISD::BRCOND, SDLoc(N),
7575 MVT::Other, Chain, Tmp, N2);
7578 // visitXOR has changed XOR's operands or replaced the XOR completely,
7580 return SDValue(N, 0);
7584 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
7586 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
7587 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
7588 Op0.getOpcode() == ISD::XOR) {
7589 TheXor = Op0.getNode();
7593 EVT SetCCVT = N1.getValueType();
7595 SetCCVT = getSetCCResultType(SetCCVT);
7596 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor),
7599 Equal ? ISD::SETEQ : ISD::SETNE);
7600 // Replace the uses of XOR with SETCC
7601 WorklistRemover DeadNodes(*this);
7602 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
7603 deleteAndRecombine(N1.getNode());
7604 return DAG.getNode(ISD::BRCOND, SDLoc(N),
7605 MVT::Other, Chain, SetCC, N2);
7612 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
7614 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
7615 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
7616 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
7618 // If N is a constant we could fold this into a fallthrough or unconditional
7619 // branch. However that doesn't happen very often in normal code, because
7620 // Instcombine/SimplifyCFG should have handled the available opportunities.
7621 // If we did this folding here, it would be necessary to update the
7622 // MachineBasicBlock CFG, which is awkward.
7624 // Use SimplifySetCC to simplify SETCC's.
7625 SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()),
7626 CondLHS, CondRHS, CC->get(), SDLoc(N),
7628 if (Simp.getNode()) AddToWorklist(Simp.getNode());
7630 // fold to a simpler setcc
7631 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
7632 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
7633 N->getOperand(0), Simp.getOperand(2),
7634 Simp.getOperand(0), Simp.getOperand(1),
7640 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
7641 /// uses N as its base pointer and that N may be folded in the load / store
7642 /// addressing mode.
7643 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
7645 const TargetLowering &TLI) {
7647 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
7648 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
7650 VT = Use->getValueType(0);
7651 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
7652 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
7654 VT = ST->getValue().getValueType();
7658 TargetLowering::AddrMode AM;
7659 if (N->getOpcode() == ISD::ADD) {
7660 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
7663 AM.BaseOffs = Offset->getSExtValue();
7667 } else if (N->getOpcode() == ISD::SUB) {
7668 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
7671 AM.BaseOffs = -Offset->getSExtValue();
7678 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
7681 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
7682 /// pre-indexed load / store when the base pointer is an add or subtract
7683 /// and it has other uses besides the load / store. After the
7684 /// transformation, the new indexed load / store has effectively folded
7685 /// the add / subtract in and all of its other uses are redirected to the
7686 /// new load / store.
7687 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
7688 if (Level < AfterLegalizeDAG)
7694 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7695 if (LD->isIndexed())
7697 VT = LD->getMemoryVT();
7698 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
7699 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
7701 Ptr = LD->getBasePtr();
7702 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7703 if (ST->isIndexed())
7705 VT = ST->getMemoryVT();
7706 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
7707 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
7709 Ptr = ST->getBasePtr();
7715 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
7716 // out. There is no reason to make this a preinc/predec.
7717 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
7718 Ptr.getNode()->hasOneUse())
7721 // Ask the target to do addressing mode selection.
7724 ISD::MemIndexedMode AM = ISD::UNINDEXED;
7725 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
7728 // Backends without true r+i pre-indexed forms may need to pass a
7729 // constant base with a variable offset so that constant coercion
7730 // will work with the patterns in canonical form.
7731 bool Swapped = false;
7732 if (isa<ConstantSDNode>(BasePtr)) {
7733 std::swap(BasePtr, Offset);
7737 // Don't create a indexed load / store with zero offset.
7738 if (isa<ConstantSDNode>(Offset) &&
7739 cast<ConstantSDNode>(Offset)->isNullValue())
7742 // Try turning it into a pre-indexed load / store except when:
7743 // 1) The new base ptr is a frame index.
7744 // 2) If N is a store and the new base ptr is either the same as or is a
7745 // predecessor of the value being stored.
7746 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
7747 // that would create a cycle.
7748 // 4) All uses are load / store ops that use it as old base ptr.
7750 // Check #1. Preinc'ing a frame index would require copying the stack pointer
7751 // (plus the implicit offset) to a register to preinc anyway.
7752 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
7757 SDValue Val = cast<StoreSDNode>(N)->getValue();
7758 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
7762 // If the offset is a constant, there may be other adds of constants that
7763 // can be folded with this one. We should do this to avoid having to keep
7764 // a copy of the original base pointer.
7765 SmallVector<SDNode *, 16> OtherUses;
7766 if (isa<ConstantSDNode>(Offset))
7767 for (SDNode *Use : BasePtr.getNode()->uses()) {
7768 if (Use == Ptr.getNode())
7771 if (Use->isPredecessorOf(N))
7774 if (Use->getOpcode() != ISD::ADD && Use->getOpcode() != ISD::SUB) {
7779 SDValue Op0 = Use->getOperand(0), Op1 = Use->getOperand(1);
7780 if (Op1.getNode() == BasePtr.getNode())
7781 std::swap(Op0, Op1);
7782 assert(Op0.getNode() == BasePtr.getNode() &&
7783 "Use of ADD/SUB but not an operand");
7785 if (!isa<ConstantSDNode>(Op1)) {
7790 // FIXME: In some cases, we can be smarter about this.
7791 if (Op1.getValueType() != Offset.getValueType()) {
7796 OtherUses.push_back(Use);
7800 std::swap(BasePtr, Offset);
7802 // Now check for #3 and #4.
7803 bool RealUse = false;
7805 // Caches for hasPredecessorHelper
7806 SmallPtrSet<const SDNode *, 32> Visited;
7807 SmallVector<const SDNode *, 16> Worklist;
7809 for (SDNode *Use : Ptr.getNode()->uses()) {
7812 if (N->hasPredecessorHelper(Use, Visited, Worklist))
7815 // If Ptr may be folded in addressing mode of other use, then it's
7816 // not profitable to do this transformation.
7817 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
7826 Result = DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
7827 BasePtr, Offset, AM);
7829 Result = DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
7830 BasePtr, Offset, AM);
7833 DEBUG(dbgs() << "\nReplacing.4 ";
7835 dbgs() << "\nWith: ";
7836 Result.getNode()->dump(&DAG);
7838 WorklistRemover DeadNodes(*this);
7840 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
7841 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
7843 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
7846 // Finally, since the node is now dead, remove it from the graph.
7847 deleteAndRecombine(N);
7850 std::swap(BasePtr, Offset);
7852 // Replace other uses of BasePtr that can be updated to use Ptr
7853 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) {
7854 unsigned OffsetIdx = 1;
7855 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode())
7857 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() ==
7858 BasePtr.getNode() && "Expected BasePtr operand");
7860 // We need to replace ptr0 in the following expression:
7861 // x0 * offset0 + y0 * ptr0 = t0
7863 // x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store)
7865 // where x0, x1, y0 and y1 in {-1, 1} are given by the types of the
7866 // indexed load/store and the expresion that needs to be re-written.
7868 // Therefore, we have:
7869 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
7871 ConstantSDNode *CN =
7872 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
7874 APInt Offset0 = CN->getAPIntValue();
7875 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
7877 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
7878 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
7879 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1;
7880 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1;
7882 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD;
7884 APInt CNV = Offset0;
7885 if (X0 < 0) CNV = -CNV;
7886 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1;
7887 else CNV = CNV - Offset1;
7889 // We can now generate the new expression.
7890 SDValue NewOp1 = DAG.getConstant(CNV, CN->getValueType(0));
7891 SDValue NewOp2 = Result.getValue(isLoad ? 1 : 0);
7893 SDValue NewUse = DAG.getNode(Opcode,
7894 SDLoc(OtherUses[i]),
7895 OtherUses[i]->getValueType(0), NewOp1, NewOp2);
7896 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse);
7897 deleteAndRecombine(OtherUses[i]);
7900 // Replace the uses of Ptr with uses of the updated base value.
7901 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
7902 deleteAndRecombine(Ptr.getNode());
7907 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
7908 /// add / sub of the base pointer node into a post-indexed load / store.
7909 /// The transformation folded the add / subtract into the new indexed
7910 /// load / store effectively and all of its uses are redirected to the
7911 /// new load / store.
7912 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
7913 if (Level < AfterLegalizeDAG)
7919 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7920 if (LD->isIndexed())
7922 VT = LD->getMemoryVT();
7923 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
7924 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
7926 Ptr = LD->getBasePtr();
7927 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7928 if (ST->isIndexed())
7930 VT = ST->getMemoryVT();
7931 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
7932 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
7934 Ptr = ST->getBasePtr();
7940 if (Ptr.getNode()->hasOneUse())
7943 for (SDNode *Op : Ptr.getNode()->uses()) {
7945 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
7950 ISD::MemIndexedMode AM = ISD::UNINDEXED;
7951 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
7952 // Don't create a indexed load / store with zero offset.
7953 if (isa<ConstantSDNode>(Offset) &&
7954 cast<ConstantSDNode>(Offset)->isNullValue())
7957 // Try turning it into a post-indexed load / store except when
7958 // 1) All uses are load / store ops that use it as base ptr (and
7959 // it may be folded as addressing mmode).
7960 // 2) Op must be independent of N, i.e. Op is neither a predecessor
7961 // nor a successor of N. Otherwise, if Op is folded that would
7964 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
7968 bool TryNext = false;
7969 for (SDNode *Use : BasePtr.getNode()->uses()) {
7970 if (Use == Ptr.getNode())
7973 // If all the uses are load / store addresses, then don't do the
7975 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
7976 bool RealUse = false;
7977 for (SDNode *UseUse : Use->uses()) {
7978 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
7993 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
7994 SDValue Result = isLoad
7995 ? DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
7996 BasePtr, Offset, AM)
7997 : DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
7998 BasePtr, Offset, AM);
8001 DEBUG(dbgs() << "\nReplacing.5 ";
8003 dbgs() << "\nWith: ";
8004 Result.getNode()->dump(&DAG);
8006 WorklistRemover DeadNodes(*this);
8008 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
8009 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
8011 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
8014 // Finally, since the node is now dead, remove it from the graph.
8015 deleteAndRecombine(N);
8017 // Replace the uses of Use with uses of the updated base value.
8018 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
8019 Result.getValue(isLoad ? 1 : 0));
8020 deleteAndRecombine(Op);
8029 SDValue DAGCombiner::visitLOAD(SDNode *N) {
8030 LoadSDNode *LD = cast<LoadSDNode>(N);
8031 SDValue Chain = LD->getChain();
8032 SDValue Ptr = LD->getBasePtr();
8034 // If load is not volatile and there are no uses of the loaded value (and
8035 // the updated indexed value in case of indexed loads), change uses of the
8036 // chain value into uses of the chain input (i.e. delete the dead load).
8037 if (!LD->isVolatile()) {
8038 if (N->getValueType(1) == MVT::Other) {
8040 if (!N->hasAnyUseOfValue(0)) {
8041 // It's not safe to use the two value CombineTo variant here. e.g.
8042 // v1, chain2 = load chain1, loc
8043 // v2, chain3 = load chain2, loc
8045 // Now we replace use of chain2 with chain1. This makes the second load
8046 // isomorphic to the one we are deleting, and thus makes this load live.
8047 DEBUG(dbgs() << "\nReplacing.6 ";
8049 dbgs() << "\nWith chain: ";
8050 Chain.getNode()->dump(&DAG);
8052 WorklistRemover DeadNodes(*this);
8053 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
8056 deleteAndRecombine(N);
8058 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8062 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
8063 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
8064 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
8065 DEBUG(dbgs() << "\nReplacing.7 ";
8067 dbgs() << "\nWith: ";
8068 Undef.getNode()->dump(&DAG);
8069 dbgs() << " and 2 other values\n");
8070 WorklistRemover DeadNodes(*this);
8071 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
8072 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
8073 DAG.getUNDEF(N->getValueType(1)));
8074 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
8075 deleteAndRecombine(N);
8076 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8081 // If this load is directly stored, replace the load value with the stored
8083 // TODO: Handle store large -> read small portion.
8084 // TODO: Handle TRUNCSTORE/LOADEXT
8085 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
8086 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
8087 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
8088 if (PrevST->getBasePtr() == Ptr &&
8089 PrevST->getValue().getValueType() == N->getValueType(0))
8090 return CombineTo(N, Chain.getOperand(1), Chain);
8094 // Try to infer better alignment information than the load already has.
8095 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
8096 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
8097 if (Align > LD->getMemOperand()->getBaseAlignment()) {
8099 DAG.getExtLoad(LD->getExtensionType(), SDLoc(N),
8100 LD->getValueType(0),
8101 Chain, Ptr, LD->getPointerInfo(),
8103 LD->isVolatile(), LD->isNonTemporal(),
8104 LD->isInvariant(), Align, LD->getAAInfo());
8105 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
8110 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA :
8111 TLI.getTargetMachine().getSubtarget<TargetSubtargetInfo>().useAA();
8113 if (CombinerAAOnlyFunc.getNumOccurrences() &&
8114 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
8117 if (UseAA && LD->isUnindexed()) {
8118 // Walk up chain skipping non-aliasing memory nodes.
8119 SDValue BetterChain = FindBetterChain(N, Chain);
8121 // If there is a better chain.
8122 if (Chain != BetterChain) {
8125 // Replace the chain to void dependency.
8126 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
8127 ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD),
8128 BetterChain, Ptr, LD->getMemOperand());
8130 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD),
8131 LD->getValueType(0),
8132 BetterChain, Ptr, LD->getMemoryVT(),
8133 LD->getMemOperand());
8136 // Create token factor to keep old chain connected.
8137 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
8138 MVT::Other, Chain, ReplLoad.getValue(1));
8140 // Make sure the new and old chains are cleaned up.
8141 AddToWorklist(Token.getNode());
8143 // Replace uses with load result and token factor. Don't add users
8145 return CombineTo(N, ReplLoad.getValue(0), Token, false);
8149 // Try transforming N to an indexed load.
8150 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
8151 return SDValue(N, 0);
8153 // Try to slice up N to more direct loads if the slices are mapped to
8154 // different register banks or pairing can take place.
8156 return SDValue(N, 0);
8162 /// \brief Helper structure used to slice a load in smaller loads.
8163 /// Basically a slice is obtained from the following sequence:
8164 /// Origin = load Ty1, Base
8165 /// Shift = srl Ty1 Origin, CstTy Amount
8166 /// Inst = trunc Shift to Ty2
8168 /// Then, it will be rewriten into:
8169 /// Slice = load SliceTy, Base + SliceOffset
8170 /// [Inst = zext Slice to Ty2], only if SliceTy <> Ty2
8172 /// SliceTy is deduced from the number of bits that are actually used to
8174 struct LoadedSlice {
8175 /// \brief Helper structure used to compute the cost of a slice.
8177 /// Are we optimizing for code size.
8182 unsigned CrossRegisterBanksCopies;
8186 Cost(bool ForCodeSize = false)
8187 : ForCodeSize(ForCodeSize), Loads(0), Truncates(0),
8188 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {}
8190 /// \brief Get the cost of one isolated slice.
8191 Cost(const LoadedSlice &LS, bool ForCodeSize = false)
8192 : ForCodeSize(ForCodeSize), Loads(1), Truncates(0),
8193 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {
8194 EVT TruncType = LS.Inst->getValueType(0);
8195 EVT LoadedType = LS.getLoadedType();
8196 if (TruncType != LoadedType &&
8197 !LS.DAG->getTargetLoweringInfo().isZExtFree(LoadedType, TruncType))
8201 /// \brief Account for slicing gain in the current cost.
8202 /// Slicing provide a few gains like removing a shift or a
8203 /// truncate. This method allows to grow the cost of the original
8204 /// load with the gain from this slice.
8205 void addSliceGain(const LoadedSlice &LS) {
8206 // Each slice saves a truncate.
8207 const TargetLowering &TLI = LS.DAG->getTargetLoweringInfo();
8208 if (!TLI.isTruncateFree(LS.Inst->getValueType(0),
8209 LS.Inst->getOperand(0).getValueType()))
8211 // If there is a shift amount, this slice gets rid of it.
8214 // If this slice can merge a cross register bank copy, account for it.
8215 if (LS.canMergeExpensiveCrossRegisterBankCopy())
8216 ++CrossRegisterBanksCopies;
8219 Cost &operator+=(const Cost &RHS) {
8221 Truncates += RHS.Truncates;
8222 CrossRegisterBanksCopies += RHS.CrossRegisterBanksCopies;
8228 bool operator==(const Cost &RHS) const {
8229 return Loads == RHS.Loads && Truncates == RHS.Truncates &&
8230 CrossRegisterBanksCopies == RHS.CrossRegisterBanksCopies &&
8231 ZExts == RHS.ZExts && Shift == RHS.Shift;
8234 bool operator!=(const Cost &RHS) const { return !(*this == RHS); }
8236 bool operator<(const Cost &RHS) const {
8237 // Assume cross register banks copies are as expensive as loads.
8238 // FIXME: Do we want some more target hooks?
8239 unsigned ExpensiveOpsLHS = Loads + CrossRegisterBanksCopies;
8240 unsigned ExpensiveOpsRHS = RHS.Loads + RHS.CrossRegisterBanksCopies;
8241 // Unless we are optimizing for code size, consider the
8242 // expensive operation first.
8243 if (!ForCodeSize && ExpensiveOpsLHS != ExpensiveOpsRHS)
8244 return ExpensiveOpsLHS < ExpensiveOpsRHS;
8245 return (Truncates + ZExts + Shift + ExpensiveOpsLHS) <
8246 (RHS.Truncates + RHS.ZExts + RHS.Shift + ExpensiveOpsRHS);
8249 bool operator>(const Cost &RHS) const { return RHS < *this; }
8251 bool operator<=(const Cost &RHS) const { return !(RHS < *this); }
8253 bool operator>=(const Cost &RHS) const { return !(*this < RHS); }
8255 // The last instruction that represent the slice. This should be a
8256 // truncate instruction.
8258 // The original load instruction.
8260 // The right shift amount in bits from the original load.
8262 // The DAG from which Origin came from.
8263 // This is used to get some contextual information about legal types, etc.
8266 LoadedSlice(SDNode *Inst = nullptr, LoadSDNode *Origin = nullptr,
8267 unsigned Shift = 0, SelectionDAG *DAG = nullptr)
8268 : Inst(Inst), Origin(Origin), Shift(Shift), DAG(DAG) {}
8270 LoadedSlice(const LoadedSlice &LS)
8271 : Inst(LS.Inst), Origin(LS.Origin), Shift(LS.Shift), DAG(LS.DAG) {}
8273 /// \brief Get the bits used in a chunk of bits \p BitWidth large.
8274 /// \return Result is \p BitWidth and has used bits set to 1 and
8275 /// not used bits set to 0.
8276 APInt getUsedBits() const {
8277 // Reproduce the trunc(lshr) sequence:
8278 // - Start from the truncated value.
8279 // - Zero extend to the desired bit width.
8281 assert(Origin && "No original load to compare against.");
8282 unsigned BitWidth = Origin->getValueSizeInBits(0);
8283 assert(Inst && "This slice is not bound to an instruction");
8284 assert(Inst->getValueSizeInBits(0) <= BitWidth &&
8285 "Extracted slice is bigger than the whole type!");
8286 APInt UsedBits(Inst->getValueSizeInBits(0), 0);
8287 UsedBits.setAllBits();
8288 UsedBits = UsedBits.zext(BitWidth);
8293 /// \brief Get the size of the slice to be loaded in bytes.
8294 unsigned getLoadedSize() const {
8295 unsigned SliceSize = getUsedBits().countPopulation();
8296 assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte.");
8297 return SliceSize / 8;
8300 /// \brief Get the type that will be loaded for this slice.
8301 /// Note: This may not be the final type for the slice.
8302 EVT getLoadedType() const {
8303 assert(DAG && "Missing context");
8304 LLVMContext &Ctxt = *DAG->getContext();
8305 return EVT::getIntegerVT(Ctxt, getLoadedSize() * 8);
8308 /// \brief Get the alignment of the load used for this slice.
8309 unsigned getAlignment() const {
8310 unsigned Alignment = Origin->getAlignment();
8311 unsigned Offset = getOffsetFromBase();
8313 Alignment = MinAlign(Alignment, Alignment + Offset);
8317 /// \brief Check if this slice can be rewritten with legal operations.
8318 bool isLegal() const {
8319 // An invalid slice is not legal.
8320 if (!Origin || !Inst || !DAG)
8323 // Offsets are for indexed load only, we do not handle that.
8324 if (Origin->getOffset().getOpcode() != ISD::UNDEF)
8327 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
8329 // Check that the type is legal.
8330 EVT SliceType = getLoadedType();
8331 if (!TLI.isTypeLegal(SliceType))
8334 // Check that the load is legal for this type.
8335 if (!TLI.isOperationLegal(ISD::LOAD, SliceType))
8338 // Check that the offset can be computed.
8339 // 1. Check its type.
8340 EVT PtrType = Origin->getBasePtr().getValueType();
8341 if (PtrType == MVT::Untyped || PtrType.isExtended())
8344 // 2. Check that it fits in the immediate.
8345 if (!TLI.isLegalAddImmediate(getOffsetFromBase()))
8348 // 3. Check that the computation is legal.
8349 if (!TLI.isOperationLegal(ISD::ADD, PtrType))
8352 // Check that the zext is legal if it needs one.
8353 EVT TruncateType = Inst->getValueType(0);
8354 if (TruncateType != SliceType &&
8355 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType))
8361 /// \brief Get the offset in bytes of this slice in the original chunk of
8363 /// \pre DAG != nullptr.
8364 uint64_t getOffsetFromBase() const {
8365 assert(DAG && "Missing context.");
8367 DAG->getTargetLoweringInfo().getDataLayout()->isBigEndian();
8368 assert(!(Shift & 0x7) && "Shifts not aligned on Bytes are not supported.");
8369 uint64_t Offset = Shift / 8;
8370 unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / 8;
8371 assert(!(Origin->getValueSizeInBits(0) & 0x7) &&
8372 "The size of the original loaded type is not a multiple of a"
8374 // If Offset is bigger than TySizeInBytes, it means we are loading all
8375 // zeros. This should have been optimized before in the process.
8376 assert(TySizeInBytes > Offset &&
8377 "Invalid shift amount for given loaded size");
8379 Offset = TySizeInBytes - Offset - getLoadedSize();
8383 /// \brief Generate the sequence of instructions to load the slice
8384 /// represented by this object and redirect the uses of this slice to
8385 /// this new sequence of instructions.
8386 /// \pre this->Inst && this->Origin are valid Instructions and this
8387 /// object passed the legal check: LoadedSlice::isLegal returned true.
8388 /// \return The last instruction of the sequence used to load the slice.
8389 SDValue loadSlice() const {
8390 assert(Inst && Origin && "Unable to replace a non-existing slice.");
8391 const SDValue &OldBaseAddr = Origin->getBasePtr();
8392 SDValue BaseAddr = OldBaseAddr;
8393 // Get the offset in that chunk of bytes w.r.t. the endianess.
8394 int64_t Offset = static_cast<int64_t>(getOffsetFromBase());
8395 assert(Offset >= 0 && "Offset too big to fit in int64_t!");
8397 // BaseAddr = BaseAddr + Offset.
8398 EVT ArithType = BaseAddr.getValueType();
8399 BaseAddr = DAG->getNode(ISD::ADD, SDLoc(Origin), ArithType, BaseAddr,
8400 DAG->getConstant(Offset, ArithType));
8403 // Create the type of the loaded slice according to its size.
8404 EVT SliceType = getLoadedType();
8406 // Create the load for the slice.
8407 SDValue LastInst = DAG->getLoad(
8408 SliceType, SDLoc(Origin), Origin->getChain(), BaseAddr,
8409 Origin->getPointerInfo().getWithOffset(Offset), Origin->isVolatile(),
8410 Origin->isNonTemporal(), Origin->isInvariant(), getAlignment());
8411 // If the final type is not the same as the loaded type, this means that
8412 // we have to pad with zero. Create a zero extend for that.
8413 EVT FinalType = Inst->getValueType(0);
8414 if (SliceType != FinalType)
8416 DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst);
8420 /// \brief Check if this slice can be merged with an expensive cross register
8421 /// bank copy. E.g.,
8423 /// f = bitcast i32 i to float
8424 bool canMergeExpensiveCrossRegisterBankCopy() const {
8425 if (!Inst || !Inst->hasOneUse())
8427 SDNode *Use = *Inst->use_begin();
8428 if (Use->getOpcode() != ISD::BITCAST)
8430 assert(DAG && "Missing context");
8431 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
8432 EVT ResVT = Use->getValueType(0);
8433 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT());
8434 const TargetRegisterClass *ArgRC =
8435 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT());
8436 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
8439 // At this point, we know that we perform a cross-register-bank copy.
8440 // Check if it is expensive.
8441 const TargetRegisterInfo *TRI =
8442 TLI.getTargetMachine().getSubtargetImpl()->getRegisterInfo();
8443 // Assume bitcasts are cheap, unless both register classes do not
8444 // explicitly share a common sub class.
8445 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC))
8448 // Check if it will be merged with the load.
8449 // 1. Check the alignment constraint.
8450 unsigned RequiredAlignment = TLI.getDataLayout()->getABITypeAlignment(
8451 ResVT.getTypeForEVT(*DAG->getContext()));
8453 if (RequiredAlignment > getAlignment())
8456 // 2. Check that the load is a legal operation for that type.
8457 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
8460 // 3. Check that we do not have a zext in the way.
8461 if (Inst->getValueType(0) != getLoadedType())
8469 /// \brief Check that all bits set in \p UsedBits form a dense region, i.e.,
8470 /// \p UsedBits looks like 0..0 1..1 0..0.
8471 static bool areUsedBitsDense(const APInt &UsedBits) {
8472 // If all the bits are one, this is dense!
8473 if (UsedBits.isAllOnesValue())
8476 // Get rid of the unused bits on the right.
8477 APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countTrailingZeros());
8478 // Get rid of the unused bits on the left.
8479 if (NarrowedUsedBits.countLeadingZeros())
8480 NarrowedUsedBits = NarrowedUsedBits.trunc(NarrowedUsedBits.getActiveBits());
8481 // Check that the chunk of bits is completely used.
8482 return NarrowedUsedBits.isAllOnesValue();
8485 /// \brief Check whether or not \p First and \p Second are next to each other
8486 /// in memory. This means that there is no hole between the bits loaded
8487 /// by \p First and the bits loaded by \p Second.
8488 static bool areSlicesNextToEachOther(const LoadedSlice &First,
8489 const LoadedSlice &Second) {
8490 assert(First.Origin == Second.Origin && First.Origin &&
8491 "Unable to match different memory origins.");
8492 APInt UsedBits = First.getUsedBits();
8493 assert((UsedBits & Second.getUsedBits()) == 0 &&
8494 "Slices are not supposed to overlap.");
8495 UsedBits |= Second.getUsedBits();
8496 return areUsedBitsDense(UsedBits);
8499 /// \brief Adjust the \p GlobalLSCost according to the target
8500 /// paring capabilities and the layout of the slices.
8501 /// \pre \p GlobalLSCost should account for at least as many loads as
8502 /// there is in the slices in \p LoadedSlices.
8503 static void adjustCostForPairing(SmallVectorImpl<LoadedSlice> &LoadedSlices,
8504 LoadedSlice::Cost &GlobalLSCost) {
8505 unsigned NumberOfSlices = LoadedSlices.size();
8506 // If there is less than 2 elements, no pairing is possible.
8507 if (NumberOfSlices < 2)
8510 // Sort the slices so that elements that are likely to be next to each
8511 // other in memory are next to each other in the list.
8512 std::sort(LoadedSlices.begin(), LoadedSlices.end(),
8513 [](const LoadedSlice &LHS, const LoadedSlice &RHS) {
8514 assert(LHS.Origin == RHS.Origin && "Different bases not implemented.");
8515 return LHS.getOffsetFromBase() < RHS.getOffsetFromBase();
8517 const TargetLowering &TLI = LoadedSlices[0].DAG->getTargetLoweringInfo();
8518 // First (resp. Second) is the first (resp. Second) potentially candidate
8519 // to be placed in a paired load.
8520 const LoadedSlice *First = nullptr;
8521 const LoadedSlice *Second = nullptr;
8522 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice,
8523 // Set the beginning of the pair.
8526 Second = &LoadedSlices[CurrSlice];
8528 // If First is NULL, it means we start a new pair.
8529 // Get to the next slice.
8533 EVT LoadedType = First->getLoadedType();
8535 // If the types of the slices are different, we cannot pair them.
8536 if (LoadedType != Second->getLoadedType())
8539 // Check if the target supplies paired loads for this type.
8540 unsigned RequiredAlignment = 0;
8541 if (!TLI.hasPairedLoad(LoadedType, RequiredAlignment)) {
8542 // move to the next pair, this type is hopeless.
8546 // Check if we meet the alignment requirement.
8547 if (RequiredAlignment > First->getAlignment())
8550 // Check that both loads are next to each other in memory.
8551 if (!areSlicesNextToEachOther(*First, *Second))
8554 assert(GlobalLSCost.Loads > 0 && "We save more loads than we created!");
8555 --GlobalLSCost.Loads;
8556 // Move to the next pair.
8561 /// \brief Check the profitability of all involved LoadedSlice.
8562 /// Currently, it is considered profitable if there is exactly two
8563 /// involved slices (1) which are (2) next to each other in memory, and
8564 /// whose cost (\see LoadedSlice::Cost) is smaller than the original load (3).
8566 /// Note: The order of the elements in \p LoadedSlices may be modified, but not
8567 /// the elements themselves.
8569 /// FIXME: When the cost model will be mature enough, we can relax
8570 /// constraints (1) and (2).
8571 static bool isSlicingProfitable(SmallVectorImpl<LoadedSlice> &LoadedSlices,
8572 const APInt &UsedBits, bool ForCodeSize) {
8573 unsigned NumberOfSlices = LoadedSlices.size();
8574 if (StressLoadSlicing)
8575 return NumberOfSlices > 1;
8578 if (NumberOfSlices != 2)
8582 if (!areUsedBitsDense(UsedBits))
8586 LoadedSlice::Cost OrigCost(ForCodeSize), GlobalSlicingCost(ForCodeSize);
8587 // The original code has one big load.
8589 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice) {
8590 const LoadedSlice &LS = LoadedSlices[CurrSlice];
8591 // Accumulate the cost of all the slices.
8592 LoadedSlice::Cost SliceCost(LS, ForCodeSize);
8593 GlobalSlicingCost += SliceCost;
8595 // Account as cost in the original configuration the gain obtained
8596 // with the current slices.
8597 OrigCost.addSliceGain(LS);
8600 // If the target supports paired load, adjust the cost accordingly.
8601 adjustCostForPairing(LoadedSlices, GlobalSlicingCost);
8602 return OrigCost > GlobalSlicingCost;
8605 /// \brief If the given load, \p LI, is used only by trunc or trunc(lshr)
8606 /// operations, split it in the various pieces being extracted.
8608 /// This sort of thing is introduced by SROA.
8609 /// This slicing takes care not to insert overlapping loads.
8610 /// \pre LI is a simple load (i.e., not an atomic or volatile load).
8611 bool DAGCombiner::SliceUpLoad(SDNode *N) {
8612 if (Level < AfterLegalizeDAG)
8615 LoadSDNode *LD = cast<LoadSDNode>(N);
8616 if (LD->isVolatile() || !ISD::isNormalLoad(LD) ||
8617 !LD->getValueType(0).isInteger())
8620 // Keep track of already used bits to detect overlapping values.
8621 // In that case, we will just abort the transformation.
8622 APInt UsedBits(LD->getValueSizeInBits(0), 0);
8624 SmallVector<LoadedSlice, 4> LoadedSlices;
8626 // Check if this load is used as several smaller chunks of bits.
8627 // Basically, look for uses in trunc or trunc(lshr) and record a new chain
8628 // of computation for each trunc.
8629 for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end();
8630 UI != UIEnd; ++UI) {
8631 // Skip the uses of the chain.
8632 if (UI.getUse().getResNo() != 0)
8638 // Check if this is a trunc(lshr).
8639 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
8640 isa<ConstantSDNode>(User->getOperand(1))) {
8641 Shift = cast<ConstantSDNode>(User->getOperand(1))->getZExtValue();
8642 User = *User->use_begin();
8645 // At this point, User is a Truncate, iff we encountered, trunc or
8647 if (User->getOpcode() != ISD::TRUNCATE)
8650 // The width of the type must be a power of 2 and greater than 8-bits.
8651 // Otherwise the load cannot be represented in LLVM IR.
8652 // Moreover, if we shifted with a non-8-bits multiple, the slice
8653 // will be across several bytes. We do not support that.
8654 unsigned Width = User->getValueSizeInBits(0);
8655 if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7))
8658 // Build the slice for this chain of computations.
8659 LoadedSlice LS(User, LD, Shift, &DAG);
8660 APInt CurrentUsedBits = LS.getUsedBits();
8662 // Check if this slice overlaps with another.
8663 if ((CurrentUsedBits & UsedBits) != 0)
8665 // Update the bits used globally.
8666 UsedBits |= CurrentUsedBits;
8668 // Check if the new slice would be legal.
8672 // Record the slice.
8673 LoadedSlices.push_back(LS);
8676 // Abort slicing if it does not seem to be profitable.
8677 if (!isSlicingProfitable(LoadedSlices, UsedBits, ForCodeSize))
8682 // Rewrite each chain to use an independent load.
8683 // By construction, each chain can be represented by a unique load.
8685 // Prepare the argument for the new token factor for all the slices.
8686 SmallVector<SDValue, 8> ArgChains;
8687 for (SmallVectorImpl<LoadedSlice>::const_iterator
8688 LSIt = LoadedSlices.begin(),
8689 LSItEnd = LoadedSlices.end();
8690 LSIt != LSItEnd; ++LSIt) {
8691 SDValue SliceInst = LSIt->loadSlice();
8692 CombineTo(LSIt->Inst, SliceInst, true);
8693 if (SliceInst.getNode()->getOpcode() != ISD::LOAD)
8694 SliceInst = SliceInst.getOperand(0);
8695 assert(SliceInst->getOpcode() == ISD::LOAD &&
8696 "It takes more than a zext to get to the loaded slice!!");
8697 ArgChains.push_back(SliceInst.getValue(1));
8700 SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,
8702 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
8706 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
8707 /// load is having specific bytes cleared out. If so, return the byte size
8708 /// being masked out and the shift amount.
8709 static std::pair<unsigned, unsigned>
8710 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
8711 std::pair<unsigned, unsigned> Result(0, 0);
8713 // Check for the structure we're looking for.
8714 if (V->getOpcode() != ISD::AND ||
8715 !isa<ConstantSDNode>(V->getOperand(1)) ||
8716 !ISD::isNormalLoad(V->getOperand(0).getNode()))
8719 // Check the chain and pointer.
8720 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
8721 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
8723 // The store should be chained directly to the load or be an operand of a
8725 if (LD == Chain.getNode())
8727 else if (Chain->getOpcode() != ISD::TokenFactor)
8728 return Result; // Fail.
8731 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
8732 if (Chain->getOperand(i).getNode() == LD) {
8736 if (!isOk) return Result;
8739 // This only handles simple types.
8740 if (V.getValueType() != MVT::i16 &&
8741 V.getValueType() != MVT::i32 &&
8742 V.getValueType() != MVT::i64)
8745 // Check the constant mask. Invert it so that the bits being masked out are
8746 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
8747 // follow the sign bit for uniformity.
8748 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
8749 unsigned NotMaskLZ = countLeadingZeros(NotMask);
8750 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
8751 unsigned NotMaskTZ = countTrailingZeros(NotMask);
8752 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
8753 if (NotMaskLZ == 64) return Result; // All zero mask.
8755 // See if we have a continuous run of bits. If so, we have 0*1+0*
8756 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
8759 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
8760 if (V.getValueType() != MVT::i64 && NotMaskLZ)
8761 NotMaskLZ -= 64-V.getValueSizeInBits();
8763 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
8764 switch (MaskedBytes) {
8768 default: return Result; // All one mask, or 5-byte mask.
8771 // Verify that the first bit starts at a multiple of mask so that the access
8772 // is aligned the same as the access width.
8773 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
8775 Result.first = MaskedBytes;
8776 Result.second = NotMaskTZ/8;
8781 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
8782 /// provides a value as specified by MaskInfo. If so, replace the specified
8783 /// store with a narrower store of truncated IVal.
8785 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
8786 SDValue IVal, StoreSDNode *St,
8788 unsigned NumBytes = MaskInfo.first;
8789 unsigned ByteShift = MaskInfo.second;
8790 SelectionDAG &DAG = DC->getDAG();
8792 // Check to see if IVal is all zeros in the part being masked in by the 'or'
8793 // that uses this. If not, this is not a replacement.
8794 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
8795 ByteShift*8, (ByteShift+NumBytes)*8);
8796 if (!DAG.MaskedValueIsZero(IVal, Mask)) return nullptr;
8798 // Check that it is legal on the target to do this. It is legal if the new
8799 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
8801 MVT VT = MVT::getIntegerVT(NumBytes*8);
8802 if (!DC->isTypeLegal(VT))
8805 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
8806 // shifted by ByteShift and truncated down to NumBytes.
8808 IVal = DAG.getNode(ISD::SRL, SDLoc(IVal), IVal.getValueType(), IVal,
8809 DAG.getConstant(ByteShift*8,
8810 DC->getShiftAmountTy(IVal.getValueType())));
8812 // Figure out the offset for the store and the alignment of the access.
8814 unsigned NewAlign = St->getAlignment();
8816 if (DAG.getTargetLoweringInfo().isLittleEndian())
8817 StOffset = ByteShift;
8819 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
8821 SDValue Ptr = St->getBasePtr();
8823 Ptr = DAG.getNode(ISD::ADD, SDLoc(IVal), Ptr.getValueType(),
8824 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
8825 NewAlign = MinAlign(NewAlign, StOffset);
8828 // Truncate down to the new size.
8829 IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
8832 return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
8833 St->getPointerInfo().getWithOffset(StOffset),
8834 false, false, NewAlign).getNode();
8838 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
8839 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
8840 /// of the loaded bits, try narrowing the load and store if it would end up
8841 /// being a win for performance or code size.
8842 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
8843 StoreSDNode *ST = cast<StoreSDNode>(N);
8844 if (ST->isVolatile())
8847 SDValue Chain = ST->getChain();
8848 SDValue Value = ST->getValue();
8849 SDValue Ptr = ST->getBasePtr();
8850 EVT VT = Value.getValueType();
8852 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
8855 unsigned Opc = Value.getOpcode();
8857 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
8858 // is a byte mask indicating a consecutive number of bytes, check to see if
8859 // Y is known to provide just those bytes. If so, we try to replace the
8860 // load + replace + store sequence with a single (narrower) store, which makes
8862 if (Opc == ISD::OR) {
8863 std::pair<unsigned, unsigned> MaskedLoad;
8864 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
8865 if (MaskedLoad.first)
8866 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
8867 Value.getOperand(1), ST,this))
8868 return SDValue(NewST, 0);
8870 // Or is commutative, so try swapping X and Y.
8871 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
8872 if (MaskedLoad.first)
8873 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
8874 Value.getOperand(0), ST,this))
8875 return SDValue(NewST, 0);
8878 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
8879 Value.getOperand(1).getOpcode() != ISD::Constant)
8882 SDValue N0 = Value.getOperand(0);
8883 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
8884 Chain == SDValue(N0.getNode(), 1)) {
8885 LoadSDNode *LD = cast<LoadSDNode>(N0);
8886 if (LD->getBasePtr() != Ptr ||
8887 LD->getPointerInfo().getAddrSpace() !=
8888 ST->getPointerInfo().getAddrSpace())
8891 // Find the type to narrow it the load / op / store to.
8892 SDValue N1 = Value.getOperand(1);
8893 unsigned BitWidth = N1.getValueSizeInBits();
8894 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
8895 if (Opc == ISD::AND)
8896 Imm ^= APInt::getAllOnesValue(BitWidth);
8897 if (Imm == 0 || Imm.isAllOnesValue())
8899 unsigned ShAmt = Imm.countTrailingZeros();
8900 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
8901 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
8902 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
8903 while (NewBW < BitWidth &&
8904 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
8905 TLI.isNarrowingProfitable(VT, NewVT))) {
8906 NewBW = NextPowerOf2(NewBW);
8907 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
8909 if (NewBW >= BitWidth)
8912 // If the lsb changed does not start at the type bitwidth boundary,
8913 // start at the previous one.
8915 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
8916 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt,
8917 std::min(BitWidth, ShAmt + NewBW));
8918 if ((Imm & Mask) == Imm) {
8919 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
8920 if (Opc == ISD::AND)
8921 NewImm ^= APInt::getAllOnesValue(NewBW);
8922 uint64_t PtrOff = ShAmt / 8;
8923 // For big endian targets, we need to adjust the offset to the pointer to
8924 // load the correct bytes.
8925 if (TLI.isBigEndian())
8926 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
8928 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
8929 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
8930 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy))
8933 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD),
8934 Ptr.getValueType(), Ptr,
8935 DAG.getConstant(PtrOff, Ptr.getValueType()));
8936 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0),
8937 LD->getChain(), NewPtr,
8938 LD->getPointerInfo().getWithOffset(PtrOff),
8939 LD->isVolatile(), LD->isNonTemporal(),
8940 LD->isInvariant(), NewAlign,
8942 SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD,
8943 DAG.getConstant(NewImm, NewVT));
8944 SDValue NewST = DAG.getStore(Chain, SDLoc(N),
8946 ST->getPointerInfo().getWithOffset(PtrOff),
8947 false, false, NewAlign);
8949 AddToWorklist(NewPtr.getNode());
8950 AddToWorklist(NewLD.getNode());
8951 AddToWorklist(NewVal.getNode());
8952 WorklistRemover DeadNodes(*this);
8953 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
8962 /// TransformFPLoadStorePair - For a given floating point load / store pair,
8963 /// if the load value isn't used by any other operations, then consider
8964 /// transforming the pair to integer load / store operations if the target
8965 /// deems the transformation profitable.
8966 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
8967 StoreSDNode *ST = cast<StoreSDNode>(N);
8968 SDValue Chain = ST->getChain();
8969 SDValue Value = ST->getValue();
8970 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
8971 Value.hasOneUse() &&
8972 Chain == SDValue(Value.getNode(), 1)) {
8973 LoadSDNode *LD = cast<LoadSDNode>(Value);
8974 EVT VT = LD->getMemoryVT();
8975 if (!VT.isFloatingPoint() ||
8976 VT != ST->getMemoryVT() ||
8977 LD->isNonTemporal() ||
8978 ST->isNonTemporal() ||
8979 LD->getPointerInfo().getAddrSpace() != 0 ||
8980 ST->getPointerInfo().getAddrSpace() != 0)
8983 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
8984 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
8985 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
8986 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
8987 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
8990 unsigned LDAlign = LD->getAlignment();
8991 unsigned STAlign = ST->getAlignment();
8992 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
8993 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy);
8994 if (LDAlign < ABIAlign || STAlign < ABIAlign)
8997 SDValue NewLD = DAG.getLoad(IntVT, SDLoc(Value),
8998 LD->getChain(), LD->getBasePtr(),
8999 LD->getPointerInfo(),
9000 false, false, false, LDAlign);
9002 SDValue NewST = DAG.getStore(NewLD.getValue(1), SDLoc(N),
9003 NewLD, ST->getBasePtr(),
9004 ST->getPointerInfo(),
9005 false, false, STAlign);
9007 AddToWorklist(NewLD.getNode());
9008 AddToWorklist(NewST.getNode());
9009 WorklistRemover DeadNodes(*this);
9010 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
9018 /// Helper struct to parse and store a memory address as base + index + offset.
9019 /// We ignore sign extensions when it is safe to do so.
9020 /// The following two expressions are not equivalent. To differentiate we need
9021 /// to store whether there was a sign extension involved in the index
9023 /// (load (i64 add (i64 copyfromreg %c)
9024 /// (i64 signextend (add (i8 load %index)
9028 /// (load (i64 add (i64 copyfromreg %c)
9029 /// (i64 signextend (i32 add (i32 signextend (i8 load %index))
9031 struct BaseIndexOffset {
9035 bool IsIndexSignExt;
9037 BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
9039 BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
9040 bool IsIndexSignExt) :
9041 Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {}
9043 bool equalBaseIndex(const BaseIndexOffset &Other) {
9044 return Other.Base == Base && Other.Index == Index &&
9045 Other.IsIndexSignExt == IsIndexSignExt;
9048 /// Parses tree in Ptr for base, index, offset addresses.
9049 static BaseIndexOffset match(SDValue Ptr) {
9050 bool IsIndexSignExt = false;
9052 // We only can pattern match BASE + INDEX + OFFSET. If Ptr is not an ADD
9053 // instruction, then it could be just the BASE or everything else we don't
9054 // know how to handle. Just use Ptr as BASE and give up.
9055 if (Ptr->getOpcode() != ISD::ADD)
9056 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9058 // We know that we have at least an ADD instruction. Try to pattern match
9059 // the simple case of BASE + OFFSET.
9060 if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
9061 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
9062 return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
9066 // Inside a loop the current BASE pointer is calculated using an ADD and a
9067 // MUL instruction. In this case Ptr is the actual BASE pointer.
9068 // (i64 add (i64 %array_ptr)
9069 // (i64 mul (i64 %induction_var)
9070 // (i64 %element_size)))
9071 if (Ptr->getOperand(1)->getOpcode() == ISD::MUL)
9072 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9074 // Look at Base + Index + Offset cases.
9075 SDValue Base = Ptr->getOperand(0);
9076 SDValue IndexOffset = Ptr->getOperand(1);
9078 // Skip signextends.
9079 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
9080 IndexOffset = IndexOffset->getOperand(0);
9081 IsIndexSignExt = true;
9084 // Either the case of Base + Index (no offset) or something else.
9085 if (IndexOffset->getOpcode() != ISD::ADD)
9086 return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt);
9088 // Now we have the case of Base + Index + offset.
9089 SDValue Index = IndexOffset->getOperand(0);
9090 SDValue Offset = IndexOffset->getOperand(1);
9092 if (!isa<ConstantSDNode>(Offset))
9093 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
9095 // Ignore signextends.
9096 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
9097 Index = Index->getOperand(0);
9098 IsIndexSignExt = true;
9099 } else IsIndexSignExt = false;
9101 int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
9102 return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
9106 /// Holds a pointer to an LSBaseSDNode as well as information on where it
9107 /// is located in a sequence of memory operations connected by a chain.
9109 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
9110 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
9111 // Ptr to the mem node.
9112 LSBaseSDNode *MemNode;
9113 // Offset from the base ptr.
9114 int64_t OffsetFromBase;
9115 // What is the sequence number of this mem node.
9116 // Lowest mem operand in the DAG starts at zero.
9117 unsigned SequenceNum;
9120 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
9121 EVT MemVT = St->getMemoryVT();
9122 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8;
9123 bool NoVectors = DAG.getMachineFunction().getFunction()->getAttributes().
9124 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat);
9126 // Don't merge vectors into wider inputs.
9127 if (MemVT.isVector() || !MemVT.isSimple())
9130 // Perform an early exit check. Do not bother looking at stored values that
9131 // are not constants or loads.
9132 SDValue StoredVal = St->getValue();
9133 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
9134 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) &&
9138 // Only look at ends of store sequences.
9139 SDValue Chain = SDValue(St, 0);
9140 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
9143 // This holds the base pointer, index, and the offset in bytes from the base
9145 BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr());
9147 // We must have a base and an offset.
9148 if (!BasePtr.Base.getNode())
9151 // Do not handle stores to undef base pointers.
9152 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
9155 // Save the LoadSDNodes that we find in the chain.
9156 // We need to make sure that these nodes do not interfere with
9157 // any of the store nodes.
9158 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
9160 // Save the StoreSDNodes that we find in the chain.
9161 SmallVector<MemOpLink, 8> StoreNodes;
9163 // Walk up the chain and look for nodes with offsets from the same
9164 // base pointer. Stop when reaching an instruction with a different kind
9165 // or instruction which has a different base pointer.
9167 StoreSDNode *Index = St;
9169 // If the chain has more than one use, then we can't reorder the mem ops.
9170 if (Index != St && !SDValue(Index, 0)->hasOneUse())
9173 // Find the base pointer and offset for this memory node.
9174 BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr());
9176 // Check that the base pointer is the same as the original one.
9177 if (!Ptr.equalBaseIndex(BasePtr))
9180 // Check that the alignment is the same.
9181 if (Index->getAlignment() != St->getAlignment())
9184 // The memory operands must not be volatile.
9185 if (Index->isVolatile() || Index->isIndexed())
9189 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
9190 if (St->isTruncatingStore())
9193 // The stored memory type must be the same.
9194 if (Index->getMemoryVT() != MemVT)
9197 // We do not allow unaligned stores because we want to prevent overriding
9199 if (Index->getAlignment()*8 != MemVT.getSizeInBits())
9202 // We found a potential memory operand to merge.
9203 StoreNodes.push_back(MemOpLink(Index, Ptr.Offset, Seq++));
9205 // Find the next memory operand in the chain. If the next operand in the
9206 // chain is a store then move up and continue the scan with the next
9207 // memory operand. If the next operand is a load save it and use alias
9208 // information to check if it interferes with anything.
9209 SDNode *NextInChain = Index->getChain().getNode();
9211 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
9212 // We found a store node. Use it for the next iteration.
9215 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
9216 if (Ldn->isVolatile()) {
9221 // Save the load node for later. Continue the scan.
9222 AliasLoadNodes.push_back(Ldn);
9223 NextInChain = Ldn->getChain().getNode();
9232 // Check if there is anything to merge.
9233 if (StoreNodes.size() < 2)
9236 // Sort the memory operands according to their distance from the base pointer.
9237 std::sort(StoreNodes.begin(), StoreNodes.end(),
9238 [](MemOpLink LHS, MemOpLink RHS) {
9239 return LHS.OffsetFromBase < RHS.OffsetFromBase ||
9240 (LHS.OffsetFromBase == RHS.OffsetFromBase &&
9241 LHS.SequenceNum > RHS.SequenceNum);
9244 // Scan the memory operations on the chain and find the first non-consecutive
9245 // store memory address.
9246 unsigned LastConsecutiveStore = 0;
9247 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
9248 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {
9250 // Check that the addresses are consecutive starting from the second
9251 // element in the list of stores.
9253 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
9254 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
9259 // Check if this store interferes with any of the loads that we found.
9260 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
9261 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
9265 // We found a load that alias with this store. Stop the sequence.
9269 // Mark this node as useful.
9270 LastConsecutiveStore = i;
9273 // The node with the lowest store address.
9274 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
9276 // Store the constants into memory as one consecutive store.
9278 unsigned LastLegalType = 0;
9279 unsigned LastLegalVectorType = 0;
9280 bool NonZero = false;
9281 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
9282 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9283 SDValue StoredVal = St->getValue();
9285 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
9286 NonZero |= !C->isNullValue();
9287 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
9288 NonZero |= !C->getConstantFPValue()->isNullValue();
9294 // Find a legal type for the constant store.
9295 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
9296 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9297 if (TLI.isTypeLegal(StoreTy))
9298 LastLegalType = i+1;
9299 // Or check whether a truncstore is legal.
9300 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
9301 TargetLowering::TypePromoteInteger) {
9302 EVT LegalizedStoredValueTy =
9303 TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType());
9304 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy))
9305 LastLegalType = i+1;
9308 // Find a legal type for the vector store.
9309 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
9310 if (TLI.isTypeLegal(Ty))
9311 LastLegalVectorType = i + 1;
9314 // We only use vectors if the constant is known to be zero and the
9315 // function is not marked with the noimplicitfloat attribute.
9316 if (NonZero || NoVectors)
9317 LastLegalVectorType = 0;
9319 // Check if we found a legal integer type to store.
9320 if (LastLegalType == 0 && LastLegalVectorType == 0)
9323 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors;
9324 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
9326 // Make sure we have something to merge.
9330 unsigned EarliestNodeUsed = 0;
9331 for (unsigned i=0; i < NumElem; ++i) {
9332 // Find a chain for the new wide-store operand. Notice that some
9333 // of the store nodes that we found may not be selected for inclusion
9334 // in the wide store. The chain we use needs to be the chain of the
9335 // earliest store node which is *used* and replaced by the wide store.
9336 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
9337 EarliestNodeUsed = i;
9340 // The earliest Node in the DAG.
9341 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
9342 SDLoc DL(StoreNodes[0].MemNode);
9346 // Find a legal type for the vector store.
9347 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
9348 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
9349 StoredVal = DAG.getConstant(0, Ty);
9351 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
9352 APInt StoreInt(StoreBW, 0);
9354 // Construct a single integer constant which is made of the smaller
9356 bool IsLE = TLI.isLittleEndian();
9357 for (unsigned i = 0; i < NumElem ; ++i) {
9358 unsigned Idx = IsLE ?(NumElem - 1 - i) : i;
9359 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
9360 SDValue Val = St->getValue();
9361 StoreInt<<=ElementSizeBytes*8;
9362 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
9363 StoreInt|=C->getAPIntValue().zext(StoreBW);
9364 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
9365 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW);
9367 assert(false && "Invalid constant element type");
9371 // Create the new Load and Store operations.
9372 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9373 StoredVal = DAG.getConstant(StoreInt, StoreTy);
9376 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal,
9377 FirstInChain->getBasePtr(),
9378 FirstInChain->getPointerInfo(),
9380 FirstInChain->getAlignment());
9382 // Replace the first store with the new store
9383 CombineTo(EarliestOp, NewStore);
9384 // Erase all other stores.
9385 for (unsigned i = 0; i < NumElem ; ++i) {
9386 if (StoreNodes[i].MemNode == EarliestOp)
9388 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9389 // ReplaceAllUsesWith will replace all uses that existed when it was
9390 // called, but graph optimizations may cause new ones to appear. For
9391 // example, the case in pr14333 looks like
9393 // St's chain -> St -> another store -> X
9395 // And the only difference from St to the other store is the chain.
9396 // When we change it's chain to be St's chain they become identical,
9397 // get CSEed and the net result is that X is now a use of St.
9398 // Since we know that St is redundant, just iterate.
9399 while (!St->use_empty())
9400 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
9401 deleteAndRecombine(St);
9407 // Below we handle the case of multiple consecutive stores that
9408 // come from multiple consecutive loads. We merge them into a single
9409 // wide load and a single wide store.
9411 // Look for load nodes which are used by the stored values.
9412 SmallVector<MemOpLink, 8> LoadNodes;
9414 // Find acceptable loads. Loads need to have the same chain (token factor),
9415 // must not be zext, volatile, indexed, and they must be consecutive.
9416 BaseIndexOffset LdBasePtr;
9417 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
9418 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9419 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
9422 // Loads must only have one use.
9423 if (!Ld->hasNUsesOfValue(1, 0))
9426 // Check that the alignment is the same as the stores.
9427 if (Ld->getAlignment() != St->getAlignment())
9430 // The memory operands must not be volatile.
9431 if (Ld->isVolatile() || Ld->isIndexed())
9434 // We do not accept ext loads.
9435 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
9438 // The stored memory type must be the same.
9439 if (Ld->getMemoryVT() != MemVT)
9442 BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld->getBasePtr());
9443 // If this is not the first ptr that we check.
9444 if (LdBasePtr.Base.getNode()) {
9445 // The base ptr must be the same.
9446 if (!LdPtr.equalBaseIndex(LdBasePtr))
9449 // Check that all other base pointers are the same as this one.
9453 // We found a potential memory operand to merge.
9454 LoadNodes.push_back(MemOpLink(Ld, LdPtr.Offset, 0));
9457 if (LoadNodes.size() < 2)
9460 // If we have load/store pair instructions and we only have two values,
9462 unsigned RequiredAlignment;
9463 if (LoadNodes.size() == 2 && TLI.hasPairedLoad(MemVT, RequiredAlignment) &&
9464 St->getAlignment() >= RequiredAlignment)
9467 // Scan the memory operations on the chain and find the first non-consecutive
9468 // load memory address. These variables hold the index in the store node
9470 unsigned LastConsecutiveLoad = 0;
9471 // This variable refers to the size and not index in the array.
9472 unsigned LastLegalVectorType = 0;
9473 unsigned LastLegalIntegerType = 0;
9474 StartAddress = LoadNodes[0].OffsetFromBase;
9475 SDValue FirstChain = LoadNodes[0].MemNode->getChain();
9476 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
9477 // All loads much share the same chain.
9478 if (LoadNodes[i].MemNode->getChain() != FirstChain)
9481 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
9482 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
9484 LastConsecutiveLoad = i;
9486 // Find a legal type for the vector store.
9487 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1);
9488 if (TLI.isTypeLegal(StoreTy))
9489 LastLegalVectorType = i + 1;
9491 // Find a legal type for the integer store.
9492 unsigned StoreBW = (i+1) * ElementSizeBytes * 8;
9493 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9494 if (TLI.isTypeLegal(StoreTy))
9495 LastLegalIntegerType = i + 1;
9496 // Or check whether a truncstore and extload is legal.
9497 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) ==
9498 TargetLowering::TypePromoteInteger) {
9499 EVT LegalizedStoredValueTy =
9500 TLI.getTypeToTransformTo(*DAG.getContext(), StoreTy);
9501 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
9502 TLI.isLoadExtLegal(ISD::ZEXTLOAD, StoreTy) &&
9503 TLI.isLoadExtLegal(ISD::SEXTLOAD, StoreTy) &&
9504 TLI.isLoadExtLegal(ISD::EXTLOAD, StoreTy))
9505 LastLegalIntegerType = i+1;
9509 // Only use vector types if the vector type is larger than the integer type.
9510 // If they are the same, use integers.
9511 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors;
9512 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
9514 // We add +1 here because the LastXXX variables refer to location while
9515 // the NumElem refers to array/index size.
9516 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
9517 NumElem = std::min(LastLegalType, NumElem);
9522 // The earliest Node in the DAG.
9523 unsigned EarliestNodeUsed = 0;
9524 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode;
9525 for (unsigned i=1; i<NumElem; ++i) {
9526 // Find a chain for the new wide-store operand. Notice that some
9527 // of the store nodes that we found may not be selected for inclusion
9528 // in the wide store. The chain we use needs to be the chain of the
9529 // earliest store node which is *used* and replaced by the wide store.
9530 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum)
9531 EarliestNodeUsed = i;
9534 // Find if it is better to use vectors or integers to load and store
9538 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
9540 unsigned StoreBW = NumElem * ElementSizeBytes * 8;
9541 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW);
9544 SDLoc LoadDL(LoadNodes[0].MemNode);
9545 SDLoc StoreDL(StoreNodes[0].MemNode);
9547 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
9548 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL,
9549 FirstLoad->getChain(),
9550 FirstLoad->getBasePtr(),
9551 FirstLoad->getPointerInfo(),
9552 false, false, false,
9553 FirstLoad->getAlignment());
9555 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad,
9556 FirstInChain->getBasePtr(),
9557 FirstInChain->getPointerInfo(), false, false,
9558 FirstInChain->getAlignment());
9560 // Replace one of the loads with the new load.
9561 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
9562 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
9563 SDValue(NewLoad.getNode(), 1));
9565 // Remove the rest of the load chains.
9566 for (unsigned i = 1; i < NumElem ; ++i) {
9567 // Replace all chain users of the old load nodes with the chain of the new
9569 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
9570 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
9573 // Replace the first store with the new store.
9574 CombineTo(EarliestOp, NewStore);
9575 // Erase all other stores.
9576 for (unsigned i = 0; i < NumElem ; ++i) {
9577 // Remove all Store nodes.
9578 if (StoreNodes[i].MemNode == EarliestOp)
9580 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
9581 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
9582 deleteAndRecombine(St);
9588 SDValue DAGCombiner::visitSTORE(SDNode *N) {
9589 StoreSDNode *ST = cast<StoreSDNode>(N);
9590 SDValue Chain = ST->getChain();
9591 SDValue Value = ST->getValue();
9592 SDValue Ptr = ST->getBasePtr();
9594 // If this is a store of a bit convert, store the input value if the
9595 // resultant store does not need a higher alignment than the original.
9596 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
9597 ST->isUnindexed()) {
9598 unsigned OrigAlign = ST->getAlignment();
9599 EVT SVT = Value.getOperand(0).getValueType();
9600 unsigned Align = TLI.getDataLayout()->
9601 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
9602 if (Align <= OrigAlign &&
9603 ((!LegalOperations && !ST->isVolatile()) ||
9604 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
9605 return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0),
9606 Ptr, ST->getPointerInfo(), ST->isVolatile(),
9607 ST->isNonTemporal(), OrigAlign,
9611 // Turn 'store undef, Ptr' -> nothing.
9612 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
9615 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
9616 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
9617 // NOTE: If the original store is volatile, this transform must not increase
9618 // the number of stores. For example, on x86-32 an f64 can be stored in one
9619 // processor operation but an i64 (which is not legal) requires two. So the
9620 // transform should not be done in this case.
9621 if (Value.getOpcode() != ISD::TargetConstantFP) {
9623 switch (CFP->getSimpleValueType(0).SimpleTy) {
9624 default: llvm_unreachable("Unknown FP type");
9625 case MVT::f16: // We don't do this for these yet.
9631 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
9632 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
9633 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
9634 bitcastToAPInt().getZExtValue(), MVT::i32);
9635 return DAG.getStore(Chain, SDLoc(N), Tmp,
9636 Ptr, ST->getMemOperand());
9640 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
9641 !ST->isVolatile()) ||
9642 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
9643 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
9644 getZExtValue(), MVT::i64);
9645 return DAG.getStore(Chain, SDLoc(N), Tmp,
9646 Ptr, ST->getMemOperand());
9649 if (!ST->isVolatile() &&
9650 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
9651 // Many FP stores are not made apparent until after legalize, e.g. for
9652 // argument passing. Since this is so common, custom legalize the
9653 // 64-bit integer store into two 32-bit stores.
9654 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
9655 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
9656 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
9657 if (TLI.isBigEndian()) std::swap(Lo, Hi);
9659 unsigned Alignment = ST->getAlignment();
9660 bool isVolatile = ST->isVolatile();
9661 bool isNonTemporal = ST->isNonTemporal();
9662 AAMDNodes AAInfo = ST->getAAInfo();
9664 SDValue St0 = DAG.getStore(Chain, SDLoc(ST), Lo,
9665 Ptr, ST->getPointerInfo(),
9666 isVolatile, isNonTemporal,
9667 ST->getAlignment(), AAInfo);
9668 Ptr = DAG.getNode(ISD::ADD, SDLoc(N), Ptr.getValueType(), Ptr,
9669 DAG.getConstant(4, Ptr.getValueType()));
9670 Alignment = MinAlign(Alignment, 4U);
9671 SDValue St1 = DAG.getStore(Chain, SDLoc(ST), Hi,
9672 Ptr, ST->getPointerInfo().getWithOffset(4),
9673 isVolatile, isNonTemporal,
9675 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other,
9684 // Try to infer better alignment information than the store already has.
9685 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
9686 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
9687 if (Align > ST->getAlignment())
9688 return DAG.getTruncStore(Chain, SDLoc(N), Value,
9689 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
9690 ST->isVolatile(), ST->isNonTemporal(), Align,
9695 // Try transforming a pair floating point load / store ops to integer
9696 // load / store ops.
9697 SDValue NewST = TransformFPLoadStorePair(N);
9698 if (NewST.getNode())
9701 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA :
9702 TLI.getTargetMachine().getSubtarget<TargetSubtargetInfo>().useAA();
9704 if (CombinerAAOnlyFunc.getNumOccurrences() &&
9705 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
9708 if (UseAA && ST->isUnindexed()) {
9709 // Walk up chain skipping non-aliasing memory nodes.
9710 SDValue BetterChain = FindBetterChain(N, Chain);
9712 // If there is a better chain.
9713 if (Chain != BetterChain) {
9716 // Replace the chain to avoid dependency.
9717 if (ST->isTruncatingStore()) {
9718 ReplStore = DAG.getTruncStore(BetterChain, SDLoc(N), Value, Ptr,
9719 ST->getMemoryVT(), ST->getMemOperand());
9721 ReplStore = DAG.getStore(BetterChain, SDLoc(N), Value, Ptr,
9722 ST->getMemOperand());
9725 // Create token to keep both nodes around.
9726 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
9727 MVT::Other, Chain, ReplStore);
9729 // Make sure the new and old chains are cleaned up.
9730 AddToWorklist(Token.getNode());
9732 // Don't add users to work list.
9733 return CombineTo(N, Token, false);
9737 // Try transforming N to an indexed store.
9738 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
9739 return SDValue(N, 0);
9741 // FIXME: is there such a thing as a truncating indexed store?
9742 if (ST->isTruncatingStore() && ST->isUnindexed() &&
9743 Value.getValueType().isInteger()) {
9744 // See if we can simplify the input to this truncstore with knowledge that
9745 // only the low bits are being used. For example:
9746 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
9748 GetDemandedBits(Value,
9749 APInt::getLowBitsSet(
9750 Value.getValueType().getScalarType().getSizeInBits(),
9751 ST->getMemoryVT().getScalarType().getSizeInBits()));
9752 AddToWorklist(Value.getNode());
9753 if (Shorter.getNode())
9754 return DAG.getTruncStore(Chain, SDLoc(N), Shorter,
9755 Ptr, ST->getMemoryVT(), ST->getMemOperand());
9757 // Otherwise, see if we can simplify the operation with
9758 // SimplifyDemandedBits, which only works if the value has a single use.
9759 if (SimplifyDemandedBits(Value,
9760 APInt::getLowBitsSet(
9761 Value.getValueType().getScalarType().getSizeInBits(),
9762 ST->getMemoryVT().getScalarType().getSizeInBits())))
9763 return SDValue(N, 0);
9766 // If this is a load followed by a store to the same location, then the store
9768 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
9769 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
9770 ST->isUnindexed() && !ST->isVolatile() &&
9771 // There can't be any side effects between the load and store, such as
9773 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
9774 // The store is dead, remove it.
9779 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
9780 // truncating store. We can do this even if this is already a truncstore.
9781 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
9782 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
9783 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
9784 ST->getMemoryVT())) {
9785 return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0),
9786 Ptr, ST->getMemoryVT(), ST->getMemOperand());
9789 // Only perform this optimization before the types are legal, because we
9790 // don't want to perform this optimization on every DAGCombine invocation.
9792 bool EverChanged = false;
9795 // There can be multiple store sequences on the same chain.
9796 // Keep trying to merge store sequences until we are unable to do so
9797 // or until we merge the last store on the chain.
9798 bool Changed = MergeConsecutiveStores(ST);
9799 EverChanged |= Changed;
9800 if (!Changed) break;
9801 } while (ST->getOpcode() != ISD::DELETED_NODE);
9804 return SDValue(N, 0);
9807 return ReduceLoadOpStoreWidth(N);
9810 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
9811 SDValue InVec = N->getOperand(0);
9812 SDValue InVal = N->getOperand(1);
9813 SDValue EltNo = N->getOperand(2);
9816 // If the inserted element is an UNDEF, just use the input vector.
9817 if (InVal.getOpcode() == ISD::UNDEF)
9820 EVT VT = InVec.getValueType();
9822 // If we can't generate a legal BUILD_VECTOR, exit
9823 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
9826 // Check that we know which element is being inserted
9827 if (!isa<ConstantSDNode>(EltNo))
9829 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
9831 // Canonicalize insert_vector_elt dag nodes.
9833 // (insert_vector_elt (insert_vector_elt A, Idx0), Idx1)
9834 // -> (insert_vector_elt (insert_vector_elt A, Idx1), Idx0)
9836 // Do this only if the child insert_vector node has one use; also
9837 // do this only if indices are both constants and Idx1 < Idx0.
9838 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
9839 && isa<ConstantSDNode>(InVec.getOperand(2))) {
9841 cast<ConstantSDNode>(InVec.getOperand(2))->getZExtValue();
9842 if (Elt < OtherElt) {
9844 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VT,
9845 InVec.getOperand(0), InVal, EltNo);
9846 AddToWorklist(NewOp.getNode());
9847 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()),
9848 VT, NewOp, InVec.getOperand(1), InVec.getOperand(2));
9852 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
9853 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
9855 SmallVector<SDValue, 8> Ops;
9856 // Do not combine these two vectors if the output vector will not replace
9857 // the input vector.
9858 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) {
9859 Ops.append(InVec.getNode()->op_begin(),
9860 InVec.getNode()->op_end());
9861 } else if (InVec.getOpcode() == ISD::UNDEF) {
9862 unsigned NElts = VT.getVectorNumElements();
9863 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
9868 // Insert the element
9869 if (Elt < Ops.size()) {
9870 // All the operands of BUILD_VECTOR must have the same type;
9871 // we enforce that here.
9872 EVT OpVT = Ops[0].getValueType();
9873 if (InVal.getValueType() != OpVT)
9874 InVal = OpVT.bitsGT(InVal.getValueType()) ?
9875 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
9876 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
9880 // Return the new vector
9881 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
9884 SDValue DAGCombiner::ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
9885 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad) {
9886 EVT ResultVT = EVE->getValueType(0);
9887 EVT VecEltVT = InVecVT.getVectorElementType();
9888 unsigned Align = OriginalLoad->getAlignment();
9889 unsigned NewAlign = TLI.getDataLayout()->getABITypeAlignment(
9890 VecEltVT.getTypeForEVT(*DAG.getContext()));
9892 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT))
9897 SDValue NewPtr = OriginalLoad->getBasePtr();
9899 EVT PtrType = NewPtr.getValueType();
9900 MachinePointerInfo MPI;
9901 if (auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo)) {
9902 int Elt = ConstEltNo->getZExtValue();
9903 unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / 8;
9904 if (TLI.isBigEndian())
9905 PtrOff = InVecVT.getSizeInBits() / 8 - PtrOff;
9906 Offset = DAG.getConstant(PtrOff, PtrType);
9907 MPI = OriginalLoad->getPointerInfo().getWithOffset(PtrOff);
9909 Offset = DAG.getNode(
9910 ISD::MUL, SDLoc(EVE), EltNo.getValueType(), EltNo,
9911 DAG.getConstant(VecEltVT.getStoreSize(), EltNo.getValueType()));
9912 if (TLI.isBigEndian())
9913 Offset = DAG.getNode(
9914 ISD::SUB, SDLoc(EVE), EltNo.getValueType(),
9915 DAG.getConstant(InVecVT.getStoreSize(), EltNo.getValueType()), Offset);
9916 MPI = OriginalLoad->getPointerInfo();
9918 NewPtr = DAG.getNode(ISD::ADD, SDLoc(EVE), PtrType, NewPtr, Offset);
9920 // The replacement we need to do here is a little tricky: we need to
9921 // replace an extractelement of a load with a load.
9922 // Use ReplaceAllUsesOfValuesWith to do the replacement.
9923 // Note that this replacement assumes that the extractvalue is the only
9924 // use of the load; that's okay because we don't want to perform this
9925 // transformation in other cases anyway.
9928 if (ResultVT.bitsGT(VecEltVT)) {
9929 // If the result type of vextract is wider than the load, then issue an
9930 // extending load instead.
9931 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, VecEltVT)
9934 Load = DAG.getExtLoad(
9935 ExtType, SDLoc(EVE), ResultVT, OriginalLoad->getChain(), NewPtr, MPI,
9936 VecEltVT, OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
9937 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
9938 Chain = Load.getValue(1);
9941 VecEltVT, SDLoc(EVE), OriginalLoad->getChain(), NewPtr, MPI,
9942 OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
9943 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
9944 Chain = Load.getValue(1);
9945 if (ResultVT.bitsLT(VecEltVT))
9946 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(EVE), ResultVT, Load);
9948 Load = DAG.getNode(ISD::BITCAST, SDLoc(EVE), ResultVT, Load);
9950 WorklistRemover DeadNodes(*this);
9951 SDValue From[] = { SDValue(EVE, 0), SDValue(OriginalLoad, 1) };
9952 SDValue To[] = { Load, Chain };
9953 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
9954 // Since we're explicitly calling ReplaceAllUses, add the new node to the
9955 // worklist explicitly as well.
9956 AddToWorklist(Load.getNode());
9957 AddUsersToWorklist(Load.getNode()); // Add users too
9958 // Make sure to revisit this node to clean it up; it will usually be dead.
9961 return SDValue(EVE, 0);
9964 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
9965 // (vextract (scalar_to_vector val, 0) -> val
9966 SDValue InVec = N->getOperand(0);
9967 EVT VT = InVec.getValueType();
9968 EVT NVT = N->getValueType(0);
9970 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
9971 // Check if the result type doesn't match the inserted element type. A
9972 // SCALAR_TO_VECTOR may truncate the inserted element and the
9973 // EXTRACT_VECTOR_ELT may widen the extracted vector.
9974 SDValue InOp = InVec.getOperand(0);
9975 if (InOp.getValueType() != NVT) {
9976 assert(InOp.getValueType().isInteger() && NVT.isInteger());
9977 return DAG.getSExtOrTrunc(InOp, SDLoc(InVec), NVT);
9982 SDValue EltNo = N->getOperand(1);
9983 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
9985 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
9986 // We only perform this optimization before the op legalization phase because
9987 // we may introduce new vector instructions which are not backed by TD
9988 // patterns. For example on AVX, extracting elements from a wide vector
9989 // without using extract_subvector. However, if we can find an underlying
9990 // scalar value, then we can always use that.
9991 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
9993 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
9994 int NumElem = VT.getVectorNumElements();
9995 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
9996 // Find the new index to extract from.
9997 int OrigElt = SVOp->getMaskElt(Elt);
9999 // Extracting an undef index is undef.
10001 return DAG.getUNDEF(NVT);
10003 // Select the right vector half to extract from.
10005 if (OrigElt < NumElem) {
10006 SVInVec = InVec->getOperand(0);
10008 SVInVec = InVec->getOperand(1);
10009 OrigElt -= NumElem;
10012 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
10013 SDValue InOp = SVInVec.getOperand(OrigElt);
10014 if (InOp.getValueType() != NVT) {
10015 assert(InOp.getValueType().isInteger() && NVT.isInteger());
10016 InOp = DAG.getSExtOrTrunc(InOp, SDLoc(SVInVec), NVT);
10022 // FIXME: We should handle recursing on other vector shuffles and
10023 // scalar_to_vector here as well.
10025 if (!LegalOperations) {
10026 EVT IndexTy = TLI.getVectorIdxTy();
10027 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT,
10028 SVInVec, DAG.getConstant(OrigElt, IndexTy));
10032 bool BCNumEltsChanged = false;
10033 EVT ExtVT = VT.getVectorElementType();
10036 // If the result of load has to be truncated, then it's not necessarily
10038 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
10041 if (InVec.getOpcode() == ISD::BITCAST) {
10042 // Don't duplicate a load with other uses.
10043 if (!InVec.hasOneUse())
10046 EVT BCVT = InVec.getOperand(0).getValueType();
10047 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
10049 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
10050 BCNumEltsChanged = true;
10051 InVec = InVec.getOperand(0);
10052 ExtVT = BCVT.getVectorElementType();
10055 // (vextract (vN[if]M load $addr), i) -> ([if]M load $addr + i * size)
10056 if (!LegalOperations && !ConstEltNo && InVec.hasOneUse() &&
10057 ISD::isNormalLoad(InVec.getNode()) &&
10058 !N->getOperand(1)->hasPredecessor(InVec.getNode())) {
10059 SDValue Index = N->getOperand(1);
10060 if (LoadSDNode *OrigLoad = dyn_cast<LoadSDNode>(InVec))
10061 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, Index,
10065 // Perform only after legalization to ensure build_vector / vector_shuffle
10066 // optimizations have already been done.
10067 if (!LegalOperations) return SDValue();
10069 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
10070 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
10071 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
10074 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
10076 LoadSDNode *LN0 = nullptr;
10077 const ShuffleVectorSDNode *SVN = nullptr;
10078 if (ISD::isNormalLoad(InVec.getNode())) {
10079 LN0 = cast<LoadSDNode>(InVec);
10080 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
10081 InVec.getOperand(0).getValueType() == ExtVT &&
10082 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
10083 // Don't duplicate a load with other uses.
10084 if (!InVec.hasOneUse())
10087 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
10088 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
10089 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
10091 // (load $addr+1*size)
10093 // Don't duplicate a load with other uses.
10094 if (!InVec.hasOneUse())
10097 // If the bit convert changed the number of elements, it is unsafe
10098 // to examine the mask.
10099 if (BCNumEltsChanged)
10102 // Select the input vector, guarding against out of range extract vector.
10103 unsigned NumElems = VT.getVectorNumElements();
10104 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
10105 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
10107 if (InVec.getOpcode() == ISD::BITCAST) {
10108 // Don't duplicate a load with other uses.
10109 if (!InVec.hasOneUse())
10112 InVec = InVec.getOperand(0);
10114 if (ISD::isNormalLoad(InVec.getNode())) {
10115 LN0 = cast<LoadSDNode>(InVec);
10116 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
10117 EltNo = DAG.getConstant(Elt, EltNo.getValueType());
10121 // Make sure we found a non-volatile load and the extractelement is
10123 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
10126 // If Idx was -1 above, Elt is going to be -1, so just return undef.
10128 return DAG.getUNDEF(LVT);
10130 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, EltNo, LN0);
10136 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
10137 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
10138 // We perform this optimization post type-legalization because
10139 // the type-legalizer often scalarizes integer-promoted vectors.
10140 // Performing this optimization before may create bit-casts which
10141 // will be type-legalized to complex code sequences.
10142 // We perform this optimization only before the operation legalizer because we
10143 // may introduce illegal operations.
10144 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
10147 unsigned NumInScalars = N->getNumOperands();
10149 EVT VT = N->getValueType(0);
10151 // Check to see if this is a BUILD_VECTOR of a bunch of values
10152 // which come from any_extend or zero_extend nodes. If so, we can create
10153 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
10154 // optimizations. We do not handle sign-extend because we can't fill the sign
10156 EVT SourceType = MVT::Other;
10157 bool AllAnyExt = true;
10159 for (unsigned i = 0; i != NumInScalars; ++i) {
10160 SDValue In = N->getOperand(i);
10161 // Ignore undef inputs.
10162 if (In.getOpcode() == ISD::UNDEF) continue;
10164 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
10165 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
10167 // Abort if the element is not an extension.
10168 if (!ZeroExt && !AnyExt) {
10169 SourceType = MVT::Other;
10173 // The input is a ZeroExt or AnyExt. Check the original type.
10174 EVT InTy = In.getOperand(0).getValueType();
10176 // Check that all of the widened source types are the same.
10177 if (SourceType == MVT::Other)
10180 else if (InTy != SourceType) {
10181 // Multiple income types. Abort.
10182 SourceType = MVT::Other;
10186 // Check if all of the extends are ANY_EXTENDs.
10187 AllAnyExt &= AnyExt;
10190 // In order to have valid types, all of the inputs must be extended from the
10191 // same source type and all of the inputs must be any or zero extend.
10192 // Scalar sizes must be a power of two.
10193 EVT OutScalarTy = VT.getScalarType();
10194 bool ValidTypes = SourceType != MVT::Other &&
10195 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
10196 isPowerOf2_32(SourceType.getSizeInBits());
10198 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
10199 // turn into a single shuffle instruction.
10203 bool isLE = TLI.isLittleEndian();
10204 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
10205 assert(ElemRatio > 1 && "Invalid element size ratio");
10206 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
10207 DAG.getConstant(0, SourceType);
10209 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
10210 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
10212 // Populate the new build_vector
10213 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
10214 SDValue Cast = N->getOperand(i);
10215 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
10216 Cast.getOpcode() == ISD::ZERO_EXTEND ||
10217 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
10219 if (Cast.getOpcode() == ISD::UNDEF)
10220 In = DAG.getUNDEF(SourceType);
10222 In = Cast->getOperand(0);
10223 unsigned Index = isLE ? (i * ElemRatio) :
10224 (i * ElemRatio + (ElemRatio - 1));
10226 assert(Index < Ops.size() && "Invalid index");
10230 // The type of the new BUILD_VECTOR node.
10231 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
10232 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
10233 "Invalid vector size");
10234 // Check if the new vector type is legal.
10235 if (!isTypeLegal(VecVT)) return SDValue();
10237 // Make the new BUILD_VECTOR.
10238 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
10240 // The new BUILD_VECTOR node has the potential to be further optimized.
10241 AddToWorklist(BV.getNode());
10242 // Bitcast to the desired type.
10243 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
10246 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
10247 EVT VT = N->getValueType(0);
10249 unsigned NumInScalars = N->getNumOperands();
10252 EVT SrcVT = MVT::Other;
10253 unsigned Opcode = ISD::DELETED_NODE;
10254 unsigned NumDefs = 0;
10256 for (unsigned i = 0; i != NumInScalars; ++i) {
10257 SDValue In = N->getOperand(i);
10258 unsigned Opc = In.getOpcode();
10260 if (Opc == ISD::UNDEF)
10263 // If all scalar values are floats and converted from integers.
10264 if (Opcode == ISD::DELETED_NODE &&
10265 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
10272 EVT InVT = In.getOperand(0).getValueType();
10274 // If all scalar values are typed differently, bail out. It's chosen to
10275 // simplify BUILD_VECTOR of integer types.
10276 if (SrcVT == MVT::Other)
10283 // If the vector has just one element defined, it's not worth to fold it into
10284 // a vectorized one.
10288 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
10289 && "Should only handle conversion from integer to float.");
10290 assert(SrcVT != MVT::Other && "Cannot determine source type!");
10292 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
10294 if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
10297 SmallVector<SDValue, 8> Opnds;
10298 for (unsigned i = 0; i != NumInScalars; ++i) {
10299 SDValue In = N->getOperand(i);
10301 if (In.getOpcode() == ISD::UNDEF)
10302 Opnds.push_back(DAG.getUNDEF(SrcVT));
10304 Opnds.push_back(In.getOperand(0));
10306 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Opnds);
10307 AddToWorklist(BV.getNode());
10309 return DAG.getNode(Opcode, dl, VT, BV);
10312 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
10313 unsigned NumInScalars = N->getNumOperands();
10315 EVT VT = N->getValueType(0);
10317 // A vector built entirely of undefs is undef.
10318 if (ISD::allOperandsUndef(N))
10319 return DAG.getUNDEF(VT);
10321 SDValue V = reduceBuildVecExtToExtBuildVec(N);
10325 V = reduceBuildVecConvertToConvertBuildVec(N);
10329 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
10330 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
10331 // at most two distinct vectors, turn this into a shuffle node.
10333 // May only combine to shuffle after legalize if shuffle is legal.
10334 if (LegalOperations &&
10335 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))
10338 SDValue VecIn1, VecIn2;
10339 for (unsigned i = 0; i != NumInScalars; ++i) {
10340 // Ignore undef inputs.
10341 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
10343 // If this input is something other than a EXTRACT_VECTOR_ELT with a
10344 // constant index, bail out.
10345 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
10346 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
10347 VecIn1 = VecIn2 = SDValue(nullptr, 0);
10351 // We allow up to two distinct input vectors.
10352 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
10353 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
10356 if (!VecIn1.getNode()) {
10357 VecIn1 = ExtractedFromVec;
10358 } else if (!VecIn2.getNode()) {
10359 VecIn2 = ExtractedFromVec;
10361 // Too many inputs.
10362 VecIn1 = VecIn2 = SDValue(nullptr, 0);
10367 // If everything is good, we can make a shuffle operation.
10368 if (VecIn1.getNode()) {
10369 SmallVector<int, 8> Mask;
10370 for (unsigned i = 0; i != NumInScalars; ++i) {
10371 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
10372 Mask.push_back(-1);
10376 // If extracting from the first vector, just use the index directly.
10377 SDValue Extract = N->getOperand(i);
10378 SDValue ExtVal = Extract.getOperand(1);
10379 if (Extract.getOperand(0) == VecIn1) {
10380 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
10381 if (ExtIndex > VT.getVectorNumElements())
10384 Mask.push_back(ExtIndex);
10388 // Otherwise, use InIdx + VecSize
10389 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
10390 Mask.push_back(Idx+NumInScalars);
10393 // We can't generate a shuffle node with mismatched input and output types.
10394 // Attempt to transform a single input vector to the correct type.
10395 if ((VT != VecIn1.getValueType())) {
10396 // We don't support shuffeling between TWO values of different types.
10397 if (VecIn2.getNode())
10400 // We only support widening of vectors which are half the size of the
10401 // output registers. For example XMM->YMM widening on X86 with AVX.
10402 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
10405 // If the input vector type has a different base type to the output
10406 // vector type, bail out.
10407 if (VecIn1.getValueType().getVectorElementType() !=
10408 VT.getVectorElementType())
10411 // Widen the input vector by adding undef values.
10412 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT,
10413 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
10416 // If VecIn2 is unused then change it to undef.
10417 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
10419 // Check that we were able to transform all incoming values to the same
10421 if (VecIn2.getValueType() != VecIn1.getValueType() ||
10422 VecIn1.getValueType() != VT)
10425 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
10426 if (!isTypeLegal(VT))
10429 // Return the new VECTOR_SHUFFLE node.
10433 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
10439 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
10440 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
10441 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
10442 // inputs come from at most two distinct vectors, turn this into a shuffle
10445 // If we only have one input vector, we don't need to do any concatenation.
10446 if (N->getNumOperands() == 1)
10447 return N->getOperand(0);
10449 // Check if all of the operands are undefs.
10450 EVT VT = N->getValueType(0);
10451 if (ISD::allOperandsUndef(N))
10452 return DAG.getUNDEF(VT);
10454 // Optimize concat_vectors where one of the vectors is undef.
10455 if (N->getNumOperands() == 2 &&
10456 N->getOperand(1)->getOpcode() == ISD::UNDEF) {
10457 SDValue In = N->getOperand(0);
10458 assert(In.getValueType().isVector() && "Must concat vectors");
10460 // Transform: concat_vectors(scalar, undef) -> scalar_to_vector(sclr).
10461 if (In->getOpcode() == ISD::BITCAST &&
10462 !In->getOperand(0)->getValueType(0).isVector()) {
10463 SDValue Scalar = In->getOperand(0);
10464 EVT SclTy = Scalar->getValueType(0);
10466 if (!SclTy.isFloatingPoint() && !SclTy.isInteger())
10469 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy,
10470 VT.getSizeInBits() / SclTy.getSizeInBits());
10471 if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType()))
10474 SDLoc dl = SDLoc(N);
10475 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar);
10476 return DAG.getNode(ISD::BITCAST, dl, VT, Res);
10480 // fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
10481 // -> (BUILD_VECTOR A, B, ..., C, D, ...)
10482 if (N->getNumOperands() == 2 &&
10483 N->getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
10484 N->getOperand(1).getOpcode() == ISD::BUILD_VECTOR) {
10485 EVT VT = N->getValueType(0);
10486 SDValue N0 = N->getOperand(0);
10487 SDValue N1 = N->getOperand(1);
10488 SmallVector<SDValue, 8> Opnds;
10489 unsigned BuildVecNumElts = N0.getNumOperands();
10491 EVT SclTy0 = N0.getOperand(0)->getValueType(0);
10492 EVT SclTy1 = N1.getOperand(0)->getValueType(0);
10493 if (SclTy0.isFloatingPoint()) {
10494 for (unsigned i = 0; i != BuildVecNumElts; ++i)
10495 Opnds.push_back(N0.getOperand(i));
10496 for (unsigned i = 0; i != BuildVecNumElts; ++i)
10497 Opnds.push_back(N1.getOperand(i));
10499 // If BUILD_VECTOR are from built from integer, they may have different
10500 // operand types. Get the smaller type and truncate all operands to it.
10501 EVT MinTy = SclTy0.bitsLE(SclTy1) ? SclTy0 : SclTy1;
10502 for (unsigned i = 0; i != BuildVecNumElts; ++i)
10503 Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
10504 N0.getOperand(i)));
10505 for (unsigned i = 0; i != BuildVecNumElts; ++i)
10506 Opnds.push_back(DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinTy,
10507 N1.getOperand(i)));
10510 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
10513 // Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
10514 // nodes often generate nop CONCAT_VECTOR nodes.
10515 // Scan the CONCAT_VECTOR operands and look for a CONCAT operations that
10516 // place the incoming vectors at the exact same location.
10517 SDValue SingleSource = SDValue();
10518 unsigned PartNumElem = N->getOperand(0).getValueType().getVectorNumElements();
10520 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
10521 SDValue Op = N->getOperand(i);
10523 if (Op.getOpcode() == ISD::UNDEF)
10526 // Check if this is the identity extract:
10527 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
10530 // Find the single incoming vector for the extract_subvector.
10531 if (SingleSource.getNode()) {
10532 if (Op.getOperand(0) != SingleSource)
10535 SingleSource = Op.getOperand(0);
10537 // Check the source type is the same as the type of the result.
10538 // If not, this concat may extend the vector, so we can not
10539 // optimize it away.
10540 if (SingleSource.getValueType() != N->getValueType(0))
10544 unsigned IdentityIndex = i * PartNumElem;
10545 ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1));
10546 // The extract index must be constant.
10550 // Check that we are reading from the identity index.
10551 if (CS->getZExtValue() != IdentityIndex)
10555 if (SingleSource.getNode())
10556 return SingleSource;
10561 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
10562 EVT NVT = N->getValueType(0);
10563 SDValue V = N->getOperand(0);
10565 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
10567 // (extract_subvec (concat V1, V2, ...), i)
10570 // Only operand 0 is checked as 'concat' assumes all inputs of the same
10572 if (V->getOperand(0).getValueType() != NVT)
10574 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
10575 unsigned NumElems = NVT.getVectorNumElements();
10576 assert((Idx % NumElems) == 0 &&
10577 "IDX in concat is not a multiple of the result vector length.");
10578 return V->getOperand(Idx / NumElems);
10582 if (V->getOpcode() == ISD::BITCAST)
10583 V = V.getOperand(0);
10585 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
10587 // Handle only simple case where vector being inserted and vector
10588 // being extracted are of same type, and are half size of larger vectors.
10589 EVT BigVT = V->getOperand(0).getValueType();
10590 EVT SmallVT = V->getOperand(1).getValueType();
10591 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
10594 // Only handle cases where both indexes are constants with the same type.
10595 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
10596 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
10598 if (InsIdx && ExtIdx &&
10599 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
10600 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
10602 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
10604 // indices are equal or bit offsets are equal => V1
10605 // otherwise => (extract_subvec V1, ExtIdx)
10606 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() ==
10607 ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits())
10608 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1));
10609 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT,
10610 DAG.getNode(ISD::BITCAST, dl,
10611 N->getOperand(0).getValueType(),
10612 V->getOperand(0)), N->getOperand(1));
10619 // Tries to turn a shuffle of two CONCAT_VECTORS into a single concat.
10620 static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
10621 EVT VT = N->getValueType(0);
10622 unsigned NumElts = VT.getVectorNumElements();
10624 SDValue N0 = N->getOperand(0);
10625 SDValue N1 = N->getOperand(1);
10626 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
10628 SmallVector<SDValue, 4> Ops;
10629 EVT ConcatVT = N0.getOperand(0).getValueType();
10630 unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements();
10631 unsigned NumConcats = NumElts / NumElemsPerConcat;
10633 // Look at every vector that's inserted. We're looking for exact
10634 // subvector-sized copies from a concatenated vector
10635 for (unsigned I = 0; I != NumConcats; ++I) {
10636 // Make sure we're dealing with a copy.
10637 unsigned Begin = I * NumElemsPerConcat;
10638 bool AllUndef = true, NoUndef = true;
10639 for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) {
10640 if (SVN->getMaskElt(J) >= 0)
10647 if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0)
10650 for (unsigned J = 1; J != NumElemsPerConcat; ++J)
10651 if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J))
10654 unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat;
10655 if (FirstElt < N0.getNumOperands())
10656 Ops.push_back(N0.getOperand(FirstElt));
10658 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
10660 } else if (AllUndef) {
10661 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType()));
10662 } else { // Mixed with general masks and undefs, can't do optimization.
10667 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
10670 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
10671 EVT VT = N->getValueType(0);
10672 unsigned NumElts = VT.getVectorNumElements();
10674 SDValue N0 = N->getOperand(0);
10675 SDValue N1 = N->getOperand(1);
10677 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
10679 // Canonicalize shuffle undef, undef -> undef
10680 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
10681 return DAG.getUNDEF(VT);
10683 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
10685 // Canonicalize shuffle v, v -> v, undef
10687 SmallVector<int, 8> NewMask;
10688 for (unsigned i = 0; i != NumElts; ++i) {
10689 int Idx = SVN->getMaskElt(i);
10690 if (Idx >= (int)NumElts) Idx -= NumElts;
10691 NewMask.push_back(Idx);
10693 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
10697 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
10698 if (N0.getOpcode() == ISD::UNDEF) {
10699 SmallVector<int, 8> NewMask;
10700 for (unsigned i = 0; i != NumElts; ++i) {
10701 int Idx = SVN->getMaskElt(i);
10703 if (Idx >= (int)NumElts)
10706 Idx = -1; // remove reference to lhs
10708 NewMask.push_back(Idx);
10710 return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT),
10714 // Remove references to rhs if it is undef
10715 if (N1.getOpcode() == ISD::UNDEF) {
10716 bool Changed = false;
10717 SmallVector<int, 8> NewMask;
10718 for (unsigned i = 0; i != NumElts; ++i) {
10719 int Idx = SVN->getMaskElt(i);
10720 if (Idx >= (int)NumElts) {
10724 NewMask.push_back(Idx);
10727 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
10730 // If it is a splat, check if the argument vector is another splat or a
10731 // build_vector with all scalar elements the same.
10732 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
10733 SDNode *V = N0.getNode();
10735 // If this is a bit convert that changes the element type of the vector but
10736 // not the number of vector elements, look through it. Be careful not to
10737 // look though conversions that change things like v4f32 to v2f64.
10738 if (V->getOpcode() == ISD::BITCAST) {
10739 SDValue ConvInput = V->getOperand(0);
10740 if (ConvInput.getValueType().isVector() &&
10741 ConvInput.getValueType().getVectorNumElements() == NumElts)
10742 V = ConvInput.getNode();
10745 if (V->getOpcode() == ISD::BUILD_VECTOR) {
10746 assert(V->getNumOperands() == NumElts &&
10747 "BUILD_VECTOR has wrong number of operands");
10749 bool AllSame = true;
10750 for (unsigned i = 0; i != NumElts; ++i) {
10751 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
10752 Base = V->getOperand(i);
10756 // Splat of <u, u, u, u>, return <u, u, u, u>
10757 if (!Base.getNode())
10759 for (unsigned i = 0; i != NumElts; ++i) {
10760 if (V->getOperand(i) != Base) {
10765 // Splat of <x, x, x, x>, return <x, x, x, x>
10771 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
10772 Level < AfterLegalizeVectorOps &&
10773 (N1.getOpcode() == ISD::UNDEF ||
10774 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
10775 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
10776 SDValue V = partitionShuffleOfConcats(N, DAG);
10782 // If this shuffle node is simply a swizzle of another shuffle node,
10783 // then try to simplify it.
10784 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
10785 N1.getOpcode() == ISD::UNDEF) {
10787 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
10789 // The incoming shuffle must be of the same type as the result of the
10790 // current shuffle.
10791 assert(OtherSV->getOperand(0).getValueType() == VT &&
10792 "Shuffle types don't match");
10794 SmallVector<int, 4> Mask;
10795 // Compute the combined shuffle mask.
10796 for (unsigned i = 0; i != NumElts; ++i) {
10797 int Idx = SVN->getMaskElt(i);
10798 assert(Idx < (int)NumElts && "Index references undef operand");
10799 // Next, this index comes from the first value, which is the incoming
10800 // shuffle. Adopt the incoming index.
10802 Idx = OtherSV->getMaskElt(Idx);
10803 Mask.push_back(Idx);
10806 // Check if all indices in Mask are Undef. In case, propagate Undef.
10807 bool isUndefMask = true;
10808 for (unsigned i = 0; i != NumElts && isUndefMask; ++i)
10809 isUndefMask &= Mask[i] < 0;
10812 return DAG.getUNDEF(VT);
10814 bool CommuteOperands = false;
10815 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) {
10816 // To be valid, the combine shuffle mask should only reference elements
10817 // from one of the two vectors in input to the inner shufflevector.
10818 bool IsValidMask = true;
10819 for (unsigned i = 0; i != NumElts && IsValidMask; ++i)
10820 // See if the combined mask only reference undefs or elements coming
10821 // from the first shufflevector operand.
10822 IsValidMask = Mask[i] < 0 || (unsigned)Mask[i] < NumElts;
10824 if (!IsValidMask) {
10825 IsValidMask = true;
10826 for (unsigned i = 0; i != NumElts && IsValidMask; ++i)
10827 // Check that all the elements come from the second shuffle operand.
10828 IsValidMask = Mask[i] < 0 || (unsigned)Mask[i] >= NumElts;
10829 CommuteOperands = IsValidMask;
10832 // Early exit if the combined shuffle mask is not valid.
10837 // See if this pair of shuffles can be safely folded according to either
10838 // of the following rules:
10839 // shuffle(shuffle(x, y), undef) -> x
10840 // shuffle(shuffle(x, undef), undef) -> x
10841 // shuffle(shuffle(x, y), undef) -> y
10842 bool IsIdentityMask = true;
10843 unsigned BaseMaskIndex = CommuteOperands ? NumElts : 0;
10844 for (unsigned i = 0; i != NumElts && IsIdentityMask; ++i) {
10849 // The combined shuffle must map each index to itself.
10850 IsIdentityMask = (unsigned)Mask[i] == i + BaseMaskIndex;
10853 if (IsIdentityMask) {
10854 if (CommuteOperands)
10855 // optimize shuffle(shuffle(x, y), undef) -> y.
10856 return OtherSV->getOperand(1);
10858 // optimize shuffle(shuffle(x, undef), undef) -> x
10859 // optimize shuffle(shuffle(x, y), undef) -> x
10860 return OtherSV->getOperand(0);
10863 // It may still be beneficial to combine the two shuffles if the
10864 // resulting shuffle is legal.
10865 if (TLI.isTypeLegal(VT)) {
10866 if (!CommuteOperands) {
10867 if (TLI.isShuffleMaskLegal(Mask, VT))
10868 // shuffle(shuffle(x, undef, M1), undef, M2) -> shuffle(x, undef, M3).
10869 // shuffle(shuffle(x, y, M1), undef, M2) -> shuffle(x, undef, M3)
10870 return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0), N1,
10873 // Compute the commuted shuffle mask.
10874 for (unsigned i = 0; i != NumElts; ++i) {
10878 else if (idx < (int)NumElts)
10879 Mask[i] = idx + NumElts;
10881 Mask[i] = idx - NumElts;
10884 if (TLI.isShuffleMaskLegal(Mask, VT))
10885 // shuffle(shuffle(x, y, M1), undef, M2) -> shuffle(y, undef, M3)
10886 return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(1), N1,
10892 // Canonicalize shuffles according to rules:
10893 // shuffle(A, shuffle(A, B)) -> shuffle(shuffle(A,B), A)
10894 // shuffle(B, shuffle(A, B)) -> shuffle(shuffle(A,B), B)
10895 // shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
10896 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && N0.getOpcode() != ISD::UNDEF &&
10897 N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
10898 TLI.isTypeLegal(VT)) {
10899 // The incoming shuffle must be of the same type as the result of the
10900 // current shuffle.
10901 assert(N1->getOperand(0).getValueType() == VT &&
10902 "Shuffle types don't match");
10904 SDValue SV0 = N1->getOperand(0);
10905 SDValue SV1 = N1->getOperand(1);
10906 bool HasSameOp0 = N0 == SV0;
10907 bool IsSV1Undef = SV1.getOpcode() == ISD::UNDEF;
10908 if (HasSameOp0 || IsSV1Undef || N0 == SV1)
10909 // Commute the operands of this shuffle so that next rule
10911 return DAG.getCommutedVectorShuffle(*SVN);
10914 // Try to fold according to rules:
10915 // shuffle(shuffle(A, B, M0), B, M1) -> shuffle(A, B, M2)
10916 // shuffle(shuffle(A, B, M0), A, M1) -> shuffle(A, B, M2)
10917 // shuffle(shuffle(A, Undef, M0), B, M1) -> shuffle(A, B, M2)
10918 // shuffle(shuffle(A, Undef, M0), A, M1) -> shuffle(A, Undef, M2)
10919 // Don't try to fold shuffles with illegal type.
10920 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
10921 N1.getOpcode() != ISD::UNDEF && TLI.isTypeLegal(VT)) {
10922 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
10924 // The incoming shuffle must be of the same type as the result of the
10925 // current shuffle.
10926 assert(OtherSV->getOperand(0).getValueType() == VT &&
10927 "Shuffle types don't match");
10929 SDValue SV0 = OtherSV->getOperand(0);
10930 SDValue SV1 = OtherSV->getOperand(1);
10931 bool HasSameOp0 = N1 == SV0;
10932 bool IsSV1Undef = SV1.getOpcode() == ISD::UNDEF;
10933 if (!HasSameOp0 && !IsSV1Undef && N1 != SV1)
10937 SmallVector<int, 4> Mask;
10938 // Compute the combined shuffle mask for a shuffle with SV0 as the first
10939 // operand, and SV1 as the second operand.
10940 for (unsigned i = 0; i != NumElts; ++i) {
10941 int Idx = SVN->getMaskElt(i);
10943 // Propagate Undef.
10944 Mask.push_back(Idx);
10948 if (Idx < (int)NumElts) {
10949 Idx = OtherSV->getMaskElt(Idx);
10950 if (IsSV1Undef && Idx >= (int) NumElts)
10951 Idx = -1; // Propagate Undef.
10953 Idx = HasSameOp0 ? Idx - NumElts : Idx;
10955 Mask.push_back(Idx);
10958 // Check if all indices in Mask are Undef. In case, propagate Undef.
10959 bool isUndefMask = true;
10960 for (unsigned i = 0; i != NumElts && isUndefMask; ++i)
10961 isUndefMask &= Mask[i] < 0;
10964 return DAG.getUNDEF(VT);
10966 // Avoid introducing shuffles with illegal mask.
10967 if (TLI.isShuffleMaskLegal(Mask, VT)) {
10969 // shuffle(shuffle(A, Undef, M0), B, M1) -> shuffle(A, B, M2)
10970 // shuffle(shuffle(A, Undef, M0), A, M1) -> shuffle(A, Undef, M2)
10971 return DAG.getVectorShuffle(VT, SDLoc(N), SV0, N1, &Mask[0]);
10972 return DAG.getVectorShuffle(VT, SDLoc(N), SV0, SV1, &Mask[0]);
10979 SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
10980 SDValue N0 = N->getOperand(0);
10981 SDValue N2 = N->getOperand(2);
10983 // If the input vector is a concatenation, and the insert replaces
10984 // one of the halves, we can optimize into a single concat_vectors.
10985 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
10986 N0->getNumOperands() == 2 && N2.getOpcode() == ISD::Constant) {
10987 APInt InsIdx = cast<ConstantSDNode>(N2)->getAPIntValue();
10988 EVT VT = N->getValueType(0);
10990 // Lower half: fold (insert_subvector (concat_vectors X, Y), Z) ->
10991 // (concat_vectors Z, Y)
10993 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
10994 N->getOperand(1), N0.getOperand(1));
10996 // Upper half: fold (insert_subvector (concat_vectors X, Y), Z) ->
10997 // (concat_vectors X, Z)
10998 if (InsIdx == VT.getVectorNumElements()/2)
10999 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
11000 N0.getOperand(0), N->getOperand(1));
11006 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
11007 /// an AND to a vector_shuffle with the destination vector and a zero vector.
11008 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
11009 /// vector_shuffle V, Zero, <0, 4, 2, 4>
11010 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
11011 EVT VT = N->getValueType(0);
11013 SDValue LHS = N->getOperand(0);
11014 SDValue RHS = N->getOperand(1);
11015 if (N->getOpcode() == ISD::AND) {
11016 if (RHS.getOpcode() == ISD::BITCAST)
11017 RHS = RHS.getOperand(0);
11018 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
11019 SmallVector<int, 8> Indices;
11020 unsigned NumElts = RHS.getNumOperands();
11021 for (unsigned i = 0; i != NumElts; ++i) {
11022 SDValue Elt = RHS.getOperand(i);
11023 if (!isa<ConstantSDNode>(Elt))
11026 if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
11027 Indices.push_back(i);
11028 else if (cast<ConstantSDNode>(Elt)->isNullValue())
11029 Indices.push_back(NumElts);
11034 // Let's see if the target supports this vector_shuffle.
11035 EVT RVT = RHS.getValueType();
11036 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
11039 // Return the new VECTOR_SHUFFLE node.
11040 EVT EltVT = RVT.getVectorElementType();
11041 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
11042 DAG.getConstant(0, EltVT));
11043 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), RVT, ZeroOps);
11044 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
11045 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
11046 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
11053 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
11054 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
11055 assert(N->getValueType(0).isVector() &&
11056 "SimplifyVBinOp only works on vectors!");
11058 SDValue LHS = N->getOperand(0);
11059 SDValue RHS = N->getOperand(1);
11060 SDValue Shuffle = XformToShuffleWithZero(N);
11061 if (Shuffle.getNode()) return Shuffle;
11063 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
11065 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
11066 RHS.getOpcode() == ISD::BUILD_VECTOR) {
11067 // Check if both vectors are constants. If not bail out.
11068 if (!(cast<BuildVectorSDNode>(LHS)->isConstant() &&
11069 cast<BuildVectorSDNode>(RHS)->isConstant()))
11072 SmallVector<SDValue, 8> Ops;
11073 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
11074 SDValue LHSOp = LHS.getOperand(i);
11075 SDValue RHSOp = RHS.getOperand(i);
11077 // Can't fold divide by zero.
11078 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
11079 N->getOpcode() == ISD::FDIV) {
11080 if ((RHSOp.getOpcode() == ISD::Constant &&
11081 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
11082 (RHSOp.getOpcode() == ISD::ConstantFP &&
11083 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
11087 EVT VT = LHSOp.getValueType();
11088 EVT RVT = RHSOp.getValueType();
11090 // Integer BUILD_VECTOR operands may have types larger than the element
11091 // size (e.g., when the element type is not legal). Prior to type
11092 // legalization, the types may not match between the two BUILD_VECTORS.
11093 // Truncate one of the operands to make them match.
11094 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
11095 RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, RHSOp);
11097 LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), RVT, LHSOp);
11101 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(LHS), VT,
11103 if (FoldOp.getOpcode() != ISD::UNDEF &&
11104 FoldOp.getOpcode() != ISD::Constant &&
11105 FoldOp.getOpcode() != ISD::ConstantFP)
11107 Ops.push_back(FoldOp);
11108 AddToWorklist(FoldOp.getNode());
11111 if (Ops.size() == LHS.getNumOperands())
11112 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), LHS.getValueType(), Ops);
11115 // Type legalization might introduce new shuffles in the DAG.
11116 // Fold (VBinOp (shuffle (A, Undef, Mask)), (shuffle (B, Undef, Mask)))
11117 // -> (shuffle (VBinOp (A, B)), Undef, Mask).
11118 if (LegalTypes && isa<ShuffleVectorSDNode>(LHS) &&
11119 isa<ShuffleVectorSDNode>(RHS) && LHS.hasOneUse() && RHS.hasOneUse() &&
11120 LHS.getOperand(1).getOpcode() == ISD::UNDEF &&
11121 RHS.getOperand(1).getOpcode() == ISD::UNDEF) {
11122 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(LHS);
11123 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(RHS);
11125 if (SVN0->getMask().equals(SVN1->getMask())) {
11126 EVT VT = N->getValueType(0);
11127 SDValue UndefVector = LHS.getOperand(1);
11128 SDValue NewBinOp = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
11129 LHS.getOperand(0), RHS.getOperand(0));
11130 AddUsersToWorklist(N);
11131 return DAG.getVectorShuffle(VT, SDLoc(N), NewBinOp, UndefVector,
11132 &SVN0->getMask()[0]);
11139 /// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG.
11140 SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) {
11141 assert(N->getValueType(0).isVector() &&
11142 "SimplifyVUnaryOp only works on vectors!");
11144 SDValue N0 = N->getOperand(0);
11146 if (N0.getOpcode() != ISD::BUILD_VECTOR)
11149 // Operand is a BUILD_VECTOR node, see if we can constant fold it.
11150 SmallVector<SDValue, 8> Ops;
11151 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
11152 SDValue Op = N0.getOperand(i);
11153 if (Op.getOpcode() != ISD::UNDEF &&
11154 Op.getOpcode() != ISD::ConstantFP)
11156 EVT EltVT = Op.getValueType();
11157 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(N0), EltVT, Op);
11158 if (FoldOp.getOpcode() != ISD::UNDEF &&
11159 FoldOp.getOpcode() != ISD::ConstantFP)
11161 Ops.push_back(FoldOp);
11162 AddToWorklist(FoldOp.getNode());
11165 if (Ops.size() != N0.getNumOperands())
11168 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N0.getValueType(), Ops);
11171 SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
11172 SDValue N1, SDValue N2){
11173 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
11175 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
11176 cast<CondCodeSDNode>(N0.getOperand(2))->get());
11178 // If we got a simplified select_cc node back from SimplifySelectCC, then
11179 // break it down into a new SETCC node, and a new SELECT node, and then return
11180 // the SELECT node, since we were called with a SELECT node.
11181 if (SCC.getNode()) {
11182 // Check to see if we got a select_cc back (to turn into setcc/select).
11183 // Otherwise, just return whatever node we got back, like fabs.
11184 if (SCC.getOpcode() == ISD::SELECT_CC) {
11185 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
11187 SCC.getOperand(0), SCC.getOperand(1),
11188 SCC.getOperand(4));
11189 AddToWorklist(SETCC.getNode());
11190 return DAG.getSelect(SDLoc(SCC), SCC.getValueType(), SETCC,
11191 SCC.getOperand(2), SCC.getOperand(3));
11199 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
11200 /// are the two values being selected between, see if we can simplify the
11201 /// select. Callers of this should assume that TheSelect is deleted if this
11202 /// returns true. As such, they should return the appropriate thing (e.g. the
11203 /// node) back to the top-level of the DAG combiner loop to avoid it being
11205 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
11208 // Cannot simplify select with vector condition
11209 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
11211 // If this is a select from two identical things, try to pull the operation
11212 // through the select.
11213 if (LHS.getOpcode() != RHS.getOpcode() ||
11214 !LHS.hasOneUse() || !RHS.hasOneUse())
11217 // If this is a load and the token chain is identical, replace the select
11218 // of two loads with a load through a select of the address to load from.
11219 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
11220 // constants have been dropped into the constant pool.
11221 if (LHS.getOpcode() == ISD::LOAD) {
11222 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
11223 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
11225 // Token chains must be identical.
11226 if (LHS.getOperand(0) != RHS.getOperand(0) ||
11227 // Do not let this transformation reduce the number of volatile loads.
11228 LLD->isVolatile() || RLD->isVolatile() ||
11229 // If this is an EXTLOAD, the VT's must match.
11230 LLD->getMemoryVT() != RLD->getMemoryVT() ||
11231 // If this is an EXTLOAD, the kind of extension must match.
11232 (LLD->getExtensionType() != RLD->getExtensionType() &&
11233 // The only exception is if one of the extensions is anyext.
11234 LLD->getExtensionType() != ISD::EXTLOAD &&
11235 RLD->getExtensionType() != ISD::EXTLOAD) ||
11236 // FIXME: this discards src value information. This is
11237 // over-conservative. It would be beneficial to be able to remember
11238 // both potential memory locations. Since we are discarding
11239 // src value info, don't do the transformation if the memory
11240 // locations are not in the default address space.
11241 LLD->getPointerInfo().getAddrSpace() != 0 ||
11242 RLD->getPointerInfo().getAddrSpace() != 0 ||
11243 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
11244 LLD->getBasePtr().getValueType()))
11247 // Check that the select condition doesn't reach either load. If so,
11248 // folding this will induce a cycle into the DAG. If not, this is safe to
11249 // xform, so create a select of the addresses.
11251 if (TheSelect->getOpcode() == ISD::SELECT) {
11252 SDNode *CondNode = TheSelect->getOperand(0).getNode();
11253 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
11254 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
11256 // The loads must not depend on one another.
11257 if (LLD->isPredecessorOf(RLD) ||
11258 RLD->isPredecessorOf(LLD))
11260 Addr = DAG.getSelect(SDLoc(TheSelect),
11261 LLD->getBasePtr().getValueType(),
11262 TheSelect->getOperand(0), LLD->getBasePtr(),
11263 RLD->getBasePtr());
11264 } else { // Otherwise SELECT_CC
11265 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
11266 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
11268 if ((LLD->hasAnyUseOfValue(1) &&
11269 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
11270 (RLD->hasAnyUseOfValue(1) &&
11271 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
11274 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect),
11275 LLD->getBasePtr().getValueType(),
11276 TheSelect->getOperand(0),
11277 TheSelect->getOperand(1),
11278 LLD->getBasePtr(), RLD->getBasePtr(),
11279 TheSelect->getOperand(4));
11283 // It is safe to replace the two loads if they have different alignments,
11284 // but the new load must be the minimum (most restrictive) alignment of the
11286 bool isInvariant = LLD->getAlignment() & RLD->getAlignment();
11287 unsigned Alignment = std::min(LLD->getAlignment(), RLD->getAlignment());
11288 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
11289 Load = DAG.getLoad(TheSelect->getValueType(0),
11291 // FIXME: Discards pointer and AA info.
11292 LLD->getChain(), Addr, MachinePointerInfo(),
11293 LLD->isVolatile(), LLD->isNonTemporal(),
11294 isInvariant, Alignment);
11296 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
11297 RLD->getExtensionType() : LLD->getExtensionType(),
11299 TheSelect->getValueType(0),
11300 // FIXME: Discards pointer and AA info.
11301 LLD->getChain(), Addr, MachinePointerInfo(),
11302 LLD->getMemoryVT(), LLD->isVolatile(),
11303 LLD->isNonTemporal(), isInvariant, Alignment);
11306 // Users of the select now use the result of the load.
11307 CombineTo(TheSelect, Load);
11309 // Users of the old loads now use the new load's chain. We know the
11310 // old-load value is dead now.
11311 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
11312 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
11319 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
11320 /// where 'cond' is the comparison specified by CC.
11321 SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
11322 SDValue N2, SDValue N3,
11323 ISD::CondCode CC, bool NotExtCompare) {
11324 // (x ? y : y) -> y.
11325 if (N2 == N3) return N2;
11327 EVT VT = N2.getValueType();
11328 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
11329 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
11330 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
11332 // Determine if the condition we're dealing with is constant
11333 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
11334 N0, N1, CC, DL, false);
11335 if (SCC.getNode()) AddToWorklist(SCC.getNode());
11336 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
11338 // fold select_cc true, x, y -> x
11339 if (SCCC && !SCCC->isNullValue())
11341 // fold select_cc false, x, y -> y
11342 if (SCCC && SCCC->isNullValue())
11345 // Check to see if we can simplify the select into an fabs node
11346 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
11347 // Allow either -0.0 or 0.0
11348 if (CFP->getValueAPF().isZero()) {
11349 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
11350 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
11351 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
11352 N2 == N3.getOperand(0))
11353 return DAG.getNode(ISD::FABS, DL, VT, N0);
11355 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
11356 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
11357 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
11358 N2.getOperand(0) == N3)
11359 return DAG.getNode(ISD::FABS, DL, VT, N3);
11363 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
11364 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
11365 // in it. This is a win when the constant is not otherwise available because
11366 // it replaces two constant pool loads with one. We only do this if the FP
11367 // type is known to be legal, because if it isn't, then we are before legalize
11368 // types an we want the other legalization to happen first (e.g. to avoid
11369 // messing with soft float) and if the ConstantFP is not legal, because if
11370 // it is legal, we may not need to store the FP constant in a constant pool.
11371 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
11372 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
11373 if (TLI.isTypeLegal(N2.getValueType()) &&
11374 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
11375 TargetLowering::Legal &&
11376 !TLI.isFPImmLegal(TV->getValueAPF(), TV->getValueType(0)) &&
11377 !TLI.isFPImmLegal(FV->getValueAPF(), FV->getValueType(0))) &&
11378 // If both constants have multiple uses, then we won't need to do an
11379 // extra load, they are likely around in registers for other users.
11380 (TV->hasOneUse() || FV->hasOneUse())) {
11381 Constant *Elts[] = {
11382 const_cast<ConstantFP*>(FV->getConstantFPValue()),
11383 const_cast<ConstantFP*>(TV->getConstantFPValue())
11385 Type *FPTy = Elts[0]->getType();
11386 const DataLayout &TD = *TLI.getDataLayout();
11388 // Create a ConstantArray of the two constants.
11389 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
11390 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
11391 TD.getPrefTypeAlignment(FPTy));
11392 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
11394 // Get the offsets to the 0 and 1 element of the array so that we can
11395 // select between them.
11396 SDValue Zero = DAG.getIntPtrConstant(0);
11397 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
11398 SDValue One = DAG.getIntPtrConstant(EltSize);
11400 SDValue Cond = DAG.getSetCC(DL,
11401 getSetCCResultType(N0.getValueType()),
11403 AddToWorklist(Cond.getNode());
11404 SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(),
11406 AddToWorklist(CstOffset.getNode());
11407 CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx,
11409 AddToWorklist(CPIdx.getNode());
11410 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
11411 MachinePointerInfo::getConstantPool(), false,
11412 false, false, Alignment);
11417 // Check to see if we can perform the "gzip trick", transforming
11418 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
11419 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
11420 (N1C->isNullValue() || // (a < 0) ? b : 0
11421 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
11422 EVT XType = N0.getValueType();
11423 EVT AType = N2.getValueType();
11424 if (XType.bitsGE(AType)) {
11425 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
11426 // single-bit constant.
11427 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
11428 unsigned ShCtV = N2C->getAPIntValue().logBase2();
11429 ShCtV = XType.getSizeInBits()-ShCtV-1;
11430 SDValue ShCt = DAG.getConstant(ShCtV,
11431 getShiftAmountTy(N0.getValueType()));
11432 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
11434 AddToWorklist(Shift.getNode());
11436 if (XType.bitsGT(AType)) {
11437 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
11438 AddToWorklist(Shift.getNode());
11441 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
11444 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
11446 DAG.getConstant(XType.getSizeInBits()-1,
11447 getShiftAmountTy(N0.getValueType())));
11448 AddToWorklist(Shift.getNode());
11450 if (XType.bitsGT(AType)) {
11451 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
11452 AddToWorklist(Shift.getNode());
11455 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
11459 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
11460 // where y is has a single bit set.
11461 // A plaintext description would be, we can turn the SELECT_CC into an AND
11462 // when the condition can be materialized as an all-ones register. Any
11463 // single bit-test can be materialized as an all-ones register with
11464 // shift-left and shift-right-arith.
11465 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
11466 N0->getValueType(0) == VT &&
11467 N1C && N1C->isNullValue() &&
11468 N2C && N2C->isNullValue()) {
11469 SDValue AndLHS = N0->getOperand(0);
11470 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
11471 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
11472 // Shift the tested bit over the sign bit.
11473 APInt AndMask = ConstAndRHS->getAPIntValue();
11475 DAG.getConstant(AndMask.countLeadingZeros(),
11476 getShiftAmountTy(AndLHS.getValueType()));
11477 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
11479 // Now arithmetic right shift it all the way over, so the result is either
11480 // all-ones, or zero.
11482 DAG.getConstant(AndMask.getBitWidth()-1,
11483 getShiftAmountTy(Shl.getValueType()));
11484 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
11486 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
11490 // fold select C, 16, 0 -> shl C, 4
11491 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
11492 TLI.getBooleanContents(N0.getValueType()) ==
11493 TargetLowering::ZeroOrOneBooleanContent) {
11495 // If the caller doesn't want us to simplify this into a zext of a compare,
11497 if (NotExtCompare && N2C->getAPIntValue() == 1)
11500 // Get a SetCC of the condition
11501 // NOTE: Don't create a SETCC if it's not legal on this target.
11502 if (!LegalOperations ||
11503 TLI.isOperationLegal(ISD::SETCC,
11504 LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) {
11506 // cast from setcc result type to select result type
11508 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
11510 if (N2.getValueType().bitsLT(SCC.getValueType()))
11511 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2),
11512 N2.getValueType());
11514 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
11515 N2.getValueType(), SCC);
11517 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
11518 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
11519 N2.getValueType(), SCC);
11522 AddToWorklist(SCC.getNode());
11523 AddToWorklist(Temp.getNode());
11525 if (N2C->getAPIntValue() == 1)
11528 // shl setcc result by log2 n2c
11529 return DAG.getNode(
11530 ISD::SHL, DL, N2.getValueType(), Temp,
11531 DAG.getConstant(N2C->getAPIntValue().logBase2(),
11532 getShiftAmountTy(Temp.getValueType())));
11536 // Check to see if this is the equivalent of setcc
11537 // FIXME: Turn all of these into setcc if setcc if setcc is legal
11538 // otherwise, go ahead with the folds.
11539 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
11540 EVT XType = N0.getValueType();
11541 if (!LegalOperations ||
11542 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) {
11543 SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC);
11544 if (Res.getValueType() != VT)
11545 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
11549 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
11550 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
11551 (!LegalOperations ||
11552 TLI.isOperationLegal(ISD::CTLZ, XType))) {
11553 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0);
11554 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
11555 DAG.getConstant(Log2_32(XType.getSizeInBits()),
11556 getShiftAmountTy(Ctlz.getValueType())));
11558 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
11559 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
11560 SDValue NegN0 = DAG.getNode(ISD::SUB, SDLoc(N0),
11561 XType, DAG.getConstant(0, XType), N0);
11562 SDValue NotN0 = DAG.getNOT(SDLoc(N0), N0, XType);
11563 return DAG.getNode(ISD::SRL, DL, XType,
11564 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
11565 DAG.getConstant(XType.getSizeInBits()-1,
11566 getShiftAmountTy(XType)));
11568 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
11569 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
11570 SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0,
11571 DAG.getConstant(XType.getSizeInBits()-1,
11572 getShiftAmountTy(N0.getValueType())));
11573 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
11577 // Check to see if this is an integer abs.
11578 // select_cc setg[te] X, 0, X, -X ->
11579 // select_cc setgt X, -1, X, -X ->
11580 // select_cc setl[te] X, 0, -X, X ->
11581 // select_cc setlt X, 1, -X, X ->
11582 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
11584 ConstantSDNode *SubC = nullptr;
11585 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
11586 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
11587 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
11588 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
11589 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
11590 (N1C->isOne() && CC == ISD::SETLT)) &&
11591 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
11592 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
11594 EVT XType = N0.getValueType();
11595 if (SubC && SubC->isNullValue() && XType.isInteger()) {
11596 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType,
11598 DAG.getConstant(XType.getSizeInBits()-1,
11599 getShiftAmountTy(N0.getValueType())));
11600 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0),
11602 AddToWorklist(Shift.getNode());
11603 AddToWorklist(Add.getNode());
11604 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
11611 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
11612 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
11613 SDValue N1, ISD::CondCode Cond,
11614 SDLoc DL, bool foldBooleans) {
11615 TargetLowering::DAGCombinerInfo
11616 DagCombineInfo(DAG, Level, false, this);
11617 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
11620 /// BuildSDIV - Given an ISD::SDIV node expressing a divide by constant, return
11621 /// a DAG expression to select that will generate the same value by multiplying
11622 /// by a magic number. See:
11623 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
11624 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
11625 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
11629 // Avoid division by zero.
11630 if (!C->getAPIntValue())
11633 std::vector<SDNode*> Built;
11635 TLI.BuildSDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
11637 for (SDNode *N : Built)
11642 /// BuildSDIVPow2 - Given an ISD::SDIV node expressing a divide by constant
11643 /// power of 2, return a DAG expression to select that will generate the same
11644 /// value by right shifting.
11645 SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) {
11646 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
11650 // Avoid division by zero.
11651 if (!C->getAPIntValue())
11654 std::vector<SDNode *> Built;
11655 SDValue S = TLI.BuildSDIVPow2(N, C->getAPIntValue(), DAG, &Built);
11657 for (SDNode *N : Built)
11662 /// BuildUDIV - Given an ISD::UDIV node expressing a divide by constant,
11663 /// return a DAG expression to select that will generate the same value by
11664 /// multiplying by a magic number. See:
11665 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
11666 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
11667 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
11671 // Avoid division by zero.
11672 if (!C->getAPIntValue())
11675 std::vector<SDNode*> Built;
11677 TLI.BuildUDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
11679 for (SDNode *N : Built)
11684 /// FindBaseOffset - Return true if base is a frame index, which is known not
11685 // to alias with anything but itself. Provides base object and offset as
11687 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
11688 const GlobalValue *&GV, const void *&CV) {
11689 // Assume it is a primitive operation.
11690 Base = Ptr; Offset = 0; GV = nullptr; CV = nullptr;
11692 // If it's an adding a simple constant then integrate the offset.
11693 if (Base.getOpcode() == ISD::ADD) {
11694 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
11695 Base = Base.getOperand(0);
11696 Offset += C->getZExtValue();
11700 // Return the underlying GlobalValue, and update the Offset. Return false
11701 // for GlobalAddressSDNode since the same GlobalAddress may be represented
11702 // by multiple nodes with different offsets.
11703 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
11704 GV = G->getGlobal();
11705 Offset += G->getOffset();
11709 // Return the underlying Constant value, and update the Offset. Return false
11710 // for ConstantSDNodes since the same constant pool entry may be represented
11711 // by multiple nodes with different offsets.
11712 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
11713 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
11714 : (const void *)C->getConstVal();
11715 Offset += C->getOffset();
11718 // If it's any of the following then it can't alias with anything but itself.
11719 return isa<FrameIndexSDNode>(Base);
11722 /// isAlias - Return true if there is any possibility that the two addresses
11724 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
11725 // If they are the same then they must be aliases.
11726 if (Op0->getBasePtr() == Op1->getBasePtr()) return true;
11728 // If they are both volatile then they cannot be reordered.
11729 if (Op0->isVolatile() && Op1->isVolatile()) return true;
11731 // Gather base node and offset information.
11732 SDValue Base1, Base2;
11733 int64_t Offset1, Offset2;
11734 const GlobalValue *GV1, *GV2;
11735 const void *CV1, *CV2;
11736 bool isFrameIndex1 = FindBaseOffset(Op0->getBasePtr(),
11737 Base1, Offset1, GV1, CV1);
11738 bool isFrameIndex2 = FindBaseOffset(Op1->getBasePtr(),
11739 Base2, Offset2, GV2, CV2);
11741 // If they have a same base address then check to see if they overlap.
11742 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
11743 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
11744 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
11746 // It is possible for different frame indices to alias each other, mostly
11747 // when tail call optimization reuses return address slots for arguments.
11748 // To catch this case, look up the actual index of frame indices to compute
11749 // the real alias relationship.
11750 if (isFrameIndex1 && isFrameIndex2) {
11751 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
11752 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
11753 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
11754 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
11755 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
11758 // Otherwise, if we know what the bases are, and they aren't identical, then
11759 // we know they cannot alias.
11760 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
11763 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
11764 // compared to the size and offset of the access, we may be able to prove they
11765 // do not alias. This check is conservative for now to catch cases created by
11766 // splitting vector types.
11767 if ((Op0->getOriginalAlignment() == Op1->getOriginalAlignment()) &&
11768 (Op0->getSrcValueOffset() != Op1->getSrcValueOffset()) &&
11769 (Op0->getMemoryVT().getSizeInBits() >> 3 ==
11770 Op1->getMemoryVT().getSizeInBits() >> 3) &&
11771 (Op0->getOriginalAlignment() > Op0->getMemoryVT().getSizeInBits()) >> 3) {
11772 int64_t OffAlign1 = Op0->getSrcValueOffset() % Op0->getOriginalAlignment();
11773 int64_t OffAlign2 = Op1->getSrcValueOffset() % Op1->getOriginalAlignment();
11775 // There is no overlap between these relatively aligned accesses of similar
11776 // size, return no alias.
11777 if ((OffAlign1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign2 ||
11778 (OffAlign2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign1)
11782 bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0 ? CombinerGlobalAA :
11783 TLI.getTargetMachine().getSubtarget<TargetSubtargetInfo>().useAA();
11785 if (CombinerAAOnlyFunc.getNumOccurrences() &&
11786 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
11790 Op0->getMemOperand()->getValue() && Op1->getMemOperand()->getValue()) {
11791 // Use alias analysis information.
11792 int64_t MinOffset = std::min(Op0->getSrcValueOffset(),
11793 Op1->getSrcValueOffset());
11794 int64_t Overlap1 = (Op0->getMemoryVT().getSizeInBits() >> 3) +
11795 Op0->getSrcValueOffset() - MinOffset;
11796 int64_t Overlap2 = (Op1->getMemoryVT().getSizeInBits() >> 3) +
11797 Op1->getSrcValueOffset() - MinOffset;
11798 AliasAnalysis::AliasResult AAResult =
11799 AA.alias(AliasAnalysis::Location(Op0->getMemOperand()->getValue(),
11801 UseTBAA ? Op0->getAAInfo() : AAMDNodes()),
11802 AliasAnalysis::Location(Op1->getMemOperand()->getValue(),
11804 UseTBAA ? Op1->getAAInfo() : AAMDNodes()));
11805 if (AAResult == AliasAnalysis::NoAlias)
11809 // Otherwise we have to assume they alias.
11813 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
11814 /// looking for aliasing nodes and adding them to the Aliases vector.
11815 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
11816 SmallVectorImpl<SDValue> &Aliases) {
11817 SmallVector<SDValue, 8> Chains; // List of chains to visit.
11818 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
11820 // Get alias information for node.
11821 bool IsLoad = isa<LoadSDNode>(N) && !cast<LSBaseSDNode>(N)->isVolatile();
11824 Chains.push_back(OriginalChain);
11825 unsigned Depth = 0;
11827 // Look at each chain and determine if it is an alias. If so, add it to the
11828 // aliases list. If not, then continue up the chain looking for the next
11830 while (!Chains.empty()) {
11831 SDValue Chain = Chains.back();
11834 // For TokenFactor nodes, look at each operand and only continue up the
11835 // chain until we find two aliases. If we've seen two aliases, assume we'll
11836 // find more and revert to original chain since the xform is unlikely to be
11839 // FIXME: The depth check could be made to return the last non-aliasing
11840 // chain we found before we hit a tokenfactor rather than the original
11842 if (Depth > 6 || Aliases.size() == 2) {
11844 Aliases.push_back(OriginalChain);
11848 // Don't bother if we've been before.
11849 if (!Visited.insert(Chain.getNode()))
11852 switch (Chain.getOpcode()) {
11853 case ISD::EntryToken:
11854 // Entry token is ideal chain operand, but handled in FindBetterChain.
11859 // Get alias information for Chain.
11860 bool IsOpLoad = isa<LoadSDNode>(Chain.getNode()) &&
11861 !cast<LSBaseSDNode>(Chain.getNode())->isVolatile();
11863 // If chain is alias then stop here.
11864 if (!(IsLoad && IsOpLoad) &&
11865 isAlias(cast<LSBaseSDNode>(N), cast<LSBaseSDNode>(Chain.getNode()))) {
11866 Aliases.push_back(Chain);
11868 // Look further up the chain.
11869 Chains.push_back(Chain.getOperand(0));
11875 case ISD::TokenFactor:
11876 // We have to check each of the operands of the token factor for "small"
11877 // token factors, so we queue them up. Adding the operands to the queue
11878 // (stack) in reverse order maintains the original order and increases the
11879 // likelihood that getNode will find a matching token factor (CSE.)
11880 if (Chain.getNumOperands() > 16) {
11881 Aliases.push_back(Chain);
11884 for (unsigned n = Chain.getNumOperands(); n;)
11885 Chains.push_back(Chain.getOperand(--n));
11890 // For all other instructions we will just have to take what we can get.
11891 Aliases.push_back(Chain);
11896 // We need to be careful here to also search for aliases through the
11897 // value operand of a store, etc. Consider the following situation:
11899 // L1 = load Token1, %52
11900 // S1 = store Token1, L1, %51
11901 // L2 = load Token1, %52+8
11902 // S2 = store Token1, L2, %51+8
11903 // Token2 = Token(S1, S2)
11904 // L3 = load Token2, %53
11905 // S3 = store Token2, L3, %52
11906 // L4 = load Token2, %53+8
11907 // S4 = store Token2, L4, %52+8
11908 // If we search for aliases of S3 (which loads address %52), and we look
11909 // only through the chain, then we'll miss the trivial dependence on L1
11910 // (which also loads from %52). We then might change all loads and
11911 // stores to use Token1 as their chain operand, which could result in
11912 // copying %53 into %52 before copying %52 into %51 (which should
11915 // The problem is, however, that searching for such data dependencies
11916 // can become expensive, and the cost is not directly related to the
11917 // chain depth. Instead, we'll rule out such configurations here by
11918 // insisting that we've visited all chain users (except for users
11919 // of the original chain, which is not necessary). When doing this,
11920 // we need to look through nodes we don't care about (otherwise, things
11921 // like register copies will interfere with trivial cases).
11923 SmallVector<const SDNode *, 16> Worklist;
11924 for (const SDNode *N : Visited)
11925 if (N != OriginalChain.getNode())
11926 Worklist.push_back(N);
11928 while (!Worklist.empty()) {
11929 const SDNode *M = Worklist.pop_back_val();
11931 // We have already visited M, and want to make sure we've visited any uses
11932 // of M that we care about. For uses that we've not visisted, and don't
11933 // care about, queue them to the worklist.
11935 for (SDNode::use_iterator UI = M->use_begin(),
11936 UIE = M->use_end(); UI != UIE; ++UI)
11937 if (UI.getUse().getValueType() == MVT::Other && Visited.insert(*UI)) {
11938 if (isa<MemIntrinsicSDNode>(*UI) || isa<MemSDNode>(*UI)) {
11939 // We've not visited this use, and we care about it (it could have an
11940 // ordering dependency with the original node).
11942 Aliases.push_back(OriginalChain);
11946 // We've not visited this use, but we don't care about it. Mark it as
11947 // visited and enqueue it to the worklist.
11948 Worklist.push_back(*UI);
11953 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
11954 /// for a better chain (aliasing node.)
11955 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
11956 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
11958 // Accumulate all the aliases to this node.
11959 GatherAllAliases(N, OldChain, Aliases);
11961 // If no operands then chain to entry token.
11962 if (Aliases.size() == 0)
11963 return DAG.getEntryNode();
11965 // If a single operand then chain to it. We don't need to revisit it.
11966 if (Aliases.size() == 1)
11969 // Construct a custom tailored token factor.
11970 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Aliases);
11973 // SelectionDAG::Combine - This is the entry point for the file.
11975 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
11976 CodeGenOpt::Level OptLevel) {
11977 /// run - This is the main entry point to this class.
11979 DAGCombiner(*this, AA, OptLevel).Run(Level);