1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/Statistic.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
40 STATISTIC(NodesCombined , "Number of dag nodes combined");
41 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
42 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
43 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
44 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
48 CombinerAA("combiner-alias-analysis", cl::Hidden,
49 cl::desc("Turn on alias analysis during testing"));
52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
53 cl::desc("Include global information in alias analysis"));
55 //------------------------------ DAGCombiner ---------------------------------//
59 const TargetLowering &TLI;
61 CodeGenOpt::Level OptLevel;
65 // Worklist of all of the nodes that need to be simplified.
67 // This has the semantics that when adding to the worklist,
68 // the item added must be next to be processed. It should
69 // also only appear once. The naive approach to this takes
72 // To reduce the insert/remove time to logarithmic, we use
73 // a set and a vector to maintain our worklist.
75 // The set contains the items on the worklist, but does not
76 // maintain the order they should be visited.
78 // The vector maintains the order nodes should be visited, but may
79 // contain duplicate or removed nodes. When choosing a node to
80 // visit, we pop off the order stack until we find an item that is
81 // also in the contents set. All operations are O(log N).
82 SmallPtrSet<SDNode*, 64> WorkListContents;
83 std::vector<SDNode*> WorkListOrder;
85 // AA - Used for DAG load/store alias analysis.
88 /// AddUsersToWorkList - When an instruction is simplified, add all users of
89 /// the instruction to the work lists because they might get more simplified
92 void AddUsersToWorkList(SDNode *N) {
93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
98 /// visit - call the node-specific routine that knows how to fold each
99 /// particular type of node.
100 SDValue visit(SDNode *N);
103 /// AddToWorkList - Add to the work list making sure its instance is at the
104 /// back (next to be processed.)
105 void AddToWorkList(SDNode *N) {
106 WorkListContents.insert(N);
107 WorkListOrder.push_back(N);
110 /// removeFromWorkList - remove all instances of N from the worklist.
112 void removeFromWorkList(SDNode *N) {
113 WorkListContents.erase(N);
116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
120 return CombineTo(N, &Res, 1, AddTo);
123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
125 SDValue To[] = { Res0, Res1 };
126 return CombineTo(N, To, 2, AddTo);
129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
133 /// SimplifyDemandedBits - Check the specified integer node value to see if
134 /// it can be simplified or if things it uses can be simplified by bit
135 /// propagation. If so, return true.
136 bool SimplifyDemandedBits(SDValue Op) {
137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
138 APInt Demanded = APInt::getAllOnesValue(BitWidth);
139 return SimplifyDemandedBits(Op, Demanded);
142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
144 bool CombineToPreIndexedLoadStore(SDNode *N);
145 bool CombineToPostIndexedLoadStore(SDNode *N);
147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
151 SDValue PromoteIntBinOp(SDValue Op);
152 SDValue PromoteIntShiftOp(SDValue Op);
153 SDValue PromoteExtend(SDValue Op);
154 bool PromoteLoad(SDValue Op);
156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
158 ISD::NodeType ExtType);
160 /// combine - call the node-specific routine that knows how to fold each
161 /// particular type of node. If that doesn't do anything, try the
162 /// target-specific DAG combines.
163 SDValue combine(SDNode *N);
165 // Visitation implementation - Implement dag node combining for different
166 // node types. The semantics are as follows:
168 // SDValue.getNode() == 0 - No change was made
169 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
170 // otherwise - N should be replaced by the returned Operand.
172 SDValue visitTokenFactor(SDNode *N);
173 SDValue visitMERGE_VALUES(SDNode *N);
174 SDValue visitADD(SDNode *N);
175 SDValue visitSUB(SDNode *N);
176 SDValue visitADDC(SDNode *N);
177 SDValue visitSUBC(SDNode *N);
178 SDValue visitADDE(SDNode *N);
179 SDValue visitSUBE(SDNode *N);
180 SDValue visitMUL(SDNode *N);
181 SDValue visitSDIV(SDNode *N);
182 SDValue visitUDIV(SDNode *N);
183 SDValue visitSREM(SDNode *N);
184 SDValue visitUREM(SDNode *N);
185 SDValue visitMULHU(SDNode *N);
186 SDValue visitMULHS(SDNode *N);
187 SDValue visitSMUL_LOHI(SDNode *N);
188 SDValue visitUMUL_LOHI(SDNode *N);
189 SDValue visitSMULO(SDNode *N);
190 SDValue visitUMULO(SDNode *N);
191 SDValue visitSDIVREM(SDNode *N);
192 SDValue visitUDIVREM(SDNode *N);
193 SDValue visitAND(SDNode *N);
194 SDValue visitOR(SDNode *N);
195 SDValue visitXOR(SDNode *N);
196 SDValue SimplifyVBinOp(SDNode *N);
197 SDValue visitSHL(SDNode *N);
198 SDValue visitSRA(SDNode *N);
199 SDValue visitSRL(SDNode *N);
200 SDValue visitCTLZ(SDNode *N);
201 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
202 SDValue visitCTTZ(SDNode *N);
203 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
204 SDValue visitCTPOP(SDNode *N);
205 SDValue visitSELECT(SDNode *N);
206 SDValue visitSELECT_CC(SDNode *N);
207 SDValue visitSETCC(SDNode *N);
208 SDValue visitSIGN_EXTEND(SDNode *N);
209 SDValue visitZERO_EXTEND(SDNode *N);
210 SDValue visitANY_EXTEND(SDNode *N);
211 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
212 SDValue visitTRUNCATE(SDNode *N);
213 SDValue visitBITCAST(SDNode *N);
214 SDValue visitBUILD_PAIR(SDNode *N);
215 SDValue visitFADD(SDNode *N);
216 SDValue visitFSUB(SDNode *N);
217 SDValue visitFMUL(SDNode *N);
218 SDValue visitFDIV(SDNode *N);
219 SDValue visitFREM(SDNode *N);
220 SDValue visitFCOPYSIGN(SDNode *N);
221 SDValue visitSINT_TO_FP(SDNode *N);
222 SDValue visitUINT_TO_FP(SDNode *N);
223 SDValue visitFP_TO_SINT(SDNode *N);
224 SDValue visitFP_TO_UINT(SDNode *N);
225 SDValue visitFP_ROUND(SDNode *N);
226 SDValue visitFP_ROUND_INREG(SDNode *N);
227 SDValue visitFP_EXTEND(SDNode *N);
228 SDValue visitFNEG(SDNode *N);
229 SDValue visitFABS(SDNode *N);
230 SDValue visitBRCOND(SDNode *N);
231 SDValue visitBR_CC(SDNode *N);
232 SDValue visitLOAD(SDNode *N);
233 SDValue visitSTORE(SDNode *N);
234 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
235 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
236 SDValue visitBUILD_VECTOR(SDNode *N);
237 SDValue visitCONCAT_VECTORS(SDNode *N);
238 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
239 SDValue visitVECTOR_SHUFFLE(SDNode *N);
240 SDValue visitMEMBARRIER(SDNode *N);
242 SDValue XformToShuffleWithZero(SDNode *N);
243 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
245 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
247 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
248 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
249 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
250 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
251 SDValue N3, ISD::CondCode CC,
252 bool NotExtCompare = false);
253 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
254 DebugLoc DL, bool foldBooleans = true);
255 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
257 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
258 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
259 SDValue BuildSDIV(SDNode *N);
260 SDValue BuildUDIV(SDNode *N);
261 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
262 bool DemandHighBits = true);
263 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
264 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
265 SDValue ReduceLoadWidth(SDNode *N);
266 SDValue ReduceLoadOpStoreWidth(SDNode *N);
267 SDValue TransformFPLoadStorePair(SDNode *N);
269 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
271 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
272 /// looking for aliasing nodes and adding them to the Aliases vector.
273 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
274 SmallVector<SDValue, 8> &Aliases);
276 /// isAlias - Return true if there is any possibility that the two addresses
278 bool isAlias(SDValue Ptr1, int64_t Size1,
279 const Value *SrcValue1, int SrcValueOffset1,
280 unsigned SrcValueAlign1,
281 const MDNode *TBAAInfo1,
282 SDValue Ptr2, int64_t Size2,
283 const Value *SrcValue2, int SrcValueOffset2,
284 unsigned SrcValueAlign2,
285 const MDNode *TBAAInfo2) const;
287 /// FindAliasInfo - Extracts the relevant alias information from the memory
288 /// node. Returns true if the operand was a load.
289 bool FindAliasInfo(SDNode *N,
290 SDValue &Ptr, int64_t &Size,
291 const Value *&SrcValue, int &SrcValueOffset,
292 unsigned &SrcValueAlignment,
293 const MDNode *&TBAAInfo) const;
295 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
296 /// looking for a better chain (aliasing node.)
297 SDValue FindBetterChain(SDNode *N, SDValue Chain);
300 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
301 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
302 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
304 /// Run - runs the dag combiner on all nodes in the work list
305 void Run(CombineLevel AtLevel);
307 SelectionDAG &getDAG() const { return DAG; }
309 /// getShiftAmountTy - Returns a type large enough to hold any valid
310 /// shift amount - before type legalization these can be huge.
311 EVT getShiftAmountTy(EVT LHSTy) {
312 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
315 /// isTypeLegal - This method returns true if we are running before type
316 /// legalization or if the specified VT is legal.
317 bool isTypeLegal(const EVT &VT) {
318 if (!LegalTypes) return true;
319 return TLI.isTypeLegal(VT);
326 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
327 /// nodes from the worklist.
328 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
331 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
333 virtual void NodeDeleted(SDNode *N, SDNode *E) {
334 DC.removeFromWorkList(N);
337 virtual void NodeUpdated(SDNode *N) {
343 //===----------------------------------------------------------------------===//
344 // TargetLowering::DAGCombinerInfo implementation
345 //===----------------------------------------------------------------------===//
347 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
348 ((DAGCombiner*)DC)->AddToWorkList(N);
351 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
352 ((DAGCombiner*)DC)->removeFromWorkList(N);
355 SDValue TargetLowering::DAGCombinerInfo::
356 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
357 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
360 SDValue TargetLowering::DAGCombinerInfo::
361 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
362 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
366 SDValue TargetLowering::DAGCombinerInfo::
367 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
368 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
371 void TargetLowering::DAGCombinerInfo::
372 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
373 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
376 //===----------------------------------------------------------------------===//
378 //===----------------------------------------------------------------------===//
380 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
381 /// specified expression for the same cost as the expression itself, or 2 if we
382 /// can compute the negated form more cheaply than the expression itself.
383 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
384 const TargetOptions *Options,
385 unsigned Depth = 0) {
386 // No compile time optimizations on this type.
387 if (Op.getValueType() == MVT::ppcf128)
390 // fneg is removable even if it has multiple uses.
391 if (Op.getOpcode() == ISD::FNEG) return 2;
393 // Don't allow anything with multiple uses.
394 if (!Op.hasOneUse()) return 0;
396 // Don't recurse exponentially.
397 if (Depth > 6) return 0;
399 switch (Op.getOpcode()) {
400 default: return false;
401 case ISD::ConstantFP:
402 // Don't invert constant FP values after legalize. The negated constant
403 // isn't necessarily legal.
404 return LegalOperations ? 0 : 1;
406 // FIXME: determine better conditions for this xform.
407 if (!Options->UnsafeFPMath) return 0;
409 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
410 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Options,
413 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
414 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Options,
417 // We can't turn -(A-B) into B-A when we honor signed zeros.
418 if (!Options->UnsafeFPMath) return 0;
420 // fold (fneg (fsub A, B)) -> (fsub B, A)
425 if (Options->HonorSignDependentRoundingFPMath()) return 0;
427 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
428 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Options,
432 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Options,
438 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Options,
443 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
444 /// returns the newly negated expression.
445 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
446 bool LegalOperations, unsigned Depth = 0) {
447 // fneg is removable even if it has multiple uses.
448 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
450 // Don't allow anything with multiple uses.
451 assert(Op.hasOneUse() && "Unknown reuse!");
453 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
454 switch (Op.getOpcode()) {
455 default: llvm_unreachable("Unknown code");
456 case ISD::ConstantFP: {
457 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
459 return DAG.getConstantFP(V, Op.getValueType());
462 // FIXME: determine better conditions for this xform.
463 assert(DAG.getTarget().Options.UnsafeFPMath);
465 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
466 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
467 &DAG.getTarget().Options, Depth+1))
468 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
469 GetNegatedExpression(Op.getOperand(0), DAG,
470 LegalOperations, Depth+1),
472 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
473 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
474 GetNegatedExpression(Op.getOperand(1), DAG,
475 LegalOperations, Depth+1),
478 // We can't turn -(A-B) into B-A when we honor signed zeros.
479 assert(DAG.getTarget().Options.UnsafeFPMath);
481 // fold (fneg (fsub 0, B)) -> B
482 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
483 if (N0CFP->getValueAPF().isZero())
484 return Op.getOperand(1);
486 // fold (fneg (fsub A, B)) -> (fsub B, A)
487 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
488 Op.getOperand(1), Op.getOperand(0));
492 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath());
494 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
495 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
496 &DAG.getTarget().Options, Depth+1))
497 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
498 GetNegatedExpression(Op.getOperand(0), DAG,
499 LegalOperations, Depth+1),
502 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
503 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
505 GetNegatedExpression(Op.getOperand(1), DAG,
506 LegalOperations, Depth+1));
510 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
511 GetNegatedExpression(Op.getOperand(0), DAG,
512 LegalOperations, Depth+1));
514 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
515 GetNegatedExpression(Op.getOperand(0), DAG,
516 LegalOperations, Depth+1),
522 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
523 // that selects between the values 1 and 0, making it equivalent to a setcc.
524 // Also, set the incoming LHS, RHS, and CC references to the appropriate
525 // nodes based on the type of node we are checking. This simplifies life a
526 // bit for the callers.
527 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
529 if (N.getOpcode() == ISD::SETCC) {
530 LHS = N.getOperand(0);
531 RHS = N.getOperand(1);
532 CC = N.getOperand(2);
535 if (N.getOpcode() == ISD::SELECT_CC &&
536 N.getOperand(2).getOpcode() == ISD::Constant &&
537 N.getOperand(3).getOpcode() == ISD::Constant &&
538 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
539 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
540 LHS = N.getOperand(0);
541 RHS = N.getOperand(1);
542 CC = N.getOperand(4);
548 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
549 // one use. If this is true, it allows the users to invert the operation for
550 // free when it is profitable to do so.
551 static bool isOneUseSetCC(SDValue N) {
553 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
558 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
559 SDValue N0, SDValue N1) {
560 EVT VT = N0.getValueType();
561 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
562 if (isa<ConstantSDNode>(N1)) {
563 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
565 DAG.FoldConstantArithmetic(Opc, VT,
566 cast<ConstantSDNode>(N0.getOperand(1)),
567 cast<ConstantSDNode>(N1));
568 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
570 if (N0.hasOneUse()) {
571 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
572 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
573 N0.getOperand(0), N1);
574 AddToWorkList(OpNode.getNode());
575 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
579 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
580 if (isa<ConstantSDNode>(N0)) {
581 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
583 DAG.FoldConstantArithmetic(Opc, VT,
584 cast<ConstantSDNode>(N1.getOperand(1)),
585 cast<ConstantSDNode>(N0));
586 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
588 if (N1.hasOneUse()) {
589 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
590 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
591 N1.getOperand(0), N0);
592 AddToWorkList(OpNode.getNode());
593 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
600 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
602 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
604 DEBUG(dbgs() << "\nReplacing.1 ";
606 dbgs() << "\nWith: ";
607 To[0].getNode()->dump(&DAG);
608 dbgs() << " and " << NumTo-1 << " other values\n";
609 for (unsigned i = 0, e = NumTo; i != e; ++i)
610 assert((!To[i].getNode() ||
611 N->getValueType(i) == To[i].getValueType()) &&
612 "Cannot combine value to value of different type!"));
613 WorkListRemover DeadNodes(*this);
614 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
617 // Push the new nodes and any users onto the worklist
618 for (unsigned i = 0, e = NumTo; i != e; ++i) {
619 if (To[i].getNode()) {
620 AddToWorkList(To[i].getNode());
621 AddUsersToWorkList(To[i].getNode());
626 // Finally, if the node is now dead, remove it from the graph. The node
627 // may not be dead if the replacement process recursively simplified to
628 // something else needing this node.
629 if (N->use_empty()) {
630 // Nodes can be reintroduced into the worklist. Make sure we do not
631 // process a node that has been replaced.
632 removeFromWorkList(N);
634 // Finally, since the node is now dead, remove it from the graph.
637 return SDValue(N, 0);
641 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
642 // Replace all uses. If any nodes become isomorphic to other nodes and
643 // are deleted, make sure to remove them from our worklist.
644 WorkListRemover DeadNodes(*this);
645 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
647 // Push the new node and any (possibly new) users onto the worklist.
648 AddToWorkList(TLO.New.getNode());
649 AddUsersToWorkList(TLO.New.getNode());
651 // Finally, if the node is now dead, remove it from the graph. The node
652 // may not be dead if the replacement process recursively simplified to
653 // something else needing this node.
654 if (TLO.Old.getNode()->use_empty()) {
655 removeFromWorkList(TLO.Old.getNode());
657 // If the operands of this node are only used by the node, they will now
658 // be dead. Make sure to visit them first to delete dead nodes early.
659 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
660 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
661 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
663 DAG.DeleteNode(TLO.Old.getNode());
667 /// SimplifyDemandedBits - Check the specified integer node value to see if
668 /// it can be simplified or if things it uses can be simplified by bit
669 /// propagation. If so, return true.
670 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
671 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
672 APInt KnownZero, KnownOne;
673 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
677 AddToWorkList(Op.getNode());
679 // Replace the old value with the new one.
681 DEBUG(dbgs() << "\nReplacing.2 ";
682 TLO.Old.getNode()->dump(&DAG);
683 dbgs() << "\nWith: ";
684 TLO.New.getNode()->dump(&DAG);
687 CommitTargetLoweringOpt(TLO);
691 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
692 DebugLoc dl = Load->getDebugLoc();
693 EVT VT = Load->getValueType(0);
694 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
696 DEBUG(dbgs() << "\nReplacing.9 ";
698 dbgs() << "\nWith: ";
699 Trunc.getNode()->dump(&DAG);
701 WorkListRemover DeadNodes(*this);
702 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
703 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
705 removeFromWorkList(Load);
706 DAG.DeleteNode(Load);
707 AddToWorkList(Trunc.getNode());
710 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
712 DebugLoc dl = Op.getDebugLoc();
713 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
714 EVT MemVT = LD->getMemoryVT();
715 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
716 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
718 : LD->getExtensionType();
720 return DAG.getExtLoad(ExtType, dl, PVT,
721 LD->getChain(), LD->getBasePtr(),
722 LD->getPointerInfo(),
723 MemVT, LD->isVolatile(),
724 LD->isNonTemporal(), LD->getAlignment());
727 unsigned Opc = Op.getOpcode();
730 case ISD::AssertSext:
731 return DAG.getNode(ISD::AssertSext, dl, PVT,
732 SExtPromoteOperand(Op.getOperand(0), PVT),
734 case ISD::AssertZext:
735 return DAG.getNode(ISD::AssertZext, dl, PVT,
736 ZExtPromoteOperand(Op.getOperand(0), PVT),
738 case ISD::Constant: {
740 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
741 return DAG.getNode(ExtOpc, dl, PVT, Op);
745 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
747 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
750 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
751 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
753 EVT OldVT = Op.getValueType();
754 DebugLoc dl = Op.getDebugLoc();
755 bool Replace = false;
756 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
757 if (NewOp.getNode() == 0)
759 AddToWorkList(NewOp.getNode());
762 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
763 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
764 DAG.getValueType(OldVT));
767 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
768 EVT OldVT = Op.getValueType();
769 DebugLoc dl = Op.getDebugLoc();
770 bool Replace = false;
771 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
772 if (NewOp.getNode() == 0)
774 AddToWorkList(NewOp.getNode());
777 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
778 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
781 /// PromoteIntBinOp - Promote the specified integer binary operation if the
782 /// target indicates it is beneficial. e.g. On x86, it's usually better to
783 /// promote i16 operations to i32 since i16 instructions are longer.
784 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
785 if (!LegalOperations)
788 EVT VT = Op.getValueType();
789 if (VT.isVector() || !VT.isInteger())
792 // If operation type is 'undesirable', e.g. i16 on x86, consider
794 unsigned Opc = Op.getOpcode();
795 if (TLI.isTypeDesirableForOp(Opc, VT))
799 // Consult target whether it is a good idea to promote this operation and
800 // what's the right type to promote it to.
801 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
802 assert(PVT != VT && "Don't know what type to promote to!");
804 bool Replace0 = false;
805 SDValue N0 = Op.getOperand(0);
806 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
807 if (NN0.getNode() == 0)
810 bool Replace1 = false;
811 SDValue N1 = Op.getOperand(1);
816 NN1 = PromoteOperand(N1, PVT, Replace1);
817 if (NN1.getNode() == 0)
821 AddToWorkList(NN0.getNode());
823 AddToWorkList(NN1.getNode());
826 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
828 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
830 DEBUG(dbgs() << "\nPromoting ";
831 Op.getNode()->dump(&DAG));
832 DebugLoc dl = Op.getDebugLoc();
833 return DAG.getNode(ISD::TRUNCATE, dl, VT,
834 DAG.getNode(Opc, dl, PVT, NN0, NN1));
839 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
840 /// target indicates it is beneficial. e.g. On x86, it's usually better to
841 /// promote i16 operations to i32 since i16 instructions are longer.
842 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
843 if (!LegalOperations)
846 EVT VT = Op.getValueType();
847 if (VT.isVector() || !VT.isInteger())
850 // If operation type is 'undesirable', e.g. i16 on x86, consider
852 unsigned Opc = Op.getOpcode();
853 if (TLI.isTypeDesirableForOp(Opc, VT))
857 // Consult target whether it is a good idea to promote this operation and
858 // what's the right type to promote it to.
859 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
860 assert(PVT != VT && "Don't know what type to promote to!");
862 bool Replace = false;
863 SDValue N0 = Op.getOperand(0);
865 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
866 else if (Opc == ISD::SRL)
867 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
869 N0 = PromoteOperand(N0, PVT, Replace);
870 if (N0.getNode() == 0)
873 AddToWorkList(N0.getNode());
875 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
877 DEBUG(dbgs() << "\nPromoting ";
878 Op.getNode()->dump(&DAG));
879 DebugLoc dl = Op.getDebugLoc();
880 return DAG.getNode(ISD::TRUNCATE, dl, VT,
881 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
886 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
887 if (!LegalOperations)
890 EVT VT = Op.getValueType();
891 if (VT.isVector() || !VT.isInteger())
894 // If operation type is 'undesirable', e.g. i16 on x86, consider
896 unsigned Opc = Op.getOpcode();
897 if (TLI.isTypeDesirableForOp(Opc, VT))
901 // Consult target whether it is a good idea to promote this operation and
902 // what's the right type to promote it to.
903 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
904 assert(PVT != VT && "Don't know what type to promote to!");
905 // fold (aext (aext x)) -> (aext x)
906 // fold (aext (zext x)) -> (zext x)
907 // fold (aext (sext x)) -> (sext x)
908 DEBUG(dbgs() << "\nPromoting ";
909 Op.getNode()->dump(&DAG));
910 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
915 bool DAGCombiner::PromoteLoad(SDValue Op) {
916 if (!LegalOperations)
919 EVT VT = Op.getValueType();
920 if (VT.isVector() || !VT.isInteger())
923 // If operation type is 'undesirable', e.g. i16 on x86, consider
925 unsigned Opc = Op.getOpcode();
926 if (TLI.isTypeDesirableForOp(Opc, VT))
930 // Consult target whether it is a good idea to promote this operation and
931 // what's the right type to promote it to.
932 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
933 assert(PVT != VT && "Don't know what type to promote to!");
935 DebugLoc dl = Op.getDebugLoc();
936 SDNode *N = Op.getNode();
937 LoadSDNode *LD = cast<LoadSDNode>(N);
938 EVT MemVT = LD->getMemoryVT();
939 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
940 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
942 : LD->getExtensionType();
943 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
944 LD->getChain(), LD->getBasePtr(),
945 LD->getPointerInfo(),
946 MemVT, LD->isVolatile(),
947 LD->isNonTemporal(), LD->getAlignment());
948 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
950 DEBUG(dbgs() << "\nPromoting ";
953 Result.getNode()->dump(&DAG);
955 WorkListRemover DeadNodes(*this);
956 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
957 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
958 removeFromWorkList(N);
960 AddToWorkList(Result.getNode());
967 //===----------------------------------------------------------------------===//
968 // Main DAG Combiner implementation
969 //===----------------------------------------------------------------------===//
971 void DAGCombiner::Run(CombineLevel AtLevel) {
972 // set the instance variables, so that the various visit routines may use it.
974 LegalOperations = Level >= AfterLegalizeVectorOps;
975 LegalTypes = Level >= AfterLegalizeTypes;
977 // Add all the dag nodes to the worklist.
978 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
979 E = DAG.allnodes_end(); I != E; ++I)
982 // Create a dummy node (which is not added to allnodes), that adds a reference
983 // to the root node, preventing it from being deleted, and tracking any
984 // changes of the root.
985 HandleSDNode Dummy(DAG.getRoot());
987 // The root of the dag may dangle to deleted nodes until the dag combiner is
988 // done. Set it to null to avoid confusion.
989 DAG.setRoot(SDValue());
991 // while the worklist isn't empty, find a node and
992 // try and combine it.
993 while (!WorkListContents.empty()) {
995 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates.
996 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
997 // worklist *should* contain, and check the node we want to visit is should
998 // actually be visited.
1000 N = WorkListOrder.back();
1001 WorkListOrder.pop_back();
1002 } while (!WorkListContents.erase(N));
1004 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1005 // N is deleted from the DAG, since they too may now be dead or may have a
1006 // reduced number of uses, allowing other xforms.
1007 if (N->use_empty() && N != &Dummy) {
1008 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1009 AddToWorkList(N->getOperand(i).getNode());
1015 SDValue RV = combine(N);
1017 if (RV.getNode() == 0)
1022 // If we get back the same node we passed in, rather than a new node or
1023 // zero, we know that the node must have defined multiple values and
1024 // CombineTo was used. Since CombineTo takes care of the worklist
1025 // mechanics for us, we have no work to do in this case.
1026 if (RV.getNode() == N)
1029 assert(N->getOpcode() != ISD::DELETED_NODE &&
1030 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1031 "Node was deleted but visit returned new node!");
1033 DEBUG(dbgs() << "\nReplacing.3 ";
1035 dbgs() << "\nWith: ";
1036 RV.getNode()->dump(&DAG);
1039 // Transfer debug value.
1040 DAG.TransferDbgValues(SDValue(N, 0), RV);
1041 WorkListRemover DeadNodes(*this);
1042 if (N->getNumValues() == RV.getNode()->getNumValues())
1043 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
1045 assert(N->getValueType(0) == RV.getValueType() &&
1046 N->getNumValues() == 1 && "Type mismatch");
1048 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
1051 // Push the new node and any users onto the worklist
1052 AddToWorkList(RV.getNode());
1053 AddUsersToWorkList(RV.getNode());
1055 // Add any uses of the old node to the worklist in case this node is the
1056 // last one that uses them. They may become dead after this node is
1058 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1059 AddToWorkList(N->getOperand(i).getNode());
1061 // Finally, if the node is now dead, remove it from the graph. The node
1062 // may not be dead if the replacement process recursively simplified to
1063 // something else needing this node.
1064 if (N->use_empty()) {
1065 // Nodes can be reintroduced into the worklist. Make sure we do not
1066 // process a node that has been replaced.
1067 removeFromWorkList(N);
1069 // Finally, since the node is now dead, remove it from the graph.
1074 // If the root changed (e.g. it was a dead load, update the root).
1075 DAG.setRoot(Dummy.getValue());
1078 SDValue DAGCombiner::visit(SDNode *N) {
1079 switch (N->getOpcode()) {
1081 case ISD::TokenFactor: return visitTokenFactor(N);
1082 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1083 case ISD::ADD: return visitADD(N);
1084 case ISD::SUB: return visitSUB(N);
1085 case ISD::ADDC: return visitADDC(N);
1086 case ISD::SUBC: return visitSUBC(N);
1087 case ISD::ADDE: return visitADDE(N);
1088 case ISD::SUBE: return visitSUBE(N);
1089 case ISD::MUL: return visitMUL(N);
1090 case ISD::SDIV: return visitSDIV(N);
1091 case ISD::UDIV: return visitUDIV(N);
1092 case ISD::SREM: return visitSREM(N);
1093 case ISD::UREM: return visitUREM(N);
1094 case ISD::MULHU: return visitMULHU(N);
1095 case ISD::MULHS: return visitMULHS(N);
1096 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1097 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1098 case ISD::SMULO: return visitSMULO(N);
1099 case ISD::UMULO: return visitUMULO(N);
1100 case ISD::SDIVREM: return visitSDIVREM(N);
1101 case ISD::UDIVREM: return visitUDIVREM(N);
1102 case ISD::AND: return visitAND(N);
1103 case ISD::OR: return visitOR(N);
1104 case ISD::XOR: return visitXOR(N);
1105 case ISD::SHL: return visitSHL(N);
1106 case ISD::SRA: return visitSRA(N);
1107 case ISD::SRL: return visitSRL(N);
1108 case ISD::CTLZ: return visitCTLZ(N);
1109 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1110 case ISD::CTTZ: return visitCTTZ(N);
1111 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1112 case ISD::CTPOP: return visitCTPOP(N);
1113 case ISD::SELECT: return visitSELECT(N);
1114 case ISD::SELECT_CC: return visitSELECT_CC(N);
1115 case ISD::SETCC: return visitSETCC(N);
1116 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1117 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1118 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1119 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1120 case ISD::TRUNCATE: return visitTRUNCATE(N);
1121 case ISD::BITCAST: return visitBITCAST(N);
1122 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1123 case ISD::FADD: return visitFADD(N);
1124 case ISD::FSUB: return visitFSUB(N);
1125 case ISD::FMUL: return visitFMUL(N);
1126 case ISD::FDIV: return visitFDIV(N);
1127 case ISD::FREM: return visitFREM(N);
1128 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1129 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1130 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1131 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1132 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1133 case ISD::FP_ROUND: return visitFP_ROUND(N);
1134 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1135 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1136 case ISD::FNEG: return visitFNEG(N);
1137 case ISD::FABS: return visitFABS(N);
1138 case ISD::BRCOND: return visitBRCOND(N);
1139 case ISD::BR_CC: return visitBR_CC(N);
1140 case ISD::LOAD: return visitLOAD(N);
1141 case ISD::STORE: return visitSTORE(N);
1142 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1143 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1144 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1145 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1146 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1147 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1148 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1153 SDValue DAGCombiner::combine(SDNode *N) {
1154 SDValue RV = visit(N);
1156 // If nothing happened, try a target-specific DAG combine.
1157 if (RV.getNode() == 0) {
1158 assert(N->getOpcode() != ISD::DELETED_NODE &&
1159 "Node was deleted but visit returned NULL!");
1161 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1162 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1164 // Expose the DAG combiner to the target combiner impls.
1165 TargetLowering::DAGCombinerInfo
1166 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1168 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1172 // If nothing happened still, try promoting the operation.
1173 if (RV.getNode() == 0) {
1174 switch (N->getOpcode()) {
1182 RV = PromoteIntBinOp(SDValue(N, 0));
1187 RV = PromoteIntShiftOp(SDValue(N, 0));
1189 case ISD::SIGN_EXTEND:
1190 case ISD::ZERO_EXTEND:
1191 case ISD::ANY_EXTEND:
1192 RV = PromoteExtend(SDValue(N, 0));
1195 if (PromoteLoad(SDValue(N, 0)))
1201 // If N is a commutative binary node, try commuting it to enable more
1203 if (RV.getNode() == 0 &&
1204 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1205 N->getNumValues() == 1) {
1206 SDValue N0 = N->getOperand(0);
1207 SDValue N1 = N->getOperand(1);
1209 // Constant operands are canonicalized to RHS.
1210 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1211 SDValue Ops[] = { N1, N0 };
1212 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1215 return SDValue(CSENode, 0);
1222 /// getInputChainForNode - Given a node, return its input chain if it has one,
1223 /// otherwise return a null sd operand.
1224 static SDValue getInputChainForNode(SDNode *N) {
1225 if (unsigned NumOps = N->getNumOperands()) {
1226 if (N->getOperand(0).getValueType() == MVT::Other)
1227 return N->getOperand(0);
1228 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1229 return N->getOperand(NumOps-1);
1230 for (unsigned i = 1; i < NumOps-1; ++i)
1231 if (N->getOperand(i).getValueType() == MVT::Other)
1232 return N->getOperand(i);
1237 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1238 // If N has two operands, where one has an input chain equal to the other,
1239 // the 'other' chain is redundant.
1240 if (N->getNumOperands() == 2) {
1241 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1242 return N->getOperand(0);
1243 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1244 return N->getOperand(1);
1247 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1248 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1249 SmallPtrSet<SDNode*, 16> SeenOps;
1250 bool Changed = false; // If we should replace this token factor.
1252 // Start out with this token factor.
1255 // Iterate through token factors. The TFs grows when new token factors are
1257 for (unsigned i = 0; i < TFs.size(); ++i) {
1258 SDNode *TF = TFs[i];
1260 // Check each of the operands.
1261 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1262 SDValue Op = TF->getOperand(i);
1264 switch (Op.getOpcode()) {
1265 case ISD::EntryToken:
1266 // Entry tokens don't need to be added to the list. They are
1271 case ISD::TokenFactor:
1272 if (Op.hasOneUse() &&
1273 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1274 // Queue up for processing.
1275 TFs.push_back(Op.getNode());
1276 // Clean up in case the token factor is removed.
1277 AddToWorkList(Op.getNode());
1284 // Only add if it isn't already in the list.
1285 if (SeenOps.insert(Op.getNode()))
1296 // If we've change things around then replace token factor.
1299 // The entry token is the only possible outcome.
1300 Result = DAG.getEntryNode();
1302 // New and improved token factor.
1303 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1304 MVT::Other, &Ops[0], Ops.size());
1307 // Don't add users to work list.
1308 return CombineTo(N, Result, false);
1314 /// MERGE_VALUES can always be eliminated.
1315 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1316 WorkListRemover DeadNodes(*this);
1317 // Replacing results may cause a different MERGE_VALUES to suddenly
1318 // be CSE'd with N, and carry its uses with it. Iterate until no
1319 // uses remain, to ensure that the node can be safely deleted.
1321 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1322 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1324 } while (!N->use_empty());
1325 removeFromWorkList(N);
1327 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1331 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1332 SelectionDAG &DAG) {
1333 EVT VT = N0.getValueType();
1334 SDValue N00 = N0.getOperand(0);
1335 SDValue N01 = N0.getOperand(1);
1336 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1338 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1339 isa<ConstantSDNode>(N00.getOperand(1))) {
1340 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1341 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1342 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1343 N00.getOperand(0), N01),
1344 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1345 N00.getOperand(1), N01));
1346 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1352 SDValue DAGCombiner::visitADD(SDNode *N) {
1353 SDValue N0 = N->getOperand(0);
1354 SDValue N1 = N->getOperand(1);
1355 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1356 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1357 EVT VT = N0.getValueType();
1360 if (VT.isVector()) {
1361 SDValue FoldedVOp = SimplifyVBinOp(N);
1362 if (FoldedVOp.getNode()) return FoldedVOp;
1365 // fold (add x, undef) -> undef
1366 if (N0.getOpcode() == ISD::UNDEF)
1368 if (N1.getOpcode() == ISD::UNDEF)
1370 // fold (add c1, c2) -> c1+c2
1372 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1373 // canonicalize constant to RHS
1375 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1376 // fold (add x, 0) -> x
1377 if (N1C && N1C->isNullValue())
1379 // fold (add Sym, c) -> Sym+c
1380 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1381 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1382 GA->getOpcode() == ISD::GlobalAddress)
1383 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1385 (uint64_t)N1C->getSExtValue());
1386 // fold ((c1-A)+c2) -> (c1+c2)-A
1387 if (N1C && N0.getOpcode() == ISD::SUB)
1388 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1389 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1390 DAG.getConstant(N1C->getAPIntValue()+
1391 N0C->getAPIntValue(), VT),
1394 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1395 if (RADD.getNode() != 0)
1397 // fold ((0-A) + B) -> B-A
1398 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1399 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1400 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1401 // fold (A + (0-B)) -> A-B
1402 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1403 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1404 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1405 // fold (A+(B-A)) -> B
1406 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1407 return N1.getOperand(0);
1408 // fold ((B-A)+A) -> B
1409 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1410 return N0.getOperand(0);
1411 // fold (A+(B-(A+C))) to (B-C)
1412 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1413 N0 == N1.getOperand(1).getOperand(0))
1414 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1415 N1.getOperand(1).getOperand(1));
1416 // fold (A+(B-(C+A))) to (B-C)
1417 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1418 N0 == N1.getOperand(1).getOperand(1))
1419 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1420 N1.getOperand(1).getOperand(0));
1421 // fold (A+((B-A)+or-C)) to (B+or-C)
1422 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1423 N1.getOperand(0).getOpcode() == ISD::SUB &&
1424 N0 == N1.getOperand(0).getOperand(1))
1425 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1426 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1428 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1429 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1430 SDValue N00 = N0.getOperand(0);
1431 SDValue N01 = N0.getOperand(1);
1432 SDValue N10 = N1.getOperand(0);
1433 SDValue N11 = N1.getOperand(1);
1435 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1436 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1437 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1438 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1441 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1442 return SDValue(N, 0);
1444 // fold (a+b) -> (a|b) iff a and b share no bits.
1445 if (VT.isInteger() && !VT.isVector()) {
1446 APInt LHSZero, LHSOne;
1447 APInt RHSZero, RHSOne;
1448 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1449 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1451 if (LHSZero.getBoolValue()) {
1452 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1454 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1455 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1456 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1457 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1458 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1462 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1463 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1464 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1465 if (Result.getNode()) return Result;
1467 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1468 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1469 if (Result.getNode()) return Result;
1472 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1473 if (N1.getOpcode() == ISD::SHL &&
1474 N1.getOperand(0).getOpcode() == ISD::SUB)
1475 if (ConstantSDNode *C =
1476 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1477 if (C->getAPIntValue() == 0)
1478 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1479 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1480 N1.getOperand(0).getOperand(1),
1482 if (N0.getOpcode() == ISD::SHL &&
1483 N0.getOperand(0).getOpcode() == ISD::SUB)
1484 if (ConstantSDNode *C =
1485 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1486 if (C->getAPIntValue() == 0)
1487 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1488 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1489 N0.getOperand(0).getOperand(1),
1492 if (N1.getOpcode() == ISD::AND) {
1493 SDValue AndOp0 = N1.getOperand(0);
1494 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1495 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1496 unsigned DestBits = VT.getScalarType().getSizeInBits();
1498 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1499 // and similar xforms where the inner op is either ~0 or 0.
1500 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1501 DebugLoc DL = N->getDebugLoc();
1502 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1506 // add (sext i1), X -> sub X, (zext i1)
1507 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1508 N0.getOperand(0).getValueType() == MVT::i1 &&
1509 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1510 DebugLoc DL = N->getDebugLoc();
1511 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1512 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1518 SDValue DAGCombiner::visitADDC(SDNode *N) {
1519 SDValue N0 = N->getOperand(0);
1520 SDValue N1 = N->getOperand(1);
1521 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1522 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1523 EVT VT = N0.getValueType();
1525 // If the flag result is dead, turn this into an ADD.
1526 if (!N->hasAnyUseOfValue(1))
1527 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1),
1528 DAG.getNode(ISD::CARRY_FALSE,
1529 N->getDebugLoc(), MVT::Glue));
1531 // canonicalize constant to RHS.
1533 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1535 // fold (addc x, 0) -> x + no carry out
1536 if (N1C && N1C->isNullValue())
1537 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1538 N->getDebugLoc(), MVT::Glue));
1540 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1541 APInt LHSZero, LHSOne;
1542 APInt RHSZero, RHSOne;
1543 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1544 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1546 if (LHSZero.getBoolValue()) {
1547 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1549 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1550 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1551 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1552 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1553 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1554 DAG.getNode(ISD::CARRY_FALSE,
1555 N->getDebugLoc(), MVT::Glue));
1561 SDValue DAGCombiner::visitADDE(SDNode *N) {
1562 SDValue N0 = N->getOperand(0);
1563 SDValue N1 = N->getOperand(1);
1564 SDValue CarryIn = N->getOperand(2);
1565 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1566 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1568 // canonicalize constant to RHS
1570 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1573 // fold (adde x, y, false) -> (addc x, y)
1574 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1575 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1);
1580 // Since it may not be valid to emit a fold to zero for vector initializers
1581 // check if we can before folding.
1582 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1583 SelectionDAG &DAG, bool LegalOperations) {
1584 if (!VT.isVector()) {
1585 return DAG.getConstant(0, VT);
1587 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1588 // Produce a vector of zeros.
1589 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1590 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1591 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1592 &Ops[0], Ops.size());
1597 SDValue DAGCombiner::visitSUB(SDNode *N) {
1598 SDValue N0 = N->getOperand(0);
1599 SDValue N1 = N->getOperand(1);
1600 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1601 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1602 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1603 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1604 EVT VT = N0.getValueType();
1607 if (VT.isVector()) {
1608 SDValue FoldedVOp = SimplifyVBinOp(N);
1609 if (FoldedVOp.getNode()) return FoldedVOp;
1612 // fold (sub x, x) -> 0
1613 // FIXME: Refactor this and xor and other similar operations together.
1615 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1616 // fold (sub c1, c2) -> c1-c2
1618 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1619 // fold (sub x, c) -> (add x, -c)
1621 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1622 DAG.getConstant(-N1C->getAPIntValue(), VT));
1623 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1624 if (N0C && N0C->isAllOnesValue())
1625 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1626 // fold A-(A-B) -> B
1627 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1628 return N1.getOperand(1);
1629 // fold (A+B)-A -> B
1630 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1631 return N0.getOperand(1);
1632 // fold (A+B)-B -> A
1633 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1634 return N0.getOperand(0);
1635 // fold C2-(A+C1) -> (C2-C1)-A
1636 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1637 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT);
1638 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1641 // fold ((A+(B+or-C))-B) -> A+or-C
1642 if (N0.getOpcode() == ISD::ADD &&
1643 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1644 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1645 N0.getOperand(1).getOperand(0) == N1)
1646 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1647 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1648 // fold ((A+(C+B))-B) -> A+C
1649 if (N0.getOpcode() == ISD::ADD &&
1650 N0.getOperand(1).getOpcode() == ISD::ADD &&
1651 N0.getOperand(1).getOperand(1) == N1)
1652 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1653 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1654 // fold ((A-(B-C))-C) -> A-B
1655 if (N0.getOpcode() == ISD::SUB &&
1656 N0.getOperand(1).getOpcode() == ISD::SUB &&
1657 N0.getOperand(1).getOperand(1) == N1)
1658 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1659 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1661 // If either operand of a sub is undef, the result is undef
1662 if (N0.getOpcode() == ISD::UNDEF)
1664 if (N1.getOpcode() == ISD::UNDEF)
1667 // If the relocation model supports it, consider symbol offsets.
1668 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1669 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1670 // fold (sub Sym, c) -> Sym-c
1671 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1672 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1674 (uint64_t)N1C->getSExtValue());
1675 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1676 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1677 if (GA->getGlobal() == GB->getGlobal())
1678 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1685 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1686 SDValue N0 = N->getOperand(0);
1687 SDValue N1 = N->getOperand(1);
1688 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1689 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1690 EVT VT = N0.getValueType();
1692 // If the flag result is dead, turn this into an SUB.
1693 if (!N->hasAnyUseOfValue(1))
1694 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1),
1695 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1698 // fold (subc x, x) -> 0 + no borrow
1700 return CombineTo(N, DAG.getConstant(0, VT),
1701 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1704 // fold (subc x, 0) -> x + no borrow
1705 if (N1C && N1C->isNullValue())
1706 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1709 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1710 if (N0C && N0C->isAllOnesValue())
1711 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0),
1712 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(),
1718 SDValue DAGCombiner::visitSUBE(SDNode *N) {
1719 SDValue N0 = N->getOperand(0);
1720 SDValue N1 = N->getOperand(1);
1721 SDValue CarryIn = N->getOperand(2);
1723 // fold (sube x, y, false) -> (subc x, y)
1724 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1725 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1);
1730 SDValue DAGCombiner::visitMUL(SDNode *N) {
1731 SDValue N0 = N->getOperand(0);
1732 SDValue N1 = N->getOperand(1);
1733 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1734 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1735 EVT VT = N0.getValueType();
1738 if (VT.isVector()) {
1739 SDValue FoldedVOp = SimplifyVBinOp(N);
1740 if (FoldedVOp.getNode()) return FoldedVOp;
1743 // fold (mul x, undef) -> 0
1744 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1745 return DAG.getConstant(0, VT);
1746 // fold (mul c1, c2) -> c1*c2
1748 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1749 // canonicalize constant to RHS
1751 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1752 // fold (mul x, 0) -> 0
1753 if (N1C && N1C->isNullValue())
1755 // fold (mul x, -1) -> 0-x
1756 if (N1C && N1C->isAllOnesValue())
1757 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1758 DAG.getConstant(0, VT), N0);
1759 // fold (mul x, (1 << c)) -> x << c
1760 if (N1C && N1C->getAPIntValue().isPowerOf2())
1761 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1762 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1763 getShiftAmountTy(N0.getValueType())));
1764 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1765 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1766 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1767 // FIXME: If the input is something that is easily negated (e.g. a
1768 // single-use add), we should put the negate there.
1769 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1770 DAG.getConstant(0, VT),
1771 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1772 DAG.getConstant(Log2Val,
1773 getShiftAmountTy(N0.getValueType()))));
1775 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1776 if (N1C && N0.getOpcode() == ISD::SHL &&
1777 isa<ConstantSDNode>(N0.getOperand(1))) {
1778 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1779 N1, N0.getOperand(1));
1780 AddToWorkList(C3.getNode());
1781 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1782 N0.getOperand(0), C3);
1785 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1788 SDValue Sh(0,0), Y(0,0);
1789 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1790 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1791 N0.getNode()->hasOneUse()) {
1793 } else if (N1.getOpcode() == ISD::SHL &&
1794 isa<ConstantSDNode>(N1.getOperand(1)) &&
1795 N1.getNode()->hasOneUse()) {
1800 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1801 Sh.getOperand(0), Y);
1802 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1803 Mul, Sh.getOperand(1));
1807 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1808 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1809 isa<ConstantSDNode>(N0.getOperand(1)))
1810 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1811 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1812 N0.getOperand(0), N1),
1813 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1814 N0.getOperand(1), N1));
1817 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1818 if (RMUL.getNode() != 0)
1824 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1825 SDValue N0 = N->getOperand(0);
1826 SDValue N1 = N->getOperand(1);
1827 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1828 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1829 EVT VT = N->getValueType(0);
1832 if (VT.isVector()) {
1833 SDValue FoldedVOp = SimplifyVBinOp(N);
1834 if (FoldedVOp.getNode()) return FoldedVOp;
1837 // fold (sdiv c1, c2) -> c1/c2
1838 if (N0C && N1C && !N1C->isNullValue())
1839 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1840 // fold (sdiv X, 1) -> X
1841 if (N1C && N1C->getAPIntValue() == 1LL)
1843 // fold (sdiv X, -1) -> 0-X
1844 if (N1C && N1C->isAllOnesValue())
1845 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1846 DAG.getConstant(0, VT), N0);
1847 // If we know the sign bits of both operands are zero, strength reduce to a
1848 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1849 if (!VT.isVector()) {
1850 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1851 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1854 // fold (sdiv X, pow2) -> simple ops after legalize
1855 if (N1C && !N1C->isNullValue() &&
1856 (N1C->getAPIntValue().isPowerOf2() ||
1857 (-N1C->getAPIntValue()).isPowerOf2())) {
1858 // If dividing by powers of two is cheap, then don't perform the following
1860 if (TLI.isPow2DivCheap())
1863 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1865 // Splat the sign bit into the register
1866 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1867 DAG.getConstant(VT.getSizeInBits()-1,
1868 getShiftAmountTy(N0.getValueType())));
1869 AddToWorkList(SGN.getNode());
1871 // Add (N0 < 0) ? abs2 - 1 : 0;
1872 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1873 DAG.getConstant(VT.getSizeInBits() - lg2,
1874 getShiftAmountTy(SGN.getValueType())));
1875 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1876 AddToWorkList(SRL.getNode());
1877 AddToWorkList(ADD.getNode()); // Divide by pow2
1878 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1879 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1881 // If we're dividing by a positive value, we're done. Otherwise, we must
1882 // negate the result.
1883 if (N1C->getAPIntValue().isNonNegative())
1886 AddToWorkList(SRA.getNode());
1887 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1888 DAG.getConstant(0, VT), SRA);
1891 // if integer divide is expensive and we satisfy the requirements, emit an
1892 // alternate sequence.
1893 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1894 SDValue Op = BuildSDIV(N);
1895 if (Op.getNode()) return Op;
1899 if (N0.getOpcode() == ISD::UNDEF)
1900 return DAG.getConstant(0, VT);
1901 // X / undef -> undef
1902 if (N1.getOpcode() == ISD::UNDEF)
1908 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1909 SDValue N0 = N->getOperand(0);
1910 SDValue N1 = N->getOperand(1);
1911 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1912 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1913 EVT VT = N->getValueType(0);
1916 if (VT.isVector()) {
1917 SDValue FoldedVOp = SimplifyVBinOp(N);
1918 if (FoldedVOp.getNode()) return FoldedVOp;
1921 // fold (udiv c1, c2) -> c1/c2
1922 if (N0C && N1C && !N1C->isNullValue())
1923 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1924 // fold (udiv x, (1 << c)) -> x >>u c
1925 if (N1C && N1C->getAPIntValue().isPowerOf2())
1926 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1927 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1928 getShiftAmountTy(N0.getValueType())));
1929 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1930 if (N1.getOpcode() == ISD::SHL) {
1931 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1932 if (SHC->getAPIntValue().isPowerOf2()) {
1933 EVT ADDVT = N1.getOperand(1).getValueType();
1934 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1936 DAG.getConstant(SHC->getAPIntValue()
1939 AddToWorkList(Add.getNode());
1940 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1944 // fold (udiv x, c) -> alternate
1945 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1946 SDValue Op = BuildUDIV(N);
1947 if (Op.getNode()) return Op;
1951 if (N0.getOpcode() == ISD::UNDEF)
1952 return DAG.getConstant(0, VT);
1953 // X / undef -> undef
1954 if (N1.getOpcode() == ISD::UNDEF)
1960 SDValue DAGCombiner::visitSREM(SDNode *N) {
1961 SDValue N0 = N->getOperand(0);
1962 SDValue N1 = N->getOperand(1);
1963 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1964 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1965 EVT VT = N->getValueType(0);
1967 // fold (srem c1, c2) -> c1%c2
1968 if (N0C && N1C && !N1C->isNullValue())
1969 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1970 // If we know the sign bits of both operands are zero, strength reduce to a
1971 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1972 if (!VT.isVector()) {
1973 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1974 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1977 // If X/C can be simplified by the division-by-constant logic, lower
1978 // X%C to the equivalent of X-X/C*C.
1979 if (N1C && !N1C->isNullValue()) {
1980 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1981 AddToWorkList(Div.getNode());
1982 SDValue OptimizedDiv = combine(Div.getNode());
1983 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1984 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1986 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1987 AddToWorkList(Mul.getNode());
1993 if (N0.getOpcode() == ISD::UNDEF)
1994 return DAG.getConstant(0, VT);
1995 // X % undef -> undef
1996 if (N1.getOpcode() == ISD::UNDEF)
2002 SDValue DAGCombiner::visitUREM(SDNode *N) {
2003 SDValue N0 = N->getOperand(0);
2004 SDValue N1 = N->getOperand(1);
2005 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2006 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2007 EVT VT = N->getValueType(0);
2009 // fold (urem c1, c2) -> c1%c2
2010 if (N0C && N1C && !N1C->isNullValue())
2011 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
2012 // fold (urem x, pow2) -> (and x, pow2-1)
2013 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
2014 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
2015 DAG.getConstant(N1C->getAPIntValue()-1,VT));
2016 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2017 if (N1.getOpcode() == ISD::SHL) {
2018 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
2019 if (SHC->getAPIntValue().isPowerOf2()) {
2021 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
2022 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
2024 AddToWorkList(Add.getNode());
2025 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
2030 // If X/C can be simplified by the division-by-constant logic, lower
2031 // X%C to the equivalent of X-X/C*C.
2032 if (N1C && !N1C->isNullValue()) {
2033 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
2034 AddToWorkList(Div.getNode());
2035 SDValue OptimizedDiv = combine(Div.getNode());
2036 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2037 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
2039 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
2040 AddToWorkList(Mul.getNode());
2046 if (N0.getOpcode() == ISD::UNDEF)
2047 return DAG.getConstant(0, VT);
2048 // X % undef -> undef
2049 if (N1.getOpcode() == ISD::UNDEF)
2055 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2056 SDValue N0 = N->getOperand(0);
2057 SDValue N1 = N->getOperand(1);
2058 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2059 EVT VT = N->getValueType(0);
2060 DebugLoc DL = N->getDebugLoc();
2062 // fold (mulhs x, 0) -> 0
2063 if (N1C && N1C->isNullValue())
2065 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2066 if (N1C && N1C->getAPIntValue() == 1)
2067 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2068 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2069 getShiftAmountTy(N0.getValueType())));
2070 // fold (mulhs x, undef) -> 0
2071 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2072 return DAG.getConstant(0, VT);
2074 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2076 if (VT.isSimple() && !VT.isVector()) {
2077 MVT Simple = VT.getSimpleVT();
2078 unsigned SimpleSize = Simple.getSizeInBits();
2079 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2080 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2081 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2082 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2083 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2084 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2085 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2086 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2093 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2094 SDValue N0 = N->getOperand(0);
2095 SDValue N1 = N->getOperand(1);
2096 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2097 EVT VT = N->getValueType(0);
2098 DebugLoc DL = N->getDebugLoc();
2100 // fold (mulhu x, 0) -> 0
2101 if (N1C && N1C->isNullValue())
2103 // fold (mulhu x, 1) -> 0
2104 if (N1C && N1C->getAPIntValue() == 1)
2105 return DAG.getConstant(0, N0.getValueType());
2106 // fold (mulhu x, undef) -> 0
2107 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2108 return DAG.getConstant(0, VT);
2110 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2112 if (VT.isSimple() && !VT.isVector()) {
2113 MVT Simple = VT.getSimpleVT();
2114 unsigned SimpleSize = Simple.getSizeInBits();
2115 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2116 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2117 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2118 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2119 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2120 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2121 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2122 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2129 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2130 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2131 /// that are being performed. Return true if a simplification was made.
2133 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2135 // If the high half is not needed, just compute the low half.
2136 bool HiExists = N->hasAnyUseOfValue(1);
2138 (!LegalOperations ||
2139 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2140 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2141 N->op_begin(), N->getNumOperands());
2142 return CombineTo(N, Res, Res);
2145 // If the low half is not needed, just compute the high half.
2146 bool LoExists = N->hasAnyUseOfValue(0);
2148 (!LegalOperations ||
2149 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2150 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2151 N->op_begin(), N->getNumOperands());
2152 return CombineTo(N, Res, Res);
2155 // If both halves are used, return as it is.
2156 if (LoExists && HiExists)
2159 // If the two computed results can be simplified separately, separate them.
2161 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2162 N->op_begin(), N->getNumOperands());
2163 AddToWorkList(Lo.getNode());
2164 SDValue LoOpt = combine(Lo.getNode());
2165 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2166 (!LegalOperations ||
2167 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2168 return CombineTo(N, LoOpt, LoOpt);
2172 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2173 N->op_begin(), N->getNumOperands());
2174 AddToWorkList(Hi.getNode());
2175 SDValue HiOpt = combine(Hi.getNode());
2176 if (HiOpt.getNode() && HiOpt != Hi &&
2177 (!LegalOperations ||
2178 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2179 return CombineTo(N, HiOpt, HiOpt);
2185 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2186 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2187 if (Res.getNode()) return Res;
2189 EVT VT = N->getValueType(0);
2190 DebugLoc DL = N->getDebugLoc();
2192 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2194 if (VT.isSimple() && !VT.isVector()) {
2195 MVT Simple = VT.getSimpleVT();
2196 unsigned SimpleSize = Simple.getSizeInBits();
2197 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2198 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2199 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2200 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2201 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2202 // Compute the high part as N1.
2203 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2204 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2205 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2206 // Compute the low part as N0.
2207 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2208 return CombineTo(N, Lo, Hi);
2215 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2216 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2217 if (Res.getNode()) return Res;
2219 EVT VT = N->getValueType(0);
2220 DebugLoc DL = N->getDebugLoc();
2222 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2224 if (VT.isSimple() && !VT.isVector()) {
2225 MVT Simple = VT.getSimpleVT();
2226 unsigned SimpleSize = Simple.getSizeInBits();
2227 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2228 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2229 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2230 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2231 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2232 // Compute the high part as N1.
2233 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2234 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2235 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2236 // Compute the low part as N0.
2237 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2238 return CombineTo(N, Lo, Hi);
2245 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2246 // (smulo x, 2) -> (saddo x, x)
2247 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2248 if (C2->getAPIntValue() == 2)
2249 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2250 N->getOperand(0), N->getOperand(0));
2255 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2256 // (umulo x, 2) -> (uaddo x, x)
2257 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2258 if (C2->getAPIntValue() == 2)
2259 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2260 N->getOperand(0), N->getOperand(0));
2265 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2266 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2267 if (Res.getNode()) return Res;
2272 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2273 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2274 if (Res.getNode()) return Res;
2279 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2280 /// two operands of the same opcode, try to simplify it.
2281 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2282 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2283 EVT VT = N0.getValueType();
2284 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2286 // Bail early if none of these transforms apply.
2287 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2289 // For each of OP in AND/OR/XOR:
2290 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2291 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2292 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2293 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2295 // do not sink logical op inside of a vector extend, since it may combine
2297 EVT Op0VT = N0.getOperand(0).getValueType();
2298 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2299 N0.getOpcode() == ISD::SIGN_EXTEND ||
2300 // Avoid infinite looping with PromoteIntBinOp.
2301 (N0.getOpcode() == ISD::ANY_EXTEND &&
2302 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2303 (N0.getOpcode() == ISD::TRUNCATE &&
2304 (!TLI.isZExtFree(VT, Op0VT) ||
2305 !TLI.isTruncateFree(Op0VT, VT)) &&
2306 TLI.isTypeLegal(Op0VT))) &&
2308 Op0VT == N1.getOperand(0).getValueType() &&
2309 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2310 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2311 N0.getOperand(0).getValueType(),
2312 N0.getOperand(0), N1.getOperand(0));
2313 AddToWorkList(ORNode.getNode());
2314 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2317 // For each of OP in SHL/SRL/SRA/AND...
2318 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2319 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2320 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2321 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2322 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2323 N0.getOperand(1) == N1.getOperand(1)) {
2324 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2325 N0.getOperand(0).getValueType(),
2326 N0.getOperand(0), N1.getOperand(0));
2327 AddToWorkList(ORNode.getNode());
2328 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2329 ORNode, N0.getOperand(1));
2335 SDValue DAGCombiner::visitAND(SDNode *N) {
2336 SDValue N0 = N->getOperand(0);
2337 SDValue N1 = N->getOperand(1);
2338 SDValue LL, LR, RL, RR, CC0, CC1;
2339 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2340 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2341 EVT VT = N1.getValueType();
2342 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2345 if (VT.isVector()) {
2346 SDValue FoldedVOp = SimplifyVBinOp(N);
2347 if (FoldedVOp.getNode()) return FoldedVOp;
2350 // fold (and x, undef) -> 0
2351 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2352 return DAG.getConstant(0, VT);
2353 // fold (and c1, c2) -> c1&c2
2355 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2356 // canonicalize constant to RHS
2358 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2359 // fold (and x, -1) -> x
2360 if (N1C && N1C->isAllOnesValue())
2362 // if (and x, c) is known to be zero, return 0
2363 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2364 APInt::getAllOnesValue(BitWidth)))
2365 return DAG.getConstant(0, VT);
2367 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2368 if (RAND.getNode() != 0)
2370 // fold (and (or x, C), D) -> D if (C & D) == D
2371 if (N1C && N0.getOpcode() == ISD::OR)
2372 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2373 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2375 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2376 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2377 SDValue N0Op0 = N0.getOperand(0);
2378 APInt Mask = ~N1C->getAPIntValue();
2379 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2380 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2381 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2382 N0.getValueType(), N0Op0);
2384 // Replace uses of the AND with uses of the Zero extend node.
2387 // We actually want to replace all uses of the any_extend with the
2388 // zero_extend, to avoid duplicating things. This will later cause this
2389 // AND to be folded.
2390 CombineTo(N0.getNode(), Zext);
2391 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2394 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2395 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2396 // already be zero by virtue of the width of the base type of the load.
2398 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2400 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2401 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2402 N0.getOpcode() == ISD::LOAD) {
2403 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2404 N0 : N0.getOperand(0) );
2406 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2407 // This can be a pure constant or a vector splat, in which case we treat the
2408 // vector as a scalar and use the splat value.
2409 APInt Constant = APInt::getNullValue(1);
2410 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2411 Constant = C->getAPIntValue();
2412 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2413 APInt SplatValue, SplatUndef;
2414 unsigned SplatBitSize;
2416 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2417 SplatBitSize, HasAnyUndefs);
2419 // Undef bits can contribute to a possible optimisation if set, so
2421 SplatValue |= SplatUndef;
2423 // The splat value may be something like "0x00FFFFFF", which means 0 for
2424 // the first vector value and FF for the rest, repeating. We need a mask
2425 // that will apply equally to all members of the vector, so AND all the
2426 // lanes of the constant together.
2427 EVT VT = Vector->getValueType(0);
2428 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2429 Constant = APInt::getAllOnesValue(BitWidth);
2430 for (unsigned i = 0, n = VT.getVectorNumElements(); i < n; ++i)
2431 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
2435 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
2436 // actually legal and isn't going to get expanded, else this is a false
2438 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
2439 Load->getMemoryVT());
2441 // Resize the constant to the same size as the original memory access before
2442 // extension. If it is still the AllOnesValue then this AND is completely
2445 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
2448 switch (Load->getExtensionType()) {
2449 default: B = false; break;
2450 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
2452 case ISD::NON_EXTLOAD: B = true; break;
2455 if (B && Constant.isAllOnesValue()) {
2456 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
2457 // preserve semantics once we get rid of the AND.
2458 SDValue NewLoad(Load, 0);
2459 if (Load->getExtensionType() == ISD::EXTLOAD) {
2460 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
2461 Load->getValueType(0), Load->getDebugLoc(),
2462 Load->getChain(), Load->getBasePtr(),
2463 Load->getOffset(), Load->getMemoryVT(),
2464 Load->getMemOperand());
2465 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
2466 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
2469 // Fold the AND away, taking care not to fold to the old load node if we
2471 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
2473 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2476 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2477 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2478 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2479 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2481 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2482 LL.getValueType().isInteger()) {
2483 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2484 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2485 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2486 LR.getValueType(), LL, RL);
2487 AddToWorkList(ORNode.getNode());
2488 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2490 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2491 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2492 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2493 LR.getValueType(), LL, RL);
2494 AddToWorkList(ANDNode.getNode());
2495 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2497 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2498 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2499 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2500 LR.getValueType(), LL, RL);
2501 AddToWorkList(ORNode.getNode());
2502 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2505 // canonicalize equivalent to ll == rl
2506 if (LL == RR && LR == RL) {
2507 Op1 = ISD::getSetCCSwappedOperands(Op1);
2510 if (LL == RL && LR == RR) {
2511 bool isInteger = LL.getValueType().isInteger();
2512 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2513 if (Result != ISD::SETCC_INVALID &&
2514 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2515 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2520 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2521 if (N0.getOpcode() == N1.getOpcode()) {
2522 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2523 if (Tmp.getNode()) return Tmp;
2526 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2527 // fold (and (sra)) -> (and (srl)) when possible.
2528 if (!VT.isVector() &&
2529 SimplifyDemandedBits(SDValue(N, 0)))
2530 return SDValue(N, 0);
2532 // fold (zext_inreg (extload x)) -> (zextload x)
2533 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2534 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2535 EVT MemVT = LN0->getMemoryVT();
2536 // If we zero all the possible extended bits, then we can turn this into
2537 // a zextload if we are running before legalize or the operation is legal.
2538 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2539 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2540 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2541 ((!LegalOperations && !LN0->isVolatile()) ||
2542 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2543 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2544 LN0->getChain(), LN0->getBasePtr(),
2545 LN0->getPointerInfo(), MemVT,
2546 LN0->isVolatile(), LN0->isNonTemporal(),
2547 LN0->getAlignment());
2549 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2550 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2553 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2554 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2556 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2557 EVT MemVT = LN0->getMemoryVT();
2558 // If we zero all the possible extended bits, then we can turn this into
2559 // a zextload if we are running before legalize or the operation is legal.
2560 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2561 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2562 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2563 ((!LegalOperations && !LN0->isVolatile()) ||
2564 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2565 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2567 LN0->getBasePtr(), LN0->getPointerInfo(),
2569 LN0->isVolatile(), LN0->isNonTemporal(),
2570 LN0->getAlignment());
2572 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2573 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2577 // fold (and (load x), 255) -> (zextload x, i8)
2578 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2579 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2580 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2581 (N0.getOpcode() == ISD::ANY_EXTEND &&
2582 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2583 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2584 LoadSDNode *LN0 = HasAnyExt
2585 ? cast<LoadSDNode>(N0.getOperand(0))
2586 : cast<LoadSDNode>(N0);
2587 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2588 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2589 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2590 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2591 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2592 EVT LoadedVT = LN0->getMemoryVT();
2594 if (ExtVT == LoadedVT &&
2595 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2596 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2599 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2600 LN0->getChain(), LN0->getBasePtr(),
2601 LN0->getPointerInfo(),
2602 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2603 LN0->getAlignment());
2605 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2606 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2609 // Do not change the width of a volatile load.
2610 // Do not generate loads of non-round integer types since these can
2611 // be expensive (and would be wrong if the type is not byte sized).
2612 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2613 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2614 EVT PtrType = LN0->getOperand(1).getValueType();
2616 unsigned Alignment = LN0->getAlignment();
2617 SDValue NewPtr = LN0->getBasePtr();
2619 // For big endian targets, we need to add an offset to the pointer
2620 // to load the correct bytes. For little endian systems, we merely
2621 // need to read fewer bytes from the same pointer.
2622 if (TLI.isBigEndian()) {
2623 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2624 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2625 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2626 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2627 NewPtr, DAG.getConstant(PtrOff, PtrType));
2628 Alignment = MinAlign(Alignment, PtrOff);
2631 AddToWorkList(NewPtr.getNode());
2633 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2635 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2636 LN0->getChain(), NewPtr,
2637 LN0->getPointerInfo(),
2638 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2641 CombineTo(LN0, Load, Load.getValue(1));
2642 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2651 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2653 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2654 bool DemandHighBits) {
2655 if (!LegalOperations)
2658 EVT VT = N->getValueType(0);
2659 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2661 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2664 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2665 bool LookPassAnd0 = false;
2666 bool LookPassAnd1 = false;
2667 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2669 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2671 if (N0.getOpcode() == ISD::AND) {
2672 if (!N0.getNode()->hasOneUse())
2674 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2675 if (!N01C || N01C->getZExtValue() != 0xFF00)
2677 N0 = N0.getOperand(0);
2678 LookPassAnd0 = true;
2681 if (N1.getOpcode() == ISD::AND) {
2682 if (!N1.getNode()->hasOneUse())
2684 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2685 if (!N11C || N11C->getZExtValue() != 0xFF)
2687 N1 = N1.getOperand(0);
2688 LookPassAnd1 = true;
2691 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2693 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2695 if (!N0.getNode()->hasOneUse() ||
2696 !N1.getNode()->hasOneUse())
2699 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2700 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2703 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2706 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2707 SDValue N00 = N0->getOperand(0);
2708 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2709 if (!N00.getNode()->hasOneUse())
2711 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2712 if (!N001C || N001C->getZExtValue() != 0xFF)
2714 N00 = N00.getOperand(0);
2715 LookPassAnd0 = true;
2718 SDValue N10 = N1->getOperand(0);
2719 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2720 if (!N10.getNode()->hasOneUse())
2722 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2723 if (!N101C || N101C->getZExtValue() != 0xFF00)
2725 N10 = N10.getOperand(0);
2726 LookPassAnd1 = true;
2732 // Make sure everything beyond the low halfword is zero since the SRL 16
2733 // will clear the top bits.
2734 unsigned OpSizeInBits = VT.getSizeInBits();
2735 if (DemandHighBits && OpSizeInBits > 16 &&
2736 (!LookPassAnd0 || !LookPassAnd1) &&
2737 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2740 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2741 if (OpSizeInBits > 16)
2742 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2743 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2747 /// isBSwapHWordElement - Return true if the specified node is an element
2748 /// that makes up a 32-bit packed halfword byteswap. i.e.
2749 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2750 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2751 if (!N.getNode()->hasOneUse())
2754 unsigned Opc = N.getOpcode();
2755 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2758 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2763 switch (N1C->getZExtValue()) {
2766 case 0xFF: Num = 0; break;
2767 case 0xFF00: Num = 1; break;
2768 case 0xFF0000: Num = 2; break;
2769 case 0xFF000000: Num = 3; break;
2772 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2773 SDValue N0 = N.getOperand(0);
2774 if (Opc == ISD::AND) {
2775 if (Num == 0 || Num == 2) {
2777 // (x >> 8) & 0xff0000
2778 if (N0.getOpcode() != ISD::SRL)
2780 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2781 if (!C || C->getZExtValue() != 8)
2784 // (x << 8) & 0xff00
2785 // (x << 8) & 0xff000000
2786 if (N0.getOpcode() != ISD::SHL)
2788 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2789 if (!C || C->getZExtValue() != 8)
2792 } else if (Opc == ISD::SHL) {
2794 // (x & 0xff0000) << 8
2795 if (Num != 0 && Num != 2)
2797 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2798 if (!C || C->getZExtValue() != 8)
2800 } else { // Opc == ISD::SRL
2801 // (x & 0xff00) >> 8
2802 // (x & 0xff000000) >> 8
2803 if (Num != 1 && Num != 3)
2805 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2806 if (!C || C->getZExtValue() != 8)
2813 Parts[Num] = N0.getOperand(0).getNode();
2817 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2818 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2819 /// => (rotl (bswap x), 16)
2820 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2821 if (!LegalOperations)
2824 EVT VT = N->getValueType(0);
2827 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2830 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2832 // (or (or (and), (and)), (or (and), (and)))
2833 // (or (or (or (and), (and)), (and)), (and))
2834 if (N0.getOpcode() != ISD::OR)
2836 SDValue N00 = N0.getOperand(0);
2837 SDValue N01 = N0.getOperand(1);
2839 if (N1.getOpcode() == ISD::OR) {
2840 // (or (or (and), (and)), (or (and), (and)))
2841 SDValue N000 = N00.getOperand(0);
2842 if (!isBSwapHWordElement(N000, Parts))
2845 SDValue N001 = N00.getOperand(1);
2846 if (!isBSwapHWordElement(N001, Parts))
2848 SDValue N010 = N01.getOperand(0);
2849 if (!isBSwapHWordElement(N010, Parts))
2851 SDValue N011 = N01.getOperand(1);
2852 if (!isBSwapHWordElement(N011, Parts))
2855 // (or (or (or (and), (and)), (and)), (and))
2856 if (!isBSwapHWordElement(N1, Parts))
2858 if (!isBSwapHWordElement(N01, Parts))
2860 if (N00.getOpcode() != ISD::OR)
2862 SDValue N000 = N00.getOperand(0);
2863 if (!isBSwapHWordElement(N000, Parts))
2865 SDValue N001 = N00.getOperand(1);
2866 if (!isBSwapHWordElement(N001, Parts))
2870 // Make sure the parts are all coming from the same node.
2871 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
2874 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
2875 SDValue(Parts[0],0));
2877 // Result of the bswap should be rotated by 16. If it's not legal, than
2878 // do (x << 16) | (x >> 16).
2879 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
2880 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
2881 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
2882 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
2883 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
2884 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
2885 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
2886 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
2889 SDValue DAGCombiner::visitOR(SDNode *N) {
2890 SDValue N0 = N->getOperand(0);
2891 SDValue N1 = N->getOperand(1);
2892 SDValue LL, LR, RL, RR, CC0, CC1;
2893 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2894 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2895 EVT VT = N1.getValueType();
2898 if (VT.isVector()) {
2899 SDValue FoldedVOp = SimplifyVBinOp(N);
2900 if (FoldedVOp.getNode()) return FoldedVOp;
2903 // fold (or x, undef) -> -1
2904 if (!LegalOperations &&
2905 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2906 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2907 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2909 // fold (or c1, c2) -> c1|c2
2911 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2912 // canonicalize constant to RHS
2914 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2915 // fold (or x, 0) -> x
2916 if (N1C && N1C->isNullValue())
2918 // fold (or x, -1) -> -1
2919 if (N1C && N1C->isAllOnesValue())
2921 // fold (or x, c) -> c iff (x & ~c) == 0
2922 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2925 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
2926 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
2927 if (BSwap.getNode() != 0)
2929 BSwap = MatchBSwapHWordLow(N, N0, N1);
2930 if (BSwap.getNode() != 0)
2934 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2935 if (ROR.getNode() != 0)
2937 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2938 // iff (c1 & c2) == 0.
2939 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2940 isa<ConstantSDNode>(N0.getOperand(1))) {
2941 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2942 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2943 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2944 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2945 N0.getOperand(0), N1),
2946 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2948 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2949 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2950 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2951 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2953 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2954 LL.getValueType().isInteger()) {
2955 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2956 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2957 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2958 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2959 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2960 LR.getValueType(), LL, RL);
2961 AddToWorkList(ORNode.getNode());
2962 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2964 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2965 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2966 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2967 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2968 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2969 LR.getValueType(), LL, RL);
2970 AddToWorkList(ANDNode.getNode());
2971 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2974 // canonicalize equivalent to ll == rl
2975 if (LL == RR && LR == RL) {
2976 Op1 = ISD::getSetCCSwappedOperands(Op1);
2979 if (LL == RL && LR == RR) {
2980 bool isInteger = LL.getValueType().isInteger();
2981 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2982 if (Result != ISD::SETCC_INVALID &&
2983 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2984 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2989 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2990 if (N0.getOpcode() == N1.getOpcode()) {
2991 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2992 if (Tmp.getNode()) return Tmp;
2995 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2996 if (N0.getOpcode() == ISD::AND &&
2997 N1.getOpcode() == ISD::AND &&
2998 N0.getOperand(1).getOpcode() == ISD::Constant &&
2999 N1.getOperand(1).getOpcode() == ISD::Constant &&
3000 // Don't increase # computations.
3001 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3002 // We can only do this xform if we know that bits from X that are set in C2
3003 // but not in C1 are already zero. Likewise for Y.
3004 const APInt &LHSMask =
3005 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3006 const APInt &RHSMask =
3007 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
3009 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3010 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3011 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
3012 N0.getOperand(0), N1.getOperand(0));
3013 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
3014 DAG.getConstant(LHSMask | RHSMask, VT));
3018 // See if this is some rotate idiom.
3019 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
3020 return SDValue(Rot, 0);
3022 // Simplify the operands using demanded-bits information.
3023 if (!VT.isVector() &&
3024 SimplifyDemandedBits(SDValue(N, 0)))
3025 return SDValue(N, 0);
3030 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
3031 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3032 if (Op.getOpcode() == ISD::AND) {
3033 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3034 Mask = Op.getOperand(1);
3035 Op = Op.getOperand(0);
3041 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3049 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3050 // idioms for rotate, and if the target supports rotation instructions, generate
3052 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
3053 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3054 EVT VT = LHS.getValueType();
3055 if (!TLI.isTypeLegal(VT)) return 0;
3057 // The target must have at least one rotate flavor.
3058 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3059 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3060 if (!HasROTL && !HasROTR) return 0;
3062 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3063 SDValue LHSShift; // The shift.
3064 SDValue LHSMask; // AND value if any.
3065 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3066 return 0; // Not part of a rotate.
3068 SDValue RHSShift; // The shift.
3069 SDValue RHSMask; // AND value if any.
3070 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3071 return 0; // Not part of a rotate.
3073 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3074 return 0; // Not shifting the same value.
3076 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3077 return 0; // Shifts must disagree.
3079 // Canonicalize shl to left side in a shl/srl pair.
3080 if (RHSShift.getOpcode() == ISD::SHL) {
3081 std::swap(LHS, RHS);
3082 std::swap(LHSShift, RHSShift);
3083 std::swap(LHSMask , RHSMask );
3086 unsigned OpSizeInBits = VT.getSizeInBits();
3087 SDValue LHSShiftArg = LHSShift.getOperand(0);
3088 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3089 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3091 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3092 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3093 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3094 RHSShiftAmt.getOpcode() == ISD::Constant) {
3095 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3096 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3097 if ((LShVal + RShVal) != OpSizeInBits)
3102 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
3104 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
3106 // If there is an AND of either shifted operand, apply it to the result.
3107 if (LHSMask.getNode() || RHSMask.getNode()) {
3108 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3110 if (LHSMask.getNode()) {
3111 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3112 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3114 if (RHSMask.getNode()) {
3115 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3116 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3119 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
3122 return Rot.getNode();
3125 // If there is a mask here, and we have a variable shift, we can't be sure
3126 // that we're masking out the right stuff.
3127 if (LHSMask.getNode() || RHSMask.getNode())
3130 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
3131 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
3132 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
3133 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
3134 if (ConstantSDNode *SUBC =
3135 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
3136 if (SUBC->getAPIntValue() == OpSizeInBits) {
3138 return DAG.getNode(ISD::ROTL, DL, VT,
3139 LHSShiftArg, LHSShiftAmt).getNode();
3141 return DAG.getNode(ISD::ROTR, DL, VT,
3142 LHSShiftArg, RHSShiftAmt).getNode();
3147 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
3148 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
3149 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
3150 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
3151 if (ConstantSDNode *SUBC =
3152 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
3153 if (SUBC->getAPIntValue() == OpSizeInBits) {
3155 return DAG.getNode(ISD::ROTR, DL, VT,
3156 LHSShiftArg, RHSShiftAmt).getNode();
3158 return DAG.getNode(ISD::ROTL, DL, VT,
3159 LHSShiftArg, LHSShiftAmt).getNode();
3164 // Look for sign/zext/any-extended or truncate cases:
3165 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3166 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3167 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3168 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3169 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3170 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3171 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3172 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3173 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3174 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3175 if (RExtOp0.getOpcode() == ISD::SUB &&
3176 RExtOp0.getOperand(1) == LExtOp0) {
3177 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3179 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3180 // (rotr x, (sub 32, y))
3181 if (ConstantSDNode *SUBC =
3182 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3183 if (SUBC->getAPIntValue() == OpSizeInBits) {
3184 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3186 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3189 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3190 RExtOp0 == LExtOp0.getOperand(1)) {
3191 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3193 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3194 // (rotl x, (sub 32, y))
3195 if (ConstantSDNode *SUBC =
3196 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3197 if (SUBC->getAPIntValue() == OpSizeInBits) {
3198 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3200 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3209 SDValue DAGCombiner::visitXOR(SDNode *N) {
3210 SDValue N0 = N->getOperand(0);
3211 SDValue N1 = N->getOperand(1);
3212 SDValue LHS, RHS, CC;
3213 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3214 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3215 EVT VT = N0.getValueType();
3218 if (VT.isVector()) {
3219 SDValue FoldedVOp = SimplifyVBinOp(N);
3220 if (FoldedVOp.getNode()) return FoldedVOp;
3223 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3224 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3225 return DAG.getConstant(0, VT);
3226 // fold (xor x, undef) -> undef
3227 if (N0.getOpcode() == ISD::UNDEF)
3229 if (N1.getOpcode() == ISD::UNDEF)
3231 // fold (xor c1, c2) -> c1^c2
3233 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3234 // canonicalize constant to RHS
3236 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3237 // fold (xor x, 0) -> x
3238 if (N1C && N1C->isNullValue())
3241 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3242 if (RXOR.getNode() != 0)
3245 // fold !(x cc y) -> (x !cc y)
3246 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3247 bool isInt = LHS.getValueType().isInteger();
3248 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3251 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
3252 switch (N0.getOpcode()) {
3254 llvm_unreachable("Unhandled SetCC Equivalent!");
3256 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3257 case ISD::SELECT_CC:
3258 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3259 N0.getOperand(3), NotCC);
3264 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3265 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3266 N0.getNode()->hasOneUse() &&
3267 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3268 SDValue V = N0.getOperand(0);
3269 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3270 DAG.getConstant(1, V.getValueType()));
3271 AddToWorkList(V.getNode());
3272 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3275 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3276 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3277 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3278 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3279 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3280 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3281 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3282 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3283 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3284 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3287 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3288 if (N1C && N1C->isAllOnesValue() &&
3289 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3290 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3291 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3292 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3293 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3294 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3295 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3296 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3299 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3300 if (N1C && N0.getOpcode() == ISD::XOR) {
3301 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3302 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3304 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3305 DAG.getConstant(N1C->getAPIntValue() ^
3306 N00C->getAPIntValue(), VT));
3308 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3309 DAG.getConstant(N1C->getAPIntValue() ^
3310 N01C->getAPIntValue(), VT));
3312 // fold (xor x, x) -> 0
3314 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3316 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3317 if (N0.getOpcode() == N1.getOpcode()) {
3318 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3319 if (Tmp.getNode()) return Tmp;
3322 // Simplify the expression using non-local knowledge.
3323 if (!VT.isVector() &&
3324 SimplifyDemandedBits(SDValue(N, 0)))
3325 return SDValue(N, 0);
3330 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3331 /// the shift amount is a constant.
3332 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3333 SDNode *LHS = N->getOperand(0).getNode();
3334 if (!LHS->hasOneUse()) return SDValue();
3336 // We want to pull some binops through shifts, so that we have (and (shift))
3337 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3338 // thing happens with address calculations, so it's important to canonicalize
3340 bool HighBitSet = false; // Can we transform this if the high bit is set?
3342 switch (LHS->getOpcode()) {
3343 default: return SDValue();
3346 HighBitSet = false; // We can only transform sra if the high bit is clear.
3349 HighBitSet = true; // We can only transform sra if the high bit is set.
3352 if (N->getOpcode() != ISD::SHL)
3353 return SDValue(); // only shl(add) not sr[al](add).
3354 HighBitSet = false; // We can only transform sra if the high bit is clear.
3358 // We require the RHS of the binop to be a constant as well.
3359 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3360 if (!BinOpCst) return SDValue();
3362 // FIXME: disable this unless the input to the binop is a shift by a constant.
3363 // If it is not a shift, it pessimizes some common cases like:
3365 // void foo(int *X, int i) { X[i & 1235] = 1; }
3366 // int bar(int *X, int i) { return X[i & 255]; }
3367 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3368 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3369 BinOpLHSVal->getOpcode() != ISD::SRA &&
3370 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3371 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3374 EVT VT = N->getValueType(0);
3376 // If this is a signed shift right, and the high bit is modified by the
3377 // logical operation, do not perform the transformation. The highBitSet
3378 // boolean indicates the value of the high bit of the constant which would
3379 // cause it to be modified for this operation.
3380 if (N->getOpcode() == ISD::SRA) {
3381 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3382 if (BinOpRHSSignSet != HighBitSet)
3386 // Fold the constants, shifting the binop RHS by the shift amount.
3387 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3389 LHS->getOperand(1), N->getOperand(1));
3391 // Create the new shift.
3392 SDValue NewShift = DAG.getNode(N->getOpcode(),
3393 LHS->getOperand(0).getDebugLoc(),
3394 VT, LHS->getOperand(0), N->getOperand(1));
3396 // Create the new binop.
3397 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3400 SDValue DAGCombiner::visitSHL(SDNode *N) {
3401 SDValue N0 = N->getOperand(0);
3402 SDValue N1 = N->getOperand(1);
3403 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3404 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3405 EVT VT = N0.getValueType();
3406 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3408 // fold (shl c1, c2) -> c1<<c2
3410 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3411 // fold (shl 0, x) -> 0
3412 if (N0C && N0C->isNullValue())
3414 // fold (shl x, c >= size(x)) -> undef
3415 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3416 return DAG.getUNDEF(VT);
3417 // fold (shl x, 0) -> x
3418 if (N1C && N1C->isNullValue())
3420 // fold (shl undef, x) -> 0
3421 if (N0.getOpcode() == ISD::UNDEF)
3422 return DAG.getConstant(0, VT);
3423 // if (shl x, c) is known to be zero, return 0
3424 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3425 APInt::getAllOnesValue(OpSizeInBits)))
3426 return DAG.getConstant(0, VT);
3427 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3428 if (N1.getOpcode() == ISD::TRUNCATE &&
3429 N1.getOperand(0).getOpcode() == ISD::AND &&
3430 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3431 SDValue N101 = N1.getOperand(0).getOperand(1);
3432 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3433 EVT TruncVT = N1.getValueType();
3434 SDValue N100 = N1.getOperand(0).getOperand(0);
3435 APInt TruncC = N101C->getAPIntValue();
3436 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3437 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3438 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3439 DAG.getNode(ISD::TRUNCATE,
3442 DAG.getConstant(TruncC, TruncVT)));
3446 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3447 return SDValue(N, 0);
3449 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3450 if (N1C && N0.getOpcode() == ISD::SHL &&
3451 N0.getOperand(1).getOpcode() == ISD::Constant) {
3452 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3453 uint64_t c2 = N1C->getZExtValue();
3454 if (c1 + c2 >= OpSizeInBits)
3455 return DAG.getConstant(0, VT);
3456 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3457 DAG.getConstant(c1 + c2, N1.getValueType()));
3460 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3461 // For this to be valid, the second form must not preserve any of the bits
3462 // that are shifted out by the inner shift in the first form. This means
3463 // the outer shift size must be >= the number of bits added by the ext.
3464 // As a corollary, we don't care what kind of ext it is.
3465 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3466 N0.getOpcode() == ISD::ANY_EXTEND ||
3467 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3468 N0.getOperand(0).getOpcode() == ISD::SHL &&
3469 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3471 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3472 uint64_t c2 = N1C->getZExtValue();
3473 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3474 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3475 if (c2 >= OpSizeInBits - InnerShiftSize) {
3476 if (c1 + c2 >= OpSizeInBits)
3477 return DAG.getConstant(0, VT);
3478 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3479 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3480 N0.getOperand(0)->getOperand(0)),
3481 DAG.getConstant(c1 + c2, N1.getValueType()));
3485 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3486 // (and (srl x, (sub c1, c2), MASK)
3487 // Only fold this if the inner shift has no other uses -- if it does, folding
3488 // this will increase the total number of instructions.
3489 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() &&
3490 N0.getOperand(1).getOpcode() == ISD::Constant) {
3491 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3492 if (c1 < VT.getSizeInBits()) {
3493 uint64_t c2 = N1C->getZExtValue();
3494 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3495 VT.getSizeInBits() - c1);
3498 Mask = Mask.shl(c2-c1);
3499 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3500 DAG.getConstant(c2-c1, N1.getValueType()));
3502 Mask = Mask.lshr(c1-c2);
3503 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3504 DAG.getConstant(c1-c2, N1.getValueType()));
3506 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3507 DAG.getConstant(Mask, VT));
3510 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3511 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3512 SDValue HiBitsMask =
3513 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3514 VT.getSizeInBits() -
3515 N1C->getZExtValue()),
3517 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3522 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3523 if (NewSHL.getNode())
3530 SDValue DAGCombiner::visitSRA(SDNode *N) {
3531 SDValue N0 = N->getOperand(0);
3532 SDValue N1 = N->getOperand(1);
3533 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3534 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3535 EVT VT = N0.getValueType();
3536 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3538 // fold (sra c1, c2) -> (sra c1, c2)
3540 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3541 // fold (sra 0, x) -> 0
3542 if (N0C && N0C->isNullValue())
3544 // fold (sra -1, x) -> -1
3545 if (N0C && N0C->isAllOnesValue())
3547 // fold (sra x, (setge c, size(x))) -> undef
3548 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3549 return DAG.getUNDEF(VT);
3550 // fold (sra x, 0) -> x
3551 if (N1C && N1C->isNullValue())
3553 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3555 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3556 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3557 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3559 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3560 ExtVT, VT.getVectorNumElements());
3561 if ((!LegalOperations ||
3562 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3563 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3564 N0.getOperand(0), DAG.getValueType(ExtVT));
3567 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3568 if (N1C && N0.getOpcode() == ISD::SRA) {
3569 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3570 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3571 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3572 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3573 DAG.getConstant(Sum, N1C->getValueType(0)));
3577 // fold (sra (shl X, m), (sub result_size, n))
3578 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3579 // result_size - n != m.
3580 // If truncate is free for the target sext(shl) is likely to result in better
3582 if (N0.getOpcode() == ISD::SHL) {
3583 // Get the two constanst of the shifts, CN0 = m, CN = n.
3584 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3586 // Determine what the truncate's result bitsize and type would be.
3588 EVT::getIntegerVT(*DAG.getContext(),
3589 OpSizeInBits - N1C->getZExtValue());
3590 // Determine the residual right-shift amount.
3591 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3593 // If the shift is not a no-op (in which case this should be just a sign
3594 // extend already), the truncated to type is legal, sign_extend is legal
3595 // on that type, and the truncate to that type is both legal and free,
3596 // perform the transform.
3597 if ((ShiftAmt > 0) &&
3598 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3599 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3600 TLI.isTruncateFree(VT, TruncVT)) {
3602 SDValue Amt = DAG.getConstant(ShiftAmt,
3603 getShiftAmountTy(N0.getOperand(0).getValueType()));
3604 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3605 N0.getOperand(0), Amt);
3606 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3608 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3609 N->getValueType(0), Trunc);
3614 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3615 if (N1.getOpcode() == ISD::TRUNCATE &&
3616 N1.getOperand(0).getOpcode() == ISD::AND &&
3617 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3618 SDValue N101 = N1.getOperand(0).getOperand(1);
3619 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3620 EVT TruncVT = N1.getValueType();
3621 SDValue N100 = N1.getOperand(0).getOperand(0);
3622 APInt TruncC = N101C->getAPIntValue();
3623 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3624 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3625 DAG.getNode(ISD::AND, N->getDebugLoc(),
3627 DAG.getNode(ISD::TRUNCATE,
3630 DAG.getConstant(TruncC, TruncVT)));
3634 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3635 // if c1 is equal to the number of bits the trunc removes
3636 if (N0.getOpcode() == ISD::TRUNCATE &&
3637 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3638 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3639 N0.getOperand(0).hasOneUse() &&
3640 N0.getOperand(0).getOperand(1).hasOneUse() &&
3641 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3642 EVT LargeVT = N0.getOperand(0).getValueType();
3643 ConstantSDNode *LargeShiftAmt =
3644 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3646 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3647 LargeShiftAmt->getZExtValue()) {
3649 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3650 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3651 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3652 N0.getOperand(0).getOperand(0), Amt);
3653 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3657 // Simplify, based on bits shifted out of the LHS.
3658 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3659 return SDValue(N, 0);
3662 // If the sign bit is known to be zero, switch this to a SRL.
3663 if (DAG.SignBitIsZero(N0))
3664 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3667 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3668 if (NewSRA.getNode())
3675 SDValue DAGCombiner::visitSRL(SDNode *N) {
3676 SDValue N0 = N->getOperand(0);
3677 SDValue N1 = N->getOperand(1);
3678 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3679 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3680 EVT VT = N0.getValueType();
3681 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3683 // fold (srl c1, c2) -> c1 >>u c2
3685 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3686 // fold (srl 0, x) -> 0
3687 if (N0C && N0C->isNullValue())
3689 // fold (srl x, c >= size(x)) -> undef
3690 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3691 return DAG.getUNDEF(VT);
3692 // fold (srl x, 0) -> x
3693 if (N1C && N1C->isNullValue())
3695 // if (srl x, c) is known to be zero, return 0
3696 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3697 APInt::getAllOnesValue(OpSizeInBits)))
3698 return DAG.getConstant(0, VT);
3700 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3701 if (N1C && N0.getOpcode() == ISD::SRL &&
3702 N0.getOperand(1).getOpcode() == ISD::Constant) {
3703 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3704 uint64_t c2 = N1C->getZExtValue();
3705 if (c1 + c2 >= OpSizeInBits)
3706 return DAG.getConstant(0, VT);
3707 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3708 DAG.getConstant(c1 + c2, N1.getValueType()));
3711 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3712 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3713 N0.getOperand(0).getOpcode() == ISD::SRL &&
3714 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3716 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3717 uint64_t c2 = N1C->getZExtValue();
3718 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3719 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3720 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3721 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3722 if (c1 + OpSizeInBits == InnerShiftSize) {
3723 if (c1 + c2 >= InnerShiftSize)
3724 return DAG.getConstant(0, VT);
3725 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3726 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3727 N0.getOperand(0)->getOperand(0),
3728 DAG.getConstant(c1 + c2, ShiftCountVT)));
3732 // fold (srl (shl x, c), c) -> (and x, cst2)
3733 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3734 N0.getValueSizeInBits() <= 64) {
3735 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3736 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3737 DAG.getConstant(~0ULL >> ShAmt, VT));
3741 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3742 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3743 // Shifting in all undef bits?
3744 EVT SmallVT = N0.getOperand(0).getValueType();
3745 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3746 return DAG.getUNDEF(VT);
3748 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3749 uint64_t ShiftAmt = N1C->getZExtValue();
3750 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3752 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3753 AddToWorkList(SmallShift.getNode());
3754 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3758 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3759 // bit, which is unmodified by sra.
3760 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3761 if (N0.getOpcode() == ISD::SRA)
3762 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3765 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3766 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3767 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3768 APInt KnownZero, KnownOne;
3769 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3770 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3772 // If any of the input bits are KnownOne, then the input couldn't be all
3773 // zeros, thus the result of the srl will always be zero.
3774 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3776 // If all of the bits input the to ctlz node are known to be zero, then
3777 // the result of the ctlz is "32" and the result of the shift is one.
3778 APInt UnknownBits = ~KnownZero & Mask;
3779 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3781 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3782 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3783 // Okay, we know that only that the single bit specified by UnknownBits
3784 // could be set on input to the CTLZ node. If this bit is set, the SRL
3785 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3786 // to an SRL/XOR pair, which is likely to simplify more.
3787 unsigned ShAmt = UnknownBits.countTrailingZeros();
3788 SDValue Op = N0.getOperand(0);
3791 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3792 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3793 AddToWorkList(Op.getNode());
3796 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3797 Op, DAG.getConstant(1, VT));
3801 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3802 if (N1.getOpcode() == ISD::TRUNCATE &&
3803 N1.getOperand(0).getOpcode() == ISD::AND &&
3804 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3805 SDValue N101 = N1.getOperand(0).getOperand(1);
3806 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3807 EVT TruncVT = N1.getValueType();
3808 SDValue N100 = N1.getOperand(0).getOperand(0);
3809 APInt TruncC = N101C->getAPIntValue();
3810 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3811 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3812 DAG.getNode(ISD::AND, N->getDebugLoc(),
3814 DAG.getNode(ISD::TRUNCATE,
3817 DAG.getConstant(TruncC, TruncVT)));
3821 // fold operands of srl based on knowledge that the low bits are not
3823 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3824 return SDValue(N, 0);
3827 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3828 if (NewSRL.getNode())
3832 // Attempt to convert a srl of a load into a narrower zero-extending load.
3833 SDValue NarrowLoad = ReduceLoadWidth(N);
3834 if (NarrowLoad.getNode())
3837 // Here is a common situation. We want to optimize:
3840 // %b = and i32 %a, 2
3841 // %c = srl i32 %b, 1
3842 // brcond i32 %c ...
3848 // %c = setcc eq %b, 0
3851 // However when after the source operand of SRL is optimized into AND, the SRL
3852 // itself may not be optimized further. Look for it and add the BRCOND into
3854 if (N->hasOneUse()) {
3855 SDNode *Use = *N->use_begin();
3856 if (Use->getOpcode() == ISD::BRCOND)
3858 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3859 // Also look pass the truncate.
3860 Use = *Use->use_begin();
3861 if (Use->getOpcode() == ISD::BRCOND)
3869 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3870 SDValue N0 = N->getOperand(0);
3871 EVT VT = N->getValueType(0);
3873 // fold (ctlz c1) -> c2
3874 if (isa<ConstantSDNode>(N0))
3875 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3879 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
3880 SDValue N0 = N->getOperand(0);
3881 EVT VT = N->getValueType(0);
3883 // fold (ctlz_zero_undef c1) -> c2
3884 if (isa<ConstantSDNode>(N0))
3885 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
3889 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3890 SDValue N0 = N->getOperand(0);
3891 EVT VT = N->getValueType(0);
3893 // fold (cttz c1) -> c2
3894 if (isa<ConstantSDNode>(N0))
3895 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3899 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
3900 SDValue N0 = N->getOperand(0);
3901 EVT VT = N->getValueType(0);
3903 // fold (cttz_zero_undef c1) -> c2
3904 if (isa<ConstantSDNode>(N0))
3905 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0);
3909 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3910 SDValue N0 = N->getOperand(0);
3911 EVT VT = N->getValueType(0);
3913 // fold (ctpop c1) -> c2
3914 if (isa<ConstantSDNode>(N0))
3915 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3919 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3920 SDValue N0 = N->getOperand(0);
3921 SDValue N1 = N->getOperand(1);
3922 SDValue N2 = N->getOperand(2);
3923 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3924 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3925 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3926 EVT VT = N->getValueType(0);
3927 EVT VT0 = N0.getValueType();
3929 // fold (select C, X, X) -> X
3932 // fold (select true, X, Y) -> X
3933 if (N0C && !N0C->isNullValue())
3935 // fold (select false, X, Y) -> Y
3936 if (N0C && N0C->isNullValue())
3938 // fold (select C, 1, X) -> (or C, X)
3939 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3940 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3941 // fold (select C, 0, 1) -> (xor C, 1)
3942 if (VT.isInteger() &&
3945 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) &&
3946 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3949 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3950 N0, DAG.getConstant(1, VT0));
3951 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3952 N0, DAG.getConstant(1, VT0));
3953 AddToWorkList(XORNode.getNode());
3955 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3956 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3958 // fold (select C, 0, X) -> (and (not C), X)
3959 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3960 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3961 AddToWorkList(NOTNode.getNode());
3962 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3964 // fold (select C, X, 1) -> (or (not C), X)
3965 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3966 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3967 AddToWorkList(NOTNode.getNode());
3968 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3970 // fold (select C, X, 0) -> (and C, X)
3971 if (VT == MVT::i1 && N2C && N2C->isNullValue())
3972 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3973 // fold (select X, X, Y) -> (or X, Y)
3974 // fold (select X, 1, Y) -> (or X, Y)
3975 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3976 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3977 // fold (select X, Y, X) -> (and X, Y)
3978 // fold (select X, Y, 0) -> (and X, Y)
3979 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3980 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3982 // If we can fold this based on the true/false value, do so.
3983 if (SimplifySelectOps(N, N1, N2))
3984 return SDValue(N, 0); // Don't revisit N.
3986 // fold selects based on a setcc into other things, such as min/max/abs
3987 if (N0.getOpcode() == ISD::SETCC) {
3989 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3990 // having to say they don't support SELECT_CC on every type the DAG knows
3991 // about, since there is no way to mark an opcode illegal at all value types
3992 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3993 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3994 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3995 N0.getOperand(0), N0.getOperand(1),
3996 N1, N2, N0.getOperand(2));
3997 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
4003 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
4004 SDValue N0 = N->getOperand(0);
4005 SDValue N1 = N->getOperand(1);
4006 SDValue N2 = N->getOperand(2);
4007 SDValue N3 = N->getOperand(3);
4008 SDValue N4 = N->getOperand(4);
4009 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
4011 // fold select_cc lhs, rhs, x, x, cc -> x
4015 // Determine if the condition we're dealing with is constant
4016 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
4017 N0, N1, CC, N->getDebugLoc(), false);
4018 if (SCC.getNode()) AddToWorkList(SCC.getNode());
4020 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
4021 if (!SCCC->isNullValue())
4022 return N2; // cond always true -> true val
4024 return N3; // cond always false -> false val
4027 // Fold to a simpler select_cc
4028 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
4029 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
4030 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
4033 // If we can fold this based on the true/false value, do so.
4034 if (SimplifySelectOps(N, N2, N3))
4035 return SDValue(N, 0); // Don't revisit N.
4037 // fold select_cc into other things, such as min/max/abs
4038 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
4041 SDValue DAGCombiner::visitSETCC(SDNode *N) {
4042 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
4043 cast<CondCodeSDNode>(N->getOperand(2))->get(),
4047 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
4048 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
4049 // transformation. Returns true if extension are possible and the above
4050 // mentioned transformation is profitable.
4051 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
4053 SmallVector<SDNode*, 4> &ExtendNodes,
4054 const TargetLowering &TLI) {
4055 bool HasCopyToRegUses = false;
4056 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
4057 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
4058 UE = N0.getNode()->use_end();
4063 if (UI.getUse().getResNo() != N0.getResNo())
4065 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
4066 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
4067 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
4068 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
4069 // Sign bits will be lost after a zext.
4072 for (unsigned i = 0; i != 2; ++i) {
4073 SDValue UseOp = User->getOperand(i);
4076 if (!isa<ConstantSDNode>(UseOp))
4081 ExtendNodes.push_back(User);
4084 // If truncates aren't free and there are users we can't
4085 // extend, it isn't worthwhile.
4088 // Remember if this value is live-out.
4089 if (User->getOpcode() == ISD::CopyToReg)
4090 HasCopyToRegUses = true;
4093 if (HasCopyToRegUses) {
4094 bool BothLiveOut = false;
4095 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
4097 SDUse &Use = UI.getUse();
4098 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
4104 // Both unextended and extended values are live out. There had better be
4105 // a good reason for the transformation.
4106 return ExtendNodes.size();
4111 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
4112 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
4113 ISD::NodeType ExtType) {
4114 // Extend SetCC uses if necessary.
4115 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4116 SDNode *SetCC = SetCCs[i];
4117 SmallVector<SDValue, 4> Ops;
4119 for (unsigned j = 0; j != 2; ++j) {
4120 SDValue SOp = SetCC->getOperand(j);
4122 Ops.push_back(ExtLoad);
4124 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
4127 Ops.push_back(SetCC->getOperand(2));
4128 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
4129 &Ops[0], Ops.size()));
4133 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
4134 SDValue N0 = N->getOperand(0);
4135 EVT VT = N->getValueType(0);
4137 // fold (sext c1) -> c1
4138 if (isa<ConstantSDNode>(N0))
4139 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
4141 // fold (sext (sext x)) -> (sext x)
4142 // fold (sext (aext x)) -> (sext x)
4143 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4144 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
4147 if (N0.getOpcode() == ISD::TRUNCATE) {
4148 // fold (sext (truncate (load x))) -> (sext (smaller load x))
4149 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
4150 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4151 if (NarrowLoad.getNode()) {
4152 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4153 if (NarrowLoad.getNode() != N0.getNode()) {
4154 CombineTo(N0.getNode(), NarrowLoad);
4155 // CombineTo deleted the truncate, if needed, but not what's under it.
4158 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4161 // See if the value being truncated is already sign extended. If so, just
4162 // eliminate the trunc/sext pair.
4163 SDValue Op = N0.getOperand(0);
4164 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
4165 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
4166 unsigned DestBits = VT.getScalarType().getSizeInBits();
4167 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
4169 if (OpBits == DestBits) {
4170 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
4171 // bits, it is already ready.
4172 if (NumSignBits > DestBits-MidBits)
4174 } else if (OpBits < DestBits) {
4175 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
4176 // bits, just sext from i32.
4177 if (NumSignBits > OpBits-MidBits)
4178 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
4180 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
4181 // bits, just truncate to i32.
4182 if (NumSignBits > OpBits-MidBits)
4183 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4186 // fold (sext (truncate x)) -> (sextinreg x).
4187 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4188 N0.getValueType())) {
4189 if (OpBits < DestBits)
4190 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4191 else if (OpBits > DestBits)
4192 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4193 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4194 DAG.getValueType(N0.getValueType()));
4198 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4199 // None of the supported targets knows how to perform load and sign extend
4200 // on vectors in one instruction. We only perform this transformation on
4202 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4203 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4204 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4205 bool DoXform = true;
4206 SmallVector<SDNode*, 4> SetCCs;
4207 if (!N0.hasOneUse())
4208 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4210 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4211 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4213 LN0->getBasePtr(), LN0->getPointerInfo(),
4215 LN0->isVolatile(), LN0->isNonTemporal(),
4216 LN0->getAlignment());
4217 CombineTo(N, ExtLoad);
4218 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4219 N0.getValueType(), ExtLoad);
4220 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4221 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4223 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4227 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4228 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4229 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4230 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4231 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4232 EVT MemVT = LN0->getMemoryVT();
4233 if ((!LegalOperations && !LN0->isVolatile()) ||
4234 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4235 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4237 LN0->getBasePtr(), LN0->getPointerInfo(),
4239 LN0->isVolatile(), LN0->isNonTemporal(),
4240 LN0->getAlignment());
4241 CombineTo(N, ExtLoad);
4242 CombineTo(N0.getNode(),
4243 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4244 N0.getValueType(), ExtLoad),
4245 ExtLoad.getValue(1));
4246 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4250 // fold (sext (and/or/xor (load x), cst)) ->
4251 // (and/or/xor (sextload x), (sext cst))
4252 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4253 N0.getOpcode() == ISD::XOR) &&
4254 isa<LoadSDNode>(N0.getOperand(0)) &&
4255 N0.getOperand(1).getOpcode() == ISD::Constant &&
4256 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4257 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4258 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4259 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4260 bool DoXform = true;
4261 SmallVector<SDNode*, 4> SetCCs;
4262 if (!N0.hasOneUse())
4263 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4266 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4267 LN0->getChain(), LN0->getBasePtr(),
4268 LN0->getPointerInfo(),
4271 LN0->isNonTemporal(),
4272 LN0->getAlignment());
4273 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4274 Mask = Mask.sext(VT.getSizeInBits());
4275 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4276 ExtLoad, DAG.getConstant(Mask, VT));
4277 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4278 N0.getOperand(0).getDebugLoc(),
4279 N0.getOperand(0).getValueType(), ExtLoad);
4281 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4282 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4284 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4289 if (N0.getOpcode() == ISD::SETCC) {
4290 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4291 // Only do this before legalize for now.
4292 if (VT.isVector() && !LegalOperations) {
4293 EVT N0VT = N0.getOperand(0).getValueType();
4294 // We know that the # elements of the results is the same as the
4295 // # elements of the compare (and the # elements of the compare result
4296 // for that matter). Check to see that they are the same size. If so,
4297 // we know that the element size of the sext'd result matches the
4298 // element size of the compare operands.
4299 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4300 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4302 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4303 // If the desired elements are smaller or larger than the source
4304 // elements we can use a matching integer vector type and then
4305 // truncate/sign extend
4307 EVT MatchingElementType =
4308 EVT::getIntegerVT(*DAG.getContext(),
4309 N0VT.getScalarType().getSizeInBits());
4310 EVT MatchingVectorType =
4311 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4312 N0VT.getVectorNumElements());
4314 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4316 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4317 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4321 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4322 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4324 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4326 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4327 NegOne, DAG.getConstant(0, VT),
4328 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4329 if (SCC.getNode()) return SCC;
4330 if (!LegalOperations ||
4331 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4332 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4333 DAG.getSetCC(N->getDebugLoc(),
4334 TLI.getSetCCResultType(VT),
4335 N0.getOperand(0), N0.getOperand(1),
4336 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4337 NegOne, DAG.getConstant(0, VT));
4340 // fold (sext x) -> (zext x) if the sign bit is known zero.
4341 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4342 DAG.SignBitIsZero(N0))
4343 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4348 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4349 SDValue N0 = N->getOperand(0);
4350 EVT VT = N->getValueType(0);
4352 // fold (zext c1) -> c1
4353 if (isa<ConstantSDNode>(N0))
4354 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4355 // fold (zext (zext x)) -> (zext x)
4356 // fold (zext (aext x)) -> (zext x)
4357 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4358 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4361 // fold (zext (truncate x)) -> (zext x) or
4362 // (zext (truncate x)) -> (truncate x)
4363 // This is valid when the truncated bits of x are already zero.
4364 // FIXME: We should extend this to work for vectors too.
4365 if (N0.getOpcode() == ISD::TRUNCATE && !VT.isVector()) {
4366 SDValue Op = N0.getOperand(0);
4368 = APInt::getBitsSet(Op.getValueSizeInBits(),
4369 N0.getValueSizeInBits(),
4370 std::min(Op.getValueSizeInBits(),
4371 VT.getSizeInBits()));
4372 APInt KnownZero, KnownOne;
4373 DAG.ComputeMaskedBits(Op, TruncatedBits, KnownZero, KnownOne);
4374 if (TruncatedBits == KnownZero) {
4375 if (VT.bitsGT(Op.getValueType()))
4376 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op);
4377 if (VT.bitsLT(Op.getValueType()))
4378 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4384 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4385 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4386 if (N0.getOpcode() == ISD::TRUNCATE) {
4387 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4388 if (NarrowLoad.getNode()) {
4389 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4390 if (NarrowLoad.getNode() != N0.getNode()) {
4391 CombineTo(N0.getNode(), NarrowLoad);
4392 // CombineTo deleted the truncate, if needed, but not what's under it.
4395 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4399 // fold (zext (truncate x)) -> (and x, mask)
4400 if (N0.getOpcode() == ISD::TRUNCATE &&
4401 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4403 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4404 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4405 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4406 if (NarrowLoad.getNode()) {
4407 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4408 if (NarrowLoad.getNode() != N0.getNode()) {
4409 CombineTo(N0.getNode(), NarrowLoad);
4410 // CombineTo deleted the truncate, if needed, but not what's under it.
4413 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4416 SDValue Op = N0.getOperand(0);
4417 if (Op.getValueType().bitsLT(VT)) {
4418 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4419 } else if (Op.getValueType().bitsGT(VT)) {
4420 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4422 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4423 N0.getValueType().getScalarType());
4426 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4427 // if either of the casts is not free.
4428 if (N0.getOpcode() == ISD::AND &&
4429 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4430 N0.getOperand(1).getOpcode() == ISD::Constant &&
4431 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4432 N0.getValueType()) ||
4433 !TLI.isZExtFree(N0.getValueType(), VT))) {
4434 SDValue X = N0.getOperand(0).getOperand(0);
4435 if (X.getValueType().bitsLT(VT)) {
4436 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4437 } else if (X.getValueType().bitsGT(VT)) {
4438 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4440 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4441 Mask = Mask.zext(VT.getSizeInBits());
4442 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4443 X, DAG.getConstant(Mask, VT));
4446 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4447 // None of the supported targets knows how to perform load and vector_zext
4448 // on vectors in one instruction. We only perform this transformation on
4450 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4451 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4452 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4453 bool DoXform = true;
4454 SmallVector<SDNode*, 4> SetCCs;
4455 if (!N0.hasOneUse())
4456 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4458 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4459 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4461 LN0->getBasePtr(), LN0->getPointerInfo(),
4463 LN0->isVolatile(), LN0->isNonTemporal(),
4464 LN0->getAlignment());
4465 CombineTo(N, ExtLoad);
4466 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4467 N0.getValueType(), ExtLoad);
4468 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4470 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4472 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4476 // fold (zext (and/or/xor (load x), cst)) ->
4477 // (and/or/xor (zextload x), (zext cst))
4478 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4479 N0.getOpcode() == ISD::XOR) &&
4480 isa<LoadSDNode>(N0.getOperand(0)) &&
4481 N0.getOperand(1).getOpcode() == ISD::Constant &&
4482 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4483 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4484 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4485 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4486 bool DoXform = true;
4487 SmallVector<SDNode*, 4> SetCCs;
4488 if (!N0.hasOneUse())
4489 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4492 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4493 LN0->getChain(), LN0->getBasePtr(),
4494 LN0->getPointerInfo(),
4497 LN0->isNonTemporal(),
4498 LN0->getAlignment());
4499 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4500 Mask = Mask.zext(VT.getSizeInBits());
4501 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4502 ExtLoad, DAG.getConstant(Mask, VT));
4503 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4504 N0.getOperand(0).getDebugLoc(),
4505 N0.getOperand(0).getValueType(), ExtLoad);
4507 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4508 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4510 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4515 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4516 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4517 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4518 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4519 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4520 EVT MemVT = LN0->getMemoryVT();
4521 if ((!LegalOperations && !LN0->isVolatile()) ||
4522 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4523 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4525 LN0->getBasePtr(), LN0->getPointerInfo(),
4527 LN0->isVolatile(), LN0->isNonTemporal(),
4528 LN0->getAlignment());
4529 CombineTo(N, ExtLoad);
4530 CombineTo(N0.getNode(),
4531 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4533 ExtLoad.getValue(1));
4534 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4538 if (N0.getOpcode() == ISD::SETCC) {
4539 if (!LegalOperations && VT.isVector()) {
4540 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4541 // Only do this before legalize for now.
4542 EVT N0VT = N0.getOperand(0).getValueType();
4543 EVT EltVT = VT.getVectorElementType();
4544 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4545 DAG.getConstant(1, EltVT));
4546 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4547 // We know that the # elements of the results is the same as the
4548 // # elements of the compare (and the # elements of the compare result
4549 // for that matter). Check to see that they are the same size. If so,
4550 // we know that the element size of the sext'd result matches the
4551 // element size of the compare operands.
4552 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4553 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4555 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4556 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4557 &OneOps[0], OneOps.size()));
4559 // If the desired elements are smaller or larger than the source
4560 // elements we can use a matching integer vector type and then
4561 // truncate/sign extend
4562 EVT MatchingElementType =
4563 EVT::getIntegerVT(*DAG.getContext(),
4564 N0VT.getScalarType().getSizeInBits());
4565 EVT MatchingVectorType =
4566 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4567 N0VT.getVectorNumElements());
4569 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4571 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4572 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4573 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4574 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4575 &OneOps[0], OneOps.size()));
4578 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4580 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4581 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4582 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4583 if (SCC.getNode()) return SCC;
4586 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4587 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4588 isa<ConstantSDNode>(N0.getOperand(1)) &&
4589 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4591 SDValue ShAmt = N0.getOperand(1);
4592 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4593 if (N0.getOpcode() == ISD::SHL) {
4594 SDValue InnerZExt = N0.getOperand(0);
4595 // If the original shl may be shifting out bits, do not perform this
4597 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4598 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4599 if (ShAmtVal > KnownZeroBits)
4603 DebugLoc DL = N->getDebugLoc();
4605 // Ensure that the shift amount is wide enough for the shifted value.
4606 if (VT.getSizeInBits() >= 256)
4607 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4609 return DAG.getNode(N0.getOpcode(), DL, VT,
4610 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4617 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4618 SDValue N0 = N->getOperand(0);
4619 EVT VT = N->getValueType(0);
4621 // fold (aext c1) -> c1
4622 if (isa<ConstantSDNode>(N0))
4623 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4624 // fold (aext (aext x)) -> (aext x)
4625 // fold (aext (zext x)) -> (zext x)
4626 // fold (aext (sext x)) -> (sext x)
4627 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4628 N0.getOpcode() == ISD::ZERO_EXTEND ||
4629 N0.getOpcode() == ISD::SIGN_EXTEND)
4630 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4632 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4633 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4634 if (N0.getOpcode() == ISD::TRUNCATE) {
4635 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4636 if (NarrowLoad.getNode()) {
4637 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4638 if (NarrowLoad.getNode() != N0.getNode()) {
4639 CombineTo(N0.getNode(), NarrowLoad);
4640 // CombineTo deleted the truncate, if needed, but not what's under it.
4643 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4647 // fold (aext (truncate x))
4648 if (N0.getOpcode() == ISD::TRUNCATE) {
4649 SDValue TruncOp = N0.getOperand(0);
4650 if (TruncOp.getValueType() == VT)
4651 return TruncOp; // x iff x size == zext size.
4652 if (TruncOp.getValueType().bitsGT(VT))
4653 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4654 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4657 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4658 // if the trunc is not free.
4659 if (N0.getOpcode() == ISD::AND &&
4660 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4661 N0.getOperand(1).getOpcode() == ISD::Constant &&
4662 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4663 N0.getValueType())) {
4664 SDValue X = N0.getOperand(0).getOperand(0);
4665 if (X.getValueType().bitsLT(VT)) {
4666 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4667 } else if (X.getValueType().bitsGT(VT)) {
4668 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4670 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4671 Mask = Mask.zext(VT.getSizeInBits());
4672 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4673 X, DAG.getConstant(Mask, VT));
4676 // fold (aext (load x)) -> (aext (truncate (extload x)))
4677 // None of the supported targets knows how to perform load and any_ext
4678 // on vectors in one instruction. We only perform this transformation on
4680 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4681 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4682 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4683 bool DoXform = true;
4684 SmallVector<SDNode*, 4> SetCCs;
4685 if (!N0.hasOneUse())
4686 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4688 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4689 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4691 LN0->getBasePtr(), LN0->getPointerInfo(),
4693 LN0->isVolatile(), LN0->isNonTemporal(),
4694 LN0->getAlignment());
4695 CombineTo(N, ExtLoad);
4696 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4697 N0.getValueType(), ExtLoad);
4698 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4699 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4701 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4705 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4706 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4707 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4708 if (N0.getOpcode() == ISD::LOAD &&
4709 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4711 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4712 EVT MemVT = LN0->getMemoryVT();
4713 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4714 VT, LN0->getChain(), LN0->getBasePtr(),
4715 LN0->getPointerInfo(), MemVT,
4716 LN0->isVolatile(), LN0->isNonTemporal(),
4717 LN0->getAlignment());
4718 CombineTo(N, ExtLoad);
4719 CombineTo(N0.getNode(),
4720 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4721 N0.getValueType(), ExtLoad),
4722 ExtLoad.getValue(1));
4723 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4726 if (N0.getOpcode() == ISD::SETCC) {
4727 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4728 // Only do this before legalize for now.
4729 if (VT.isVector() && !LegalOperations) {
4730 EVT N0VT = N0.getOperand(0).getValueType();
4731 // We know that the # elements of the results is the same as the
4732 // # elements of the compare (and the # elements of the compare result
4733 // for that matter). Check to see that they are the same size. If so,
4734 // we know that the element size of the sext'd result matches the
4735 // element size of the compare operands.
4736 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4737 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4739 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4740 // If the desired elements are smaller or larger than the source
4741 // elements we can use a matching integer vector type and then
4742 // truncate/sign extend
4744 EVT MatchingElementType =
4745 EVT::getIntegerVT(*DAG.getContext(),
4746 N0VT.getScalarType().getSizeInBits());
4747 EVT MatchingVectorType =
4748 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4749 N0VT.getVectorNumElements());
4751 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4753 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4754 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4758 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4760 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4761 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4762 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4770 /// GetDemandedBits - See if the specified operand can be simplified with the
4771 /// knowledge that only the bits specified by Mask are used. If so, return the
4772 /// simpler operand, otherwise return a null SDValue.
4773 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4774 switch (V.getOpcode()) {
4776 case ISD::Constant: {
4777 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
4778 assert(CV != 0 && "Const value should be ConstSDNode.");
4779 const APInt &CVal = CV->getAPIntValue();
4780 APInt NewVal = CVal & Mask;
4781 if (NewVal != CVal) {
4782 return DAG.getConstant(NewVal, V.getValueType());
4788 // If the LHS or RHS don't contribute bits to the or, drop them.
4789 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4790 return V.getOperand(1);
4791 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4792 return V.getOperand(0);
4795 // Only look at single-use SRLs.
4796 if (!V.getNode()->hasOneUse())
4798 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4799 // See if we can recursively simplify the LHS.
4800 unsigned Amt = RHSC->getZExtValue();
4802 // Watch out for shift count overflow though.
4803 if (Amt >= Mask.getBitWidth()) break;
4804 APInt NewMask = Mask << Amt;
4805 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4806 if (SimplifyLHS.getNode())
4807 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4808 SimplifyLHS, V.getOperand(1));
4814 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4815 /// bits and then truncated to a narrower type and where N is a multiple
4816 /// of number of bits of the narrower type, transform it to a narrower load
4817 /// from address + N / num of bits of new type. If the result is to be
4818 /// extended, also fold the extension to form a extending load.
4819 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4820 unsigned Opc = N->getOpcode();
4822 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4823 SDValue N0 = N->getOperand(0);
4824 EVT VT = N->getValueType(0);
4827 // This transformation isn't valid for vector loads.
4831 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4833 if (Opc == ISD::SIGN_EXTEND_INREG) {
4834 ExtType = ISD::SEXTLOAD;
4835 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4836 } else if (Opc == ISD::SRL) {
4837 // Another special-case: SRL is basically zero-extending a narrower value.
4838 ExtType = ISD::ZEXTLOAD;
4840 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4841 if (!N01) return SDValue();
4842 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4843 VT.getSizeInBits() - N01->getZExtValue());
4845 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
4848 unsigned EVTBits = ExtVT.getSizeInBits();
4850 // Do not generate loads of non-round integer types since these can
4851 // be expensive (and would be wrong if the type is not byte sized).
4852 if (!ExtVT.isRound())
4856 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4857 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4858 ShAmt = N01->getZExtValue();
4859 // Is the shift amount a multiple of size of VT?
4860 if ((ShAmt & (EVTBits-1)) == 0) {
4861 N0 = N0.getOperand(0);
4862 // Is the load width a multiple of size of VT?
4863 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4867 // At this point, we must have a load or else we can't do the transform.
4868 if (!isa<LoadSDNode>(N0)) return SDValue();
4870 // If the shift amount is larger than the input type then we're not
4871 // accessing any of the loaded bytes. If the load was a zextload/extload
4872 // then the result of the shift+trunc is zero/undef (handled elsewhere).
4873 // If the load was a sextload then the result is a splat of the sign bit
4874 // of the extended byte. This is not worth optimizing for.
4875 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
4880 // If the load is shifted left (and the result isn't shifted back right),
4881 // we can fold the truncate through the shift.
4882 unsigned ShLeftAmt = 0;
4883 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
4884 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
4885 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4886 ShLeftAmt = N01->getZExtValue();
4887 N0 = N0.getOperand(0);
4891 // If we haven't found a load, we can't narrow it. Don't transform one with
4892 // multiple uses, this would require adding a new load.
4893 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
4894 // Don't change the width of a volatile load.
4895 cast<LoadSDNode>(N0)->isVolatile())
4898 // Verify that we are actually reducing a load width here.
4899 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
4902 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4903 EVT PtrType = N0.getOperand(1).getValueType();
4905 // For big endian targets, we need to adjust the offset to the pointer to
4906 // load the correct bytes.
4907 if (TLI.isBigEndian()) {
4908 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4909 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4910 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4913 uint64_t PtrOff = ShAmt / 8;
4914 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4915 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4916 PtrType, LN0->getBasePtr(),
4917 DAG.getConstant(PtrOff, PtrType));
4918 AddToWorkList(NewPtr.getNode());
4921 if (ExtType == ISD::NON_EXTLOAD)
4922 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4923 LN0->getPointerInfo().getWithOffset(PtrOff),
4924 LN0->isVolatile(), LN0->isNonTemporal(),
4925 LN0->isInvariant(), NewAlign);
4927 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
4928 LN0->getPointerInfo().getWithOffset(PtrOff),
4929 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4932 // Replace the old load's chain with the new load's chain.
4933 WorkListRemover DeadNodes(*this);
4934 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4937 // Shift the result left, if we've swallowed a left shift.
4938 SDValue Result = Load;
4939 if (ShLeftAmt != 0) {
4940 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
4941 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
4943 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
4944 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
4947 // Return the new loaded value.
4951 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4952 SDValue N0 = N->getOperand(0);
4953 SDValue N1 = N->getOperand(1);
4954 EVT VT = N->getValueType(0);
4955 EVT EVT = cast<VTSDNode>(N1)->getVT();
4956 unsigned VTBits = VT.getScalarType().getSizeInBits();
4957 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4959 // fold (sext_in_reg c1) -> c1
4960 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4961 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4963 // If the input is already sign extended, just drop the extension.
4964 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4967 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4968 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4969 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4970 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4971 N0.getOperand(0), N1);
4974 // fold (sext_in_reg (sext x)) -> (sext x)
4975 // fold (sext_in_reg (aext x)) -> (sext x)
4976 // if x is small enough.
4977 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4978 SDValue N00 = N0.getOperand(0);
4979 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4980 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4981 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4984 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4985 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4986 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4988 // fold operands of sext_in_reg based on knowledge that the top bits are not
4990 if (SimplifyDemandedBits(SDValue(N, 0)))
4991 return SDValue(N, 0);
4993 // fold (sext_in_reg (load x)) -> (smaller sextload x)
4994 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4995 SDValue NarrowLoad = ReduceLoadWidth(N);
4996 if (NarrowLoad.getNode())
4999 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
5000 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
5001 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
5002 if (N0.getOpcode() == ISD::SRL) {
5003 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
5004 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
5005 // We can turn this into an SRA iff the input to the SRL is already sign
5007 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
5008 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
5009 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
5010 N0.getOperand(0), N0.getOperand(1));
5014 // fold (sext_inreg (extload x)) -> (sextload x)
5015 if (ISD::isEXTLoad(N0.getNode()) &&
5016 ISD::isUNINDEXEDLoad(N0.getNode()) &&
5017 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5018 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5019 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5020 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5021 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5023 LN0->getBasePtr(), LN0->getPointerInfo(),
5025 LN0->isVolatile(), LN0->isNonTemporal(),
5026 LN0->getAlignment());
5027 CombineTo(N, ExtLoad);
5028 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5029 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5031 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
5032 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5034 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
5035 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5036 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
5037 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5038 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
5040 LN0->getBasePtr(), LN0->getPointerInfo(),
5042 LN0->isVolatile(), LN0->isNonTemporal(),
5043 LN0->getAlignment());
5044 CombineTo(N, ExtLoad);
5045 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
5046 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5049 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
5050 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
5051 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
5052 N0.getOperand(1), false);
5053 if (BSwap.getNode() != 0)
5054 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
5061 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
5062 SDValue N0 = N->getOperand(0);
5063 EVT VT = N->getValueType(0);
5064 bool isLE = TLI.isLittleEndian();
5067 if (N0.getValueType() == N->getValueType(0))
5069 // fold (truncate c1) -> c1
5070 if (isa<ConstantSDNode>(N0))
5071 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
5072 // fold (truncate (truncate x)) -> (truncate x)
5073 if (N0.getOpcode() == ISD::TRUNCATE)
5074 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5075 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
5076 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
5077 N0.getOpcode() == ISD::SIGN_EXTEND ||
5078 N0.getOpcode() == ISD::ANY_EXTEND) {
5079 if (N0.getOperand(0).getValueType().bitsLT(VT))
5080 // if the source is smaller than the dest, we still need an extend
5081 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
5083 else if (N0.getOperand(0).getValueType().bitsGT(VT))
5084 // if the source is larger than the dest, than we just need the truncate
5085 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
5087 // if the source and dest are the same type, we can drop both the extend
5088 // and the truncate.
5089 return N0.getOperand(0);
5092 // Fold extract-and-trunc into a narrow extract. For example:
5093 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
5094 // i32 y = TRUNCATE(i64 x)
5096 // v16i8 b = BITCAST (v2i64 val)
5097 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
5099 // Note: We only run this optimization after type legalization (which often
5100 // creates this pattern) and before operation legalization after which
5101 // we need to be more careful about the vector instructions that we generate.
5102 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5103 LegalTypes && !LegalOperations && N0->hasOneUse()) {
5105 EVT VecTy = N0.getOperand(0).getValueType();
5106 EVT ExTy = N0.getValueType();
5107 EVT TrTy = N->getValueType(0);
5109 unsigned NumElem = VecTy.getVectorNumElements();
5110 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
5112 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
5113 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
5115 SDValue EltNo = N0->getOperand(1);
5116 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
5117 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5119 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
5121 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5122 NVT, N0.getOperand(0));
5124 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
5125 N->getDebugLoc(), TrTy, V,
5126 DAG.getConstant(Index, MVT::i32));
5130 // See if we can simplify the input to this truncate through knowledge that
5131 // only the low bits are being used.
5132 // For example "trunc (or (shl x, 8), y)" // -> trunc y
5133 // Currently we only perform this optimization on scalars because vectors
5134 // may have different active low bits.
5135 if (!VT.isVector()) {
5137 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
5138 VT.getSizeInBits()));
5139 if (Shorter.getNode())
5140 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
5142 // fold (truncate (load x)) -> (smaller load x)
5143 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
5144 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
5145 SDValue Reduced = ReduceLoadWidth(N);
5146 if (Reduced.getNode())
5150 // Simplify the operands using demanded-bits information.
5151 if (!VT.isVector() &&
5152 SimplifyDemandedBits(SDValue(N, 0)))
5153 return SDValue(N, 0);
5158 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
5159 SDValue Elt = N->getOperand(i);
5160 if (Elt.getOpcode() != ISD::MERGE_VALUES)
5161 return Elt.getNode();
5162 return Elt.getOperand(Elt.getResNo()).getNode();
5165 /// CombineConsecutiveLoads - build_pair (load, load) -> load
5166 /// if load locations are consecutive.
5167 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
5168 assert(N->getOpcode() == ISD::BUILD_PAIR);
5170 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
5171 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
5172 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
5173 LD1->getPointerInfo().getAddrSpace() !=
5174 LD2->getPointerInfo().getAddrSpace())
5176 EVT LD1VT = LD1->getValueType(0);
5178 if (ISD::isNON_EXTLoad(LD2) &&
5180 // If both are volatile this would reduce the number of volatile loads.
5181 // If one is volatile it might be ok, but play conservative and bail out.
5182 !LD1->isVolatile() &&
5183 !LD2->isVolatile() &&
5184 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
5185 unsigned Align = LD1->getAlignment();
5186 unsigned NewAlign = TLI.getTargetData()->
5187 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5189 if (NewAlign <= Align &&
5190 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
5191 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
5192 LD1->getBasePtr(), LD1->getPointerInfo(),
5193 false, false, false, Align);
5199 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
5200 SDValue N0 = N->getOperand(0);
5201 EVT VT = N->getValueType(0);
5203 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
5204 // Only do this before legalize, since afterward the target may be depending
5205 // on the bitconvert.
5206 // First check to see if this is all constant.
5208 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
5210 bool isSimple = true;
5211 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
5212 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
5213 N0.getOperand(i).getOpcode() != ISD::Constant &&
5214 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
5219 EVT DestEltVT = N->getValueType(0).getVectorElementType();
5220 assert(!DestEltVT.isVector() &&
5221 "Element type of vector ValueType must not be vector!");
5223 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
5226 // If the input is a constant, let getNode fold it.
5227 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
5228 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
5229 if (Res.getNode() != N) {
5230 if (!LegalOperations ||
5231 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
5234 // Folding it resulted in an illegal node, and it's too late to
5235 // do that. Clean up the old node and forego the transformation.
5236 // Ideally this won't happen very often, because instcombine
5237 // and the earlier dagcombine runs (where illegal nodes are
5238 // permitted) should have folded most of them already.
5239 DAG.DeleteNode(Res.getNode());
5243 // (conv (conv x, t1), t2) -> (conv x, t2)
5244 if (N0.getOpcode() == ISD::BITCAST)
5245 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
5248 // fold (conv (load x)) -> (load (conv*)x)
5249 // If the resultant load doesn't need a higher alignment than the original!
5250 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
5251 // Do not change the width of a volatile load.
5252 !cast<LoadSDNode>(N0)->isVolatile() &&
5253 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
5254 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5255 unsigned Align = TLI.getTargetData()->
5256 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
5257 unsigned OrigAlign = LN0->getAlignment();
5259 if (Align <= OrigAlign) {
5260 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5261 LN0->getBasePtr(), LN0->getPointerInfo(),
5262 LN0->isVolatile(), LN0->isNonTemporal(),
5263 LN0->isInvariant(), OrigAlign);
5265 CombineTo(N0.getNode(),
5266 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5267 N0.getValueType(), Load),
5273 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5274 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5275 // This often reduces constant pool loads.
5276 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
5277 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
5278 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5280 AddToWorkList(NewConv.getNode());
5282 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5283 if (N0.getOpcode() == ISD::FNEG)
5284 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5285 NewConv, DAG.getConstant(SignBit, VT));
5286 assert(N0.getOpcode() == ISD::FABS);
5287 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5288 NewConv, DAG.getConstant(~SignBit, VT));
5291 // fold (bitconvert (fcopysign cst, x)) ->
5292 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5293 // Note that we don't handle (copysign x, cst) because this can always be
5294 // folded to an fneg or fabs.
5295 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5296 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5297 VT.isInteger() && !VT.isVector()) {
5298 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5299 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5300 if (isTypeLegal(IntXVT)) {
5301 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5302 IntXVT, N0.getOperand(1));
5303 AddToWorkList(X.getNode());
5305 // If X has a different width than the result/lhs, sext it or truncate it.
5306 unsigned VTWidth = VT.getSizeInBits();
5307 if (OrigXWidth < VTWidth) {
5308 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5309 AddToWorkList(X.getNode());
5310 } else if (OrigXWidth > VTWidth) {
5311 // To get the sign bit in the right place, we have to shift it right
5312 // before truncating.
5313 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5314 X.getValueType(), X,
5315 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5316 AddToWorkList(X.getNode());
5317 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5318 AddToWorkList(X.getNode());
5321 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5322 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5323 X, DAG.getConstant(SignBit, VT));
5324 AddToWorkList(X.getNode());
5326 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5327 VT, N0.getOperand(0));
5328 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5329 Cst, DAG.getConstant(~SignBit, VT));
5330 AddToWorkList(Cst.getNode());
5332 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5336 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5337 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5338 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5339 if (CombineLD.getNode())
5346 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5347 EVT VT = N->getValueType(0);
5348 return CombineConsecutiveLoads(N, VT);
5351 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5352 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5353 /// destination element value type.
5354 SDValue DAGCombiner::
5355 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5356 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5358 // If this is already the right type, we're done.
5359 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5361 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5362 unsigned DstBitSize = DstEltVT.getSizeInBits();
5364 // If this is a conversion of N elements of one type to N elements of another
5365 // type, convert each element. This handles FP<->INT cases.
5366 if (SrcBitSize == DstBitSize) {
5367 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5368 BV->getValueType(0).getVectorNumElements());
5370 // Due to the FP element handling below calling this routine recursively,
5371 // we can end up with a scalar-to-vector node here.
5372 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5373 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5374 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5375 DstEltVT, BV->getOperand(0)));
5377 SmallVector<SDValue, 8> Ops;
5378 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5379 SDValue Op = BV->getOperand(i);
5380 // If the vector element type is not legal, the BUILD_VECTOR operands
5381 // are promoted and implicitly truncated. Make that explicit here.
5382 if (Op.getValueType() != SrcEltVT)
5383 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5384 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5386 AddToWorkList(Ops.back().getNode());
5388 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5389 &Ops[0], Ops.size());
5392 // Otherwise, we're growing or shrinking the elements. To avoid having to
5393 // handle annoying details of growing/shrinking FP values, we convert them to
5395 if (SrcEltVT.isFloatingPoint()) {
5396 // Convert the input float vector to a int vector where the elements are the
5398 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5399 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5400 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5404 // Now we know the input is an integer vector. If the output is a FP type,
5405 // convert to integer first, then to FP of the right size.
5406 if (DstEltVT.isFloatingPoint()) {
5407 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5408 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5409 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5411 // Next, convert to FP elements of the same size.
5412 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5415 // Okay, we know the src/dst types are both integers of differing types.
5416 // Handling growing first.
5417 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5418 if (SrcBitSize < DstBitSize) {
5419 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5421 SmallVector<SDValue, 8> Ops;
5422 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5423 i += NumInputsPerOutput) {
5424 bool isLE = TLI.isLittleEndian();
5425 APInt NewBits = APInt(DstBitSize, 0);
5426 bool EltIsUndef = true;
5427 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5428 // Shift the previously computed bits over.
5429 NewBits <<= SrcBitSize;
5430 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5431 if (Op.getOpcode() == ISD::UNDEF) continue;
5434 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5435 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5439 Ops.push_back(DAG.getUNDEF(DstEltVT));
5441 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5444 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5445 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5446 &Ops[0], Ops.size());
5449 // Finally, this must be the case where we are shrinking elements: each input
5450 // turns into multiple outputs.
5451 bool isS2V = ISD::isScalarToVector(BV);
5452 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5453 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5454 NumOutputsPerInput*BV->getNumOperands());
5455 SmallVector<SDValue, 8> Ops;
5457 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5458 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5459 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5460 Ops.push_back(DAG.getUNDEF(DstEltVT));
5464 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5465 getAPIntValue().zextOrTrunc(SrcBitSize);
5467 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5468 APInt ThisVal = OpVal.trunc(DstBitSize);
5469 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5470 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5471 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5472 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5474 OpVal = OpVal.lshr(DstBitSize);
5477 // For big endian targets, swap the order of the pieces of each element.
5478 if (TLI.isBigEndian())
5479 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5482 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5483 &Ops[0], Ops.size());
5486 SDValue DAGCombiner::visitFADD(SDNode *N) {
5487 SDValue N0 = N->getOperand(0);
5488 SDValue N1 = N->getOperand(1);
5489 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5490 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5491 EVT VT = N->getValueType(0);
5494 if (VT.isVector()) {
5495 SDValue FoldedVOp = SimplifyVBinOp(N);
5496 if (FoldedVOp.getNode()) return FoldedVOp;
5499 // fold (fadd c1, c2) -> (fadd c1, c2)
5500 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5501 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5502 // canonicalize constant to RHS
5503 if (N0CFP && !N1CFP)
5504 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5505 // fold (fadd A, 0) -> A
5506 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5507 N1CFP->getValueAPF().isZero())
5509 // fold (fadd A, (fneg B)) -> (fsub A, B)
5510 if (isNegatibleForFree(N1, LegalOperations, &DAG.getTarget().Options) == 2)
5511 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5512 GetNegatedExpression(N1, DAG, LegalOperations));
5513 // fold (fadd (fneg A), B) -> (fsub B, A)
5514 if (isNegatibleForFree(N0, LegalOperations, &DAG.getTarget().Options) == 2)
5515 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5516 GetNegatedExpression(N0, DAG, LegalOperations));
5518 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5519 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP &&
5520 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
5521 isa<ConstantFPSDNode>(N0.getOperand(1)))
5522 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5523 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5524 N0.getOperand(1), N1));
5529 SDValue DAGCombiner::visitFSUB(SDNode *N) {
5530 SDValue N0 = N->getOperand(0);
5531 SDValue N1 = N->getOperand(1);
5532 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5533 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5534 EVT VT = N->getValueType(0);
5537 if (VT.isVector()) {
5538 SDValue FoldedVOp = SimplifyVBinOp(N);
5539 if (FoldedVOp.getNode()) return FoldedVOp;
5542 // fold (fsub c1, c2) -> c1-c2
5543 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5544 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5545 // fold (fsub A, 0) -> A
5546 if (DAG.getTarget().Options.UnsafeFPMath &&
5547 N1CFP && N1CFP->getValueAPF().isZero())
5549 // fold (fsub 0, B) -> -B
5550 if (DAG.getTarget().Options.UnsafeFPMath &&
5551 N0CFP && N0CFP->getValueAPF().isZero()) {
5552 if (isNegatibleForFree(N1, LegalOperations, &DAG.getTarget().Options))
5553 return GetNegatedExpression(N1, DAG, LegalOperations);
5554 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5555 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
5557 // fold (fsub A, (fneg B)) -> (fadd A, B)
5558 if (isNegatibleForFree(N1, LegalOperations, &DAG.getTarget().Options))
5559 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
5560 GetNegatedExpression(N1, DAG, LegalOperations));
5565 SDValue DAGCombiner::visitFMUL(SDNode *N) {
5566 SDValue N0 = N->getOperand(0);
5567 SDValue N1 = N->getOperand(1);
5568 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5569 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5570 EVT VT = N->getValueType(0);
5573 if (VT.isVector()) {
5574 SDValue FoldedVOp = SimplifyVBinOp(N);
5575 if (FoldedVOp.getNode()) return FoldedVOp;
5578 // fold (fmul c1, c2) -> c1*c2
5579 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5580 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5581 // canonicalize constant to RHS
5582 if (N0CFP && !N1CFP)
5583 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5584 // fold (fmul A, 0) -> 0
5585 if (DAG.getTarget().Options.UnsafeFPMath &&
5586 N1CFP && N1CFP->getValueAPF().isZero())
5588 // fold (fmul A, 0) -> 0, vector edition.
5589 if (DAG.getTarget().Options.UnsafeFPMath &&
5590 ISD::isBuildVectorAllZeros(N1.getNode()))
5592 // fold (fmul X, 2.0) -> (fadd X, X)
5593 if (N1CFP && N1CFP->isExactlyValue(+2.0))
5594 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5595 // fold (fmul X, -1.0) -> (fneg X)
5596 if (N1CFP && N1CFP->isExactlyValue(-1.0))
5597 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5598 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5600 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5601 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations,
5602 &DAG.getTarget().Options)) {
5603 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations,
5604 &DAG.getTarget().Options)) {
5605 // Both can be negated for free, check to see if at least one is cheaper
5607 if (LHSNeg == 2 || RHSNeg == 2)
5608 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5609 GetNegatedExpression(N0, DAG, LegalOperations),
5610 GetNegatedExpression(N1, DAG, LegalOperations));
5614 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5615 if (DAG.getTarget().Options.UnsafeFPMath &&
5616 N1CFP && N0.getOpcode() == ISD::FMUL &&
5617 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5618 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5619 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5620 N0.getOperand(1), N1));
5625 SDValue DAGCombiner::visitFDIV(SDNode *N) {
5626 SDValue N0 = N->getOperand(0);
5627 SDValue N1 = N->getOperand(1);
5628 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5629 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5630 EVT VT = N->getValueType(0);
5633 if (VT.isVector()) {
5634 SDValue FoldedVOp = SimplifyVBinOp(N);
5635 if (FoldedVOp.getNode()) return FoldedVOp;
5638 // fold (fdiv c1, c2) -> c1/c2
5639 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5640 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
5643 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
5644 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations,
5645 &DAG.getTarget().Options)) {
5646 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations,
5647 &DAG.getTarget().Options)) {
5648 // Both can be negated for free, check to see if at least one is cheaper
5650 if (LHSNeg == 2 || RHSNeg == 2)
5651 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
5652 GetNegatedExpression(N0, DAG, LegalOperations),
5653 GetNegatedExpression(N1, DAG, LegalOperations));
5660 SDValue DAGCombiner::visitFREM(SDNode *N) {
5661 SDValue N0 = N->getOperand(0);
5662 SDValue N1 = N->getOperand(1);
5663 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5664 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5665 EVT VT = N->getValueType(0);
5667 // fold (frem c1, c2) -> fmod(c1,c2)
5668 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5669 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
5674 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
5675 SDValue N0 = N->getOperand(0);
5676 SDValue N1 = N->getOperand(1);
5677 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5678 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5679 EVT VT = N->getValueType(0);
5681 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
5682 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
5685 const APFloat& V = N1CFP->getValueAPF();
5686 // copysign(x, c1) -> fabs(x) iff ispos(c1)
5687 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
5688 if (!V.isNegative()) {
5689 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
5690 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5692 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5693 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
5694 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
5698 // copysign(fabs(x), y) -> copysign(x, y)
5699 // copysign(fneg(x), y) -> copysign(x, y)
5700 // copysign(copysign(x,z), y) -> copysign(x, y)
5701 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
5702 N0.getOpcode() == ISD::FCOPYSIGN)
5703 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5704 N0.getOperand(0), N1);
5706 // copysign(x, abs(y)) -> abs(x)
5707 if (N1.getOpcode() == ISD::FABS)
5708 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5710 // copysign(x, copysign(y,z)) -> copysign(x, z)
5711 if (N1.getOpcode() == ISD::FCOPYSIGN)
5712 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5713 N0, N1.getOperand(1));
5715 // copysign(x, fp_extend(y)) -> copysign(x, y)
5716 // copysign(x, fp_round(y)) -> copysign(x, y)
5717 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
5718 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5719 N0, N1.getOperand(0));
5724 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
5725 SDValue N0 = N->getOperand(0);
5726 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5727 EVT VT = N->getValueType(0);
5728 EVT OpVT = N0.getValueType();
5730 // fold (sint_to_fp c1) -> c1fp
5731 if (N0C && OpVT != MVT::ppcf128 &&
5732 // ...but only if the target supports immediate floating-point values
5733 (!LegalOperations ||
5734 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5735 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5737 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
5738 // but UINT_TO_FP is legal on this target, try to convert.
5739 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
5740 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
5741 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
5742 if (DAG.SignBitIsZero(N0))
5743 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5749 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
5750 SDValue N0 = N->getOperand(0);
5751 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5752 EVT VT = N->getValueType(0);
5753 EVT OpVT = N0.getValueType();
5755 // fold (uint_to_fp c1) -> c1fp
5756 if (N0C && OpVT != MVT::ppcf128 &&
5757 // ...but only if the target supports immediate floating-point values
5758 (!LegalOperations ||
5759 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5760 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5762 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
5763 // but SINT_TO_FP is legal on this target, try to convert.
5764 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
5765 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
5766 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
5767 if (DAG.SignBitIsZero(N0))
5768 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5774 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
5775 SDValue N0 = N->getOperand(0);
5776 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5777 EVT VT = N->getValueType(0);
5779 // fold (fp_to_sint c1fp) -> c1
5781 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
5786 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
5787 SDValue N0 = N->getOperand(0);
5788 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5789 EVT VT = N->getValueType(0);
5791 // fold (fp_to_uint c1fp) -> c1
5792 if (N0CFP && VT != MVT::ppcf128)
5793 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
5798 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
5799 SDValue N0 = N->getOperand(0);
5800 SDValue N1 = N->getOperand(1);
5801 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5802 EVT VT = N->getValueType(0);
5804 // fold (fp_round c1fp) -> c1fp
5805 if (N0CFP && N0.getValueType() != MVT::ppcf128)
5806 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
5808 // fold (fp_round (fp_extend x)) -> x
5809 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
5810 return N0.getOperand(0);
5812 // fold (fp_round (fp_round x)) -> (fp_round x)
5813 if (N0.getOpcode() == ISD::FP_ROUND) {
5814 // This is a value preserving truncation if both round's are.
5815 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
5816 N0.getNode()->getConstantOperandVal(1) == 1;
5817 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
5818 DAG.getIntPtrConstant(IsTrunc));
5821 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
5822 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
5823 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
5824 N0.getOperand(0), N1);
5825 AddToWorkList(Tmp.getNode());
5826 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5827 Tmp, N0.getOperand(1));
5833 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
5834 SDValue N0 = N->getOperand(0);
5835 EVT VT = N->getValueType(0);
5836 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5837 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5839 // fold (fp_round_inreg c1fp) -> c1fp
5840 if (N0CFP && isTypeLegal(EVT)) {
5841 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
5842 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
5848 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
5849 SDValue N0 = N->getOperand(0);
5850 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5851 EVT VT = N->getValueType(0);
5853 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
5854 if (N->hasOneUse() &&
5855 N->use_begin()->getOpcode() == ISD::FP_ROUND)
5858 // fold (fp_extend c1fp) -> c1fp
5859 if (N0CFP && VT != MVT::ppcf128)
5860 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
5862 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
5864 if (N0.getOpcode() == ISD::FP_ROUND
5865 && N0.getNode()->getConstantOperandVal(1) == 1) {
5866 SDValue In = N0.getOperand(0);
5867 if (In.getValueType() == VT) return In;
5868 if (VT.bitsLT(In.getValueType()))
5869 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
5870 In, N0.getOperand(1));
5871 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
5874 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
5875 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
5876 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5877 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5878 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5879 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
5881 LN0->getBasePtr(), LN0->getPointerInfo(),
5883 LN0->isVolatile(), LN0->isNonTemporal(),
5884 LN0->getAlignment());
5885 CombineTo(N, ExtLoad);
5886 CombineTo(N0.getNode(),
5887 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
5888 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
5889 ExtLoad.getValue(1));
5890 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5896 SDValue DAGCombiner::visitFNEG(SDNode *N) {
5897 SDValue N0 = N->getOperand(0);
5898 EVT VT = N->getValueType(0);
5900 if (isNegatibleForFree(N0, LegalOperations, &DAG.getTarget().Options))
5901 return GetNegatedExpression(N0, DAG, LegalOperations);
5903 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
5904 // constant pool values.
5905 if (N0.getOpcode() == ISD::BITCAST &&
5907 N0.getNode()->hasOneUse() &&
5908 N0.getOperand(0).getValueType().isInteger()) {
5909 SDValue Int = N0.getOperand(0);
5910 EVT IntVT = Int.getValueType();
5911 if (IntVT.isInteger() && !IntVT.isVector()) {
5912 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5913 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5914 AddToWorkList(Int.getNode());
5915 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5923 SDValue DAGCombiner::visitFABS(SDNode *N) {
5924 SDValue N0 = N->getOperand(0);
5925 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5926 EVT VT = N->getValueType(0);
5928 // fold (fabs c1) -> fabs(c1)
5929 if (N0CFP && VT != MVT::ppcf128)
5930 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5931 // fold (fabs (fabs x)) -> (fabs x)
5932 if (N0.getOpcode() == ISD::FABS)
5933 return N->getOperand(0);
5934 // fold (fabs (fneg x)) -> (fabs x)
5935 // fold (fabs (fcopysign x, y)) -> (fabs x)
5936 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5937 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5939 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5940 // constant pool values.
5941 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
5942 N0.getOperand(0).getValueType().isInteger() &&
5943 !N0.getOperand(0).getValueType().isVector()) {
5944 SDValue Int = N0.getOperand(0);
5945 EVT IntVT = Int.getValueType();
5946 if (IntVT.isInteger() && !IntVT.isVector()) {
5947 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5948 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5949 AddToWorkList(Int.getNode());
5950 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5951 N->getValueType(0), Int);
5958 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
5959 SDValue Chain = N->getOperand(0);
5960 SDValue N1 = N->getOperand(1);
5961 SDValue N2 = N->getOperand(2);
5963 // If N is a constant we could fold this into a fallthrough or unconditional
5964 // branch. However that doesn't happen very often in normal code, because
5965 // Instcombine/SimplifyCFG should have handled the available opportunities.
5966 // If we did this folding here, it would be necessary to update the
5967 // MachineBasicBlock CFG, which is awkward.
5969 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5971 if (N1.getOpcode() == ISD::SETCC &&
5972 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5973 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5974 Chain, N1.getOperand(2),
5975 N1.getOperand(0), N1.getOperand(1), N2);
5978 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
5979 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
5980 (N1.getOperand(0).hasOneUse() &&
5981 N1.getOperand(0).getOpcode() == ISD::SRL))) {
5983 if (N1.getOpcode() == ISD::TRUNCATE) {
5984 // Look pass the truncate.
5985 Trunc = N1.getNode();
5986 N1 = N1.getOperand(0);
5989 // Match this pattern so that we can generate simpler code:
5992 // %b = and i32 %a, 2
5993 // %c = srl i32 %b, 1
5994 // brcond i32 %c ...
5999 // %b = and i32 %a, 2
6000 // %c = setcc eq %b, 0
6003 // This applies only when the AND constant value has one bit set and the
6004 // SRL constant is equal to the log2 of the AND constant. The back-end is
6005 // smart enough to convert the result into a TEST/JMP sequence.
6006 SDValue Op0 = N1.getOperand(0);
6007 SDValue Op1 = N1.getOperand(1);
6009 if (Op0.getOpcode() == ISD::AND &&
6010 Op1.getOpcode() == ISD::Constant) {
6011 SDValue AndOp1 = Op0.getOperand(1);
6013 if (AndOp1.getOpcode() == ISD::Constant) {
6014 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
6016 if (AndConst.isPowerOf2() &&
6017 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
6019 DAG.getSetCC(N->getDebugLoc(),
6020 TLI.getSetCCResultType(Op0.getValueType()),
6021 Op0, DAG.getConstant(0, Op0.getValueType()),
6024 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6025 MVT::Other, Chain, SetCC, N2);
6026 // Don't add the new BRCond into the worklist or else SimplifySelectCC
6027 // will convert it back to (X & C1) >> C2.
6028 CombineTo(N, NewBRCond, false);
6029 // Truncate is dead.
6031 removeFromWorkList(Trunc);
6032 DAG.DeleteNode(Trunc);
6034 // Replace the uses of SRL with SETCC
6035 WorkListRemover DeadNodes(*this);
6036 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
6037 removeFromWorkList(N1.getNode());
6038 DAG.DeleteNode(N1.getNode());
6039 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6045 // Restore N1 if the above transformation doesn't match.
6046 N1 = N->getOperand(1);
6049 // Transform br(xor(x, y)) -> br(x != y)
6050 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
6051 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
6052 SDNode *TheXor = N1.getNode();
6053 SDValue Op0 = TheXor->getOperand(0);
6054 SDValue Op1 = TheXor->getOperand(1);
6055 if (Op0.getOpcode() == Op1.getOpcode()) {
6056 // Avoid missing important xor optimizations.
6057 SDValue Tmp = visitXOR(TheXor);
6058 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
6059 DEBUG(dbgs() << "\nReplacing.8 ";
6061 dbgs() << "\nWith: ";
6062 Tmp.getNode()->dump(&DAG);
6064 WorkListRemover DeadNodes(*this);
6065 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
6066 removeFromWorkList(TheXor);
6067 DAG.DeleteNode(TheXor);
6068 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6069 MVT::Other, Chain, Tmp, N2);
6073 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
6075 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
6076 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
6077 Op0.getOpcode() == ISD::XOR) {
6078 TheXor = Op0.getNode();
6082 EVT SetCCVT = N1.getValueType();
6084 SetCCVT = TLI.getSetCCResultType(SetCCVT);
6085 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
6088 Equal ? ISD::SETEQ : ISD::SETNE);
6089 // Replace the uses of XOR with SETCC
6090 WorkListRemover DeadNodes(*this);
6091 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
6092 removeFromWorkList(N1.getNode());
6093 DAG.DeleteNode(N1.getNode());
6094 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
6095 MVT::Other, Chain, SetCC, N2);
6102 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
6104 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
6105 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
6106 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
6108 // If N is a constant we could fold this into a fallthrough or unconditional
6109 // branch. However that doesn't happen very often in normal code, because
6110 // Instcombine/SimplifyCFG should have handled the available opportunities.
6111 // If we did this folding here, it would be necessary to update the
6112 // MachineBasicBlock CFG, which is awkward.
6114 // Use SimplifySetCC to simplify SETCC's.
6115 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
6116 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
6118 if (Simp.getNode()) AddToWorkList(Simp.getNode());
6120 // fold to a simpler setcc
6121 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
6122 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
6123 N->getOperand(0), Simp.getOperand(2),
6124 Simp.getOperand(0), Simp.getOperand(1),
6130 /// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
6131 /// uses N as its base pointer and that N may be folded in the load / store
6132 /// addressing mode. FIXME: This currently only looks for folding of
6133 /// [reg +/- imm] addressing modes.
6134 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
6136 const TargetLowering &TLI) {
6138 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
6139 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
6141 VT = Use->getValueType(0);
6142 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
6143 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
6145 VT = ST->getValue().getValueType();
6149 TargetLowering::AddrMode AM;
6150 if (N->getOpcode() == ISD::ADD) {
6151 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6153 AM.BaseOffs = Offset->getSExtValue();
6156 } else if (N->getOpcode() == ISD::SUB) {
6157 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
6159 AM.BaseOffs = -Offset->getSExtValue();
6165 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext()));
6168 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
6169 /// pre-indexed load / store when the base pointer is an add or subtract
6170 /// and it has other uses besides the load / store. After the
6171 /// transformation, the new indexed load / store has effectively folded
6172 /// the add / subtract in and all of its other uses are redirected to the
6173 /// new load / store.
6174 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
6175 if (Level < AfterLegalizeDAG)
6181 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6182 if (LD->isIndexed())
6184 VT = LD->getMemoryVT();
6185 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
6186 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
6188 Ptr = LD->getBasePtr();
6189 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6190 if (ST->isIndexed())
6192 VT = ST->getMemoryVT();
6193 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
6194 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
6196 Ptr = ST->getBasePtr();
6202 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
6203 // out. There is no reason to make this a preinc/predec.
6204 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
6205 Ptr.getNode()->hasOneUse())
6208 // Ask the target to do addressing mode selection.
6211 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6212 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
6214 // Don't create a indexed load / store with zero offset.
6215 if (isa<ConstantSDNode>(Offset) &&
6216 cast<ConstantSDNode>(Offset)->isNullValue())
6219 // Try turning it into a pre-indexed load / store except when:
6220 // 1) The new base ptr is a frame index.
6221 // 2) If N is a store and the new base ptr is either the same as or is a
6222 // predecessor of the value being stored.
6223 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
6224 // that would create a cycle.
6225 // 4) All uses are load / store ops that use it as old base ptr.
6227 // Check #1. Preinc'ing a frame index would require copying the stack pointer
6228 // (plus the implicit offset) to a register to preinc anyway.
6229 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6234 SDValue Val = cast<StoreSDNode>(N)->getValue();
6235 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
6239 // Now check for #3 and #4.
6240 bool RealUse = false;
6242 // Caches for hasPredecessorHelper
6243 SmallPtrSet<const SDNode *, 32> Visited;
6244 SmallVector<const SDNode *, 16> Worklist;
6246 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6247 E = Ptr.getNode()->use_end(); I != E; ++I) {
6251 if (N->hasPredecessorHelper(Use, Visited, Worklist))
6254 // If Ptr may be folded in addressing mode of other use, then it's
6255 // not profitable to do this transformation.
6256 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
6265 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6266 BasePtr, Offset, AM);
6268 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6269 BasePtr, Offset, AM);
6272 DEBUG(dbgs() << "\nReplacing.4 ";
6274 dbgs() << "\nWith: ";
6275 Result.getNode()->dump(&DAG);
6277 WorkListRemover DeadNodes(*this);
6279 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
6281 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
6284 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
6288 // Finally, since the node is now dead, remove it from the graph.
6291 // Replace the uses of Ptr with uses of the updated base value.
6292 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
6294 removeFromWorkList(Ptr.getNode());
6295 DAG.DeleteNode(Ptr.getNode());
6300 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
6301 /// add / sub of the base pointer node into a post-indexed load / store.
6302 /// The transformation folded the add / subtract into the new indexed
6303 /// load / store effectively and all of its uses are redirected to the
6304 /// new load / store.
6305 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
6306 if (Level < AfterLegalizeDAG)
6312 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6313 if (LD->isIndexed())
6315 VT = LD->getMemoryVT();
6316 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6317 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6319 Ptr = LD->getBasePtr();
6320 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6321 if (ST->isIndexed())
6323 VT = ST->getMemoryVT();
6324 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6325 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6327 Ptr = ST->getBasePtr();
6333 if (Ptr.getNode()->hasOneUse())
6336 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6337 E = Ptr.getNode()->use_end(); I != E; ++I) {
6340 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
6345 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6346 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
6347 // Don't create a indexed load / store with zero offset.
6348 if (isa<ConstantSDNode>(Offset) &&
6349 cast<ConstantSDNode>(Offset)->isNullValue())
6352 // Try turning it into a post-indexed load / store except when
6353 // 1) All uses are load / store ops that use it as base ptr (and
6354 // it may be folded as addressing mmode).
6355 // 2) Op must be independent of N, i.e. Op is neither a predecessor
6356 // nor a successor of N. Otherwise, if Op is folded that would
6359 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6363 bool TryNext = false;
6364 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
6365 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
6367 if (Use == Ptr.getNode())
6370 // If all the uses are load / store addresses, then don't do the
6372 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
6373 bool RealUse = false;
6374 for (SDNode::use_iterator III = Use->use_begin(),
6375 EEE = Use->use_end(); III != EEE; ++III) {
6376 SDNode *UseUse = *III;
6377 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
6392 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
6393 SDValue Result = isLoad
6394 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6395 BasePtr, Offset, AM)
6396 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6397 BasePtr, Offset, AM);
6400 DEBUG(dbgs() << "\nReplacing.5 ";
6402 dbgs() << "\nWith: ";
6403 Result.getNode()->dump(&DAG);
6405 WorkListRemover DeadNodes(*this);
6407 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
6409 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
6412 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
6416 // Finally, since the node is now dead, remove it from the graph.
6419 // Replace the uses of Use with uses of the updated base value.
6420 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
6421 Result.getValue(isLoad ? 1 : 0),
6423 removeFromWorkList(Op);
6433 SDValue DAGCombiner::visitLOAD(SDNode *N) {
6434 LoadSDNode *LD = cast<LoadSDNode>(N);
6435 SDValue Chain = LD->getChain();
6436 SDValue Ptr = LD->getBasePtr();
6438 // If load is not volatile and there are no uses of the loaded value (and
6439 // the updated indexed value in case of indexed loads), change uses of the
6440 // chain value into uses of the chain input (i.e. delete the dead load).
6441 if (!LD->isVolatile()) {
6442 if (N->getValueType(1) == MVT::Other) {
6444 if (!N->hasAnyUseOfValue(0)) {
6445 // It's not safe to use the two value CombineTo variant here. e.g.
6446 // v1, chain2 = load chain1, loc
6447 // v2, chain3 = load chain2, loc
6449 // Now we replace use of chain2 with chain1. This makes the second load
6450 // isomorphic to the one we are deleting, and thus makes this load live.
6451 DEBUG(dbgs() << "\nReplacing.6 ";
6453 dbgs() << "\nWith chain: ";
6454 Chain.getNode()->dump(&DAG);
6456 WorkListRemover DeadNodes(*this);
6457 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
6459 if (N->use_empty()) {
6460 removeFromWorkList(N);
6464 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6468 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
6469 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) {
6470 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
6471 DEBUG(dbgs() << "\nReplacing.7 ";
6473 dbgs() << "\nWith: ";
6474 Undef.getNode()->dump(&DAG);
6475 dbgs() << " and 2 other values\n");
6476 WorkListRemover DeadNodes(*this);
6477 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
6478 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
6479 DAG.getUNDEF(N->getValueType(1)),
6481 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
6482 removeFromWorkList(N);
6484 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6489 // If this load is directly stored, replace the load value with the stored
6491 // TODO: Handle store large -> read small portion.
6492 // TODO: Handle TRUNCSTORE/LOADEXT
6493 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
6494 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
6495 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
6496 if (PrevST->getBasePtr() == Ptr &&
6497 PrevST->getValue().getValueType() == N->getValueType(0))
6498 return CombineTo(N, Chain.getOperand(1), Chain);
6502 // Try to infer better alignment information than the load already has.
6503 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
6504 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6505 if (Align > LD->getAlignment())
6506 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
6507 LD->getValueType(0),
6508 Chain, Ptr, LD->getPointerInfo(),
6510 LD->isVolatile(), LD->isNonTemporal(), Align);
6515 // Walk up chain skipping non-aliasing memory nodes.
6516 SDValue BetterChain = FindBetterChain(N, Chain);
6518 // If there is a better chain.
6519 if (Chain != BetterChain) {
6522 // Replace the chain to void dependency.
6523 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
6524 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
6525 BetterChain, Ptr, LD->getPointerInfo(),
6526 LD->isVolatile(), LD->isNonTemporal(),
6527 LD->isInvariant(), LD->getAlignment());
6529 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
6530 LD->getValueType(0),
6531 BetterChain, Ptr, LD->getPointerInfo(),
6534 LD->isNonTemporal(),
6535 LD->getAlignment());
6538 // Create token factor to keep old chain connected.
6539 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6540 MVT::Other, Chain, ReplLoad.getValue(1));
6542 // Make sure the new and old chains are cleaned up.
6543 AddToWorkList(Token.getNode());
6545 // Replace uses with load result and token factor. Don't add users
6547 return CombineTo(N, ReplLoad.getValue(0), Token, false);
6551 // Try transforming N to an indexed load.
6552 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6553 return SDValue(N, 0);
6558 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
6559 /// load is having specific bytes cleared out. If so, return the byte size
6560 /// being masked out and the shift amount.
6561 static std::pair<unsigned, unsigned>
6562 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
6563 std::pair<unsigned, unsigned> Result(0, 0);
6565 // Check for the structure we're looking for.
6566 if (V->getOpcode() != ISD::AND ||
6567 !isa<ConstantSDNode>(V->getOperand(1)) ||
6568 !ISD::isNormalLoad(V->getOperand(0).getNode()))
6571 // Check the chain and pointer.
6572 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
6573 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
6575 // The store should be chained directly to the load or be an operand of a
6577 if (LD == Chain.getNode())
6579 else if (Chain->getOpcode() != ISD::TokenFactor)
6580 return Result; // Fail.
6583 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
6584 if (Chain->getOperand(i).getNode() == LD) {
6588 if (!isOk) return Result;
6591 // This only handles simple types.
6592 if (V.getValueType() != MVT::i16 &&
6593 V.getValueType() != MVT::i32 &&
6594 V.getValueType() != MVT::i64)
6597 // Check the constant mask. Invert it so that the bits being masked out are
6598 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
6599 // follow the sign bit for uniformity.
6600 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
6601 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
6602 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
6603 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
6604 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
6605 if (NotMaskLZ == 64) return Result; // All zero mask.
6607 // See if we have a continuous run of bits. If so, we have 0*1+0*
6608 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
6611 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
6612 if (V.getValueType() != MVT::i64 && NotMaskLZ)
6613 NotMaskLZ -= 64-V.getValueSizeInBits();
6615 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
6616 switch (MaskedBytes) {
6620 default: return Result; // All one mask, or 5-byte mask.
6623 // Verify that the first bit starts at a multiple of mask so that the access
6624 // is aligned the same as the access width.
6625 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
6627 Result.first = MaskedBytes;
6628 Result.second = NotMaskTZ/8;
6633 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
6634 /// provides a value as specified by MaskInfo. If so, replace the specified
6635 /// store with a narrower store of truncated IVal.
6637 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
6638 SDValue IVal, StoreSDNode *St,
6640 unsigned NumBytes = MaskInfo.first;
6641 unsigned ByteShift = MaskInfo.second;
6642 SelectionDAG &DAG = DC->getDAG();
6644 // Check to see if IVal is all zeros in the part being masked in by the 'or'
6645 // that uses this. If not, this is not a replacement.
6646 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
6647 ByteShift*8, (ByteShift+NumBytes)*8);
6648 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
6650 // Check that it is legal on the target to do this. It is legal if the new
6651 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
6653 MVT VT = MVT::getIntegerVT(NumBytes*8);
6654 if (!DC->isTypeLegal(VT))
6657 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
6658 // shifted by ByteShift and truncated down to NumBytes.
6660 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
6661 DAG.getConstant(ByteShift*8,
6662 DC->getShiftAmountTy(IVal.getValueType())));
6664 // Figure out the offset for the store and the alignment of the access.
6666 unsigned NewAlign = St->getAlignment();
6668 if (DAG.getTargetLoweringInfo().isLittleEndian())
6669 StOffset = ByteShift;
6671 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
6673 SDValue Ptr = St->getBasePtr();
6675 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
6676 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
6677 NewAlign = MinAlign(NewAlign, StOffset);
6680 // Truncate down to the new size.
6681 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
6684 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
6685 St->getPointerInfo().getWithOffset(StOffset),
6686 false, false, NewAlign).getNode();
6690 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
6691 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
6692 /// of the loaded bits, try narrowing the load and store if it would end up
6693 /// being a win for performance or code size.
6694 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
6695 StoreSDNode *ST = cast<StoreSDNode>(N);
6696 if (ST->isVolatile())
6699 SDValue Chain = ST->getChain();
6700 SDValue Value = ST->getValue();
6701 SDValue Ptr = ST->getBasePtr();
6702 EVT VT = Value.getValueType();
6704 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
6707 unsigned Opc = Value.getOpcode();
6709 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
6710 // is a byte mask indicating a consecutive number of bytes, check to see if
6711 // Y is known to provide just those bytes. If so, we try to replace the
6712 // load + replace + store sequence with a single (narrower) store, which makes
6714 if (Opc == ISD::OR) {
6715 std::pair<unsigned, unsigned> MaskedLoad;
6716 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
6717 if (MaskedLoad.first)
6718 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6719 Value.getOperand(1), ST,this))
6720 return SDValue(NewST, 0);
6722 // Or is commutative, so try swapping X and Y.
6723 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
6724 if (MaskedLoad.first)
6725 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6726 Value.getOperand(0), ST,this))
6727 return SDValue(NewST, 0);
6730 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
6731 Value.getOperand(1).getOpcode() != ISD::Constant)
6734 SDValue N0 = Value.getOperand(0);
6735 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6736 Chain == SDValue(N0.getNode(), 1)) {
6737 LoadSDNode *LD = cast<LoadSDNode>(N0);
6738 if (LD->getBasePtr() != Ptr ||
6739 LD->getPointerInfo().getAddrSpace() !=
6740 ST->getPointerInfo().getAddrSpace())
6743 // Find the type to narrow it the load / op / store to.
6744 SDValue N1 = Value.getOperand(1);
6745 unsigned BitWidth = N1.getValueSizeInBits();
6746 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
6747 if (Opc == ISD::AND)
6748 Imm ^= APInt::getAllOnesValue(BitWidth);
6749 if (Imm == 0 || Imm.isAllOnesValue())
6751 unsigned ShAmt = Imm.countTrailingZeros();
6752 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
6753 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
6754 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6755 while (NewBW < BitWidth &&
6756 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
6757 TLI.isNarrowingProfitable(VT, NewVT))) {
6758 NewBW = NextPowerOf2(NewBW);
6759 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6761 if (NewBW >= BitWidth)
6764 // If the lsb changed does not start at the type bitwidth boundary,
6765 // start at the previous one.
6767 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
6768 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
6769 if ((Imm & Mask) == Imm) {
6770 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
6771 if (Opc == ISD::AND)
6772 NewImm ^= APInt::getAllOnesValue(NewBW);
6773 uint64_t PtrOff = ShAmt / 8;
6774 // For big endian targets, we need to adjust the offset to the pointer to
6775 // load the correct bytes.
6776 if (TLI.isBigEndian())
6777 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
6779 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
6780 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
6781 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
6784 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
6785 Ptr.getValueType(), Ptr,
6786 DAG.getConstant(PtrOff, Ptr.getValueType()));
6787 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
6788 LD->getChain(), NewPtr,
6789 LD->getPointerInfo().getWithOffset(PtrOff),
6790 LD->isVolatile(), LD->isNonTemporal(),
6791 LD->isInvariant(), NewAlign);
6792 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
6793 DAG.getConstant(NewImm, NewVT));
6794 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
6796 ST->getPointerInfo().getWithOffset(PtrOff),
6797 false, false, NewAlign);
6799 AddToWorkList(NewPtr.getNode());
6800 AddToWorkList(NewLD.getNode());
6801 AddToWorkList(NewVal.getNode());
6802 WorkListRemover DeadNodes(*this);
6803 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
6813 /// TransformFPLoadStorePair - For a given floating point load / store pair,
6814 /// if the load value isn't used by any other operations, then consider
6815 /// transforming the pair to integer load / store operations if the target
6816 /// deems the transformation profitable.
6817 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
6818 StoreSDNode *ST = cast<StoreSDNode>(N);
6819 SDValue Chain = ST->getChain();
6820 SDValue Value = ST->getValue();
6821 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
6822 Value.hasOneUse() &&
6823 Chain == SDValue(Value.getNode(), 1)) {
6824 LoadSDNode *LD = cast<LoadSDNode>(Value);
6825 EVT VT = LD->getMemoryVT();
6826 if (!VT.isFloatingPoint() ||
6827 VT != ST->getMemoryVT() ||
6828 LD->isNonTemporal() ||
6829 ST->isNonTemporal() ||
6830 LD->getPointerInfo().getAddrSpace() != 0 ||
6831 ST->getPointerInfo().getAddrSpace() != 0)
6834 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
6835 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
6836 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
6837 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
6838 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
6841 unsigned LDAlign = LD->getAlignment();
6842 unsigned STAlign = ST->getAlignment();
6843 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
6844 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy);
6845 if (LDAlign < ABIAlign || STAlign < ABIAlign)
6848 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
6849 LD->getChain(), LD->getBasePtr(),
6850 LD->getPointerInfo(),
6851 false, false, false, LDAlign);
6853 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
6854 NewLD, ST->getBasePtr(),
6855 ST->getPointerInfo(),
6856 false, false, STAlign);
6858 AddToWorkList(NewLD.getNode());
6859 AddToWorkList(NewST.getNode());
6860 WorkListRemover DeadNodes(*this);
6861 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1),
6870 SDValue DAGCombiner::visitSTORE(SDNode *N) {
6871 StoreSDNode *ST = cast<StoreSDNode>(N);
6872 SDValue Chain = ST->getChain();
6873 SDValue Value = ST->getValue();
6874 SDValue Ptr = ST->getBasePtr();
6876 // If this is a store of a bit convert, store the input value if the
6877 // resultant store does not need a higher alignment than the original.
6878 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
6879 ST->isUnindexed()) {
6880 unsigned OrigAlign = ST->getAlignment();
6881 EVT SVT = Value.getOperand(0).getValueType();
6882 unsigned Align = TLI.getTargetData()->
6883 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
6884 if (Align <= OrigAlign &&
6885 ((!LegalOperations && !ST->isVolatile()) ||
6886 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
6887 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6888 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6889 ST->isNonTemporal(), OrigAlign);
6892 // Turn 'store undef, Ptr' -> nothing.
6893 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
6896 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
6897 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
6898 // NOTE: If the original store is volatile, this transform must not increase
6899 // the number of stores. For example, on x86-32 an f64 can be stored in one
6900 // processor operation but an i64 (which is not legal) requires two. So the
6901 // transform should not be done in this case.
6902 if (Value.getOpcode() != ISD::TargetConstantFP) {
6904 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
6905 default: llvm_unreachable("Unknown FP type");
6906 case MVT::f80: // We don't do this for these yet.
6911 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
6912 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6913 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
6914 bitcastToAPInt().getZExtValue(), MVT::i32);
6915 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6916 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6917 ST->isNonTemporal(), ST->getAlignment());
6921 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
6922 !ST->isVolatile()) ||
6923 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
6924 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
6925 getZExtValue(), MVT::i64);
6926 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6927 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6928 ST->isNonTemporal(), ST->getAlignment());
6931 if (!ST->isVolatile() &&
6932 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6933 // Many FP stores are not made apparent until after legalize, e.g. for
6934 // argument passing. Since this is so common, custom legalize the
6935 // 64-bit integer store into two 32-bit stores.
6936 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
6937 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
6938 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
6939 if (TLI.isBigEndian()) std::swap(Lo, Hi);
6941 unsigned Alignment = ST->getAlignment();
6942 bool isVolatile = ST->isVolatile();
6943 bool isNonTemporal = ST->isNonTemporal();
6945 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
6946 Ptr, ST->getPointerInfo(),
6947 isVolatile, isNonTemporal,
6948 ST->getAlignment());
6949 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
6950 DAG.getConstant(4, Ptr.getValueType()));
6951 Alignment = MinAlign(Alignment, 4U);
6952 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
6953 Ptr, ST->getPointerInfo().getWithOffset(4),
6954 isVolatile, isNonTemporal,
6956 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6965 // Try to infer better alignment information than the store already has.
6966 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
6967 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6968 if (Align > ST->getAlignment())
6969 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
6970 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6971 ST->isVolatile(), ST->isNonTemporal(), Align);
6975 // Try transforming a pair floating point load / store ops to integer
6976 // load / store ops.
6977 SDValue NewST = TransformFPLoadStorePair(N);
6978 if (NewST.getNode())
6982 // Walk up chain skipping non-aliasing memory nodes.
6983 SDValue BetterChain = FindBetterChain(N, Chain);
6985 // If there is a better chain.
6986 if (Chain != BetterChain) {
6989 // Replace the chain to avoid dependency.
6990 if (ST->isTruncatingStore()) {
6991 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6992 ST->getPointerInfo(),
6993 ST->getMemoryVT(), ST->isVolatile(),
6994 ST->isNonTemporal(), ST->getAlignment());
6996 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6997 ST->getPointerInfo(),
6998 ST->isVolatile(), ST->isNonTemporal(),
6999 ST->getAlignment());
7002 // Create token to keep both nodes around.
7003 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
7004 MVT::Other, Chain, ReplStore);
7006 // Make sure the new and old chains are cleaned up.
7007 AddToWorkList(Token.getNode());
7009 // Don't add users to work list.
7010 return CombineTo(N, Token, false);
7014 // Try transforming N to an indexed store.
7015 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
7016 return SDValue(N, 0);
7018 // FIXME: is there such a thing as a truncating indexed store?
7019 if (ST->isTruncatingStore() && ST->isUnindexed() &&
7020 Value.getValueType().isInteger()) {
7021 // See if we can simplify the input to this truncstore with knowledge that
7022 // only the low bits are being used. For example:
7023 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
7025 GetDemandedBits(Value,
7026 APInt::getLowBitsSet(
7027 Value.getValueType().getScalarType().getSizeInBits(),
7028 ST->getMemoryVT().getScalarType().getSizeInBits()));
7029 AddToWorkList(Value.getNode());
7030 if (Shorter.getNode())
7031 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
7032 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7033 ST->isVolatile(), ST->isNonTemporal(),
7034 ST->getAlignment());
7036 // Otherwise, see if we can simplify the operation with
7037 // SimplifyDemandedBits, which only works if the value has a single use.
7038 if (SimplifyDemandedBits(Value,
7039 APInt::getLowBitsSet(
7040 Value.getValueType().getScalarType().getSizeInBits(),
7041 ST->getMemoryVT().getScalarType().getSizeInBits())))
7042 return SDValue(N, 0);
7045 // If this is a load followed by a store to the same location, then the store
7047 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
7048 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
7049 ST->isUnindexed() && !ST->isVolatile() &&
7050 // There can't be any side effects between the load and store, such as
7052 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
7053 // The store is dead, remove it.
7058 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
7059 // truncating store. We can do this even if this is already a truncstore.
7060 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
7061 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
7062 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
7063 ST->getMemoryVT())) {
7064 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
7065 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
7066 ST->isVolatile(), ST->isNonTemporal(),
7067 ST->getAlignment());
7070 return ReduceLoadOpStoreWidth(N);
7073 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
7074 SDValue InVec = N->getOperand(0);
7075 SDValue InVal = N->getOperand(1);
7076 SDValue EltNo = N->getOperand(2);
7077 DebugLoc dl = N->getDebugLoc();
7079 // If the inserted element is an UNDEF, just use the input vector.
7080 if (InVal.getOpcode() == ISD::UNDEF)
7083 EVT VT = InVec.getValueType();
7085 // If we can't generate a legal BUILD_VECTOR, exit
7086 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
7089 // Check that we know which element is being inserted
7090 if (!isa<ConstantSDNode>(EltNo))
7092 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7094 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
7095 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
7097 SmallVector<SDValue, 8> Ops;
7098 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
7099 Ops.append(InVec.getNode()->op_begin(),
7100 InVec.getNode()->op_end());
7101 } else if (InVec.getOpcode() == ISD::UNDEF) {
7102 unsigned NElts = VT.getVectorNumElements();
7103 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
7108 // Insert the element
7109 if (Elt < Ops.size()) {
7110 // All the operands of BUILD_VECTOR must have the same type;
7111 // we enforce that here.
7112 EVT OpVT = Ops[0].getValueType();
7113 if (InVal.getValueType() != OpVT)
7114 InVal = OpVT.bitsGT(InVal.getValueType()) ?
7115 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
7116 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
7120 // Return the new vector
7121 return DAG.getNode(ISD::BUILD_VECTOR, dl,
7122 VT, &Ops[0], Ops.size());
7125 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
7126 // (vextract (scalar_to_vector val, 0) -> val
7127 SDValue InVec = N->getOperand(0);
7128 EVT VT = InVec.getValueType();
7129 EVT NVT = N->getValueType(0);
7131 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
7132 // Check if the result type doesn't match the inserted element type. A
7133 // SCALAR_TO_VECTOR may truncate the inserted element and the
7134 // EXTRACT_VECTOR_ELT may widen the extracted vector.
7135 SDValue InOp = InVec.getOperand(0);
7136 if (InOp.getValueType() != NVT) {
7137 assert(InOp.getValueType().isInteger() && NVT.isInteger());
7138 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
7143 SDValue EltNo = N->getOperand(1);
7144 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
7146 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
7147 // We only perform this optimization before the op legalization phase because
7148 // we may introduce new vector instructions which are not backed by TD patterns.
7149 // For example on AVX, extracting elements from a wide vector without using
7150 // extract_subvector.
7151 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
7152 && ConstEltNo && !LegalOperations) {
7153 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7154 int NumElem = VT.getVectorNumElements();
7155 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
7156 // Find the new index to extract from.
7157 int OrigElt = SVOp->getMaskElt(Elt);
7159 // Extracting an undef index is undef.
7161 return DAG.getUNDEF(NVT);
7163 // Select the right vector half to extract from.
7164 if (OrigElt < NumElem) {
7165 InVec = InVec->getOperand(0);
7167 InVec = InVec->getOperand(1);
7171 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT,
7172 InVec, DAG.getConstant(OrigElt, MVT::i32));
7175 // Perform only after legalization to ensure build_vector / vector_shuffle
7176 // optimizations have already been done.
7177 if (!LegalOperations) return SDValue();
7179 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
7180 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
7181 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
7184 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
7185 bool NewLoad = false;
7186 bool BCNumEltsChanged = false;
7187 EVT ExtVT = VT.getVectorElementType();
7190 if (InVec.getOpcode() == ISD::BITCAST) {
7191 // Don't duplicate a load with other uses.
7192 if (!InVec.hasOneUse())
7195 EVT BCVT = InVec.getOperand(0).getValueType();
7196 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
7198 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
7199 BCNumEltsChanged = true;
7200 InVec = InVec.getOperand(0);
7201 ExtVT = BCVT.getVectorElementType();
7205 LoadSDNode *LN0 = NULL;
7206 const ShuffleVectorSDNode *SVN = NULL;
7207 if (ISD::isNormalLoad(InVec.getNode())) {
7208 LN0 = cast<LoadSDNode>(InVec);
7209 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
7210 InVec.getOperand(0).getValueType() == ExtVT &&
7211 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
7212 // Don't duplicate a load with other uses.
7213 if (!InVec.hasOneUse())
7216 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
7217 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
7218 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
7220 // (load $addr+1*size)
7222 // Don't duplicate a load with other uses.
7223 if (!InVec.hasOneUse())
7226 // If the bit convert changed the number of elements, it is unsafe
7227 // to examine the mask.
7228 if (BCNumEltsChanged)
7231 // Select the input vector, guarding against out of range extract vector.
7232 unsigned NumElems = VT.getVectorNumElements();
7233 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
7234 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
7236 if (InVec.getOpcode() == ISD::BITCAST) {
7237 // Don't duplicate a load with other uses.
7238 if (!InVec.hasOneUse())
7241 InVec = InVec.getOperand(0);
7243 if (ISD::isNormalLoad(InVec.getNode())) {
7244 LN0 = cast<LoadSDNode>(InVec);
7245 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
7249 // Make sure we found a non-volatile load and the extractelement is
7251 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
7254 // If Idx was -1 above, Elt is going to be -1, so just return undef.
7256 return DAG.getUNDEF(LVT);
7258 unsigned Align = LN0->getAlignment();
7260 // Check the resultant load doesn't need a higher alignment than the
7264 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
7266 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
7272 SDValue NewPtr = LN0->getBasePtr();
7273 unsigned PtrOff = 0;
7276 PtrOff = LVT.getSizeInBits() * Elt / 8;
7277 EVT PtrType = NewPtr.getValueType();
7278 if (TLI.isBigEndian())
7279 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
7280 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
7281 DAG.getConstant(PtrOff, PtrType));
7284 // The replacement we need to do here is a little tricky: we need to
7285 // replace an extractelement of a load with a load.
7286 // Use ReplaceAllUsesOfValuesWith to do the replacement.
7287 // Note that this replacement assumes that the extractvalue is the only
7288 // use of the load; that's okay because we don't want to perform this
7289 // transformation in other cases anyway.
7290 SDValue Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
7291 LN0->getPointerInfo().getWithOffset(PtrOff),
7292 LN0->isVolatile(), LN0->isNonTemporal(),
7293 LN0->isInvariant(), Align);
7294 WorkListRemover DeadNodes(*this);
7295 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) };
7296 SDValue To[] = { Load.getValue(0), Load.getValue(1) };
7297 DAG.ReplaceAllUsesOfValuesWith(From, To, 2, &DeadNodes);
7298 // Since we're explcitly calling ReplaceAllUses, add the new node to the
7299 // worklist explicitly as well.
7300 AddToWorkList(Load.getNode());
7301 // Make sure to revisit this node to clean it up; it will usually be dead.
7303 return SDValue(N, 0);
7309 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
7310 unsigned NumInScalars = N->getNumOperands();
7311 DebugLoc dl = N->getDebugLoc();
7312 EVT VT = N->getValueType(0);
7313 // Check to see if this is a BUILD_VECTOR of a bunch of values
7314 // which come from any_extend or zero_extend nodes. If so, we can create
7315 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
7316 // optimizations. We do not handle sign-extend because we can't fill the sign
7318 EVT SourceType = MVT::Other;
7319 bool AllAnyExt = true;
7320 bool AllUndef = true;
7321 for (unsigned i = 0; i != NumInScalars; ++i) {
7322 SDValue In = N->getOperand(i);
7323 // Ignore undef inputs.
7324 if (In.getOpcode() == ISD::UNDEF) continue;
7327 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
7328 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
7330 // Abort if the element is not an extension.
7331 if (!ZeroExt && !AnyExt) {
7332 SourceType = MVT::Other;
7336 // The input is a ZeroExt or AnyExt. Check the original type.
7337 EVT InTy = In.getOperand(0).getValueType();
7339 // Check that all of the widened source types are the same.
7340 if (SourceType == MVT::Other)
7343 else if (InTy != SourceType) {
7344 // Multiple income types. Abort.
7345 SourceType = MVT::Other;
7349 // Check if all of the extends are ANY_EXTENDs.
7350 AllAnyExt &= AnyExt;
7354 return DAG.getUNDEF(VT);
7356 // In order to have valid types, all of the inputs must be extended from the
7357 // same source type and all of the inputs must be any or zero extend.
7358 // Scalar sizes must be a power of two.
7359 EVT OutScalarTy = N->getValueType(0).getScalarType();
7360 bool ValidTypes = SourceType != MVT::Other &&
7361 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
7362 isPowerOf2_32(SourceType.getSizeInBits());
7364 // We perform this optimization post type-legalization because
7365 // the type-legalizer often scalarizes integer-promoted vectors.
7366 // Performing this optimization before may create bit-casts which
7367 // will be type-legalized to complex code sequences.
7368 // We perform this optimization only before the operation legalizer because we
7369 // may introduce illegal operations.
7370 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) &&
7372 bool isLE = TLI.isLittleEndian();
7373 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
7374 assert(ElemRatio > 1 && "Invalid element size ratio");
7375 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
7376 DAG.getConstant(0, SourceType);
7378 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements();
7379 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
7381 // Populate the new build_vector
7382 for (unsigned i=0; i < N->getNumOperands(); ++i) {
7383 SDValue Cast = N->getOperand(i);
7384 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
7385 Cast.getOpcode() == ISD::ZERO_EXTEND ||
7386 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
7388 if (Cast.getOpcode() == ISD::UNDEF)
7389 In = DAG.getUNDEF(SourceType);
7391 In = Cast->getOperand(0);
7392 unsigned Index = isLE ? (i * ElemRatio) :
7393 (i * ElemRatio + (ElemRatio - 1));
7395 assert(Index < Ops.size() && "Invalid index");
7399 // The type of the new BUILD_VECTOR node.
7400 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
7401 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() &&
7402 "Invalid vector size");
7403 // Check if the new vector type is legal.
7404 if (!isTypeLegal(VecVT)) return SDValue();
7406 // Make the new BUILD_VECTOR.
7407 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7408 VecVT, &Ops[0], Ops.size());
7410 // Bitcast to the desired type.
7411 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV);
7414 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
7415 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
7416 // at most two distinct vectors, turn this into a shuffle node.
7417 SDValue VecIn1, VecIn2;
7418 for (unsigned i = 0; i != NumInScalars; ++i) {
7419 // Ignore undef inputs.
7420 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
7422 // If this input is something other than a EXTRACT_VECTOR_ELT with a
7423 // constant index, bail out.
7424 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
7425 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
7426 VecIn1 = VecIn2 = SDValue(0, 0);
7430 // We allow up to two distinct input vectors.
7431 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
7432 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
7435 if (VecIn1.getNode() == 0) {
7436 VecIn1 = ExtractedFromVec;
7437 } else if (VecIn2.getNode() == 0) {
7438 VecIn2 = ExtractedFromVec;
7441 VecIn1 = VecIn2 = SDValue(0, 0);
7446 // If everything is good, we can make a shuffle operation.
7447 if (VecIn1.getNode()) {
7448 SmallVector<int, 8> Mask;
7449 for (unsigned i = 0; i != NumInScalars; ++i) {
7450 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
7455 // If extracting from the first vector, just use the index directly.
7456 SDValue Extract = N->getOperand(i);
7457 SDValue ExtVal = Extract.getOperand(1);
7458 if (Extract.getOperand(0) == VecIn1) {
7459 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7460 if (ExtIndex > VT.getVectorNumElements())
7463 Mask.push_back(ExtIndex);
7467 // Otherwise, use InIdx + VecSize
7468 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7469 Mask.push_back(Idx+NumInScalars);
7472 // We can't generate a shuffle node with mismatched input and output types.
7473 // Attempt to transform a single input vector to the correct type.
7474 if ((VT != VecIn1.getValueType())) {
7475 // We don't support shuffeling between TWO values of different types.
7476 if (VecIn2.getNode() != 0)
7479 // We only support widening of vectors which are half the size of the
7480 // output registers. For example XMM->YMM widening on X86 with AVX.
7481 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits())
7484 // Widen the input vector by adding undef values.
7485 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
7486 VecIn1, DAG.getUNDEF(VecIn1.getValueType()));
7489 // If VecIn2 is unused then change it to undef.
7490 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
7492 // Check that we were able to transform all incoming values to the same type.
7493 if (VecIn2.getValueType() != VecIn1.getValueType() ||
7494 VecIn1.getValueType() != VT)
7497 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
7498 if (!isTypeLegal(VT))
7501 // Return the new VECTOR_SHUFFLE node.
7505 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
7511 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
7512 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
7513 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
7514 // inputs come from at most two distinct vectors, turn this into a shuffle
7517 // If we only have one input vector, we don't need to do any concatenation.
7518 if (N->getNumOperands() == 1)
7519 return N->getOperand(0);
7524 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
7525 EVT NVT = N->getValueType(0);
7526 SDValue V = N->getOperand(0);
7528 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
7529 // Handle only simple case where vector being inserted and vector
7530 // being extracted are of same type, and are half size of larger vectors.
7531 EVT BigVT = V->getOperand(0).getValueType();
7532 EVT SmallVT = V->getOperand(1).getValueType();
7533 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
7536 // Only handle cases where both indexes are constants with the same type.
7537 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
7538 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
7540 if (InsIdx && ExtIdx &&
7541 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
7542 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
7544 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
7546 // indices are equal => V1
7547 // otherwise => (extract_subvec V1, ExtIdx)
7548 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue())
7549 return V->getOperand(1);
7550 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
7551 V->getOperand(0), N->getOperand(1));
7558 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
7559 EVT VT = N->getValueType(0);
7560 unsigned NumElts = VT.getVectorNumElements();
7562 SDValue N0 = N->getOperand(0);
7563 SDValue N1 = N->getOperand(1);
7565 assert(N0.getValueType().getVectorNumElements() == NumElts &&
7566 "Vector shuffle must be normalized in DAG");
7568 // Canonicalize shuffle undef, undef -> undef
7569 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
7570 return DAG.getUNDEF(VT);
7572 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7574 // Canonicalize shuffle v, v -> v, undef
7576 SmallVector<int, 8> NewMask;
7577 for (unsigned i = 0; i != NumElts; ++i) {
7578 int Idx = SVN->getMaskElt(i);
7579 if (Idx >= (int)NumElts) Idx -= NumElts;
7580 NewMask.push_back(Idx);
7582 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT),
7586 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
7587 if (N0.getOpcode() == ISD::UNDEF) {
7588 SmallVector<int, 8> NewMask;
7589 for (unsigned i = 0; i != NumElts; ++i) {
7590 int Idx = SVN->getMaskElt(i);
7592 NewMask.push_back(Idx);
7593 else if (Idx < (int)NumElts)
7594 NewMask.push_back(Idx + NumElts);
7596 NewMask.push_back(Idx - NumElts);
7598 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT),
7602 // Remove references to rhs if it is undef
7603 if (N1.getOpcode() == ISD::UNDEF) {
7604 bool Changed = false;
7605 SmallVector<int, 8> NewMask;
7606 for (unsigned i = 0; i != NumElts; ++i) {
7607 int Idx = SVN->getMaskElt(i);
7608 if (Idx >= (int)NumElts) {
7612 NewMask.push_back(Idx);
7615 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]);
7618 // If it is a splat, check if the argument vector is another splat or a
7619 // build_vector with all scalar elements the same.
7620 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
7621 SDNode *V = N0.getNode();
7623 // If this is a bit convert that changes the element type of the vector but
7624 // not the number of vector elements, look through it. Be careful not to
7625 // look though conversions that change things like v4f32 to v2f64.
7626 if (V->getOpcode() == ISD::BITCAST) {
7627 SDValue ConvInput = V->getOperand(0);
7628 if (ConvInput.getValueType().isVector() &&
7629 ConvInput.getValueType().getVectorNumElements() == NumElts)
7630 V = ConvInput.getNode();
7633 if (V->getOpcode() == ISD::BUILD_VECTOR) {
7634 assert(V->getNumOperands() == NumElts &&
7635 "BUILD_VECTOR has wrong number of operands");
7637 bool AllSame = true;
7638 for (unsigned i = 0; i != NumElts; ++i) {
7639 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
7640 Base = V->getOperand(i);
7644 // Splat of <u, u, u, u>, return <u, u, u, u>
7645 if (!Base.getNode())
7647 for (unsigned i = 0; i != NumElts; ++i) {
7648 if (V->getOperand(i) != Base) {
7653 // Splat of <x, x, x, x>, return <x, x, x, x>
7661 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
7662 if (!TLI.getShouldFoldAtomicFences())
7665 SDValue atomic = N->getOperand(0);
7666 switch (atomic.getOpcode()) {
7667 case ISD::ATOMIC_CMP_SWAP:
7668 case ISD::ATOMIC_SWAP:
7669 case ISD::ATOMIC_LOAD_ADD:
7670 case ISD::ATOMIC_LOAD_SUB:
7671 case ISD::ATOMIC_LOAD_AND:
7672 case ISD::ATOMIC_LOAD_OR:
7673 case ISD::ATOMIC_LOAD_XOR:
7674 case ISD::ATOMIC_LOAD_NAND:
7675 case ISD::ATOMIC_LOAD_MIN:
7676 case ISD::ATOMIC_LOAD_MAX:
7677 case ISD::ATOMIC_LOAD_UMIN:
7678 case ISD::ATOMIC_LOAD_UMAX:
7684 SDValue fence = atomic.getOperand(0);
7685 if (fence.getOpcode() != ISD::MEMBARRIER)
7688 switch (atomic.getOpcode()) {
7689 case ISD::ATOMIC_CMP_SWAP:
7690 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7691 fence.getOperand(0),
7692 atomic.getOperand(1), atomic.getOperand(2),
7693 atomic.getOperand(3)), atomic.getResNo());
7694 case ISD::ATOMIC_SWAP:
7695 case ISD::ATOMIC_LOAD_ADD:
7696 case ISD::ATOMIC_LOAD_SUB:
7697 case ISD::ATOMIC_LOAD_AND:
7698 case ISD::ATOMIC_LOAD_OR:
7699 case ISD::ATOMIC_LOAD_XOR:
7700 case ISD::ATOMIC_LOAD_NAND:
7701 case ISD::ATOMIC_LOAD_MIN:
7702 case ISD::ATOMIC_LOAD_MAX:
7703 case ISD::ATOMIC_LOAD_UMIN:
7704 case ISD::ATOMIC_LOAD_UMAX:
7705 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7706 fence.getOperand(0),
7707 atomic.getOperand(1), atomic.getOperand(2)),
7714 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
7715 /// an AND to a vector_shuffle with the destination vector and a zero vector.
7716 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
7717 /// vector_shuffle V, Zero, <0, 4, 2, 4>
7718 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
7719 EVT VT = N->getValueType(0);
7720 DebugLoc dl = N->getDebugLoc();
7721 SDValue LHS = N->getOperand(0);
7722 SDValue RHS = N->getOperand(1);
7723 if (N->getOpcode() == ISD::AND) {
7724 if (RHS.getOpcode() == ISD::BITCAST)
7725 RHS = RHS.getOperand(0);
7726 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
7727 SmallVector<int, 8> Indices;
7728 unsigned NumElts = RHS.getNumOperands();
7729 for (unsigned i = 0; i != NumElts; ++i) {
7730 SDValue Elt = RHS.getOperand(i);
7731 if (!isa<ConstantSDNode>(Elt))
7733 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
7734 Indices.push_back(i);
7735 else if (cast<ConstantSDNode>(Elt)->isNullValue())
7736 Indices.push_back(NumElts);
7741 // Let's see if the target supports this vector_shuffle.
7742 EVT RVT = RHS.getValueType();
7743 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
7746 // Return the new VECTOR_SHUFFLE node.
7747 EVT EltVT = RVT.getVectorElementType();
7748 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
7749 DAG.getConstant(0, EltVT));
7750 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7751 RVT, &ZeroOps[0], ZeroOps.size());
7752 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
7753 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
7754 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
7761 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
7762 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
7763 // After legalize, the target may be depending on adds and other
7764 // binary ops to provide legal ways to construct constants or other
7765 // things. Simplifying them may result in a loss of legality.
7766 if (LegalOperations) return SDValue();
7768 assert(N->getValueType(0).isVector() &&
7769 "SimplifyVBinOp only works on vectors!");
7771 SDValue LHS = N->getOperand(0);
7772 SDValue RHS = N->getOperand(1);
7773 SDValue Shuffle = XformToShuffleWithZero(N);
7774 if (Shuffle.getNode()) return Shuffle;
7776 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
7778 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
7779 RHS.getOpcode() == ISD::BUILD_VECTOR) {
7780 SmallVector<SDValue, 8> Ops;
7781 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
7782 SDValue LHSOp = LHS.getOperand(i);
7783 SDValue RHSOp = RHS.getOperand(i);
7784 // If these two elements can't be folded, bail out.
7785 if ((LHSOp.getOpcode() != ISD::UNDEF &&
7786 LHSOp.getOpcode() != ISD::Constant &&
7787 LHSOp.getOpcode() != ISD::ConstantFP) ||
7788 (RHSOp.getOpcode() != ISD::UNDEF &&
7789 RHSOp.getOpcode() != ISD::Constant &&
7790 RHSOp.getOpcode() != ISD::ConstantFP))
7793 // Can't fold divide by zero.
7794 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
7795 N->getOpcode() == ISD::FDIV) {
7796 if ((RHSOp.getOpcode() == ISD::Constant &&
7797 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
7798 (RHSOp.getOpcode() == ISD::ConstantFP &&
7799 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
7803 EVT VT = LHSOp.getValueType();
7804 EVT RVT = RHSOp.getValueType();
7806 // Integer BUILD_VECTOR operands may have types larger than the element
7807 // size (e.g., when the element type is not legal). Prior to type
7808 // legalization, the types may not match between the two BUILD_VECTORS.
7809 // Truncate one of the operands to make them match.
7810 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
7811 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp);
7813 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp);
7817 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
7819 if (FoldOp.getOpcode() != ISD::UNDEF &&
7820 FoldOp.getOpcode() != ISD::Constant &&
7821 FoldOp.getOpcode() != ISD::ConstantFP)
7823 Ops.push_back(FoldOp);
7824 AddToWorkList(FoldOp.getNode());
7827 if (Ops.size() == LHS.getNumOperands())
7828 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7829 LHS.getValueType(), &Ops[0], Ops.size());
7835 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
7836 SDValue N1, SDValue N2){
7837 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
7839 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
7840 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7842 // If we got a simplified select_cc node back from SimplifySelectCC, then
7843 // break it down into a new SETCC node, and a new SELECT node, and then return
7844 // the SELECT node, since we were called with a SELECT node.
7845 if (SCC.getNode()) {
7846 // Check to see if we got a select_cc back (to turn into setcc/select).
7847 // Otherwise, just return whatever node we got back, like fabs.
7848 if (SCC.getOpcode() == ISD::SELECT_CC) {
7849 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
7851 SCC.getOperand(0), SCC.getOperand(1),
7853 AddToWorkList(SETCC.getNode());
7854 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
7855 SCC.getOperand(2), SCC.getOperand(3), SETCC);
7863 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
7864 /// are the two values being selected between, see if we can simplify the
7865 /// select. Callers of this should assume that TheSelect is deleted if this
7866 /// returns true. As such, they should return the appropriate thing (e.g. the
7867 /// node) back to the top-level of the DAG combiner loop to avoid it being
7869 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
7872 // Cannot simplify select with vector condition
7873 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
7875 // If this is a select from two identical things, try to pull the operation
7876 // through the select.
7877 if (LHS.getOpcode() != RHS.getOpcode() ||
7878 !LHS.hasOneUse() || !RHS.hasOneUse())
7881 // If this is a load and the token chain is identical, replace the select
7882 // of two loads with a load through a select of the address to load from.
7883 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
7884 // constants have been dropped into the constant pool.
7885 if (LHS.getOpcode() == ISD::LOAD) {
7886 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
7887 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
7889 // Token chains must be identical.
7890 if (LHS.getOperand(0) != RHS.getOperand(0) ||
7891 // Do not let this transformation reduce the number of volatile loads.
7892 LLD->isVolatile() || RLD->isVolatile() ||
7893 // If this is an EXTLOAD, the VT's must match.
7894 LLD->getMemoryVT() != RLD->getMemoryVT() ||
7895 // If this is an EXTLOAD, the kind of extension must match.
7896 (LLD->getExtensionType() != RLD->getExtensionType() &&
7897 // The only exception is if one of the extensions is anyext.
7898 LLD->getExtensionType() != ISD::EXTLOAD &&
7899 RLD->getExtensionType() != ISD::EXTLOAD) ||
7900 // FIXME: this discards src value information. This is
7901 // over-conservative. It would be beneficial to be able to remember
7902 // both potential memory locations. Since we are discarding
7903 // src value info, don't do the transformation if the memory
7904 // locations are not in the default address space.
7905 LLD->getPointerInfo().getAddrSpace() != 0 ||
7906 RLD->getPointerInfo().getAddrSpace() != 0)
7909 // Check that the select condition doesn't reach either load. If so,
7910 // folding this will induce a cycle into the DAG. If not, this is safe to
7911 // xform, so create a select of the addresses.
7913 if (TheSelect->getOpcode() == ISD::SELECT) {
7914 SDNode *CondNode = TheSelect->getOperand(0).getNode();
7915 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
7916 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
7918 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
7919 LLD->getBasePtr().getValueType(),
7920 TheSelect->getOperand(0), LLD->getBasePtr(),
7922 } else { // Otherwise SELECT_CC
7923 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
7924 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
7926 if ((LLD->hasAnyUseOfValue(1) &&
7927 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
7928 (LLD->hasAnyUseOfValue(1) &&
7929 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))))
7932 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
7933 LLD->getBasePtr().getValueType(),
7934 TheSelect->getOperand(0),
7935 TheSelect->getOperand(1),
7936 LLD->getBasePtr(), RLD->getBasePtr(),
7937 TheSelect->getOperand(4));
7941 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
7942 Load = DAG.getLoad(TheSelect->getValueType(0),
7943 TheSelect->getDebugLoc(),
7944 // FIXME: Discards pointer info.
7945 LLD->getChain(), Addr, MachinePointerInfo(),
7946 LLD->isVolatile(), LLD->isNonTemporal(),
7947 LLD->isInvariant(), LLD->getAlignment());
7949 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
7950 RLD->getExtensionType() : LLD->getExtensionType(),
7951 TheSelect->getDebugLoc(),
7952 TheSelect->getValueType(0),
7953 // FIXME: Discards pointer info.
7954 LLD->getChain(), Addr, MachinePointerInfo(),
7955 LLD->getMemoryVT(), LLD->isVolatile(),
7956 LLD->isNonTemporal(), LLD->getAlignment());
7959 // Users of the select now use the result of the load.
7960 CombineTo(TheSelect, Load);
7962 // Users of the old loads now use the new load's chain. We know the
7963 // old-load value is dead now.
7964 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
7965 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
7972 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
7973 /// where 'cond' is the comparison specified by CC.
7974 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
7975 SDValue N2, SDValue N3,
7976 ISD::CondCode CC, bool NotExtCompare) {
7977 // (x ? y : y) -> y.
7978 if (N2 == N3) return N2;
7980 EVT VT = N2.getValueType();
7981 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
7982 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
7983 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
7985 // Determine if the condition we're dealing with is constant
7986 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
7987 N0, N1, CC, DL, false);
7988 if (SCC.getNode()) AddToWorkList(SCC.getNode());
7989 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
7991 // fold select_cc true, x, y -> x
7992 if (SCCC && !SCCC->isNullValue())
7994 // fold select_cc false, x, y -> y
7995 if (SCCC && SCCC->isNullValue())
7998 // Check to see if we can simplify the select into an fabs node
7999 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
8000 // Allow either -0.0 or 0.0
8001 if (CFP->getValueAPF().isZero()) {
8002 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
8003 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
8004 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
8005 N2 == N3.getOperand(0))
8006 return DAG.getNode(ISD::FABS, DL, VT, N0);
8008 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
8009 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
8010 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
8011 N2.getOperand(0) == N3)
8012 return DAG.getNode(ISD::FABS, DL, VT, N3);
8016 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
8017 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
8018 // in it. This is a win when the constant is not otherwise available because
8019 // it replaces two constant pool loads with one. We only do this if the FP
8020 // type is known to be legal, because if it isn't, then we are before legalize
8021 // types an we want the other legalization to happen first (e.g. to avoid
8022 // messing with soft float) and if the ConstantFP is not legal, because if
8023 // it is legal, we may not need to store the FP constant in a constant pool.
8024 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
8025 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
8026 if (TLI.isTypeLegal(N2.getValueType()) &&
8027 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
8028 TargetLowering::Legal) &&
8029 // If both constants have multiple uses, then we won't need to do an
8030 // extra load, they are likely around in registers for other users.
8031 (TV->hasOneUse() || FV->hasOneUse())) {
8032 Constant *Elts[] = {
8033 const_cast<ConstantFP*>(FV->getConstantFPValue()),
8034 const_cast<ConstantFP*>(TV->getConstantFPValue())
8036 Type *FPTy = Elts[0]->getType();
8037 const TargetData &TD = *TLI.getTargetData();
8039 // Create a ConstantArray of the two constants.
8040 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
8041 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
8042 TD.getPrefTypeAlignment(FPTy));
8043 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
8045 // Get the offsets to the 0 and 1 element of the array so that we can
8046 // select between them.
8047 SDValue Zero = DAG.getIntPtrConstant(0);
8048 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
8049 SDValue One = DAG.getIntPtrConstant(EltSize);
8051 SDValue Cond = DAG.getSetCC(DL,
8052 TLI.getSetCCResultType(N0.getValueType()),
8054 AddToWorkList(Cond.getNode());
8055 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
8057 AddToWorkList(CstOffset.getNode());
8058 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
8060 AddToWorkList(CPIdx.getNode());
8061 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
8062 MachinePointerInfo::getConstantPool(), false,
8063 false, false, Alignment);
8068 // Check to see if we can perform the "gzip trick", transforming
8069 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
8070 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
8071 (N1C->isNullValue() || // (a < 0) ? b : 0
8072 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
8073 EVT XType = N0.getValueType();
8074 EVT AType = N2.getValueType();
8075 if (XType.bitsGE(AType)) {
8076 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
8077 // single-bit constant.
8078 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
8079 unsigned ShCtV = N2C->getAPIntValue().logBase2();
8080 ShCtV = XType.getSizeInBits()-ShCtV-1;
8081 SDValue ShCt = DAG.getConstant(ShCtV,
8082 getShiftAmountTy(N0.getValueType()));
8083 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
8085 AddToWorkList(Shift.getNode());
8087 if (XType.bitsGT(AType)) {
8088 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
8089 AddToWorkList(Shift.getNode());
8092 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
8095 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
8097 DAG.getConstant(XType.getSizeInBits()-1,
8098 getShiftAmountTy(N0.getValueType())));
8099 AddToWorkList(Shift.getNode());
8101 if (XType.bitsGT(AType)) {
8102 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
8103 AddToWorkList(Shift.getNode());
8106 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
8110 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
8111 // where y is has a single bit set.
8112 // A plaintext description would be, we can turn the SELECT_CC into an AND
8113 // when the condition can be materialized as an all-ones register. Any
8114 // single bit-test can be materialized as an all-ones register with
8115 // shift-left and shift-right-arith.
8116 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
8117 N0->getValueType(0) == VT &&
8118 N1C && N1C->isNullValue() &&
8119 N2C && N2C->isNullValue()) {
8120 SDValue AndLHS = N0->getOperand(0);
8121 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
8122 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
8123 // Shift the tested bit over the sign bit.
8124 APInt AndMask = ConstAndRHS->getAPIntValue();
8126 DAG.getConstant(AndMask.countLeadingZeros(),
8127 getShiftAmountTy(AndLHS.getValueType()));
8128 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
8130 // Now arithmetic right shift it all the way over, so the result is either
8131 // all-ones, or zero.
8133 DAG.getConstant(AndMask.getBitWidth()-1,
8134 getShiftAmountTy(Shl.getValueType()));
8135 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
8137 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
8141 // fold select C, 16, 0 -> shl C, 4
8142 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
8143 TLI.getBooleanContents(N0.getValueType().isVector()) ==
8144 TargetLowering::ZeroOrOneBooleanContent) {
8146 // If the caller doesn't want us to simplify this into a zext of a compare,
8148 if (NotExtCompare && N2C->getAPIntValue() == 1)
8151 // Get a SetCC of the condition
8152 // FIXME: Should probably make sure that setcc is legal if we ever have a
8153 // target where it isn't.
8155 // cast from setcc result type to select result type
8157 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
8159 if (N2.getValueType().bitsLT(SCC.getValueType()))
8160 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
8162 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8163 N2.getValueType(), SCC);
8165 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
8166 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
8167 N2.getValueType(), SCC);
8170 AddToWorkList(SCC.getNode());
8171 AddToWorkList(Temp.getNode());
8173 if (N2C->getAPIntValue() == 1)
8176 // shl setcc result by log2 n2c
8177 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
8178 DAG.getConstant(N2C->getAPIntValue().logBase2(),
8179 getShiftAmountTy(Temp.getValueType())));
8182 // Check to see if this is the equivalent of setcc
8183 // FIXME: Turn all of these into setcc if setcc if setcc is legal
8184 // otherwise, go ahead with the folds.
8185 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
8186 EVT XType = N0.getValueType();
8187 if (!LegalOperations ||
8188 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
8189 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
8190 if (Res.getValueType() != VT)
8191 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
8195 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
8196 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
8197 (!LegalOperations ||
8198 TLI.isOperationLegal(ISD::CTLZ, XType))) {
8199 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
8200 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
8201 DAG.getConstant(Log2_32(XType.getSizeInBits()),
8202 getShiftAmountTy(Ctlz.getValueType())));
8204 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
8205 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
8206 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
8207 XType, DAG.getConstant(0, XType), N0);
8208 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
8209 return DAG.getNode(ISD::SRL, DL, XType,
8210 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
8211 DAG.getConstant(XType.getSizeInBits()-1,
8212 getShiftAmountTy(XType)));
8214 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
8215 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
8216 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
8217 DAG.getConstant(XType.getSizeInBits()-1,
8218 getShiftAmountTy(N0.getValueType())));
8219 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
8223 // Check to see if this is an integer abs.
8224 // select_cc setg[te] X, 0, X, -X ->
8225 // select_cc setgt X, -1, X, -X ->
8226 // select_cc setl[te] X, 0, -X, X ->
8227 // select_cc setlt X, 1, -X, X ->
8228 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
8230 ConstantSDNode *SubC = NULL;
8231 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
8232 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
8233 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
8234 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
8235 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
8236 (N1C->isOne() && CC == ISD::SETLT)) &&
8237 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
8238 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
8240 EVT XType = N0.getValueType();
8241 if (SubC && SubC->isNullValue() && XType.isInteger()) {
8242 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
8244 DAG.getConstant(XType.getSizeInBits()-1,
8245 getShiftAmountTy(N0.getValueType())));
8246 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
8248 AddToWorkList(Shift.getNode());
8249 AddToWorkList(Add.getNode());
8250 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
8257 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
8258 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
8259 SDValue N1, ISD::CondCode Cond,
8260 DebugLoc DL, bool foldBooleans) {
8261 TargetLowering::DAGCombinerInfo
8262 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
8263 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
8266 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
8267 /// return a DAG expression to select that will generate the same value by
8268 /// multiplying by a magic number. See:
8269 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
8270 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
8271 std::vector<SDNode*> Built;
8272 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built);
8274 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
8280 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
8281 /// return a DAG expression to select that will generate the same value by
8282 /// multiplying by a magic number. See:
8283 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
8284 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
8285 std::vector<SDNode*> Built;
8286 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built);
8288 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
8294 /// FindBaseOffset - Return true if base is a frame index, which is known not
8295 // to alias with anything but itself. Provides base object and offset as
8297 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
8298 const GlobalValue *&GV, void *&CV) {
8299 // Assume it is a primitive operation.
8300 Base = Ptr; Offset = 0; GV = 0; CV = 0;
8302 // If it's an adding a simple constant then integrate the offset.
8303 if (Base.getOpcode() == ISD::ADD) {
8304 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
8305 Base = Base.getOperand(0);
8306 Offset += C->getZExtValue();
8310 // Return the underlying GlobalValue, and update the Offset. Return false
8311 // for GlobalAddressSDNode since the same GlobalAddress may be represented
8312 // by multiple nodes with different offsets.
8313 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
8314 GV = G->getGlobal();
8315 Offset += G->getOffset();
8319 // Return the underlying Constant value, and update the Offset. Return false
8320 // for ConstantSDNodes since the same constant pool entry may be represented
8321 // by multiple nodes with different offsets.
8322 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
8323 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
8324 : (void *)C->getConstVal();
8325 Offset += C->getOffset();
8328 // If it's any of the following then it can't alias with anything but itself.
8329 return isa<FrameIndexSDNode>(Base);
8332 /// isAlias - Return true if there is any possibility that the two addresses
8334 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
8335 const Value *SrcValue1, int SrcValueOffset1,
8336 unsigned SrcValueAlign1,
8337 const MDNode *TBAAInfo1,
8338 SDValue Ptr2, int64_t Size2,
8339 const Value *SrcValue2, int SrcValueOffset2,
8340 unsigned SrcValueAlign2,
8341 const MDNode *TBAAInfo2) const {
8342 // If they are the same then they must be aliases.
8343 if (Ptr1 == Ptr2) return true;
8345 // Gather base node and offset information.
8346 SDValue Base1, Base2;
8347 int64_t Offset1, Offset2;
8348 const GlobalValue *GV1, *GV2;
8350 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
8351 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
8353 // If they have a same base address then check to see if they overlap.
8354 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
8355 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
8357 // It is possible for different frame indices to alias each other, mostly
8358 // when tail call optimization reuses return address slots for arguments.
8359 // To catch this case, look up the actual index of frame indices to compute
8360 // the real alias relationship.
8361 if (isFrameIndex1 && isFrameIndex2) {
8362 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8363 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
8364 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
8365 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
8368 // Otherwise, if we know what the bases are, and they aren't identical, then
8369 // we know they cannot alias.
8370 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
8373 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
8374 // compared to the size and offset of the access, we may be able to prove they
8375 // do not alias. This check is conservative for now to catch cases created by
8376 // splitting vector types.
8377 if ((SrcValueAlign1 == SrcValueAlign2) &&
8378 (SrcValueOffset1 != SrcValueOffset2) &&
8379 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
8380 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
8381 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
8383 // There is no overlap between these relatively aligned accesses of similar
8384 // size, return no alias.
8385 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
8389 if (CombinerGlobalAA) {
8390 // Use alias analysis information.
8391 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
8392 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
8393 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
8394 AliasAnalysis::AliasResult AAResult =
8395 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
8396 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
8397 if (AAResult == AliasAnalysis::NoAlias)
8401 // Otherwise we have to assume they alias.
8405 /// FindAliasInfo - Extracts the relevant alias information from the memory
8406 /// node. Returns true if the operand was a load.
8407 bool DAGCombiner::FindAliasInfo(SDNode *N,
8408 SDValue &Ptr, int64_t &Size,
8409 const Value *&SrcValue,
8410 int &SrcValueOffset,
8411 unsigned &SrcValueAlign,
8412 const MDNode *&TBAAInfo) const {
8413 LSBaseSDNode *LS = cast<LSBaseSDNode>(N);
8415 Ptr = LS->getBasePtr();
8416 Size = LS->getMemoryVT().getSizeInBits() >> 3;
8417 SrcValue = LS->getSrcValue();
8418 SrcValueOffset = LS->getSrcValueOffset();
8419 SrcValueAlign = LS->getOriginalAlignment();
8420 TBAAInfo = LS->getTBAAInfo();
8421 return isa<LoadSDNode>(LS);
8424 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
8425 /// looking for aliasing nodes and adding them to the Aliases vector.
8426 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
8427 SmallVector<SDValue, 8> &Aliases) {
8428 SmallVector<SDValue, 8> Chains; // List of chains to visit.
8429 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
8431 // Get alias information for node.
8434 const Value *SrcValue;
8436 unsigned SrcValueAlign;
8437 const MDNode *SrcTBAAInfo;
8438 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
8439 SrcValueAlign, SrcTBAAInfo);
8442 Chains.push_back(OriginalChain);
8445 // Look at each chain and determine if it is an alias. If so, add it to the
8446 // aliases list. If not, then continue up the chain looking for the next
8448 while (!Chains.empty()) {
8449 SDValue Chain = Chains.back();
8452 // For TokenFactor nodes, look at each operand and only continue up the
8453 // chain until we find two aliases. If we've seen two aliases, assume we'll
8454 // find more and revert to original chain since the xform is unlikely to be
8457 // FIXME: The depth check could be made to return the last non-aliasing
8458 // chain we found before we hit a tokenfactor rather than the original
8460 if (Depth > 6 || Aliases.size() == 2) {
8462 Aliases.push_back(OriginalChain);
8466 // Don't bother if we've been before.
8467 if (!Visited.insert(Chain.getNode()))
8470 switch (Chain.getOpcode()) {
8471 case ISD::EntryToken:
8472 // Entry token is ideal chain operand, but handled in FindBetterChain.
8477 // Get alias information for Chain.
8480 const Value *OpSrcValue;
8481 int OpSrcValueOffset;
8482 unsigned OpSrcValueAlign;
8483 const MDNode *OpSrcTBAAInfo;
8484 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
8485 OpSrcValue, OpSrcValueOffset,
8489 // If chain is alias then stop here.
8490 if (!(IsLoad && IsOpLoad) &&
8491 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
8493 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
8494 OpSrcValueAlign, OpSrcTBAAInfo)) {
8495 Aliases.push_back(Chain);
8497 // Look further up the chain.
8498 Chains.push_back(Chain.getOperand(0));
8504 case ISD::TokenFactor:
8505 // We have to check each of the operands of the token factor for "small"
8506 // token factors, so we queue them up. Adding the operands to the queue
8507 // (stack) in reverse order maintains the original order and increases the
8508 // likelihood that getNode will find a matching token factor (CSE.)
8509 if (Chain.getNumOperands() > 16) {
8510 Aliases.push_back(Chain);
8513 for (unsigned n = Chain.getNumOperands(); n;)
8514 Chains.push_back(Chain.getOperand(--n));
8519 // For all other instructions we will just have to take what we can get.
8520 Aliases.push_back(Chain);
8526 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
8527 /// for a better chain (aliasing node.)
8528 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
8529 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
8531 // Accumulate all the aliases to this node.
8532 GatherAllAliases(N, OldChain, Aliases);
8534 // If no operands then chain to entry token.
8535 if (Aliases.size() == 0)
8536 return DAG.getEntryNode();
8538 // If a single operand then chain to it. We don't need to revisit it.
8539 if (Aliases.size() == 1)
8542 // Construct a custom tailored token factor.
8543 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
8544 &Aliases[0], Aliases.size());
8547 // SelectionDAG::Combine - This is the entry point for the file.
8549 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
8550 CodeGenOpt::Level OptLevel) {
8551 /// run - This is the main entry point to this class.
8553 DAGCombiner(*this, AA, OptLevel).Run(Level);