1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "dagcombine"
16 #include "llvm/CodeGen/SelectionDAG.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetFrameInfo.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/SmallPtrSet.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
37 STATISTIC(NodesCombined , "Number of dag nodes combined");
38 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
39 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
43 CombinerAA("combiner-alias-analysis", cl::Hidden,
44 cl::desc("Turn on alias analysis during testing"));
47 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
48 cl::desc("Include global information in alias analysis"));
50 //------------------------------ DAGCombiner ---------------------------------//
52 class VISIBILITY_HIDDEN DAGCombiner {
54 const TargetLowering &TLI;
60 // Worklist of all of the nodes that need to be simplified.
61 std::vector<SDNode*> WorkList;
63 // AA - Used for DAG load/store alias analysis.
66 /// AddUsersToWorkList - When an instruction is simplified, add all users of
67 /// the instruction to the work lists because they might get more simplified
70 void AddUsersToWorkList(SDNode *N) {
71 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
76 /// visit - call the node-specific routine that knows how to fold each
77 /// particular type of node.
78 SDValue visit(SDNode *N);
81 /// AddToWorkList - Add to the work list making sure it's instance is at the
82 /// the back (next to be processed.)
83 void AddToWorkList(SDNode *N) {
84 removeFromWorkList(N);
85 WorkList.push_back(N);
88 /// removeFromWorkList - remove all instances of N from the worklist.
90 void removeFromWorkList(SDNode *N) {
91 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
95 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
98 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
99 return CombineTo(N, &Res, 1, AddTo);
102 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
104 SDValue To[] = { Res0, Res1 };
105 return CombineTo(N, To, 2, AddTo);
108 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
112 /// SimplifyDemandedBits - Check the specified integer node value to see if
113 /// it can be simplified or if things it uses can be simplified by bit
114 /// propagation. If so, return true.
115 bool SimplifyDemandedBits(SDValue Op) {
116 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits());
117 return SimplifyDemandedBits(Op, Demanded);
120 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
122 bool CombineToPreIndexedLoadStore(SDNode *N);
123 bool CombineToPostIndexedLoadStore(SDNode *N);
126 /// combine - call the node-specific routine that knows how to fold each
127 /// particular type of node. If that doesn't do anything, try the
128 /// target-specific DAG combines.
129 SDValue combine(SDNode *N);
131 // Visitation implementation - Implement dag node combining for different
132 // node types. The semantics are as follows:
134 // SDValue.getNode() == 0 - No change was made
135 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
136 // otherwise - N should be replaced by the returned Operand.
138 SDValue visitTokenFactor(SDNode *N);
139 SDValue visitMERGE_VALUES(SDNode *N);
140 SDValue visitADD(SDNode *N);
141 SDValue visitSUB(SDNode *N);
142 SDValue visitADDC(SDNode *N);
143 SDValue visitADDE(SDNode *N);
144 SDValue visitMUL(SDNode *N);
145 SDValue visitSDIV(SDNode *N);
146 SDValue visitUDIV(SDNode *N);
147 SDValue visitSREM(SDNode *N);
148 SDValue visitUREM(SDNode *N);
149 SDValue visitMULHU(SDNode *N);
150 SDValue visitMULHS(SDNode *N);
151 SDValue visitSMUL_LOHI(SDNode *N);
152 SDValue visitUMUL_LOHI(SDNode *N);
153 SDValue visitSDIVREM(SDNode *N);
154 SDValue visitUDIVREM(SDNode *N);
155 SDValue visitAND(SDNode *N);
156 SDValue visitOR(SDNode *N);
157 SDValue visitXOR(SDNode *N);
158 SDValue SimplifyVBinOp(SDNode *N);
159 SDValue visitSHL(SDNode *N);
160 SDValue visitSRA(SDNode *N);
161 SDValue visitSRL(SDNode *N);
162 SDValue visitCTLZ(SDNode *N);
163 SDValue visitCTTZ(SDNode *N);
164 SDValue visitCTPOP(SDNode *N);
165 SDValue visitSELECT(SDNode *N);
166 SDValue visitSELECT_CC(SDNode *N);
167 SDValue visitSETCC(SDNode *N);
168 SDValue visitSIGN_EXTEND(SDNode *N);
169 SDValue visitZERO_EXTEND(SDNode *N);
170 SDValue visitANY_EXTEND(SDNode *N);
171 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
172 SDValue visitTRUNCATE(SDNode *N);
173 SDValue visitBIT_CONVERT(SDNode *N);
174 SDValue visitBUILD_PAIR(SDNode *N);
175 SDValue visitFADD(SDNode *N);
176 SDValue visitFSUB(SDNode *N);
177 SDValue visitFMUL(SDNode *N);
178 SDValue visitFDIV(SDNode *N);
179 SDValue visitFREM(SDNode *N);
180 SDValue visitFCOPYSIGN(SDNode *N);
181 SDValue visitSINT_TO_FP(SDNode *N);
182 SDValue visitUINT_TO_FP(SDNode *N);
183 SDValue visitFP_TO_SINT(SDNode *N);
184 SDValue visitFP_TO_UINT(SDNode *N);
185 SDValue visitFP_ROUND(SDNode *N);
186 SDValue visitFP_ROUND_INREG(SDNode *N);
187 SDValue visitFP_EXTEND(SDNode *N);
188 SDValue visitFNEG(SDNode *N);
189 SDValue visitFABS(SDNode *N);
190 SDValue visitBRCOND(SDNode *N);
191 SDValue visitBR_CC(SDNode *N);
192 SDValue visitLOAD(SDNode *N);
193 SDValue visitSTORE(SDNode *N);
194 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
195 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
196 SDValue visitBUILD_VECTOR(SDNode *N);
197 SDValue visitCONCAT_VECTORS(SDNode *N);
198 SDValue visitVECTOR_SHUFFLE(SDNode *N);
200 SDValue XformToShuffleWithZero(SDNode *N);
201 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
203 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
205 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
206 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
207 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
208 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
209 SDValue N3, ISD::CondCode CC,
210 bool NotExtCompare = false);
211 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
212 DebugLoc DL, bool foldBooleans = true);
213 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
215 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
216 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
217 SDValue BuildSDIV(SDNode *N);
218 SDValue BuildUDIV(SDNode *N);
219 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
220 SDValue ReduceLoadWidth(SDNode *N);
222 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
224 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
225 /// looking for aliasing nodes and adding them to the Aliases vector.
226 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
227 SmallVector<SDValue, 8> &Aliases);
229 /// isAlias - Return true if there is any possibility that the two addresses
231 bool isAlias(SDValue Ptr1, int64_t Size1,
232 const Value *SrcValue1, int SrcValueOffset1,
233 SDValue Ptr2, int64_t Size2,
234 const Value *SrcValue2, int SrcValueOffset2) const;
236 /// FindAliasInfo - Extracts the relevant alias information from the memory
237 /// node. Returns true if the operand was a load.
238 bool FindAliasInfo(SDNode *N,
239 SDValue &Ptr, int64_t &Size,
240 const Value *&SrcValue, int &SrcValueOffset) const;
242 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
243 /// looking for a better chain (aliasing node.)
244 SDValue FindBetterChain(SDNode *N, SDValue Chain);
246 /// getShiftAmountTy - Returns a type large enough to hold any valid
247 /// shift amount - before type legalization these can be huge.
248 MVT getShiftAmountTy() {
249 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
253 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
255 TLI(D.getTargetLoweringInfo()),
257 LegalOperations(false),
262 /// Run - runs the dag combiner on all nodes in the work list
263 void Run(CombineLevel AtLevel);
269 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
270 /// nodes from the worklist.
271 class VISIBILITY_HIDDEN WorkListRemover :
272 public SelectionDAG::DAGUpdateListener {
275 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
277 virtual void NodeDeleted(SDNode *N, SDNode *E) {
278 DC.removeFromWorkList(N);
281 virtual void NodeUpdated(SDNode *N) {
287 //===----------------------------------------------------------------------===//
288 // TargetLowering::DAGCombinerInfo implementation
289 //===----------------------------------------------------------------------===//
291 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
292 ((DAGCombiner*)DC)->AddToWorkList(N);
295 SDValue TargetLowering::DAGCombinerInfo::
296 CombineTo(SDNode *N, const std::vector<SDValue> &To) {
297 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
300 SDValue TargetLowering::DAGCombinerInfo::
301 CombineTo(SDNode *N, SDValue Res) {
302 return ((DAGCombiner*)DC)->CombineTo(N, Res);
306 SDValue TargetLowering::DAGCombinerInfo::
307 CombineTo(SDNode *N, SDValue Res0, SDValue Res1) {
308 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
311 void TargetLowering::DAGCombinerInfo::
312 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
313 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
316 //===----------------------------------------------------------------------===//
318 //===----------------------------------------------------------------------===//
320 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
321 /// specified expression for the same cost as the expression itself, or 2 if we
322 /// can compute the negated form more cheaply than the expression itself.
323 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
324 unsigned Depth = 0) {
325 // No compile time optimizations on this type.
326 if (Op.getValueType() == MVT::ppcf128)
329 // fneg is removable even if it has multiple uses.
330 if (Op.getOpcode() == ISD::FNEG) return 2;
332 // Don't allow anything with multiple uses.
333 if (!Op.hasOneUse()) return 0;
335 // Don't recurse exponentially.
336 if (Depth > 6) return 0;
338 switch (Op.getOpcode()) {
339 default: return false;
340 case ISD::ConstantFP:
341 // Don't invert constant FP values after legalize. The negated constant
342 // isn't necessarily legal.
343 return LegalOperations ? 0 : 1;
345 // FIXME: determine better conditions for this xform.
346 if (!UnsafeFPMath) return 0;
348 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
349 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
351 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
352 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
354 // We can't turn -(A-B) into B-A when we honor signed zeros.
355 if (!UnsafeFPMath) return 0;
357 // fold (fneg (fsub A, B)) -> (fsub B, A)
362 if (HonorSignDependentRoundingFPMath()) return 0;
364 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
365 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
368 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
373 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
377 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
378 /// returns the newly negated expression.
379 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
380 bool LegalOperations, unsigned Depth = 0) {
381 // fneg is removable even if it has multiple uses.
382 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
384 // Don't allow anything with multiple uses.
385 assert(Op.hasOneUse() && "Unknown reuse!");
387 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
388 switch (Op.getOpcode()) {
389 default: assert(0 && "Unknown code");
390 case ISD::ConstantFP: {
391 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
393 return DAG.getConstantFP(V, Op.getValueType());
396 // FIXME: determine better conditions for this xform.
397 assert(UnsafeFPMath);
399 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
400 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
401 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
402 GetNegatedExpression(Op.getOperand(0), DAG,
403 LegalOperations, Depth+1),
405 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
406 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
407 GetNegatedExpression(Op.getOperand(1), DAG,
408 LegalOperations, Depth+1),
411 // We can't turn -(A-B) into B-A when we honor signed zeros.
412 assert(UnsafeFPMath);
414 // fold (fneg (fsub 0, B)) -> B
415 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
416 if (N0CFP->getValueAPF().isZero())
417 return Op.getOperand(1);
419 // fold (fneg (fsub A, B)) -> (fsub B, A)
420 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
421 Op.getOperand(1), Op.getOperand(0));
425 assert(!HonorSignDependentRoundingFPMath());
427 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
428 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
429 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
430 GetNegatedExpression(Op.getOperand(0), DAG,
431 LegalOperations, Depth+1),
434 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
435 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
437 GetNegatedExpression(Op.getOperand(1), DAG,
438 LegalOperations, Depth+1));
442 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
443 GetNegatedExpression(Op.getOperand(0), DAG,
444 LegalOperations, Depth+1));
446 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
447 GetNegatedExpression(Op.getOperand(0), DAG,
448 LegalOperations, Depth+1),
454 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
455 // that selects between the values 1 and 0, making it equivalent to a setcc.
456 // Also, set the incoming LHS, RHS, and CC references to the appropriate
457 // nodes based on the type of node we are checking. This simplifies life a
458 // bit for the callers.
459 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
461 if (N.getOpcode() == ISD::SETCC) {
462 LHS = N.getOperand(0);
463 RHS = N.getOperand(1);
464 CC = N.getOperand(2);
467 if (N.getOpcode() == ISD::SELECT_CC &&
468 N.getOperand(2).getOpcode() == ISD::Constant &&
469 N.getOperand(3).getOpcode() == ISD::Constant &&
470 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
471 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
472 LHS = N.getOperand(0);
473 RHS = N.getOperand(1);
474 CC = N.getOperand(4);
480 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
481 // one use. If this is true, it allows the users to invert the operation for
482 // free when it is profitable to do so.
483 static bool isOneUseSetCC(SDValue N) {
485 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
490 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
491 SDValue N0, SDValue N1) {
492 MVT VT = N0.getValueType();
493 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
494 if (isa<ConstantSDNode>(N1)) {
495 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
497 DAG.FoldConstantArithmetic(Opc, VT,
498 cast<ConstantSDNode>(N0.getOperand(1)),
499 cast<ConstantSDNode>(N1));
500 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
501 } else if (N0.hasOneUse()) {
502 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
503 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
504 N0.getOperand(0), N1);
505 AddToWorkList(OpNode.getNode());
506 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
510 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
511 if (isa<ConstantSDNode>(N0)) {
512 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
514 DAG.FoldConstantArithmetic(Opc, VT,
515 cast<ConstantSDNode>(N1.getOperand(1)),
516 cast<ConstantSDNode>(N0));
517 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
518 } else if (N1.hasOneUse()) {
519 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
520 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
521 N1.getOperand(0), N0);
522 AddToWorkList(OpNode.getNode());
523 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
530 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
532 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
534 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
535 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG));
536 DOUT << " and " << NumTo-1 << " other values\n";
537 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i)
538 assert(N->getValueType(i) == To[i].getValueType() &&
539 "Cannot combine value to value of different type!"));
540 WorkListRemover DeadNodes(*this);
541 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
544 // Push the new nodes and any users onto the worklist
545 for (unsigned i = 0, e = NumTo; i != e; ++i) {
546 AddToWorkList(To[i].getNode());
547 AddUsersToWorkList(To[i].getNode());
551 // Finally, if the node is now dead, remove it from the graph. The node
552 // may not be dead if the replacement process recursively simplified to
553 // something else needing this node.
554 if (N->use_empty()) {
555 // Nodes can be reintroduced into the worklist. Make sure we do not
556 // process a node that has been replaced.
557 removeFromWorkList(N);
559 // Finally, since the node is now dead, remove it from the graph.
562 return SDValue(N, 0);
566 DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &
568 // Replace all uses. If any nodes become isomorphic to other nodes and
569 // are deleted, make sure to remove them from our worklist.
570 WorkListRemover DeadNodes(*this);
571 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
573 // Push the new node and any (possibly new) users onto the worklist.
574 AddToWorkList(TLO.New.getNode());
575 AddUsersToWorkList(TLO.New.getNode());
577 // Finally, if the node is now dead, remove it from the graph. The node
578 // may not be dead if the replacement process recursively simplified to
579 // something else needing this node.
580 if (TLO.Old.getNode()->use_empty()) {
581 removeFromWorkList(TLO.Old.getNode());
583 // If the operands of this node are only used by the node, they will now
584 // be dead. Make sure to visit them first to delete dead nodes early.
585 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
586 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
587 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
589 DAG.DeleteNode(TLO.Old.getNode());
593 /// SimplifyDemandedBits - Check the specified integer node value to see if
594 /// it can be simplified or if things it uses can be simplified by bit
595 /// propagation. If so, return true.
596 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
597 TargetLowering::TargetLoweringOpt TLO(DAG);
598 APInt KnownZero, KnownOne;
599 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
603 AddToWorkList(Op.getNode());
605 // Replace the old value with the new one.
607 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
608 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
611 CommitTargetLoweringOpt(TLO);
615 //===----------------------------------------------------------------------===//
616 // Main DAG Combiner implementation
617 //===----------------------------------------------------------------------===//
619 void DAGCombiner::Run(CombineLevel AtLevel) {
620 // set the instance variables, so that the various visit routines may use it.
622 LegalOperations = Level >= NoIllegalOperations;
623 LegalTypes = Level >= NoIllegalTypes;
625 // Add all the dag nodes to the worklist.
626 WorkList.reserve(DAG.allnodes_size());
627 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
628 E = DAG.allnodes_end(); I != E; ++I)
629 WorkList.push_back(I);
631 // Create a dummy node (which is not added to allnodes), that adds a reference
632 // to the root node, preventing it from being deleted, and tracking any
633 // changes of the root.
634 HandleSDNode Dummy(DAG.getRoot());
636 // The root of the dag may dangle to deleted nodes until the dag combiner is
637 // done. Set it to null to avoid confusion.
638 DAG.setRoot(SDValue());
640 // while the worklist isn't empty, inspect the node on the end of it and
641 // try and combine it.
642 while (!WorkList.empty()) {
643 SDNode *N = WorkList.back();
646 // If N has no uses, it is dead. Make sure to revisit all N's operands once
647 // N is deleted from the DAG, since they too may now be dead or may have a
648 // reduced number of uses, allowing other xforms.
649 if (N->use_empty() && N != &Dummy) {
650 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
651 AddToWorkList(N->getOperand(i).getNode());
657 SDValue RV = combine(N);
659 if (RV.getNode() == 0)
664 // If we get back the same node we passed in, rather than a new node or
665 // zero, we know that the node must have defined multiple values and
666 // CombineTo was used. Since CombineTo takes care of the worklist
667 // mechanics for us, we have no work to do in this case.
668 if (RV.getNode() == N)
671 assert(N->getOpcode() != ISD::DELETED_NODE &&
672 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
673 "Node was deleted but visit returned new node!");
675 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
676 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG));
678 WorkListRemover DeadNodes(*this);
679 if (N->getNumValues() == RV.getNode()->getNumValues())
680 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
682 assert(N->getValueType(0) == RV.getValueType() &&
683 N->getNumValues() == 1 && "Type mismatch");
685 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
688 // Push the new node and any users onto the worklist
689 AddToWorkList(RV.getNode());
690 AddUsersToWorkList(RV.getNode());
692 // Add any uses of the old node to the worklist in case this node is the
693 // last one that uses them. They may become dead after this node is
695 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
696 AddToWorkList(N->getOperand(i).getNode());
698 // Finally, if the node is now dead, remove it from the graph. The node
699 // may not be dead if the replacement process recursively simplified to
700 // something else needing this node.
701 if (N->use_empty()) {
702 // Nodes can be reintroduced into the worklist. Make sure we do not
703 // process a node that has been replaced.
704 removeFromWorkList(N);
706 // Finally, since the node is now dead, remove it from the graph.
711 // If the root changed (e.g. it was a dead load, update the root).
712 DAG.setRoot(Dummy.getValue());
715 SDValue DAGCombiner::visit(SDNode *N) {
716 switch(N->getOpcode()) {
718 case ISD::TokenFactor: return visitTokenFactor(N);
719 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
720 case ISD::ADD: return visitADD(N);
721 case ISD::SUB: return visitSUB(N);
722 case ISD::ADDC: return visitADDC(N);
723 case ISD::ADDE: return visitADDE(N);
724 case ISD::MUL: return visitMUL(N);
725 case ISD::SDIV: return visitSDIV(N);
726 case ISD::UDIV: return visitUDIV(N);
727 case ISD::SREM: return visitSREM(N);
728 case ISD::UREM: return visitUREM(N);
729 case ISD::MULHU: return visitMULHU(N);
730 case ISD::MULHS: return visitMULHS(N);
731 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
732 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
733 case ISD::SDIVREM: return visitSDIVREM(N);
734 case ISD::UDIVREM: return visitUDIVREM(N);
735 case ISD::AND: return visitAND(N);
736 case ISD::OR: return visitOR(N);
737 case ISD::XOR: return visitXOR(N);
738 case ISD::SHL: return visitSHL(N);
739 case ISD::SRA: return visitSRA(N);
740 case ISD::SRL: return visitSRL(N);
741 case ISD::CTLZ: return visitCTLZ(N);
742 case ISD::CTTZ: return visitCTTZ(N);
743 case ISD::CTPOP: return visitCTPOP(N);
744 case ISD::SELECT: return visitSELECT(N);
745 case ISD::SELECT_CC: return visitSELECT_CC(N);
746 case ISD::SETCC: return visitSETCC(N);
747 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
748 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
749 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
750 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
751 case ISD::TRUNCATE: return visitTRUNCATE(N);
752 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
753 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
754 case ISD::FADD: return visitFADD(N);
755 case ISD::FSUB: return visitFSUB(N);
756 case ISD::FMUL: return visitFMUL(N);
757 case ISD::FDIV: return visitFDIV(N);
758 case ISD::FREM: return visitFREM(N);
759 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
760 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
761 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
762 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
763 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
764 case ISD::FP_ROUND: return visitFP_ROUND(N);
765 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
766 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
767 case ISD::FNEG: return visitFNEG(N);
768 case ISD::FABS: return visitFABS(N);
769 case ISD::BRCOND: return visitBRCOND(N);
770 case ISD::BR_CC: return visitBR_CC(N);
771 case ISD::LOAD: return visitLOAD(N);
772 case ISD::STORE: return visitSTORE(N);
773 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
774 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
775 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
776 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
777 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
782 SDValue DAGCombiner::combine(SDNode *N) {
783 SDValue RV = visit(N);
785 // If nothing happened, try a target-specific DAG combine.
786 if (RV.getNode() == 0) {
787 assert(N->getOpcode() != ISD::DELETED_NODE &&
788 "Node was deleted but visit returned NULL!");
790 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
791 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
793 // Expose the DAG combiner to the target combiner impls.
794 TargetLowering::DAGCombinerInfo
795 DagCombineInfo(DAG, Level == Unrestricted, false, this);
797 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
801 // If N is a commutative binary node, try commuting it to enable more
803 if (RV.getNode() == 0 &&
804 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
805 N->getNumValues() == 1) {
806 SDValue N0 = N->getOperand(0);
807 SDValue N1 = N->getOperand(1);
809 // Constant operands are canonicalized to RHS.
810 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
811 SDValue Ops[] = { N1, N0 };
812 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
815 return SDValue(CSENode, 0);
822 /// getInputChainForNode - Given a node, return its input chain if it has one,
823 /// otherwise return a null sd operand.
824 static SDValue getInputChainForNode(SDNode *N) {
825 if (unsigned NumOps = N->getNumOperands()) {
826 if (N->getOperand(0).getValueType() == MVT::Other)
827 return N->getOperand(0);
828 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
829 return N->getOperand(NumOps-1);
830 for (unsigned i = 1; i < NumOps-1; ++i)
831 if (N->getOperand(i).getValueType() == MVT::Other)
832 return N->getOperand(i);
837 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
838 // If N has two operands, where one has an input chain equal to the other,
839 // the 'other' chain is redundant.
840 if (N->getNumOperands() == 2) {
841 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
842 return N->getOperand(0);
843 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
844 return N->getOperand(1);
847 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
848 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
849 SmallPtrSet<SDNode*, 16> SeenOps;
850 bool Changed = false; // If we should replace this token factor.
852 // Start out with this token factor.
855 // Iterate through token factors. The TFs grows when new token factors are
857 for (unsigned i = 0; i < TFs.size(); ++i) {
860 // Check each of the operands.
861 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
862 SDValue Op = TF->getOperand(i);
864 switch (Op.getOpcode()) {
865 case ISD::EntryToken:
866 // Entry tokens don't need to be added to the list. They are
871 case ISD::TokenFactor:
872 if ((CombinerAA || Op.hasOneUse()) &&
873 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
874 // Queue up for processing.
875 TFs.push_back(Op.getNode());
876 // Clean up in case the token factor is removed.
877 AddToWorkList(Op.getNode());
884 // Only add if it isn't already in the list.
885 if (SeenOps.insert(Op.getNode()))
896 // If we've change things around then replace token factor.
899 // The entry token is the only possible outcome.
900 Result = DAG.getEntryNode();
902 // New and improved token factor.
903 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
904 MVT::Other, &Ops[0], Ops.size());
907 // Don't add users to work list.
908 return CombineTo(N, Result, false);
914 /// MERGE_VALUES can always be eliminated.
915 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
916 WorkListRemover DeadNodes(*this);
917 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
918 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
920 removeFromWorkList(N);
922 return SDValue(N, 0); // Return N so it doesn't get rechecked!
926 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
928 MVT VT = N0.getValueType();
929 SDValue N00 = N0.getOperand(0);
930 SDValue N01 = N0.getOperand(1);
931 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
933 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
934 isa<ConstantSDNode>(N00.getOperand(1))) {
935 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
936 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
937 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
938 N00.getOperand(0), N01),
939 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
940 N00.getOperand(1), N01));
941 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
948 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
949 SelectionDAG &DAG, const TargetLowering &TLI,
950 bool LegalOperations) {
951 MVT VT = N->getValueType(0);
952 unsigned Opc = N->getOpcode();
953 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
954 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
955 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
956 ISD::CondCode CC = ISD::SETCC_INVALID;
959 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
961 SDValue CCOp = Slct.getOperand(0);
962 if (CCOp.getOpcode() == ISD::SETCC)
963 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
966 bool DoXform = false;
968 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
971 if (LHS.getOpcode() == ISD::Constant &&
972 cast<ConstantSDNode>(LHS)->isNullValue()) {
974 } else if (CC != ISD::SETCC_INVALID &&
975 RHS.getOpcode() == ISD::Constant &&
976 cast<ConstantSDNode>(RHS)->isNullValue()) {
978 SDValue Op0 = Slct.getOperand(0);
979 MVT OpVT = isSlctCC ? Op0.getValueType() :
980 Op0.getOperand(0).getValueType();
981 bool isInt = OpVT.isInteger();
982 CC = ISD::getSetCCInverse(CC, isInt);
984 if (LegalOperations && !TLI.isCondCodeLegal(CC, OpVT))
985 return SDValue(); // Inverse operator isn't legal.
992 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
994 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
995 Slct.getOperand(0), Slct.getOperand(1), CC);
996 SDValue CCOp = Slct.getOperand(0);
998 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
999 CCOp.getOperand(0), CCOp.getOperand(1), CC);
1000 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
1001 CCOp, OtherOp, Result);
1006 SDValue DAGCombiner::visitADD(SDNode *N) {
1007 SDValue N0 = N->getOperand(0);
1008 SDValue N1 = N->getOperand(1);
1009 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1010 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1011 MVT VT = N0.getValueType();
1014 if (VT.isVector()) {
1015 SDValue FoldedVOp = SimplifyVBinOp(N);
1016 if (FoldedVOp.getNode()) return FoldedVOp;
1019 // fold (add x, undef) -> undef
1020 if (N0.getOpcode() == ISD::UNDEF)
1022 if (N1.getOpcode() == ISD::UNDEF)
1024 // fold (add c1, c2) -> c1+c2
1026 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1027 // canonicalize constant to RHS
1029 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1030 // fold (add x, 0) -> x
1031 if (N1C && N1C->isNullValue())
1033 // fold (add Sym, c) -> Sym+c
1034 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1035 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1036 GA->getOpcode() == ISD::GlobalAddress)
1037 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1039 (uint64_t)N1C->getSExtValue());
1040 // fold ((c1-A)+c2) -> (c1+c2)-A
1041 if (N1C && N0.getOpcode() == ISD::SUB)
1042 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1043 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1044 DAG.getConstant(N1C->getAPIntValue()+
1045 N0C->getAPIntValue(), VT),
1048 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1049 if (RADD.getNode() != 0)
1051 // fold ((0-A) + B) -> B-A
1052 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1053 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1054 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1055 // fold (A + (0-B)) -> A-B
1056 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1057 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1058 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1059 // fold (A+(B-A)) -> B
1060 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1061 return N1.getOperand(0);
1062 // fold ((B-A)+A) -> B
1063 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1064 return N0.getOperand(0);
1065 // fold (A+(B-(A+C))) to (B-C)
1066 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1067 N0 == N1.getOperand(1).getOperand(0))
1068 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1069 N1.getOperand(1).getOperand(1));
1070 // fold (A+(B-(C+A))) to (B-C)
1071 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1072 N0 == N1.getOperand(1).getOperand(1))
1073 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1074 N1.getOperand(1).getOperand(0));
1075 // fold (A+((B-A)+or-C)) to (B+or-C)
1076 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1077 N1.getOperand(0).getOpcode() == ISD::SUB &&
1078 N0 == N1.getOperand(0).getOperand(1))
1079 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1080 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1082 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1083 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1084 SDValue N00 = N0.getOperand(0);
1085 SDValue N01 = N0.getOperand(1);
1086 SDValue N10 = N1.getOperand(0);
1087 SDValue N11 = N1.getOperand(1);
1089 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1090 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1091 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1092 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1095 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1096 return SDValue(N, 0);
1098 // fold (a+b) -> (a|b) iff a and b share no bits.
1099 if (VT.isInteger() && !VT.isVector()) {
1100 APInt LHSZero, LHSOne;
1101 APInt RHSZero, RHSOne;
1102 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1103 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1105 if (LHSZero.getBoolValue()) {
1106 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1108 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1109 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1110 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1111 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1112 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1116 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1117 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1118 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1119 if (Result.getNode()) return Result;
1121 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1122 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1123 if (Result.getNode()) return Result;
1126 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1127 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
1128 SDValue Result = combineSelectAndUse(N, N0, N1, DAG, TLI, LegalOperations);
1129 if (Result.getNode()) return Result;
1131 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1132 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations);
1133 if (Result.getNode()) return Result;
1139 SDValue DAGCombiner::visitADDC(SDNode *N) {
1140 SDValue N0 = N->getOperand(0);
1141 SDValue N1 = N->getOperand(1);
1142 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1143 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1144 MVT VT = N0.getValueType();
1146 // If the flag result is dead, turn this into an ADD.
1147 if (N->hasNUsesOfValue(0, 1))
1148 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1149 DAG.getNode(ISD::CARRY_FALSE,
1150 N->getDebugLoc(), MVT::Flag));
1152 // canonicalize constant to RHS.
1154 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1156 // fold (addc x, 0) -> x + no carry out
1157 if (N1C && N1C->isNullValue())
1158 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1159 N->getDebugLoc(), MVT::Flag));
1161 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1162 APInt LHSZero, LHSOne;
1163 APInt RHSZero, RHSOne;
1164 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1165 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1167 if (LHSZero.getBoolValue()) {
1168 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1170 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1171 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1172 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1173 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1174 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1175 DAG.getNode(ISD::CARRY_FALSE,
1176 N->getDebugLoc(), MVT::Flag));
1182 SDValue DAGCombiner::visitADDE(SDNode *N) {
1183 SDValue N0 = N->getOperand(0);
1184 SDValue N1 = N->getOperand(1);
1185 SDValue CarryIn = N->getOperand(2);
1186 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1187 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1189 // canonicalize constant to RHS
1191 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1194 // fold (adde x, y, false) -> (addc x, y)
1195 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1196 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1201 SDValue DAGCombiner::visitSUB(SDNode *N) {
1202 SDValue N0 = N->getOperand(0);
1203 SDValue N1 = N->getOperand(1);
1204 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1205 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1206 MVT VT = N0.getValueType();
1209 if (VT.isVector()) {
1210 SDValue FoldedVOp = SimplifyVBinOp(N);
1211 if (FoldedVOp.getNode()) return FoldedVOp;
1214 // fold (sub x, x) -> 0
1216 return DAG.getConstant(0, N->getValueType(0));
1217 // fold (sub c1, c2) -> c1-c2
1219 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1220 // fold (sub x, c) -> (add x, -c)
1222 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1223 DAG.getConstant(-N1C->getAPIntValue(), VT));
1224 // fold (A+B)-A -> B
1225 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1226 return N0.getOperand(1);
1227 // fold (A+B)-B -> A
1228 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1229 return N0.getOperand(0);
1230 // fold ((A+(B+or-C))-B) -> A+or-C
1231 if (N0.getOpcode() == ISD::ADD &&
1232 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1233 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1234 N0.getOperand(1).getOperand(0) == N1)
1235 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1236 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1237 // fold ((A+(C+B))-B) -> A+C
1238 if (N0.getOpcode() == ISD::ADD &&
1239 N0.getOperand(1).getOpcode() == ISD::ADD &&
1240 N0.getOperand(1).getOperand(1) == N1)
1241 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1242 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1243 // fold ((A-(B-C))-C) -> A-B
1244 if (N0.getOpcode() == ISD::SUB &&
1245 N0.getOperand(1).getOpcode() == ISD::SUB &&
1246 N0.getOperand(1).getOperand(1) == N1)
1247 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1248 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1249 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1250 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1251 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations);
1252 if (Result.getNode()) return Result;
1255 // If either operand of a sub is undef, the result is undef
1256 if (N0.getOpcode() == ISD::UNDEF)
1258 if (N1.getOpcode() == ISD::UNDEF)
1261 // If the relocation model supports it, consider symbol offsets.
1262 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1263 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1264 // fold (sub Sym, c) -> Sym-c
1265 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1266 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1268 (uint64_t)N1C->getSExtValue());
1269 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1270 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1271 if (GA->getGlobal() == GB->getGlobal())
1272 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1279 SDValue DAGCombiner::visitMUL(SDNode *N) {
1280 SDValue N0 = N->getOperand(0);
1281 SDValue N1 = N->getOperand(1);
1282 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1283 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1284 MVT VT = N0.getValueType();
1287 if (VT.isVector()) {
1288 SDValue FoldedVOp = SimplifyVBinOp(N);
1289 if (FoldedVOp.getNode()) return FoldedVOp;
1292 // fold (mul x, undef) -> 0
1293 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1294 return DAG.getConstant(0, VT);
1295 // fold (mul c1, c2) -> c1*c2
1297 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1298 // canonicalize constant to RHS
1300 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1301 // fold (mul x, 0) -> 0
1302 if (N1C && N1C->isNullValue())
1304 // fold (mul x, -1) -> 0-x
1305 if (N1C && N1C->isAllOnesValue())
1306 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1307 DAG.getConstant(0, VT), N0);
1308 // fold (mul x, (1 << c)) -> x << c
1309 if (N1C && N1C->getAPIntValue().isPowerOf2())
1310 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1311 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1312 getShiftAmountTy()));
1313 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1314 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1315 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1316 // FIXME: If the input is something that is easily negated (e.g. a
1317 // single-use add), we should put the negate there.
1318 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1319 DAG.getConstant(0, VT),
1320 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1321 DAG.getConstant(Log2Val, getShiftAmountTy())));
1323 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1324 if (N1C && N0.getOpcode() == ISD::SHL &&
1325 isa<ConstantSDNode>(N0.getOperand(1))) {
1326 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1327 N1, N0.getOperand(1));
1328 AddToWorkList(C3.getNode());
1329 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1330 N0.getOperand(0), C3);
1333 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1336 SDValue Sh(0,0), Y(0,0);
1337 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1338 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1339 N0.getNode()->hasOneUse()) {
1341 } else if (N1.getOpcode() == ISD::SHL &&
1342 isa<ConstantSDNode>(N1.getOperand(1)) &&
1343 N1.getNode()->hasOneUse()) {
1348 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1349 Sh.getOperand(0), Y);
1350 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1351 Mul, Sh.getOperand(1));
1355 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1356 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1357 isa<ConstantSDNode>(N0.getOperand(1)))
1358 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1359 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1360 N0.getOperand(0), N1),
1361 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1362 N0.getOperand(1), N1));
1365 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1366 if (RMUL.getNode() != 0)
1372 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1373 SDValue N0 = N->getOperand(0);
1374 SDValue N1 = N->getOperand(1);
1375 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1376 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1377 MVT VT = N->getValueType(0);
1380 if (VT.isVector()) {
1381 SDValue FoldedVOp = SimplifyVBinOp(N);
1382 if (FoldedVOp.getNode()) return FoldedVOp;
1385 // fold (sdiv c1, c2) -> c1/c2
1386 if (N0C && N1C && !N1C->isNullValue())
1387 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1388 // fold (sdiv X, 1) -> X
1389 if (N1C && N1C->getSExtValue() == 1LL)
1391 // fold (sdiv X, -1) -> 0-X
1392 if (N1C && N1C->isAllOnesValue())
1393 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1394 DAG.getConstant(0, VT), N0);
1395 // If we know the sign bits of both operands are zero, strength reduce to a
1396 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1397 if (!VT.isVector()) {
1398 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1399 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1402 // fold (sdiv X, pow2) -> simple ops after legalize
1403 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1404 (isPowerOf2_64(N1C->getSExtValue()) ||
1405 isPowerOf2_64(-N1C->getSExtValue()))) {
1406 // If dividing by powers of two is cheap, then don't perform the following
1408 if (TLI.isPow2DivCheap())
1411 int64_t pow2 = N1C->getSExtValue();
1412 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1413 unsigned lg2 = Log2_64(abs2);
1415 // Splat the sign bit into the register
1416 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1417 DAG.getConstant(VT.getSizeInBits()-1,
1418 getShiftAmountTy()));
1419 AddToWorkList(SGN.getNode());
1421 // Add (N0 < 0) ? abs2 - 1 : 0;
1422 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1423 DAG.getConstant(VT.getSizeInBits() - lg2,
1424 getShiftAmountTy()));
1425 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1426 AddToWorkList(SRL.getNode());
1427 AddToWorkList(ADD.getNode()); // Divide by pow2
1428 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1429 DAG.getConstant(lg2, getShiftAmountTy()));
1431 // If we're dividing by a positive value, we're done. Otherwise, we must
1432 // negate the result.
1436 AddToWorkList(SRA.getNode());
1437 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1438 DAG.getConstant(0, VT), SRA);
1441 // if integer divide is expensive and we satisfy the requirements, emit an
1442 // alternate sequence.
1443 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1444 !TLI.isIntDivCheap()) {
1445 SDValue Op = BuildSDIV(N);
1446 if (Op.getNode()) return Op;
1450 if (N0.getOpcode() == ISD::UNDEF)
1451 return DAG.getConstant(0, VT);
1452 // X / undef -> undef
1453 if (N1.getOpcode() == ISD::UNDEF)
1459 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1460 SDValue N0 = N->getOperand(0);
1461 SDValue N1 = N->getOperand(1);
1462 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1463 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1464 MVT VT = N->getValueType(0);
1467 if (VT.isVector()) {
1468 SDValue FoldedVOp = SimplifyVBinOp(N);
1469 if (FoldedVOp.getNode()) return FoldedVOp;
1472 // fold (udiv c1, c2) -> c1/c2
1473 if (N0C && N1C && !N1C->isNullValue())
1474 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1475 // fold (udiv x, (1 << c)) -> x >>u c
1476 if (N1C && N1C->getAPIntValue().isPowerOf2())
1477 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1478 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1479 getShiftAmountTy()));
1480 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1481 if (N1.getOpcode() == ISD::SHL) {
1482 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1483 if (SHC->getAPIntValue().isPowerOf2()) {
1484 MVT ADDVT = N1.getOperand(1).getValueType();
1485 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1487 DAG.getConstant(SHC->getAPIntValue()
1490 AddToWorkList(Add.getNode());
1491 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1495 // fold (udiv x, c) -> alternate
1496 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1497 SDValue Op = BuildUDIV(N);
1498 if (Op.getNode()) return Op;
1502 if (N0.getOpcode() == ISD::UNDEF)
1503 return DAG.getConstant(0, VT);
1504 // X / undef -> undef
1505 if (N1.getOpcode() == ISD::UNDEF)
1511 SDValue DAGCombiner::visitSREM(SDNode *N) {
1512 SDValue N0 = N->getOperand(0);
1513 SDValue N1 = N->getOperand(1);
1514 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1515 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1516 MVT VT = N->getValueType(0);
1518 // fold (srem c1, c2) -> c1%c2
1519 if (N0C && N1C && !N1C->isNullValue())
1520 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1521 // If we know the sign bits of both operands are zero, strength reduce to a
1522 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1523 if (!VT.isVector()) {
1524 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1525 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1528 // If X/C can be simplified by the division-by-constant logic, lower
1529 // X%C to the equivalent of X-X/C*C.
1530 if (N1C && !N1C->isNullValue()) {
1531 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1532 AddToWorkList(Div.getNode());
1533 SDValue OptimizedDiv = combine(Div.getNode());
1534 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1535 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1537 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1538 AddToWorkList(Mul.getNode());
1544 if (N0.getOpcode() == ISD::UNDEF)
1545 return DAG.getConstant(0, VT);
1546 // X % undef -> undef
1547 if (N1.getOpcode() == ISD::UNDEF)
1553 SDValue DAGCombiner::visitUREM(SDNode *N) {
1554 SDValue N0 = N->getOperand(0);
1555 SDValue N1 = N->getOperand(1);
1556 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1557 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1558 MVT VT = N->getValueType(0);
1560 // fold (urem c1, c2) -> c1%c2
1561 if (N0C && N1C && !N1C->isNullValue())
1562 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1563 // fold (urem x, pow2) -> (and x, pow2-1)
1564 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1565 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1566 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1567 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1568 if (N1.getOpcode() == ISD::SHL) {
1569 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1570 if (SHC->getAPIntValue().isPowerOf2()) {
1572 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1573 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1575 AddToWorkList(Add.getNode());
1576 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1581 // If X/C can be simplified by the division-by-constant logic, lower
1582 // X%C to the equivalent of X-X/C*C.
1583 if (N1C && !N1C->isNullValue()) {
1584 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1585 AddToWorkList(Div.getNode());
1586 SDValue OptimizedDiv = combine(Div.getNode());
1587 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1588 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1590 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1591 AddToWorkList(Mul.getNode());
1597 if (N0.getOpcode() == ISD::UNDEF)
1598 return DAG.getConstant(0, VT);
1599 // X % undef -> undef
1600 if (N1.getOpcode() == ISD::UNDEF)
1606 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1607 SDValue N0 = N->getOperand(0);
1608 SDValue N1 = N->getOperand(1);
1609 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1610 MVT VT = N->getValueType(0);
1612 // fold (mulhs x, 0) -> 0
1613 if (N1C && N1C->isNullValue())
1615 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1616 if (N1C && N1C->getAPIntValue() == 1)
1617 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1618 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1619 getShiftAmountTy()));
1620 // fold (mulhs x, undef) -> 0
1621 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1622 return DAG.getConstant(0, VT);
1627 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1628 SDValue N0 = N->getOperand(0);
1629 SDValue N1 = N->getOperand(1);
1630 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1631 MVT VT = N->getValueType(0);
1633 // fold (mulhu x, 0) -> 0
1634 if (N1C && N1C->isNullValue())
1636 // fold (mulhu x, 1) -> 0
1637 if (N1C && N1C->getAPIntValue() == 1)
1638 return DAG.getConstant(0, N0.getValueType());
1639 // fold (mulhu x, undef) -> 0
1640 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1641 return DAG.getConstant(0, VT);
1646 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1647 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1648 /// that are being performed. Return true if a simplification was made.
1650 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1652 // If the high half is not needed, just compute the low half.
1653 bool HiExists = N->hasAnyUseOfValue(1);
1655 (!LegalOperations ||
1656 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1657 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1658 N->op_begin(), N->getNumOperands());
1659 return CombineTo(N, Res, Res);
1662 // If the low half is not needed, just compute the high half.
1663 bool LoExists = N->hasAnyUseOfValue(0);
1665 (!LegalOperations ||
1666 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1667 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1668 N->op_begin(), N->getNumOperands());
1669 return CombineTo(N, Res, Res);
1672 // If both halves are used, return as it is.
1673 if (LoExists && HiExists)
1676 // If the two computed results can be simplified separately, separate them.
1678 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1679 N->op_begin(), N->getNumOperands());
1680 AddToWorkList(Lo.getNode());
1681 SDValue LoOpt = combine(Lo.getNode());
1682 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1683 (!LegalOperations ||
1684 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1685 return CombineTo(N, LoOpt, LoOpt);
1689 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1690 N->op_begin(), N->getNumOperands());
1691 AddToWorkList(Hi.getNode());
1692 SDValue HiOpt = combine(Hi.getNode());
1693 if (HiOpt.getNode() && HiOpt != Hi &&
1694 (!LegalOperations ||
1695 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1696 return CombineTo(N, HiOpt, HiOpt);
1702 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1703 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1704 if (Res.getNode()) return Res;
1709 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1710 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1711 if (Res.getNode()) return Res;
1716 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
1717 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1718 if (Res.getNode()) return Res;
1723 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
1724 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1725 if (Res.getNode()) return Res;
1730 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1731 /// two operands of the same opcode, try to simplify it.
1732 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1733 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1734 MVT VT = N0.getValueType();
1735 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1737 // For each of OP in AND/OR/XOR:
1738 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1739 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1740 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1741 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1742 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1743 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1744 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1745 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1746 N0.getOperand(0).getValueType(),
1747 N0.getOperand(0), N1.getOperand(0));
1748 AddToWorkList(ORNode.getNode());
1749 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
1752 // For each of OP in SHL/SRL/SRA/AND...
1753 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1754 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1755 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1756 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1757 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1758 N0.getOperand(1) == N1.getOperand(1)) {
1759 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1760 N0.getOperand(0).getValueType(),
1761 N0.getOperand(0), N1.getOperand(0));
1762 AddToWorkList(ORNode.getNode());
1763 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
1764 ORNode, N0.getOperand(1));
1770 SDValue DAGCombiner::visitAND(SDNode *N) {
1771 SDValue N0 = N->getOperand(0);
1772 SDValue N1 = N->getOperand(1);
1773 SDValue LL, LR, RL, RR, CC0, CC1;
1774 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1775 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1776 MVT VT = N1.getValueType();
1777 unsigned BitWidth = VT.getSizeInBits();
1780 if (VT.isVector()) {
1781 SDValue FoldedVOp = SimplifyVBinOp(N);
1782 if (FoldedVOp.getNode()) return FoldedVOp;
1785 // fold (and x, undef) -> 0
1786 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1787 return DAG.getConstant(0, VT);
1788 // fold (and c1, c2) -> c1&c2
1790 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
1791 // canonicalize constant to RHS
1793 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
1794 // fold (and x, -1) -> x
1795 if (N1C && N1C->isAllOnesValue())
1797 // if (and x, c) is known to be zero, return 0
1798 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
1799 APInt::getAllOnesValue(BitWidth)))
1800 return DAG.getConstant(0, VT);
1802 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
1803 if (RAND.getNode() != 0)
1805 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1806 if (N1C && N0.getOpcode() == ISD::OR)
1807 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1808 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
1810 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1811 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1812 SDValue N0Op0 = N0.getOperand(0);
1813 APInt Mask = ~N1C->getAPIntValue();
1814 Mask.trunc(N0Op0.getValueSizeInBits());
1815 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
1816 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
1817 N0.getValueType(), N0Op0);
1819 // Replace uses of the AND with uses of the Zero extend node.
1822 // We actually want to replace all uses of the any_extend with the
1823 // zero_extend, to avoid duplicating things. This will later cause this
1824 // AND to be folded.
1825 CombineTo(N0.getNode(), Zext);
1826 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1829 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1830 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1831 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1832 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1834 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1835 LL.getValueType().isInteger()) {
1836 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
1837 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
1838 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1839 LR.getValueType(), LL, RL);
1840 AddToWorkList(ORNode.getNode());
1841 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1843 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
1844 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1845 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
1846 LR.getValueType(), LL, RL);
1847 AddToWorkList(ANDNode.getNode());
1848 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1850 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
1851 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1852 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1853 LR.getValueType(), LL, RL);
1854 AddToWorkList(ORNode.getNode());
1855 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1858 // canonicalize equivalent to ll == rl
1859 if (LL == RR && LR == RL) {
1860 Op1 = ISD::getSetCCSwappedOperands(Op1);
1863 if (LL == RL && LR == RR) {
1864 bool isInteger = LL.getValueType().isInteger();
1865 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1866 if (Result != ISD::SETCC_INVALID &&
1867 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
1868 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
1873 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
1874 if (N0.getOpcode() == N1.getOpcode()) {
1875 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1876 if (Tmp.getNode()) return Tmp;
1879 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1880 // fold (and (sra)) -> (and (srl)) when possible.
1881 if (!VT.isVector() &&
1882 SimplifyDemandedBits(SDValue(N, 0)))
1883 return SDValue(N, 0);
1884 // fold (zext_inreg (extload x)) -> (zextload x)
1885 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
1886 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1887 MVT EVT = LN0->getMemoryVT();
1888 // If we zero all the possible extended bits, then we can turn this into
1889 // a zextload if we are running before legalize or the operation is legal.
1890 unsigned BitWidth = N1.getValueSizeInBits();
1891 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1892 BitWidth - EVT.getSizeInBits())) &&
1893 ((!LegalOperations && !LN0->isVolatile()) ||
1894 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1895 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1896 LN0->getChain(), LN0->getBasePtr(),
1898 LN0->getSrcValueOffset(), EVT,
1899 LN0->isVolatile(), LN0->getAlignment());
1901 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1902 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1905 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1906 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
1908 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1909 MVT EVT = LN0->getMemoryVT();
1910 // If we zero all the possible extended bits, then we can turn this into
1911 // a zextload if we are running before legalize or the operation is legal.
1912 unsigned BitWidth = N1.getValueSizeInBits();
1913 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1914 BitWidth - EVT.getSizeInBits())) &&
1915 ((!LegalOperations && !LN0->isVolatile()) ||
1916 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1917 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1919 LN0->getBasePtr(), LN0->getSrcValue(),
1920 LN0->getSrcValueOffset(), EVT,
1921 LN0->isVolatile(), LN0->getAlignment());
1923 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1924 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1928 // fold (and (load x), 255) -> (zextload x, i8)
1929 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1930 if (N1C && N0.getOpcode() == ISD::LOAD) {
1931 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1932 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1933 LN0->isUnindexed() && N0.hasOneUse() &&
1934 // Do not change the width of a volatile load.
1935 !LN0->isVolatile()) {
1936 MVT EVT = MVT::Other;
1937 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
1938 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
1939 EVT = MVT::getIntegerVT(ActiveBits);
1941 MVT LoadedVT = LN0->getMemoryVT();
1943 // Do not generate loads of non-round integer types since these can
1944 // be expensive (and would be wrong if the type is not byte sized).
1945 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() &&
1946 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1947 MVT PtrType = N0.getOperand(1).getValueType();
1949 // For big endian targets, we need to add an offset to the pointer to
1950 // load the correct bytes. For little endian systems, we merely need to
1951 // read fewer bytes from the same pointer.
1952 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
1953 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
1954 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1955 unsigned Alignment = LN0->getAlignment();
1956 SDValue NewPtr = LN0->getBasePtr();
1958 if (TLI.isBigEndian()) {
1959 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
1960 NewPtr, DAG.getConstant(PtrOff, PtrType));
1961 Alignment = MinAlign(Alignment, PtrOff);
1964 AddToWorkList(NewPtr.getNode());
1966 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(),
1967 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(),
1968 EVT, LN0->isVolatile(), Alignment);
1970 CombineTo(N0.getNode(), Load, Load.getValue(1));
1971 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1979 SDValue DAGCombiner::visitOR(SDNode *N) {
1980 SDValue N0 = N->getOperand(0);
1981 SDValue N1 = N->getOperand(1);
1982 SDValue LL, LR, RL, RR, CC0, CC1;
1983 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1984 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1985 MVT VT = N1.getValueType();
1988 if (VT.isVector()) {
1989 SDValue FoldedVOp = SimplifyVBinOp(N);
1990 if (FoldedVOp.getNode()) return FoldedVOp;
1993 // fold (or x, undef) -> -1
1994 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1995 return DAG.getConstant(~0ULL, VT);
1996 // fold (or c1, c2) -> c1|c2
1998 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
1999 // canonicalize constant to RHS
2001 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2002 // fold (or x, 0) -> x
2003 if (N1C && N1C->isNullValue())
2005 // fold (or x, -1) -> -1
2006 if (N1C && N1C->isAllOnesValue())
2008 // fold (or x, c) -> c iff (x & ~c) == 0
2009 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2012 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2013 if (ROR.getNode() != 0)
2015 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2016 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2017 isa<ConstantSDNode>(N0.getOperand(1))) {
2018 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2019 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2020 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2021 N0.getOperand(0), N1),
2022 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2024 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2025 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2026 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2027 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2029 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2030 LL.getValueType().isInteger()) {
2031 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2032 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2033 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2034 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2035 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2036 LR.getValueType(), LL, RL);
2037 AddToWorkList(ORNode.getNode());
2038 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2040 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2041 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2042 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2043 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2044 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2045 LR.getValueType(), LL, RL);
2046 AddToWorkList(ANDNode.getNode());
2047 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2050 // canonicalize equivalent to ll == rl
2051 if (LL == RR && LR == RL) {
2052 Op1 = ISD::getSetCCSwappedOperands(Op1);
2055 if (LL == RL && LR == RR) {
2056 bool isInteger = LL.getValueType().isInteger();
2057 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2058 if (Result != ISD::SETCC_INVALID &&
2059 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2060 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2065 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2066 if (N0.getOpcode() == N1.getOpcode()) {
2067 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2068 if (Tmp.getNode()) return Tmp;
2071 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2072 if (N0.getOpcode() == ISD::AND &&
2073 N1.getOpcode() == ISD::AND &&
2074 N0.getOperand(1).getOpcode() == ISD::Constant &&
2075 N1.getOperand(1).getOpcode() == ISD::Constant &&
2076 // Don't increase # computations.
2077 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2078 // We can only do this xform if we know that bits from X that are set in C2
2079 // but not in C1 are already zero. Likewise for Y.
2080 const APInt &LHSMask =
2081 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2082 const APInt &RHSMask =
2083 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2085 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2086 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2087 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2088 N0.getOperand(0), N1.getOperand(0));
2089 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2090 DAG.getConstant(LHSMask | RHSMask, VT));
2094 // See if this is some rotate idiom.
2095 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2096 return SDValue(Rot, 0);
2101 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2102 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2103 if (Op.getOpcode() == ISD::AND) {
2104 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2105 Mask = Op.getOperand(1);
2106 Op = Op.getOperand(0);
2112 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2120 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2121 // idioms for rotate, and if the target supports rotation instructions, generate
2123 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2124 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2125 MVT VT = LHS.getValueType();
2126 if (!TLI.isTypeLegal(VT)) return 0;
2128 // The target must have at least one rotate flavor.
2129 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2130 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2131 if (!HasROTL && !HasROTR) return 0;
2133 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2134 SDValue LHSShift; // The shift.
2135 SDValue LHSMask; // AND value if any.
2136 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2137 return 0; // Not part of a rotate.
2139 SDValue RHSShift; // The shift.
2140 SDValue RHSMask; // AND value if any.
2141 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2142 return 0; // Not part of a rotate.
2144 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2145 return 0; // Not shifting the same value.
2147 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2148 return 0; // Shifts must disagree.
2150 // Canonicalize shl to left side in a shl/srl pair.
2151 if (RHSShift.getOpcode() == ISD::SHL) {
2152 std::swap(LHS, RHS);
2153 std::swap(LHSShift, RHSShift);
2154 std::swap(LHSMask , RHSMask );
2157 unsigned OpSizeInBits = VT.getSizeInBits();
2158 SDValue LHSShiftArg = LHSShift.getOperand(0);
2159 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2160 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2162 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2163 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2164 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2165 RHSShiftAmt.getOpcode() == ISD::Constant) {
2166 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2167 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2168 if ((LShVal + RShVal) != OpSizeInBits)
2173 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2175 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2177 // If there is an AND of either shifted operand, apply it to the result.
2178 if (LHSMask.getNode() || RHSMask.getNode()) {
2179 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2181 if (LHSMask.getNode()) {
2182 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2183 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2185 if (RHSMask.getNode()) {
2186 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2187 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2190 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2193 return Rot.getNode();
2196 // If there is a mask here, and we have a variable shift, we can't be sure
2197 // that we're masking out the right stuff.
2198 if (LHSMask.getNode() || RHSMask.getNode())
2201 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2202 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2203 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2204 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2205 if (ConstantSDNode *SUBC =
2206 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2207 if (SUBC->getAPIntValue() == OpSizeInBits) {
2209 return DAG.getNode(ISD::ROTL, DL, VT,
2210 LHSShiftArg, LHSShiftAmt).getNode();
2212 return DAG.getNode(ISD::ROTR, DL, VT,
2213 LHSShiftArg, RHSShiftAmt).getNode();
2218 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2219 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2220 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2221 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2222 if (ConstantSDNode *SUBC =
2223 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2224 if (SUBC->getAPIntValue() == OpSizeInBits) {
2226 return DAG.getNode(ISD::ROTR, DL, VT,
2227 LHSShiftArg, RHSShiftAmt).getNode();
2229 return DAG.getNode(ISD::ROTL, DL, VT,
2230 LHSShiftArg, LHSShiftAmt).getNode();
2235 // Look for sign/zext/any-extended or truncate cases:
2236 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2237 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2238 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2239 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2240 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2241 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2242 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2243 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2244 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2245 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2246 if (RExtOp0.getOpcode() == ISD::SUB &&
2247 RExtOp0.getOperand(1) == LExtOp0) {
2248 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2250 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2251 // (rotr x, (sub 32, y))
2252 if (ConstantSDNode *SUBC =
2253 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2254 if (SUBC->getAPIntValue() == OpSizeInBits) {
2255 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2257 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2260 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2261 RExtOp0 == LExtOp0.getOperand(1)) {
2262 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2264 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2265 // (rotl x, (sub 32, y))
2266 if (ConstantSDNode *SUBC =
2267 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2268 if (SUBC->getAPIntValue() == OpSizeInBits) {
2269 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2271 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2280 SDValue DAGCombiner::visitXOR(SDNode *N) {
2281 SDValue N0 = N->getOperand(0);
2282 SDValue N1 = N->getOperand(1);
2283 SDValue LHS, RHS, CC;
2284 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2285 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2286 MVT VT = N0.getValueType();
2289 if (VT.isVector()) {
2290 SDValue FoldedVOp = SimplifyVBinOp(N);
2291 if (FoldedVOp.getNode()) return FoldedVOp;
2294 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2295 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2296 return DAG.getConstant(0, VT);
2297 // fold (xor x, undef) -> undef
2298 if (N0.getOpcode() == ISD::UNDEF)
2300 if (N1.getOpcode() == ISD::UNDEF)
2302 // fold (xor c1, c2) -> c1^c2
2304 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2305 // canonicalize constant to RHS
2307 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2308 // fold (xor x, 0) -> x
2309 if (N1C && N1C->isNullValue())
2312 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2313 if (RXOR.getNode() != 0)
2316 // fold !(x cc y) -> (x !cc y)
2317 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2318 bool isInt = LHS.getValueType().isInteger();
2319 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2322 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2323 switch (N0.getOpcode()) {
2325 assert(0 && "Unhandled SetCC Equivalent!");
2328 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2329 case ISD::SELECT_CC:
2330 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2331 N0.getOperand(3), NotCC);
2336 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2337 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2338 N0.getNode()->hasOneUse() &&
2339 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2340 SDValue V = N0.getOperand(0);
2341 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2342 DAG.getConstant(1, V.getValueType()));
2343 AddToWorkList(V.getNode());
2344 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2347 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2348 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2349 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2350 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2351 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2352 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2353 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2354 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2355 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2356 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2359 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2360 if (N1C && N1C->isAllOnesValue() &&
2361 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2362 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2363 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2364 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2365 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2366 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2367 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2368 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2371 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2372 if (N1C && N0.getOpcode() == ISD::XOR) {
2373 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2374 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2376 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2377 DAG.getConstant(N1C->getAPIntValue() ^
2378 N00C->getAPIntValue(), VT));
2380 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2381 DAG.getConstant(N1C->getAPIntValue() ^
2382 N01C->getAPIntValue(), VT));
2384 // fold (xor x, x) -> 0
2386 if (!VT.isVector()) {
2387 return DAG.getConstant(0, VT);
2388 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2389 // Produce a vector of zeros.
2390 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2391 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2392 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2393 &Ops[0], Ops.size());
2397 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2398 if (N0.getOpcode() == N1.getOpcode()) {
2399 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2400 if (Tmp.getNode()) return Tmp;
2403 // Simplify the expression using non-local knowledge.
2404 if (!VT.isVector() &&
2405 SimplifyDemandedBits(SDValue(N, 0)))
2406 return SDValue(N, 0);
2411 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2412 /// the shift amount is a constant.
2413 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2414 SDNode *LHS = N->getOperand(0).getNode();
2415 if (!LHS->hasOneUse()) return SDValue();
2417 // We want to pull some binops through shifts, so that we have (and (shift))
2418 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2419 // thing happens with address calculations, so it's important to canonicalize
2421 bool HighBitSet = false; // Can we transform this if the high bit is set?
2423 switch (LHS->getOpcode()) {
2424 default: return SDValue();
2427 HighBitSet = false; // We can only transform sra if the high bit is clear.
2430 HighBitSet = true; // We can only transform sra if the high bit is set.
2433 if (N->getOpcode() != ISD::SHL)
2434 return SDValue(); // only shl(add) not sr[al](add).
2435 HighBitSet = false; // We can only transform sra if the high bit is clear.
2439 // We require the RHS of the binop to be a constant as well.
2440 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2441 if (!BinOpCst) return SDValue();
2443 // FIXME: disable this unless the input to the binop is a shift by a constant.
2444 // If it is not a shift, it pessimizes some common cases like:
2446 // void foo(int *X, int i) { X[i & 1235] = 1; }
2447 // int bar(int *X, int i) { return X[i & 255]; }
2448 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2449 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2450 BinOpLHSVal->getOpcode() != ISD::SRA &&
2451 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2452 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2455 MVT VT = N->getValueType(0);
2457 // If this is a signed shift right, and the high bit is modified by the
2458 // logical operation, do not perform the transformation. The highBitSet
2459 // boolean indicates the value of the high bit of the constant which would
2460 // cause it to be modified for this operation.
2461 if (N->getOpcode() == ISD::SRA) {
2462 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2463 if (BinOpRHSSignSet != HighBitSet)
2467 // Fold the constants, shifting the binop RHS by the shift amount.
2468 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2470 LHS->getOperand(1), N->getOperand(1));
2472 // Create the new shift.
2473 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2474 VT, LHS->getOperand(0), N->getOperand(1));
2476 // Create the new binop.
2477 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2480 SDValue DAGCombiner::visitSHL(SDNode *N) {
2481 SDValue N0 = N->getOperand(0);
2482 SDValue N1 = N->getOperand(1);
2483 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2484 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2485 MVT VT = N0.getValueType();
2486 unsigned OpSizeInBits = VT.getSizeInBits();
2488 // fold (shl c1, c2) -> c1<<c2
2490 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2491 // fold (shl 0, x) -> 0
2492 if (N0C && N0C->isNullValue())
2494 // fold (shl x, c >= size(x)) -> undef
2495 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2496 return DAG.getUNDEF(VT);
2497 // fold (shl x, 0) -> x
2498 if (N1C && N1C->isNullValue())
2500 // if (shl x, c) is known to be zero, return 0
2501 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2502 APInt::getAllOnesValue(VT.getSizeInBits())))
2503 return DAG.getConstant(0, VT);
2504 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2505 if (N1.getOpcode() == ISD::TRUNCATE &&
2506 N1.getOperand(0).getOpcode() == ISD::AND &&
2507 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2508 SDValue N101 = N1.getOperand(0).getOperand(1);
2509 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2510 MVT TruncVT = N1.getValueType();
2511 SDValue N100 = N1.getOperand(0).getOperand(0);
2512 APInt TruncC = N101C->getAPIntValue();
2513 TruncC.trunc(TruncVT.getSizeInBits());
2514 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2515 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2516 DAG.getNode(ISD::TRUNCATE,
2519 DAG.getConstant(TruncC, TruncVT)));
2523 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2524 return SDValue(N, 0);
2526 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2527 if (N1C && N0.getOpcode() == ISD::SHL &&
2528 N0.getOperand(1).getOpcode() == ISD::Constant) {
2529 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2530 uint64_t c2 = N1C->getZExtValue();
2531 if (c1 + c2 > OpSizeInBits)
2532 return DAG.getConstant(0, VT);
2533 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2534 DAG.getConstant(c1 + c2, N1.getValueType()));
2536 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2537 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2538 if (N1C && N0.getOpcode() == ISD::SRL &&
2539 N0.getOperand(1).getOpcode() == ISD::Constant) {
2540 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2541 uint64_t c2 = N1C->getZExtValue();
2542 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0),
2543 DAG.getConstant(~0ULL << c1, VT));
2545 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2546 DAG.getConstant(c2-c1, N1.getValueType()));
2548 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2549 DAG.getConstant(c1-c2, N1.getValueType()));
2551 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2552 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2553 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2554 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT));
2556 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2559 SDValue DAGCombiner::visitSRA(SDNode *N) {
2560 SDValue N0 = N->getOperand(0);
2561 SDValue N1 = N->getOperand(1);
2562 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2563 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2564 MVT VT = N0.getValueType();
2566 // fold (sra c1, c2) -> (sra c1, c2)
2568 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2569 // fold (sra 0, x) -> 0
2570 if (N0C && N0C->isNullValue())
2572 // fold (sra -1, x) -> -1
2573 if (N0C && N0C->isAllOnesValue())
2575 // fold (sra x, (setge c, size(x))) -> undef
2576 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits())
2577 return DAG.getUNDEF(VT);
2578 // fold (sra x, 0) -> x
2579 if (N1C && N1C->isNullValue())
2581 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2583 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2584 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
2585 MVT EVT = MVT::getIntegerVT(LowBits);
2586 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
2587 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2588 N0.getOperand(0), DAG.getValueType(EVT));
2591 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2592 if (N1C && N0.getOpcode() == ISD::SRA) {
2593 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2594 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2595 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
2596 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2597 DAG.getConstant(Sum, N1C->getValueType(0)));
2601 // fold (sra (shl X, m), (sub result_size, n))
2602 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2603 // result_size - n != m.
2604 // If truncate is free for the target sext(shl) is likely to result in better
2606 if (N0.getOpcode() == ISD::SHL) {
2607 // Get the two constanst of the shifts, CN0 = m, CN = n.
2608 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2610 // Determine what the truncate's result bitsize and type would be.
2611 unsigned VTValSize = VT.getSizeInBits();
2613 MVT::getIntegerVT(VTValSize - N1C->getZExtValue());
2614 // Determine the residual right-shift amount.
2615 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2617 // If the shift is not a no-op (in which case this should be just a sign
2618 // extend already), the truncated to type is legal, sign_extend is legal
2619 // on that type, and the the truncate to that type is both legal and free,
2620 // perform the transform.
2622 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2623 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
2624 TLI.isTruncateFree(VT, TruncVT)) {
2626 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
2627 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
2628 N0.getOperand(0), Amt);
2629 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
2631 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
2632 N->getValueType(0), Trunc);
2637 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
2638 if (N1.getOpcode() == ISD::TRUNCATE &&
2639 N1.getOperand(0).getOpcode() == ISD::AND &&
2640 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2641 SDValue N101 = N1.getOperand(0).getOperand(1);
2642 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2643 MVT TruncVT = N1.getValueType();
2644 SDValue N100 = N1.getOperand(0).getOperand(0);
2645 APInt TruncC = N101C->getAPIntValue();
2646 TruncC.trunc(TruncVT.getSizeInBits());
2647 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
2648 DAG.getNode(ISD::AND, N->getDebugLoc(),
2650 DAG.getNode(ISD::TRUNCATE,
2653 DAG.getConstant(TruncC, TruncVT)));
2657 // Simplify, based on bits shifted out of the LHS.
2658 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2659 return SDValue(N, 0);
2662 // If the sign bit is known to be zero, switch this to a SRL.
2663 if (DAG.SignBitIsZero(N0))
2664 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
2666 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2669 SDValue DAGCombiner::visitSRL(SDNode *N) {
2670 SDValue N0 = N->getOperand(0);
2671 SDValue N1 = N->getOperand(1);
2672 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2673 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2674 MVT VT = N0.getValueType();
2675 unsigned OpSizeInBits = VT.getSizeInBits();
2677 // fold (srl c1, c2) -> c1 >>u c2
2679 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
2680 // fold (srl 0, x) -> 0
2681 if (N0C && N0C->isNullValue())
2683 // fold (srl x, c >= size(x)) -> undef
2684 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2685 return DAG.getUNDEF(VT);
2686 // fold (srl x, 0) -> x
2687 if (N1C && N1C->isNullValue())
2689 // if (srl x, c) is known to be zero, return 0
2690 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2691 APInt::getAllOnesValue(OpSizeInBits)))
2692 return DAG.getConstant(0, VT);
2694 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
2695 if (N1C && N0.getOpcode() == ISD::SRL &&
2696 N0.getOperand(1).getOpcode() == ISD::Constant) {
2697 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2698 uint64_t c2 = N1C->getZExtValue();
2699 if (c1 + c2 > OpSizeInBits)
2700 return DAG.getConstant(0, VT);
2701 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
2702 DAG.getConstant(c1 + c2, N1.getValueType()));
2705 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2706 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2707 // Shifting in all undef bits?
2708 MVT SmallVT = N0.getOperand(0).getValueType();
2709 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
2710 return DAG.getUNDEF(VT);
2712 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
2713 N0.getOperand(0), N1);
2714 AddToWorkList(SmallShift.getNode());
2715 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
2718 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2719 // bit, which is unmodified by sra.
2720 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
2721 if (N0.getOpcode() == ISD::SRA)
2722 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
2725 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2726 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2727 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
2728 APInt KnownZero, KnownOne;
2729 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
2730 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2732 // If any of the input bits are KnownOne, then the input couldn't be all
2733 // zeros, thus the result of the srl will always be zero.
2734 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
2736 // If all of the bits input the to ctlz node are known to be zero, then
2737 // the result of the ctlz is "32" and the result of the shift is one.
2738 APInt UnknownBits = ~KnownZero & Mask;
2739 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2741 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2742 if ((UnknownBits & (UnknownBits - 1)) == 0) {
2743 // Okay, we know that only that the single bit specified by UnknownBits
2744 // could be set on input to the CTLZ node. If this bit is set, the SRL
2745 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2746 // to an SRL/XOR pair, which is likely to simplify more.
2747 unsigned ShAmt = UnknownBits.countTrailingZeros();
2748 SDValue Op = N0.getOperand(0);
2751 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
2752 DAG.getConstant(ShAmt, getShiftAmountTy()));
2753 AddToWorkList(Op.getNode());
2756 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
2757 Op, DAG.getConstant(1, VT));
2761 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
2762 if (N1.getOpcode() == ISD::TRUNCATE &&
2763 N1.getOperand(0).getOpcode() == ISD::AND &&
2764 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2765 SDValue N101 = N1.getOperand(0).getOperand(1);
2766 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2767 MVT TruncVT = N1.getValueType();
2768 SDValue N100 = N1.getOperand(0).getOperand(0);
2769 APInt TruncC = N101C->getAPIntValue();
2770 TruncC.trunc(TruncVT.getSizeInBits());
2771 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
2772 DAG.getNode(ISD::AND, N->getDebugLoc(),
2774 DAG.getNode(ISD::TRUNCATE,
2777 DAG.getConstant(TruncC, TruncVT)));
2781 // fold operands of srl based on knowledge that the low bits are not
2783 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2784 return SDValue(N, 0);
2786 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2789 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
2790 SDValue N0 = N->getOperand(0);
2791 MVT VT = N->getValueType(0);
2793 // fold (ctlz c1) -> c2
2794 if (isa<ConstantSDNode>(N0))
2795 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
2799 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
2800 SDValue N0 = N->getOperand(0);
2801 MVT VT = N->getValueType(0);
2803 // fold (cttz c1) -> c2
2804 if (isa<ConstantSDNode>(N0))
2805 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
2809 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
2810 SDValue N0 = N->getOperand(0);
2811 MVT VT = N->getValueType(0);
2813 // fold (ctpop c1) -> c2
2814 if (isa<ConstantSDNode>(N0))
2815 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
2819 SDValue DAGCombiner::visitSELECT(SDNode *N) {
2820 SDValue N0 = N->getOperand(0);
2821 SDValue N1 = N->getOperand(1);
2822 SDValue N2 = N->getOperand(2);
2823 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2824 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2825 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2826 MVT VT = N->getValueType(0);
2827 MVT VT0 = N0.getValueType();
2829 // fold (select C, X, X) -> X
2832 // fold (select true, X, Y) -> X
2833 if (N0C && !N0C->isNullValue())
2835 // fold (select false, X, Y) -> Y
2836 if (N0C && N0C->isNullValue())
2838 // fold (select C, 1, X) -> (or C, X)
2839 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
2840 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2841 // fold (select C, 0, 1) -> (xor C, 1)
2842 if (VT.isInteger() &&
2845 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
2846 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
2849 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
2850 N0, DAG.getConstant(1, VT0));
2851 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
2852 N0, DAG.getConstant(1, VT0));
2853 AddToWorkList(XORNode.getNode());
2855 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
2856 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
2858 // fold (select C, 0, X) -> (and (not C), X)
2859 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2860 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2861 AddToWorkList(NOTNode.getNode());
2862 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
2864 // fold (select C, X, 1) -> (or (not C), X)
2865 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
2866 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2867 AddToWorkList(NOTNode.getNode());
2868 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
2870 // fold (select C, X, 0) -> (and C, X)
2871 if (VT == MVT::i1 && N2C && N2C->isNullValue())
2872 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2873 // fold (select X, X, Y) -> (or X, Y)
2874 // fold (select X, 1, Y) -> (or X, Y)
2875 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
2876 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2877 // fold (select X, Y, X) -> (and X, Y)
2878 // fold (select X, Y, 0) -> (and X, Y)
2879 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
2880 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2882 // If we can fold this based on the true/false value, do so.
2883 if (SimplifySelectOps(N, N1, N2))
2884 return SDValue(N, 0); // Don't revisit N.
2886 // fold selects based on a setcc into other things, such as min/max/abs
2887 if (N0.getOpcode() == ISD::SETCC) {
2889 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2890 // having to say they don't support SELECT_CC on every type the DAG knows
2891 // about, since there is no way to mark an opcode illegal at all value types
2892 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other))
2893 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
2894 N0.getOperand(0), N0.getOperand(1),
2895 N1, N2, N0.getOperand(2));
2896 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
2902 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
2903 SDValue N0 = N->getOperand(0);
2904 SDValue N1 = N->getOperand(1);
2905 SDValue N2 = N->getOperand(2);
2906 SDValue N3 = N->getOperand(3);
2907 SDValue N4 = N->getOperand(4);
2908 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2910 // fold select_cc lhs, rhs, x, x, cc -> x
2914 // Determine if the condition we're dealing with is constant
2915 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
2916 N0, N1, CC, N->getDebugLoc(), false);
2917 if (SCC.getNode()) AddToWorkList(SCC.getNode());
2919 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
2920 if (!SCCC->isNullValue())
2921 return N2; // cond always true -> true val
2923 return N3; // cond always false -> false val
2926 // Fold to a simpler select_cc
2927 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
2928 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
2929 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2932 // If we can fold this based on the true/false value, do so.
2933 if (SimplifySelectOps(N, N2, N3))
2934 return SDValue(N, 0); // Don't revisit N.
2936 // fold select_cc into other things, such as min/max/abs
2937 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
2940 SDValue DAGCombiner::visitSETCC(SDNode *N) {
2941 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2942 cast<CondCodeSDNode>(N->getOperand(2))->get(),
2946 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2947 // "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
2948 // transformation. Returns true if extension are possible and the above
2949 // mentioned transformation is profitable.
2950 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
2952 SmallVector<SDNode*, 4> &ExtendNodes,
2953 const TargetLowering &TLI) {
2954 bool HasCopyToRegUses = false;
2955 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2956 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
2957 UE = N0.getNode()->use_end();
2962 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2963 if (User->getOpcode() == ISD::SETCC) {
2964 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2965 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2966 // Sign bits will be lost after a zext.
2969 for (unsigned i = 0; i != 2; ++i) {
2970 SDValue UseOp = User->getOperand(i);
2973 if (!isa<ConstantSDNode>(UseOp))
2978 ExtendNodes.push_back(User);
2980 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2981 SDValue UseOp = User->getOperand(i);
2983 // If truncate from extended type to original load type is free
2984 // on this target, then it's ok to extend a CopyToReg.
2985 if (isTruncFree && User->getOpcode() == ISD::CopyToReg)
2986 HasCopyToRegUses = true;
2994 if (HasCopyToRegUses) {
2995 bool BothLiveOut = false;
2996 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2999 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3000 SDValue UseOp = User->getOperand(i);
3001 if (UseOp.getNode() == N && UseOp.getResNo() == 0) {
3008 // Both unextended and extended values are live out. There had better be
3009 // good a reason for the transformation.
3010 return ExtendNodes.size();
3015 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3016 SDValue N0 = N->getOperand(0);
3017 MVT VT = N->getValueType(0);
3019 // fold (sext c1) -> c1
3020 if (isa<ConstantSDNode>(N0))
3021 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3023 // fold (sext (sext x)) -> (sext x)
3024 // fold (sext (aext x)) -> (sext x)
3025 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3026 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3029 if (N0.getOpcode() == ISD::TRUNCATE) {
3030 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3031 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3032 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3033 if (NarrowLoad.getNode()) {
3034 if (NarrowLoad.getNode() != N0.getNode())
3035 CombineTo(N0.getNode(), NarrowLoad);
3036 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3039 // See if the value being truncated is already sign extended. If so, just
3040 // eliminate the trunc/sext pair.
3041 SDValue Op = N0.getOperand(0);
3042 unsigned OpBits = Op.getValueType().getSizeInBits();
3043 unsigned MidBits = N0.getValueType().getSizeInBits();
3044 unsigned DestBits = VT.getSizeInBits();
3045 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3047 if (OpBits == DestBits) {
3048 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3049 // bits, it is already ready.
3050 if (NumSignBits > DestBits-MidBits)
3052 } else if (OpBits < DestBits) {
3053 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3054 // bits, just sext from i32.
3055 if (NumSignBits > OpBits-MidBits)
3056 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3058 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3059 // bits, just truncate to i32.
3060 if (NumSignBits > OpBits-MidBits)
3061 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3064 // fold (sext (truncate x)) -> (sextinreg x).
3065 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3066 N0.getValueType())) {
3067 if (Op.getValueType().bitsLT(VT))
3068 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3069 else if (Op.getValueType().bitsGT(VT))
3070 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3071 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3072 DAG.getValueType(N0.getValueType()));
3076 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3077 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3078 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3079 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3080 bool DoXform = true;
3081 SmallVector<SDNode*, 4> SetCCs;
3082 if (!N0.hasOneUse())
3083 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3085 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3086 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(),
3087 VT, LN0->getChain(),
3088 LN0->getBasePtr(), LN0->getSrcValue(),
3089 LN0->getSrcValueOffset(),
3091 LN0->isVolatile(), LN0->getAlignment());
3092 CombineTo(N, ExtLoad);
3093 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3094 N0.getValueType(), ExtLoad);
3095 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3097 // Extend SetCC uses if necessary.
3098 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3099 SDNode *SetCC = SetCCs[i];
3100 SmallVector<SDValue, 4> Ops;
3102 for (unsigned j = 0; j != 2; ++j) {
3103 SDValue SOp = SetCC->getOperand(j);
3105 Ops.push_back(ExtLoad);
3107 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3111 Ops.push_back(SetCC->getOperand(2));
3112 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3113 SetCC->getValueType(0),
3114 &Ops[0], Ops.size()));
3117 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3121 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3122 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3123 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3124 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3125 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3126 MVT EVT = LN0->getMemoryVT();
3127 if ((!LegalOperations && !LN0->isVolatile()) ||
3128 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) {
3129 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3131 LN0->getBasePtr(), LN0->getSrcValue(),
3132 LN0->getSrcValueOffset(), EVT,
3133 LN0->isVolatile(), LN0->getAlignment());
3134 CombineTo(N, ExtLoad);
3135 CombineTo(N0.getNode(),
3136 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3137 N0.getValueType(), ExtLoad),
3138 ExtLoad.getValue(1));
3139 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3143 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3144 if (N0.getOpcode() == ISD::SETCC) {
3146 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3147 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
3148 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3149 if (SCC.getNode()) return SCC;
3152 // fold (sext x) -> (zext x) if the sign bit is known zero.
3153 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3154 DAG.SignBitIsZero(N0))
3155 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3160 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3161 SDValue N0 = N->getOperand(0);
3162 MVT VT = N->getValueType(0);
3164 // fold (zext c1) -> c1
3165 if (isa<ConstantSDNode>(N0))
3166 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3167 // fold (zext (zext x)) -> (zext x)
3168 // fold (zext (aext x)) -> (zext x)
3169 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3170 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3173 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3174 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3175 if (N0.getOpcode() == ISD::TRUNCATE) {
3176 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3177 if (NarrowLoad.getNode()) {
3178 if (NarrowLoad.getNode() != N0.getNode())
3179 CombineTo(N0.getNode(), NarrowLoad);
3180 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3184 // fold (zext (truncate x)) -> (and x, mask)
3185 if (N0.getOpcode() == ISD::TRUNCATE &&
3186 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
3187 SDValue Op = N0.getOperand(0);
3188 if (Op.getValueType().bitsLT(VT)) {
3189 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3190 } else if (Op.getValueType().bitsGT(VT)) {
3191 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3193 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType());
3196 // fold (zext (and (trunc x), cst)) -> (and x, cst).
3197 if (N0.getOpcode() == ISD::AND &&
3198 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3199 N0.getOperand(1).getOpcode() == ISD::Constant) {
3200 SDValue X = N0.getOperand(0).getOperand(0);
3201 if (X.getValueType().bitsLT(VT)) {
3202 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3203 } else if (X.getValueType().bitsGT(VT)) {
3204 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3206 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3207 Mask.zext(VT.getSizeInBits());
3208 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3209 X, DAG.getConstant(Mask, VT));
3212 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3213 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3214 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3215 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3216 bool DoXform = true;
3217 SmallVector<SDNode*, 4> SetCCs;
3218 if (!N0.hasOneUse())
3219 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3221 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3222 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3224 LN0->getBasePtr(), LN0->getSrcValue(),
3225 LN0->getSrcValueOffset(),
3227 LN0->isVolatile(), LN0->getAlignment());
3228 CombineTo(N, ExtLoad);
3229 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3230 N0.getValueType(), ExtLoad);
3231 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3233 // Extend SetCC uses if necessary.
3234 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3235 SDNode *SetCC = SetCCs[i];
3236 SmallVector<SDValue, 4> Ops;
3238 for (unsigned j = 0; j != 2; ++j) {
3239 SDValue SOp = SetCC->getOperand(j);
3241 Ops.push_back(ExtLoad);
3243 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3244 N->getDebugLoc(), VT, SOp));
3247 Ops.push_back(SetCC->getOperand(2));
3248 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3249 SetCC->getValueType(0),
3250 &Ops[0], Ops.size()));
3253 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3257 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3258 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3259 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3260 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3261 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3262 MVT EVT = LN0->getMemoryVT();
3263 if ((!LegalOperations && !LN0->isVolatile()) ||
3264 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) {
3265 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3267 LN0->getBasePtr(), LN0->getSrcValue(),
3268 LN0->getSrcValueOffset(), EVT,
3269 LN0->isVolatile(), LN0->getAlignment());
3270 CombineTo(N, ExtLoad);
3271 CombineTo(N0.getNode(),
3272 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3274 ExtLoad.getValue(1));
3275 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3279 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3280 if (N0.getOpcode() == ISD::SETCC) {
3282 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3283 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3284 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3285 if (SCC.getNode()) return SCC;
3291 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3292 SDValue N0 = N->getOperand(0);
3293 MVT VT = N->getValueType(0);
3295 // fold (aext c1) -> c1
3296 if (isa<ConstantSDNode>(N0))
3297 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3298 // fold (aext (aext x)) -> (aext x)
3299 // fold (aext (zext x)) -> (zext x)
3300 // fold (aext (sext x)) -> (sext x)
3301 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3302 N0.getOpcode() == ISD::ZERO_EXTEND ||
3303 N0.getOpcode() == ISD::SIGN_EXTEND)
3304 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3306 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3307 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3308 if (N0.getOpcode() == ISD::TRUNCATE) {
3309 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3310 if (NarrowLoad.getNode()) {
3311 if (NarrowLoad.getNode() != N0.getNode())
3312 CombineTo(N0.getNode(), NarrowLoad);
3313 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3317 // fold (aext (truncate x))
3318 if (N0.getOpcode() == ISD::TRUNCATE) {
3319 SDValue TruncOp = N0.getOperand(0);
3320 if (TruncOp.getValueType() == VT)
3321 return TruncOp; // x iff x size == zext size.
3322 if (TruncOp.getValueType().bitsGT(VT))
3323 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3324 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3327 // fold (aext (and (trunc x), cst)) -> (and x, cst).
3328 if (N0.getOpcode() == ISD::AND &&
3329 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3330 N0.getOperand(1).getOpcode() == ISD::Constant) {
3331 SDValue X = N0.getOperand(0).getOperand(0);
3332 if (X.getValueType().bitsLT(VT)) {
3333 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3334 } else if (X.getValueType().bitsGT(VT)) {
3335 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3337 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3338 Mask.zext(VT.getSizeInBits());
3339 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3340 X, DAG.getConstant(Mask, VT));
3343 // fold (aext (load x)) -> (aext (truncate (extload x)))
3344 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
3345 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3346 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3347 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3348 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
3350 LN0->getBasePtr(), LN0->getSrcValue(),
3351 LN0->getSrcValueOffset(),
3353 LN0->isVolatile(), LN0->getAlignment());
3354 CombineTo(N, ExtLoad);
3355 // Redirect any chain users to the new load.
3356 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1),
3357 SDValue(ExtLoad.getNode(), 1));
3358 // If any node needs the original loaded value, recompute it.
3359 if (!LN0->use_empty())
3360 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3361 N0.getValueType(), ExtLoad),
3362 ExtLoad.getValue(1));
3363 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3366 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3367 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3368 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3369 if (N0.getOpcode() == ISD::LOAD &&
3370 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3372 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3373 MVT EVT = LN0->getMemoryVT();
3374 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
3375 VT, LN0->getChain(), LN0->getBasePtr(),
3377 LN0->getSrcValueOffset(), EVT,
3378 LN0->isVolatile(), LN0->getAlignment());
3379 CombineTo(N, ExtLoad);
3380 CombineTo(N0.getNode(),
3381 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3382 N0.getValueType(), ExtLoad),
3383 ExtLoad.getValue(1));
3384 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3387 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3388 if (N0.getOpcode() == ISD::SETCC) {
3390 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3391 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3392 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3400 /// GetDemandedBits - See if the specified operand can be simplified with the
3401 /// knowledge that only the bits specified by Mask are used. If so, return the
3402 /// simpler operand, otherwise return a null SDValue.
3403 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
3404 switch (V.getOpcode()) {
3408 // If the LHS or RHS don't contribute bits to the or, drop them.
3409 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3410 return V.getOperand(1);
3411 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3412 return V.getOperand(0);
3415 // Only look at single-use SRLs.
3416 if (!V.getNode()->hasOneUse())
3418 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3419 // See if we can recursively simplify the LHS.
3420 unsigned Amt = RHSC->getZExtValue();
3422 // Watch out for shift count overflow though.
3423 if (Amt >= Mask.getBitWidth()) break;
3424 APInt NewMask = Mask << Amt;
3425 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
3426 if (SimplifyLHS.getNode())
3427 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
3428 SimplifyLHS, V.getOperand(1));
3434 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3435 /// bits and then truncated to a narrower type and where N is a multiple
3436 /// of number of bits of the narrower type, transform it to a narrower load
3437 /// from address + N / num of bits of new type. If the result is to be
3438 /// extended, also fold the extension to form a extending load.
3439 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
3440 unsigned Opc = N->getOpcode();
3441 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3442 SDValue N0 = N->getOperand(0);
3443 MVT VT = N->getValueType(0);
3446 // This transformation isn't valid for vector loads.
3450 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3452 if (Opc == ISD::SIGN_EXTEND_INREG) {
3453 ExtType = ISD::SEXTLOAD;
3454 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3455 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))
3459 unsigned EVTBits = EVT.getSizeInBits();
3461 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3462 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3463 ShAmt = N01->getZExtValue();
3464 // Is the shift amount a multiple of size of VT?
3465 if ((ShAmt & (EVTBits-1)) == 0) {
3466 N0 = N0.getOperand(0);
3467 if (N0.getValueType().getSizeInBits() <= EVTBits)
3473 // Do not generate loads of non-round integer types since these can
3474 // be expensive (and would be wrong if the type is not byte sized).
3475 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() &&
3476 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
3477 // Do not change the width of a volatile load.
3478 !cast<LoadSDNode>(N0)->isVolatile()) {
3479 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3480 MVT PtrType = N0.getOperand(1).getValueType();
3482 // For big endian targets, we need to adjust the offset to the pointer to
3483 // load the correct bytes.
3484 if (TLI.isBigEndian()) {
3485 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
3486 unsigned EVTStoreBits = EVT.getStoreSizeInBits();
3487 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3490 uint64_t PtrOff = ShAmt / 8;
3491 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3492 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
3493 PtrType, LN0->getBasePtr(),
3494 DAG.getConstant(PtrOff, PtrType));
3495 AddToWorkList(NewPtr.getNode());
3497 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
3498 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
3499 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3500 LN0->isVolatile(), NewAlign)
3501 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
3502 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3503 EVT, LN0->isVolatile(), NewAlign);
3505 // Replace the old load's chain with the new load's chain.
3506 WorkListRemover DeadNodes(*this);
3507 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
3510 // Return the new loaded value.
3517 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3518 SDValue N0 = N->getOperand(0);
3519 SDValue N1 = N->getOperand(1);
3520 MVT VT = N->getValueType(0);
3521 MVT EVT = cast<VTSDNode>(N1)->getVT();
3522 unsigned VTBits = VT.getSizeInBits();
3523 unsigned EVTBits = EVT.getSizeInBits();
3525 // fold (sext_in_reg c1) -> c1
3526 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3527 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
3529 // If the input is already sign extended, just drop the extension.
3530 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
3533 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3534 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3535 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
3536 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3537 N0.getOperand(0), N1);
3540 // fold (sext_in_reg (sext x)) -> (sext x)
3541 // fold (sext_in_reg (aext x)) -> (sext x)
3542 // if x is small enough.
3543 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
3544 SDValue N00 = N0.getOperand(0);
3545 if (N00.getValueType().getSizeInBits() < EVTBits)
3546 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
3549 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3550 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
3551 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
3553 // fold operands of sext_in_reg based on knowledge that the top bits are not
3555 if (SimplifyDemandedBits(SDValue(N, 0)))
3556 return SDValue(N, 0);
3558 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3559 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3560 SDValue NarrowLoad = ReduceLoadWidth(N);
3561 if (NarrowLoad.getNode())
3564 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
3565 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
3566 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3567 if (N0.getOpcode() == ISD::SRL) {
3568 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3569 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) {
3570 // We can turn this into an SRA iff the input to the SRL is already sign
3572 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3573 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
3574 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
3575 N0.getOperand(0), N0.getOperand(1));
3579 // fold (sext_inreg (extload x)) -> (sextload x)
3580 if (ISD::isEXTLoad(N0.getNode()) &&
3581 ISD::isUNINDEXEDLoad(N0.getNode()) &&
3582 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3583 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3584 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3585 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3586 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3588 LN0->getBasePtr(), LN0->getSrcValue(),
3589 LN0->getSrcValueOffset(), EVT,
3590 LN0->isVolatile(), LN0->getAlignment());
3591 CombineTo(N, ExtLoad);
3592 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3593 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3595 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3596 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3598 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3599 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3600 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3601 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3602 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3604 LN0->getBasePtr(), LN0->getSrcValue(),
3605 LN0->getSrcValueOffset(), EVT,
3606 LN0->isVolatile(), LN0->getAlignment());
3607 CombineTo(N, ExtLoad);
3608 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3609 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3614 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
3615 SDValue N0 = N->getOperand(0);
3616 MVT VT = N->getValueType(0);
3619 if (N0.getValueType() == N->getValueType(0))
3621 // fold (truncate c1) -> c1
3622 if (isa<ConstantSDNode>(N0))
3623 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
3624 // fold (truncate (truncate x)) -> (truncate x)
3625 if (N0.getOpcode() == ISD::TRUNCATE)
3626 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3627 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3628 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3629 N0.getOpcode() == ISD::ANY_EXTEND) {
3630 if (N0.getOperand(0).getValueType().bitsLT(VT))
3631 // if the source is smaller than the dest, we still need an extend
3632 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
3634 else if (N0.getOperand(0).getValueType().bitsGT(VT))
3635 // if the source is larger than the dest, than we just need the truncate
3636 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3638 // if the source and dest are the same type, we can drop both the extend
3640 return N0.getOperand(0);
3643 // See if we can simplify the input to this truncate through knowledge that
3644 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3647 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3648 VT.getSizeInBits()));
3649 if (Shorter.getNode())
3650 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
3652 // fold (truncate (load x)) -> (smaller load x)
3653 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3654 return ReduceLoadWidth(N);
3657 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
3658 SDValue Elt = N->getOperand(i);
3659 if (Elt.getOpcode() != ISD::MERGE_VALUES)
3660 return Elt.getNode();
3661 return Elt.getOperand(Elt.getResNo()).getNode();
3664 /// CombineConsecutiveLoads - build_pair (load, load) -> load
3665 /// if load locations are consecutive.
3666 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
3667 assert(N->getOpcode() == ISD::BUILD_PAIR);
3669 SDNode *LD1 = getBuildPairElt(N, 0);
3670 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
3672 MVT LD1VT = LD1->getValueType(0);
3673 SDNode *LD2 = getBuildPairElt(N, 1);
3674 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3676 if (ISD::isNON_EXTLoad(LD2) &&
3678 // If both are volatile this would reduce the number of volatile loads.
3679 // If one is volatile it might be ok, but play conservative and bail out.
3680 !cast<LoadSDNode>(LD1)->isVolatile() &&
3681 !cast<LoadSDNode>(LD2)->isVolatile() &&
3682 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
3683 LoadSDNode *LD = cast<LoadSDNode>(LD1);
3684 unsigned Align = LD->getAlignment();
3685 unsigned NewAlign = TLI.getTargetData()->
3686 getABITypeAlignment(VT.getTypeForMVT());
3688 if (NewAlign <= Align &&
3689 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
3690 return DAG.getLoad(VT, N->getDebugLoc(), LD->getChain(), LD->getBasePtr(),
3691 LD->getSrcValue(), LD->getSrcValueOffset(),
3698 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3699 SDValue N0 = N->getOperand(0);
3700 MVT VT = N->getValueType(0);
3702 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3703 // Only do this before legalize, since afterward the target may be depending
3704 // on the bitconvert.
3705 // First check to see if this is all constant.
3707 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
3709 bool isSimple = true;
3710 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3711 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3712 N0.getOperand(i).getOpcode() != ISD::Constant &&
3713 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3718 MVT DestEltVT = N->getValueType(0).getVectorElementType();
3719 assert(!DestEltVT.isVector() &&
3720 "Element type of vector ValueType must not be vector!");
3722 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
3725 // If the input is a constant, let getNode fold it.
3726 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3727 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
3728 if (Res.getNode() != N) return Res;
3731 // (conv (conv x, t1), t2) -> (conv x, t2)
3732 if (N0.getOpcode() == ISD::BIT_CONVERT)
3733 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
3736 // fold (conv (load x)) -> (load (conv*)x)
3737 // If the resultant load doesn't need a higher alignment than the original!
3738 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
3739 // Do not change the width of a volatile load.
3740 !cast<LoadSDNode>(N0)->isVolatile() &&
3741 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
3742 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3743 unsigned Align = TLI.getTargetData()->
3744 getABITypeAlignment(VT.getTypeForMVT());
3745 unsigned OrigAlign = LN0->getAlignment();
3747 if (Align <= OrigAlign) {
3748 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
3750 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3751 LN0->isVolatile(), OrigAlign);
3753 CombineTo(N0.getNode(),
3754 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3755 N0.getValueType(), Load),
3761 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
3762 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
3763 // This often reduces constant pool loads.
3764 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3765 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
3766 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
3768 AddToWorkList(NewConv.getNode());
3770 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3771 if (N0.getOpcode() == ISD::FNEG)
3772 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3773 NewConv, DAG.getConstant(SignBit, VT));
3774 assert(N0.getOpcode() == ISD::FABS);
3775 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3776 NewConv, DAG.getConstant(~SignBit, VT));
3779 // fold (bitconvert (fcopysign cst, x)) ->
3780 // (or (and (bitconvert x), sign), (and cst, (not sign)))
3781 // Note that we don't handle (copysign x, cst) because this can always be
3782 // folded to an fneg or fabs.
3783 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
3784 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
3785 VT.isInteger() && !VT.isVector()) {
3786 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
3787 MVT IntXVT = MVT::getIntegerVT(OrigXWidth);
3788 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) {
3789 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3790 IntXVT, N0.getOperand(1));
3791 AddToWorkList(X.getNode());
3793 // If X has a different width than the result/lhs, sext it or truncate it.
3794 unsigned VTWidth = VT.getSizeInBits();
3795 if (OrigXWidth < VTWidth) {
3796 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
3797 AddToWorkList(X.getNode());
3798 } else if (OrigXWidth > VTWidth) {
3799 // To get the sign bit in the right place, we have to shift it right
3800 // before truncating.
3801 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
3802 X.getValueType(), X,
3803 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
3804 AddToWorkList(X.getNode());
3805 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3806 AddToWorkList(X.getNode());
3809 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3810 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
3811 X, DAG.getConstant(SignBit, VT));
3812 AddToWorkList(X.getNode());
3814 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3815 VT, N0.getOperand(0));
3816 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
3817 Cst, DAG.getConstant(~SignBit, VT));
3818 AddToWorkList(Cst.getNode());
3820 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
3824 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
3825 if (N0.getOpcode() == ISD::BUILD_PAIR) {
3826 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
3827 if (CombineLD.getNode())
3834 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
3835 MVT VT = N->getValueType(0);
3836 return CombineConsecutiveLoads(N, VT);
3839 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3840 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3841 /// destination element value type.
3842 SDValue DAGCombiner::
3843 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
3844 MVT SrcEltVT = BV->getOperand(0).getValueType();
3846 // If this is already the right type, we're done.
3847 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
3849 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
3850 unsigned DstBitSize = DstEltVT.getSizeInBits();
3852 // If this is a conversion of N elements of one type to N elements of another
3853 // type, convert each element. This handles FP<->INT cases.
3854 if (SrcBitSize == DstBitSize) {
3855 SmallVector<SDValue, 8> Ops;
3856 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3857 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
3858 DstEltVT, BV->getOperand(i)));
3859 AddToWorkList(Ops.back().getNode());
3861 MVT VT = MVT::getVectorVT(DstEltVT,
3862 BV->getValueType(0).getVectorNumElements());
3863 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3864 &Ops[0], Ops.size());
3867 // Otherwise, we're growing or shrinking the elements. To avoid having to
3868 // handle annoying details of growing/shrinking FP values, we convert them to
3870 if (SrcEltVT.isFloatingPoint()) {
3871 // Convert the input float vector to a int vector where the elements are the
3873 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3874 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
3875 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
3879 // Now we know the input is an integer vector. If the output is a FP type,
3880 // convert to integer first, then to FP of the right size.
3881 if (DstEltVT.isFloatingPoint()) {
3882 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3883 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
3884 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
3886 // Next, convert to FP elements of the same size.
3887 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3890 // Okay, we know the src/dst types are both integers of differing types.
3891 // Handling growing first.
3892 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
3893 if (SrcBitSize < DstBitSize) {
3894 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3896 SmallVector<SDValue, 8> Ops;
3897 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3898 i += NumInputsPerOutput) {
3899 bool isLE = TLI.isLittleEndian();
3900 APInt NewBits = APInt(DstBitSize, 0);
3901 bool EltIsUndef = true;
3902 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3903 // Shift the previously computed bits over.
3904 NewBits <<= SrcBitSize;
3905 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3906 if (Op.getOpcode() == ISD::UNDEF) continue;
3910 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize);
3914 Ops.push_back(DAG.getUNDEF(DstEltVT));
3916 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3919 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size());
3920 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3921 &Ops[0], Ops.size());
3924 // Finally, this must be the case where we are shrinking elements: each input
3925 // turns into multiple outputs.
3926 bool isS2V = ISD::isScalarToVector(BV);
3927 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3928 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
3929 SmallVector<SDValue, 8> Ops;
3931 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3932 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3933 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3934 Ops.push_back(DAG.getUNDEF(DstEltVT));
3938 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue();
3940 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3941 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
3942 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3943 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
3944 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
3945 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
3947 OpVal = OpVal.lshr(DstBitSize);
3950 // For big endian targets, swap the order of the pieces of each element.
3951 if (TLI.isBigEndian())
3952 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3955 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3956 &Ops[0], Ops.size());
3959 SDValue DAGCombiner::visitFADD(SDNode *N) {
3960 SDValue N0 = N->getOperand(0);
3961 SDValue N1 = N->getOperand(1);
3962 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3963 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3964 MVT VT = N->getValueType(0);
3967 if (VT.isVector()) {
3968 SDValue FoldedVOp = SimplifyVBinOp(N);
3969 if (FoldedVOp.getNode()) return FoldedVOp;
3972 // fold (fadd c1, c2) -> (fadd c1, c2)
3973 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3974 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
3975 // canonicalize constant to RHS
3976 if (N0CFP && !N1CFP)
3977 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
3978 // fold (fadd A, 0) -> A
3979 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
3981 // fold (fadd A, (fneg B)) -> (fsub A, B)
3982 if (isNegatibleForFree(N1, LegalOperations) == 2)
3983 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
3984 GetNegatedExpression(N1, DAG, LegalOperations));
3985 // fold (fadd (fneg A), B) -> (fsub B, A)
3986 if (isNegatibleForFree(N0, LegalOperations) == 2)
3987 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
3988 GetNegatedExpression(N0, DAG, LegalOperations));
3990 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3991 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3992 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3993 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
3994 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
3995 N0.getOperand(1), N1));
4000 SDValue DAGCombiner::visitFSUB(SDNode *N) {
4001 SDValue N0 = N->getOperand(0);
4002 SDValue N1 = N->getOperand(1);
4003 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4004 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4005 MVT VT = N->getValueType(0);
4008 if (VT.isVector()) {
4009 SDValue FoldedVOp = SimplifyVBinOp(N);
4010 if (FoldedVOp.getNode()) return FoldedVOp;
4013 // fold (fsub c1, c2) -> c1-c2
4014 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4015 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
4016 // fold (fsub A, 0) -> A
4017 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4019 // fold (fsub 0, B) -> -B
4020 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
4021 if (isNegatibleForFree(N1, LegalOperations))
4022 return GetNegatedExpression(N1, DAG, LegalOperations);
4023 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4024 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
4026 // fold (fsub A, (fneg B)) -> (fadd A, B)
4027 if (isNegatibleForFree(N1, LegalOperations))
4028 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
4029 GetNegatedExpression(N1, DAG, LegalOperations));
4034 SDValue DAGCombiner::visitFMUL(SDNode *N) {
4035 SDValue N0 = N->getOperand(0);
4036 SDValue N1 = N->getOperand(1);
4037 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4038 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4039 MVT VT = N->getValueType(0);
4042 if (VT.isVector()) {
4043 SDValue FoldedVOp = SimplifyVBinOp(N);
4044 if (FoldedVOp.getNode()) return FoldedVOp;
4047 // fold (fmul c1, c2) -> c1*c2
4048 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4049 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4050 // canonicalize constant to RHS
4051 if (N0CFP && !N1CFP)
4052 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4053 // fold (fmul A, 0) -> 0
4054 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4056 // fold (fmul X, 2.0) -> (fadd X, X)
4057 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4058 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4059 // fold (fmul X, (fneg 1.0)) -> (fneg X)
4060 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4061 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4062 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4064 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4065 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4066 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4067 // Both can be negated for free, check to see if at least one is cheaper
4069 if (LHSNeg == 2 || RHSNeg == 2)
4070 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4071 GetNegatedExpression(N0, DAG, LegalOperations),
4072 GetNegatedExpression(N1, DAG, LegalOperations));
4076 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4077 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4078 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4079 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4080 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4081 N0.getOperand(1), N1));
4086 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4087 SDValue N0 = N->getOperand(0);
4088 SDValue N1 = N->getOperand(1);
4089 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4090 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4091 MVT VT = N->getValueType(0);
4094 if (VT.isVector()) {
4095 SDValue FoldedVOp = SimplifyVBinOp(N);
4096 if (FoldedVOp.getNode()) return FoldedVOp;
4099 // fold (fdiv c1, c2) -> c1/c2
4100 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4101 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4104 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4105 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4106 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4107 // Both can be negated for free, check to see if at least one is cheaper
4109 if (LHSNeg == 2 || RHSNeg == 2)
4110 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4111 GetNegatedExpression(N0, DAG, LegalOperations),
4112 GetNegatedExpression(N1, DAG, LegalOperations));
4119 SDValue DAGCombiner::visitFREM(SDNode *N) {
4120 SDValue N0 = N->getOperand(0);
4121 SDValue N1 = N->getOperand(1);
4122 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4123 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4124 MVT VT = N->getValueType(0);
4126 // fold (frem c1, c2) -> fmod(c1,c2)
4127 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4128 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4133 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4134 SDValue N0 = N->getOperand(0);
4135 SDValue N1 = N->getOperand(1);
4136 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4137 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4138 MVT VT = N->getValueType(0);
4140 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4141 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4144 const APFloat& V = N1CFP->getValueAPF();
4145 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4146 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4147 if (!V.isNegative()) {
4148 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4149 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4151 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4152 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4153 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4157 // copysign(fabs(x), y) -> copysign(x, y)
4158 // copysign(fneg(x), y) -> copysign(x, y)
4159 // copysign(copysign(x,z), y) -> copysign(x, y)
4160 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4161 N0.getOpcode() == ISD::FCOPYSIGN)
4162 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4163 N0.getOperand(0), N1);
4165 // copysign(x, abs(y)) -> abs(x)
4166 if (N1.getOpcode() == ISD::FABS)
4167 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4169 // copysign(x, copysign(y,z)) -> copysign(x, z)
4170 if (N1.getOpcode() == ISD::FCOPYSIGN)
4171 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4172 N0, N1.getOperand(1));
4174 // copysign(x, fp_extend(y)) -> copysign(x, y)
4175 // copysign(x, fp_round(y)) -> copysign(x, y)
4176 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4177 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4178 N0, N1.getOperand(0));
4183 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4184 SDValue N0 = N->getOperand(0);
4185 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4186 MVT VT = N->getValueType(0);
4187 MVT OpVT = N0.getValueType();
4189 // fold (sint_to_fp c1) -> c1fp
4190 if (N0C && OpVT != MVT::ppcf128)
4191 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4193 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4194 // but UINT_TO_FP is legal on this target, try to convert.
4195 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4196 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4197 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4198 if (DAG.SignBitIsZero(N0))
4199 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4205 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4206 SDValue N0 = N->getOperand(0);
4207 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4208 MVT VT = N->getValueType(0);
4209 MVT OpVT = N0.getValueType();
4211 // fold (uint_to_fp c1) -> c1fp
4212 if (N0C && OpVT != MVT::ppcf128)
4213 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4215 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
4216 // but SINT_TO_FP is legal on this target, try to convert.
4217 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4218 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4219 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4220 if (DAG.SignBitIsZero(N0))
4221 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4227 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4228 SDValue N0 = N->getOperand(0);
4229 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4230 MVT VT = N->getValueType(0);
4232 // fold (fp_to_sint c1fp) -> c1
4234 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
4239 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4240 SDValue N0 = N->getOperand(0);
4241 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4242 MVT VT = N->getValueType(0);
4244 // fold (fp_to_uint c1fp) -> c1
4245 if (N0CFP && VT != MVT::ppcf128)
4246 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
4251 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4252 SDValue N0 = N->getOperand(0);
4253 SDValue N1 = N->getOperand(1);
4254 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4255 MVT VT = N->getValueType(0);
4257 // fold (fp_round c1fp) -> c1fp
4258 if (N0CFP && N0.getValueType() != MVT::ppcf128)
4259 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
4261 // fold (fp_round (fp_extend x)) -> x
4262 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4263 return N0.getOperand(0);
4265 // fold (fp_round (fp_round x)) -> (fp_round x)
4266 if (N0.getOpcode() == ISD::FP_ROUND) {
4267 // This is a value preserving truncation if both round's are.
4268 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4269 N0.getNode()->getConstantOperandVal(1) == 1;
4270 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
4271 DAG.getIntPtrConstant(IsTrunc));
4274 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4275 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4276 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
4277 N0.getOperand(0), N1);
4278 AddToWorkList(Tmp.getNode());
4279 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4280 Tmp, N0.getOperand(1));
4286 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4287 SDValue N0 = N->getOperand(0);
4288 MVT VT = N->getValueType(0);
4289 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4290 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4292 // fold (fp_round_inreg c1fp) -> c1fp
4293 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) {
4294 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4295 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
4301 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4302 SDValue N0 = N->getOperand(0);
4303 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4304 MVT VT = N->getValueType(0);
4306 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4307 if (N->hasOneUse() &&
4308 N->use_begin()->getOpcode() == ISD::FP_ROUND)
4311 // fold (fp_extend c1fp) -> c1fp
4312 if (N0CFP && VT != MVT::ppcf128)
4313 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
4315 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4317 if (N0.getOpcode() == ISD::FP_ROUND
4318 && N0.getNode()->getConstantOperandVal(1) == 1) {
4319 SDValue In = N0.getOperand(0);
4320 if (In.getValueType() == VT) return In;
4321 if (VT.bitsLT(In.getValueType()))
4322 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
4323 In, N0.getOperand(1));
4324 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
4327 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
4328 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
4329 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4330 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4331 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4332 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4334 LN0->getBasePtr(), LN0->getSrcValue(),
4335 LN0->getSrcValueOffset(),
4337 LN0->isVolatile(), LN0->getAlignment());
4338 CombineTo(N, ExtLoad);
4339 CombineTo(N0.getNode(),
4340 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
4341 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
4342 ExtLoad.getValue(1));
4343 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4349 SDValue DAGCombiner::visitFNEG(SDNode *N) {
4350 SDValue N0 = N->getOperand(0);
4352 if (isNegatibleForFree(N0, LegalOperations))
4353 return GetNegatedExpression(N0, DAG, LegalOperations);
4355 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
4356 // constant pool values.
4357 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4358 N0.getOperand(0).getValueType().isInteger() &&
4359 !N0.getOperand(0).getValueType().isVector()) {
4360 SDValue Int = N0.getOperand(0);
4361 MVT IntVT = Int.getValueType();
4362 if (IntVT.isInteger() && !IntVT.isVector()) {
4363 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
4364 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4365 AddToWorkList(Int.getNode());
4366 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4367 N->getValueType(0), Int);
4374 SDValue DAGCombiner::visitFABS(SDNode *N) {
4375 SDValue N0 = N->getOperand(0);
4376 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4377 MVT VT = N->getValueType(0);
4379 // fold (fabs c1) -> fabs(c1)
4380 if (N0CFP && VT != MVT::ppcf128)
4381 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4382 // fold (fabs (fabs x)) -> (fabs x)
4383 if (N0.getOpcode() == ISD::FABS)
4384 return N->getOperand(0);
4385 // fold (fabs (fneg x)) -> (fabs x)
4386 // fold (fabs (fcopysign x, y)) -> (fabs x)
4387 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
4388 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
4390 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
4391 // constant pool values.
4392 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4393 N0.getOperand(0).getValueType().isInteger() &&
4394 !N0.getOperand(0).getValueType().isVector()) {
4395 SDValue Int = N0.getOperand(0);
4396 MVT IntVT = Int.getValueType();
4397 if (IntVT.isInteger() && !IntVT.isVector()) {
4398 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
4399 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4400 AddToWorkList(Int.getNode());
4401 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4402 N->getValueType(0), Int);
4409 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
4410 SDValue Chain = N->getOperand(0);
4411 SDValue N1 = N->getOperand(1);
4412 SDValue N2 = N->getOperand(2);
4413 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4415 // never taken branch, fold to chain
4416 if (N1C && N1C->isNullValue())
4418 // unconditional branch
4419 if (N1C && N1C->getAPIntValue() == 1)
4420 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2);
4421 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
4423 if (N1.getOpcode() == ISD::SETCC &&
4424 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
4425 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4426 Chain, N1.getOperand(2),
4427 N1.getOperand(0), N1.getOperand(1), N2);
4433 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
4435 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
4436 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
4437 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
4439 // Use SimplifySetCC to simplify SETCC's.
4440 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
4441 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
4443 if (Simp.getNode()) AddToWorkList(Simp.getNode());
4445 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
4447 // fold br_cc true, dest -> br dest (unconditional branch)
4448 if (SCCC && !SCCC->isNullValue())
4449 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other,
4450 N->getOperand(0), N->getOperand(4));
4451 // fold br_cc false, dest -> unconditional fall through
4452 if (SCCC && SCCC->isNullValue())
4453 return N->getOperand(0);
4455 // fold to a simpler setcc
4456 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
4457 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4458 N->getOperand(0), Simp.getOperand(2),
4459 Simp.getOperand(0), Simp.getOperand(1),
4465 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
4466 /// pre-indexed load / store when the base pointer is an add or subtract
4467 /// and it has other uses besides the load / store. After the
4468 /// transformation, the new indexed load / store has effectively folded
4469 /// the add / subtract in and all of its other uses are redirected to the
4470 /// new load / store.
4471 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
4472 if (!LegalOperations)
4478 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4479 if (LD->isIndexed())
4481 VT = LD->getMemoryVT();
4482 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
4483 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
4485 Ptr = LD->getBasePtr();
4486 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4487 if (ST->isIndexed())
4489 VT = ST->getMemoryVT();
4490 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
4491 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
4493 Ptr = ST->getBasePtr();
4499 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
4500 // out. There is no reason to make this a preinc/predec.
4501 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
4502 Ptr.getNode()->hasOneUse())
4505 // Ask the target to do addressing mode selection.
4508 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4509 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
4511 // Don't create a indexed load / store with zero offset.
4512 if (isa<ConstantSDNode>(Offset) &&
4513 cast<ConstantSDNode>(Offset)->isNullValue())
4516 // Try turning it into a pre-indexed load / store except when:
4517 // 1) The new base ptr is a frame index.
4518 // 2) If N is a store and the new base ptr is either the same as or is a
4519 // predecessor of the value being stored.
4520 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
4521 // that would create a cycle.
4522 // 4) All uses are load / store ops that use it as old base ptr.
4524 // Check #1. Preinc'ing a frame index would require copying the stack pointer
4525 // (plus the implicit offset) to a register to preinc anyway.
4526 if (isa<FrameIndexSDNode>(BasePtr))
4531 SDValue Val = cast<StoreSDNode>(N)->getValue();
4532 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
4536 // Now check for #3 and #4.
4537 bool RealUse = false;
4538 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4539 E = Ptr.getNode()->use_end(); I != E; ++I) {
4543 if (Use->isPredecessorOf(N))
4546 if (!((Use->getOpcode() == ISD::LOAD &&
4547 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
4548 (Use->getOpcode() == ISD::STORE &&
4549 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
4558 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4559 BasePtr, Offset, AM);
4561 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4562 BasePtr, Offset, AM);
4565 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
4566 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4568 WorkListRemover DeadNodes(*this);
4570 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4572 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4575 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4579 // Finally, since the node is now dead, remove it from the graph.
4582 // Replace the uses of Ptr with uses of the updated base value.
4583 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
4585 removeFromWorkList(Ptr.getNode());
4586 DAG.DeleteNode(Ptr.getNode());
4591 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
4592 /// add / sub of the base pointer node into a post-indexed load / store.
4593 /// The transformation folded the add / subtract into the new indexed
4594 /// load / store effectively and all of its uses are redirected to the
4595 /// new load / store.
4596 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
4597 if (!LegalOperations)
4603 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4604 if (LD->isIndexed())
4606 VT = LD->getMemoryVT();
4607 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
4608 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
4610 Ptr = LD->getBasePtr();
4611 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4612 if (ST->isIndexed())
4614 VT = ST->getMemoryVT();
4615 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
4616 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
4618 Ptr = ST->getBasePtr();
4624 if (Ptr.getNode()->hasOneUse())
4627 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4628 E = Ptr.getNode()->use_end(); I != E; ++I) {
4631 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
4636 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4637 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
4639 std::swap(BasePtr, Offset);
4642 // Don't create a indexed load / store with zero offset.
4643 if (isa<ConstantSDNode>(Offset) &&
4644 cast<ConstantSDNode>(Offset)->isNullValue())
4647 // Try turning it into a post-indexed load / store except when
4648 // 1) All uses are load / store ops that use it as base ptr.
4649 // 2) Op must be independent of N, i.e. Op is neither a predecessor
4650 // nor a successor of N. Otherwise, if Op is folded that would
4654 bool TryNext = false;
4655 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
4656 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
4658 if (Use == Ptr.getNode())
4661 // If all the uses are load / store addresses, then don't do the
4663 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
4664 bool RealUse = false;
4665 for (SDNode::use_iterator III = Use->use_begin(),
4666 EEE = Use->use_end(); III != EEE; ++III) {
4667 SDNode *UseUse = *III;
4668 if (!((UseUse->getOpcode() == ISD::LOAD &&
4669 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
4670 (UseUse->getOpcode() == ISD::STORE &&
4671 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
4686 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
4687 SDValue Result = isLoad
4688 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4689 BasePtr, Offset, AM)
4690 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4691 BasePtr, Offset, AM);
4694 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4695 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4697 WorkListRemover DeadNodes(*this);
4699 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4701 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4704 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4708 // Finally, since the node is now dead, remove it from the graph.
4711 // Replace the uses of Use with uses of the updated base value.
4712 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
4713 Result.getValue(isLoad ? 1 : 0),
4715 removeFromWorkList(Op);
4725 /// InferAlignment - If we can infer some alignment information from this
4726 /// pointer, return it.
4727 static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) {
4728 // If this is a direct reference to a stack slot, use information about the
4729 // stack slot's alignment.
4730 int FrameIdx = 1 << 31;
4731 int64_t FrameOffset = 0;
4732 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) {
4733 FrameIdx = FI->getIndex();
4734 } else if (Ptr.getOpcode() == ISD::ADD &&
4735 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4736 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4737 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4738 FrameOffset = Ptr.getConstantOperandVal(1);
4741 if (FrameIdx != (1 << 31)) {
4742 // FIXME: Handle FI+CST.
4743 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
4744 if (MFI.isFixedObjectIndex(FrameIdx)) {
4745 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset;
4747 // The alignment of the frame index can be determined from its offset from
4748 // the incoming frame position. If the frame object is at offset 32 and
4749 // the stack is guaranteed to be 16-byte aligned, then we know that the
4750 // object is 16-byte aligned.
4751 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment();
4752 unsigned Align = MinAlign(ObjectOffset, StackAlign);
4754 // Finally, the frame object itself may have a known alignment. Factor
4755 // the alignment + offset into a new alignment. For example, if we know
4756 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a
4757 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte
4758 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc.
4759 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
4761 return std::max(Align, FIInfoAlign);
4768 SDValue DAGCombiner::visitLOAD(SDNode *N) {
4769 LoadSDNode *LD = cast<LoadSDNode>(N);
4770 SDValue Chain = LD->getChain();
4771 SDValue Ptr = LD->getBasePtr();
4773 // Try to infer better alignment information than the load already has.
4774 if (!Fast && LD->isUnindexed()) {
4775 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4776 if (Align > LD->getAlignment())
4777 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
4778 LD->getValueType(0),
4779 Chain, Ptr, LD->getSrcValue(),
4780 LD->getSrcValueOffset(), LD->getMemoryVT(),
4781 LD->isVolatile(), Align);
4785 // If load is not volatile and there are no uses of the loaded value (and
4786 // the updated indexed value in case of indexed loads), change uses of the
4787 // chain value into uses of the chain input (i.e. delete the dead load).
4788 if (!LD->isVolatile()) {
4789 if (N->getValueType(1) == MVT::Other) {
4791 if (N->hasNUsesOfValue(0, 0)) {
4792 // It's not safe to use the two value CombineTo variant here. e.g.
4793 // v1, chain2 = load chain1, loc
4794 // v2, chain3 = load chain2, loc
4796 // Now we replace use of chain2 with chain1. This makes the second load
4797 // isomorphic to the one we are deleting, and thus makes this load live.
4798 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4799 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG));
4801 WorkListRemover DeadNodes(*this);
4802 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
4804 if (N->use_empty()) {
4805 removeFromWorkList(N);
4809 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4813 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4814 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4815 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
4816 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4817 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
4818 DOUT << " and 2 other values\n";
4819 WorkListRemover DeadNodes(*this);
4820 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
4821 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
4822 DAG.getUNDEF(N->getValueType(1)),
4824 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
4825 removeFromWorkList(N);
4827 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4832 // If this load is directly stored, replace the load value with the stored
4834 // TODO: Handle store large -> read small portion.
4835 // TODO: Handle TRUNCSTORE/LOADEXT
4836 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
4837 !LD->isVolatile()) {
4838 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
4839 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4840 if (PrevST->getBasePtr() == Ptr &&
4841 PrevST->getValue().getValueType() == N->getValueType(0))
4842 return CombineTo(N, Chain.getOperand(1), Chain);
4847 // Walk up chain skipping non-aliasing memory nodes.
4848 SDValue BetterChain = FindBetterChain(N, Chain);
4850 // If there is a better chain.
4851 if (Chain != BetterChain) {
4854 // Replace the chain to void dependency.
4855 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4856 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
4858 LD->getSrcValue(), LD->getSrcValueOffset(),
4859 LD->isVolatile(), LD->getAlignment());
4861 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
4862 LD->getValueType(0),
4863 BetterChain, Ptr, LD->getSrcValue(),
4864 LD->getSrcValueOffset(),
4867 LD->getAlignment());
4870 // Create token factor to keep old chain connected.
4871 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
4872 MVT::Other, Chain, ReplLoad.getValue(1));
4874 // Replace uses with load result and token factor. Don't add users
4876 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4880 // Try transforming N to an indexed load.
4881 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4882 return SDValue(N, 0);
4887 SDValue DAGCombiner::visitSTORE(SDNode *N) {
4888 StoreSDNode *ST = cast<StoreSDNode>(N);
4889 SDValue Chain = ST->getChain();
4890 SDValue Value = ST->getValue();
4891 SDValue Ptr = ST->getBasePtr();
4893 // Try to infer better alignment information than the store already has.
4894 if (!Fast && ST->isUnindexed()) {
4895 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4896 if (Align > ST->getAlignment())
4897 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
4898 Ptr, ST->getSrcValue(),
4899 ST->getSrcValueOffset(), ST->getMemoryVT(),
4900 ST->isVolatile(), Align);
4904 // If this is a store of a bit convert, store the input value if the
4905 // resultant store does not need a higher alignment than the original.
4906 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
4907 ST->isUnindexed()) {
4908 unsigned OrigAlign = ST->getAlignment();
4909 MVT SVT = Value.getOperand(0).getValueType();
4910 unsigned Align = TLI.getTargetData()->
4911 getABITypeAlignment(SVT.getTypeForMVT());
4912 if (Align <= OrigAlign &&
4913 ((!LegalOperations && !ST->isVolatile()) ||
4914 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
4915 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
4916 Ptr, ST->getSrcValue(),
4917 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign);
4920 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
4921 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
4922 // NOTE: If the original store is volatile, this transform must not increase
4923 // the number of stores. For example, on x86-32 an f64 can be stored in one
4924 // processor operation but an i64 (which is not legal) requires two. So the
4925 // transform should not be done in this case.
4926 if (Value.getOpcode() != ISD::TargetConstantFP) {
4928 switch (CFP->getValueType(0).getSimpleVT()) {
4929 default: assert(0 && "Unknown FP type");
4930 case MVT::f80: // We don't do this for these yet.
4935 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
4936 !ST->isVolatile()) ||
4937 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
4938 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
4939 bitcastToAPInt().getZExtValue(), MVT::i32);
4940 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
4941 Ptr, ST->getSrcValue(),
4942 ST->getSrcValueOffset(), ST->isVolatile(),
4943 ST->getAlignment());
4947 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
4948 !ST->isVolatile()) ||
4949 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
4950 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
4951 getZExtValue(), MVT::i64);
4952 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
4953 Ptr, ST->getSrcValue(),
4954 ST->getSrcValueOffset(), ST->isVolatile(),
4955 ST->getAlignment());
4956 } else if (!ST->isVolatile() &&
4957 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
4958 // Many FP stores are not made apparent until after legalize, e.g. for
4959 // argument passing. Since this is so common, custom legalize the
4960 // 64-bit integer store into two 32-bit stores.
4961 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
4962 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
4963 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
4964 if (TLI.isBigEndian()) std::swap(Lo, Hi);
4966 int SVOffset = ST->getSrcValueOffset();
4967 unsigned Alignment = ST->getAlignment();
4968 bool isVolatile = ST->isVolatile();
4970 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
4971 Ptr, ST->getSrcValue(),
4972 ST->getSrcValueOffset(),
4973 isVolatile, ST->getAlignment());
4974 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
4975 DAG.getConstant(4, Ptr.getValueType()));
4977 Alignment = MinAlign(Alignment, 4U);
4978 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
4979 Ptr, ST->getSrcValue(),
4980 SVOffset, isVolatile, Alignment);
4981 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
4991 // Walk up chain skipping non-aliasing memory nodes.
4992 SDValue BetterChain = FindBetterChain(N, Chain);
4994 // If there is a better chain.
4995 if (Chain != BetterChain) {
4996 // Replace the chain to avoid dependency.
4998 if (ST->isTruncatingStore()) {
4999 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5000 ST->getSrcValue(),ST->getSrcValueOffset(),
5002 ST->isVolatile(), ST->getAlignment());
5004 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5005 ST->getSrcValue(), ST->getSrcValueOffset(),
5006 ST->isVolatile(), ST->getAlignment());
5009 // Create token to keep both nodes around.
5010 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5011 MVT::Other, Chain, ReplStore);
5013 // Don't add users to work list.
5014 return CombineTo(N, Token, false);
5018 // Try transforming N to an indexed store.
5019 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5020 return SDValue(N, 0);
5022 // FIXME: is there such a thing as a truncating indexed store?
5023 if (ST->isTruncatingStore() && ST->isUnindexed() &&
5024 Value.getValueType().isInteger()) {
5025 // See if we can simplify the input to this truncstore with knowledge that
5026 // only the low bits are being used. For example:
5027 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
5029 GetDemandedBits(Value,
5030 APInt::getLowBitsSet(Value.getValueSizeInBits(),
5031 ST->getMemoryVT().getSizeInBits()));
5032 AddToWorkList(Value.getNode());
5033 if (Shorter.getNode())
5034 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
5035 Ptr, ST->getSrcValue(),
5036 ST->getSrcValueOffset(), ST->getMemoryVT(),
5037 ST->isVolatile(), ST->getAlignment());
5039 // Otherwise, see if we can simplify the operation with
5040 // SimplifyDemandedBits, which only works if the value has a single use.
5041 if (SimplifyDemandedBits(Value,
5042 APInt::getLowBitsSet(
5043 Value.getValueSizeInBits(),
5044 ST->getMemoryVT().getSizeInBits())))
5045 return SDValue(N, 0);
5048 // If this is a load followed by a store to the same location, then the store
5050 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
5051 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
5052 ST->isUnindexed() && !ST->isVolatile() &&
5053 // There can't be any side effects between the load and store, such as
5055 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
5056 // The store is dead, remove it.
5061 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
5062 // truncating store. We can do this even if this is already a truncstore.
5063 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
5064 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
5065 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
5066 ST->getMemoryVT())) {
5067 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5068 Ptr, ST->getSrcValue(),
5069 ST->getSrcValueOffset(), ST->getMemoryVT(),
5070 ST->isVolatile(), ST->getAlignment());
5076 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
5077 SDValue InVec = N->getOperand(0);
5078 SDValue InVal = N->getOperand(1);
5079 SDValue EltNo = N->getOperand(2);
5081 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
5082 // vector with the inserted element.
5083 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
5084 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5085 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
5086 InVec.getNode()->op_end());
5087 if (Elt < Ops.size())
5089 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5090 InVec.getValueType(), &Ops[0], Ops.size());
5096 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
5097 // (vextract (scalar_to_vector val, 0) -> val
5098 SDValue InVec = N->getOperand(0);
5100 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR)
5101 return InVec.getOperand(0);
5103 // Perform only after legalization to ensure build_vector / vector_shuffle
5104 // optimizations have already been done.
5105 if (!LegalOperations) return SDValue();
5107 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
5108 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
5109 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
5110 SDValue EltNo = N->getOperand(1);
5112 if (isa<ConstantSDNode>(EltNo)) {
5113 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5114 bool NewLoad = false;
5115 bool BCNumEltsChanged = false;
5116 MVT VT = InVec.getValueType();
5117 MVT EVT = VT.getVectorElementType();
5120 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
5121 MVT BCVT = InVec.getOperand(0).getValueType();
5122 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
5124 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
5125 BCNumEltsChanged = true;
5126 InVec = InVec.getOperand(0);
5127 EVT = BCVT.getVectorElementType();
5131 LoadSDNode *LN0 = NULL;
5132 if (ISD::isNormalLoad(InVec.getNode())) {
5133 LN0 = cast<LoadSDNode>(InVec);
5134 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5135 InVec.getOperand(0).getValueType() == EVT &&
5136 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
5137 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
5138 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
5139 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
5141 // (load $addr+1*size)
5143 // If the bit convert changed the number of elements, it is unsafe
5144 // to examine the mask.
5145 if (BCNumEltsChanged)
5147 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2).
5148 getOperand(Elt))->getZExtValue();
5149 unsigned NumElems = InVec.getOperand(2).getNumOperands();
5150 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
5151 if (InVec.getOpcode() == ISD::BIT_CONVERT)
5152 InVec = InVec.getOperand(0);
5153 if (ISD::isNormalLoad(InVec.getNode())) {
5154 LN0 = cast<LoadSDNode>(InVec);
5155 Elt = (Idx < NumElems) ? Idx : Idx - NumElems;
5159 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
5162 unsigned Align = LN0->getAlignment();
5164 // Check the resultant load doesn't need a higher alignment than the
5167 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT());
5169 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
5175 SDValue NewPtr = LN0->getBasePtr();
5177 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
5178 MVT PtrType = NewPtr.getValueType();
5179 if (TLI.isBigEndian())
5180 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
5181 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
5182 DAG.getConstant(PtrOff, PtrType));
5185 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
5186 LN0->getSrcValue(), LN0->getSrcValueOffset(),
5187 LN0->isVolatile(), Align);
5193 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
5194 unsigned NumInScalars = N->getNumOperands();
5195 MVT VT = N->getValueType(0);
5196 unsigned NumElts = VT.getVectorNumElements();
5197 MVT EltType = VT.getVectorElementType();
5199 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
5200 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
5201 // at most two distinct vectors, turn this into a shuffle node.
5202 SDValue VecIn1, VecIn2;
5203 for (unsigned i = 0; i != NumInScalars; ++i) {
5204 // Ignore undef inputs.
5205 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5207 // If this input is something other than a EXTRACT_VECTOR_ELT with a
5208 // constant index, bail out.
5209 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5210 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
5211 VecIn1 = VecIn2 = SDValue(0, 0);
5215 // If the input vector type disagrees with the result of the build_vector,
5216 // we can't make a shuffle.
5217 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
5218 if (ExtractedFromVec.getValueType() != VT) {
5219 VecIn1 = VecIn2 = SDValue(0, 0);
5223 // Otherwise, remember this. We allow up to two distinct input vectors.
5224 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
5227 if (VecIn1.getNode() == 0) {
5228 VecIn1 = ExtractedFromVec;
5229 } else if (VecIn2.getNode() == 0) {
5230 VecIn2 = ExtractedFromVec;
5233 VecIn1 = VecIn2 = SDValue(0, 0);
5238 // If everything is good, we can make a shuffle operation.
5239 if (VecIn1.getNode()) {
5240 SmallVector<SDValue, 8> BuildVecIndices;
5241 for (unsigned i = 0; i != NumInScalars; ++i) {
5242 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
5243 BuildVecIndices.push_back(DAG.getUNDEF(TLI.getPointerTy()));
5247 SDValue Extract = N->getOperand(i);
5249 // If extracting from the first vector, just use the index directly.
5250 if (Extract.getOperand(0) == VecIn1) {
5251 BuildVecIndices.push_back(Extract.getOperand(1));
5255 // Otherwise, use InIdx + VecSize
5257 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue();
5258 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
5261 // Add count and size info.
5262 MVT IndexVT = MVT::getIntegerVT(EltType.getSizeInBits());
5263 MVT BuildVecVT = MVT::getVectorVT(IndexVT, NumElts);
5264 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes)
5267 // Return the new VECTOR_SHUFFLE node.
5270 if (VecIn2.getNode()) {
5273 // Use an undef build_vector as input for the second operand.
5274 std::vector<SDValue> UnOps(NumInScalars,
5275 DAG.getUNDEF(EltType));
5276 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
5277 &UnOps[0], UnOps.size());
5278 AddToWorkList(Ops[1].getNode());
5281 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), BuildVecVT,
5282 &BuildVecIndices[0], BuildVecIndices.size());
5283 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), VT, Ops, 3);
5289 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
5290 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
5291 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
5292 // inputs come from at most two distinct vectors, turn this into a shuffle
5295 // If we only have one input vector, we don't need to do any concatenation.
5296 if (N->getNumOperands() == 1)
5297 return N->getOperand(0);
5302 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
5303 SDValue ShufMask = N->getOperand(2);
5304 unsigned NumElts = ShufMask.getNumOperands();
5306 SDValue N0 = N->getOperand(0);
5307 SDValue N1 = N->getOperand(1);
5309 assert(N0.getValueType().getVectorNumElements() == NumElts &&
5310 "Vector shuffle must be normalized in DAG");
5312 // If the shuffle mask is an identity operation on the LHS, return the LHS.
5313 bool isIdentity = true;
5314 for (unsigned i = 0; i != NumElts; ++i) {
5315 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
5316 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) {
5321 if (isIdentity) return N->getOperand(0);
5323 // If the shuffle mask is an identity operation on the RHS, return the RHS.
5325 for (unsigned i = 0; i != NumElts; ++i) {
5326 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
5327 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() !=
5333 if (isIdentity) return N->getOperand(1);
5335 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
5337 bool isUnary = true;
5338 bool isSplat = true;
5340 unsigned BaseIdx = 0;
5341 for (unsigned i = 0; i != NumElts; ++i)
5342 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
5343 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue();
5344 int V = (Idx < NumElts) ? 0 : 1;
5358 // Normalize unary shuffle so the RHS is undef.
5359 if (isUnary && VecNum == 1)
5362 // If it is a splat, check if the argument vector is a build_vector with
5363 // all scalar elements the same.
5365 SDNode *V = N0.getNode();
5367 // If this is a bit convert that changes the element type of the vector but
5368 // not the number of vector elements, look through it. Be careful not to
5369 // look though conversions that change things like v4f32 to v2f64.
5370 if (V->getOpcode() == ISD::BIT_CONVERT) {
5371 SDValue ConvInput = V->getOperand(0);
5372 if (ConvInput.getValueType().isVector() &&
5373 ConvInput.getValueType().getVectorNumElements() == NumElts)
5374 V = ConvInput.getNode();
5377 if (V->getOpcode() == ISD::BUILD_VECTOR) {
5378 unsigned NumElems = V->getNumOperands();
5379 if (NumElems > BaseIdx) {
5381 bool AllSame = true;
5382 for (unsigned i = 0; i != NumElems; ++i) {
5383 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
5384 Base = V->getOperand(i);
5388 // Splat of <u, u, u, u>, return <u, u, u, u>
5389 if (!Base.getNode())
5391 for (unsigned i = 0; i != NumElems; ++i) {
5392 if (V->getOperand(i) != Base) {
5397 // Splat of <x, x, x, x>, return <x, x, x, x>
5404 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
5406 if (isUnary || N0 == N1) {
5407 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
5409 SmallVector<SDValue, 8> MappedOps;
5411 for (unsigned i = 0; i != NumElts; ++i) {
5412 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
5413 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() <
5415 MappedOps.push_back(ShufMask.getOperand(i));
5418 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() -
5420 MappedOps.push_back(DAG.getConstant(NewIdx,
5421 ShufMask.getOperand(i).getValueType()));
5425 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5426 ShufMask.getValueType(),
5427 &MappedOps[0], MappedOps.size());
5428 AddToWorkList(ShufMask.getNode());
5429 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
5430 N->getValueType(0), N0,
5431 DAG.getUNDEF(N->getValueType(0)),
5438 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
5439 /// an AND to a vector_shuffle with the destination vector and a zero vector.
5440 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
5441 /// vector_shuffle V, Zero, <0, 4, 2, 4>
5442 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
5443 SDValue LHS = N->getOperand(0);
5444 SDValue RHS = N->getOperand(1);
5445 if (N->getOpcode() == ISD::AND) {
5446 if (RHS.getOpcode() == ISD::BIT_CONVERT)
5447 RHS = RHS.getOperand(0);
5448 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
5449 std::vector<SDValue> IdxOps;
5450 unsigned NumOps = RHS.getNumOperands();
5451 unsigned NumElts = NumOps;
5452 for (unsigned i = 0; i != NumElts; ++i) {
5453 SDValue Elt = RHS.getOperand(i);
5454 if (!isa<ConstantSDNode>(Elt))
5456 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
5457 IdxOps.push_back(DAG.getIntPtrConstant(i));
5458 else if (cast<ConstantSDNode>(Elt)->isNullValue())
5459 IdxOps.push_back(DAG.getIntPtrConstant(NumElts));
5464 // Let's see if the target supports this vector_shuffle.
5465 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG))
5468 // Return the new VECTOR_SHUFFLE node.
5469 MVT EVT = RHS.getValueType().getVectorElementType();
5470 MVT VT = MVT::getVectorVT(EVT, NumElts);
5471 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
5472 std::vector<SDValue> Ops;
5473 LHS = DAG.getNode(ISD::BIT_CONVERT, LHS.getDebugLoc(), VT, LHS);
5475 AddToWorkList(LHS.getNode());
5476 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
5477 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5478 VT, &ZeroOps[0], ZeroOps.size()));
5479 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5480 MaskVT, &IdxOps[0], IdxOps.size()));
5481 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
5482 VT, &Ops[0], Ops.size());
5484 if (VT != N->getValueType(0))
5485 Result = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
5486 N->getValueType(0), Result);
5495 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
5496 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
5497 // After legalize, the target may be depending on adds and other
5498 // binary ops to provide legal ways to construct constants or other
5499 // things. Simplifying them may result in a loss of legality.
5500 if (LegalOperations) return SDValue();
5502 MVT VT = N->getValueType(0);
5503 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
5505 MVT EltType = VT.getVectorElementType();
5506 SDValue LHS = N->getOperand(0);
5507 SDValue RHS = N->getOperand(1);
5508 SDValue Shuffle = XformToShuffleWithZero(N);
5509 if (Shuffle.getNode()) return Shuffle;
5511 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
5513 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
5514 RHS.getOpcode() == ISD::BUILD_VECTOR) {
5515 SmallVector<SDValue, 8> Ops;
5516 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
5517 SDValue LHSOp = LHS.getOperand(i);
5518 SDValue RHSOp = RHS.getOperand(i);
5519 // If these two elements can't be folded, bail out.
5520 if ((LHSOp.getOpcode() != ISD::UNDEF &&
5521 LHSOp.getOpcode() != ISD::Constant &&
5522 LHSOp.getOpcode() != ISD::ConstantFP) ||
5523 (RHSOp.getOpcode() != ISD::UNDEF &&
5524 RHSOp.getOpcode() != ISD::Constant &&
5525 RHSOp.getOpcode() != ISD::ConstantFP))
5528 // Can't fold divide by zero.
5529 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
5530 N->getOpcode() == ISD::FDIV) {
5531 if ((RHSOp.getOpcode() == ISD::Constant &&
5532 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
5533 (RHSOp.getOpcode() == ISD::ConstantFP &&
5534 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
5538 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(),
5539 EltType, LHSOp, RHSOp));
5540 AddToWorkList(Ops.back().getNode());
5541 assert((Ops.back().getOpcode() == ISD::UNDEF ||
5542 Ops.back().getOpcode() == ISD::Constant ||
5543 Ops.back().getOpcode() == ISD::ConstantFP) &&
5544 "Scalar binop didn't fold!");
5547 if (Ops.size() == LHS.getNumOperands()) {
5548 MVT VT = LHS.getValueType();
5549 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
5550 &Ops[0], Ops.size());
5557 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
5558 SDValue N1, SDValue N2){
5559 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
5561 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
5562 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5564 // If we got a simplified select_cc node back from SimplifySelectCC, then
5565 // break it down into a new SETCC node, and a new SELECT node, and then return
5566 // the SELECT node, since we were called with a SELECT node.
5567 if (SCC.getNode()) {
5568 // Check to see if we got a select_cc back (to turn into setcc/select).
5569 // Otherwise, just return whatever node we got back, like fabs.
5570 if (SCC.getOpcode() == ISD::SELECT_CC) {
5571 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
5573 SCC.getOperand(0), SCC.getOperand(1),
5575 AddToWorkList(SETCC.getNode());
5576 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
5577 SCC.getOperand(2), SCC.getOperand(3), SETCC);
5585 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
5586 /// are the two values being selected between, see if we can simplify the
5587 /// select. Callers of this should assume that TheSelect is deleted if this
5588 /// returns true. As such, they should return the appropriate thing (e.g. the
5589 /// node) back to the top-level of the DAG combiner loop to avoid it being
5591 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
5594 // If this is a select from two identical things, try to pull the operation
5595 // through the select.
5596 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
5597 // If this is a load and the token chain is identical, replace the select
5598 // of two loads with a load through a select of the address to load from.
5599 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
5600 // constants have been dropped into the constant pool.
5601 if (LHS.getOpcode() == ISD::LOAD &&
5602 // Do not let this transformation reduce the number of volatile loads.
5603 !cast<LoadSDNode>(LHS)->isVolatile() &&
5604 !cast<LoadSDNode>(RHS)->isVolatile() &&
5605 // Token chains must be identical.
5606 LHS.getOperand(0) == RHS.getOperand(0)) {
5607 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
5608 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
5610 // If this is an EXTLOAD, the VT's must match.
5611 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
5612 // FIXME: this conflates two src values, discarding one. This is not
5613 // the right thing to do, but nothing uses srcvalues now. When they do,
5614 // turn SrcValue into a list of locations.
5616 if (TheSelect->getOpcode() == ISD::SELECT) {
5617 // Check that the condition doesn't reach either load. If so, folding
5618 // this will induce a cycle into the DAG.
5619 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5620 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) {
5621 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
5622 LLD->getBasePtr().getValueType(),
5623 TheSelect->getOperand(0), LLD->getBasePtr(),
5627 // Check that the condition doesn't reach either load. If so, folding
5628 // this will induce a cycle into the DAG.
5629 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5630 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5631 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) &&
5632 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) {
5633 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
5634 LLD->getBasePtr().getValueType(),
5635 TheSelect->getOperand(0),
5636 TheSelect->getOperand(1),
5637 LLD->getBasePtr(), RLD->getBasePtr(),
5638 TheSelect->getOperand(4));
5642 if (Addr.getNode()) {
5644 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
5645 Load = DAG.getLoad(TheSelect->getValueType(0),
5646 TheSelect->getDebugLoc(),
5648 Addr,LLD->getSrcValue(),
5649 LLD->getSrcValueOffset(),
5651 LLD->getAlignment());
5653 Load = DAG.getExtLoad(LLD->getExtensionType(),
5654 TheSelect->getDebugLoc(),
5655 TheSelect->getValueType(0),
5656 LLD->getChain(), Addr, LLD->getSrcValue(),
5657 LLD->getSrcValueOffset(),
5660 LLD->getAlignment());
5663 // Users of the select now use the result of the load.
5664 CombineTo(TheSelect, Load);
5666 // Users of the old loads now use the new load's chain. We know the
5667 // old-load value is dead now.
5668 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
5669 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
5679 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
5680 /// where 'cond' is the comparison specified by CC.
5681 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
5682 SDValue N2, SDValue N3,
5683 ISD::CondCode CC, bool NotExtCompare) {
5684 // (x ? y : y) -> y.
5685 if (N2 == N3) return N2;
5687 MVT VT = N2.getValueType();
5688 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
5689 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
5690 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
5692 // Determine if the condition we're dealing with is constant
5693 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
5694 N0, N1, CC, DL, false);
5695 if (SCC.getNode()) AddToWorkList(SCC.getNode());
5696 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
5698 // fold select_cc true, x, y -> x
5699 if (SCCC && !SCCC->isNullValue())
5701 // fold select_cc false, x, y -> y
5702 if (SCCC && SCCC->isNullValue())
5705 // Check to see if we can simplify the select into an fabs node
5706 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
5707 // Allow either -0.0 or 0.0
5708 if (CFP->getValueAPF().isZero()) {
5709 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
5710 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
5711 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
5712 N2 == N3.getOperand(0))
5713 return DAG.getNode(ISD::FABS, DL, VT, N0);
5715 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
5716 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
5717 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
5718 N2.getOperand(0) == N3)
5719 return DAG.getNode(ISD::FABS, DL, VT, N3);
5723 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
5724 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
5725 // in it. This is a win when the constant is not otherwise available because
5726 // it replaces two constant pool loads with one. We only do this if the FP
5727 // type is known to be legal, because if it isn't, then we are before legalize
5728 // types an we want the other legalization to happen first (e.g. to avoid
5729 // messing with soft float).
5730 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
5731 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
5732 if (TLI.isTypeLegal(N2.getValueType()) &&
5733 // If both constants have multiple uses, then we won't need to do an
5734 // extra load, they are likely around in registers for other users.
5735 (TV->hasOneUse() || FV->hasOneUse())) {
5736 Constant *Elts[] = {
5737 const_cast<ConstantFP*>(FV->getConstantFPValue()),
5738 const_cast<ConstantFP*>(TV->getConstantFPValue())
5740 // Create a ConstantArray of the two constants.
5742 ConstantArray::get(ArrayType::get(Elts[0]->getType(), 2), Elts, 2);
5743 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy());
5744 unsigned Alignment =
5745 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5747 // Get the offsets to the 0 and 1 element of the array so that we can
5748 // select between them.
5749 SDValue Zero = DAG.getIntPtrConstant(0);
5751 (unsigned)TLI.getTargetData()->getTypePaddedSize(Elts[0]->getType());
5752 SDValue One = DAG.getIntPtrConstant(EltSize);
5754 SDValue Cond = DAG.getSetCC(DL,
5755 TLI.getSetCCResultType(N0.getValueType()),
5757 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
5759 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
5761 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
5762 PseudoSourceValue::getConstantPool(), 0, false,
5768 // Check to see if we can perform the "gzip trick", transforming
5769 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
5770 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
5771 N0.getValueType().isInteger() &&
5772 N2.getValueType().isInteger() &&
5773 (N1C->isNullValue() || // (a < 0) ? b : 0
5774 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
5775 MVT XType = N0.getValueType();
5776 MVT AType = N2.getValueType();
5777 if (XType.bitsGE(AType)) {
5778 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
5779 // single-bit constant.
5780 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
5781 unsigned ShCtV = N2C->getAPIntValue().logBase2();
5782 ShCtV = XType.getSizeInBits()-ShCtV-1;
5783 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
5784 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
5786 AddToWorkList(Shift.getNode());
5788 if (XType.bitsGT(AType)) {
5789 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
5790 AddToWorkList(Shift.getNode());
5793 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
5796 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
5798 DAG.getConstant(XType.getSizeInBits()-1,
5799 getShiftAmountTy()));
5800 AddToWorkList(Shift.getNode());
5802 if (XType.bitsGT(AType)) {
5803 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
5804 AddToWorkList(Shift.getNode());
5807 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
5811 // fold select C, 16, 0 -> shl C, 4
5812 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
5813 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
5815 // If the caller doesn't want us to simplify this into a zext of a compare,
5817 if (NotExtCompare && N2C->getAPIntValue() == 1)
5820 // Get a SetCC of the condition
5821 // FIXME: Should probably make sure that setcc is legal if we ever have a
5822 // target where it isn't.
5824 // cast from setcc result type to select result type
5826 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
5828 if (N2.getValueType().bitsLT(SCC.getValueType()))
5829 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
5831 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
5832 N2.getValueType(), SCC);
5834 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
5835 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
5836 N2.getValueType(), SCC);
5839 AddToWorkList(SCC.getNode());
5840 AddToWorkList(Temp.getNode());
5842 if (N2C->getAPIntValue() == 1)
5845 // shl setcc result by log2 n2c
5846 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
5847 DAG.getConstant(N2C->getAPIntValue().logBase2(),
5848 getShiftAmountTy()));
5851 // Check to see if this is the equivalent of setcc
5852 // FIXME: Turn all of these into setcc if setcc if setcc is legal
5853 // otherwise, go ahead with the folds.
5854 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
5855 MVT XType = N0.getValueType();
5856 if (!LegalOperations ||
5857 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
5858 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
5859 if (Res.getValueType() != VT)
5860 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
5864 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
5865 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
5866 (!LegalOperations ||
5867 TLI.isOperationLegal(ISD::CTLZ, XType))) {
5868 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
5869 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
5870 DAG.getConstant(Log2_32(XType.getSizeInBits()),
5871 getShiftAmountTy()));
5873 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
5874 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
5875 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
5876 XType, DAG.getConstant(0, XType), N0);
5877 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
5878 return DAG.getNode(ISD::SRL, DL, XType,
5879 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
5880 DAG.getConstant(XType.getSizeInBits()-1,
5881 getShiftAmountTy()));
5883 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
5884 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
5885 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
5886 DAG.getConstant(XType.getSizeInBits()-1,
5887 getShiftAmountTy()));
5888 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
5892 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
5893 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5894 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
5895 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
5896 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
5897 MVT XType = N0.getValueType();
5898 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
5899 DAG.getConstant(XType.getSizeInBits()-1,
5900 getShiftAmountTy()));
5901 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
5903 AddToWorkList(Shift.getNode());
5904 AddToWorkList(Add.getNode());
5905 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
5907 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
5908 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5909 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
5910 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
5911 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
5912 MVT XType = N0.getValueType();
5913 if (SubC->isNullValue() && XType.isInteger()) {
5914 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
5916 DAG.getConstant(XType.getSizeInBits()-1,
5917 getShiftAmountTy()));
5918 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
5920 AddToWorkList(Shift.getNode());
5921 AddToWorkList(Add.getNode());
5922 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
5930 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
5931 SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0,
5932 SDValue N1, ISD::CondCode Cond,
5933 DebugLoc DL, bool foldBooleans) {
5934 TargetLowering::DAGCombinerInfo
5935 DagCombineInfo(DAG, Level == Unrestricted, false, this);
5936 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
5939 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
5940 /// return a DAG expression to select that will generate the same value by
5941 /// multiplying by a magic number. See:
5942 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5943 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
5944 std::vector<SDNode*> Built;
5945 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
5947 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5953 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
5954 /// return a DAG expression to select that will generate the same value by
5955 /// multiplying by a magic number. See:
5956 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5957 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
5958 std::vector<SDNode*> Built;
5959 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
5961 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5967 /// FindBaseOffset - Return true if base is known not to alias with anything
5968 /// but itself. Provides base object and offset as results.
5969 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
5970 // Assume it is a primitive operation.
5971 Base = Ptr; Offset = 0;
5973 // If it's an adding a simple constant then integrate the offset.
5974 if (Base.getOpcode() == ISD::ADD) {
5975 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
5976 Base = Base.getOperand(0);
5977 Offset += C->getZExtValue();
5981 // If it's any of the following then it can't alias with anything but itself.
5982 return isa<FrameIndexSDNode>(Base) ||
5983 isa<ConstantPoolSDNode>(Base) ||
5984 isa<GlobalAddressSDNode>(Base);
5987 /// isAlias - Return true if there is any possibility that the two addresses
5989 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
5990 const Value *SrcValue1, int SrcValueOffset1,
5991 SDValue Ptr2, int64_t Size2,
5992 const Value *SrcValue2, int SrcValueOffset2) const {
5993 // If they are the same then they must be aliases.
5994 if (Ptr1 == Ptr2) return true;
5996 // Gather base node and offset information.
5997 SDValue Base1, Base2;
5998 int64_t Offset1, Offset2;
5999 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
6000 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
6002 // If they have a same base address then...
6004 // Check to see if the addresses overlap.
6005 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
6007 // If we know both bases then they can't alias.
6008 if (KnownBase1 && KnownBase2) return false;
6010 if (CombinerGlobalAA) {
6011 // Use alias analysis information.
6012 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
6013 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
6014 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
6015 AliasAnalysis::AliasResult AAResult =
6016 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
6017 if (AAResult == AliasAnalysis::NoAlias)
6021 // Otherwise we have to assume they alias.
6025 /// FindAliasInfo - Extracts the relevant alias information from the memory
6026 /// node. Returns true if the operand was a load.
6027 bool DAGCombiner::FindAliasInfo(SDNode *N,
6028 SDValue &Ptr, int64_t &Size,
6029 const Value *&SrcValue, int &SrcValueOffset) const {
6030 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6031 Ptr = LD->getBasePtr();
6032 Size = LD->getMemoryVT().getSizeInBits() >> 3;
6033 SrcValue = LD->getSrcValue();
6034 SrcValueOffset = LD->getSrcValueOffset();
6036 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6037 Ptr = ST->getBasePtr();
6038 Size = ST->getMemoryVT().getSizeInBits() >> 3;
6039 SrcValue = ST->getSrcValue();
6040 SrcValueOffset = ST->getSrcValueOffset();
6042 assert(0 && "FindAliasInfo expected a memory operand");
6048 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
6049 /// looking for aliasing nodes and adding them to the Aliases vector.
6050 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
6051 SmallVector<SDValue, 8> &Aliases) {
6052 SmallVector<SDValue, 8> Chains; // List of chains to visit.
6053 std::set<SDNode *> Visited; // Visited node set.
6055 // Get alias information for node.
6058 const Value *SrcValue;
6060 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
6063 Chains.push_back(OriginalChain);
6065 // Look at each chain and determine if it is an alias. If so, add it to the
6066 // aliases list. If not, then continue up the chain looking for the next
6068 while (!Chains.empty()) {
6069 SDValue Chain = Chains.back();
6072 // Don't bother if we've been before.
6073 if (Visited.find(Chain.getNode()) != Visited.end()) continue;
6074 Visited.insert(Chain.getNode());
6076 switch (Chain.getOpcode()) {
6077 case ISD::EntryToken:
6078 // Entry token is ideal chain operand, but handled in FindBetterChain.
6083 // Get alias information for Chain.
6086 const Value *OpSrcValue;
6087 int OpSrcValueOffset;
6088 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
6089 OpSrcValue, OpSrcValueOffset);
6091 // If chain is alias then stop here.
6092 if (!(IsLoad && IsOpLoad) &&
6093 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
6094 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
6095 Aliases.push_back(Chain);
6097 // Look further up the chain.
6098 Chains.push_back(Chain.getOperand(0));
6099 // Clean up old chain.
6100 AddToWorkList(Chain.getNode());
6105 case ISD::TokenFactor:
6106 // We have to check each of the operands of the token factor, so we queue
6107 // then up. Adding the operands to the queue (stack) in reverse order
6108 // maintains the original order and increases the likelihood that getNode
6109 // will find a matching token factor (CSE.)
6110 for (unsigned n = Chain.getNumOperands(); n;)
6111 Chains.push_back(Chain.getOperand(--n));
6112 // Eliminate the token factor if we can.
6113 AddToWorkList(Chain.getNode());
6117 // For all other instructions we will just have to take what we can get.
6118 Aliases.push_back(Chain);
6124 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
6125 /// for a better chain (aliasing node.)
6126 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
6127 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
6129 // Accumulate all the aliases to this node.
6130 GatherAllAliases(N, OldChain, Aliases);
6132 if (Aliases.size() == 0) {
6133 // If no operands then chain to entry token.
6134 return DAG.getEntryNode();
6135 } else if (Aliases.size() == 1) {
6136 // If a single operand then chain to it. We don't need to revisit it.
6140 // Construct a custom tailored token factor.
6141 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6142 &Aliases[0], Aliases.size());
6144 // Make sure the old chain gets cleaned up.
6145 if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
6150 // SelectionDAG::Combine - This is the entry point for the file.
6152 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) {
6153 /// run - This is the main entry point to this class.
6155 DAGCombiner(*this, AA, Fast).Run(Level);