1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: Should add a corresponding version of fold AND with
20 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
23 // FIXME: select C, pow2, pow2 -> something smart
24 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
25 // FIXME: Dead stores -> nuke
26 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
27 // FIXME: mul (x, const) -> shifts + adds
28 // FIXME: undef values
29 // FIXME: make truncate see through SIGN_EXTEND and AND
30 // FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
31 // FIXME: verify that getNode can't return extends with an operand whose type
32 // is >= to that of the extend.
33 // FIXME: divide by zero is currently left unfolded. do we want to turn this
35 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
36 // FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use
38 //===----------------------------------------------------------------------===//
40 #define DEBUG_TYPE "dagcombine"
41 #include "llvm/ADT/Statistic.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/Support/Debug.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Target/TargetLowering.h"
52 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
59 // Worklist of all of the nodes that need to be simplified.
60 std::vector<SDNode*> WorkList;
62 /// AddUsersToWorkList - When an instruction is simplified, add all users of
63 /// the instruction to the work lists because they might get more simplified
66 void AddUsersToWorkList(SDNode *N) {
67 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
69 WorkList.push_back(*UI);
72 /// removeFromWorkList - remove all instances of N from the worklist.
73 void removeFromWorkList(SDNode *N) {
74 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
78 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
80 DEBUG(std::cerr << "\nReplacing "; N->dump();
81 std::cerr << "\nWith: "; To[0].Val->dump();
82 std::cerr << " and " << To.size()-1 << " other values\n");
83 std::vector<SDNode*> NowDead;
84 DAG.ReplaceAllUsesWith(N, To, &NowDead);
86 // Push the new nodes and any users onto the worklist
87 for (unsigned i = 0, e = To.size(); i != e; ++i) {
88 WorkList.push_back(To[i].Val);
89 AddUsersToWorkList(To[i].Val);
92 // Nodes can end up on the worklist more than once. Make sure we do
93 // not process a node that has been replaced.
94 removeFromWorkList(N);
95 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
96 removeFromWorkList(NowDead[i]);
98 // Finally, since the node is now dead, remove it from the graph.
100 return SDOperand(N, 0);
103 SDOperand CombineTo(SDNode *N, SDOperand Res) {
104 std::vector<SDOperand> To;
106 return CombineTo(N, To);
109 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
110 std::vector<SDOperand> To;
113 return CombineTo(N, To);
116 /// visit - call the node-specific routine that knows how to fold each
117 /// particular type of node.
118 SDOperand visit(SDNode *N);
120 // Visitation implementation - Implement dag node combining for different
121 // node types. The semantics are as follows:
123 // SDOperand.Val == 0 - No change was made
124 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
125 // otherwise - N should be replaced by the returned Operand.
127 SDOperand visitTokenFactor(SDNode *N);
128 SDOperand visitADD(SDNode *N);
129 SDOperand visitSUB(SDNode *N);
130 SDOperand visitMUL(SDNode *N);
131 SDOperand visitSDIV(SDNode *N);
132 SDOperand visitUDIV(SDNode *N);
133 SDOperand visitSREM(SDNode *N);
134 SDOperand visitUREM(SDNode *N);
135 SDOperand visitMULHU(SDNode *N);
136 SDOperand visitMULHS(SDNode *N);
137 SDOperand visitAND(SDNode *N);
138 SDOperand visitOR(SDNode *N);
139 SDOperand visitXOR(SDNode *N);
140 SDOperand visitSHL(SDNode *N);
141 SDOperand visitSRA(SDNode *N);
142 SDOperand visitSRL(SDNode *N);
143 SDOperand visitCTLZ(SDNode *N);
144 SDOperand visitCTTZ(SDNode *N);
145 SDOperand visitCTPOP(SDNode *N);
146 SDOperand visitSELECT(SDNode *N);
147 SDOperand visitSELECT_CC(SDNode *N);
148 SDOperand visitSETCC(SDNode *N);
149 SDOperand visitADD_PARTS(SDNode *N);
150 SDOperand visitSUB_PARTS(SDNode *N);
151 SDOperand visitSIGN_EXTEND(SDNode *N);
152 SDOperand visitZERO_EXTEND(SDNode *N);
153 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
154 SDOperand visitTRUNCATE(SDNode *N);
155 SDOperand visitBIT_CONVERT(SDNode *N);
157 SDOperand visitFADD(SDNode *N);
158 SDOperand visitFSUB(SDNode *N);
159 SDOperand visitFMUL(SDNode *N);
160 SDOperand visitFDIV(SDNode *N);
161 SDOperand visitFREM(SDNode *N);
162 SDOperand visitSINT_TO_FP(SDNode *N);
163 SDOperand visitUINT_TO_FP(SDNode *N);
164 SDOperand visitFP_TO_SINT(SDNode *N);
165 SDOperand visitFP_TO_UINT(SDNode *N);
166 SDOperand visitFP_ROUND(SDNode *N);
167 SDOperand visitFP_ROUND_INREG(SDNode *N);
168 SDOperand visitFP_EXTEND(SDNode *N);
169 SDOperand visitFNEG(SDNode *N);
170 SDOperand visitFABS(SDNode *N);
171 SDOperand visitBRCOND(SDNode *N);
172 SDOperand visitBRCONDTWOWAY(SDNode *N);
173 SDOperand visitBR_CC(SDNode *N);
174 SDOperand visitBRTWOWAY_CC(SDNode *N);
176 SDOperand visitLOAD(SDNode *N);
177 SDOperand visitSTORE(SDNode *N);
179 SDOperand visitLOCATION(SDNode *N);
180 SDOperand visitDEBUGLOC(SDNode *N);
182 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
183 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
184 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
185 SDOperand N3, ISD::CondCode CC);
186 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
187 ISD::CondCode Cond, bool foldBooleans = true);
189 SDOperand BuildSDIV(SDNode *N);
190 SDOperand BuildUDIV(SDNode *N);
192 DAGCombiner(SelectionDAG &D)
193 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
195 /// Run - runs the dag combiner on all nodes in the work list
196 void Run(bool RunningAfterLegalize);
201 int64_t m; // magic number
202 int64_t s; // shift amount
206 uint64_t m; // magic number
207 int64_t a; // add indicator
208 int64_t s; // shift amount
211 /// magic - calculate the magic numbers required to codegen an integer sdiv as
212 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
214 static ms magic32(int32_t d) {
216 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
217 const uint32_t two31 = 0x80000000U;
221 t = two31 + ((uint32_t)d >> 31);
222 anc = t - 1 - t%ad; // absolute value of nc
223 p = 31; // initialize p
224 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
225 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
226 q2 = two31/ad; // initialize q2 = 2p/abs(d)
227 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
230 q1 = 2*q1; // update q1 = 2p/abs(nc)
231 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
232 if (r1 >= anc) { // must be unsigned comparison
236 q2 = 2*q2; // update q2 = 2p/abs(d)
237 r2 = 2*r2; // update r2 = rem(2p/abs(d))
238 if (r2 >= ad) { // must be unsigned comparison
243 } while (q1 < delta || (q1 == delta && r1 == 0));
245 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
246 if (d < 0) mag.m = -mag.m; // resulting magic number
247 mag.s = p - 32; // resulting shift
251 /// magicu - calculate the magic numbers required to codegen an integer udiv as
252 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
253 static mu magicu32(uint32_t d) {
255 uint32_t nc, delta, q1, r1, q2, r2;
257 magu.a = 0; // initialize "add" indicator
259 p = 31; // initialize p
260 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
261 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
262 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
263 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
266 if (r1 >= nc - r1 ) {
267 q1 = 2*q1 + 1; // update q1
268 r1 = 2*r1 - nc; // update r1
271 q1 = 2*q1; // update q1
272 r1 = 2*r1; // update r1
274 if (r2 + 1 >= d - r2) {
275 if (q2 >= 0x7FFFFFFF) magu.a = 1;
276 q2 = 2*q2 + 1; // update q2
277 r2 = 2*r2 + 1 - d; // update r2
280 if (q2 >= 0x80000000) magu.a = 1;
281 q2 = 2*q2; // update q2
282 r2 = 2*r2 + 1; // update r2
285 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
286 magu.m = q2 + 1; // resulting magic number
287 magu.s = p - 32; // resulting shift
291 /// magic - calculate the magic numbers required to codegen an integer sdiv as
292 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
294 static ms magic64(int64_t d) {
296 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
297 const uint64_t two63 = 9223372036854775808ULL; // 2^63
300 ad = d >= 0 ? d : -d;
301 t = two63 + ((uint64_t)d >> 63);
302 anc = t - 1 - t%ad; // absolute value of nc
303 p = 63; // initialize p
304 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
305 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
306 q2 = two63/ad; // initialize q2 = 2p/abs(d)
307 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
310 q1 = 2*q1; // update q1 = 2p/abs(nc)
311 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
312 if (r1 >= anc) { // must be unsigned comparison
316 q2 = 2*q2; // update q2 = 2p/abs(d)
317 r2 = 2*r2; // update r2 = rem(2p/abs(d))
318 if (r2 >= ad) { // must be unsigned comparison
323 } while (q1 < delta || (q1 == delta && r1 == 0));
326 if (d < 0) mag.m = -mag.m; // resulting magic number
327 mag.s = p - 64; // resulting shift
331 /// magicu - calculate the magic numbers required to codegen an integer udiv as
332 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
333 static mu magicu64(uint64_t d)
336 uint64_t nc, delta, q1, r1, q2, r2;
338 magu.a = 0; // initialize "add" indicator
340 p = 63; // initialize p
341 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
342 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
343 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
344 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
347 if (r1 >= nc - r1 ) {
348 q1 = 2*q1 + 1; // update q1
349 r1 = 2*r1 - nc; // update r1
352 q1 = 2*q1; // update q1
353 r1 = 2*r1; // update r1
355 if (r2 + 1 >= d - r2) {
356 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
357 q2 = 2*q2 + 1; // update q2
358 r2 = 2*r2 + 1 - d; // update r2
361 if (q2 >= 0x8000000000000000ull) magu.a = 1;
362 q2 = 2*q2; // update q2
363 r2 = 2*r2 + 1; // update r2
366 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
367 magu.m = q2 + 1; // resulting magic number
368 magu.s = p - 64; // resulting shift
372 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
373 // that selects between the values 1 and 0, making it equivalent to a setcc.
374 // Also, set the incoming LHS, RHS, and CC references to the appropriate
375 // nodes based on the type of node we are checking. This simplifies life a
376 // bit for the callers.
377 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
379 if (N.getOpcode() == ISD::SETCC) {
380 LHS = N.getOperand(0);
381 RHS = N.getOperand(1);
382 CC = N.getOperand(2);
385 if (N.getOpcode() == ISD::SELECT_CC &&
386 N.getOperand(2).getOpcode() == ISD::Constant &&
387 N.getOperand(3).getOpcode() == ISD::Constant &&
388 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
389 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
390 LHS = N.getOperand(0);
391 RHS = N.getOperand(1);
392 CC = N.getOperand(4);
398 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
399 // one use. If this is true, it allows the users to invert the operation for
400 // free when it is profitable to do so.
401 static bool isOneUseSetCC(SDOperand N) {
402 SDOperand N0, N1, N2;
403 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
408 // FIXME: This should probably go in the ISD class rather than being duplicated
410 static bool isCommutativeBinOp(unsigned Opcode) {
416 case ISD::XOR: return true;
417 default: return false; // FIXME: Need commutative info for user ops!
421 void DAGCombiner::Run(bool RunningAfterLegalize) {
422 // set the instance variable, so that the various visit routines may use it.
423 AfterLegalize = RunningAfterLegalize;
425 // Add all the dag nodes to the worklist.
426 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
427 E = DAG.allnodes_end(); I != E; ++I)
428 WorkList.push_back(I);
430 // Create a dummy node (which is not added to allnodes), that adds a reference
431 // to the root node, preventing it from being deleted, and tracking any
432 // changes of the root.
433 HandleSDNode Dummy(DAG.getRoot());
435 // while the worklist isn't empty, inspect the node on the end of it and
436 // try and combine it.
437 while (!WorkList.empty()) {
438 SDNode *N = WorkList.back();
441 // If N has no uses, it is dead. Make sure to revisit all N's operands once
442 // N is deleted from the DAG, since they too may now be dead or may have a
443 // reduced number of uses, allowing other xforms.
444 if (N->use_empty() && N != &Dummy) {
445 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
446 WorkList.push_back(N->getOperand(i).Val);
448 removeFromWorkList(N);
453 SDOperand RV = visit(N);
456 // If we get back the same node we passed in, rather than a new node or
457 // zero, we know that the node must have defined multiple values and
458 // CombineTo was used. Since CombineTo takes care of the worklist
459 // mechanics for us, we have no work to do in this case.
461 DEBUG(std::cerr << "\nReplacing "; N->dump();
462 std::cerr << "\nWith: "; RV.Val->dump();
464 std::vector<SDNode*> NowDead;
465 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
467 // Push the new node and any users onto the worklist
468 WorkList.push_back(RV.Val);
469 AddUsersToWorkList(RV.Val);
471 // Nodes can end up on the worklist more than once. Make sure we do
472 // not process a node that has been replaced.
473 removeFromWorkList(N);
474 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
475 removeFromWorkList(NowDead[i]);
477 // Finally, since the node is now dead, remove it from the graph.
483 // If the root changed (e.g. it was a dead load, update the root).
484 DAG.setRoot(Dummy.getValue());
487 SDOperand DAGCombiner::visit(SDNode *N) {
488 switch(N->getOpcode()) {
490 case ISD::TokenFactor: return visitTokenFactor(N);
491 case ISD::ADD: return visitADD(N);
492 case ISD::SUB: return visitSUB(N);
493 case ISD::MUL: return visitMUL(N);
494 case ISD::SDIV: return visitSDIV(N);
495 case ISD::UDIV: return visitUDIV(N);
496 case ISD::SREM: return visitSREM(N);
497 case ISD::UREM: return visitUREM(N);
498 case ISD::MULHU: return visitMULHU(N);
499 case ISD::MULHS: return visitMULHS(N);
500 case ISD::AND: return visitAND(N);
501 case ISD::OR: return visitOR(N);
502 case ISD::XOR: return visitXOR(N);
503 case ISD::SHL: return visitSHL(N);
504 case ISD::SRA: return visitSRA(N);
505 case ISD::SRL: return visitSRL(N);
506 case ISD::CTLZ: return visitCTLZ(N);
507 case ISD::CTTZ: return visitCTTZ(N);
508 case ISD::CTPOP: return visitCTPOP(N);
509 case ISD::SELECT: return visitSELECT(N);
510 case ISD::SELECT_CC: return visitSELECT_CC(N);
511 case ISD::SETCC: return visitSETCC(N);
512 case ISD::ADD_PARTS: return visitADD_PARTS(N);
513 case ISD::SUB_PARTS: return visitSUB_PARTS(N);
514 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
515 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
516 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
517 case ISD::TRUNCATE: return visitTRUNCATE(N);
518 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
519 case ISD::FADD: return visitFADD(N);
520 case ISD::FSUB: return visitFSUB(N);
521 case ISD::FMUL: return visitFMUL(N);
522 case ISD::FDIV: return visitFDIV(N);
523 case ISD::FREM: return visitFREM(N);
524 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
525 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
526 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
527 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
528 case ISD::FP_ROUND: return visitFP_ROUND(N);
529 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
530 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
531 case ISD::FNEG: return visitFNEG(N);
532 case ISD::FABS: return visitFABS(N);
533 case ISD::BRCOND: return visitBRCOND(N);
534 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
535 case ISD::BR_CC: return visitBR_CC(N);
536 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
537 case ISD::LOAD: return visitLOAD(N);
538 case ISD::STORE: return visitSTORE(N);
539 case ISD::LOCATION: return visitLOCATION(N);
540 case ISD::DEBUG_LOC: return visitDEBUGLOC(N);
545 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
546 std::vector<SDOperand> Ops;
547 bool Changed = false;
549 // If the token factor has two operands and one is the entry token, replace
550 // the token factor with the other operand.
551 if (N->getNumOperands() == 2) {
552 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
553 return N->getOperand(1);
554 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
555 return N->getOperand(0);
558 // fold (tokenfactor (tokenfactor)) -> tokenfactor
559 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
560 SDOperand Op = N->getOperand(i);
561 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
563 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
564 Ops.push_back(Op.getOperand(j));
570 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
574 SDOperand DAGCombiner::visitADD(SDNode *N) {
575 SDOperand N0 = N->getOperand(0);
576 SDOperand N1 = N->getOperand(1);
577 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
578 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
579 MVT::ValueType VT = N0.getValueType();
581 // fold (add c1, c2) -> c1+c2
583 return DAG.getNode(ISD::ADD, VT, N0, N1);
584 // canonicalize constant to RHS
586 return DAG.getNode(ISD::ADD, VT, N1, N0);
587 // fold (add x, 0) -> x
588 if (N1C && N1C->isNullValue())
590 // fold (add (add x, c1), c2) -> (add x, c1+c2)
591 if (N1C && N0.getOpcode() == ISD::ADD) {
592 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
593 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
595 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1),
596 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT));
598 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
599 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT));
602 // fold ((c1-A)+c2) -> (c1+c2)-A
603 if (N1C && N0.getOpcode() == ISD::SUB)
604 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
605 return DAG.getNode(ISD::SUB, VT,
606 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
609 // fold ((0-A) + B) -> B-A
610 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
611 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
612 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
613 // fold (A + (0-B)) -> A-B
614 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
615 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
616 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
617 // fold (A+(B-A)) -> B
618 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
619 return N1.getOperand(0);
623 SDOperand DAGCombiner::visitSUB(SDNode *N) {
624 SDOperand N0 = N->getOperand(0);
625 SDOperand N1 = N->getOperand(1);
626 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
627 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
628 MVT::ValueType VT = N0.getValueType();
630 // fold (sub x, x) -> 0
632 return DAG.getConstant(0, N->getValueType(0));
633 // fold (sub c1, c2) -> c1-c2
635 return DAG.getNode(ISD::SUB, VT, N0, N1);
636 // fold (sub x, c) -> (add x, -c)
638 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
640 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
641 return N0.getOperand(1);
643 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
644 return N0.getOperand(0);
648 SDOperand DAGCombiner::visitMUL(SDNode *N) {
649 SDOperand N0 = N->getOperand(0);
650 SDOperand N1 = N->getOperand(1);
651 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
652 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
653 MVT::ValueType VT = N0.getValueType();
655 // fold (mul c1, c2) -> c1*c2
657 return DAG.getNode(ISD::MUL, VT, N0, N1);
658 // canonicalize constant to RHS
660 return DAG.getNode(ISD::MUL, VT, N1, N0);
661 // fold (mul x, 0) -> 0
662 if (N1C && N1C->isNullValue())
664 // fold (mul x, -1) -> 0-x
665 if (N1C && N1C->isAllOnesValue())
666 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
667 // fold (mul x, (1 << c)) -> x << c
668 if (N1C && isPowerOf2_64(N1C->getValue()))
669 return DAG.getNode(ISD::SHL, VT, N0,
670 DAG.getConstant(Log2_64(N1C->getValue()),
671 TLI.getShiftAmountTy()));
672 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
673 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
674 // FIXME: If the input is something that is easily negated (e.g. a
675 // single-use add), we should put the negate there.
676 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
677 DAG.getNode(ISD::SHL, VT, N0,
678 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
679 TLI.getShiftAmountTy())));
683 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
684 if (N1C && N0.getOpcode() == ISD::MUL) {
685 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
686 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
688 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1),
689 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT));
691 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
692 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT));
697 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
698 SDOperand N0 = N->getOperand(0);
699 SDOperand N1 = N->getOperand(1);
700 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
701 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
702 MVT::ValueType VT = N->getValueType(0);
704 // fold (sdiv c1, c2) -> c1/c2
705 if (N0C && N1C && !N1C->isNullValue())
706 return DAG.getNode(ISD::SDIV, VT, N0, N1);
707 // fold (sdiv X, 1) -> X
708 if (N1C && N1C->getSignExtended() == 1LL)
710 // fold (sdiv X, -1) -> 0-X
711 if (N1C && N1C->isAllOnesValue())
712 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
713 // If we know the sign bits of both operands are zero, strength reduce to a
714 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
715 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
716 if (TLI.MaskedValueIsZero(N1, SignBit) &&
717 TLI.MaskedValueIsZero(N0, SignBit))
718 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
719 // fold (sdiv X, pow2) -> (add (sra X, log(pow2)), (srl X, sizeof(X)-1))
720 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
721 (isPowerOf2_64(N1C->getSignExtended()) ||
722 isPowerOf2_64(-N1C->getSignExtended()))) {
723 // If dividing by powers of two is cheap, then don't perform the following
725 if (TLI.isPow2DivCheap())
727 int64_t pow2 = N1C->getSignExtended();
728 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
729 SDOperand SRL = DAG.getNode(ISD::SRL, VT, N0,
730 DAG.getConstant(MVT::getSizeInBits(VT)-1,
731 TLI.getShiftAmountTy()));
732 WorkList.push_back(SRL.Val);
733 SDOperand SGN = DAG.getNode(ISD::ADD, VT, N0, SRL);
734 WorkList.push_back(SGN.Val);
735 SDOperand SRA = DAG.getNode(ISD::SRA, VT, SGN,
736 DAG.getConstant(Log2_64(abs2),
737 TLI.getShiftAmountTy()));
738 // If we're dividing by a positive value, we're done. Otherwise, we must
739 // negate the result.
742 WorkList.push_back(SRA.Val);
743 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
745 // if integer divide is expensive and we satisfy the requirements, emit an
746 // alternate sequence.
747 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
748 !TLI.isIntDivCheap()) {
749 SDOperand Op = BuildSDIV(N);
750 if (Op.Val) return Op;
755 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
756 SDOperand N0 = N->getOperand(0);
757 SDOperand N1 = N->getOperand(1);
758 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
759 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
760 MVT::ValueType VT = N->getValueType(0);
762 // fold (udiv c1, c2) -> c1/c2
763 if (N0C && N1C && !N1C->isNullValue())
764 return DAG.getNode(ISD::UDIV, VT, N0, N1);
765 // fold (udiv x, (1 << c)) -> x >>u c
766 if (N1C && isPowerOf2_64(N1C->getValue()))
767 return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
768 DAG.getConstant(Log2_64(N1C->getValue()),
769 TLI.getShiftAmountTy()));
770 // fold (udiv x, c) -> alternate
771 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
772 SDOperand Op = BuildUDIV(N);
773 if (Op.Val) return Op;
779 SDOperand DAGCombiner::visitSREM(SDNode *N) {
780 SDOperand N0 = N->getOperand(0);
781 SDOperand N1 = N->getOperand(1);
782 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
783 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
784 MVT::ValueType VT = N->getValueType(0);
786 // fold (srem c1, c2) -> c1%c2
787 if (N0C && N1C && !N1C->isNullValue())
788 return DAG.getNode(ISD::SREM, VT, N0, N1);
789 // If we know the sign bits of both operands are zero, strength reduce to a
790 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
791 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
792 if (TLI.MaskedValueIsZero(N1, SignBit) &&
793 TLI.MaskedValueIsZero(N0, SignBit))
794 return DAG.getNode(ISD::UREM, VT, N0, N1);
798 SDOperand DAGCombiner::visitUREM(SDNode *N) {
799 SDOperand N0 = N->getOperand(0);
800 SDOperand N1 = N->getOperand(1);
801 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
802 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
803 MVT::ValueType VT = N->getValueType(0);
805 // fold (urem c1, c2) -> c1%c2
806 if (N0C && N1C && !N1C->isNullValue())
807 return DAG.getNode(ISD::UREM, VT, N0, N1);
808 // fold (urem x, pow2) -> (and x, pow2-1)
809 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
810 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
814 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
815 SDOperand N0 = N->getOperand(0);
816 SDOperand N1 = N->getOperand(1);
817 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
819 // fold (mulhs x, 0) -> 0
820 if (N1C && N1C->isNullValue())
822 // fold (mulhs x, 1) -> (sra x, size(x)-1)
823 if (N1C && N1C->getValue() == 1)
824 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
825 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
826 TLI.getShiftAmountTy()));
830 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
831 SDOperand N0 = N->getOperand(0);
832 SDOperand N1 = N->getOperand(1);
833 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
835 // fold (mulhu x, 0) -> 0
836 if (N1C && N1C->isNullValue())
838 // fold (mulhu x, 1) -> 0
839 if (N1C && N1C->getValue() == 1)
840 return DAG.getConstant(0, N0.getValueType());
844 SDOperand DAGCombiner::visitAND(SDNode *N) {
845 SDOperand N0 = N->getOperand(0);
846 SDOperand N1 = N->getOperand(1);
847 SDOperand LL, LR, RL, RR, CC0, CC1;
848 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
849 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
850 MVT::ValueType VT = N1.getValueType();
851 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
853 // fold (and c1, c2) -> c1&c2
855 return DAG.getNode(ISD::AND, VT, N0, N1);
856 // canonicalize constant to RHS
858 return DAG.getNode(ISD::AND, VT, N1, N0);
859 // fold (and x, -1) -> x
860 if (N1C && N1C->isAllOnesValue())
862 // if (and x, c) is known to be zero, return 0
863 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
864 return DAG.getConstant(0, VT);
865 // fold (and x, c) -> x iff (x & ~c) == 0
867 TLI.MaskedValueIsZero(N0, ~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
869 // fold (and (and x, c1), c2) -> (and x, c1^c2)
870 if (N1C && N0.getOpcode() == ISD::AND) {
871 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
872 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
874 return DAG.getNode(ISD::AND, VT, N0.getOperand(1),
875 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT));
877 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
878 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
880 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
881 if (N1C && N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
882 unsigned ExtendBits =
883 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
884 if (ExtendBits == 64 || ((N1C->getValue() & (~0ULL << ExtendBits)) == 0))
885 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
887 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
888 if (N1C && N0.getOpcode() == ISD::OR)
889 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
890 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
892 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
893 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
894 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
895 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
897 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
898 MVT::isInteger(LL.getValueType())) {
899 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
900 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
901 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
902 WorkList.push_back(ORNode.Val);
903 return DAG.getSetCC(VT, ORNode, LR, Op1);
905 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
906 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
907 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
908 WorkList.push_back(ANDNode.Val);
909 return DAG.getSetCC(VT, ANDNode, LR, Op1);
911 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
912 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
913 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
914 WorkList.push_back(ORNode.Val);
915 return DAG.getSetCC(VT, ORNode, LR, Op1);
918 // canonicalize equivalent to ll == rl
919 if (LL == RR && LR == RL) {
920 Op1 = ISD::getSetCCSwappedOperands(Op1);
923 if (LL == RL && LR == RR) {
924 bool isInteger = MVT::isInteger(LL.getValueType());
925 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
926 if (Result != ISD::SETCC_INVALID)
927 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
930 // fold (and (zext x), (zext y)) -> (zext (and x, y))
931 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
932 N1.getOpcode() == ISD::ZERO_EXTEND &&
933 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
934 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
935 N0.getOperand(0), N1.getOperand(0));
936 WorkList.push_back(ANDNode.Val);
937 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
939 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y))
940 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
941 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
942 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
943 N0.getOperand(1) == N1.getOperand(1)) {
944 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
945 N0.getOperand(0), N1.getOperand(0));
946 WorkList.push_back(ANDNode.Val);
947 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
949 // fold (and (sra)) -> (and (srl)) when possible.
950 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) {
951 if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
952 // If the RHS of the AND has zeros where the sign bits of the SRA will
953 // land, turn the SRA into an SRL.
954 if (TLI.MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) &
955 (~0ULL>>(64-OpSizeInBits)))) {
956 WorkList.push_back(N);
957 CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
963 // fold (zext_inreg (extload x)) -> (zextload x)
964 if (N0.getOpcode() == ISD::EXTLOAD) {
965 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
966 // If we zero all the possible extended bits, then we can turn this into
967 // a zextload if we are running before legalize or the operation is legal.
968 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
969 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
970 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
971 N0.getOperand(1), N0.getOperand(2),
973 WorkList.push_back(N);
974 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
978 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
979 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
980 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
981 // If we zero all the possible extended bits, then we can turn this into
982 // a zextload if we are running before legalize or the operation is legal.
983 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
984 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
985 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
986 N0.getOperand(1), N0.getOperand(2),
988 WorkList.push_back(N);
989 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
996 SDOperand DAGCombiner::visitOR(SDNode *N) {
997 SDOperand N0 = N->getOperand(0);
998 SDOperand N1 = N->getOperand(1);
999 SDOperand LL, LR, RL, RR, CC0, CC1;
1000 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1001 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1002 MVT::ValueType VT = N1.getValueType();
1003 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1005 // fold (or c1, c2) -> c1|c2
1007 return DAG.getNode(ISD::OR, VT, N0, N1);
1008 // canonicalize constant to RHS
1010 return DAG.getNode(ISD::OR, VT, N1, N0);
1011 // fold (or x, 0) -> x
1012 if (N1C && N1C->isNullValue())
1014 // fold (or x, -1) -> -1
1015 if (N1C && N1C->isAllOnesValue())
1017 // fold (or x, c) -> c iff (x & ~c) == 0
1019 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1021 // fold (or (or x, c1), c2) -> (or x, c1|c2)
1022 if (N1C && N0.getOpcode() == ISD::OR) {
1023 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1024 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1026 return DAG.getNode(ISD::OR, VT, N0.getOperand(1),
1027 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT));
1029 return DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1030 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT));
1031 } else if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1032 isa<ConstantSDNode>(N0.getOperand(1))) {
1033 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1034 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1035 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1037 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1039 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1040 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1041 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1042 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1044 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1045 MVT::isInteger(LL.getValueType())) {
1046 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1047 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1048 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1049 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1050 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1051 WorkList.push_back(ORNode.Val);
1052 return DAG.getSetCC(VT, ORNode, LR, Op1);
1054 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1055 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1056 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1057 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1058 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1059 WorkList.push_back(ANDNode.Val);
1060 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1063 // canonicalize equivalent to ll == rl
1064 if (LL == RR && LR == RL) {
1065 Op1 = ISD::getSetCCSwappedOperands(Op1);
1068 if (LL == RL && LR == RR) {
1069 bool isInteger = MVT::isInteger(LL.getValueType());
1070 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1071 if (Result != ISD::SETCC_INVALID)
1072 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1075 // fold (or (zext x), (zext y)) -> (zext (or x, y))
1076 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1077 N1.getOpcode() == ISD::ZERO_EXTEND &&
1078 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1079 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1080 N0.getOperand(0), N1.getOperand(0));
1081 WorkList.push_back(ORNode.Val);
1082 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
1084 // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y))
1085 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1086 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1087 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1088 N0.getOperand(1) == N1.getOperand(1)) {
1089 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1090 N0.getOperand(0), N1.getOperand(0));
1091 WorkList.push_back(ORNode.Val);
1092 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1094 // canonicalize shl to left side in a shl/srl pair, to match rotate
1095 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
1097 // check for rotl, rotr
1098 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
1099 N0.getOperand(0) == N1.getOperand(0) &&
1100 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
1101 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1102 if (N0.getOperand(1).getOpcode() == ISD::Constant &&
1103 N1.getOperand(1).getOpcode() == ISD::Constant) {
1104 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1105 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1106 if ((c1val + c2val) == OpSizeInBits)
1107 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1109 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1110 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
1111 N0.getOperand(1) == N1.getOperand(1).getOperand(1))
1112 if (ConstantSDNode *SUBC =
1113 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
1114 if (SUBC->getValue() == OpSizeInBits)
1115 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1116 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1117 if (N0.getOperand(1).getOpcode() == ISD::SUB &&
1118 N1.getOperand(1) == N0.getOperand(1).getOperand(1))
1119 if (ConstantSDNode *SUBC =
1120 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
1121 if (SUBC->getValue() == OpSizeInBits) {
1122 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
1123 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
1126 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
1133 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1134 SDOperand N0 = N->getOperand(0);
1135 SDOperand N1 = N->getOperand(1);
1136 SDOperand LHS, RHS, CC;
1137 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1138 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1139 MVT::ValueType VT = N0.getValueType();
1141 // fold (xor c1, c2) -> c1^c2
1143 return DAG.getNode(ISD::XOR, VT, N0, N1);
1144 // canonicalize constant to RHS
1146 return DAG.getNode(ISD::XOR, VT, N1, N0);
1147 // fold (xor x, 0) -> x
1148 if (N1C && N1C->isNullValue())
1150 // fold !(x cc y) -> (x !cc y)
1151 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1152 bool isInt = MVT::isInteger(LHS.getValueType());
1153 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1155 if (N0.getOpcode() == ISD::SETCC)
1156 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1157 if (N0.getOpcode() == ISD::SELECT_CC)
1158 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1159 assert(0 && "Unhandled SetCC Equivalent!");
1162 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1163 if (N1C && N1C->getValue() == 1 &&
1164 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1165 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1166 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1167 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1168 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1169 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1170 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1171 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1174 // fold !(x or y) -> (!x and !y) iff x or y are constants
1175 if (N1C && N1C->isAllOnesValue() &&
1176 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1177 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1178 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1179 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1180 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1181 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1182 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1183 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1186 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1187 if (N1C && N0.getOpcode() == ISD::XOR) {
1188 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1189 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1191 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1192 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1194 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1195 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1197 // fold (xor x, x) -> 0
1199 return DAG.getConstant(0, VT);
1200 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
1201 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1202 N1.getOpcode() == ISD::ZERO_EXTEND &&
1203 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1204 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1205 N0.getOperand(0), N1.getOperand(0));
1206 WorkList.push_back(XORNode.Val);
1207 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
1209 // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y))
1210 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1211 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1212 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1213 N0.getOperand(1) == N1.getOperand(1)) {
1214 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1215 N0.getOperand(0), N1.getOperand(0));
1216 WorkList.push_back(XORNode.Val);
1217 return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1));
1222 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1223 SDOperand N0 = N->getOperand(0);
1224 SDOperand N1 = N->getOperand(1);
1225 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1226 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1227 MVT::ValueType VT = N0.getValueType();
1228 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1230 // fold (shl c1, c2) -> c1<<c2
1232 return DAG.getNode(ISD::SHL, VT, N0, N1);
1233 // fold (shl 0, x) -> 0
1234 if (N0C && N0C->isNullValue())
1236 // fold (shl x, c >= size(x)) -> undef
1237 if (N1C && N1C->getValue() >= OpSizeInBits)
1238 return DAG.getNode(ISD::UNDEF, VT);
1239 // fold (shl x, 0) -> x
1240 if (N1C && N1C->isNullValue())
1242 // if (shl x, c) is known to be zero, return 0
1243 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1244 return DAG.getConstant(0, VT);
1245 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1246 if (N1C && N0.getOpcode() == ISD::SHL &&
1247 N0.getOperand(1).getOpcode() == ISD::Constant) {
1248 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1249 uint64_t c2 = N1C->getValue();
1250 if (c1 + c2 > OpSizeInBits)
1251 return DAG.getConstant(0, VT);
1252 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1253 DAG.getConstant(c1 + c2, N1.getValueType()));
1255 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1256 // (srl (and x, -1 << c1), c1-c2)
1257 if (N1C && N0.getOpcode() == ISD::SRL &&
1258 N0.getOperand(1).getOpcode() == ISD::Constant) {
1259 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1260 uint64_t c2 = N1C->getValue();
1261 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1262 DAG.getConstant(~0ULL << c1, VT));
1264 return DAG.getNode(ISD::SHL, VT, Mask,
1265 DAG.getConstant(c2-c1, N1.getValueType()));
1267 return DAG.getNode(ISD::SRL, VT, Mask,
1268 DAG.getConstant(c1-c2, N1.getValueType()));
1270 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1271 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1272 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1273 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1277 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1278 SDOperand N0 = N->getOperand(0);
1279 SDOperand N1 = N->getOperand(1);
1280 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1281 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1282 MVT::ValueType VT = N0.getValueType();
1283 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1285 // fold (sra c1, c2) -> c1>>c2
1287 return DAG.getNode(ISD::SRA, VT, N0, N1);
1288 // fold (sra 0, x) -> 0
1289 if (N0C && N0C->isNullValue())
1291 // fold (sra -1, x) -> -1
1292 if (N0C && N0C->isAllOnesValue())
1294 // fold (sra x, c >= size(x)) -> undef
1295 if (N1C && N1C->getValue() >= OpSizeInBits)
1296 return DAG.getNode(ISD::UNDEF, VT);
1297 // fold (sra x, 0) -> x
1298 if (N1C && N1C->isNullValue())
1300 // If the sign bit is known to be zero, switch this to a SRL.
1301 if (TLI.MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1))))
1302 return DAG.getNode(ISD::SRL, VT, N0, N1);
1306 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1307 SDOperand N0 = N->getOperand(0);
1308 SDOperand N1 = N->getOperand(1);
1309 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1310 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1311 MVT::ValueType VT = N0.getValueType();
1312 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1314 // fold (srl c1, c2) -> c1 >>u c2
1316 return DAG.getNode(ISD::SRL, VT, N0, N1);
1317 // fold (srl 0, x) -> 0
1318 if (N0C && N0C->isNullValue())
1320 // fold (srl x, c >= size(x)) -> undef
1321 if (N1C && N1C->getValue() >= OpSizeInBits)
1322 return DAG.getNode(ISD::UNDEF, VT);
1323 // fold (srl x, 0) -> x
1324 if (N1C && N1C->isNullValue())
1326 // if (srl x, c) is known to be zero, return 0
1327 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1328 return DAG.getConstant(0, VT);
1329 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1330 if (N1C && N0.getOpcode() == ISD::SRL &&
1331 N0.getOperand(1).getOpcode() == ISD::Constant) {
1332 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1333 uint64_t c2 = N1C->getValue();
1334 if (c1 + c2 > OpSizeInBits)
1335 return DAG.getConstant(0, VT);
1336 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1337 DAG.getConstant(c1 + c2, N1.getValueType()));
1342 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1343 SDOperand N0 = N->getOperand(0);
1344 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1345 MVT::ValueType VT = N->getValueType(0);
1347 // fold (ctlz c1) -> c2
1349 return DAG.getNode(ISD::CTLZ, VT, N0);
1353 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1354 SDOperand N0 = N->getOperand(0);
1355 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1356 MVT::ValueType VT = N->getValueType(0);
1358 // fold (cttz c1) -> c2
1360 return DAG.getNode(ISD::CTTZ, VT, N0);
1364 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1365 SDOperand N0 = N->getOperand(0);
1366 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1367 MVT::ValueType VT = N->getValueType(0);
1369 // fold (ctpop c1) -> c2
1371 return DAG.getNode(ISD::CTPOP, VT, N0);
1375 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1376 SDOperand N0 = N->getOperand(0);
1377 SDOperand N1 = N->getOperand(1);
1378 SDOperand N2 = N->getOperand(2);
1379 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1380 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1381 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1382 MVT::ValueType VT = N->getValueType(0);
1384 // fold select C, X, X -> X
1387 // fold select true, X, Y -> X
1388 if (N0C && !N0C->isNullValue())
1390 // fold select false, X, Y -> Y
1391 if (N0C && N0C->isNullValue())
1393 // fold select C, 1, X -> C | X
1394 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1395 return DAG.getNode(ISD::OR, VT, N0, N2);
1396 // fold select C, 0, X -> ~C & X
1397 // FIXME: this should check for C type == X type, not i1?
1398 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1399 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1400 WorkList.push_back(XORNode.Val);
1401 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1403 // fold select C, X, 1 -> ~C | X
1404 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1405 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1406 WorkList.push_back(XORNode.Val);
1407 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1409 // fold select C, X, 0 -> C & X
1410 // FIXME: this should check for C type == X type, not i1?
1411 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1412 return DAG.getNode(ISD::AND, VT, N0, N1);
1413 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1414 if (MVT::i1 == VT && N0 == N1)
1415 return DAG.getNode(ISD::OR, VT, N0, N2);
1416 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1417 if (MVT::i1 == VT && N0 == N2)
1418 return DAG.getNode(ISD::AND, VT, N0, N1);
1419 // If we can fold this based on the true/false value, do so.
1420 if (SimplifySelectOps(N, N1, N2))
1422 // fold selects based on a setcc into other things, such as min/max/abs
1423 if (N0.getOpcode() == ISD::SETCC)
1425 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1426 // having to say they don't support SELECT_CC on every type the DAG knows
1427 // about, since there is no way to mark an opcode illegal at all value types
1428 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1429 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1430 N1, N2, N0.getOperand(2));
1432 return SimplifySelect(N0, N1, N2);
1436 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1437 SDOperand N0 = N->getOperand(0);
1438 SDOperand N1 = N->getOperand(1);
1439 SDOperand N2 = N->getOperand(2);
1440 SDOperand N3 = N->getOperand(3);
1441 SDOperand N4 = N->getOperand(4);
1442 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1443 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1444 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1445 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1447 // Determine if the condition we're dealing with is constant
1448 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1449 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1451 // fold select_cc lhs, rhs, x, x, cc -> x
1455 // If we can fold this based on the true/false value, do so.
1456 if (SimplifySelectOps(N, N2, N3))
1459 // fold select_cc into other things, such as min/max/abs
1460 return SimplifySelectCC(N0, N1, N2, N3, CC);
1463 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1464 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1465 cast<CondCodeSDNode>(N->getOperand(2))->get());
1468 SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
1469 SDOperand LHSLo = N->getOperand(0);
1470 SDOperand RHSLo = N->getOperand(2);
1471 MVT::ValueType VT = LHSLo.getValueType();
1473 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo)
1474 if (TLI.MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) {
1475 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1477 WorkList.push_back(Hi.Val);
1478 CombineTo(N, RHSLo, Hi);
1481 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo)
1482 if (TLI.MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) {
1483 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1485 WorkList.push_back(Hi.Val);
1486 CombineTo(N, LHSLo, Hi);
1492 SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) {
1493 SDOperand LHSLo = N->getOperand(0);
1494 SDOperand RHSLo = N->getOperand(2);
1495 MVT::ValueType VT = LHSLo.getValueType();
1497 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo)
1498 if (TLI.MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) {
1499 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1),
1501 WorkList.push_back(Hi.Val);
1502 CombineTo(N, LHSLo, Hi);
1508 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1509 SDOperand N0 = N->getOperand(0);
1510 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1511 MVT::ValueType VT = N->getValueType(0);
1513 // fold (sext c1) -> c1
1515 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1516 // fold (sext (sext x)) -> (sext x)
1517 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1518 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1519 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
1520 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1522 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
1523 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1524 DAG.getValueType(N0.getValueType()));
1525 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1526 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1527 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
1528 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1529 N0.getOperand(1), N0.getOperand(2),
1531 CombineTo(N, ExtLoad);
1532 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1533 ExtLoad.getValue(1));
1537 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1538 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1539 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1541 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0),
1542 N0.getOperand(1), N0.getOperand(2),
1544 CombineTo(N, ExtLoad);
1545 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1546 ExtLoad.getValue(1));
1553 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1554 SDOperand N0 = N->getOperand(0);
1555 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1556 MVT::ValueType VT = N->getValueType(0);
1558 // fold (zext c1) -> c1
1560 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1561 // fold (zext (zext x)) -> (zext x)
1562 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1563 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1564 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
1565 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1566 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType())))
1567 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
1568 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1569 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1570 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
1571 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1572 N0.getOperand(1), N0.getOperand(2),
1574 CombineTo(N, ExtLoad);
1575 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1576 ExtLoad.getValue(1));
1580 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1581 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1582 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1584 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1585 N0.getOperand(1), N0.getOperand(2),
1587 CombineTo(N, ExtLoad);
1588 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1589 ExtLoad.getValue(1));
1595 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1596 SDOperand N0 = N->getOperand(0);
1597 SDOperand N1 = N->getOperand(1);
1598 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1599 MVT::ValueType VT = N->getValueType(0);
1600 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1601 unsigned EVTBits = MVT::getSizeInBits(EVT);
1603 // fold (sext_in_reg c1) -> c1
1605 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1606 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1608 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1609 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1610 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1613 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1614 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1615 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1616 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1618 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1619 if (N0.getOpcode() == ISD::AssertSext &&
1620 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1623 // fold (sext_in_reg (sextload x)) -> (sextload x)
1624 if (N0.getOpcode() == ISD::SEXTLOAD &&
1625 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1628 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1629 if (N0.getOpcode() == ISD::SETCC &&
1630 TLI.getSetCCResultContents() ==
1631 TargetLowering::ZeroOrNegativeOneSetCCResult)
1633 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1634 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
1635 return DAG.getNode(ISD::AND, N0.getValueType(), N0,
1636 DAG.getConstant(~0ULL >> (64-EVTBits), VT));
1637 // fold (sext_in_reg (srl x)) -> sra x
1638 if (N0.getOpcode() == ISD::SRL &&
1639 N0.getOperand(1).getOpcode() == ISD::Constant &&
1640 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1641 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1644 // fold (sext_inreg (extload x)) -> (sextload x)
1645 if (N0.getOpcode() == ISD::EXTLOAD &&
1646 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1647 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1648 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1649 N0.getOperand(1), N0.getOperand(2),
1651 CombineTo(N, ExtLoad);
1652 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1655 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1656 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
1657 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1658 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1659 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1660 N0.getOperand(1), N0.getOperand(2),
1662 CombineTo(N, ExtLoad);
1663 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1669 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1670 SDOperand N0 = N->getOperand(0);
1671 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1672 MVT::ValueType VT = N->getValueType(0);
1675 if (N0.getValueType() == N->getValueType(0))
1677 // fold (truncate c1) -> c1
1679 return DAG.getNode(ISD::TRUNCATE, VT, N0);
1680 // fold (truncate (truncate x)) -> (truncate x)
1681 if (N0.getOpcode() == ISD::TRUNCATE)
1682 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1683 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1684 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1685 if (N0.getValueType() < VT)
1686 // if the source is smaller than the dest, we still need an extend
1687 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1688 else if (N0.getValueType() > VT)
1689 // if the source is larger than the dest, than we just need the truncate
1690 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1692 // if the source and dest are the same type, we can drop both the extend
1694 return N0.getOperand(0);
1696 // fold (truncate (load x)) -> (smaller load x)
1697 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1698 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1699 "Cannot truncate to larger type!");
1700 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1701 // For big endian targets, we need to add an offset to the pointer to load
1702 // the correct bytes. For little endian systems, we merely need to read
1703 // fewer bytes from the same pointer.
1705 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1706 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1707 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1708 DAG.getConstant(PtrOff, PtrType));
1709 WorkList.push_back(NewPtr.Val);
1710 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1711 WorkList.push_back(N);
1712 CombineTo(N0.Val, Load, Load.getValue(1));
1718 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
1719 SDOperand N0 = N->getOperand(0);
1720 MVT::ValueType VT = N->getValueType(0);
1722 // If the input is a constant, let getNode() fold it.
1723 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
1724 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
1725 if (Res.Val != N) return Res;
1728 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
1729 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
1731 // fold (conv (load x)) -> (load (conv*)x)
1732 // FIXME: These xforms need to know that the resultant load doesn't need a
1733 // higher alignment than the original!
1734 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1735 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
1737 WorkList.push_back(N);
1738 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
1746 SDOperand DAGCombiner::visitFADD(SDNode *N) {
1747 SDOperand N0 = N->getOperand(0);
1748 SDOperand N1 = N->getOperand(1);
1749 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1750 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1751 MVT::ValueType VT = N->getValueType(0);
1753 // fold (fadd c1, c2) -> c1+c2
1755 return DAG.getNode(ISD::FADD, VT, N0, N1);
1756 // canonicalize constant to RHS
1757 if (N0CFP && !N1CFP)
1758 return DAG.getNode(ISD::FADD, VT, N1, N0);
1759 // fold (A + (-B)) -> A-B
1760 if (N1.getOpcode() == ISD::FNEG)
1761 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1762 // fold ((-A) + B) -> B-A
1763 if (N0.getOpcode() == ISD::FNEG)
1764 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1768 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1769 SDOperand N0 = N->getOperand(0);
1770 SDOperand N1 = N->getOperand(1);
1771 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1772 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1773 MVT::ValueType VT = N->getValueType(0);
1775 // fold (fsub c1, c2) -> c1-c2
1777 return DAG.getNode(ISD::FSUB, VT, N0, N1);
1778 // fold (A-(-B)) -> A+B
1779 if (N1.getOpcode() == ISD::FNEG)
1780 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
1784 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1785 SDOperand N0 = N->getOperand(0);
1786 SDOperand N1 = N->getOperand(1);
1787 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1788 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1789 MVT::ValueType VT = N->getValueType(0);
1791 // fold (fmul c1, c2) -> c1*c2
1793 return DAG.getNode(ISD::FMUL, VT, N0, N1);
1794 // canonicalize constant to RHS
1795 if (N0CFP && !N1CFP)
1796 return DAG.getNode(ISD::FMUL, VT, N1, N0);
1797 // fold (fmul X, 2.0) -> (fadd X, X)
1798 if (N1CFP && N1CFP->isExactlyValue(+2.0))
1799 return DAG.getNode(ISD::FADD, VT, N0, N0);
1803 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1804 SDOperand N0 = N->getOperand(0);
1805 SDOperand N1 = N->getOperand(1);
1806 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1807 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1808 MVT::ValueType VT = N->getValueType(0);
1810 // fold (fdiv c1, c2) -> c1/c2
1812 return DAG.getNode(ISD::FDIV, VT, N0, N1);
1816 SDOperand DAGCombiner::visitFREM(SDNode *N) {
1817 SDOperand N0 = N->getOperand(0);
1818 SDOperand N1 = N->getOperand(1);
1819 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1820 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1821 MVT::ValueType VT = N->getValueType(0);
1823 // fold (frem c1, c2) -> fmod(c1,c2)
1825 return DAG.getNode(ISD::FREM, VT, N0, N1);
1830 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1831 SDOperand N0 = N->getOperand(0);
1832 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1833 MVT::ValueType VT = N->getValueType(0);
1835 // fold (sint_to_fp c1) -> c1fp
1837 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
1841 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1842 SDOperand N0 = N->getOperand(0);
1843 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1844 MVT::ValueType VT = N->getValueType(0);
1846 // fold (uint_to_fp c1) -> c1fp
1848 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
1852 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1853 SDOperand N0 = N->getOperand(0);
1854 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1855 MVT::ValueType VT = N->getValueType(0);
1857 // fold (fp_to_sint c1fp) -> c1
1859 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
1863 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1864 SDOperand N0 = N->getOperand(0);
1865 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1866 MVT::ValueType VT = N->getValueType(0);
1868 // fold (fp_to_uint c1fp) -> c1
1870 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
1874 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1875 SDOperand N0 = N->getOperand(0);
1876 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1877 MVT::ValueType VT = N->getValueType(0);
1879 // fold (fp_round c1fp) -> c1fp
1881 return DAG.getNode(ISD::FP_ROUND, VT, N0);
1885 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1886 SDOperand N0 = N->getOperand(0);
1887 MVT::ValueType VT = N->getValueType(0);
1888 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1889 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1891 // fold (fp_round_inreg c1fp) -> c1fp
1893 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1894 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1899 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1900 SDOperand N0 = N->getOperand(0);
1901 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1902 MVT::ValueType VT = N->getValueType(0);
1904 // fold (fp_extend c1fp) -> c1fp
1906 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
1910 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1911 SDOperand N0 = N->getOperand(0);
1912 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1913 MVT::ValueType VT = N->getValueType(0);
1915 // fold (fneg c1) -> -c1
1917 return DAG.getNode(ISD::FNEG, VT, N0);
1918 // fold (fneg (sub x, y)) -> (sub y, x)
1919 if (N->getOperand(0).getOpcode() == ISD::SUB)
1920 return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0));
1921 // fold (fneg (fneg x)) -> x
1922 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1923 return N->getOperand(0).getOperand(0);
1927 SDOperand DAGCombiner::visitFABS(SDNode *N) {
1928 SDOperand N0 = N->getOperand(0);
1929 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1930 MVT::ValueType VT = N->getValueType(0);
1932 // fold (fabs c1) -> fabs(c1)
1934 return DAG.getNode(ISD::FABS, VT, N0);
1935 // fold (fabs (fabs x)) -> (fabs x)
1936 if (N->getOperand(0).getOpcode() == ISD::FABS)
1937 return N->getOperand(0);
1938 // fold (fabs (fneg x)) -> (fabs x)
1939 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1940 return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0));
1944 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
1945 SDOperand Chain = N->getOperand(0);
1946 SDOperand N1 = N->getOperand(1);
1947 SDOperand N2 = N->getOperand(2);
1948 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1950 // never taken branch, fold to chain
1951 if (N1C && N1C->isNullValue())
1953 // unconditional branch
1954 if (N1C && N1C->getValue() == 1)
1955 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1956 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
1958 if (N1.getOpcode() == ISD::SETCC &&
1959 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
1960 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
1961 N1.getOperand(0), N1.getOperand(1), N2);
1966 SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
1967 SDOperand Chain = N->getOperand(0);
1968 SDOperand N1 = N->getOperand(1);
1969 SDOperand N2 = N->getOperand(2);
1970 SDOperand N3 = N->getOperand(3);
1971 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1973 // unconditional branch to true mbb
1974 if (N1C && N1C->getValue() == 1)
1975 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1976 // unconditional branch to false mbb
1977 if (N1C && N1C->isNullValue())
1978 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
1979 // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if
1980 // BRTWOWAY_CC is legal on the target.
1981 if (N1.getOpcode() == ISD::SETCC &&
1982 TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
1983 std::vector<SDOperand> Ops;
1984 Ops.push_back(Chain);
1985 Ops.push_back(N1.getOperand(2));
1986 Ops.push_back(N1.getOperand(0));
1987 Ops.push_back(N1.getOperand(1));
1990 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
1995 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
1997 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
1998 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
1999 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2001 // Use SimplifySetCC to simplify SETCC's.
2002 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2003 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2005 // fold br_cc true, dest -> br dest (unconditional branch)
2006 if (SCCC && SCCC->getValue())
2007 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2009 // fold br_cc false, dest -> unconditional fall through
2010 if (SCCC && SCCC->isNullValue())
2011 return N->getOperand(0);
2012 // fold to a simpler setcc
2013 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2014 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2015 Simp.getOperand(2), Simp.getOperand(0),
2016 Simp.getOperand(1), N->getOperand(4));
2020 SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
2021 SDOperand Chain = N->getOperand(0);
2022 SDOperand CCN = N->getOperand(1);
2023 SDOperand LHS = N->getOperand(2);
2024 SDOperand RHS = N->getOperand(3);
2025 SDOperand N4 = N->getOperand(4);
2026 SDOperand N5 = N->getOperand(5);
2028 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
2029 cast<CondCodeSDNode>(CCN)->get(), false);
2030 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2032 // fold select_cc lhs, rhs, x, x, cc -> x
2034 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2035 // fold select_cc true, x, y -> x
2036 if (SCCC && SCCC->getValue())
2037 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2038 // fold select_cc false, x, y -> y
2039 if (SCCC && SCCC->isNullValue())
2040 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
2041 // fold to a simpler setcc
2042 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) {
2043 std::vector<SDOperand> Ops;
2044 Ops.push_back(Chain);
2045 Ops.push_back(SCC.getOperand(2));
2046 Ops.push_back(SCC.getOperand(0));
2047 Ops.push_back(SCC.getOperand(1));
2050 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
2055 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2056 SDOperand Chain = N->getOperand(0);
2057 SDOperand Ptr = N->getOperand(1);
2058 SDOperand SrcValue = N->getOperand(2);
2060 // If this load is directly stored, replace the load value with the stored
2062 // TODO: Handle store large -> read small portion.
2063 // TODO: Handle TRUNCSTORE/EXTLOAD
2064 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2065 Chain.getOperand(1).getValueType() == N->getValueType(0))
2066 return CombineTo(N, Chain.getOperand(1), Chain);
2071 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2072 SDOperand Chain = N->getOperand(0);
2073 SDOperand Value = N->getOperand(1);
2074 SDOperand Ptr = N->getOperand(2);
2075 SDOperand SrcValue = N->getOperand(3);
2077 // If this is a store that kills a previous store, remove the previous store.
2078 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2079 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2080 // Make sure that these stores are the same value type:
2081 // FIXME: we really care that the second store is >= size of the first.
2082 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2083 // Create a new store of Value that replaces both stores.
2084 SDNode *PrevStore = Chain.Val;
2085 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2087 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
2088 PrevStore->getOperand(0), Value, Ptr,
2090 CombineTo(N, NewStore); // Nuke this store.
2091 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2092 return SDOperand(N, 0);
2095 // If this is a store of a bit convert, store the input value.
2096 // FIXME: This needs to know that the resultant store does not need a
2097 // higher alignment than the original.
2098 if (0 && Value.getOpcode() == ISD::BIT_CONVERT)
2099 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
2105 SDOperand DAGCombiner::visitLOCATION(SDNode *N) {
2106 SDOperand Chain = N->getOperand(0);
2108 // Remove redundant locations (last one holds)
2109 if (Chain.getOpcode() == ISD::LOCATION && Chain.hasOneUse()) {
2110 return DAG.getNode(ISD::LOCATION, MVT::Other, Chain.getOperand(0),
2120 SDOperand DAGCombiner::visitDEBUGLOC(SDNode *N) {
2121 SDOperand Chain = N->getOperand(0);
2123 // Remove redundant debug locations (last one holds)
2124 if (Chain.getOpcode() == ISD::DEBUG_LOC && Chain.hasOneUse()) {
2125 return DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Chain.getOperand(0),
2134 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
2135 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
2137 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
2138 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2139 // If we got a simplified select_cc node back from SimplifySelectCC, then
2140 // break it down into a new SETCC node, and a new SELECT node, and then return
2141 // the SELECT node, since we were called with a SELECT node.
2143 // Check to see if we got a select_cc back (to turn into setcc/select).
2144 // Otherwise, just return whatever node we got back, like fabs.
2145 if (SCC.getOpcode() == ISD::SELECT_CC) {
2146 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
2147 SCC.getOperand(0), SCC.getOperand(1),
2149 WorkList.push_back(SETCC.Val);
2150 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
2151 SCC.getOperand(3), SETCC);
2158 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
2159 /// are the two values being selected between, see if we can simplify the
2162 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
2165 // If this is a select from two identical things, try to pull the operation
2166 // through the select.
2167 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
2169 std::cerr << "SELECT: ["; LHS.Val->dump();
2170 std::cerr << "] ["; RHS.Val->dump();
2174 // If this is a load and the token chain is identical, replace the select
2175 // of two loads with a load through a select of the address to load from.
2176 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
2177 // constants have been dropped into the constant pool.
2178 if ((LHS.getOpcode() == ISD::LOAD ||
2179 LHS.getOpcode() == ISD::EXTLOAD ||
2180 LHS.getOpcode() == ISD::ZEXTLOAD ||
2181 LHS.getOpcode() == ISD::SEXTLOAD) &&
2182 // Token chains must be identical.
2183 LHS.getOperand(0) == RHS.getOperand(0) &&
2184 // If this is an EXTLOAD, the VT's must match.
2185 (LHS.getOpcode() == ISD::LOAD ||
2186 LHS.getOperand(3) == RHS.getOperand(3))) {
2187 // FIXME: this conflates two src values, discarding one. This is not
2188 // the right thing to do, but nothing uses srcvalues now. When they do,
2189 // turn SrcValue into a list of locations.
2191 if (TheSelect->getOpcode() == ISD::SELECT)
2192 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
2193 TheSelect->getOperand(0), LHS.getOperand(1),
2196 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
2197 TheSelect->getOperand(0),
2198 TheSelect->getOperand(1),
2199 LHS.getOperand(1), RHS.getOperand(1),
2200 TheSelect->getOperand(4));
2203 if (LHS.getOpcode() == ISD::LOAD)
2204 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
2205 Addr, LHS.getOperand(2));
2207 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
2208 LHS.getOperand(0), Addr, LHS.getOperand(2),
2209 cast<VTSDNode>(LHS.getOperand(3))->getVT());
2210 // Users of the select now use the result of the load.
2211 CombineTo(TheSelect, Load);
2213 // Users of the old loads now use the new load's chain. We know the
2214 // old-load value is dead now.
2215 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
2216 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
2224 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
2225 SDOperand N2, SDOperand N3,
2228 MVT::ValueType VT = N2.getValueType();
2229 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
2230 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
2231 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
2232 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
2234 // Determine if the condition we're dealing with is constant
2235 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2236 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2238 // fold select_cc true, x, y -> x
2239 if (SCCC && SCCC->getValue())
2241 // fold select_cc false, x, y -> y
2242 if (SCCC && SCCC->getValue() == 0)
2245 // Check to see if we can simplify the select into an fabs node
2246 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
2247 // Allow either -0.0 or 0.0
2248 if (CFP->getValue() == 0.0) {
2249 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
2250 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
2251 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
2252 N2 == N3.getOperand(0))
2253 return DAG.getNode(ISD::FABS, VT, N0);
2255 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
2256 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
2257 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
2258 N2.getOperand(0) == N3)
2259 return DAG.getNode(ISD::FABS, VT, N3);
2263 // Check to see if we can perform the "gzip trick", transforming
2264 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
2265 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
2266 MVT::isInteger(N0.getValueType()) &&
2267 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
2268 MVT::ValueType XType = N0.getValueType();
2269 MVT::ValueType AType = N2.getValueType();
2270 if (XType >= AType) {
2271 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
2272 // single-bit constant.
2273 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
2274 unsigned ShCtV = Log2_64(N2C->getValue());
2275 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
2276 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
2277 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
2278 WorkList.push_back(Shift.Val);
2279 if (XType > AType) {
2280 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2281 WorkList.push_back(Shift.Val);
2283 return DAG.getNode(ISD::AND, AType, Shift, N2);
2285 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2286 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2287 TLI.getShiftAmountTy()));
2288 WorkList.push_back(Shift.Val);
2289 if (XType > AType) {
2290 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2291 WorkList.push_back(Shift.Val);
2293 return DAG.getNode(ISD::AND, AType, Shift, N2);
2297 // fold select C, 16, 0 -> shl C, 4
2298 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
2299 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
2300 // Get a SetCC of the condition
2301 // FIXME: Should probably make sure that setcc is legal if we ever have a
2302 // target where it isn't.
2303 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2304 WorkList.push_back(SCC.Val);
2305 // cast from setcc result type to select result type
2307 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
2309 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
2310 WorkList.push_back(Temp.Val);
2311 // shl setcc result by log2 n2c
2312 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
2313 DAG.getConstant(Log2_64(N2C->getValue()),
2314 TLI.getShiftAmountTy()));
2317 // Check to see if this is the equivalent of setcc
2318 // FIXME: Turn all of these into setcc if setcc if setcc is legal
2319 // otherwise, go ahead with the folds.
2320 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
2321 MVT::ValueType XType = N0.getValueType();
2322 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
2323 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2324 if (Res.getValueType() != VT)
2325 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
2329 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
2330 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
2331 TLI.isOperationLegal(ISD::CTLZ, XType)) {
2332 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
2333 return DAG.getNode(ISD::SRL, XType, Ctlz,
2334 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
2335 TLI.getShiftAmountTy()));
2337 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
2338 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
2339 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
2341 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
2342 DAG.getConstant(~0ULL, XType));
2343 return DAG.getNode(ISD::SRL, XType,
2344 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
2345 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2346 TLI.getShiftAmountTy()));
2348 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
2349 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
2350 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
2351 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2352 TLI.getShiftAmountTy()));
2353 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
2357 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
2358 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2359 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
2360 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
2361 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
2362 MVT::ValueType XType = N0.getValueType();
2363 if (SubC->isNullValue() && MVT::isInteger(XType)) {
2364 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2365 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2366 TLI.getShiftAmountTy()));
2367 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
2368 WorkList.push_back(Shift.Val);
2369 WorkList.push_back(Add.Val);
2370 return DAG.getNode(ISD::XOR, XType, Add, Shift);
2378 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
2379 SDOperand N1, ISD::CondCode Cond,
2380 bool foldBooleans) {
2381 // These setcc operations always fold.
2385 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
2387 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
2390 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
2391 uint64_t C1 = N1C->getValue();
2392 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
2393 uint64_t C0 = N0C->getValue();
2395 // Sign extend the operands if required
2396 if (ISD::isSignedIntSetCC(Cond)) {
2397 C0 = N0C->getSignExtended();
2398 C1 = N1C->getSignExtended();
2402 default: assert(0 && "Unknown integer setcc!");
2403 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2404 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2405 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
2406 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
2407 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
2408 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
2409 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
2410 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
2411 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
2412 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
2415 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2416 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2417 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
2419 // If the comparison constant has bits in the upper part, the
2420 // zero-extended value could never match.
2421 if (C1 & (~0ULL << InSize)) {
2422 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
2426 case ISD::SETEQ: return DAG.getConstant(0, VT);
2429 case ISD::SETNE: return DAG.getConstant(1, VT);
2432 // True if the sign bit of C1 is set.
2433 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
2436 // True if the sign bit of C1 isn't set.
2437 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
2443 // Otherwise, we can perform the comparison with the low bits.
2451 return DAG.getSetCC(VT, N0.getOperand(0),
2452 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
2455 break; // todo, be more careful with signed comparisons
2457 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2458 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2459 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2460 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
2461 MVT::ValueType ExtDstTy = N0.getValueType();
2462 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
2464 // If the extended part has any inconsistent bits, it cannot ever
2465 // compare equal. In other words, they have to be all ones or all
2468 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
2469 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
2470 return DAG.getConstant(Cond == ISD::SETNE, VT);
2473 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
2474 if (Op0Ty == ExtSrcTy) {
2475 ZextOp = N0.getOperand(0);
2477 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
2478 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
2479 DAG.getConstant(Imm, Op0Ty));
2481 WorkList.push_back(ZextOp.Val);
2482 // Otherwise, make this a use of a zext.
2483 return DAG.getSetCC(VT, ZextOp,
2484 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
2489 uint64_t MinVal, MaxVal;
2490 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
2491 if (ISD::isSignedIntSetCC(Cond)) {
2492 MinVal = 1ULL << (OperandBitSize-1);
2493 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
2494 MaxVal = ~0ULL >> (65-OperandBitSize);
2499 MaxVal = ~0ULL >> (64-OperandBitSize);
2502 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2503 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2504 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2505 --C1; // X >= C0 --> X > (C0-1)
2506 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2507 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2510 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2511 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2512 ++C1; // X <= C0 --> X < (C0+1)
2513 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2514 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2517 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2518 return DAG.getConstant(0, VT); // X < MIN --> false
2520 // Canonicalize setgt X, Min --> setne X, Min
2521 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2522 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2523 // Canonicalize setlt X, Max --> setne X, Max
2524 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2525 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2527 // If we have setult X, 1, turn it into seteq X, 0
2528 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2529 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
2531 // If we have setugt X, Max-1, turn it into seteq X, Max
2532 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2533 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
2536 // If we have "setcc X, C0", check to see if we can shrink the immediate
2539 // SETUGT X, SINTMAX -> SETLT X, 0
2540 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
2541 C1 == (~0ULL >> (65-OperandBitSize)))
2542 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
2545 // FIXME: Implement the rest of these.
2547 // Fold bit comparisons when we can.
2548 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2549 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
2550 if (ConstantSDNode *AndRHS =
2551 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2552 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2553 // Perform the xform if the AND RHS is a single bit.
2554 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
2555 return DAG.getNode(ISD::SRL, VT, N0,
2556 DAG.getConstant(Log2_64(AndRHS->getValue()),
2557 TLI.getShiftAmountTy()));
2559 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
2560 // (X & 8) == 8 --> (X & 8) >> 3
2561 // Perform the xform if C1 is a single bit.
2562 if ((C1 & (C1-1)) == 0) {
2563 return DAG.getNode(ISD::SRL, VT, N0,
2564 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
2569 } else if (isa<ConstantSDNode>(N0.Val)) {
2570 // Ensure that the constant occurs on the RHS.
2571 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2574 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
2575 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
2576 double C0 = N0C->getValue(), C1 = N1C->getValue();
2579 default: break; // FIXME: Implement the rest of these!
2580 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2581 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2582 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
2583 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
2584 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
2585 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
2588 // Ensure that the constant occurs on the RHS.
2589 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2593 // We can always fold X == Y for integer setcc's.
2594 if (MVT::isInteger(N0.getValueType()))
2595 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2596 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2597 if (UOF == 2) // FP operators that are undefined on NaNs.
2598 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2599 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2600 return DAG.getConstant(UOF, VT);
2601 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2602 // if it is not already.
2603 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2604 if (NewCond != Cond)
2605 return DAG.getSetCC(VT, N0, N1, NewCond);
2608 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2609 MVT::isInteger(N0.getValueType())) {
2610 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2611 N0.getOpcode() == ISD::XOR) {
2612 // Simplify (X+Y) == (X+Z) --> Y == Z
2613 if (N0.getOpcode() == N1.getOpcode()) {
2614 if (N0.getOperand(0) == N1.getOperand(0))
2615 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2616 if (N0.getOperand(1) == N1.getOperand(1))
2617 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2618 if (isCommutativeBinOp(N0.getOpcode())) {
2619 // If X op Y == Y op X, try other combinations.
2620 if (N0.getOperand(0) == N1.getOperand(1))
2621 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2622 if (N0.getOperand(1) == N1.getOperand(0))
2623 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
2627 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes.
2628 if (N0.getOpcode() == ISD::XOR)
2629 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2630 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2631 // If we know that all of the inverted bits are zero, don't bother
2632 // performing the inversion.
2633 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue()))
2634 return DAG.getSetCC(VT, N0.getOperand(0),
2635 DAG.getConstant(XORC->getValue()^RHSC->getValue(),
2636 N0.getValueType()), Cond);
2639 // Simplify (X+Z) == X --> Z == 0
2640 if (N0.getOperand(0) == N1)
2641 return DAG.getSetCC(VT, N0.getOperand(1),
2642 DAG.getConstant(0, N0.getValueType()), Cond);
2643 if (N0.getOperand(1) == N1) {
2644 if (isCommutativeBinOp(N0.getOpcode()))
2645 return DAG.getSetCC(VT, N0.getOperand(0),
2646 DAG.getConstant(0, N0.getValueType()), Cond);
2648 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2649 // (Z-X) == X --> Z == X<<1
2650 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2652 DAG.getConstant(1,TLI.getShiftAmountTy()));
2653 WorkList.push_back(SH.Val);
2654 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2659 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2660 N1.getOpcode() == ISD::XOR) {
2661 // Simplify X == (X+Z) --> Z == 0
2662 if (N1.getOperand(0) == N0) {
2663 return DAG.getSetCC(VT, N1.getOperand(1),
2664 DAG.getConstant(0, N1.getValueType()), Cond);
2665 } else if (N1.getOperand(1) == N0) {
2666 if (isCommutativeBinOp(N1.getOpcode())) {
2667 return DAG.getSetCC(VT, N1.getOperand(0),
2668 DAG.getConstant(0, N1.getValueType()), Cond);
2670 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2671 // X == (Z-X) --> X<<1 == Z
2672 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2673 DAG.getConstant(1,TLI.getShiftAmountTy()));
2674 WorkList.push_back(SH.Val);
2675 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2681 // Fold away ALL boolean setcc's.
2683 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2685 default: assert(0 && "Unknown integer setcc!");
2686 case ISD::SETEQ: // X == Y -> (X^Y)^1
2687 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2688 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2689 WorkList.push_back(Temp.Val);
2691 case ISD::SETNE: // X != Y --> (X^Y)
2692 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2694 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
2695 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
2696 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2697 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2698 WorkList.push_back(Temp.Val);
2700 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
2701 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
2702 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2703 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2704 WorkList.push_back(Temp.Val);
2706 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
2707 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
2708 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2709 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2710 WorkList.push_back(Temp.Val);
2712 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
2713 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
2714 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2715 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2718 if (VT != MVT::i1) {
2719 WorkList.push_back(N0.Val);
2720 // FIXME: If running after legalize, we probably can't do this.
2721 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2726 // Could not fold it.
2730 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2731 /// return a DAG expression to select that will generate the same value by
2732 /// multiplying by a magic number. See:
2733 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2734 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
2735 MVT::ValueType VT = N->getValueType(0);
2737 // Check to see if we can do this.
2738 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2739 return SDOperand(); // BuildSDIV only operates on i32 or i64
2740 if (!TLI.isOperationLegal(ISD::MULHS, VT))
2741 return SDOperand(); // Make sure the target supports MULHS.
2743 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
2744 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
2746 // Multiply the numerator (operand 0) by the magic value
2747 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
2748 DAG.getConstant(magics.m, VT));
2749 // If d > 0 and m < 0, add the numerator
2750 if (d > 0 && magics.m < 0) {
2751 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
2752 WorkList.push_back(Q.Val);
2754 // If d < 0 and m > 0, subtract the numerator.
2755 if (d < 0 && magics.m > 0) {
2756 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
2757 WorkList.push_back(Q.Val);
2759 // Shift right algebraic if shift value is nonzero
2761 Q = DAG.getNode(ISD::SRA, VT, Q,
2762 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2763 WorkList.push_back(Q.Val);
2765 // Extract the sign bit and add it to the quotient
2767 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
2768 TLI.getShiftAmountTy()));
2769 WorkList.push_back(T.Val);
2770 return DAG.getNode(ISD::ADD, VT, Q, T);
2773 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2774 /// return a DAG expression to select that will generate the same value by
2775 /// multiplying by a magic number. See:
2776 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2777 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
2778 MVT::ValueType VT = N->getValueType(0);
2780 // Check to see if we can do this.
2781 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2782 return SDOperand(); // BuildUDIV only operates on i32 or i64
2783 if (!TLI.isOperationLegal(ISD::MULHU, VT))
2784 return SDOperand(); // Make sure the target supports MULHU.
2786 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
2787 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
2789 // Multiply the numerator (operand 0) by the magic value
2790 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
2791 DAG.getConstant(magics.m, VT));
2792 WorkList.push_back(Q.Val);
2794 if (magics.a == 0) {
2795 return DAG.getNode(ISD::SRL, VT, Q,
2796 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2798 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
2799 WorkList.push_back(NPQ.Val);
2800 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
2801 DAG.getConstant(1, TLI.getShiftAmountTy()));
2802 WorkList.push_back(NPQ.Val);
2803 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
2804 WorkList.push_back(NPQ.Val);
2805 return DAG.getNode(ISD::SRL, VT, NPQ,
2806 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
2810 // SelectionDAG::Combine - This is the entry point for the file.
2812 void SelectionDAG::Combine(bool RunningAfterLegalize) {
2813 /// run - This is the main entry point to this class.
2815 DAGCombiner(*this).Run(RunningAfterLegalize);