1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/Analysis/AliasAnalysis.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetFrameInfo.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
41 STATISTIC(NodesCombined , "Number of dag nodes combined");
42 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
43 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
44 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
48 CombinerAA("combiner-alias-analysis", cl::Hidden,
49 cl::desc("Turn on alias analysis during testing"));
52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
53 cl::desc("Include global information in alias analysis"));
55 //------------------------------ DAGCombiner ---------------------------------//
57 class VISIBILITY_HIDDEN DAGCombiner {
59 const TargetLowering &TLI;
61 CodeGenOpt::Level OptLevel;
65 // Worklist of all of the nodes that need to be simplified.
66 std::vector<SDNode*> WorkList;
68 // AA - Used for DAG load/store alias analysis.
71 /// AddUsersToWorkList - When an instruction is simplified, add all users of
72 /// the instruction to the work lists because they might get more simplified
75 void AddUsersToWorkList(SDNode *N) {
76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
81 /// visit - call the node-specific routine that knows how to fold each
82 /// particular type of node.
83 SDValue visit(SDNode *N);
86 /// AddToWorkList - Add to the work list making sure it's instance is at the
87 /// the back (next to be processed.)
88 void AddToWorkList(SDNode *N) {
89 removeFromWorkList(N);
90 WorkList.push_back(N);
93 /// removeFromWorkList - remove all instances of N from the worklist.
95 void removeFromWorkList(SDNode *N) {
96 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
100 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
103 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
104 return CombineTo(N, &Res, 1, AddTo);
107 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
109 SDValue To[] = { Res0, Res1 };
110 return CombineTo(N, To, 2, AddTo);
113 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
117 /// SimplifyDemandedBits - Check the specified integer node value to see if
118 /// it can be simplified or if things it uses can be simplified by bit
119 /// propagation. If so, return true.
120 bool SimplifyDemandedBits(SDValue Op) {
121 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits());
122 return SimplifyDemandedBits(Op, Demanded);
125 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
127 bool CombineToPreIndexedLoadStore(SDNode *N);
128 bool CombineToPostIndexedLoadStore(SDNode *N);
131 /// combine - call the node-specific routine that knows how to fold each
132 /// particular type of node. If that doesn't do anything, try the
133 /// target-specific DAG combines.
134 SDValue combine(SDNode *N);
136 // Visitation implementation - Implement dag node combining for different
137 // node types. The semantics are as follows:
139 // SDValue.getNode() == 0 - No change was made
140 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
141 // otherwise - N should be replaced by the returned Operand.
143 SDValue visitTokenFactor(SDNode *N);
144 SDValue visitMERGE_VALUES(SDNode *N);
145 SDValue visitADD(SDNode *N);
146 SDValue visitSUB(SDNode *N);
147 SDValue visitADDC(SDNode *N);
148 SDValue visitADDE(SDNode *N);
149 SDValue visitMUL(SDNode *N);
150 SDValue visitSDIV(SDNode *N);
151 SDValue visitUDIV(SDNode *N);
152 SDValue visitSREM(SDNode *N);
153 SDValue visitUREM(SDNode *N);
154 SDValue visitMULHU(SDNode *N);
155 SDValue visitMULHS(SDNode *N);
156 SDValue visitSMUL_LOHI(SDNode *N);
157 SDValue visitUMUL_LOHI(SDNode *N);
158 SDValue visitSDIVREM(SDNode *N);
159 SDValue visitUDIVREM(SDNode *N);
160 SDValue visitAND(SDNode *N);
161 SDValue visitOR(SDNode *N);
162 SDValue visitXOR(SDNode *N);
163 SDValue SimplifyVBinOp(SDNode *N);
164 SDValue visitSHL(SDNode *N);
165 SDValue visitSRA(SDNode *N);
166 SDValue visitSRL(SDNode *N);
167 SDValue visitCTLZ(SDNode *N);
168 SDValue visitCTTZ(SDNode *N);
169 SDValue visitCTPOP(SDNode *N);
170 SDValue visitSELECT(SDNode *N);
171 SDValue visitSELECT_CC(SDNode *N);
172 SDValue visitSETCC(SDNode *N);
173 SDValue visitSIGN_EXTEND(SDNode *N);
174 SDValue visitZERO_EXTEND(SDNode *N);
175 SDValue visitANY_EXTEND(SDNode *N);
176 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
177 SDValue visitTRUNCATE(SDNode *N);
178 SDValue visitBIT_CONVERT(SDNode *N);
179 SDValue visitBUILD_PAIR(SDNode *N);
180 SDValue visitFADD(SDNode *N);
181 SDValue visitFSUB(SDNode *N);
182 SDValue visitFMUL(SDNode *N);
183 SDValue visitFDIV(SDNode *N);
184 SDValue visitFREM(SDNode *N);
185 SDValue visitFCOPYSIGN(SDNode *N);
186 SDValue visitSINT_TO_FP(SDNode *N);
187 SDValue visitUINT_TO_FP(SDNode *N);
188 SDValue visitFP_TO_SINT(SDNode *N);
189 SDValue visitFP_TO_UINT(SDNode *N);
190 SDValue visitFP_ROUND(SDNode *N);
191 SDValue visitFP_ROUND_INREG(SDNode *N);
192 SDValue visitFP_EXTEND(SDNode *N);
193 SDValue visitFNEG(SDNode *N);
194 SDValue visitFABS(SDNode *N);
195 SDValue visitBRCOND(SDNode *N);
196 SDValue visitBR_CC(SDNode *N);
197 SDValue visitLOAD(SDNode *N);
198 SDValue visitSTORE(SDNode *N);
199 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
200 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
201 SDValue visitBUILD_VECTOR(SDNode *N);
202 SDValue visitCONCAT_VECTORS(SDNode *N);
203 SDValue visitVECTOR_SHUFFLE(SDNode *N);
205 SDValue XformToShuffleWithZero(SDNode *N);
206 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
208 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
210 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
211 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
212 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
213 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
214 SDValue N3, ISD::CondCode CC,
215 bool NotExtCompare = false);
216 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
217 DebugLoc DL, bool foldBooleans = true);
218 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
220 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
221 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
222 SDValue BuildSDIV(SDNode *N);
223 SDValue BuildUDIV(SDNode *N);
224 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
225 SDValue ReduceLoadWidth(SDNode *N);
226 SDValue ReduceLoadOpStoreWidth(SDNode *N);
228 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
230 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
231 /// looking for aliasing nodes and adding them to the Aliases vector.
232 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
233 SmallVector<SDValue, 8> &Aliases);
235 /// isAlias - Return true if there is any possibility that the two addresses
237 bool isAlias(SDValue Ptr1, int64_t Size1,
238 const Value *SrcValue1, int SrcValueOffset1,
239 SDValue Ptr2, int64_t Size2,
240 const Value *SrcValue2, int SrcValueOffset2) const;
242 /// FindAliasInfo - Extracts the relevant alias information from the memory
243 /// node. Returns true if the operand was a load.
244 bool FindAliasInfo(SDNode *N,
245 SDValue &Ptr, int64_t &Size,
246 const Value *&SrcValue, int &SrcValueOffset) const;
248 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
249 /// looking for a better chain (aliasing node.)
250 SDValue FindBetterChain(SDNode *N, SDValue Chain);
252 /// getShiftAmountTy - Returns a type large enough to hold any valid
253 /// shift amount - before type legalization these can be huge.
254 MVT getShiftAmountTy() {
255 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
259 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
261 TLI(D.getTargetLoweringInfo()),
264 LegalOperations(false),
268 /// Run - runs the dag combiner on all nodes in the work list
269 void Run(CombineLevel AtLevel);
275 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
276 /// nodes from the worklist.
277 class VISIBILITY_HIDDEN WorkListRemover :
278 public SelectionDAG::DAGUpdateListener {
281 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
283 virtual void NodeDeleted(SDNode *N, SDNode *E) {
284 DC.removeFromWorkList(N);
287 virtual void NodeUpdated(SDNode *N) {
293 //===----------------------------------------------------------------------===//
294 // TargetLowering::DAGCombinerInfo implementation
295 //===----------------------------------------------------------------------===//
297 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
298 ((DAGCombiner*)DC)->AddToWorkList(N);
301 SDValue TargetLowering::DAGCombinerInfo::
302 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
303 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
306 SDValue TargetLowering::DAGCombinerInfo::
307 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
308 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
312 SDValue TargetLowering::DAGCombinerInfo::
313 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
314 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
317 void TargetLowering::DAGCombinerInfo::
318 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
319 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
322 //===----------------------------------------------------------------------===//
324 //===----------------------------------------------------------------------===//
326 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
327 /// specified expression for the same cost as the expression itself, or 2 if we
328 /// can compute the negated form more cheaply than the expression itself.
329 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
330 unsigned Depth = 0) {
331 // No compile time optimizations on this type.
332 if (Op.getValueType() == MVT::ppcf128)
335 // fneg is removable even if it has multiple uses.
336 if (Op.getOpcode() == ISD::FNEG) return 2;
338 // Don't allow anything with multiple uses.
339 if (!Op.hasOneUse()) return 0;
341 // Don't recurse exponentially.
342 if (Depth > 6) return 0;
344 switch (Op.getOpcode()) {
345 default: return false;
346 case ISD::ConstantFP:
347 // Don't invert constant FP values after legalize. The negated constant
348 // isn't necessarily legal.
349 return LegalOperations ? 0 : 1;
351 // FIXME: determine better conditions for this xform.
352 if (!UnsafeFPMath) return 0;
354 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
355 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
357 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
358 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
360 // We can't turn -(A-B) into B-A when we honor signed zeros.
361 if (!UnsafeFPMath) return 0;
363 // fold (fneg (fsub A, B)) -> (fsub B, A)
368 if (HonorSignDependentRoundingFPMath()) return 0;
370 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
371 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
374 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
379 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
383 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
384 /// returns the newly negated expression.
385 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
386 bool LegalOperations, unsigned Depth = 0) {
387 // fneg is removable even if it has multiple uses.
388 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
390 // Don't allow anything with multiple uses.
391 assert(Op.hasOneUse() && "Unknown reuse!");
393 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
394 switch (Op.getOpcode()) {
395 default: assert(0 && "Unknown code");
396 case ISD::ConstantFP: {
397 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
399 return DAG.getConstantFP(V, Op.getValueType());
402 // FIXME: determine better conditions for this xform.
403 assert(UnsafeFPMath);
405 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
406 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
407 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
408 GetNegatedExpression(Op.getOperand(0), DAG,
409 LegalOperations, Depth+1),
411 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
412 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
413 GetNegatedExpression(Op.getOperand(1), DAG,
414 LegalOperations, Depth+1),
417 // We can't turn -(A-B) into B-A when we honor signed zeros.
418 assert(UnsafeFPMath);
420 // fold (fneg (fsub 0, B)) -> B
421 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
422 if (N0CFP->getValueAPF().isZero())
423 return Op.getOperand(1);
425 // fold (fneg (fsub A, B)) -> (fsub B, A)
426 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
427 Op.getOperand(1), Op.getOperand(0));
431 assert(!HonorSignDependentRoundingFPMath());
433 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
434 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
435 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
436 GetNegatedExpression(Op.getOperand(0), DAG,
437 LegalOperations, Depth+1),
440 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
441 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
443 GetNegatedExpression(Op.getOperand(1), DAG,
444 LegalOperations, Depth+1));
448 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
449 GetNegatedExpression(Op.getOperand(0), DAG,
450 LegalOperations, Depth+1));
452 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
453 GetNegatedExpression(Op.getOperand(0), DAG,
454 LegalOperations, Depth+1),
460 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
461 // that selects between the values 1 and 0, making it equivalent to a setcc.
462 // Also, set the incoming LHS, RHS, and CC references to the appropriate
463 // nodes based on the type of node we are checking. This simplifies life a
464 // bit for the callers.
465 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
467 if (N.getOpcode() == ISD::SETCC) {
468 LHS = N.getOperand(0);
469 RHS = N.getOperand(1);
470 CC = N.getOperand(2);
473 if (N.getOpcode() == ISD::SELECT_CC &&
474 N.getOperand(2).getOpcode() == ISD::Constant &&
475 N.getOperand(3).getOpcode() == ISD::Constant &&
476 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
477 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
478 LHS = N.getOperand(0);
479 RHS = N.getOperand(1);
480 CC = N.getOperand(4);
486 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
487 // one use. If this is true, it allows the users to invert the operation for
488 // free when it is profitable to do so.
489 static bool isOneUseSetCC(SDValue N) {
491 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
496 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
497 SDValue N0, SDValue N1) {
498 MVT VT = N0.getValueType();
499 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
500 if (isa<ConstantSDNode>(N1)) {
501 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
503 DAG.FoldConstantArithmetic(Opc, VT,
504 cast<ConstantSDNode>(N0.getOperand(1)),
505 cast<ConstantSDNode>(N1));
506 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
507 } else if (N0.hasOneUse()) {
508 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
509 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
510 N0.getOperand(0), N1);
511 AddToWorkList(OpNode.getNode());
512 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
516 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
517 if (isa<ConstantSDNode>(N0)) {
518 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
520 DAG.FoldConstantArithmetic(Opc, VT,
521 cast<ConstantSDNode>(N1.getOperand(1)),
522 cast<ConstantSDNode>(N0));
523 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
524 } else if (N1.hasOneUse()) {
525 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
526 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
527 N1.getOperand(0), N0);
528 AddToWorkList(OpNode.getNode());
529 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
536 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
538 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
540 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
541 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG));
542 DOUT << " and " << NumTo-1 << " other values\n";
543 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i)
544 assert(N->getValueType(i) == To[i].getValueType() &&
545 "Cannot combine value to value of different type!"));
546 WorkListRemover DeadNodes(*this);
547 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
550 // Push the new nodes and any users onto the worklist
551 for (unsigned i = 0, e = NumTo; i != e; ++i) {
552 if (To[i].getNode()) {
553 AddToWorkList(To[i].getNode());
554 AddUsersToWorkList(To[i].getNode());
559 // Finally, if the node is now dead, remove it from the graph. The node
560 // may not be dead if the replacement process recursively simplified to
561 // something else needing this node.
562 if (N->use_empty()) {
563 // Nodes can be reintroduced into the worklist. Make sure we do not
564 // process a node that has been replaced.
565 removeFromWorkList(N);
567 // Finally, since the node is now dead, remove it from the graph.
570 return SDValue(N, 0);
574 DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &
576 // Replace all uses. If any nodes become isomorphic to other nodes and
577 // are deleted, make sure to remove them from our worklist.
578 WorkListRemover DeadNodes(*this);
579 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
581 // Push the new node and any (possibly new) users onto the worklist.
582 AddToWorkList(TLO.New.getNode());
583 AddUsersToWorkList(TLO.New.getNode());
585 // Finally, if the node is now dead, remove it from the graph. The node
586 // may not be dead if the replacement process recursively simplified to
587 // something else needing this node.
588 if (TLO.Old.getNode()->use_empty()) {
589 removeFromWorkList(TLO.Old.getNode());
591 // If the operands of this node are only used by the node, they will now
592 // be dead. Make sure to visit them first to delete dead nodes early.
593 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
594 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
595 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
597 DAG.DeleteNode(TLO.Old.getNode());
601 /// SimplifyDemandedBits - Check the specified integer node value to see if
602 /// it can be simplified or if things it uses can be simplified by bit
603 /// propagation. If so, return true.
604 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
605 TargetLowering::TargetLoweringOpt TLO(DAG);
606 APInt KnownZero, KnownOne;
607 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
611 AddToWorkList(Op.getNode());
613 // Replace the old value with the new one.
615 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
616 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
619 CommitTargetLoweringOpt(TLO);
623 //===----------------------------------------------------------------------===//
624 // Main DAG Combiner implementation
625 //===----------------------------------------------------------------------===//
627 void DAGCombiner::Run(CombineLevel AtLevel) {
628 // set the instance variables, so that the various visit routines may use it.
630 LegalOperations = Level >= NoIllegalOperations;
631 LegalTypes = Level >= NoIllegalTypes;
633 // Add all the dag nodes to the worklist.
634 WorkList.reserve(DAG.allnodes_size());
635 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
636 E = DAG.allnodes_end(); I != E; ++I)
637 WorkList.push_back(I);
639 // Create a dummy node (which is not added to allnodes), that adds a reference
640 // to the root node, preventing it from being deleted, and tracking any
641 // changes of the root.
642 HandleSDNode Dummy(DAG.getRoot());
644 // The root of the dag may dangle to deleted nodes until the dag combiner is
645 // done. Set it to null to avoid confusion.
646 DAG.setRoot(SDValue());
648 // while the worklist isn't empty, inspect the node on the end of it and
649 // try and combine it.
650 while (!WorkList.empty()) {
651 SDNode *N = WorkList.back();
654 // If N has no uses, it is dead. Make sure to revisit all N's operands once
655 // N is deleted from the DAG, since they too may now be dead or may have a
656 // reduced number of uses, allowing other xforms.
657 if (N->use_empty() && N != &Dummy) {
658 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
659 AddToWorkList(N->getOperand(i).getNode());
665 SDValue RV = combine(N);
667 if (RV.getNode() == 0)
672 // If we get back the same node we passed in, rather than a new node or
673 // zero, we know that the node must have defined multiple values and
674 // CombineTo was used. Since CombineTo takes care of the worklist
675 // mechanics for us, we have no work to do in this case.
676 if (RV.getNode() == N)
679 assert(N->getOpcode() != ISD::DELETED_NODE &&
680 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
681 "Node was deleted but visit returned new node!");
683 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
684 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG));
686 WorkListRemover DeadNodes(*this);
687 if (N->getNumValues() == RV.getNode()->getNumValues())
688 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
690 assert(N->getValueType(0) == RV.getValueType() &&
691 N->getNumValues() == 1 && "Type mismatch");
693 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
696 // Push the new node and any users onto the worklist
697 AddToWorkList(RV.getNode());
698 AddUsersToWorkList(RV.getNode());
700 // Add any uses of the old node to the worklist in case this node is the
701 // last one that uses them. They may become dead after this node is
703 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
704 AddToWorkList(N->getOperand(i).getNode());
706 // Finally, if the node is now dead, remove it from the graph. The node
707 // may not be dead if the replacement process recursively simplified to
708 // something else needing this node.
709 if (N->use_empty()) {
710 // Nodes can be reintroduced into the worklist. Make sure we do not
711 // process a node that has been replaced.
712 removeFromWorkList(N);
714 // Finally, since the node is now dead, remove it from the graph.
719 // If the root changed (e.g. it was a dead load, update the root).
720 DAG.setRoot(Dummy.getValue());
723 SDValue DAGCombiner::visit(SDNode *N) {
724 switch(N->getOpcode()) {
726 case ISD::TokenFactor: return visitTokenFactor(N);
727 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
728 case ISD::ADD: return visitADD(N);
729 case ISD::SUB: return visitSUB(N);
730 case ISD::ADDC: return visitADDC(N);
731 case ISD::ADDE: return visitADDE(N);
732 case ISD::MUL: return visitMUL(N);
733 case ISD::SDIV: return visitSDIV(N);
734 case ISD::UDIV: return visitUDIV(N);
735 case ISD::SREM: return visitSREM(N);
736 case ISD::UREM: return visitUREM(N);
737 case ISD::MULHU: return visitMULHU(N);
738 case ISD::MULHS: return visitMULHS(N);
739 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
740 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
741 case ISD::SDIVREM: return visitSDIVREM(N);
742 case ISD::UDIVREM: return visitUDIVREM(N);
743 case ISD::AND: return visitAND(N);
744 case ISD::OR: return visitOR(N);
745 case ISD::XOR: return visitXOR(N);
746 case ISD::SHL: return visitSHL(N);
747 case ISD::SRA: return visitSRA(N);
748 case ISD::SRL: return visitSRL(N);
749 case ISD::CTLZ: return visitCTLZ(N);
750 case ISD::CTTZ: return visitCTTZ(N);
751 case ISD::CTPOP: return visitCTPOP(N);
752 case ISD::SELECT: return visitSELECT(N);
753 case ISD::SELECT_CC: return visitSELECT_CC(N);
754 case ISD::SETCC: return visitSETCC(N);
755 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
756 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
757 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
758 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
759 case ISD::TRUNCATE: return visitTRUNCATE(N);
760 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
761 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
762 case ISD::FADD: return visitFADD(N);
763 case ISD::FSUB: return visitFSUB(N);
764 case ISD::FMUL: return visitFMUL(N);
765 case ISD::FDIV: return visitFDIV(N);
766 case ISD::FREM: return visitFREM(N);
767 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
768 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
769 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
770 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
771 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
772 case ISD::FP_ROUND: return visitFP_ROUND(N);
773 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
774 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
775 case ISD::FNEG: return visitFNEG(N);
776 case ISD::FABS: return visitFABS(N);
777 case ISD::BRCOND: return visitBRCOND(N);
778 case ISD::BR_CC: return visitBR_CC(N);
779 case ISD::LOAD: return visitLOAD(N);
780 case ISD::STORE: return visitSTORE(N);
781 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
782 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
783 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
784 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
785 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
790 SDValue DAGCombiner::combine(SDNode *N) {
791 SDValue RV = visit(N);
793 // If nothing happened, try a target-specific DAG combine.
794 if (RV.getNode() == 0) {
795 assert(N->getOpcode() != ISD::DELETED_NODE &&
796 "Node was deleted but visit returned NULL!");
798 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
799 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
801 // Expose the DAG combiner to the target combiner impls.
802 TargetLowering::DAGCombinerInfo
803 DagCombineInfo(DAG, Level == Unrestricted, false, this);
805 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
809 // If N is a commutative binary node, try commuting it to enable more
811 if (RV.getNode() == 0 &&
812 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
813 N->getNumValues() == 1) {
814 SDValue N0 = N->getOperand(0);
815 SDValue N1 = N->getOperand(1);
817 // Constant operands are canonicalized to RHS.
818 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
819 SDValue Ops[] = { N1, N0 };
820 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
823 return SDValue(CSENode, 0);
830 /// getInputChainForNode - Given a node, return its input chain if it has one,
831 /// otherwise return a null sd operand.
832 static SDValue getInputChainForNode(SDNode *N) {
833 if (unsigned NumOps = N->getNumOperands()) {
834 if (N->getOperand(0).getValueType() == MVT::Other)
835 return N->getOperand(0);
836 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
837 return N->getOperand(NumOps-1);
838 for (unsigned i = 1; i < NumOps-1; ++i)
839 if (N->getOperand(i).getValueType() == MVT::Other)
840 return N->getOperand(i);
845 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
846 // If N has two operands, where one has an input chain equal to the other,
847 // the 'other' chain is redundant.
848 if (N->getNumOperands() == 2) {
849 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
850 return N->getOperand(0);
851 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
852 return N->getOperand(1);
855 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
856 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
857 SmallPtrSet<SDNode*, 16> SeenOps;
858 bool Changed = false; // If we should replace this token factor.
860 // Start out with this token factor.
863 // Iterate through token factors. The TFs grows when new token factors are
865 for (unsigned i = 0; i < TFs.size(); ++i) {
868 // Check each of the operands.
869 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
870 SDValue Op = TF->getOperand(i);
872 switch (Op.getOpcode()) {
873 case ISD::EntryToken:
874 // Entry tokens don't need to be added to the list. They are
879 case ISD::TokenFactor:
880 if ((CombinerAA || Op.hasOneUse()) &&
881 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
882 // Queue up for processing.
883 TFs.push_back(Op.getNode());
884 // Clean up in case the token factor is removed.
885 AddToWorkList(Op.getNode());
892 // Only add if it isn't already in the list.
893 if (SeenOps.insert(Op.getNode()))
904 // If we've change things around then replace token factor.
907 // The entry token is the only possible outcome.
908 Result = DAG.getEntryNode();
910 // New and improved token factor.
911 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
912 MVT::Other, &Ops[0], Ops.size());
915 // Don't add users to work list.
916 return CombineTo(N, Result, false);
922 /// MERGE_VALUES can always be eliminated.
923 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
924 WorkListRemover DeadNodes(*this);
925 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
926 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
928 removeFromWorkList(N);
930 return SDValue(N, 0); // Return N so it doesn't get rechecked!
934 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
936 MVT VT = N0.getValueType();
937 SDValue N00 = N0.getOperand(0);
938 SDValue N01 = N0.getOperand(1);
939 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
941 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
942 isa<ConstantSDNode>(N00.getOperand(1))) {
943 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
944 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
945 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
946 N00.getOperand(0), N01),
947 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
948 N00.getOperand(1), N01));
949 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
955 SDValue DAGCombiner::visitADD(SDNode *N) {
956 SDValue N0 = N->getOperand(0);
957 SDValue N1 = N->getOperand(1);
958 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
959 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
960 MVT VT = N0.getValueType();
964 SDValue FoldedVOp = SimplifyVBinOp(N);
965 if (FoldedVOp.getNode()) return FoldedVOp;
968 // fold (add x, undef) -> undef
969 if (N0.getOpcode() == ISD::UNDEF)
971 if (N1.getOpcode() == ISD::UNDEF)
973 // fold (add c1, c2) -> c1+c2
975 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
976 // canonicalize constant to RHS
978 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
979 // fold (add x, 0) -> x
980 if (N1C && N1C->isNullValue())
982 // fold (add Sym, c) -> Sym+c
983 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
984 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
985 GA->getOpcode() == ISD::GlobalAddress)
986 return DAG.getGlobalAddress(GA->getGlobal(), VT,
988 (uint64_t)N1C->getSExtValue());
989 // fold ((c1-A)+c2) -> (c1+c2)-A
990 if (N1C && N0.getOpcode() == ISD::SUB)
991 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
992 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
993 DAG.getConstant(N1C->getAPIntValue()+
994 N0C->getAPIntValue(), VT),
997 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
998 if (RADD.getNode() != 0)
1000 // fold ((0-A) + B) -> B-A
1001 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1002 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1003 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1004 // fold (A + (0-B)) -> A-B
1005 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1006 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1007 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1008 // fold (A+(B-A)) -> B
1009 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1010 return N1.getOperand(0);
1011 // fold ((B-A)+A) -> B
1012 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1013 return N0.getOperand(0);
1014 // fold (A+(B-(A+C))) to (B-C)
1015 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1016 N0 == N1.getOperand(1).getOperand(0))
1017 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1018 N1.getOperand(1).getOperand(1));
1019 // fold (A+(B-(C+A))) to (B-C)
1020 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1021 N0 == N1.getOperand(1).getOperand(1))
1022 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1023 N1.getOperand(1).getOperand(0));
1024 // fold (A+((B-A)+or-C)) to (B+or-C)
1025 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1026 N1.getOperand(0).getOpcode() == ISD::SUB &&
1027 N0 == N1.getOperand(0).getOperand(1))
1028 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1029 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1031 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1032 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1033 SDValue N00 = N0.getOperand(0);
1034 SDValue N01 = N0.getOperand(1);
1035 SDValue N10 = N1.getOperand(0);
1036 SDValue N11 = N1.getOperand(1);
1038 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1039 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1040 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1041 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1044 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1045 return SDValue(N, 0);
1047 // fold (a+b) -> (a|b) iff a and b share no bits.
1048 if (VT.isInteger() && !VT.isVector()) {
1049 APInt LHSZero, LHSOne;
1050 APInt RHSZero, RHSOne;
1051 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1052 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1054 if (LHSZero.getBoolValue()) {
1055 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1057 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1058 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1059 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1060 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1061 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1065 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1066 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1067 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1068 if (Result.getNode()) return Result;
1070 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1071 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1072 if (Result.getNode()) return Result;
1078 SDValue DAGCombiner::visitADDC(SDNode *N) {
1079 SDValue N0 = N->getOperand(0);
1080 SDValue N1 = N->getOperand(1);
1081 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1082 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1083 MVT VT = N0.getValueType();
1085 // If the flag result is dead, turn this into an ADD.
1086 if (N->hasNUsesOfValue(0, 1))
1087 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1088 DAG.getNode(ISD::CARRY_FALSE,
1089 N->getDebugLoc(), MVT::Flag));
1091 // canonicalize constant to RHS.
1093 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1095 // fold (addc x, 0) -> x + no carry out
1096 if (N1C && N1C->isNullValue())
1097 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1098 N->getDebugLoc(), MVT::Flag));
1100 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1101 APInt LHSZero, LHSOne;
1102 APInt RHSZero, RHSOne;
1103 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1104 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1106 if (LHSZero.getBoolValue()) {
1107 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1109 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1110 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1111 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1112 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1113 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1114 DAG.getNode(ISD::CARRY_FALSE,
1115 N->getDebugLoc(), MVT::Flag));
1121 SDValue DAGCombiner::visitADDE(SDNode *N) {
1122 SDValue N0 = N->getOperand(0);
1123 SDValue N1 = N->getOperand(1);
1124 SDValue CarryIn = N->getOperand(2);
1125 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1126 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1128 // canonicalize constant to RHS
1130 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1133 // fold (adde x, y, false) -> (addc x, y)
1134 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1135 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1140 SDValue DAGCombiner::visitSUB(SDNode *N) {
1141 SDValue N0 = N->getOperand(0);
1142 SDValue N1 = N->getOperand(1);
1143 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1144 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1145 MVT VT = N0.getValueType();
1148 if (VT.isVector()) {
1149 SDValue FoldedVOp = SimplifyVBinOp(N);
1150 if (FoldedVOp.getNode()) return FoldedVOp;
1153 // fold (sub x, x) -> 0
1155 return DAG.getConstant(0, N->getValueType(0));
1156 // fold (sub c1, c2) -> c1-c2
1158 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1159 // fold (sub x, c) -> (add x, -c)
1161 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1162 DAG.getConstant(-N1C->getAPIntValue(), VT));
1163 // fold (A+B)-A -> B
1164 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1165 return N0.getOperand(1);
1166 // fold (A+B)-B -> A
1167 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1168 return N0.getOperand(0);
1169 // fold ((A+(B+or-C))-B) -> A+or-C
1170 if (N0.getOpcode() == ISD::ADD &&
1171 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1172 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1173 N0.getOperand(1).getOperand(0) == N1)
1174 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1175 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1176 // fold ((A+(C+B))-B) -> A+C
1177 if (N0.getOpcode() == ISD::ADD &&
1178 N0.getOperand(1).getOpcode() == ISD::ADD &&
1179 N0.getOperand(1).getOperand(1) == N1)
1180 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1181 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1182 // fold ((A-(B-C))-C) -> A-B
1183 if (N0.getOpcode() == ISD::SUB &&
1184 N0.getOperand(1).getOpcode() == ISD::SUB &&
1185 N0.getOperand(1).getOperand(1) == N1)
1186 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1187 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1189 // If either operand of a sub is undef, the result is undef
1190 if (N0.getOpcode() == ISD::UNDEF)
1192 if (N1.getOpcode() == ISD::UNDEF)
1195 // If the relocation model supports it, consider symbol offsets.
1196 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1197 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1198 // fold (sub Sym, c) -> Sym-c
1199 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1200 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1202 (uint64_t)N1C->getSExtValue());
1203 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1204 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1205 if (GA->getGlobal() == GB->getGlobal())
1206 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1213 SDValue DAGCombiner::visitMUL(SDNode *N) {
1214 SDValue N0 = N->getOperand(0);
1215 SDValue N1 = N->getOperand(1);
1216 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1217 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1218 MVT VT = N0.getValueType();
1221 if (VT.isVector()) {
1222 SDValue FoldedVOp = SimplifyVBinOp(N);
1223 if (FoldedVOp.getNode()) return FoldedVOp;
1226 // fold (mul x, undef) -> 0
1227 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1228 return DAG.getConstant(0, VT);
1229 // fold (mul c1, c2) -> c1*c2
1231 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1232 // canonicalize constant to RHS
1234 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1235 // fold (mul x, 0) -> 0
1236 if (N1C && N1C->isNullValue())
1238 // fold (mul x, -1) -> 0-x
1239 if (N1C && N1C->isAllOnesValue())
1240 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1241 DAG.getConstant(0, VT), N0);
1242 // fold (mul x, (1 << c)) -> x << c
1243 if (N1C && N1C->getAPIntValue().isPowerOf2())
1244 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1245 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1246 getShiftAmountTy()));
1247 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1248 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1249 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1250 // FIXME: If the input is something that is easily negated (e.g. a
1251 // single-use add), we should put the negate there.
1252 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1253 DAG.getConstant(0, VT),
1254 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1255 DAG.getConstant(Log2Val, getShiftAmountTy())));
1257 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1258 if (N1C && N0.getOpcode() == ISD::SHL &&
1259 isa<ConstantSDNode>(N0.getOperand(1))) {
1260 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1261 N1, N0.getOperand(1));
1262 AddToWorkList(C3.getNode());
1263 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1264 N0.getOperand(0), C3);
1267 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1270 SDValue Sh(0,0), Y(0,0);
1271 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1272 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1273 N0.getNode()->hasOneUse()) {
1275 } else if (N1.getOpcode() == ISD::SHL &&
1276 isa<ConstantSDNode>(N1.getOperand(1)) &&
1277 N1.getNode()->hasOneUse()) {
1282 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1283 Sh.getOperand(0), Y);
1284 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1285 Mul, Sh.getOperand(1));
1289 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1290 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1291 isa<ConstantSDNode>(N0.getOperand(1)))
1292 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1293 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1294 N0.getOperand(0), N1),
1295 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1296 N0.getOperand(1), N1));
1299 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1300 if (RMUL.getNode() != 0)
1306 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1307 SDValue N0 = N->getOperand(0);
1308 SDValue N1 = N->getOperand(1);
1309 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1310 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1311 MVT VT = N->getValueType(0);
1314 if (VT.isVector()) {
1315 SDValue FoldedVOp = SimplifyVBinOp(N);
1316 if (FoldedVOp.getNode()) return FoldedVOp;
1319 // fold (sdiv c1, c2) -> c1/c2
1320 if (N0C && N1C && !N1C->isNullValue())
1321 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1322 // fold (sdiv X, 1) -> X
1323 if (N1C && N1C->getSExtValue() == 1LL)
1325 // fold (sdiv X, -1) -> 0-X
1326 if (N1C && N1C->isAllOnesValue())
1327 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1328 DAG.getConstant(0, VT), N0);
1329 // If we know the sign bits of both operands are zero, strength reduce to a
1330 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1331 if (!VT.isVector()) {
1332 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1333 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1336 // fold (sdiv X, pow2) -> simple ops after legalize
1337 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1338 (isPowerOf2_64(N1C->getSExtValue()) ||
1339 isPowerOf2_64(-N1C->getSExtValue()))) {
1340 // If dividing by powers of two is cheap, then don't perform the following
1342 if (TLI.isPow2DivCheap())
1345 int64_t pow2 = N1C->getSExtValue();
1346 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1347 unsigned lg2 = Log2_64(abs2);
1349 // Splat the sign bit into the register
1350 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1351 DAG.getConstant(VT.getSizeInBits()-1,
1352 getShiftAmountTy()));
1353 AddToWorkList(SGN.getNode());
1355 // Add (N0 < 0) ? abs2 - 1 : 0;
1356 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1357 DAG.getConstant(VT.getSizeInBits() - lg2,
1358 getShiftAmountTy()));
1359 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1360 AddToWorkList(SRL.getNode());
1361 AddToWorkList(ADD.getNode()); // Divide by pow2
1362 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1363 DAG.getConstant(lg2, getShiftAmountTy()));
1365 // If we're dividing by a positive value, we're done. Otherwise, we must
1366 // negate the result.
1370 AddToWorkList(SRA.getNode());
1371 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1372 DAG.getConstant(0, VT), SRA);
1375 // if integer divide is expensive and we satisfy the requirements, emit an
1376 // alternate sequence.
1377 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1378 !TLI.isIntDivCheap()) {
1379 SDValue Op = BuildSDIV(N);
1380 if (Op.getNode()) return Op;
1384 if (N0.getOpcode() == ISD::UNDEF)
1385 return DAG.getConstant(0, VT);
1386 // X / undef -> undef
1387 if (N1.getOpcode() == ISD::UNDEF)
1393 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1394 SDValue N0 = N->getOperand(0);
1395 SDValue N1 = N->getOperand(1);
1396 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1397 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1398 MVT VT = N->getValueType(0);
1401 if (VT.isVector()) {
1402 SDValue FoldedVOp = SimplifyVBinOp(N);
1403 if (FoldedVOp.getNode()) return FoldedVOp;
1406 // fold (udiv c1, c2) -> c1/c2
1407 if (N0C && N1C && !N1C->isNullValue())
1408 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1409 // fold (udiv x, (1 << c)) -> x >>u c
1410 if (N1C && N1C->getAPIntValue().isPowerOf2())
1411 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1412 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1413 getShiftAmountTy()));
1414 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1415 if (N1.getOpcode() == ISD::SHL) {
1416 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1417 if (SHC->getAPIntValue().isPowerOf2()) {
1418 MVT ADDVT = N1.getOperand(1).getValueType();
1419 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1421 DAG.getConstant(SHC->getAPIntValue()
1424 AddToWorkList(Add.getNode());
1425 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1429 // fold (udiv x, c) -> alternate
1430 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1431 SDValue Op = BuildUDIV(N);
1432 if (Op.getNode()) return Op;
1436 if (N0.getOpcode() == ISD::UNDEF)
1437 return DAG.getConstant(0, VT);
1438 // X / undef -> undef
1439 if (N1.getOpcode() == ISD::UNDEF)
1445 SDValue DAGCombiner::visitSREM(SDNode *N) {
1446 SDValue N0 = N->getOperand(0);
1447 SDValue N1 = N->getOperand(1);
1448 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1449 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1450 MVT VT = N->getValueType(0);
1452 // fold (srem c1, c2) -> c1%c2
1453 if (N0C && N1C && !N1C->isNullValue())
1454 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1455 // If we know the sign bits of both operands are zero, strength reduce to a
1456 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1457 if (!VT.isVector()) {
1458 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1459 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1462 // If X/C can be simplified by the division-by-constant logic, lower
1463 // X%C to the equivalent of X-X/C*C.
1464 if (N1C && !N1C->isNullValue()) {
1465 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1466 AddToWorkList(Div.getNode());
1467 SDValue OptimizedDiv = combine(Div.getNode());
1468 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1469 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1471 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1472 AddToWorkList(Mul.getNode());
1478 if (N0.getOpcode() == ISD::UNDEF)
1479 return DAG.getConstant(0, VT);
1480 // X % undef -> undef
1481 if (N1.getOpcode() == ISD::UNDEF)
1487 SDValue DAGCombiner::visitUREM(SDNode *N) {
1488 SDValue N0 = N->getOperand(0);
1489 SDValue N1 = N->getOperand(1);
1490 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1491 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1492 MVT VT = N->getValueType(0);
1494 // fold (urem c1, c2) -> c1%c2
1495 if (N0C && N1C && !N1C->isNullValue())
1496 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1497 // fold (urem x, pow2) -> (and x, pow2-1)
1498 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1499 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1500 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1501 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1502 if (N1.getOpcode() == ISD::SHL) {
1503 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1504 if (SHC->getAPIntValue().isPowerOf2()) {
1506 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1507 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1509 AddToWorkList(Add.getNode());
1510 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1515 // If X/C can be simplified by the division-by-constant logic, lower
1516 // X%C to the equivalent of X-X/C*C.
1517 if (N1C && !N1C->isNullValue()) {
1518 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1519 AddToWorkList(Div.getNode());
1520 SDValue OptimizedDiv = combine(Div.getNode());
1521 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1522 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1524 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1525 AddToWorkList(Mul.getNode());
1531 if (N0.getOpcode() == ISD::UNDEF)
1532 return DAG.getConstant(0, VT);
1533 // X % undef -> undef
1534 if (N1.getOpcode() == ISD::UNDEF)
1540 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1541 SDValue N0 = N->getOperand(0);
1542 SDValue N1 = N->getOperand(1);
1543 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1544 MVT VT = N->getValueType(0);
1546 // fold (mulhs x, 0) -> 0
1547 if (N1C && N1C->isNullValue())
1549 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1550 if (N1C && N1C->getAPIntValue() == 1)
1551 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1552 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1553 getShiftAmountTy()));
1554 // fold (mulhs x, undef) -> 0
1555 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1556 return DAG.getConstant(0, VT);
1561 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1562 SDValue N0 = N->getOperand(0);
1563 SDValue N1 = N->getOperand(1);
1564 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1565 MVT VT = N->getValueType(0);
1567 // fold (mulhu x, 0) -> 0
1568 if (N1C && N1C->isNullValue())
1570 // fold (mulhu x, 1) -> 0
1571 if (N1C && N1C->getAPIntValue() == 1)
1572 return DAG.getConstant(0, N0.getValueType());
1573 // fold (mulhu x, undef) -> 0
1574 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1575 return DAG.getConstant(0, VT);
1580 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1581 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1582 /// that are being performed. Return true if a simplification was made.
1584 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1586 // If the high half is not needed, just compute the low half.
1587 bool HiExists = N->hasAnyUseOfValue(1);
1589 (!LegalOperations ||
1590 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1591 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1592 N->op_begin(), N->getNumOperands());
1593 return CombineTo(N, Res, Res);
1596 // If the low half is not needed, just compute the high half.
1597 bool LoExists = N->hasAnyUseOfValue(0);
1599 (!LegalOperations ||
1600 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1601 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1602 N->op_begin(), N->getNumOperands());
1603 return CombineTo(N, Res, Res);
1606 // If both halves are used, return as it is.
1607 if (LoExists && HiExists)
1610 // If the two computed results can be simplified separately, separate them.
1612 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1613 N->op_begin(), N->getNumOperands());
1614 AddToWorkList(Lo.getNode());
1615 SDValue LoOpt = combine(Lo.getNode());
1616 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1617 (!LegalOperations ||
1618 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1619 return CombineTo(N, LoOpt, LoOpt);
1623 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1624 N->op_begin(), N->getNumOperands());
1625 AddToWorkList(Hi.getNode());
1626 SDValue HiOpt = combine(Hi.getNode());
1627 if (HiOpt.getNode() && HiOpt != Hi &&
1628 (!LegalOperations ||
1629 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1630 return CombineTo(N, HiOpt, HiOpt);
1636 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1637 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1638 if (Res.getNode()) return Res;
1643 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1644 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1645 if (Res.getNode()) return Res;
1650 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
1651 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1652 if (Res.getNode()) return Res;
1657 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
1658 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1659 if (Res.getNode()) return Res;
1664 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1665 /// two operands of the same opcode, try to simplify it.
1666 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1667 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1668 MVT VT = N0.getValueType();
1669 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1671 // For each of OP in AND/OR/XOR:
1672 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1673 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1674 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1675 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
1676 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1677 N0.getOpcode() == ISD::SIGN_EXTEND ||
1678 (N0.getOpcode() == ISD::TRUNCATE &&
1679 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) &&
1680 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1681 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1682 N0.getOperand(0).getValueType(),
1683 N0.getOperand(0), N1.getOperand(0));
1684 AddToWorkList(ORNode.getNode());
1685 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
1688 // For each of OP in SHL/SRL/SRA/AND...
1689 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1690 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1691 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1692 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1693 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1694 N0.getOperand(1) == N1.getOperand(1)) {
1695 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1696 N0.getOperand(0).getValueType(),
1697 N0.getOperand(0), N1.getOperand(0));
1698 AddToWorkList(ORNode.getNode());
1699 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
1700 ORNode, N0.getOperand(1));
1706 SDValue DAGCombiner::visitAND(SDNode *N) {
1707 SDValue N0 = N->getOperand(0);
1708 SDValue N1 = N->getOperand(1);
1709 SDValue LL, LR, RL, RR, CC0, CC1;
1710 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1711 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1712 MVT VT = N1.getValueType();
1713 unsigned BitWidth = VT.getSizeInBits();
1716 if (VT.isVector()) {
1717 SDValue FoldedVOp = SimplifyVBinOp(N);
1718 if (FoldedVOp.getNode()) return FoldedVOp;
1721 // fold (and x, undef) -> 0
1722 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1723 return DAG.getConstant(0, VT);
1724 // fold (and c1, c2) -> c1&c2
1726 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
1727 // canonicalize constant to RHS
1729 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
1730 // fold (and x, -1) -> x
1731 if (N1C && N1C->isAllOnesValue())
1733 // if (and x, c) is known to be zero, return 0
1734 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
1735 APInt::getAllOnesValue(BitWidth)))
1736 return DAG.getConstant(0, VT);
1738 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
1739 if (RAND.getNode() != 0)
1741 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1742 if (N1C && N0.getOpcode() == ISD::OR)
1743 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1744 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
1746 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1747 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1748 SDValue N0Op0 = N0.getOperand(0);
1749 APInt Mask = ~N1C->getAPIntValue();
1750 Mask.trunc(N0Op0.getValueSizeInBits());
1751 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
1752 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
1753 N0.getValueType(), N0Op0);
1755 // Replace uses of the AND with uses of the Zero extend node.
1758 // We actually want to replace all uses of the any_extend with the
1759 // zero_extend, to avoid duplicating things. This will later cause this
1760 // AND to be folded.
1761 CombineTo(N0.getNode(), Zext);
1762 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1765 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1766 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1767 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1768 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1770 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1771 LL.getValueType().isInteger()) {
1772 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
1773 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
1774 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1775 LR.getValueType(), LL, RL);
1776 AddToWorkList(ORNode.getNode());
1777 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1779 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
1780 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1781 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
1782 LR.getValueType(), LL, RL);
1783 AddToWorkList(ANDNode.getNode());
1784 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1786 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
1787 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1788 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1789 LR.getValueType(), LL, RL);
1790 AddToWorkList(ORNode.getNode());
1791 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1794 // canonicalize equivalent to ll == rl
1795 if (LL == RR && LR == RL) {
1796 Op1 = ISD::getSetCCSwappedOperands(Op1);
1799 if (LL == RL && LR == RR) {
1800 bool isInteger = LL.getValueType().isInteger();
1801 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1802 if (Result != ISD::SETCC_INVALID &&
1803 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
1804 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
1809 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
1810 if (N0.getOpcode() == N1.getOpcode()) {
1811 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1812 if (Tmp.getNode()) return Tmp;
1815 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1816 // fold (and (sra)) -> (and (srl)) when possible.
1817 if (!VT.isVector() &&
1818 SimplifyDemandedBits(SDValue(N, 0)))
1819 return SDValue(N, 0);
1820 // fold (zext_inreg (extload x)) -> (zextload x)
1821 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
1822 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1823 MVT EVT = LN0->getMemoryVT();
1824 // If we zero all the possible extended bits, then we can turn this into
1825 // a zextload if we are running before legalize or the operation is legal.
1826 unsigned BitWidth = N1.getValueSizeInBits();
1827 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1828 BitWidth - EVT.getSizeInBits())) &&
1829 ((!LegalOperations && !LN0->isVolatile()) ||
1830 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1831 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1832 LN0->getChain(), LN0->getBasePtr(),
1834 LN0->getSrcValueOffset(), EVT,
1835 LN0->isVolatile(), LN0->getAlignment());
1837 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1838 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1841 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1842 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
1844 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1845 MVT EVT = LN0->getMemoryVT();
1846 // If we zero all the possible extended bits, then we can turn this into
1847 // a zextload if we are running before legalize or the operation is legal.
1848 unsigned BitWidth = N1.getValueSizeInBits();
1849 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1850 BitWidth - EVT.getSizeInBits())) &&
1851 ((!LegalOperations && !LN0->isVolatile()) ||
1852 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1853 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1855 LN0->getBasePtr(), LN0->getSrcValue(),
1856 LN0->getSrcValueOffset(), EVT,
1857 LN0->isVolatile(), LN0->getAlignment());
1859 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1860 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1864 // fold (and (load x), 255) -> (zextload x, i8)
1865 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1866 if (N1C && N0.getOpcode() == ISD::LOAD) {
1867 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1868 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1869 LN0->isUnindexed() && N0.hasOneUse() &&
1870 // Do not change the width of a volatile load.
1871 !LN0->isVolatile()) {
1872 MVT EVT = MVT::Other;
1873 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
1874 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
1875 EVT = MVT::getIntegerVT(ActiveBits);
1877 MVT LoadedVT = LN0->getMemoryVT();
1879 // Do not generate loads of non-round integer types since these can
1880 // be expensive (and would be wrong if the type is not byte sized).
1881 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() &&
1882 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1883 MVT PtrType = N0.getOperand(1).getValueType();
1885 // For big endian targets, we need to add an offset to the pointer to
1886 // load the correct bytes. For little endian systems, we merely need to
1887 // read fewer bytes from the same pointer.
1888 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
1889 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
1890 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1891 unsigned Alignment = LN0->getAlignment();
1892 SDValue NewPtr = LN0->getBasePtr();
1894 if (TLI.isBigEndian()) {
1895 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
1896 NewPtr, DAG.getConstant(PtrOff, PtrType));
1897 Alignment = MinAlign(Alignment, PtrOff);
1900 AddToWorkList(NewPtr.getNode());
1902 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(),
1903 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(),
1904 EVT, LN0->isVolatile(), Alignment);
1906 CombineTo(N0.getNode(), Load, Load.getValue(1));
1907 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1915 SDValue DAGCombiner::visitOR(SDNode *N) {
1916 SDValue N0 = N->getOperand(0);
1917 SDValue N1 = N->getOperand(1);
1918 SDValue LL, LR, RL, RR, CC0, CC1;
1919 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1920 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1921 MVT VT = N1.getValueType();
1924 if (VT.isVector()) {
1925 SDValue FoldedVOp = SimplifyVBinOp(N);
1926 if (FoldedVOp.getNode()) return FoldedVOp;
1929 // fold (or x, undef) -> -1
1930 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1931 return DAG.getConstant(~0ULL, VT);
1932 // fold (or c1, c2) -> c1|c2
1934 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
1935 // canonicalize constant to RHS
1937 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
1938 // fold (or x, 0) -> x
1939 if (N1C && N1C->isNullValue())
1941 // fold (or x, -1) -> -1
1942 if (N1C && N1C->isAllOnesValue())
1944 // fold (or x, c) -> c iff (x & ~c) == 0
1945 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
1948 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
1949 if (ROR.getNode() != 0)
1951 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1952 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
1953 isa<ConstantSDNode>(N0.getOperand(1))) {
1954 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1955 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
1956 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
1957 N0.getOperand(0), N1),
1958 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
1960 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1961 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1962 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1963 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1965 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1966 LL.getValueType().isInteger()) {
1967 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
1968 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
1969 if (cast<ConstantSDNode>(LR)->isNullValue() &&
1970 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1971 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
1972 LR.getValueType(), LL, RL);
1973 AddToWorkList(ORNode.getNode());
1974 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1976 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
1977 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
1978 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1979 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1980 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
1981 LR.getValueType(), LL, RL);
1982 AddToWorkList(ANDNode.getNode());
1983 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1986 // canonicalize equivalent to ll == rl
1987 if (LL == RR && LR == RL) {
1988 Op1 = ISD::getSetCCSwappedOperands(Op1);
1991 if (LL == RL && LR == RR) {
1992 bool isInteger = LL.getValueType().isInteger();
1993 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1994 if (Result != ISD::SETCC_INVALID &&
1995 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
1996 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2001 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2002 if (N0.getOpcode() == N1.getOpcode()) {
2003 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2004 if (Tmp.getNode()) return Tmp;
2007 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2008 if (N0.getOpcode() == ISD::AND &&
2009 N1.getOpcode() == ISD::AND &&
2010 N0.getOperand(1).getOpcode() == ISD::Constant &&
2011 N1.getOperand(1).getOpcode() == ISD::Constant &&
2012 // Don't increase # computations.
2013 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2014 // We can only do this xform if we know that bits from X that are set in C2
2015 // but not in C1 are already zero. Likewise for Y.
2016 const APInt &LHSMask =
2017 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2018 const APInt &RHSMask =
2019 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2021 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2022 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2023 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2024 N0.getOperand(0), N1.getOperand(0));
2025 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2026 DAG.getConstant(LHSMask | RHSMask, VT));
2030 // See if this is some rotate idiom.
2031 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2032 return SDValue(Rot, 0);
2037 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2038 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2039 if (Op.getOpcode() == ISD::AND) {
2040 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2041 Mask = Op.getOperand(1);
2042 Op = Op.getOperand(0);
2048 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2056 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2057 // idioms for rotate, and if the target supports rotation instructions, generate
2059 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2060 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2061 MVT VT = LHS.getValueType();
2062 if (!TLI.isTypeLegal(VT)) return 0;
2064 // The target must have at least one rotate flavor.
2065 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2066 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2067 if (!HasROTL && !HasROTR) return 0;
2069 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2070 SDValue LHSShift; // The shift.
2071 SDValue LHSMask; // AND value if any.
2072 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2073 return 0; // Not part of a rotate.
2075 SDValue RHSShift; // The shift.
2076 SDValue RHSMask; // AND value if any.
2077 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2078 return 0; // Not part of a rotate.
2080 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2081 return 0; // Not shifting the same value.
2083 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2084 return 0; // Shifts must disagree.
2086 // Canonicalize shl to left side in a shl/srl pair.
2087 if (RHSShift.getOpcode() == ISD::SHL) {
2088 std::swap(LHS, RHS);
2089 std::swap(LHSShift, RHSShift);
2090 std::swap(LHSMask , RHSMask );
2093 unsigned OpSizeInBits = VT.getSizeInBits();
2094 SDValue LHSShiftArg = LHSShift.getOperand(0);
2095 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2096 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2098 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2099 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2100 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2101 RHSShiftAmt.getOpcode() == ISD::Constant) {
2102 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2103 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2104 if ((LShVal + RShVal) != OpSizeInBits)
2109 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2111 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2113 // If there is an AND of either shifted operand, apply it to the result.
2114 if (LHSMask.getNode() || RHSMask.getNode()) {
2115 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2117 if (LHSMask.getNode()) {
2118 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2119 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2121 if (RHSMask.getNode()) {
2122 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2123 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2126 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2129 return Rot.getNode();
2132 // If there is a mask here, and we have a variable shift, we can't be sure
2133 // that we're masking out the right stuff.
2134 if (LHSMask.getNode() || RHSMask.getNode())
2137 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2138 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2139 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2140 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2141 if (ConstantSDNode *SUBC =
2142 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2143 if (SUBC->getAPIntValue() == OpSizeInBits) {
2145 return DAG.getNode(ISD::ROTL, DL, VT,
2146 LHSShiftArg, LHSShiftAmt).getNode();
2148 return DAG.getNode(ISD::ROTR, DL, VT,
2149 LHSShiftArg, RHSShiftAmt).getNode();
2154 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2155 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2156 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2157 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2158 if (ConstantSDNode *SUBC =
2159 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2160 if (SUBC->getAPIntValue() == OpSizeInBits) {
2162 return DAG.getNode(ISD::ROTR, DL, VT,
2163 LHSShiftArg, RHSShiftAmt).getNode();
2165 return DAG.getNode(ISD::ROTL, DL, VT,
2166 LHSShiftArg, LHSShiftAmt).getNode();
2171 // Look for sign/zext/any-extended or truncate cases:
2172 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2173 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2174 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2175 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2176 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2177 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2178 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2179 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2180 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2181 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2182 if (RExtOp0.getOpcode() == ISD::SUB &&
2183 RExtOp0.getOperand(1) == LExtOp0) {
2184 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2186 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2187 // (rotr x, (sub 32, y))
2188 if (ConstantSDNode *SUBC =
2189 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2190 if (SUBC->getAPIntValue() == OpSizeInBits) {
2191 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2193 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2196 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2197 RExtOp0 == LExtOp0.getOperand(1)) {
2198 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2200 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2201 // (rotl x, (sub 32, y))
2202 if (ConstantSDNode *SUBC =
2203 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2204 if (SUBC->getAPIntValue() == OpSizeInBits) {
2205 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2207 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2216 SDValue DAGCombiner::visitXOR(SDNode *N) {
2217 SDValue N0 = N->getOperand(0);
2218 SDValue N1 = N->getOperand(1);
2219 SDValue LHS, RHS, CC;
2220 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2221 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2222 MVT VT = N0.getValueType();
2225 if (VT.isVector()) {
2226 SDValue FoldedVOp = SimplifyVBinOp(N);
2227 if (FoldedVOp.getNode()) return FoldedVOp;
2230 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2231 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2232 return DAG.getConstant(0, VT);
2233 // fold (xor x, undef) -> undef
2234 if (N0.getOpcode() == ISD::UNDEF)
2236 if (N1.getOpcode() == ISD::UNDEF)
2238 // fold (xor c1, c2) -> c1^c2
2240 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2241 // canonicalize constant to RHS
2243 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2244 // fold (xor x, 0) -> x
2245 if (N1C && N1C->isNullValue())
2248 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2249 if (RXOR.getNode() != 0)
2252 // fold !(x cc y) -> (x !cc y)
2253 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2254 bool isInt = LHS.getValueType().isInteger();
2255 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2258 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2259 switch (N0.getOpcode()) {
2261 assert(0 && "Unhandled SetCC Equivalent!");
2264 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2265 case ISD::SELECT_CC:
2266 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2267 N0.getOperand(3), NotCC);
2272 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2273 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2274 N0.getNode()->hasOneUse() &&
2275 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2276 SDValue V = N0.getOperand(0);
2277 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2278 DAG.getConstant(1, V.getValueType()));
2279 AddToWorkList(V.getNode());
2280 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2283 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2284 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2285 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2286 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2287 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2288 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2289 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2290 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2291 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2292 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2295 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2296 if (N1C && N1C->isAllOnesValue() &&
2297 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2298 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2299 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2300 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2301 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2302 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2303 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2304 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2307 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2308 if (N1C && N0.getOpcode() == ISD::XOR) {
2309 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2310 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2312 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2313 DAG.getConstant(N1C->getAPIntValue() ^
2314 N00C->getAPIntValue(), VT));
2316 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2317 DAG.getConstant(N1C->getAPIntValue() ^
2318 N01C->getAPIntValue(), VT));
2320 // fold (xor x, x) -> 0
2322 if (!VT.isVector()) {
2323 return DAG.getConstant(0, VT);
2324 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2325 // Produce a vector of zeros.
2326 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2327 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2328 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2329 &Ops[0], Ops.size());
2333 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2334 if (N0.getOpcode() == N1.getOpcode()) {
2335 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2336 if (Tmp.getNode()) return Tmp;
2339 // Simplify the expression using non-local knowledge.
2340 if (!VT.isVector() &&
2341 SimplifyDemandedBits(SDValue(N, 0)))
2342 return SDValue(N, 0);
2347 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2348 /// the shift amount is a constant.
2349 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2350 SDNode *LHS = N->getOperand(0).getNode();
2351 if (!LHS->hasOneUse()) return SDValue();
2353 // We want to pull some binops through shifts, so that we have (and (shift))
2354 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2355 // thing happens with address calculations, so it's important to canonicalize
2357 bool HighBitSet = false; // Can we transform this if the high bit is set?
2359 switch (LHS->getOpcode()) {
2360 default: return SDValue();
2363 HighBitSet = false; // We can only transform sra if the high bit is clear.
2366 HighBitSet = true; // We can only transform sra if the high bit is set.
2369 if (N->getOpcode() != ISD::SHL)
2370 return SDValue(); // only shl(add) not sr[al](add).
2371 HighBitSet = false; // We can only transform sra if the high bit is clear.
2375 // We require the RHS of the binop to be a constant as well.
2376 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2377 if (!BinOpCst) return SDValue();
2379 // FIXME: disable this unless the input to the binop is a shift by a constant.
2380 // If it is not a shift, it pessimizes some common cases like:
2382 // void foo(int *X, int i) { X[i & 1235] = 1; }
2383 // int bar(int *X, int i) { return X[i & 255]; }
2384 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2385 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2386 BinOpLHSVal->getOpcode() != ISD::SRA &&
2387 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2388 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2391 MVT VT = N->getValueType(0);
2393 // If this is a signed shift right, and the high bit is modified by the
2394 // logical operation, do not perform the transformation. The highBitSet
2395 // boolean indicates the value of the high bit of the constant which would
2396 // cause it to be modified for this operation.
2397 if (N->getOpcode() == ISD::SRA) {
2398 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2399 if (BinOpRHSSignSet != HighBitSet)
2403 // Fold the constants, shifting the binop RHS by the shift amount.
2404 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2406 LHS->getOperand(1), N->getOperand(1));
2408 // Create the new shift.
2409 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2410 VT, LHS->getOperand(0), N->getOperand(1));
2412 // Create the new binop.
2413 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2416 SDValue DAGCombiner::visitSHL(SDNode *N) {
2417 SDValue N0 = N->getOperand(0);
2418 SDValue N1 = N->getOperand(1);
2419 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2420 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2421 MVT VT = N0.getValueType();
2422 unsigned OpSizeInBits = VT.getSizeInBits();
2424 // fold (shl c1, c2) -> c1<<c2
2426 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2427 // fold (shl 0, x) -> 0
2428 if (N0C && N0C->isNullValue())
2430 // fold (shl x, c >= size(x)) -> undef
2431 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2432 return DAG.getUNDEF(VT);
2433 // fold (shl x, 0) -> x
2434 if (N1C && N1C->isNullValue())
2436 // if (shl x, c) is known to be zero, return 0
2437 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2438 APInt::getAllOnesValue(VT.getSizeInBits())))
2439 return DAG.getConstant(0, VT);
2440 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2441 if (N1.getOpcode() == ISD::TRUNCATE &&
2442 N1.getOperand(0).getOpcode() == ISD::AND &&
2443 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2444 SDValue N101 = N1.getOperand(0).getOperand(1);
2445 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2446 MVT TruncVT = N1.getValueType();
2447 SDValue N100 = N1.getOperand(0).getOperand(0);
2448 APInt TruncC = N101C->getAPIntValue();
2449 TruncC.trunc(TruncVT.getSizeInBits());
2450 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2451 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2452 DAG.getNode(ISD::TRUNCATE,
2455 DAG.getConstant(TruncC, TruncVT)));
2459 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2460 return SDValue(N, 0);
2462 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2463 if (N1C && N0.getOpcode() == ISD::SHL &&
2464 N0.getOperand(1).getOpcode() == ISD::Constant) {
2465 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2466 uint64_t c2 = N1C->getZExtValue();
2467 if (c1 + c2 > OpSizeInBits)
2468 return DAG.getConstant(0, VT);
2469 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2470 DAG.getConstant(c1 + c2, N1.getValueType()));
2472 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2473 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2474 if (N1C && N0.getOpcode() == ISD::SRL &&
2475 N0.getOperand(1).getOpcode() == ISD::Constant) {
2476 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2477 uint64_t c2 = N1C->getZExtValue();
2478 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0),
2479 DAG.getConstant(~0ULL << c1, VT));
2481 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2482 DAG.getConstant(c2-c1, N1.getValueType()));
2484 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2485 DAG.getConstant(c1-c2, N1.getValueType()));
2487 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2488 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2489 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2490 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT));
2492 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2495 SDValue DAGCombiner::visitSRA(SDNode *N) {
2496 SDValue N0 = N->getOperand(0);
2497 SDValue N1 = N->getOperand(1);
2498 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2499 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2500 MVT VT = N0.getValueType();
2502 // fold (sra c1, c2) -> (sra c1, c2)
2504 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2505 // fold (sra 0, x) -> 0
2506 if (N0C && N0C->isNullValue())
2508 // fold (sra -1, x) -> -1
2509 if (N0C && N0C->isAllOnesValue())
2511 // fold (sra x, (setge c, size(x))) -> undef
2512 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits())
2513 return DAG.getUNDEF(VT);
2514 // fold (sra x, 0) -> x
2515 if (N1C && N1C->isNullValue())
2517 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2519 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2520 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
2521 MVT EVT = MVT::getIntegerVT(LowBits);
2522 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
2523 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2524 N0.getOperand(0), DAG.getValueType(EVT));
2527 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2528 if (N1C && N0.getOpcode() == ISD::SRA) {
2529 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2530 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2531 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
2532 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2533 DAG.getConstant(Sum, N1C->getValueType(0)));
2537 // fold (sra (shl X, m), (sub result_size, n))
2538 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2539 // result_size - n != m.
2540 // If truncate is free for the target sext(shl) is likely to result in better
2542 if (N0.getOpcode() == ISD::SHL) {
2543 // Get the two constanst of the shifts, CN0 = m, CN = n.
2544 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2546 // Determine what the truncate's result bitsize and type would be.
2547 unsigned VTValSize = VT.getSizeInBits();
2549 MVT::getIntegerVT(VTValSize - N1C->getZExtValue());
2550 // Determine the residual right-shift amount.
2551 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2553 // If the shift is not a no-op (in which case this should be just a sign
2554 // extend already), the truncated to type is legal, sign_extend is legal
2555 // on that type, and the the truncate to that type is both legal and free,
2556 // perform the transform.
2557 if ((ShiftAmt > 0) &&
2558 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2559 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
2560 TLI.isTruncateFree(VT, TruncVT)) {
2562 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
2563 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
2564 N0.getOperand(0), Amt);
2565 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
2567 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
2568 N->getValueType(0), Trunc);
2573 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
2574 if (N1.getOpcode() == ISD::TRUNCATE &&
2575 N1.getOperand(0).getOpcode() == ISD::AND &&
2576 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2577 SDValue N101 = N1.getOperand(0).getOperand(1);
2578 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2579 MVT TruncVT = N1.getValueType();
2580 SDValue N100 = N1.getOperand(0).getOperand(0);
2581 APInt TruncC = N101C->getAPIntValue();
2582 TruncC.trunc(TruncVT.getSizeInBits());
2583 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
2584 DAG.getNode(ISD::AND, N->getDebugLoc(),
2586 DAG.getNode(ISD::TRUNCATE,
2589 DAG.getConstant(TruncC, TruncVT)));
2593 // Simplify, based on bits shifted out of the LHS.
2594 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2595 return SDValue(N, 0);
2598 // If the sign bit is known to be zero, switch this to a SRL.
2599 if (DAG.SignBitIsZero(N0))
2600 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
2602 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2605 SDValue DAGCombiner::visitSRL(SDNode *N) {
2606 SDValue N0 = N->getOperand(0);
2607 SDValue N1 = N->getOperand(1);
2608 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2609 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2610 MVT VT = N0.getValueType();
2611 unsigned OpSizeInBits = VT.getSizeInBits();
2613 // fold (srl c1, c2) -> c1 >>u c2
2615 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
2616 // fold (srl 0, x) -> 0
2617 if (N0C && N0C->isNullValue())
2619 // fold (srl x, c >= size(x)) -> undef
2620 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2621 return DAG.getUNDEF(VT);
2622 // fold (srl x, 0) -> x
2623 if (N1C && N1C->isNullValue())
2625 // if (srl x, c) is known to be zero, return 0
2626 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2627 APInt::getAllOnesValue(OpSizeInBits)))
2628 return DAG.getConstant(0, VT);
2630 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
2631 if (N1C && N0.getOpcode() == ISD::SRL &&
2632 N0.getOperand(1).getOpcode() == ISD::Constant) {
2633 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2634 uint64_t c2 = N1C->getZExtValue();
2635 if (c1 + c2 > OpSizeInBits)
2636 return DAG.getConstant(0, VT);
2637 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
2638 DAG.getConstant(c1 + c2, N1.getValueType()));
2641 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2642 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2643 // Shifting in all undef bits?
2644 MVT SmallVT = N0.getOperand(0).getValueType();
2645 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
2646 return DAG.getUNDEF(VT);
2648 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
2649 N0.getOperand(0), N1);
2650 AddToWorkList(SmallShift.getNode());
2651 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
2654 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2655 // bit, which is unmodified by sra.
2656 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
2657 if (N0.getOpcode() == ISD::SRA)
2658 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
2661 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2662 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2663 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
2664 APInt KnownZero, KnownOne;
2665 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
2666 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2668 // If any of the input bits are KnownOne, then the input couldn't be all
2669 // zeros, thus the result of the srl will always be zero.
2670 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
2672 // If all of the bits input the to ctlz node are known to be zero, then
2673 // the result of the ctlz is "32" and the result of the shift is one.
2674 APInt UnknownBits = ~KnownZero & Mask;
2675 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2677 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2678 if ((UnknownBits & (UnknownBits - 1)) == 0) {
2679 // Okay, we know that only that the single bit specified by UnknownBits
2680 // could be set on input to the CTLZ node. If this bit is set, the SRL
2681 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2682 // to an SRL/XOR pair, which is likely to simplify more.
2683 unsigned ShAmt = UnknownBits.countTrailingZeros();
2684 SDValue Op = N0.getOperand(0);
2687 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
2688 DAG.getConstant(ShAmt, getShiftAmountTy()));
2689 AddToWorkList(Op.getNode());
2692 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
2693 Op, DAG.getConstant(1, VT));
2697 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
2698 if (N1.getOpcode() == ISD::TRUNCATE &&
2699 N1.getOperand(0).getOpcode() == ISD::AND &&
2700 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2701 SDValue N101 = N1.getOperand(0).getOperand(1);
2702 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2703 MVT TruncVT = N1.getValueType();
2704 SDValue N100 = N1.getOperand(0).getOperand(0);
2705 APInt TruncC = N101C->getAPIntValue();
2706 TruncC.trunc(TruncVT.getSizeInBits());
2707 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
2708 DAG.getNode(ISD::AND, N->getDebugLoc(),
2710 DAG.getNode(ISD::TRUNCATE,
2713 DAG.getConstant(TruncC, TruncVT)));
2717 // fold operands of srl based on knowledge that the low bits are not
2719 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2720 return SDValue(N, 0);
2722 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2725 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
2726 SDValue N0 = N->getOperand(0);
2727 MVT VT = N->getValueType(0);
2729 // fold (ctlz c1) -> c2
2730 if (isa<ConstantSDNode>(N0))
2731 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
2735 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
2736 SDValue N0 = N->getOperand(0);
2737 MVT VT = N->getValueType(0);
2739 // fold (cttz c1) -> c2
2740 if (isa<ConstantSDNode>(N0))
2741 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
2745 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
2746 SDValue N0 = N->getOperand(0);
2747 MVT VT = N->getValueType(0);
2749 // fold (ctpop c1) -> c2
2750 if (isa<ConstantSDNode>(N0))
2751 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
2755 SDValue DAGCombiner::visitSELECT(SDNode *N) {
2756 SDValue N0 = N->getOperand(0);
2757 SDValue N1 = N->getOperand(1);
2758 SDValue N2 = N->getOperand(2);
2759 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2760 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2761 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2762 MVT VT = N->getValueType(0);
2763 MVT VT0 = N0.getValueType();
2765 // fold (select C, X, X) -> X
2768 // fold (select true, X, Y) -> X
2769 if (N0C && !N0C->isNullValue())
2771 // fold (select false, X, Y) -> Y
2772 if (N0C && N0C->isNullValue())
2774 // fold (select C, 1, X) -> (or C, X)
2775 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
2776 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2777 // fold (select C, 0, 1) -> (xor C, 1)
2778 if (VT.isInteger() &&
2781 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
2782 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
2785 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
2786 N0, DAG.getConstant(1, VT0));
2787 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
2788 N0, DAG.getConstant(1, VT0));
2789 AddToWorkList(XORNode.getNode());
2791 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
2792 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
2794 // fold (select C, 0, X) -> (and (not C), X)
2795 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2796 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2797 AddToWorkList(NOTNode.getNode());
2798 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
2800 // fold (select C, X, 1) -> (or (not C), X)
2801 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
2802 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2803 AddToWorkList(NOTNode.getNode());
2804 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
2806 // fold (select C, X, 0) -> (and C, X)
2807 if (VT == MVT::i1 && N2C && N2C->isNullValue())
2808 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2809 // fold (select X, X, Y) -> (or X, Y)
2810 // fold (select X, 1, Y) -> (or X, Y)
2811 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
2812 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2813 // fold (select X, Y, X) -> (and X, Y)
2814 // fold (select X, Y, 0) -> (and X, Y)
2815 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
2816 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2818 // If we can fold this based on the true/false value, do so.
2819 if (SimplifySelectOps(N, N1, N2))
2820 return SDValue(N, 0); // Don't revisit N.
2822 // fold selects based on a setcc into other things, such as min/max/abs
2823 if (N0.getOpcode() == ISD::SETCC) {
2825 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2826 // having to say they don't support SELECT_CC on every type the DAG knows
2827 // about, since there is no way to mark an opcode illegal at all value types
2828 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other))
2829 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
2830 N0.getOperand(0), N0.getOperand(1),
2831 N1, N2, N0.getOperand(2));
2832 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
2838 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
2839 SDValue N0 = N->getOperand(0);
2840 SDValue N1 = N->getOperand(1);
2841 SDValue N2 = N->getOperand(2);
2842 SDValue N3 = N->getOperand(3);
2843 SDValue N4 = N->getOperand(4);
2844 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2846 // fold select_cc lhs, rhs, x, x, cc -> x
2850 // Determine if the condition we're dealing with is constant
2851 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
2852 N0, N1, CC, N->getDebugLoc(), false);
2853 if (SCC.getNode()) AddToWorkList(SCC.getNode());
2855 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
2856 if (!SCCC->isNullValue())
2857 return N2; // cond always true -> true val
2859 return N3; // cond always false -> false val
2862 // Fold to a simpler select_cc
2863 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
2864 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
2865 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2868 // If we can fold this based on the true/false value, do so.
2869 if (SimplifySelectOps(N, N2, N3))
2870 return SDValue(N, 0); // Don't revisit N.
2872 // fold select_cc into other things, such as min/max/abs
2873 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
2876 SDValue DAGCombiner::visitSETCC(SDNode *N) {
2877 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2878 cast<CondCodeSDNode>(N->getOperand(2))->get(),
2882 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2883 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
2884 // transformation. Returns true if extension are possible and the above
2885 // mentioned transformation is profitable.
2886 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
2888 SmallVector<SDNode*, 4> &ExtendNodes,
2889 const TargetLowering &TLI) {
2890 bool HasCopyToRegUses = false;
2891 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2892 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
2893 UE = N0.getNode()->use_end();
2898 if (UI.getUse().getResNo() != N0.getResNo())
2900 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2901 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
2902 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2903 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2904 // Sign bits will be lost after a zext.
2907 for (unsigned i = 0; i != 2; ++i) {
2908 SDValue UseOp = User->getOperand(i);
2911 if (!isa<ConstantSDNode>(UseOp))
2916 ExtendNodes.push_back(User);
2919 // If truncates aren't free and there are users we can't
2920 // extend, it isn't worthwhile.
2923 // Remember if this value is live-out.
2924 if (User->getOpcode() == ISD::CopyToReg)
2925 HasCopyToRegUses = true;
2928 if (HasCopyToRegUses) {
2929 bool BothLiveOut = false;
2930 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2932 SDUse &Use = UI.getUse();
2933 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
2939 // Both unextended and extended values are live out. There had better be
2940 // good a reason for the transformation.
2941 return ExtendNodes.size();
2946 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2947 SDValue N0 = N->getOperand(0);
2948 MVT VT = N->getValueType(0);
2950 // fold (sext c1) -> c1
2951 if (isa<ConstantSDNode>(N0))
2952 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
2954 // fold (sext (sext x)) -> (sext x)
2955 // fold (sext (aext x)) -> (sext x)
2956 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2957 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
2960 if (N0.getOpcode() == ISD::TRUNCATE) {
2961 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2962 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2963 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
2964 if (NarrowLoad.getNode()) {
2965 if (NarrowLoad.getNode() != N0.getNode())
2966 CombineTo(N0.getNode(), NarrowLoad);
2967 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2970 // See if the value being truncated is already sign extended. If so, just
2971 // eliminate the trunc/sext pair.
2972 SDValue Op = N0.getOperand(0);
2973 unsigned OpBits = Op.getValueType().getSizeInBits();
2974 unsigned MidBits = N0.getValueType().getSizeInBits();
2975 unsigned DestBits = VT.getSizeInBits();
2976 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2978 if (OpBits == DestBits) {
2979 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2980 // bits, it is already ready.
2981 if (NumSignBits > DestBits-MidBits)
2983 } else if (OpBits < DestBits) {
2984 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2985 // bits, just sext from i32.
2986 if (NumSignBits > OpBits-MidBits)
2987 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
2989 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2990 // bits, just truncate to i32.
2991 if (NumSignBits > OpBits-MidBits)
2992 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
2995 // fold (sext (truncate x)) -> (sextinreg x).
2996 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2997 N0.getValueType())) {
2998 if (Op.getValueType().bitsLT(VT))
2999 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3000 else if (Op.getValueType().bitsGT(VT))
3001 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3002 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3003 DAG.getValueType(N0.getValueType()));
3007 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3008 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3009 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3010 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3011 bool DoXform = true;
3012 SmallVector<SDNode*, 4> SetCCs;
3013 if (!N0.hasOneUse())
3014 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3016 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3017 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3019 LN0->getBasePtr(), LN0->getSrcValue(),
3020 LN0->getSrcValueOffset(),
3022 LN0->isVolatile(), LN0->getAlignment());
3023 CombineTo(N, ExtLoad);
3024 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3025 N0.getValueType(), ExtLoad);
3026 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3028 // Extend SetCC uses if necessary.
3029 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3030 SDNode *SetCC = SetCCs[i];
3031 SmallVector<SDValue, 4> Ops;
3033 for (unsigned j = 0; j != 2; ++j) {
3034 SDValue SOp = SetCC->getOperand(j);
3036 Ops.push_back(ExtLoad);
3038 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3039 N->getDebugLoc(), VT, SOp));
3042 Ops.push_back(SetCC->getOperand(2));
3043 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3044 SetCC->getValueType(0),
3045 &Ops[0], Ops.size()));
3048 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3052 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3053 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3054 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3055 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3056 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3057 MVT EVT = LN0->getMemoryVT();
3058 if ((!LegalOperations && !LN0->isVolatile()) ||
3059 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) {
3060 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3062 LN0->getBasePtr(), LN0->getSrcValue(),
3063 LN0->getSrcValueOffset(), EVT,
3064 LN0->isVolatile(), LN0->getAlignment());
3065 CombineTo(N, ExtLoad);
3066 CombineTo(N0.getNode(),
3067 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3068 N0.getValueType(), ExtLoad),
3069 ExtLoad.getValue(1));
3070 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3074 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3075 if (N0.getOpcode() == ISD::SETCC) {
3077 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3078 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
3079 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3080 if (SCC.getNode()) return SCC;
3083 // fold (sext x) -> (zext x) if the sign bit is known zero.
3084 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3085 DAG.SignBitIsZero(N0))
3086 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3091 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3092 SDValue N0 = N->getOperand(0);
3093 MVT VT = N->getValueType(0);
3095 // fold (zext c1) -> c1
3096 if (isa<ConstantSDNode>(N0))
3097 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3098 // fold (zext (zext x)) -> (zext x)
3099 // fold (zext (aext x)) -> (zext x)
3100 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3101 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3104 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3105 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3106 if (N0.getOpcode() == ISD::TRUNCATE) {
3107 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3108 if (NarrowLoad.getNode()) {
3109 if (NarrowLoad.getNode() != N0.getNode())
3110 CombineTo(N0.getNode(), NarrowLoad);
3111 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3115 // fold (zext (truncate x)) -> (and x, mask)
3116 if (N0.getOpcode() == ISD::TRUNCATE &&
3117 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
3118 SDValue Op = N0.getOperand(0);
3119 if (Op.getValueType().bitsLT(VT)) {
3120 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3121 } else if (Op.getValueType().bitsGT(VT)) {
3122 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3124 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType());
3127 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
3128 // if either of the casts is not free.
3129 if (N0.getOpcode() == ISD::AND &&
3130 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3131 N0.getOperand(1).getOpcode() == ISD::Constant &&
3132 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3133 N0.getValueType()) ||
3134 !TLI.isZExtFree(N0.getValueType(), VT))) {
3135 SDValue X = N0.getOperand(0).getOperand(0);
3136 if (X.getValueType().bitsLT(VT)) {
3137 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3138 } else if (X.getValueType().bitsGT(VT)) {
3139 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3141 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3142 Mask.zext(VT.getSizeInBits());
3143 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3144 X, DAG.getConstant(Mask, VT));
3147 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3148 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3149 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3150 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3151 bool DoXform = true;
3152 SmallVector<SDNode*, 4> SetCCs;
3153 if (!N0.hasOneUse())
3154 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3156 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3157 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3159 LN0->getBasePtr(), LN0->getSrcValue(),
3160 LN0->getSrcValueOffset(),
3162 LN0->isVolatile(), LN0->getAlignment());
3163 CombineTo(N, ExtLoad);
3164 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3165 N0.getValueType(), ExtLoad);
3166 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3168 // Extend SetCC uses if necessary.
3169 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3170 SDNode *SetCC = SetCCs[i];
3171 SmallVector<SDValue, 4> Ops;
3173 for (unsigned j = 0; j != 2; ++j) {
3174 SDValue SOp = SetCC->getOperand(j);
3176 Ops.push_back(ExtLoad);
3178 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3179 N->getDebugLoc(), VT, SOp));
3182 Ops.push_back(SetCC->getOperand(2));
3183 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3184 SetCC->getValueType(0),
3185 &Ops[0], Ops.size()));
3188 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3192 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3193 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3194 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3195 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3196 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3197 MVT EVT = LN0->getMemoryVT();
3198 if ((!LegalOperations && !LN0->isVolatile()) ||
3199 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) {
3200 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3202 LN0->getBasePtr(), LN0->getSrcValue(),
3203 LN0->getSrcValueOffset(), EVT,
3204 LN0->isVolatile(), LN0->getAlignment());
3205 CombineTo(N, ExtLoad);
3206 CombineTo(N0.getNode(),
3207 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3209 ExtLoad.getValue(1));
3210 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3214 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3215 if (N0.getOpcode() == ISD::SETCC) {
3217 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3218 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3219 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3220 if (SCC.getNode()) return SCC;
3226 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3227 SDValue N0 = N->getOperand(0);
3228 MVT VT = N->getValueType(0);
3230 // fold (aext c1) -> c1
3231 if (isa<ConstantSDNode>(N0))
3232 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3233 // fold (aext (aext x)) -> (aext x)
3234 // fold (aext (zext x)) -> (zext x)
3235 // fold (aext (sext x)) -> (sext x)
3236 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3237 N0.getOpcode() == ISD::ZERO_EXTEND ||
3238 N0.getOpcode() == ISD::SIGN_EXTEND)
3239 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3241 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3242 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3243 if (N0.getOpcode() == ISD::TRUNCATE) {
3244 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3245 if (NarrowLoad.getNode()) {
3246 if (NarrowLoad.getNode() != N0.getNode())
3247 CombineTo(N0.getNode(), NarrowLoad);
3248 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3252 // fold (aext (truncate x))
3253 if (N0.getOpcode() == ISD::TRUNCATE) {
3254 SDValue TruncOp = N0.getOperand(0);
3255 if (TruncOp.getValueType() == VT)
3256 return TruncOp; // x iff x size == zext size.
3257 if (TruncOp.getValueType().bitsGT(VT))
3258 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3259 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3262 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
3263 // if the trunc is not free.
3264 if (N0.getOpcode() == ISD::AND &&
3265 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3266 N0.getOperand(1).getOpcode() == ISD::Constant &&
3267 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3268 N0.getValueType())) {
3269 SDValue X = N0.getOperand(0).getOperand(0);
3270 if (X.getValueType().bitsLT(VT)) {
3271 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3272 } else if (X.getValueType().bitsGT(VT)) {
3273 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3275 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3276 Mask.zext(VT.getSizeInBits());
3277 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3278 X, DAG.getConstant(Mask, VT));
3281 // fold (aext (load x)) -> (aext (truncate (extload x)))
3282 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3283 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3284 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3285 bool DoXform = true;
3286 SmallVector<SDNode*, 4> SetCCs;
3287 if (!N0.hasOneUse())
3288 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
3290 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3291 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
3293 LN0->getBasePtr(), LN0->getSrcValue(),
3294 LN0->getSrcValueOffset(),
3296 LN0->isVolatile(), LN0->getAlignment());
3297 CombineTo(N, ExtLoad);
3298 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3299 N0.getValueType(), ExtLoad);
3300 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3302 // Extend SetCC uses if necessary.
3303 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3304 SDNode *SetCC = SetCCs[i];
3305 SmallVector<SDValue, 4> Ops;
3307 for (unsigned j = 0; j != 2; ++j) {
3308 SDValue SOp = SetCC->getOperand(j);
3310 Ops.push_back(ExtLoad);
3312 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
3313 N->getDebugLoc(), VT, SOp));
3316 Ops.push_back(SetCC->getOperand(2));
3317 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3318 SetCC->getValueType(0),
3319 &Ops[0], Ops.size()));
3322 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3326 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3327 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3328 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3329 if (N0.getOpcode() == ISD::LOAD &&
3330 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3332 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3333 MVT EVT = LN0->getMemoryVT();
3334 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
3335 VT, LN0->getChain(), LN0->getBasePtr(),
3337 LN0->getSrcValueOffset(), EVT,
3338 LN0->isVolatile(), LN0->getAlignment());
3339 CombineTo(N, ExtLoad);
3340 CombineTo(N0.getNode(),
3341 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3342 N0.getValueType(), ExtLoad),
3343 ExtLoad.getValue(1));
3344 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3347 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3348 if (N0.getOpcode() == ISD::SETCC) {
3350 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3351 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3352 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3360 /// GetDemandedBits - See if the specified operand can be simplified with the
3361 /// knowledge that only the bits specified by Mask are used. If so, return the
3362 /// simpler operand, otherwise return a null SDValue.
3363 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
3364 switch (V.getOpcode()) {
3368 // If the LHS or RHS don't contribute bits to the or, drop them.
3369 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3370 return V.getOperand(1);
3371 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3372 return V.getOperand(0);
3375 // Only look at single-use SRLs.
3376 if (!V.getNode()->hasOneUse())
3378 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3379 // See if we can recursively simplify the LHS.
3380 unsigned Amt = RHSC->getZExtValue();
3382 // Watch out for shift count overflow though.
3383 if (Amt >= Mask.getBitWidth()) break;
3384 APInt NewMask = Mask << Amt;
3385 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
3386 if (SimplifyLHS.getNode())
3387 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
3388 SimplifyLHS, V.getOperand(1));
3394 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3395 /// bits and then truncated to a narrower type and where N is a multiple
3396 /// of number of bits of the narrower type, transform it to a narrower load
3397 /// from address + N / num of bits of new type. If the result is to be
3398 /// extended, also fold the extension to form a extending load.
3399 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
3400 unsigned Opc = N->getOpcode();
3401 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3402 SDValue N0 = N->getOperand(0);
3403 MVT VT = N->getValueType(0);
3406 // This transformation isn't valid for vector loads.
3410 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3412 if (Opc == ISD::SIGN_EXTEND_INREG) {
3413 ExtType = ISD::SEXTLOAD;
3414 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3415 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))
3419 unsigned EVTBits = EVT.getSizeInBits();
3421 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3422 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3423 ShAmt = N01->getZExtValue();
3424 // Is the shift amount a multiple of size of VT?
3425 if ((ShAmt & (EVTBits-1)) == 0) {
3426 N0 = N0.getOperand(0);
3427 if (N0.getValueType().getSizeInBits() <= EVTBits)
3433 // Do not generate loads of non-round integer types since these can
3434 // be expensive (and would be wrong if the type is not byte sized).
3435 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() &&
3436 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
3437 // Do not change the width of a volatile load.
3438 !cast<LoadSDNode>(N0)->isVolatile()) {
3439 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3440 MVT PtrType = N0.getOperand(1).getValueType();
3442 // For big endian targets, we need to adjust the offset to the pointer to
3443 // load the correct bytes.
3444 if (TLI.isBigEndian()) {
3445 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
3446 unsigned EVTStoreBits = EVT.getStoreSizeInBits();
3447 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3450 uint64_t PtrOff = ShAmt / 8;
3451 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3452 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
3453 PtrType, LN0->getBasePtr(),
3454 DAG.getConstant(PtrOff, PtrType));
3455 AddToWorkList(NewPtr.getNode());
3457 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
3458 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
3459 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3460 LN0->isVolatile(), NewAlign)
3461 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
3462 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3463 EVT, LN0->isVolatile(), NewAlign);
3465 // Replace the old load's chain with the new load's chain.
3466 WorkListRemover DeadNodes(*this);
3467 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
3470 // Return the new loaded value.
3477 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3478 SDValue N0 = N->getOperand(0);
3479 SDValue N1 = N->getOperand(1);
3480 MVT VT = N->getValueType(0);
3481 MVT EVT = cast<VTSDNode>(N1)->getVT();
3482 unsigned VTBits = VT.getSizeInBits();
3483 unsigned EVTBits = EVT.getSizeInBits();
3485 // fold (sext_in_reg c1) -> c1
3486 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3487 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
3489 // If the input is already sign extended, just drop the extension.
3490 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
3493 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3494 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3495 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
3496 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3497 N0.getOperand(0), N1);
3500 // fold (sext_in_reg (sext x)) -> (sext x)
3501 // fold (sext_in_reg (aext x)) -> (sext x)
3502 // if x is small enough.
3503 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
3504 SDValue N00 = N0.getOperand(0);
3505 if (N00.getValueType().getSizeInBits() < EVTBits)
3506 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
3509 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3510 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
3511 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
3513 // fold operands of sext_in_reg based on knowledge that the top bits are not
3515 if (SimplifyDemandedBits(SDValue(N, 0)))
3516 return SDValue(N, 0);
3518 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3519 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3520 SDValue NarrowLoad = ReduceLoadWidth(N);
3521 if (NarrowLoad.getNode())
3524 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
3525 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
3526 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3527 if (N0.getOpcode() == ISD::SRL) {
3528 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3529 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) {
3530 // We can turn this into an SRA iff the input to the SRL is already sign
3532 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3533 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
3534 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
3535 N0.getOperand(0), N0.getOperand(1));
3539 // fold (sext_inreg (extload x)) -> (sextload x)
3540 if (ISD::isEXTLoad(N0.getNode()) &&
3541 ISD::isUNINDEXEDLoad(N0.getNode()) &&
3542 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3543 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3544 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3545 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3546 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3548 LN0->getBasePtr(), LN0->getSrcValue(),
3549 LN0->getSrcValueOffset(), EVT,
3550 LN0->isVolatile(), LN0->getAlignment());
3551 CombineTo(N, ExtLoad);
3552 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3553 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3555 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3556 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3558 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3559 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3560 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3561 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3562 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3564 LN0->getBasePtr(), LN0->getSrcValue(),
3565 LN0->getSrcValueOffset(), EVT,
3566 LN0->isVolatile(), LN0->getAlignment());
3567 CombineTo(N, ExtLoad);
3568 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3569 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3574 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
3575 SDValue N0 = N->getOperand(0);
3576 MVT VT = N->getValueType(0);
3579 if (N0.getValueType() == N->getValueType(0))
3581 // fold (truncate c1) -> c1
3582 if (isa<ConstantSDNode>(N0))
3583 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
3584 // fold (truncate (truncate x)) -> (truncate x)
3585 if (N0.getOpcode() == ISD::TRUNCATE)
3586 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3587 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3588 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3589 N0.getOpcode() == ISD::ANY_EXTEND) {
3590 if (N0.getOperand(0).getValueType().bitsLT(VT))
3591 // if the source is smaller than the dest, we still need an extend
3592 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
3594 else if (N0.getOperand(0).getValueType().bitsGT(VT))
3595 // if the source is larger than the dest, than we just need the truncate
3596 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3598 // if the source and dest are the same type, we can drop both the extend
3600 return N0.getOperand(0);
3603 // See if we can simplify the input to this truncate through knowledge that
3604 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3607 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3608 VT.getSizeInBits()));
3609 if (Shorter.getNode())
3610 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
3612 // fold (truncate (load x)) -> (smaller load x)
3613 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3614 return ReduceLoadWidth(N);
3617 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
3618 SDValue Elt = N->getOperand(i);
3619 if (Elt.getOpcode() != ISD::MERGE_VALUES)
3620 return Elt.getNode();
3621 return Elt.getOperand(Elt.getResNo()).getNode();
3624 /// CombineConsecutiveLoads - build_pair (load, load) -> load
3625 /// if load locations are consecutive.
3626 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
3627 assert(N->getOpcode() == ISD::BUILD_PAIR);
3629 SDNode *LD1 = getBuildPairElt(N, 0);
3630 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
3632 MVT LD1VT = LD1->getValueType(0);
3633 SDNode *LD2 = getBuildPairElt(N, 1);
3634 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3636 if (ISD::isNON_EXTLoad(LD2) &&
3638 // If both are volatile this would reduce the number of volatile loads.
3639 // If one is volatile it might be ok, but play conservative and bail out.
3640 !cast<LoadSDNode>(LD1)->isVolatile() &&
3641 !cast<LoadSDNode>(LD2)->isVolatile() &&
3642 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
3643 LoadSDNode *LD = cast<LoadSDNode>(LD1);
3644 unsigned Align = LD->getAlignment();
3645 unsigned NewAlign = TLI.getTargetData()->
3646 getABITypeAlignment(VT.getTypeForMVT());
3648 if (NewAlign <= Align &&
3649 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
3650 return DAG.getLoad(VT, N->getDebugLoc(), LD->getChain(), LD->getBasePtr(),
3651 LD->getSrcValue(), LD->getSrcValueOffset(),
3658 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3659 SDValue N0 = N->getOperand(0);
3660 MVT VT = N->getValueType(0);
3662 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3663 // Only do this before legalize, since afterward the target may be depending
3664 // on the bitconvert.
3665 // First check to see if this is all constant.
3667 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
3669 bool isSimple = true;
3670 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3671 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3672 N0.getOperand(i).getOpcode() != ISD::Constant &&
3673 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3678 MVT DestEltVT = N->getValueType(0).getVectorElementType();
3679 assert(!DestEltVT.isVector() &&
3680 "Element type of vector ValueType must not be vector!");
3682 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
3685 // If the input is a constant, let getNode fold it.
3686 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3687 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
3688 if (Res.getNode() != N) return Res;
3691 // (conv (conv x, t1), t2) -> (conv x, t2)
3692 if (N0.getOpcode() == ISD::BIT_CONVERT)
3693 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
3696 // fold (conv (load x)) -> (load (conv*)x)
3697 // If the resultant load doesn't need a higher alignment than the original!
3698 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
3699 // Do not change the width of a volatile load.
3700 !cast<LoadSDNode>(N0)->isVolatile() &&
3701 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
3702 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3703 unsigned Align = TLI.getTargetData()->
3704 getABITypeAlignment(VT.getTypeForMVT());
3705 unsigned OrigAlign = LN0->getAlignment();
3707 if (Align <= OrigAlign) {
3708 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
3710 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3711 LN0->isVolatile(), OrigAlign);
3713 CombineTo(N0.getNode(),
3714 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3715 N0.getValueType(), Load),
3721 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
3722 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
3723 // This often reduces constant pool loads.
3724 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3725 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
3726 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
3728 AddToWorkList(NewConv.getNode());
3730 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3731 if (N0.getOpcode() == ISD::FNEG)
3732 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3733 NewConv, DAG.getConstant(SignBit, VT));
3734 assert(N0.getOpcode() == ISD::FABS);
3735 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3736 NewConv, DAG.getConstant(~SignBit, VT));
3739 // fold (bitconvert (fcopysign cst, x)) ->
3740 // (or (and (bitconvert x), sign), (and cst, (not sign)))
3741 // Note that we don't handle (copysign x, cst) because this can always be
3742 // folded to an fneg or fabs.
3743 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
3744 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
3745 VT.isInteger() && !VT.isVector()) {
3746 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
3747 MVT IntXVT = MVT::getIntegerVT(OrigXWidth);
3748 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) {
3749 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3750 IntXVT, N0.getOperand(1));
3751 AddToWorkList(X.getNode());
3753 // If X has a different width than the result/lhs, sext it or truncate it.
3754 unsigned VTWidth = VT.getSizeInBits();
3755 if (OrigXWidth < VTWidth) {
3756 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
3757 AddToWorkList(X.getNode());
3758 } else if (OrigXWidth > VTWidth) {
3759 // To get the sign bit in the right place, we have to shift it right
3760 // before truncating.
3761 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
3762 X.getValueType(), X,
3763 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
3764 AddToWorkList(X.getNode());
3765 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3766 AddToWorkList(X.getNode());
3769 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3770 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
3771 X, DAG.getConstant(SignBit, VT));
3772 AddToWorkList(X.getNode());
3774 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3775 VT, N0.getOperand(0));
3776 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
3777 Cst, DAG.getConstant(~SignBit, VT));
3778 AddToWorkList(Cst.getNode());
3780 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
3784 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
3785 if (N0.getOpcode() == ISD::BUILD_PAIR) {
3786 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
3787 if (CombineLD.getNode())
3794 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
3795 MVT VT = N->getValueType(0);
3796 return CombineConsecutiveLoads(N, VT);
3799 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3800 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3801 /// destination element value type.
3802 SDValue DAGCombiner::
3803 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
3804 MVT SrcEltVT = BV->getValueType(0).getVectorElementType();
3806 // If this is already the right type, we're done.
3807 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
3809 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
3810 unsigned DstBitSize = DstEltVT.getSizeInBits();
3812 // If this is a conversion of N elements of one type to N elements of another
3813 // type, convert each element. This handles FP<->INT cases.
3814 if (SrcBitSize == DstBitSize) {
3815 SmallVector<SDValue, 8> Ops;
3816 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3817 SDValue Op = BV->getOperand(i);
3818 // If the vector element type is not legal, the BUILD_VECTOR operands
3819 // are promoted and implicitly truncated. Make that explicit here.
3820 if (Op.getValueType() != SrcEltVT)
3821 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
3822 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
3824 AddToWorkList(Ops.back().getNode());
3826 MVT VT = MVT::getVectorVT(DstEltVT,
3827 BV->getValueType(0).getVectorNumElements());
3828 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3829 &Ops[0], Ops.size());
3832 // Otherwise, we're growing or shrinking the elements. To avoid having to
3833 // handle annoying details of growing/shrinking FP values, we convert them to
3835 if (SrcEltVT.isFloatingPoint()) {
3836 // Convert the input float vector to a int vector where the elements are the
3838 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3839 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
3840 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
3844 // Now we know the input is an integer vector. If the output is a FP type,
3845 // convert to integer first, then to FP of the right size.
3846 if (DstEltVT.isFloatingPoint()) {
3847 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3848 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
3849 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
3851 // Next, convert to FP elements of the same size.
3852 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3855 // Okay, we know the src/dst types are both integers of differing types.
3856 // Handling growing first.
3857 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
3858 if (SrcBitSize < DstBitSize) {
3859 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3861 SmallVector<SDValue, 8> Ops;
3862 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3863 i += NumInputsPerOutput) {
3864 bool isLE = TLI.isLittleEndian();
3865 APInt NewBits = APInt(DstBitSize, 0);
3866 bool EltIsUndef = true;
3867 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3868 // Shift the previously computed bits over.
3869 NewBits <<= SrcBitSize;
3870 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3871 if (Op.getOpcode() == ISD::UNDEF) continue;
3874 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).
3875 zextOrTrunc(SrcBitSize).zext(DstBitSize));
3879 Ops.push_back(DAG.getUNDEF(DstEltVT));
3881 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3884 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size());
3885 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3886 &Ops[0], Ops.size());
3889 // Finally, this must be the case where we are shrinking elements: each input
3890 // turns into multiple outputs.
3891 bool isS2V = ISD::isScalarToVector(BV);
3892 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3893 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
3894 SmallVector<SDValue, 8> Ops;
3896 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3897 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3898 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3899 Ops.push_back(DAG.getUNDEF(DstEltVT));
3903 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))->
3904 getAPIntValue()).zextOrTrunc(SrcBitSize);
3906 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3907 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
3908 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3909 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
3910 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
3911 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
3913 OpVal = OpVal.lshr(DstBitSize);
3916 // For big endian targets, swap the order of the pieces of each element.
3917 if (TLI.isBigEndian())
3918 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3921 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3922 &Ops[0], Ops.size());
3925 SDValue DAGCombiner::visitFADD(SDNode *N) {
3926 SDValue N0 = N->getOperand(0);
3927 SDValue N1 = N->getOperand(1);
3928 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3929 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3930 MVT VT = N->getValueType(0);
3933 if (VT.isVector()) {
3934 SDValue FoldedVOp = SimplifyVBinOp(N);
3935 if (FoldedVOp.getNode()) return FoldedVOp;
3938 // fold (fadd c1, c2) -> (fadd c1, c2)
3939 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3940 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
3941 // canonicalize constant to RHS
3942 if (N0CFP && !N1CFP)
3943 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
3944 // fold (fadd A, 0) -> A
3945 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
3947 // fold (fadd A, (fneg B)) -> (fsub A, B)
3948 if (isNegatibleForFree(N1, LegalOperations) == 2)
3949 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
3950 GetNegatedExpression(N1, DAG, LegalOperations));
3951 // fold (fadd (fneg A), B) -> (fsub B, A)
3952 if (isNegatibleForFree(N0, LegalOperations) == 2)
3953 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
3954 GetNegatedExpression(N0, DAG, LegalOperations));
3956 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3957 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3958 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3959 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
3960 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
3961 N0.getOperand(1), N1));
3966 SDValue DAGCombiner::visitFSUB(SDNode *N) {
3967 SDValue N0 = N->getOperand(0);
3968 SDValue N1 = N->getOperand(1);
3969 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3970 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3971 MVT VT = N->getValueType(0);
3974 if (VT.isVector()) {
3975 SDValue FoldedVOp = SimplifyVBinOp(N);
3976 if (FoldedVOp.getNode()) return FoldedVOp;
3979 // fold (fsub c1, c2) -> c1-c2
3980 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3981 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
3982 // fold (fsub A, 0) -> A
3983 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
3985 // fold (fsub 0, B) -> -B
3986 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3987 if (isNegatibleForFree(N1, LegalOperations))
3988 return GetNegatedExpression(N1, DAG, LegalOperations);
3989 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
3990 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
3992 // fold (fsub A, (fneg B)) -> (fadd A, B)
3993 if (isNegatibleForFree(N1, LegalOperations))
3994 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
3995 GetNegatedExpression(N1, DAG, LegalOperations));
4000 SDValue DAGCombiner::visitFMUL(SDNode *N) {
4001 SDValue N0 = N->getOperand(0);
4002 SDValue N1 = N->getOperand(1);
4003 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4004 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4005 MVT VT = N->getValueType(0);
4008 if (VT.isVector()) {
4009 SDValue FoldedVOp = SimplifyVBinOp(N);
4010 if (FoldedVOp.getNode()) return FoldedVOp;
4013 // fold (fmul c1, c2) -> c1*c2
4014 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4015 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4016 // canonicalize constant to RHS
4017 if (N0CFP && !N1CFP)
4018 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4019 // fold (fmul A, 0) -> 0
4020 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4022 // fold (fmul A, 0) -> 0, vector edition.
4023 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
4025 // fold (fmul X, 2.0) -> (fadd X, X)
4026 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4027 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4028 // fold (fmul X, (fneg 1.0)) -> (fneg X)
4029 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4030 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4031 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4033 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4034 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4035 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4036 // Both can be negated for free, check to see if at least one is cheaper
4038 if (LHSNeg == 2 || RHSNeg == 2)
4039 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4040 GetNegatedExpression(N0, DAG, LegalOperations),
4041 GetNegatedExpression(N1, DAG, LegalOperations));
4045 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4046 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4047 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4048 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4049 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4050 N0.getOperand(1), N1));
4055 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4056 SDValue N0 = N->getOperand(0);
4057 SDValue N1 = N->getOperand(1);
4058 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4059 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4060 MVT VT = N->getValueType(0);
4063 if (VT.isVector()) {
4064 SDValue FoldedVOp = SimplifyVBinOp(N);
4065 if (FoldedVOp.getNode()) return FoldedVOp;
4068 // fold (fdiv c1, c2) -> c1/c2
4069 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4070 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4073 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4074 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4075 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4076 // Both can be negated for free, check to see if at least one is cheaper
4078 if (LHSNeg == 2 || RHSNeg == 2)
4079 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4080 GetNegatedExpression(N0, DAG, LegalOperations),
4081 GetNegatedExpression(N1, DAG, LegalOperations));
4088 SDValue DAGCombiner::visitFREM(SDNode *N) {
4089 SDValue N0 = N->getOperand(0);
4090 SDValue N1 = N->getOperand(1);
4091 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4092 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4093 MVT VT = N->getValueType(0);
4095 // fold (frem c1, c2) -> fmod(c1,c2)
4096 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4097 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4102 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4103 SDValue N0 = N->getOperand(0);
4104 SDValue N1 = N->getOperand(1);
4105 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4106 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4107 MVT VT = N->getValueType(0);
4109 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4110 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4113 const APFloat& V = N1CFP->getValueAPF();
4114 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4115 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4116 if (!V.isNegative()) {
4117 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4118 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4120 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4121 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4122 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4126 // copysign(fabs(x), y) -> copysign(x, y)
4127 // copysign(fneg(x), y) -> copysign(x, y)
4128 // copysign(copysign(x,z), y) -> copysign(x, y)
4129 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4130 N0.getOpcode() == ISD::FCOPYSIGN)
4131 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4132 N0.getOperand(0), N1);
4134 // copysign(x, abs(y)) -> abs(x)
4135 if (N1.getOpcode() == ISD::FABS)
4136 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4138 // copysign(x, copysign(y,z)) -> copysign(x, z)
4139 if (N1.getOpcode() == ISD::FCOPYSIGN)
4140 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4141 N0, N1.getOperand(1));
4143 // copysign(x, fp_extend(y)) -> copysign(x, y)
4144 // copysign(x, fp_round(y)) -> copysign(x, y)
4145 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4146 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4147 N0, N1.getOperand(0));
4152 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4153 SDValue N0 = N->getOperand(0);
4154 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4155 MVT VT = N->getValueType(0);
4156 MVT OpVT = N0.getValueType();
4158 // fold (sint_to_fp c1) -> c1fp
4159 if (N0C && OpVT != MVT::ppcf128)
4160 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4162 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4163 // but UINT_TO_FP is legal on this target, try to convert.
4164 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4165 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4166 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4167 if (DAG.SignBitIsZero(N0))
4168 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4174 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4175 SDValue N0 = N->getOperand(0);
4176 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4177 MVT VT = N->getValueType(0);
4178 MVT OpVT = N0.getValueType();
4180 // fold (uint_to_fp c1) -> c1fp
4181 if (N0C && OpVT != MVT::ppcf128)
4182 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4184 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
4185 // but SINT_TO_FP is legal on this target, try to convert.
4186 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4187 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4188 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4189 if (DAG.SignBitIsZero(N0))
4190 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4196 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4197 SDValue N0 = N->getOperand(0);
4198 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4199 MVT VT = N->getValueType(0);
4201 // fold (fp_to_sint c1fp) -> c1
4203 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
4208 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4209 SDValue N0 = N->getOperand(0);
4210 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4211 MVT VT = N->getValueType(0);
4213 // fold (fp_to_uint c1fp) -> c1
4214 if (N0CFP && VT != MVT::ppcf128)
4215 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
4220 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4221 SDValue N0 = N->getOperand(0);
4222 SDValue N1 = N->getOperand(1);
4223 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4224 MVT VT = N->getValueType(0);
4226 // fold (fp_round c1fp) -> c1fp
4227 if (N0CFP && N0.getValueType() != MVT::ppcf128)
4228 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
4230 // fold (fp_round (fp_extend x)) -> x
4231 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4232 return N0.getOperand(0);
4234 // fold (fp_round (fp_round x)) -> (fp_round x)
4235 if (N0.getOpcode() == ISD::FP_ROUND) {
4236 // This is a value preserving truncation if both round's are.
4237 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4238 N0.getNode()->getConstantOperandVal(1) == 1;
4239 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
4240 DAG.getIntPtrConstant(IsTrunc));
4243 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4244 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4245 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
4246 N0.getOperand(0), N1);
4247 AddToWorkList(Tmp.getNode());
4248 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4249 Tmp, N0.getOperand(1));
4255 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4256 SDValue N0 = N->getOperand(0);
4257 MVT VT = N->getValueType(0);
4258 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4259 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4261 // fold (fp_round_inreg c1fp) -> c1fp
4262 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) {
4263 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4264 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
4270 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4271 SDValue N0 = N->getOperand(0);
4272 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4273 MVT VT = N->getValueType(0);
4275 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4276 if (N->hasOneUse() &&
4277 N->use_begin()->getOpcode() == ISD::FP_ROUND)
4280 // fold (fp_extend c1fp) -> c1fp
4281 if (N0CFP && VT != MVT::ppcf128)
4282 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
4284 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4286 if (N0.getOpcode() == ISD::FP_ROUND
4287 && N0.getNode()->getConstantOperandVal(1) == 1) {
4288 SDValue In = N0.getOperand(0);
4289 if (In.getValueType() == VT) return In;
4290 if (VT.bitsLT(In.getValueType()))
4291 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
4292 In, N0.getOperand(1));
4293 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
4296 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
4297 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
4298 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4299 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4300 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4301 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4303 LN0->getBasePtr(), LN0->getSrcValue(),
4304 LN0->getSrcValueOffset(),
4306 LN0->isVolatile(), LN0->getAlignment());
4307 CombineTo(N, ExtLoad);
4308 CombineTo(N0.getNode(),
4309 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
4310 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
4311 ExtLoad.getValue(1));
4312 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4318 SDValue DAGCombiner::visitFNEG(SDNode *N) {
4319 SDValue N0 = N->getOperand(0);
4321 if (isNegatibleForFree(N0, LegalOperations))
4322 return GetNegatedExpression(N0, DAG, LegalOperations);
4324 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
4325 // constant pool values.
4326 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4327 N0.getOperand(0).getValueType().isInteger() &&
4328 !N0.getOperand(0).getValueType().isVector()) {
4329 SDValue Int = N0.getOperand(0);
4330 MVT IntVT = Int.getValueType();
4331 if (IntVT.isInteger() && !IntVT.isVector()) {
4332 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
4333 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4334 AddToWorkList(Int.getNode());
4335 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4336 N->getValueType(0), Int);
4343 SDValue DAGCombiner::visitFABS(SDNode *N) {
4344 SDValue N0 = N->getOperand(0);
4345 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4346 MVT VT = N->getValueType(0);
4348 // fold (fabs c1) -> fabs(c1)
4349 if (N0CFP && VT != MVT::ppcf128)
4350 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4351 // fold (fabs (fabs x)) -> (fabs x)
4352 if (N0.getOpcode() == ISD::FABS)
4353 return N->getOperand(0);
4354 // fold (fabs (fneg x)) -> (fabs x)
4355 // fold (fabs (fcopysign x, y)) -> (fabs x)
4356 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
4357 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
4359 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
4360 // constant pool values.
4361 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4362 N0.getOperand(0).getValueType().isInteger() &&
4363 !N0.getOperand(0).getValueType().isVector()) {
4364 SDValue Int = N0.getOperand(0);
4365 MVT IntVT = Int.getValueType();
4366 if (IntVT.isInteger() && !IntVT.isVector()) {
4367 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
4368 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4369 AddToWorkList(Int.getNode());
4370 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4371 N->getValueType(0), Int);
4378 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
4379 SDValue Chain = N->getOperand(0);
4380 SDValue N1 = N->getOperand(1);
4381 SDValue N2 = N->getOperand(2);
4382 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4384 // never taken branch, fold to chain
4385 if (N1C && N1C->isNullValue())
4387 // unconditional branch
4388 if (N1C && N1C->getAPIntValue() == 1)
4389 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2);
4390 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
4392 if (N1.getOpcode() == ISD::SETCC &&
4393 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
4394 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4395 Chain, N1.getOperand(2),
4396 N1.getOperand(0), N1.getOperand(1), N2);
4399 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) {
4400 // Match this pattern so that we can generate simpler code:
4403 // %b = and i32 %a, 2
4404 // %c = srl i32 %b, 1
4405 // brcond i32 %c ...
4411 // %c = setcc eq %b, 0
4414 // This applies only when the AND constant value has one bit set and the
4415 // SRL constant is equal to the log2 of the AND constant. The back-end is
4416 // smart enough to convert the result into a TEST/JMP sequence.
4417 SDValue Op0 = N1.getOperand(0);
4418 SDValue Op1 = N1.getOperand(1);
4420 if (Op0.getOpcode() == ISD::AND &&
4422 Op1.getOpcode() == ISD::Constant) {
4423 SDValue AndOp0 = Op0.getOperand(0);
4424 SDValue AndOp1 = Op0.getOperand(1);
4426 if (AndOp1.getOpcode() == ISD::Constant) {
4427 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
4429 if (AndConst.isPowerOf2() &&
4430 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
4432 DAG.getSetCC(N->getDebugLoc(),
4433 TLI.getSetCCResultType(Op0.getValueType()),
4434 Op0, DAG.getConstant(0, Op0.getValueType()),
4437 // Replace the uses of SRL with SETCC
4438 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
4439 removeFromWorkList(N1.getNode());
4440 DAG.DeleteNode(N1.getNode());
4441 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4442 MVT::Other, Chain, SetCC, N2);
4451 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
4453 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
4454 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
4455 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
4457 // Use SimplifySetCC to simplify SETCC's.
4458 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
4459 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
4461 if (Simp.getNode()) AddToWorkList(Simp.getNode());
4463 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
4465 // fold br_cc true, dest -> br dest (unconditional branch)
4466 if (SCCC && !SCCC->isNullValue())
4467 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other,
4468 N->getOperand(0), N->getOperand(4));
4469 // fold br_cc false, dest -> unconditional fall through
4470 if (SCCC && SCCC->isNullValue())
4471 return N->getOperand(0);
4473 // fold to a simpler setcc
4474 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
4475 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4476 N->getOperand(0), Simp.getOperand(2),
4477 Simp.getOperand(0), Simp.getOperand(1),
4483 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
4484 /// pre-indexed load / store when the base pointer is an add or subtract
4485 /// and it has other uses besides the load / store. After the
4486 /// transformation, the new indexed load / store has effectively folded
4487 /// the add / subtract in and all of its other uses are redirected to the
4488 /// new load / store.
4489 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
4490 if (!LegalOperations)
4496 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4497 if (LD->isIndexed())
4499 VT = LD->getMemoryVT();
4500 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
4501 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
4503 Ptr = LD->getBasePtr();
4504 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4505 if (ST->isIndexed())
4507 VT = ST->getMemoryVT();
4508 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
4509 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
4511 Ptr = ST->getBasePtr();
4517 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
4518 // out. There is no reason to make this a preinc/predec.
4519 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
4520 Ptr.getNode()->hasOneUse())
4523 // Ask the target to do addressing mode selection.
4526 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4527 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
4529 // Don't create a indexed load / store with zero offset.
4530 if (isa<ConstantSDNode>(Offset) &&
4531 cast<ConstantSDNode>(Offset)->isNullValue())
4534 // Try turning it into a pre-indexed load / store except when:
4535 // 1) The new base ptr is a frame index.
4536 // 2) If N is a store and the new base ptr is either the same as or is a
4537 // predecessor of the value being stored.
4538 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
4539 // that would create a cycle.
4540 // 4) All uses are load / store ops that use it as old base ptr.
4542 // Check #1. Preinc'ing a frame index would require copying the stack pointer
4543 // (plus the implicit offset) to a register to preinc anyway.
4544 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
4549 SDValue Val = cast<StoreSDNode>(N)->getValue();
4550 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
4554 // Now check for #3 and #4.
4555 bool RealUse = false;
4556 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4557 E = Ptr.getNode()->use_end(); I != E; ++I) {
4561 if (Use->isPredecessorOf(N))
4564 if (!((Use->getOpcode() == ISD::LOAD &&
4565 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
4566 (Use->getOpcode() == ISD::STORE &&
4567 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
4576 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4577 BasePtr, Offset, AM);
4579 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4580 BasePtr, Offset, AM);
4583 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
4584 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4586 WorkListRemover DeadNodes(*this);
4588 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4590 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4593 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4597 // Finally, since the node is now dead, remove it from the graph.
4600 // Replace the uses of Ptr with uses of the updated base value.
4601 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
4603 removeFromWorkList(Ptr.getNode());
4604 DAG.DeleteNode(Ptr.getNode());
4609 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
4610 /// add / sub of the base pointer node into a post-indexed load / store.
4611 /// The transformation folded the add / subtract into the new indexed
4612 /// load / store effectively and all of its uses are redirected to the
4613 /// new load / store.
4614 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
4615 if (!LegalOperations)
4621 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4622 if (LD->isIndexed())
4624 VT = LD->getMemoryVT();
4625 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
4626 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
4628 Ptr = LD->getBasePtr();
4629 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4630 if (ST->isIndexed())
4632 VT = ST->getMemoryVT();
4633 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
4634 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
4636 Ptr = ST->getBasePtr();
4642 if (Ptr.getNode()->hasOneUse())
4645 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4646 E = Ptr.getNode()->use_end(); I != E; ++I) {
4649 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
4654 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4655 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
4657 std::swap(BasePtr, Offset);
4660 // Don't create a indexed load / store with zero offset.
4661 if (isa<ConstantSDNode>(Offset) &&
4662 cast<ConstantSDNode>(Offset)->isNullValue())
4665 // Try turning it into a post-indexed load / store except when
4666 // 1) All uses are load / store ops that use it as base ptr.
4667 // 2) Op must be independent of N, i.e. Op is neither a predecessor
4668 // nor a successor of N. Otherwise, if Op is folded that would
4671 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
4675 bool TryNext = false;
4676 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
4677 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
4679 if (Use == Ptr.getNode())
4682 // If all the uses are load / store addresses, then don't do the
4684 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
4685 bool RealUse = false;
4686 for (SDNode::use_iterator III = Use->use_begin(),
4687 EEE = Use->use_end(); III != EEE; ++III) {
4688 SDNode *UseUse = *III;
4689 if (!((UseUse->getOpcode() == ISD::LOAD &&
4690 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
4691 (UseUse->getOpcode() == ISD::STORE &&
4692 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
4707 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
4708 SDValue Result = isLoad
4709 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4710 BasePtr, Offset, AM)
4711 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4712 BasePtr, Offset, AM);
4715 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4716 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4718 WorkListRemover DeadNodes(*this);
4720 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4722 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4725 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4729 // Finally, since the node is now dead, remove it from the graph.
4732 // Replace the uses of Use with uses of the updated base value.
4733 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
4734 Result.getValue(isLoad ? 1 : 0),
4736 removeFromWorkList(Op);
4746 /// InferAlignment - If we can infer some alignment information from this
4747 /// pointer, return it.
4748 static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) {
4749 // If this is a direct reference to a stack slot, use information about the
4750 // stack slot's alignment.
4751 int FrameIdx = 1 << 31;
4752 int64_t FrameOffset = 0;
4753 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) {
4754 FrameIdx = FI->getIndex();
4755 } else if (Ptr.getOpcode() == ISD::ADD &&
4756 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4757 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4758 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4759 FrameOffset = Ptr.getConstantOperandVal(1);
4762 if (FrameIdx != (1 << 31)) {
4763 // FIXME: Handle FI+CST.
4764 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
4765 if (MFI.isFixedObjectIndex(FrameIdx)) {
4766 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset;
4768 // The alignment of the frame index can be determined from its offset from
4769 // the incoming frame position. If the frame object is at offset 32 and
4770 // the stack is guaranteed to be 16-byte aligned, then we know that the
4771 // object is 16-byte aligned.
4772 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment();
4773 unsigned Align = MinAlign(ObjectOffset, StackAlign);
4775 // Finally, the frame object itself may have a known alignment. Factor
4776 // the alignment + offset into a new alignment. For example, if we know
4777 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a
4778 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte
4779 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc.
4780 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
4782 return std::max(Align, FIInfoAlign);
4789 SDValue DAGCombiner::visitLOAD(SDNode *N) {
4790 LoadSDNode *LD = cast<LoadSDNode>(N);
4791 SDValue Chain = LD->getChain();
4792 SDValue Ptr = LD->getBasePtr();
4794 // Try to infer better alignment information than the load already has.
4795 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
4796 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4797 if (Align > LD->getAlignment())
4798 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
4799 LD->getValueType(0),
4800 Chain, Ptr, LD->getSrcValue(),
4801 LD->getSrcValueOffset(), LD->getMemoryVT(),
4802 LD->isVolatile(), Align);
4806 // If load is not volatile and there are no uses of the loaded value (and
4807 // the updated indexed value in case of indexed loads), change uses of the
4808 // chain value into uses of the chain input (i.e. delete the dead load).
4809 if (!LD->isVolatile()) {
4810 if (N->getValueType(1) == MVT::Other) {
4812 if (N->hasNUsesOfValue(0, 0)) {
4813 // It's not safe to use the two value CombineTo variant here. e.g.
4814 // v1, chain2 = load chain1, loc
4815 // v2, chain3 = load chain2, loc
4817 // Now we replace use of chain2 with chain1. This makes the second load
4818 // isomorphic to the one we are deleting, and thus makes this load live.
4819 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4820 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG));
4822 WorkListRemover DeadNodes(*this);
4823 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
4825 if (N->use_empty()) {
4826 removeFromWorkList(N);
4830 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4834 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4835 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4836 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
4837 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4838 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
4839 DOUT << " and 2 other values\n";
4840 WorkListRemover DeadNodes(*this);
4841 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
4842 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
4843 DAG.getUNDEF(N->getValueType(1)),
4845 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
4846 removeFromWorkList(N);
4848 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4853 // If this load is directly stored, replace the load value with the stored
4855 // TODO: Handle store large -> read small portion.
4856 // TODO: Handle TRUNCSTORE/LOADEXT
4857 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
4858 !LD->isVolatile()) {
4859 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
4860 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4861 if (PrevST->getBasePtr() == Ptr &&
4862 PrevST->getValue().getValueType() == N->getValueType(0))
4863 return CombineTo(N, Chain.getOperand(1), Chain);
4868 // Walk up chain skipping non-aliasing memory nodes.
4869 SDValue BetterChain = FindBetterChain(N, Chain);
4871 // If there is a better chain.
4872 if (Chain != BetterChain) {
4875 // Replace the chain to void dependency.
4876 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4877 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
4879 LD->getSrcValue(), LD->getSrcValueOffset(),
4880 LD->isVolatile(), LD->getAlignment());
4882 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
4883 LD->getValueType(0),
4884 BetterChain, Ptr, LD->getSrcValue(),
4885 LD->getSrcValueOffset(),
4888 LD->getAlignment());
4891 // Create token factor to keep old chain connected.
4892 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
4893 MVT::Other, Chain, ReplLoad.getValue(1));
4895 // Replace uses with load result and token factor. Don't add users
4897 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4901 // Try transforming N to an indexed load.
4902 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4903 return SDValue(N, 0);
4909 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
4910 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
4911 /// of the loaded bits, try narrowing the load and store if it would end up
4912 /// being a win for performance or code size.
4913 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
4914 StoreSDNode *ST = cast<StoreSDNode>(N);
4915 if (ST->isVolatile())
4918 SDValue Chain = ST->getChain();
4919 SDValue Value = ST->getValue();
4920 SDValue Ptr = ST->getBasePtr();
4921 MVT VT = Value.getValueType();
4923 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
4926 unsigned Opc = Value.getOpcode();
4927 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
4928 Value.getOperand(1).getOpcode() != ISD::Constant)
4931 SDValue N0 = Value.getOperand(0);
4932 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) {
4933 LoadSDNode *LD = cast<LoadSDNode>(N0);
4934 if (LD->getBasePtr() != Ptr)
4937 // Find the type to narrow it the load / op / store to.
4938 SDValue N1 = Value.getOperand(1);
4939 unsigned BitWidth = N1.getValueSizeInBits();
4940 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
4941 if (Opc == ISD::AND)
4942 Imm ^= APInt::getAllOnesValue(BitWidth);
4943 if (Imm == 0 || Imm.isAllOnesValue())
4945 unsigned ShAmt = Imm.countTrailingZeros();
4946 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
4947 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
4948 MVT NewVT = MVT::getIntegerVT(NewBW);
4949 while (NewBW < BitWidth &&
4950 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
4951 TLI.isNarrowingProfitable(VT, NewVT))) {
4952 NewBW = NextPowerOf2(NewBW);
4953 NewVT = MVT::getIntegerVT(NewBW);
4955 if (NewBW >= BitWidth)
4958 // If the lsb changed does not start at the type bitwidth boundary,
4959 // start at the previous one.
4961 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
4962 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
4963 if ((Imm & Mask) == Imm) {
4964 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
4965 if (Opc == ISD::AND)
4966 NewImm ^= APInt::getAllOnesValue(NewBW);
4967 uint64_t PtrOff = ShAmt / 8;
4968 // For big endian targets, we need to adjust the offset to the pointer to
4969 // load the correct bytes.
4970 if (TLI.isBigEndian())
4971 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
4973 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
4975 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT()))
4978 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
4979 Ptr.getValueType(), Ptr,
4980 DAG.getConstant(PtrOff, Ptr.getValueType()));
4981 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
4982 LD->getChain(), NewPtr,
4983 LD->getSrcValue(), LD->getSrcValueOffset(),
4984 LD->isVolatile(), NewAlign);
4985 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
4986 DAG.getConstant(NewImm, NewVT));
4987 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
4989 ST->getSrcValue(), ST->getSrcValueOffset(),
4992 AddToWorkList(NewPtr.getNode());
4993 AddToWorkList(NewLD.getNode());
4994 AddToWorkList(NewVal.getNode());
4995 WorkListRemover DeadNodes(*this);
4996 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
5006 SDValue DAGCombiner::visitSTORE(SDNode *N) {
5007 StoreSDNode *ST = cast<StoreSDNode>(N);
5008 SDValue Chain = ST->getChain();
5009 SDValue Value = ST->getValue();
5010 SDValue Ptr = ST->getBasePtr();
5012 // Try to infer better alignment information than the store already has.
5013 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
5014 if (unsigned Align = InferAlignment(Ptr, DAG)) {
5015 if (Align > ST->getAlignment())
5016 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
5017 Ptr, ST->getSrcValue(),
5018 ST->getSrcValueOffset(), ST->getMemoryVT(),
5019 ST->isVolatile(), Align);
5023 // If this is a store of a bit convert, store the input value if the
5024 // resultant store does not need a higher alignment than the original.
5025 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
5026 ST->isUnindexed()) {
5027 unsigned OrigAlign = ST->getAlignment();
5028 MVT SVT = Value.getOperand(0).getValueType();
5029 unsigned Align = TLI.getTargetData()->
5030 getABITypeAlignment(SVT.getTypeForMVT());
5031 if (Align <= OrigAlign &&
5032 ((!LegalOperations && !ST->isVolatile()) ||
5033 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
5034 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5035 Ptr, ST->getSrcValue(),
5036 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign);
5039 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
5040 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
5041 // NOTE: If the original store is volatile, this transform must not increase
5042 // the number of stores. For example, on x86-32 an f64 can be stored in one
5043 // processor operation but an i64 (which is not legal) requires two. So the
5044 // transform should not be done in this case.
5045 if (Value.getOpcode() != ISD::TargetConstantFP) {
5047 switch (CFP->getValueType(0).getSimpleVT()) {
5048 default: assert(0 && "Unknown FP type");
5049 case MVT::f80: // We don't do this for these yet.
5054 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
5055 !ST->isVolatile()) ||
5056 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5057 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
5058 bitcastToAPInt().getZExtValue(), MVT::i32);
5059 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5060 Ptr, ST->getSrcValue(),
5061 ST->getSrcValueOffset(), ST->isVolatile(),
5062 ST->getAlignment());
5066 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
5067 !ST->isVolatile()) ||
5068 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
5069 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
5070 getZExtValue(), MVT::i64);
5071 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5072 Ptr, ST->getSrcValue(),
5073 ST->getSrcValueOffset(), ST->isVolatile(),
5074 ST->getAlignment());
5075 } else if (!ST->isVolatile() &&
5076 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5077 // Many FP stores are not made apparent until after legalize, e.g. for
5078 // argument passing. Since this is so common, custom legalize the
5079 // 64-bit integer store into two 32-bit stores.
5080 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
5081 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
5082 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
5083 if (TLI.isBigEndian()) std::swap(Lo, Hi);
5085 int SVOffset = ST->getSrcValueOffset();
5086 unsigned Alignment = ST->getAlignment();
5087 bool isVolatile = ST->isVolatile();
5089 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
5090 Ptr, ST->getSrcValue(),
5091 ST->getSrcValueOffset(),
5092 isVolatile, ST->getAlignment());
5093 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
5094 DAG.getConstant(4, Ptr.getValueType()));
5096 Alignment = MinAlign(Alignment, 4U);
5097 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
5098 Ptr, ST->getSrcValue(),
5099 SVOffset, isVolatile, Alignment);
5100 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
5110 // Walk up chain skipping non-aliasing memory nodes.
5111 SDValue BetterChain = FindBetterChain(N, Chain);
5113 // If there is a better chain.
5114 if (Chain != BetterChain) {
5115 // Replace the chain to avoid dependency.
5117 if (ST->isTruncatingStore()) {
5118 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5119 ST->getSrcValue(),ST->getSrcValueOffset(),
5121 ST->isVolatile(), ST->getAlignment());
5123 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5124 ST->getSrcValue(), ST->getSrcValueOffset(),
5125 ST->isVolatile(), ST->getAlignment());
5128 // Create token to keep both nodes around.
5129 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5130 MVT::Other, Chain, ReplStore);
5132 // Don't add users to work list.
5133 return CombineTo(N, Token, false);
5137 // Try transforming N to an indexed store.
5138 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5139 return SDValue(N, 0);
5141 // FIXME: is there such a thing as a truncating indexed store?
5142 if (ST->isTruncatingStore() && ST->isUnindexed() &&
5143 Value.getValueType().isInteger()) {
5144 // See if we can simplify the input to this truncstore with knowledge that
5145 // only the low bits are being used. For example:
5146 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
5148 GetDemandedBits(Value,
5149 APInt::getLowBitsSet(Value.getValueSizeInBits(),
5150 ST->getMemoryVT().getSizeInBits()));
5151 AddToWorkList(Value.getNode());
5152 if (Shorter.getNode())
5153 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
5154 Ptr, ST->getSrcValue(),
5155 ST->getSrcValueOffset(), ST->getMemoryVT(),
5156 ST->isVolatile(), ST->getAlignment());
5158 // Otherwise, see if we can simplify the operation with
5159 // SimplifyDemandedBits, which only works if the value has a single use.
5160 if (SimplifyDemandedBits(Value,
5161 APInt::getLowBitsSet(
5162 Value.getValueSizeInBits(),
5163 ST->getMemoryVT().getSizeInBits())))
5164 return SDValue(N, 0);
5167 // If this is a load followed by a store to the same location, then the store
5169 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
5170 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
5171 ST->isUnindexed() && !ST->isVolatile() &&
5172 // There can't be any side effects between the load and store, such as
5174 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
5175 // The store is dead, remove it.
5180 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
5181 // truncating store. We can do this even if this is already a truncstore.
5182 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
5183 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
5184 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
5185 ST->getMemoryVT())) {
5186 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5187 Ptr, ST->getSrcValue(),
5188 ST->getSrcValueOffset(), ST->getMemoryVT(),
5189 ST->isVolatile(), ST->getAlignment());
5192 return ReduceLoadOpStoreWidth(N);
5195 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
5196 SDValue InVec = N->getOperand(0);
5197 SDValue InVal = N->getOperand(1);
5198 SDValue EltNo = N->getOperand(2);
5200 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
5201 // vector with the inserted element.
5202 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
5203 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5204 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
5205 InVec.getNode()->op_end());
5206 if (Elt < Ops.size())
5208 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5209 InVec.getValueType(), &Ops[0], Ops.size());
5211 // If the invec is an UNDEF and if EltNo is a constant, create a new
5212 // BUILD_VECTOR with undef elements and the inserted element.
5213 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
5214 isa<ConstantSDNode>(EltNo)) {
5215 MVT VT = InVec.getValueType();
5216 MVT EVT = VT.getVectorElementType();
5217 unsigned NElts = VT.getVectorNumElements();
5218 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT));
5220 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5221 if (Elt < Ops.size())
5223 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5224 InVec.getValueType(), &Ops[0], Ops.size());
5229 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
5230 // (vextract (scalar_to_vector val, 0) -> val
5231 SDValue InVec = N->getOperand(0);
5233 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5234 // If the operand is wider than the vector element type then it is implicitly
5235 // truncated. Make that explicit here.
5236 MVT EltVT = InVec.getValueType().getVectorElementType();
5237 SDValue InOp = InVec.getOperand(0);
5238 if (InOp.getValueType() != EltVT)
5239 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp);
5243 // Perform only after legalization to ensure build_vector / vector_shuffle
5244 // optimizations have already been done.
5245 if (!LegalOperations) return SDValue();
5247 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
5248 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
5249 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
5250 SDValue EltNo = N->getOperand(1);
5252 if (isa<ConstantSDNode>(EltNo)) {
5253 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5254 bool NewLoad = false;
5255 bool BCNumEltsChanged = false;
5256 MVT VT = InVec.getValueType();
5257 MVT EVT = VT.getVectorElementType();
5260 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
5261 MVT BCVT = InVec.getOperand(0).getValueType();
5262 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
5264 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
5265 BCNumEltsChanged = true;
5266 InVec = InVec.getOperand(0);
5267 EVT = BCVT.getVectorElementType();
5271 LoadSDNode *LN0 = NULL;
5272 const ShuffleVectorSDNode *SVN = NULL;
5273 if (ISD::isNormalLoad(InVec.getNode())) {
5274 LN0 = cast<LoadSDNode>(InVec);
5275 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5276 InVec.getOperand(0).getValueType() == EVT &&
5277 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
5278 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
5279 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
5280 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
5282 // (load $addr+1*size)
5284 // If the bit convert changed the number of elements, it is unsafe
5285 // to examine the mask.
5286 if (BCNumEltsChanged)
5289 // Select the input vector, guarding against out of range extract vector.
5290 unsigned NumElems = VT.getVectorNumElements();
5291 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt);
5292 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
5294 if (InVec.getOpcode() == ISD::BIT_CONVERT)
5295 InVec = InVec.getOperand(0);
5296 if (ISD::isNormalLoad(InVec.getNode())) {
5297 LN0 = cast<LoadSDNode>(InVec);
5298 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems;
5302 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
5305 unsigned Align = LN0->getAlignment();
5307 // Check the resultant load doesn't need a higher alignment than the
5310 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT());
5312 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
5318 SDValue NewPtr = LN0->getBasePtr();
5320 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
5321 MVT PtrType = NewPtr.getValueType();
5322 if (TLI.isBigEndian())
5323 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
5324 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
5325 DAG.getConstant(PtrOff, PtrType));
5328 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
5329 LN0->getSrcValue(), LN0->getSrcValueOffset(),
5330 LN0->isVolatile(), Align);
5336 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
5337 unsigned NumInScalars = N->getNumOperands();
5338 MVT VT = N->getValueType(0);
5339 MVT EltType = VT.getVectorElementType();
5341 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
5342 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
5343 // at most two distinct vectors, turn this into a shuffle node.
5344 SDValue VecIn1, VecIn2;
5345 for (unsigned i = 0; i != NumInScalars; ++i) {
5346 // Ignore undef inputs.
5347 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5349 // If this input is something other than a EXTRACT_VECTOR_ELT with a
5350 // constant index, bail out.
5351 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5352 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
5353 VecIn1 = VecIn2 = SDValue(0, 0);
5357 // If the input vector type disagrees with the result of the build_vector,
5358 // we can't make a shuffle.
5359 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
5360 if (ExtractedFromVec.getValueType() != VT) {
5361 VecIn1 = VecIn2 = SDValue(0, 0);
5365 // Otherwise, remember this. We allow up to two distinct input vectors.
5366 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
5369 if (VecIn1.getNode() == 0) {
5370 VecIn1 = ExtractedFromVec;
5371 } else if (VecIn2.getNode() == 0) {
5372 VecIn2 = ExtractedFromVec;
5375 VecIn1 = VecIn2 = SDValue(0, 0);
5380 // If everything is good, we can make a shuffle operation.
5381 if (VecIn1.getNode()) {
5382 SmallVector<int, 8> Mask;
5383 for (unsigned i = 0; i != NumInScalars; ++i) {
5384 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
5389 // If extracting from the first vector, just use the index directly.
5390 SDValue Extract = N->getOperand(i);
5391 SDValue ExtVal = Extract.getOperand(1);
5392 if (Extract.getOperand(0) == VecIn1) {
5393 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5394 if (ExtIndex > VT.getVectorNumElements())
5397 Mask.push_back(ExtIndex);
5401 // Otherwise, use InIdx + VecSize
5402 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5403 Mask.push_back(Idx+NumInScalars);
5406 // Add count and size info.
5407 if (!TLI.isTypeLegal(VT) && LegalTypes)
5410 // Return the new VECTOR_SHUFFLE node.
5413 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5414 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
5420 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
5421 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
5422 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
5423 // inputs come from at most two distinct vectors, turn this into a shuffle
5426 // If we only have one input vector, we don't need to do any concatenation.
5427 if (N->getNumOperands() == 1)
5428 return N->getOperand(0);
5433 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
5436 MVT VT = N->getValueType(0);
5437 unsigned NumElts = VT.getVectorNumElements();
5439 SDValue N0 = N->getOperand(0);
5440 SDValue N1 = N->getOperand(1);
5442 assert(N0.getValueType().getVectorNumElements() == NumElts &&
5443 "Vector shuffle must be normalized in DAG");
5445 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
5447 // If it is a splat, check if the argument vector is a build_vector with
5448 // all scalar elements the same.
5449 if (cast<ShuffleVectorSDNode>(N)->isSplat()) {
5450 SDNode *V = N0.getNode();
5453 // If this is a bit convert that changes the element type of the vector but
5454 // not the number of vector elements, look through it. Be careful not to
5455 // look though conversions that change things like v4f32 to v2f64.
5456 if (V->getOpcode() == ISD::BIT_CONVERT) {
5457 SDValue ConvInput = V->getOperand(0);
5458 if (ConvInput.getValueType().isVector() &&
5459 ConvInput.getValueType().getVectorNumElements() == NumElts)
5460 V = ConvInput.getNode();
5463 if (V->getOpcode() == ISD::BUILD_VECTOR) {
5464 unsigned NumElems = V->getNumOperands();
5465 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex();
5466 if (NumElems > BaseIdx) {
5468 bool AllSame = true;
5469 for (unsigned i = 0; i != NumElems; ++i) {
5470 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
5471 Base = V->getOperand(i);
5475 // Splat of <u, u, u, u>, return <u, u, u, u>
5476 if (!Base.getNode())
5478 for (unsigned i = 0; i != NumElems; ++i) {
5479 if (V->getOperand(i) != Base) {
5484 // Splat of <x, x, x, x>, return <x, x, x, x>
5493 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
5494 /// an AND to a vector_shuffle with the destination vector and a zero vector.
5495 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
5496 /// vector_shuffle V, Zero, <0, 4, 2, 4>
5497 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
5498 MVT VT = N->getValueType(0);
5499 DebugLoc dl = N->getDebugLoc();
5500 SDValue LHS = N->getOperand(0);
5501 SDValue RHS = N->getOperand(1);
5502 if (N->getOpcode() == ISD::AND) {
5503 if (RHS.getOpcode() == ISD::BIT_CONVERT)
5504 RHS = RHS.getOperand(0);
5505 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
5506 SmallVector<int, 8> Indices;
5507 unsigned NumElts = RHS.getNumOperands();
5508 for (unsigned i = 0; i != NumElts; ++i) {
5509 SDValue Elt = RHS.getOperand(i);
5510 if (!isa<ConstantSDNode>(Elt))
5512 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
5513 Indices.push_back(i);
5514 else if (cast<ConstantSDNode>(Elt)->isNullValue())
5515 Indices.push_back(NumElts);
5520 // Let's see if the target supports this vector_shuffle.
5521 MVT RVT = RHS.getValueType();
5522 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
5525 // Return the new VECTOR_SHUFFLE node.
5526 MVT EVT = RVT.getVectorElementType();
5527 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
5528 DAG.getConstant(0, EVT));
5529 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5530 RVT, &ZeroOps[0], ZeroOps.size());
5531 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS);
5532 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
5533 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf);
5540 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
5541 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
5542 // After legalize, the target may be depending on adds and other
5543 // binary ops to provide legal ways to construct constants or other
5544 // things. Simplifying them may result in a loss of legality.
5545 if (LegalOperations) return SDValue();
5547 MVT VT = N->getValueType(0);
5548 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
5550 MVT EltType = VT.getVectorElementType();
5551 SDValue LHS = N->getOperand(0);
5552 SDValue RHS = N->getOperand(1);
5553 SDValue Shuffle = XformToShuffleWithZero(N);
5554 if (Shuffle.getNode()) return Shuffle;
5556 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
5558 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
5559 RHS.getOpcode() == ISD::BUILD_VECTOR) {
5560 SmallVector<SDValue, 8> Ops;
5561 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
5562 SDValue LHSOp = LHS.getOperand(i);
5563 SDValue RHSOp = RHS.getOperand(i);
5564 // If these two elements can't be folded, bail out.
5565 if ((LHSOp.getOpcode() != ISD::UNDEF &&
5566 LHSOp.getOpcode() != ISD::Constant &&
5567 LHSOp.getOpcode() != ISD::ConstantFP) ||
5568 (RHSOp.getOpcode() != ISD::UNDEF &&
5569 RHSOp.getOpcode() != ISD::Constant &&
5570 RHSOp.getOpcode() != ISD::ConstantFP))
5573 // Can't fold divide by zero.
5574 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
5575 N->getOpcode() == ISD::FDIV) {
5576 if ((RHSOp.getOpcode() == ISD::Constant &&
5577 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
5578 (RHSOp.getOpcode() == ISD::ConstantFP &&
5579 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
5583 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(),
5584 EltType, LHSOp, RHSOp));
5585 AddToWorkList(Ops.back().getNode());
5586 assert((Ops.back().getOpcode() == ISD::UNDEF ||
5587 Ops.back().getOpcode() == ISD::Constant ||
5588 Ops.back().getOpcode() == ISD::ConstantFP) &&
5589 "Scalar binop didn't fold!");
5592 if (Ops.size() == LHS.getNumOperands()) {
5593 MVT VT = LHS.getValueType();
5594 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
5595 &Ops[0], Ops.size());
5602 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
5603 SDValue N1, SDValue N2){
5604 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
5606 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
5607 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5609 // If we got a simplified select_cc node back from SimplifySelectCC, then
5610 // break it down into a new SETCC node, and a new SELECT node, and then return
5611 // the SELECT node, since we were called with a SELECT node.
5612 if (SCC.getNode()) {
5613 // Check to see if we got a select_cc back (to turn into setcc/select).
5614 // Otherwise, just return whatever node we got back, like fabs.
5615 if (SCC.getOpcode() == ISD::SELECT_CC) {
5616 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
5618 SCC.getOperand(0), SCC.getOperand(1),
5620 AddToWorkList(SETCC.getNode());
5621 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
5622 SCC.getOperand(2), SCC.getOperand(3), SETCC);
5630 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
5631 /// are the two values being selected between, see if we can simplify the
5632 /// select. Callers of this should assume that TheSelect is deleted if this
5633 /// returns true. As such, they should return the appropriate thing (e.g. the
5634 /// node) back to the top-level of the DAG combiner loop to avoid it being
5636 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
5639 // If this is a select from two identical things, try to pull the operation
5640 // through the select.
5641 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
5642 // If this is a load and the token chain is identical, replace the select
5643 // of two loads with a load through a select of the address to load from.
5644 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
5645 // constants have been dropped into the constant pool.
5646 if (LHS.getOpcode() == ISD::LOAD &&
5647 // Do not let this transformation reduce the number of volatile loads.
5648 !cast<LoadSDNode>(LHS)->isVolatile() &&
5649 !cast<LoadSDNode>(RHS)->isVolatile() &&
5650 // Token chains must be identical.
5651 LHS.getOperand(0) == RHS.getOperand(0)) {
5652 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
5653 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
5655 // If this is an EXTLOAD, the VT's must match.
5656 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
5657 // FIXME: this conflates two src values, discarding one. This is not
5658 // the right thing to do, but nothing uses srcvalues now. When they do,
5659 // turn SrcValue into a list of locations.
5661 if (TheSelect->getOpcode() == ISD::SELECT) {
5662 // Check that the condition doesn't reach either load. If so, folding
5663 // this will induce a cycle into the DAG.
5664 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5665 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) {
5666 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
5667 LLD->getBasePtr().getValueType(),
5668 TheSelect->getOperand(0), LLD->getBasePtr(),
5672 // Check that the condition doesn't reach either load. If so, folding
5673 // this will induce a cycle into the DAG.
5674 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5675 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5676 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) &&
5677 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) {
5678 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
5679 LLD->getBasePtr().getValueType(),
5680 TheSelect->getOperand(0),
5681 TheSelect->getOperand(1),
5682 LLD->getBasePtr(), RLD->getBasePtr(),
5683 TheSelect->getOperand(4));
5687 if (Addr.getNode()) {
5689 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
5690 Load = DAG.getLoad(TheSelect->getValueType(0),
5691 TheSelect->getDebugLoc(),
5693 Addr,LLD->getSrcValue(),
5694 LLD->getSrcValueOffset(),
5696 LLD->getAlignment());
5698 Load = DAG.getExtLoad(LLD->getExtensionType(),
5699 TheSelect->getDebugLoc(),
5700 TheSelect->getValueType(0),
5701 LLD->getChain(), Addr, LLD->getSrcValue(),
5702 LLD->getSrcValueOffset(),
5705 LLD->getAlignment());
5708 // Users of the select now use the result of the load.
5709 CombineTo(TheSelect, Load);
5711 // Users of the old loads now use the new load's chain. We know the
5712 // old-load value is dead now.
5713 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
5714 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
5724 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
5725 /// where 'cond' is the comparison specified by CC.
5726 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
5727 SDValue N2, SDValue N3,
5728 ISD::CondCode CC, bool NotExtCompare) {
5729 // (x ? y : y) -> y.
5730 if (N2 == N3) return N2;
5732 MVT VT = N2.getValueType();
5733 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
5734 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
5735 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
5737 // Determine if the condition we're dealing with is constant
5738 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
5739 N0, N1, CC, DL, false);
5740 if (SCC.getNode()) AddToWorkList(SCC.getNode());
5741 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
5743 // fold select_cc true, x, y -> x
5744 if (SCCC && !SCCC->isNullValue())
5746 // fold select_cc false, x, y -> y
5747 if (SCCC && SCCC->isNullValue())
5750 // Check to see if we can simplify the select into an fabs node
5751 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
5752 // Allow either -0.0 or 0.0
5753 if (CFP->getValueAPF().isZero()) {
5754 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
5755 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
5756 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
5757 N2 == N3.getOperand(0))
5758 return DAG.getNode(ISD::FABS, DL, VT, N0);
5760 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
5761 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
5762 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
5763 N2.getOperand(0) == N3)
5764 return DAG.getNode(ISD::FABS, DL, VT, N3);
5768 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
5769 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
5770 // in it. This is a win when the constant is not otherwise available because
5771 // it replaces two constant pool loads with one. We only do this if the FP
5772 // type is known to be legal, because if it isn't, then we are before legalize
5773 // types an we want the other legalization to happen first (e.g. to avoid
5774 // messing with soft float) and if the ConstantFP is not legal, because if
5775 // it is legal, we may not need to store the FP constant in a constant pool.
5776 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
5777 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
5778 if (TLI.isTypeLegal(N2.getValueType()) &&
5779 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
5780 TargetLowering::Legal) &&
5781 // If both constants have multiple uses, then we won't need to do an
5782 // extra load, they are likely around in registers for other users.
5783 (TV->hasOneUse() || FV->hasOneUse())) {
5784 Constant *Elts[] = {
5785 const_cast<ConstantFP*>(FV->getConstantFPValue()),
5786 const_cast<ConstantFP*>(TV->getConstantFPValue())
5788 const Type *FPTy = Elts[0]->getType();
5789 const TargetData &TD = *TLI.getTargetData();
5791 // Create a ConstantArray of the two constants.
5792 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
5793 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
5794 TD.getPrefTypeAlignment(FPTy));
5795 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5797 // Get the offsets to the 0 and 1 element of the array so that we can
5798 // select between them.
5799 SDValue Zero = DAG.getIntPtrConstant(0);
5800 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
5801 SDValue One = DAG.getIntPtrConstant(EltSize);
5803 SDValue Cond = DAG.getSetCC(DL,
5804 TLI.getSetCCResultType(N0.getValueType()),
5806 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
5808 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
5810 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
5811 PseudoSourceValue::getConstantPool(), 0, false,
5817 // Check to see if we can perform the "gzip trick", transforming
5818 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
5819 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
5820 N0.getValueType().isInteger() &&
5821 N2.getValueType().isInteger() &&
5822 (N1C->isNullValue() || // (a < 0) ? b : 0
5823 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
5824 MVT XType = N0.getValueType();
5825 MVT AType = N2.getValueType();
5826 if (XType.bitsGE(AType)) {
5827 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
5828 // single-bit constant.
5829 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
5830 unsigned ShCtV = N2C->getAPIntValue().logBase2();
5831 ShCtV = XType.getSizeInBits()-ShCtV-1;
5832 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
5833 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
5835 AddToWorkList(Shift.getNode());
5837 if (XType.bitsGT(AType)) {
5838 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
5839 AddToWorkList(Shift.getNode());
5842 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
5845 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
5847 DAG.getConstant(XType.getSizeInBits()-1,
5848 getShiftAmountTy()));
5849 AddToWorkList(Shift.getNode());
5851 if (XType.bitsGT(AType)) {
5852 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
5853 AddToWorkList(Shift.getNode());
5856 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
5860 // fold select C, 16, 0 -> shl C, 4
5861 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
5862 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
5864 // If the caller doesn't want us to simplify this into a zext of a compare,
5866 if (NotExtCompare && N2C->getAPIntValue() == 1)
5869 // Get a SetCC of the condition
5870 // FIXME: Should probably make sure that setcc is legal if we ever have a
5871 // target where it isn't.
5873 // cast from setcc result type to select result type
5875 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
5877 if (N2.getValueType().bitsLT(SCC.getValueType()))
5878 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
5880 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
5881 N2.getValueType(), SCC);
5883 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
5884 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
5885 N2.getValueType(), SCC);
5888 AddToWorkList(SCC.getNode());
5889 AddToWorkList(Temp.getNode());
5891 if (N2C->getAPIntValue() == 1)
5894 // shl setcc result by log2 n2c
5895 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
5896 DAG.getConstant(N2C->getAPIntValue().logBase2(),
5897 getShiftAmountTy()));
5900 // Check to see if this is the equivalent of setcc
5901 // FIXME: Turn all of these into setcc if setcc if setcc is legal
5902 // otherwise, go ahead with the folds.
5903 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
5904 MVT XType = N0.getValueType();
5905 if (!LegalOperations ||
5906 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
5907 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
5908 if (Res.getValueType() != VT)
5909 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
5913 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
5914 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
5915 (!LegalOperations ||
5916 TLI.isOperationLegal(ISD::CTLZ, XType))) {
5917 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
5918 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
5919 DAG.getConstant(Log2_32(XType.getSizeInBits()),
5920 getShiftAmountTy()));
5922 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
5923 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
5924 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
5925 XType, DAG.getConstant(0, XType), N0);
5926 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
5927 return DAG.getNode(ISD::SRL, DL, XType,
5928 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
5929 DAG.getConstant(XType.getSizeInBits()-1,
5930 getShiftAmountTy()));
5932 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
5933 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
5934 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
5935 DAG.getConstant(XType.getSizeInBits()-1,
5936 getShiftAmountTy()));
5937 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
5941 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
5942 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5943 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
5944 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
5945 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
5946 MVT XType = N0.getValueType();
5947 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
5948 DAG.getConstant(XType.getSizeInBits()-1,
5949 getShiftAmountTy()));
5950 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
5952 AddToWorkList(Shift.getNode());
5953 AddToWorkList(Add.getNode());
5954 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
5956 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
5957 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5958 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
5959 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
5960 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
5961 MVT XType = N0.getValueType();
5962 if (SubC->isNullValue() && XType.isInteger()) {
5963 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
5965 DAG.getConstant(XType.getSizeInBits()-1,
5966 getShiftAmountTy()));
5967 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
5969 AddToWorkList(Shift.getNode());
5970 AddToWorkList(Add.getNode());
5971 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
5979 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
5980 SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0,
5981 SDValue N1, ISD::CondCode Cond,
5982 DebugLoc DL, bool foldBooleans) {
5983 TargetLowering::DAGCombinerInfo
5984 DagCombineInfo(DAG, Level == Unrestricted, false, this);
5985 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
5988 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
5989 /// return a DAG expression to select that will generate the same value by
5990 /// multiplying by a magic number. See:
5991 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5992 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
5993 std::vector<SDNode*> Built;
5994 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
5996 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6002 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
6003 /// return a DAG expression to select that will generate the same value by
6004 /// multiplying by a magic number. See:
6005 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6006 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
6007 std::vector<SDNode*> Built;
6008 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
6010 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6016 /// FindBaseOffset - Return true if base is known not to alias with anything
6017 /// but itself. Provides base object and offset as results.
6018 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
6019 // Assume it is a primitive operation.
6020 Base = Ptr; Offset = 0;
6022 // If it's an adding a simple constant then integrate the offset.
6023 if (Base.getOpcode() == ISD::ADD) {
6024 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
6025 Base = Base.getOperand(0);
6026 Offset += C->getZExtValue();
6030 // If it's any of the following then it can't alias with anything but itself.
6031 return isa<FrameIndexSDNode>(Base) ||
6032 isa<ConstantPoolSDNode>(Base) ||
6033 isa<GlobalAddressSDNode>(Base);
6036 /// isAlias - Return true if there is any possibility that the two addresses
6038 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
6039 const Value *SrcValue1, int SrcValueOffset1,
6040 SDValue Ptr2, int64_t Size2,
6041 const Value *SrcValue2, int SrcValueOffset2) const {
6042 // If they are the same then they must be aliases.
6043 if (Ptr1 == Ptr2) return true;
6045 // Gather base node and offset information.
6046 SDValue Base1, Base2;
6047 int64_t Offset1, Offset2;
6048 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
6049 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
6051 // If they have a same base address then...
6053 // Check to see if the addresses overlap.
6054 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
6056 // If we know both bases then they can't alias.
6057 if (KnownBase1 && KnownBase2) return false;
6059 if (CombinerGlobalAA) {
6060 // Use alias analysis information.
6061 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
6062 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
6063 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
6064 AliasAnalysis::AliasResult AAResult =
6065 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
6066 if (AAResult == AliasAnalysis::NoAlias)
6070 // Otherwise we have to assume they alias.
6074 /// FindAliasInfo - Extracts the relevant alias information from the memory
6075 /// node. Returns true if the operand was a load.
6076 bool DAGCombiner::FindAliasInfo(SDNode *N,
6077 SDValue &Ptr, int64_t &Size,
6078 const Value *&SrcValue, int &SrcValueOffset) const {
6079 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6080 Ptr = LD->getBasePtr();
6081 Size = LD->getMemoryVT().getSizeInBits() >> 3;
6082 SrcValue = LD->getSrcValue();
6083 SrcValueOffset = LD->getSrcValueOffset();
6085 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6086 Ptr = ST->getBasePtr();
6087 Size = ST->getMemoryVT().getSizeInBits() >> 3;
6088 SrcValue = ST->getSrcValue();
6089 SrcValueOffset = ST->getSrcValueOffset();
6091 assert(0 && "FindAliasInfo expected a memory operand");
6097 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
6098 /// looking for aliasing nodes and adding them to the Aliases vector.
6099 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
6100 SmallVector<SDValue, 8> &Aliases) {
6101 SmallVector<SDValue, 8> Chains; // List of chains to visit.
6102 std::set<SDNode *> Visited; // Visited node set.
6104 // Get alias information for node.
6107 const Value *SrcValue = 0;
6108 int SrcValueOffset = 0;
6109 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
6112 Chains.push_back(OriginalChain);
6114 // Look at each chain and determine if it is an alias. If so, add it to the
6115 // aliases list. If not, then continue up the chain looking for the next
6117 while (!Chains.empty()) {
6118 SDValue Chain = Chains.back();
6121 // Don't bother if we've been before.
6122 if (Visited.find(Chain.getNode()) != Visited.end()) continue;
6123 Visited.insert(Chain.getNode());
6125 switch (Chain.getOpcode()) {
6126 case ISD::EntryToken:
6127 // Entry token is ideal chain operand, but handled in FindBetterChain.
6132 // Get alias information for Chain.
6135 const Value *OpSrcValue = 0;
6136 int OpSrcValueOffset = 0;
6137 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
6138 OpSrcValue, OpSrcValueOffset);
6140 // If chain is alias then stop here.
6141 if (!(IsLoad && IsOpLoad) &&
6142 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
6143 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
6144 Aliases.push_back(Chain);
6146 // Look further up the chain.
6147 Chains.push_back(Chain.getOperand(0));
6148 // Clean up old chain.
6149 AddToWorkList(Chain.getNode());
6154 case ISD::TokenFactor:
6155 // We have to check each of the operands of the token factor, so we queue
6156 // then up. Adding the operands to the queue (stack) in reverse order
6157 // maintains the original order and increases the likelihood that getNode
6158 // will find a matching token factor (CSE.)
6159 for (unsigned n = Chain.getNumOperands(); n;)
6160 Chains.push_back(Chain.getOperand(--n));
6161 // Eliminate the token factor if we can.
6162 AddToWorkList(Chain.getNode());
6166 // For all other instructions we will just have to take what we can get.
6167 Aliases.push_back(Chain);
6173 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
6174 /// for a better chain (aliasing node.)
6175 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
6176 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
6178 // Accumulate all the aliases to this node.
6179 GatherAllAliases(N, OldChain, Aliases);
6181 if (Aliases.size() == 0) {
6182 // If no operands then chain to entry token.
6183 return DAG.getEntryNode();
6184 } else if (Aliases.size() == 1) {
6185 // If a single operand then chain to it. We don't need to revisit it.
6189 // Construct a custom tailored token factor.
6190 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6191 &Aliases[0], Aliases.size());
6193 // Make sure the old chain gets cleaned up.
6194 if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
6199 // SelectionDAG::Combine - This is the entry point for the file.
6201 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
6202 CodeGenOpt::Level OptLevel) {
6203 /// run - This is the main entry point to this class.
6205 DAGCombiner(*this, AA, OptLevel).Run(Level);