1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/CommandLine.h"
46 static Statistic<> NodesCombined ("dagcombiner",
47 "Number of dag nodes combined");
51 CombinerAA("combiner-alias-analysis", cl::Hidden,
52 cl::desc("Turn on alias analysis turning testing"));
55 /// FindBaseOffset - Return true if base is known not to alias with anything
56 /// but itself. Provides base object and offset as results.
57 bool FindBaseOffset(SDOperand Ptr, SDOperand &Object, int64_t &Offset) {
58 // If it's an adding or subtracting a simple constant then add the constant
60 if (Ptr.getOpcode() == ISD::ADD) {
61 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Ptr.getOperand(1))) {
62 bool IsNonAliasing = FindBaseOffset(Ptr.getOperand(0), Object, Offset);
63 Offset += C->getValue();
66 } else if (Ptr.getOpcode() == ISD::SUB) {
67 // FIXME - Aren't all subtract constants converted to add negative constant.
68 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Ptr.getOperand(1))) {
69 bool IsNonAliasing = FindBaseOffset(Ptr.getOperand(0), Object, Offset);
70 Offset -= C->getValue();
75 // Primitive operation.
76 Object = Ptr; Offset = 0;
78 // If it's any of the following then it can't alias with anything but itself.
79 return isa<FrameIndexSDNode>(Ptr) ||
80 isa<ConstantPoolSDNode>(Ptr) ||
81 isa<GlobalAddressSDNode>(Ptr);
84 /// isAlias - Return true if there is any possibility that the two addresses
86 bool isAlias(SDOperand Ptr1, int64_t Size1, SDOperand SrcValue1,
87 SDOperand Ptr2, int64_t Size2, SDOperand SrcValue2) {
88 // If they are the same then they must be aliases.
89 if (Ptr1 == Ptr2) return true;
91 // Gather base node and offset information.
92 SDOperand Object1, Object2;
93 int64_t Offset1, Offset2;
94 bool IsNonAliasing1 = FindBaseOffset(Ptr1, Object1, Offset1);
95 bool IsNonAliasing2 = FindBaseOffset(Ptr2, Object2, Offset2);
97 // If they have a same base address then...
98 if (Object1 == Object2) {
99 // Check to see if the addresses overlap.
100 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
103 // Otherwise they alias if they are both non aliasing.
104 return !IsNonAliasing1 && IsNonAliasing2;
107 /// FindAliasInfo - Extracts the relevant alias information from the memory
108 /// node. Returns true if the operand was a load.
109 bool FindAliasInfo(SDNode *N,
110 SDOperand &Ptr, int64_t &Size, SDOperand &SrcValue) {
111 switch (N->getOpcode()) {
113 Ptr = N->getOperand(1);
114 Size = MVT::getSizeInBits(N->getValueType(0)) >> 3;
115 SrcValue = N->getOperand(2);
118 Ptr = N->getOperand(2);
119 Size = MVT::getSizeInBits(N->getOperand(1).getValueType()) >> 3;
120 SrcValue = N->getOperand(3);
123 assert(0 && "FindAliasInfo expected a memory operand");
130 //------------------------------ DAGCombiner ---------------------------------//
132 class VISIBILITY_HIDDEN DAGCombiner {
137 // Worklist of all of the nodes that need to be simplified.
138 std::vector<SDNode*> WorkList;
140 /// AddUsersToWorkList - When an instruction is simplified, add all users of
141 /// the instruction to the work lists because they might get more simplified
144 void AddUsersToWorkList(SDNode *N) {
145 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
150 /// removeFromWorkList - remove all instances of N from the worklist.
152 void removeFromWorkList(SDNode *N) {
153 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
158 /// AddToWorkList - Add to the work list making sure it's instance is at the
159 /// the back (next to be processed.)
160 void AddToWorkList(SDNode *N) {
161 removeFromWorkList(N);
162 WorkList.push_back(N);
165 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo) {
166 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
168 DEBUG(std::cerr << "\nReplacing.1 "; N->dump();
169 std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
170 std::cerr << " and " << NumTo-1 << " other values\n");
171 std::vector<SDNode*> NowDead;
172 DAG.ReplaceAllUsesWith(N, To, &NowDead);
174 // Push the new nodes and any users onto the worklist
175 for (unsigned i = 0, e = NumTo; i != e; ++i) {
176 AddToWorkList(To[i].Val);
177 AddUsersToWorkList(To[i].Val);
180 // Nodes can be reintroduced into the worklist. Make sure we do not
181 // process a node that has been replaced.
182 removeFromWorkList(N);
183 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
184 removeFromWorkList(NowDead[i]);
186 // Finally, since the node is now dead, remove it from the graph.
188 return SDOperand(N, 0);
191 SDOperand CombineTo(SDNode *N, SDOperand Res) {
192 return CombineTo(N, &Res, 1);
195 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
196 SDOperand To[] = { Res0, Res1 };
197 return CombineTo(N, To, 2);
201 /// SimplifyDemandedBits - Check the specified integer node value to see if
202 /// it can be simplified or if things it uses can be simplified by bit
203 /// propagation. If so, return true.
204 bool SimplifyDemandedBits(SDOperand Op) {
205 TargetLowering::TargetLoweringOpt TLO(DAG);
206 uint64_t KnownZero, KnownOne;
207 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
208 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
212 AddToWorkList(Op.Val);
214 // Replace the old value with the new one.
216 DEBUG(std::cerr << "\nReplacing.2 "; TLO.Old.Val->dump();
217 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG);
220 std::vector<SDNode*> NowDead;
221 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
223 // Push the new node and any (possibly new) users onto the worklist.
224 AddToWorkList(TLO.New.Val);
225 AddUsersToWorkList(TLO.New.Val);
227 // Nodes can end up on the worklist more than once. Make sure we do
228 // not process a node that has been replaced.
229 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
230 removeFromWorkList(NowDead[i]);
232 // Finally, if the node is now dead, remove it from the graph. The node
233 // may not be dead if the replacement process recursively simplified to
234 // something else needing this node.
235 if (TLO.Old.Val->use_empty()) {
236 removeFromWorkList(TLO.Old.Val);
237 DAG.DeleteNode(TLO.Old.Val);
242 /// visit - call the node-specific routine that knows how to fold each
243 /// particular type of node.
244 SDOperand visit(SDNode *N);
246 // Visitation implementation - Implement dag node combining for different
247 // node types. The semantics are as follows:
249 // SDOperand.Val == 0 - No change was made
250 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
251 // otherwise - N should be replaced by the returned Operand.
253 SDOperand visitTokenFactor(SDNode *N);
254 SDOperand visitADD(SDNode *N);
255 SDOperand visitSUB(SDNode *N);
256 SDOperand visitMUL(SDNode *N);
257 SDOperand visitSDIV(SDNode *N);
258 SDOperand visitUDIV(SDNode *N);
259 SDOperand visitSREM(SDNode *N);
260 SDOperand visitUREM(SDNode *N);
261 SDOperand visitMULHU(SDNode *N);
262 SDOperand visitMULHS(SDNode *N);
263 SDOperand visitAND(SDNode *N);
264 SDOperand visitOR(SDNode *N);
265 SDOperand visitXOR(SDNode *N);
266 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
267 SDOperand visitSHL(SDNode *N);
268 SDOperand visitSRA(SDNode *N);
269 SDOperand visitSRL(SDNode *N);
270 SDOperand visitCTLZ(SDNode *N);
271 SDOperand visitCTTZ(SDNode *N);
272 SDOperand visitCTPOP(SDNode *N);
273 SDOperand visitSELECT(SDNode *N);
274 SDOperand visitSELECT_CC(SDNode *N);
275 SDOperand visitSETCC(SDNode *N);
276 SDOperand visitSIGN_EXTEND(SDNode *N);
277 SDOperand visitZERO_EXTEND(SDNode *N);
278 SDOperand visitANY_EXTEND(SDNode *N);
279 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
280 SDOperand visitTRUNCATE(SDNode *N);
281 SDOperand visitBIT_CONVERT(SDNode *N);
282 SDOperand visitVBIT_CONVERT(SDNode *N);
283 SDOperand visitFADD(SDNode *N);
284 SDOperand visitFSUB(SDNode *N);
285 SDOperand visitFMUL(SDNode *N);
286 SDOperand visitFDIV(SDNode *N);
287 SDOperand visitFREM(SDNode *N);
288 SDOperand visitFCOPYSIGN(SDNode *N);
289 SDOperand visitSINT_TO_FP(SDNode *N);
290 SDOperand visitUINT_TO_FP(SDNode *N);
291 SDOperand visitFP_TO_SINT(SDNode *N);
292 SDOperand visitFP_TO_UINT(SDNode *N);
293 SDOperand visitFP_ROUND(SDNode *N);
294 SDOperand visitFP_ROUND_INREG(SDNode *N);
295 SDOperand visitFP_EXTEND(SDNode *N);
296 SDOperand visitFNEG(SDNode *N);
297 SDOperand visitFABS(SDNode *N);
298 SDOperand visitBRCOND(SDNode *N);
299 SDOperand visitBR_CC(SDNode *N);
300 SDOperand visitLOAD(SDNode *N);
301 SDOperand visitLOADX(SDNode *N);
302 SDOperand visitSTORE(SDNode *N);
303 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
304 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
305 SDOperand visitVBUILD_VECTOR(SDNode *N);
306 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
307 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
309 SDOperand XformToShuffleWithZero(SDNode *N);
310 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
312 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
313 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
314 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
315 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
316 SDOperand N3, ISD::CondCode CC);
317 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
318 ISD::CondCode Cond, bool foldBooleans = true);
319 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
320 SDOperand BuildSDIV(SDNode *N);
321 SDOperand BuildUDIV(SDNode *N);
322 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
324 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
325 /// looking for aliasing nodes and adding them to the Aliases vector.
326 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
327 SmallVector<SDOperand, 8> &Aliases);
329 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
330 /// looking for a better chain (aliasing node.)
331 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
334 DAGCombiner(SelectionDAG &D)
335 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
337 /// Run - runs the dag combiner on all nodes in the work list
338 void Run(bool RunningAfterLegalize);
342 //===----------------------------------------------------------------------===//
343 // TargetLowering::DAGCombinerInfo implementation
344 //===----------------------------------------------------------------------===//
346 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
347 ((DAGCombiner*)DC)->AddToWorkList(N);
350 SDOperand TargetLowering::DAGCombinerInfo::
351 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
352 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
355 SDOperand TargetLowering::DAGCombinerInfo::
356 CombineTo(SDNode *N, SDOperand Res) {
357 return ((DAGCombiner*)DC)->CombineTo(N, Res);
361 SDOperand TargetLowering::DAGCombinerInfo::
362 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
363 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
369 //===----------------------------------------------------------------------===//
372 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
373 // that selects between the values 1 and 0, making it equivalent to a setcc.
374 // Also, set the incoming LHS, RHS, and CC references to the appropriate
375 // nodes based on the type of node we are checking. This simplifies life a
376 // bit for the callers.
377 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
379 if (N.getOpcode() == ISD::SETCC) {
380 LHS = N.getOperand(0);
381 RHS = N.getOperand(1);
382 CC = N.getOperand(2);
385 if (N.getOpcode() == ISD::SELECT_CC &&
386 N.getOperand(2).getOpcode() == ISD::Constant &&
387 N.getOperand(3).getOpcode() == ISD::Constant &&
388 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
389 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
390 LHS = N.getOperand(0);
391 RHS = N.getOperand(1);
392 CC = N.getOperand(4);
398 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
399 // one use. If this is true, it allows the users to invert the operation for
400 // free when it is profitable to do so.
401 static bool isOneUseSetCC(SDOperand N) {
402 SDOperand N0, N1, N2;
403 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
408 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
409 MVT::ValueType VT = N0.getValueType();
410 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
411 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
412 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
413 if (isa<ConstantSDNode>(N1)) {
414 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
415 AddToWorkList(OpNode.Val);
416 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
417 } else if (N0.hasOneUse()) {
418 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
419 AddToWorkList(OpNode.Val);
420 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
423 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
424 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
425 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
426 if (isa<ConstantSDNode>(N0)) {
427 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
428 AddToWorkList(OpNode.Val);
429 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
430 } else if (N1.hasOneUse()) {
431 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
432 AddToWorkList(OpNode.Val);
433 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
439 void DAGCombiner::Run(bool RunningAfterLegalize) {
440 // set the instance variable, so that the various visit routines may use it.
441 AfterLegalize = RunningAfterLegalize;
443 // Add all the dag nodes to the worklist.
444 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
445 E = DAG.allnodes_end(); I != E; ++I)
446 WorkList.push_back(I);
448 // Create a dummy node (which is not added to allnodes), that adds a reference
449 // to the root node, preventing it from being deleted, and tracking any
450 // changes of the root.
451 HandleSDNode Dummy(DAG.getRoot());
454 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
455 TargetLowering::DAGCombinerInfo
456 DagCombineInfo(DAG, !RunningAfterLegalize, this);
458 // while the worklist isn't empty, inspect the node on the end of it and
459 // try and combine it.
460 while (!WorkList.empty()) {
461 SDNode *N = WorkList.back();
464 // If N has no uses, it is dead. Make sure to revisit all N's operands once
465 // N is deleted from the DAG, since they too may now be dead or may have a
466 // reduced number of uses, allowing other xforms.
467 if (N->use_empty() && N != &Dummy) {
468 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
469 AddToWorkList(N->getOperand(i).Val);
475 SDOperand RV = visit(N);
477 // If nothing happened, try a target-specific DAG combine.
479 assert(N->getOpcode() != ISD::DELETED_NODE &&
480 "Node was deleted but visit returned NULL!");
481 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
482 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
483 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
488 // If we get back the same node we passed in, rather than a new node or
489 // zero, we know that the node must have defined multiple values and
490 // CombineTo was used. Since CombineTo takes care of the worklist
491 // mechanics for us, we have no work to do in this case.
493 assert(N->getOpcode() != ISD::DELETED_NODE &&
494 RV.Val->getOpcode() != ISD::DELETED_NODE &&
495 "Node was deleted but visit returned new node!");
497 DEBUG(std::cerr << "\nReplacing.3 "; N->dump();
498 std::cerr << "\nWith: "; RV.Val->dump(&DAG);
500 std::vector<SDNode*> NowDead;
501 if (N->getNumValues() == RV.Val->getNumValues())
502 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
504 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
506 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
509 // Push the new node and any users onto the worklist
510 AddToWorkList(RV.Val);
511 AddUsersToWorkList(RV.Val);
513 // Nodes can be reintroduced into the worklist. Make sure we do not
514 // process a node that has been replaced.
515 removeFromWorkList(N);
516 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
517 removeFromWorkList(NowDead[i]);
519 // Finally, since the node is now dead, remove it from the graph.
525 // If the root changed (e.g. it was a dead load, update the root).
526 DAG.setRoot(Dummy.getValue());
529 SDOperand DAGCombiner::visit(SDNode *N) {
530 switch(N->getOpcode()) {
532 case ISD::TokenFactor: return visitTokenFactor(N);
533 case ISD::ADD: return visitADD(N);
534 case ISD::SUB: return visitSUB(N);
535 case ISD::MUL: return visitMUL(N);
536 case ISD::SDIV: return visitSDIV(N);
537 case ISD::UDIV: return visitUDIV(N);
538 case ISD::SREM: return visitSREM(N);
539 case ISD::UREM: return visitUREM(N);
540 case ISD::MULHU: return visitMULHU(N);
541 case ISD::MULHS: return visitMULHS(N);
542 case ISD::AND: return visitAND(N);
543 case ISD::OR: return visitOR(N);
544 case ISD::XOR: return visitXOR(N);
545 case ISD::SHL: return visitSHL(N);
546 case ISD::SRA: return visitSRA(N);
547 case ISD::SRL: return visitSRL(N);
548 case ISD::CTLZ: return visitCTLZ(N);
549 case ISD::CTTZ: return visitCTTZ(N);
550 case ISD::CTPOP: return visitCTPOP(N);
551 case ISD::SELECT: return visitSELECT(N);
552 case ISD::SELECT_CC: return visitSELECT_CC(N);
553 case ISD::SETCC: return visitSETCC(N);
554 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
555 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
556 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
557 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
558 case ISD::TRUNCATE: return visitTRUNCATE(N);
559 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
560 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
561 case ISD::FADD: return visitFADD(N);
562 case ISD::FSUB: return visitFSUB(N);
563 case ISD::FMUL: return visitFMUL(N);
564 case ISD::FDIV: return visitFDIV(N);
565 case ISD::FREM: return visitFREM(N);
566 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
567 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
568 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
569 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
570 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
571 case ISD::FP_ROUND: return visitFP_ROUND(N);
572 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
573 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
574 case ISD::FNEG: return visitFNEG(N);
575 case ISD::FABS: return visitFABS(N);
576 case ISD::BRCOND: return visitBRCOND(N);
577 case ISD::BR_CC: return visitBR_CC(N);
578 case ISD::LOAD: return visitLOAD(N);
579 case ISD::LOADX: return visitLOADX(N);
580 case ISD::STORE: return visitSTORE(N);
581 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
582 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
583 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
584 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
585 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
586 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
587 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
588 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
589 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
590 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
591 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
592 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
593 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
598 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
599 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
600 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
601 bool Changed = false; // If we should replace this token factor.
603 // Start out with this token factor.
606 // Iterate through token factors. The TFs grows a new token factors are
608 for (unsigned i = 0; i < TFs.size(); ++i) {
611 // Check each of the operands.
612 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
613 SDOperand Op = TF->getOperand(i);
615 switch (Op.getOpcode()) {
616 case ISD::EntryToken:
617 // Entry tokens don't need to be added to the list. They are
622 case ISD::TokenFactor:
623 if ((CombinerAA || Op.hasOneUse()) &&
624 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
625 // Queue up for processing.
626 TFs.push_back(Op.Val);
627 // Clean up in case the token factor is removed.
628 AddToWorkList(Op.Val);
635 // Only add if not there prior.
636 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
645 // If we've change things around then replace token factor.
647 if (Ops.size() == 0) {
648 // The entry token is the only possible outcome.
649 Result = DAG.getEntryNode();
651 // New and improved token factor.
652 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
659 SDOperand DAGCombiner::visitADD(SDNode *N) {
660 SDOperand N0 = N->getOperand(0);
661 SDOperand N1 = N->getOperand(1);
662 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
663 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
664 MVT::ValueType VT = N0.getValueType();
666 // fold (add c1, c2) -> c1+c2
668 return DAG.getNode(ISD::ADD, VT, N0, N1);
669 // canonicalize constant to RHS
671 return DAG.getNode(ISD::ADD, VT, N1, N0);
672 // fold (add x, 0) -> x
673 if (N1C && N1C->isNullValue())
675 // fold ((c1-A)+c2) -> (c1+c2)-A
676 if (N1C && N0.getOpcode() == ISD::SUB)
677 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
678 return DAG.getNode(ISD::SUB, VT,
679 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
682 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
685 // fold ((0-A) + B) -> B-A
686 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
687 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
688 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
689 // fold (A + (0-B)) -> A-B
690 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
691 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
692 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
693 // fold (A+(B-A)) -> B
694 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
695 return N1.getOperand(0);
697 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
698 return SDOperand(N, 0);
700 // fold (a+b) -> (a|b) iff a and b share no bits.
701 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
702 uint64_t LHSZero, LHSOne;
703 uint64_t RHSZero, RHSOne;
704 uint64_t Mask = MVT::getIntVTBitMask(VT);
705 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
707 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
709 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
710 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
711 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
712 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
713 return DAG.getNode(ISD::OR, VT, N0, N1);
720 SDOperand DAGCombiner::visitSUB(SDNode *N) {
721 SDOperand N0 = N->getOperand(0);
722 SDOperand N1 = N->getOperand(1);
723 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
724 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
725 MVT::ValueType VT = N0.getValueType();
727 // fold (sub x, x) -> 0
729 return DAG.getConstant(0, N->getValueType(0));
730 // fold (sub c1, c2) -> c1-c2
732 return DAG.getNode(ISD::SUB, VT, N0, N1);
733 // fold (sub x, c) -> (add x, -c)
735 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
737 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
738 return N0.getOperand(1);
740 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
741 return N0.getOperand(0);
745 SDOperand DAGCombiner::visitMUL(SDNode *N) {
746 SDOperand N0 = N->getOperand(0);
747 SDOperand N1 = N->getOperand(1);
748 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
749 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
750 MVT::ValueType VT = N0.getValueType();
752 // fold (mul c1, c2) -> c1*c2
754 return DAG.getNode(ISD::MUL, VT, N0, N1);
755 // canonicalize constant to RHS
757 return DAG.getNode(ISD::MUL, VT, N1, N0);
758 // fold (mul x, 0) -> 0
759 if (N1C && N1C->isNullValue())
761 // fold (mul x, -1) -> 0-x
762 if (N1C && N1C->isAllOnesValue())
763 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
764 // fold (mul x, (1 << c)) -> x << c
765 if (N1C && isPowerOf2_64(N1C->getValue()))
766 return DAG.getNode(ISD::SHL, VT, N0,
767 DAG.getConstant(Log2_64(N1C->getValue()),
768 TLI.getShiftAmountTy()));
769 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
770 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
771 // FIXME: If the input is something that is easily negated (e.g. a
772 // single-use add), we should put the negate there.
773 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
774 DAG.getNode(ISD::SHL, VT, N0,
775 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
776 TLI.getShiftAmountTy())));
779 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
780 if (N1C && N0.getOpcode() == ISD::SHL &&
781 isa<ConstantSDNode>(N0.getOperand(1))) {
782 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
783 AddToWorkList(C3.Val);
784 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
787 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
790 SDOperand Sh(0,0), Y(0,0);
791 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
792 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
793 N0.Val->hasOneUse()) {
795 } else if (N1.getOpcode() == ISD::SHL &&
796 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
800 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
801 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
804 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
805 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
806 isa<ConstantSDNode>(N0.getOperand(1))) {
807 return DAG.getNode(ISD::ADD, VT,
808 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
809 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
813 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
819 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
820 SDOperand N0 = N->getOperand(0);
821 SDOperand N1 = N->getOperand(1);
822 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
823 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
824 MVT::ValueType VT = N->getValueType(0);
826 // fold (sdiv c1, c2) -> c1/c2
827 if (N0C && N1C && !N1C->isNullValue())
828 return DAG.getNode(ISD::SDIV, VT, N0, N1);
829 // fold (sdiv X, 1) -> X
830 if (N1C && N1C->getSignExtended() == 1LL)
832 // fold (sdiv X, -1) -> 0-X
833 if (N1C && N1C->isAllOnesValue())
834 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
835 // If we know the sign bits of both operands are zero, strength reduce to a
836 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
837 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
838 if (TLI.MaskedValueIsZero(N1, SignBit) &&
839 TLI.MaskedValueIsZero(N0, SignBit))
840 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
841 // fold (sdiv X, pow2) -> simple ops after legalize
842 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
843 (isPowerOf2_64(N1C->getSignExtended()) ||
844 isPowerOf2_64(-N1C->getSignExtended()))) {
845 // If dividing by powers of two is cheap, then don't perform the following
847 if (TLI.isPow2DivCheap())
849 int64_t pow2 = N1C->getSignExtended();
850 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
851 unsigned lg2 = Log2_64(abs2);
852 // Splat the sign bit into the register
853 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
854 DAG.getConstant(MVT::getSizeInBits(VT)-1,
855 TLI.getShiftAmountTy()));
856 AddToWorkList(SGN.Val);
857 // Add (N0 < 0) ? abs2 - 1 : 0;
858 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
859 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
860 TLI.getShiftAmountTy()));
861 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
862 AddToWorkList(SRL.Val);
863 AddToWorkList(ADD.Val); // Divide by pow2
864 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
865 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
866 // If we're dividing by a positive value, we're done. Otherwise, we must
867 // negate the result.
870 AddToWorkList(SRA.Val);
871 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
873 // if integer divide is expensive and we satisfy the requirements, emit an
874 // alternate sequence.
875 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
876 !TLI.isIntDivCheap()) {
877 SDOperand Op = BuildSDIV(N);
878 if (Op.Val) return Op;
883 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
884 SDOperand N0 = N->getOperand(0);
885 SDOperand N1 = N->getOperand(1);
886 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
887 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
888 MVT::ValueType VT = N->getValueType(0);
890 // fold (udiv c1, c2) -> c1/c2
891 if (N0C && N1C && !N1C->isNullValue())
892 return DAG.getNode(ISD::UDIV, VT, N0, N1);
893 // fold (udiv x, (1 << c)) -> x >>u c
894 if (N1C && isPowerOf2_64(N1C->getValue()))
895 return DAG.getNode(ISD::SRL, VT, N0,
896 DAG.getConstant(Log2_64(N1C->getValue()),
897 TLI.getShiftAmountTy()));
898 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
899 if (N1.getOpcode() == ISD::SHL) {
900 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
901 if (isPowerOf2_64(SHC->getValue())) {
902 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
903 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
904 DAG.getConstant(Log2_64(SHC->getValue()),
906 AddToWorkList(Add.Val);
907 return DAG.getNode(ISD::SRL, VT, N0, Add);
911 // fold (udiv x, c) -> alternate
912 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
913 SDOperand Op = BuildUDIV(N);
914 if (Op.Val) return Op;
919 SDOperand DAGCombiner::visitSREM(SDNode *N) {
920 SDOperand N0 = N->getOperand(0);
921 SDOperand N1 = N->getOperand(1);
922 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
923 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
924 MVT::ValueType VT = N->getValueType(0);
926 // fold (srem c1, c2) -> c1%c2
927 if (N0C && N1C && !N1C->isNullValue())
928 return DAG.getNode(ISD::SREM, VT, N0, N1);
929 // If we know the sign bits of both operands are zero, strength reduce to a
930 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
931 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
932 if (TLI.MaskedValueIsZero(N1, SignBit) &&
933 TLI.MaskedValueIsZero(N0, SignBit))
934 return DAG.getNode(ISD::UREM, VT, N0, N1);
938 SDOperand DAGCombiner::visitUREM(SDNode *N) {
939 SDOperand N0 = N->getOperand(0);
940 SDOperand N1 = N->getOperand(1);
941 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
942 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
943 MVT::ValueType VT = N->getValueType(0);
945 // fold (urem c1, c2) -> c1%c2
946 if (N0C && N1C && !N1C->isNullValue())
947 return DAG.getNode(ISD::UREM, VT, N0, N1);
948 // fold (urem x, pow2) -> (and x, pow2-1)
949 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
950 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
951 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
952 if (N1.getOpcode() == ISD::SHL) {
953 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
954 if (isPowerOf2_64(SHC->getValue())) {
955 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
956 AddToWorkList(Add.Val);
957 return DAG.getNode(ISD::AND, VT, N0, Add);
964 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
965 SDOperand N0 = N->getOperand(0);
966 SDOperand N1 = N->getOperand(1);
967 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
969 // fold (mulhs x, 0) -> 0
970 if (N1C && N1C->isNullValue())
972 // fold (mulhs x, 1) -> (sra x, size(x)-1)
973 if (N1C && N1C->getValue() == 1)
974 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
975 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
976 TLI.getShiftAmountTy()));
980 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
981 SDOperand N0 = N->getOperand(0);
982 SDOperand N1 = N->getOperand(1);
983 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
985 // fold (mulhu x, 0) -> 0
986 if (N1C && N1C->isNullValue())
988 // fold (mulhu x, 1) -> 0
989 if (N1C && N1C->getValue() == 1)
990 return DAG.getConstant(0, N0.getValueType());
994 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
995 /// two operands of the same opcode, try to simplify it.
996 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
997 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
998 MVT::ValueType VT = N0.getValueType();
999 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1001 // For each of OP in AND/OR/XOR:
1002 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1003 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1004 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1005 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1006 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1007 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1008 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1009 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1010 N0.getOperand(0).getValueType(),
1011 N0.getOperand(0), N1.getOperand(0));
1012 AddToWorkList(ORNode.Val);
1013 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1016 // For each of OP in SHL/SRL/SRA/AND...
1017 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1018 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1019 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1020 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1021 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1022 N0.getOperand(1) == N1.getOperand(1)) {
1023 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1024 N0.getOperand(0).getValueType(),
1025 N0.getOperand(0), N1.getOperand(0));
1026 AddToWorkList(ORNode.Val);
1027 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1033 SDOperand DAGCombiner::visitAND(SDNode *N) {
1034 SDOperand N0 = N->getOperand(0);
1035 SDOperand N1 = N->getOperand(1);
1036 SDOperand LL, LR, RL, RR, CC0, CC1;
1037 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1038 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1039 MVT::ValueType VT = N1.getValueType();
1040 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1042 // fold (and c1, c2) -> c1&c2
1044 return DAG.getNode(ISD::AND, VT, N0, N1);
1045 // canonicalize constant to RHS
1047 return DAG.getNode(ISD::AND, VT, N1, N0);
1048 // fold (and x, -1) -> x
1049 if (N1C && N1C->isAllOnesValue())
1051 // if (and x, c) is known to be zero, return 0
1052 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1053 return DAG.getConstant(0, VT);
1055 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1058 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1059 if (N1C && N0.getOpcode() == ISD::OR)
1060 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1061 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1063 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1064 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1065 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1066 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1067 ~N1C->getValue() & InMask)) {
1068 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1071 // Replace uses of the AND with uses of the Zero extend node.
1074 // We actually want to replace all uses of the any_extend with the
1075 // zero_extend, to avoid duplicating things. This will later cause this
1076 // AND to be folded.
1077 CombineTo(N0.Val, Zext);
1078 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1081 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1082 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1083 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1084 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1086 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1087 MVT::isInteger(LL.getValueType())) {
1088 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1089 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1090 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1091 AddToWorkList(ORNode.Val);
1092 return DAG.getSetCC(VT, ORNode, LR, Op1);
1094 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1095 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1096 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1097 AddToWorkList(ANDNode.Val);
1098 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1100 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1101 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1102 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1103 AddToWorkList(ORNode.Val);
1104 return DAG.getSetCC(VT, ORNode, LR, Op1);
1107 // canonicalize equivalent to ll == rl
1108 if (LL == RR && LR == RL) {
1109 Op1 = ISD::getSetCCSwappedOperands(Op1);
1112 if (LL == RL && LR == RR) {
1113 bool isInteger = MVT::isInteger(LL.getValueType());
1114 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1115 if (Result != ISD::SETCC_INVALID)
1116 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1120 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1121 if (N0.getOpcode() == N1.getOpcode()) {
1122 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1123 if (Tmp.Val) return Tmp;
1126 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1127 // fold (and (sra)) -> (and (srl)) when possible.
1128 if (!MVT::isVector(VT) &&
1129 SimplifyDemandedBits(SDOperand(N, 0)))
1130 return SDOperand(N, 0);
1131 // fold (zext_inreg (extload x)) -> (zextload x)
1132 if (ISD::isEXTLoad(N0.Val)) {
1133 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1134 // If we zero all the possible extended bits, then we can turn this into
1135 // a zextload if we are running before legalize or the operation is legal.
1136 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1137 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1138 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1139 N0.getOperand(1), N0.getOperand(2),
1142 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1143 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1146 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1147 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
1148 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1149 // If we zero all the possible extended bits, then we can turn this into
1150 // a zextload if we are running before legalize or the operation is legal.
1151 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1152 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1153 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1154 N0.getOperand(1), N0.getOperand(2),
1157 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1158 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1162 // fold (and (load x), 255) -> (zextload x, i8)
1163 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1165 (N0.getOpcode() == ISD::LOAD || ISD::isEXTLoad(N0.Val) ||
1166 ISD::isZEXTLoad(N0.Val)) &&
1168 MVT::ValueType EVT, LoadedVT;
1169 if (N1C->getValue() == 255)
1171 else if (N1C->getValue() == 65535)
1173 else if (N1C->getValue() == ~0U)
1178 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT :
1179 cast<VTSDNode>(N0.getOperand(3))->getVT();
1180 if (EVT != MVT::Other && LoadedVT > EVT &&
1181 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1182 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1183 // For big endian targets, we need to add an offset to the pointer to load
1184 // the correct bytes. For little endian systems, we merely need to read
1185 // fewer bytes from the same pointer.
1187 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1188 SDOperand NewPtr = N0.getOperand(1);
1189 if (!TLI.isLittleEndian())
1190 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1191 DAG.getConstant(PtrOff, PtrType));
1192 AddToWorkList(NewPtr.Val);
1194 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr,
1195 N0.getOperand(2), EVT);
1197 CombineTo(N0.Val, Load, Load.getValue(1));
1198 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1205 SDOperand DAGCombiner::visitOR(SDNode *N) {
1206 SDOperand N0 = N->getOperand(0);
1207 SDOperand N1 = N->getOperand(1);
1208 SDOperand LL, LR, RL, RR, CC0, CC1;
1209 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1210 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1211 MVT::ValueType VT = N1.getValueType();
1212 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1214 // fold (or c1, c2) -> c1|c2
1216 return DAG.getNode(ISD::OR, VT, N0, N1);
1217 // canonicalize constant to RHS
1219 return DAG.getNode(ISD::OR, VT, N1, N0);
1220 // fold (or x, 0) -> x
1221 if (N1C && N1C->isNullValue())
1223 // fold (or x, -1) -> -1
1224 if (N1C && N1C->isAllOnesValue())
1226 // fold (or x, c) -> c iff (x & ~c) == 0
1228 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1231 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1234 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1235 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1236 isa<ConstantSDNode>(N0.getOperand(1))) {
1237 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1238 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1240 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1242 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1243 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1244 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1245 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1247 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1248 MVT::isInteger(LL.getValueType())) {
1249 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1250 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1251 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1252 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1253 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1254 AddToWorkList(ORNode.Val);
1255 return DAG.getSetCC(VT, ORNode, LR, Op1);
1257 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1258 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1259 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1260 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1261 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1262 AddToWorkList(ANDNode.Val);
1263 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1266 // canonicalize equivalent to ll == rl
1267 if (LL == RR && LR == RL) {
1268 Op1 = ISD::getSetCCSwappedOperands(Op1);
1271 if (LL == RL && LR == RR) {
1272 bool isInteger = MVT::isInteger(LL.getValueType());
1273 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1274 if (Result != ISD::SETCC_INVALID)
1275 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1279 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1280 if (N0.getOpcode() == N1.getOpcode()) {
1281 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1282 if (Tmp.Val) return Tmp;
1285 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1286 if (N0.getOpcode() == ISD::AND &&
1287 N1.getOpcode() == ISD::AND &&
1288 N0.getOperand(1).getOpcode() == ISD::Constant &&
1289 N1.getOperand(1).getOpcode() == ISD::Constant &&
1290 // Don't increase # computations.
1291 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1292 // We can only do this xform if we know that bits from X that are set in C2
1293 // but not in C1 are already zero. Likewise for Y.
1294 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1295 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1297 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1298 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1299 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1300 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1305 // See if this is some rotate idiom.
1306 if (SDNode *Rot = MatchRotate(N0, N1))
1307 return SDOperand(Rot, 0);
1313 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1314 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1315 if (Op.getOpcode() == ISD::AND) {
1316 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1317 Mask = Op.getOperand(1);
1318 Op = Op.getOperand(0);
1324 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1332 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1333 // idioms for rotate, and if the target supports rotation instructions, generate
1335 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1336 // Must be a legal type. Expanded an promoted things won't work with rotates.
1337 MVT::ValueType VT = LHS.getValueType();
1338 if (!TLI.isTypeLegal(VT)) return 0;
1340 // The target must have at least one rotate flavor.
1341 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1342 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1343 if (!HasROTL && !HasROTR) return 0;
1345 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1346 SDOperand LHSShift; // The shift.
1347 SDOperand LHSMask; // AND value if any.
1348 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1349 return 0; // Not part of a rotate.
1351 SDOperand RHSShift; // The shift.
1352 SDOperand RHSMask; // AND value if any.
1353 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1354 return 0; // Not part of a rotate.
1356 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1357 return 0; // Not shifting the same value.
1359 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1360 return 0; // Shifts must disagree.
1362 // Canonicalize shl to left side in a shl/srl pair.
1363 if (RHSShift.getOpcode() == ISD::SHL) {
1364 std::swap(LHS, RHS);
1365 std::swap(LHSShift, RHSShift);
1366 std::swap(LHSMask , RHSMask );
1369 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1371 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1372 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1373 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1374 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1375 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1376 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1377 if ((LShVal + RShVal) != OpSizeInBits)
1382 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1383 LHSShift.getOperand(1));
1385 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1386 RHSShift.getOperand(1));
1388 // If there is an AND of either shifted operand, apply it to the result.
1389 if (LHSMask.Val || RHSMask.Val) {
1390 uint64_t Mask = MVT::getIntVTBitMask(VT);
1393 uint64_t RHSBits = (1ULL << LShVal)-1;
1394 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1397 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1398 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1401 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1407 // If there is a mask here, and we have a variable shift, we can't be sure
1408 // that we're masking out the right stuff.
1409 if (LHSMask.Val || RHSMask.Val)
1412 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1413 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1414 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1415 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1416 if (ConstantSDNode *SUBC =
1417 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1418 if (SUBC->getValue() == OpSizeInBits)
1420 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1421 LHSShift.getOperand(1)).Val;
1423 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1424 LHSShift.getOperand(1)).Val;
1428 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1429 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1430 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1431 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1432 if (ConstantSDNode *SUBC =
1433 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1434 if (SUBC->getValue() == OpSizeInBits)
1436 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1437 LHSShift.getOperand(1)).Val;
1439 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1440 RHSShift.getOperand(1)).Val;
1448 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1449 SDOperand N0 = N->getOperand(0);
1450 SDOperand N1 = N->getOperand(1);
1451 SDOperand LHS, RHS, CC;
1452 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1453 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1454 MVT::ValueType VT = N0.getValueType();
1456 // fold (xor c1, c2) -> c1^c2
1458 return DAG.getNode(ISD::XOR, VT, N0, N1);
1459 // canonicalize constant to RHS
1461 return DAG.getNode(ISD::XOR, VT, N1, N0);
1462 // fold (xor x, 0) -> x
1463 if (N1C && N1C->isNullValue())
1466 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1469 // fold !(x cc y) -> (x !cc y)
1470 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1471 bool isInt = MVT::isInteger(LHS.getValueType());
1472 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1474 if (N0.getOpcode() == ISD::SETCC)
1475 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1476 if (N0.getOpcode() == ISD::SELECT_CC)
1477 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1478 assert(0 && "Unhandled SetCC Equivalent!");
1481 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1482 if (N1C && N1C->getValue() == 1 &&
1483 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1484 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1485 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1486 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1487 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1488 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1489 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1490 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1493 // fold !(x or y) -> (!x and !y) iff x or y are constants
1494 if (N1C && N1C->isAllOnesValue() &&
1495 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1496 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1497 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1498 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1499 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1500 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1501 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1502 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1505 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1506 if (N1C && N0.getOpcode() == ISD::XOR) {
1507 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1508 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1510 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1511 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1513 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1514 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1516 // fold (xor x, x) -> 0
1518 if (!MVT::isVector(VT)) {
1519 return DAG.getConstant(0, VT);
1520 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1521 // Produce a vector of zeros.
1522 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1523 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1524 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1528 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1529 if (N0.getOpcode() == N1.getOpcode()) {
1530 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1531 if (Tmp.Val) return Tmp;
1534 // Simplify the expression using non-local knowledge.
1535 if (!MVT::isVector(VT) &&
1536 SimplifyDemandedBits(SDOperand(N, 0)))
1537 return SDOperand(N, 0);
1542 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1543 SDOperand N0 = N->getOperand(0);
1544 SDOperand N1 = N->getOperand(1);
1545 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1546 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1547 MVT::ValueType VT = N0.getValueType();
1548 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1550 // fold (shl c1, c2) -> c1<<c2
1552 return DAG.getNode(ISD::SHL, VT, N0, N1);
1553 // fold (shl 0, x) -> 0
1554 if (N0C && N0C->isNullValue())
1556 // fold (shl x, c >= size(x)) -> undef
1557 if (N1C && N1C->getValue() >= OpSizeInBits)
1558 return DAG.getNode(ISD::UNDEF, VT);
1559 // fold (shl x, 0) -> x
1560 if (N1C && N1C->isNullValue())
1562 // if (shl x, c) is known to be zero, return 0
1563 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1564 return DAG.getConstant(0, VT);
1565 if (SimplifyDemandedBits(SDOperand(N, 0)))
1566 return SDOperand(N, 0);
1567 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1568 if (N1C && N0.getOpcode() == ISD::SHL &&
1569 N0.getOperand(1).getOpcode() == ISD::Constant) {
1570 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1571 uint64_t c2 = N1C->getValue();
1572 if (c1 + c2 > OpSizeInBits)
1573 return DAG.getConstant(0, VT);
1574 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1575 DAG.getConstant(c1 + c2, N1.getValueType()));
1577 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1578 // (srl (and x, -1 << c1), c1-c2)
1579 if (N1C && N0.getOpcode() == ISD::SRL &&
1580 N0.getOperand(1).getOpcode() == ISD::Constant) {
1581 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1582 uint64_t c2 = N1C->getValue();
1583 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1584 DAG.getConstant(~0ULL << c1, VT));
1586 return DAG.getNode(ISD::SHL, VT, Mask,
1587 DAG.getConstant(c2-c1, N1.getValueType()));
1589 return DAG.getNode(ISD::SRL, VT, Mask,
1590 DAG.getConstant(c1-c2, N1.getValueType()));
1592 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1593 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1594 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1595 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1596 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1597 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1598 isa<ConstantSDNode>(N0.getOperand(1))) {
1599 return DAG.getNode(ISD::ADD, VT,
1600 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1601 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1606 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1607 SDOperand N0 = N->getOperand(0);
1608 SDOperand N1 = N->getOperand(1);
1609 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1610 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1611 MVT::ValueType VT = N0.getValueType();
1613 // fold (sra c1, c2) -> c1>>c2
1615 return DAG.getNode(ISD::SRA, VT, N0, N1);
1616 // fold (sra 0, x) -> 0
1617 if (N0C && N0C->isNullValue())
1619 // fold (sra -1, x) -> -1
1620 if (N0C && N0C->isAllOnesValue())
1622 // fold (sra x, c >= size(x)) -> undef
1623 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1624 return DAG.getNode(ISD::UNDEF, VT);
1625 // fold (sra x, 0) -> x
1626 if (N1C && N1C->isNullValue())
1628 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1630 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1631 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1634 default: EVT = MVT::Other; break;
1635 case 1: EVT = MVT::i1; break;
1636 case 8: EVT = MVT::i8; break;
1637 case 16: EVT = MVT::i16; break;
1638 case 32: EVT = MVT::i32; break;
1640 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1641 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1642 DAG.getValueType(EVT));
1645 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1646 if (N1C && N0.getOpcode() == ISD::SRA) {
1647 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1648 unsigned Sum = N1C->getValue() + C1->getValue();
1649 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1650 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1651 DAG.getConstant(Sum, N1C->getValueType(0)));
1655 // Simplify, based on bits shifted out of the LHS.
1656 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1657 return SDOperand(N, 0);
1660 // If the sign bit is known to be zero, switch this to a SRL.
1661 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1662 return DAG.getNode(ISD::SRL, VT, N0, N1);
1666 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1667 SDOperand N0 = N->getOperand(0);
1668 SDOperand N1 = N->getOperand(1);
1669 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1670 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1671 MVT::ValueType VT = N0.getValueType();
1672 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1674 // fold (srl c1, c2) -> c1 >>u c2
1676 return DAG.getNode(ISD::SRL, VT, N0, N1);
1677 // fold (srl 0, x) -> 0
1678 if (N0C && N0C->isNullValue())
1680 // fold (srl x, c >= size(x)) -> undef
1681 if (N1C && N1C->getValue() >= OpSizeInBits)
1682 return DAG.getNode(ISD::UNDEF, VT);
1683 // fold (srl x, 0) -> x
1684 if (N1C && N1C->isNullValue())
1686 // if (srl x, c) is known to be zero, return 0
1687 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1688 return DAG.getConstant(0, VT);
1689 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1690 if (N1C && N0.getOpcode() == ISD::SRL &&
1691 N0.getOperand(1).getOpcode() == ISD::Constant) {
1692 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1693 uint64_t c2 = N1C->getValue();
1694 if (c1 + c2 > OpSizeInBits)
1695 return DAG.getConstant(0, VT);
1696 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1697 DAG.getConstant(c1 + c2, N1.getValueType()));
1700 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1701 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1702 // Shifting in all undef bits?
1703 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1704 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1705 return DAG.getNode(ISD::UNDEF, VT);
1707 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1708 AddToWorkList(SmallShift.Val);
1709 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1712 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1713 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1714 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1715 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1716 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1718 // If any of the input bits are KnownOne, then the input couldn't be all
1719 // zeros, thus the result of the srl will always be zero.
1720 if (KnownOne) return DAG.getConstant(0, VT);
1722 // If all of the bits input the to ctlz node are known to be zero, then
1723 // the result of the ctlz is "32" and the result of the shift is one.
1724 uint64_t UnknownBits = ~KnownZero & Mask;
1725 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1727 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1728 if ((UnknownBits & (UnknownBits-1)) == 0) {
1729 // Okay, we know that only that the single bit specified by UnknownBits
1730 // could be set on input to the CTLZ node. If this bit is set, the SRL
1731 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1732 // to an SRL,XOR pair, which is likely to simplify more.
1733 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1734 SDOperand Op = N0.getOperand(0);
1736 Op = DAG.getNode(ISD::SRL, VT, Op,
1737 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1738 AddToWorkList(Op.Val);
1740 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1747 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1748 SDOperand N0 = N->getOperand(0);
1749 MVT::ValueType VT = N->getValueType(0);
1751 // fold (ctlz c1) -> c2
1752 if (isa<ConstantSDNode>(N0))
1753 return DAG.getNode(ISD::CTLZ, VT, N0);
1757 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1758 SDOperand N0 = N->getOperand(0);
1759 MVT::ValueType VT = N->getValueType(0);
1761 // fold (cttz c1) -> c2
1762 if (isa<ConstantSDNode>(N0))
1763 return DAG.getNode(ISD::CTTZ, VT, N0);
1767 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1768 SDOperand N0 = N->getOperand(0);
1769 MVT::ValueType VT = N->getValueType(0);
1771 // fold (ctpop c1) -> c2
1772 if (isa<ConstantSDNode>(N0))
1773 return DAG.getNode(ISD::CTPOP, VT, N0);
1777 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1778 SDOperand N0 = N->getOperand(0);
1779 SDOperand N1 = N->getOperand(1);
1780 SDOperand N2 = N->getOperand(2);
1781 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1782 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1783 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1784 MVT::ValueType VT = N->getValueType(0);
1786 // fold select C, X, X -> X
1789 // fold select true, X, Y -> X
1790 if (N0C && !N0C->isNullValue())
1792 // fold select false, X, Y -> Y
1793 if (N0C && N0C->isNullValue())
1795 // fold select C, 1, X -> C | X
1796 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1797 return DAG.getNode(ISD::OR, VT, N0, N2);
1798 // fold select C, 0, X -> ~C & X
1799 // FIXME: this should check for C type == X type, not i1?
1800 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1801 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1802 AddToWorkList(XORNode.Val);
1803 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1805 // fold select C, X, 1 -> ~C | X
1806 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1807 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1808 AddToWorkList(XORNode.Val);
1809 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1811 // fold select C, X, 0 -> C & X
1812 // FIXME: this should check for C type == X type, not i1?
1813 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1814 return DAG.getNode(ISD::AND, VT, N0, N1);
1815 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1816 if (MVT::i1 == VT && N0 == N1)
1817 return DAG.getNode(ISD::OR, VT, N0, N2);
1818 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1819 if (MVT::i1 == VT && N0 == N2)
1820 return DAG.getNode(ISD::AND, VT, N0, N1);
1822 // If we can fold this based on the true/false value, do so.
1823 if (SimplifySelectOps(N, N1, N2))
1824 return SDOperand(N, 0); // Don't revisit N.
1826 // fold selects based on a setcc into other things, such as min/max/abs
1827 if (N0.getOpcode() == ISD::SETCC)
1829 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1830 // having to say they don't support SELECT_CC on every type the DAG knows
1831 // about, since there is no way to mark an opcode illegal at all value types
1832 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1833 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1834 N1, N2, N0.getOperand(2));
1836 return SimplifySelect(N0, N1, N2);
1840 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1841 SDOperand N0 = N->getOperand(0);
1842 SDOperand N1 = N->getOperand(1);
1843 SDOperand N2 = N->getOperand(2);
1844 SDOperand N3 = N->getOperand(3);
1845 SDOperand N4 = N->getOperand(4);
1846 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1847 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1848 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1849 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1851 // fold select_cc lhs, rhs, x, x, cc -> x
1855 // Determine if the condition we're dealing with is constant
1856 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1858 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1859 if (SCCC->getValue())
1860 return N2; // cond always true -> true val
1862 return N3; // cond always false -> false val
1865 // Fold to a simpler select_cc
1866 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1867 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1868 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1871 // If we can fold this based on the true/false value, do so.
1872 if (SimplifySelectOps(N, N2, N3))
1873 return SDOperand(N, 0); // Don't revisit N.
1875 // fold select_cc into other things, such as min/max/abs
1876 return SimplifySelectCC(N0, N1, N2, N3, CC);
1879 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1880 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1881 cast<CondCodeSDNode>(N->getOperand(2))->get());
1884 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1885 SDOperand N0 = N->getOperand(0);
1886 MVT::ValueType VT = N->getValueType(0);
1888 // fold (sext c1) -> c1
1889 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1890 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1892 // fold (sext (sext x)) -> (sext x)
1893 // fold (sext (aext x)) -> (sext x)
1894 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1895 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1897 // fold (sext (truncate x)) -> (sextinreg x).
1898 if (N0.getOpcode() == ISD::TRUNCATE &&
1899 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
1900 N0.getValueType()))) {
1901 SDOperand Op = N0.getOperand(0);
1902 if (Op.getValueType() < VT) {
1903 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1904 } else if (Op.getValueType() > VT) {
1905 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1907 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
1908 DAG.getValueType(N0.getValueType()));
1911 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1912 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1913 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
1914 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1915 N0.getOperand(1), N0.getOperand(2),
1917 CombineTo(N, ExtLoad);
1918 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1919 ExtLoad.getValue(1));
1920 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1923 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1924 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1925 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1926 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1927 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1928 N0.getOperand(1), N0.getOperand(2), EVT);
1929 CombineTo(N, ExtLoad);
1930 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1931 ExtLoad.getValue(1));
1932 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1938 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1939 SDOperand N0 = N->getOperand(0);
1940 MVT::ValueType VT = N->getValueType(0);
1942 // fold (zext c1) -> c1
1943 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1944 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1945 // fold (zext (zext x)) -> (zext x)
1946 // fold (zext (aext x)) -> (zext x)
1947 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1948 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1950 // fold (zext (truncate x)) -> (and x, mask)
1951 if (N0.getOpcode() == ISD::TRUNCATE &&
1952 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
1953 SDOperand Op = N0.getOperand(0);
1954 if (Op.getValueType() < VT) {
1955 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1956 } else if (Op.getValueType() > VT) {
1957 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1959 return DAG.getZeroExtendInReg(Op, N0.getValueType());
1962 // fold (zext (and (trunc x), cst)) -> (and x, cst).
1963 if (N0.getOpcode() == ISD::AND &&
1964 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1965 N0.getOperand(1).getOpcode() == ISD::Constant) {
1966 SDOperand X = N0.getOperand(0).getOperand(0);
1967 if (X.getValueType() < VT) {
1968 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1969 } else if (X.getValueType() > VT) {
1970 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1972 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1973 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
1976 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1977 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1978 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
1979 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1980 N0.getOperand(1), N0.getOperand(2),
1982 CombineTo(N, ExtLoad);
1983 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1984 ExtLoad.getValue(1));
1985 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1988 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1989 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1990 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1991 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1992 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1993 N0.getOperand(1), N0.getOperand(2), EVT);
1994 CombineTo(N, ExtLoad);
1995 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1996 ExtLoad.getValue(1));
1997 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2002 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2003 SDOperand N0 = N->getOperand(0);
2004 MVT::ValueType VT = N->getValueType(0);
2006 // fold (aext c1) -> c1
2007 if (isa<ConstantSDNode>(N0))
2008 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2009 // fold (aext (aext x)) -> (aext x)
2010 // fold (aext (zext x)) -> (zext x)
2011 // fold (aext (sext x)) -> (sext x)
2012 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2013 N0.getOpcode() == ISD::ZERO_EXTEND ||
2014 N0.getOpcode() == ISD::SIGN_EXTEND)
2015 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2017 // fold (aext (truncate x))
2018 if (N0.getOpcode() == ISD::TRUNCATE) {
2019 SDOperand TruncOp = N0.getOperand(0);
2020 if (TruncOp.getValueType() == VT)
2021 return TruncOp; // x iff x size == zext size.
2022 if (TruncOp.getValueType() > VT)
2023 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2024 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2027 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2028 if (N0.getOpcode() == ISD::AND &&
2029 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2030 N0.getOperand(1).getOpcode() == ISD::Constant) {
2031 SDOperand X = N0.getOperand(0).getOperand(0);
2032 if (X.getValueType() < VT) {
2033 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2034 } else if (X.getValueType() > VT) {
2035 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2037 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2038 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2041 // fold (aext (load x)) -> (aext (truncate (extload x)))
2042 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
2043 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2044 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0),
2045 N0.getOperand(1), N0.getOperand(2),
2047 CombineTo(N, ExtLoad);
2048 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2049 ExtLoad.getValue(1));
2050 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2053 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2054 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2055 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2056 if (N0.getOpcode() == ISD::LOADX && N0.hasOneUse()) {
2057 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
2058 unsigned LType = N0.getConstantOperandVal(4);
2059 SDOperand ExtLoad = DAG.getExtLoad((ISD::LoadExtType)LType, VT,
2060 N0.getOperand(0), N0.getOperand(1),
2061 N0.getOperand(2), EVT);
2062 CombineTo(N, ExtLoad);
2063 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2064 ExtLoad.getValue(1));
2065 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2071 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2072 SDOperand N0 = N->getOperand(0);
2073 SDOperand N1 = N->getOperand(1);
2074 MVT::ValueType VT = N->getValueType(0);
2075 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2076 unsigned EVTBits = MVT::getSizeInBits(EVT);
2078 // fold (sext_in_reg c1) -> c1
2079 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2080 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2082 // If the input is already sign extended, just drop the extension.
2083 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2086 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2087 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2088 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2089 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2092 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2093 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2094 return DAG.getZeroExtendInReg(N0, EVT);
2096 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2097 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2098 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2099 if (N0.getOpcode() == ISD::SRL) {
2100 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2101 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2102 // We can turn this into an SRA iff the input to the SRL is already sign
2104 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2105 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2106 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2110 // fold (sext_inreg (extload x)) -> (sextload x)
2111 if (ISD::isEXTLoad(N0.Val) &&
2112 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
2113 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2114 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
2115 N0.getOperand(1), N0.getOperand(2),
2117 CombineTo(N, ExtLoad);
2118 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2119 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2121 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2122 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
2123 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
2124 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2125 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
2126 N0.getOperand(1), N0.getOperand(2),
2128 CombineTo(N, ExtLoad);
2129 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2130 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2135 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2136 SDOperand N0 = N->getOperand(0);
2137 MVT::ValueType VT = N->getValueType(0);
2140 if (N0.getValueType() == N->getValueType(0))
2142 // fold (truncate c1) -> c1
2143 if (isa<ConstantSDNode>(N0))
2144 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2145 // fold (truncate (truncate x)) -> (truncate x)
2146 if (N0.getOpcode() == ISD::TRUNCATE)
2147 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2148 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2149 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2150 N0.getOpcode() == ISD::ANY_EXTEND) {
2151 if (N0.getValueType() < VT)
2152 // if the source is smaller than the dest, we still need an extend
2153 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2154 else if (N0.getValueType() > VT)
2155 // if the source is larger than the dest, than we just need the truncate
2156 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2158 // if the source and dest are the same type, we can drop both the extend
2160 return N0.getOperand(0);
2162 // fold (truncate (load x)) -> (smaller load x)
2163 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
2164 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2165 "Cannot truncate to larger type!");
2166 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2167 // For big endian targets, we need to add an offset to the pointer to load
2168 // the correct bytes. For little endian systems, we merely need to read
2169 // fewer bytes from the same pointer.
2171 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2172 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
2173 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
2174 DAG.getConstant(PtrOff, PtrType));
2175 AddToWorkList(NewPtr.Val);
2176 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
2178 CombineTo(N0.Val, Load, Load.getValue(1));
2179 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2184 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2185 SDOperand N0 = N->getOperand(0);
2186 MVT::ValueType VT = N->getValueType(0);
2188 // If the input is a constant, let getNode() fold it.
2189 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2190 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2191 if (Res.Val != N) return Res;
2194 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2195 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2197 // fold (conv (load x)) -> (load (conv*)x)
2198 // FIXME: These xforms need to know that the resultant load doesn't need a
2199 // higher alignment than the original!
2200 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
2201 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
2204 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2212 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2213 SDOperand N0 = N->getOperand(0);
2214 MVT::ValueType VT = N->getValueType(0);
2216 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2217 // First check to see if this is all constant.
2218 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2219 VT == MVT::Vector) {
2220 bool isSimple = true;
2221 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2222 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2223 N0.getOperand(i).getOpcode() != ISD::Constant &&
2224 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2229 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2230 if (isSimple && !MVT::isVector(DestEltVT)) {
2231 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2238 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2239 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2240 /// destination element value type.
2241 SDOperand DAGCombiner::
2242 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2243 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2245 // If this is already the right type, we're done.
2246 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2248 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2249 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2251 // If this is a conversion of N elements of one type to N elements of another
2252 // type, convert each element. This handles FP<->INT cases.
2253 if (SrcBitSize == DstBitSize) {
2254 SmallVector<SDOperand, 8> Ops;
2255 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2256 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2257 AddToWorkList(Ops.back().Val);
2259 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2260 Ops.push_back(DAG.getValueType(DstEltVT));
2261 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2264 // Otherwise, we're growing or shrinking the elements. To avoid having to
2265 // handle annoying details of growing/shrinking FP values, we convert them to
2267 if (MVT::isFloatingPoint(SrcEltVT)) {
2268 // Convert the input float vector to a int vector where the elements are the
2270 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2271 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2272 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2276 // Now we know the input is an integer vector. If the output is a FP type,
2277 // convert to integer first, then to FP of the right size.
2278 if (MVT::isFloatingPoint(DstEltVT)) {
2279 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2280 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2281 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2283 // Next, convert to FP elements of the same size.
2284 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2287 // Okay, we know the src/dst types are both integers of differing types.
2288 // Handling growing first.
2289 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2290 if (SrcBitSize < DstBitSize) {
2291 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2293 SmallVector<SDOperand, 8> Ops;
2294 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2295 i += NumInputsPerOutput) {
2296 bool isLE = TLI.isLittleEndian();
2297 uint64_t NewBits = 0;
2298 bool EltIsUndef = true;
2299 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2300 // Shift the previously computed bits over.
2301 NewBits <<= SrcBitSize;
2302 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2303 if (Op.getOpcode() == ISD::UNDEF) continue;
2306 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2310 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2312 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2315 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2316 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2317 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2320 // Finally, this must be the case where we are shrinking elements: each input
2321 // turns into multiple outputs.
2322 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2323 SmallVector<SDOperand, 8> Ops;
2324 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2325 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2326 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2327 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2330 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2332 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2333 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2334 OpVal >>= DstBitSize;
2335 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2338 // For big endian targets, swap the order of the pieces of each element.
2339 if (!TLI.isLittleEndian())
2340 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2342 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2343 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2344 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2349 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2350 SDOperand N0 = N->getOperand(0);
2351 SDOperand N1 = N->getOperand(1);
2352 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2353 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2354 MVT::ValueType VT = N->getValueType(0);
2356 // fold (fadd c1, c2) -> c1+c2
2358 return DAG.getNode(ISD::FADD, VT, N0, N1);
2359 // canonicalize constant to RHS
2360 if (N0CFP && !N1CFP)
2361 return DAG.getNode(ISD::FADD, VT, N1, N0);
2362 // fold (A + (-B)) -> A-B
2363 if (N1.getOpcode() == ISD::FNEG)
2364 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2365 // fold ((-A) + B) -> B-A
2366 if (N0.getOpcode() == ISD::FNEG)
2367 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2371 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2372 SDOperand N0 = N->getOperand(0);
2373 SDOperand N1 = N->getOperand(1);
2374 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2375 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2376 MVT::ValueType VT = N->getValueType(0);
2378 // fold (fsub c1, c2) -> c1-c2
2380 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2381 // fold (A-(-B)) -> A+B
2382 if (N1.getOpcode() == ISD::FNEG)
2383 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2387 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2388 SDOperand N0 = N->getOperand(0);
2389 SDOperand N1 = N->getOperand(1);
2390 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2391 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2392 MVT::ValueType VT = N->getValueType(0);
2394 // fold (fmul c1, c2) -> c1*c2
2396 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2397 // canonicalize constant to RHS
2398 if (N0CFP && !N1CFP)
2399 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2400 // fold (fmul X, 2.0) -> (fadd X, X)
2401 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2402 return DAG.getNode(ISD::FADD, VT, N0, N0);
2406 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2407 SDOperand N0 = N->getOperand(0);
2408 SDOperand N1 = N->getOperand(1);
2409 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2410 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2411 MVT::ValueType VT = N->getValueType(0);
2413 // fold (fdiv c1, c2) -> c1/c2
2415 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2419 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2420 SDOperand N0 = N->getOperand(0);
2421 SDOperand N1 = N->getOperand(1);
2422 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2423 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2424 MVT::ValueType VT = N->getValueType(0);
2426 // fold (frem c1, c2) -> fmod(c1,c2)
2428 return DAG.getNode(ISD::FREM, VT, N0, N1);
2432 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2433 SDOperand N0 = N->getOperand(0);
2434 SDOperand N1 = N->getOperand(1);
2435 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2436 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2437 MVT::ValueType VT = N->getValueType(0);
2439 if (N0CFP && N1CFP) // Constant fold
2440 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2443 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2444 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2449 u.d = N1CFP->getValue();
2451 return DAG.getNode(ISD::FABS, VT, N0);
2453 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2456 // copysign(fabs(x), y) -> copysign(x, y)
2457 // copysign(fneg(x), y) -> copysign(x, y)
2458 // copysign(copysign(x,z), y) -> copysign(x, y)
2459 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2460 N0.getOpcode() == ISD::FCOPYSIGN)
2461 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2463 // copysign(x, abs(y)) -> abs(x)
2464 if (N1.getOpcode() == ISD::FABS)
2465 return DAG.getNode(ISD::FABS, VT, N0);
2467 // copysign(x, copysign(y,z)) -> copysign(x, z)
2468 if (N1.getOpcode() == ISD::FCOPYSIGN)
2469 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2471 // copysign(x, fp_extend(y)) -> copysign(x, y)
2472 // copysign(x, fp_round(y)) -> copysign(x, y)
2473 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2474 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2481 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2482 SDOperand N0 = N->getOperand(0);
2483 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2484 MVT::ValueType VT = N->getValueType(0);
2486 // fold (sint_to_fp c1) -> c1fp
2488 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2492 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2493 SDOperand N0 = N->getOperand(0);
2494 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2495 MVT::ValueType VT = N->getValueType(0);
2497 // fold (uint_to_fp c1) -> c1fp
2499 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2503 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2504 SDOperand N0 = N->getOperand(0);
2505 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2506 MVT::ValueType VT = N->getValueType(0);
2508 // fold (fp_to_sint c1fp) -> c1
2510 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2514 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2515 SDOperand N0 = N->getOperand(0);
2516 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2517 MVT::ValueType VT = N->getValueType(0);
2519 // fold (fp_to_uint c1fp) -> c1
2521 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2525 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2526 SDOperand N0 = N->getOperand(0);
2527 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2528 MVT::ValueType VT = N->getValueType(0);
2530 // fold (fp_round c1fp) -> c1fp
2532 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2534 // fold (fp_round (fp_extend x)) -> x
2535 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2536 return N0.getOperand(0);
2538 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2539 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2540 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2541 AddToWorkList(Tmp.Val);
2542 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2548 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2549 SDOperand N0 = N->getOperand(0);
2550 MVT::ValueType VT = N->getValueType(0);
2551 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2552 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2554 // fold (fp_round_inreg c1fp) -> c1fp
2556 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2557 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2562 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2563 SDOperand N0 = N->getOperand(0);
2564 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2565 MVT::ValueType VT = N->getValueType(0);
2567 // fold (fp_extend c1fp) -> c1fp
2569 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2571 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2572 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
2573 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2574 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0),
2575 N0.getOperand(1), N0.getOperand(2),
2577 CombineTo(N, ExtLoad);
2578 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2579 ExtLoad.getValue(1));
2580 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2587 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2588 SDOperand N0 = N->getOperand(0);
2589 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2590 MVT::ValueType VT = N->getValueType(0);
2592 // fold (fneg c1) -> -c1
2594 return DAG.getNode(ISD::FNEG, VT, N0);
2595 // fold (fneg (sub x, y)) -> (sub y, x)
2596 if (N0.getOpcode() == ISD::SUB)
2597 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2598 // fold (fneg (fneg x)) -> x
2599 if (N0.getOpcode() == ISD::FNEG)
2600 return N0.getOperand(0);
2604 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2605 SDOperand N0 = N->getOperand(0);
2606 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2607 MVT::ValueType VT = N->getValueType(0);
2609 // fold (fabs c1) -> fabs(c1)
2611 return DAG.getNode(ISD::FABS, VT, N0);
2612 // fold (fabs (fabs x)) -> (fabs x)
2613 if (N0.getOpcode() == ISD::FABS)
2614 return N->getOperand(0);
2615 // fold (fabs (fneg x)) -> (fabs x)
2616 // fold (fabs (fcopysign x, y)) -> (fabs x)
2617 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2618 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2623 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2624 SDOperand Chain = N->getOperand(0);
2625 SDOperand N1 = N->getOperand(1);
2626 SDOperand N2 = N->getOperand(2);
2627 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2629 // never taken branch, fold to chain
2630 if (N1C && N1C->isNullValue())
2632 // unconditional branch
2633 if (N1C && N1C->getValue() == 1)
2634 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2635 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2637 if (N1.getOpcode() == ISD::SETCC &&
2638 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2639 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2640 N1.getOperand(0), N1.getOperand(1), N2);
2645 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2647 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2648 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2649 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2651 // Use SimplifySetCC to simplify SETCC's.
2652 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2653 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2655 // fold br_cc true, dest -> br dest (unconditional branch)
2656 if (SCCC && SCCC->getValue())
2657 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2659 // fold br_cc false, dest -> unconditional fall through
2660 if (SCCC && SCCC->isNullValue())
2661 return N->getOperand(0);
2662 // fold to a simpler setcc
2663 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2664 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2665 Simp.getOperand(2), Simp.getOperand(0),
2666 Simp.getOperand(1), N->getOperand(4));
2670 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2671 SDOperand Chain = N->getOperand(0);
2672 SDOperand Ptr = N->getOperand(1);
2673 SDOperand SrcValue = N->getOperand(2);
2675 // If there are no uses of the loaded value, change uses of the chain value
2676 // into uses of the chain input (i.e. delete the dead load).
2677 if (N->hasNUsesOfValue(0, 0))
2678 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2680 // If this load is directly stored, replace the load value with the stored
2682 // TODO: Handle store large -> read small portion.
2683 // TODO: Handle TRUNCSTORE/EXTLOAD
2684 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2685 Chain.getOperand(1).getValueType() == N->getValueType(0))
2686 return CombineTo(N, Chain.getOperand(1), Chain);
2689 // Walk up chain skipping non-aliasing memory nodes.
2690 SDOperand BetterChain = FindBetterChain(N, Chain);
2692 // If there is a better chain.
2693 if (Chain != BetterChain) {
2694 // Replace the chain to void dependency.
2695 SDOperand ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
2698 // Create token factor to keep old chain connected.
2699 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
2700 Chain, ReplLoad.getValue(1));
2702 // Replace uses with load result and token factor.
2703 return CombineTo(N, ReplLoad.getValue(0), Token);
2710 /// visitLOADX - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD.
2711 SDOperand DAGCombiner::visitLOADX(SDNode *N) {
2712 SDOperand Chain = N->getOperand(0);
2713 SDOperand Ptr = N->getOperand(1);
2714 SDOperand SrcValue = N->getOperand(2);
2715 SDOperand EVT = N->getOperand(3);
2717 // If there are no uses of the loaded value, change uses of the chain value
2718 // into uses of the chain input (i.e. delete the dead load).
2719 if (N->hasNUsesOfValue(0, 0))
2720 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2725 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2726 SDOperand Chain = N->getOperand(0);
2727 SDOperand Value = N->getOperand(1);
2728 SDOperand Ptr = N->getOperand(2);
2729 SDOperand SrcValue = N->getOperand(3);
2731 // If this is a store that kills a previous store, remove the previous store.
2732 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2733 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2734 // Make sure that these stores are the same value type:
2735 // FIXME: we really care that the second store is >= size of the first.
2736 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2737 // Create a new store of Value that replaces both stores.
2738 SDNode *PrevStore = Chain.Val;
2739 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2741 SDOperand NewStore = DAG.getStore(PrevStore->getOperand(0), Value, Ptr,
2743 CombineTo(N, NewStore); // Nuke this store.
2744 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2745 return SDOperand(N, 0);
2748 // If this is a store of a bit convert, store the input value.
2749 // FIXME: This needs to know that the resultant store does not need a
2750 // higher alignment than the original.
2751 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
2752 return DAG.getStore(Chain, Value.getOperand(0), Ptr, SrcValue);
2756 // If the store ptr is a frame index and the frame index has a use of one
2757 // and this is a return block, then the store is redundant.
2758 if (Ptr.hasOneUse() && isa<FrameIndexSDNode>(Ptr) &&
2759 DAG.getRoot().getOpcode() == ISD::RET) {
2763 // Walk up chain skipping non-aliasing memory nodes.
2764 SDOperand BetterChain = FindBetterChain(N, Chain);
2766 // If there is a better chain.
2767 if (Chain != BetterChain) {
2768 // Replace the chain to avoid dependency.
2769 SDOperand ReplStore = DAG.getStore(BetterChain, Value, Ptr, SrcValue);
2770 // Create token to keep both nodes around.
2771 return DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
2778 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
2779 SDOperand InVec = N->getOperand(0);
2780 SDOperand InVal = N->getOperand(1);
2781 SDOperand EltNo = N->getOperand(2);
2783 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
2784 // vector with the inserted element.
2785 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2786 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2787 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2788 if (Elt < Ops.size())
2790 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
2791 &Ops[0], Ops.size());
2797 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
2798 SDOperand InVec = N->getOperand(0);
2799 SDOperand InVal = N->getOperand(1);
2800 SDOperand EltNo = N->getOperand(2);
2801 SDOperand NumElts = N->getOperand(3);
2802 SDOperand EltType = N->getOperand(4);
2804 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
2805 // vector with the inserted element.
2806 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2807 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2808 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2809 if (Elt < Ops.size()-2)
2811 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
2812 &Ops[0], Ops.size());
2818 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
2819 unsigned NumInScalars = N->getNumOperands()-2;
2820 SDOperand NumElts = N->getOperand(NumInScalars);
2821 SDOperand EltType = N->getOperand(NumInScalars+1);
2823 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
2824 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
2825 // two distinct vectors, turn this into a shuffle node.
2826 SDOperand VecIn1, VecIn2;
2827 for (unsigned i = 0; i != NumInScalars; ++i) {
2828 // Ignore undef inputs.
2829 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2831 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
2832 // constant index, bail out.
2833 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
2834 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
2835 VecIn1 = VecIn2 = SDOperand(0, 0);
2839 // If the input vector type disagrees with the result of the vbuild_vector,
2840 // we can't make a shuffle.
2841 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
2842 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
2843 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
2844 VecIn1 = VecIn2 = SDOperand(0, 0);
2848 // Otherwise, remember this. We allow up to two distinct input vectors.
2849 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
2852 if (VecIn1.Val == 0) {
2853 VecIn1 = ExtractedFromVec;
2854 } else if (VecIn2.Val == 0) {
2855 VecIn2 = ExtractedFromVec;
2858 VecIn1 = VecIn2 = SDOperand(0, 0);
2863 // If everything is good, we can make a shuffle operation.
2865 SmallVector<SDOperand, 8> BuildVecIndices;
2866 for (unsigned i = 0; i != NumInScalars; ++i) {
2867 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
2868 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2872 SDOperand Extract = N->getOperand(i);
2874 // If extracting from the first vector, just use the index directly.
2875 if (Extract.getOperand(0) == VecIn1) {
2876 BuildVecIndices.push_back(Extract.getOperand(1));
2880 // Otherwise, use InIdx + VecSize
2881 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
2882 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
2885 // Add count and size info.
2886 BuildVecIndices.push_back(NumElts);
2887 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
2889 // Return the new VVECTOR_SHUFFLE node.
2895 // Use an undef vbuild_vector as input for the second operand.
2896 std::vector<SDOperand> UnOps(NumInScalars,
2897 DAG.getNode(ISD::UNDEF,
2898 cast<VTSDNode>(EltType)->getVT()));
2899 UnOps.push_back(NumElts);
2900 UnOps.push_back(EltType);
2901 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2902 &UnOps[0], UnOps.size());
2903 AddToWorkList(Ops[1].Val);
2905 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2906 &BuildVecIndices[0], BuildVecIndices.size());
2909 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
2915 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
2916 SDOperand ShufMask = N->getOperand(2);
2917 unsigned NumElts = ShufMask.getNumOperands();
2919 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2920 bool isIdentity = true;
2921 for (unsigned i = 0; i != NumElts; ++i) {
2922 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2923 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2928 if (isIdentity) return N->getOperand(0);
2930 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2932 for (unsigned i = 0; i != NumElts; ++i) {
2933 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2934 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2939 if (isIdentity) return N->getOperand(1);
2941 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
2943 bool isUnary = true;
2944 bool isSplat = true;
2946 unsigned BaseIdx = 0;
2947 for (unsigned i = 0; i != NumElts; ++i)
2948 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
2949 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
2950 int V = (Idx < NumElts) ? 0 : 1;
2964 SDOperand N0 = N->getOperand(0);
2965 SDOperand N1 = N->getOperand(1);
2966 // Normalize unary shuffle so the RHS is undef.
2967 if (isUnary && VecNum == 1)
2970 // If it is a splat, check if the argument vector is a build_vector with
2971 // all scalar elements the same.
2974 if (V->getOpcode() == ISD::BIT_CONVERT)
2975 V = V->getOperand(0).Val;
2976 if (V->getOpcode() == ISD::BUILD_VECTOR) {
2977 unsigned NumElems = V->getNumOperands()-2;
2978 if (NumElems > BaseIdx) {
2980 bool AllSame = true;
2981 for (unsigned i = 0; i != NumElems; ++i) {
2982 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
2983 Base = V->getOperand(i);
2987 // Splat of <u, u, u, u>, return <u, u, u, u>
2990 for (unsigned i = 0; i != NumElems; ++i) {
2991 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
2992 V->getOperand(i) != Base) {
2997 // Splat of <x, x, x, x>, return <x, x, x, x>
3004 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3006 if (isUnary || N0 == N1) {
3007 if (N0.getOpcode() == ISD::UNDEF)
3008 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
3009 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3011 SmallVector<SDOperand, 8> MappedOps;
3012 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
3013 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3014 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3015 MappedOps.push_back(ShufMask.getOperand(i));
3018 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3019 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3022 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
3023 &MappedOps[0], MappedOps.size());
3024 AddToWorkList(ShufMask.Val);
3025 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3027 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3034 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3035 SDOperand ShufMask = N->getOperand(2);
3036 unsigned NumElts = ShufMask.getNumOperands()-2;
3038 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3039 bool isIdentity = true;
3040 for (unsigned i = 0; i != NumElts; ++i) {
3041 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3042 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3047 if (isIdentity) return N->getOperand(0);
3049 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3051 for (unsigned i = 0; i != NumElts; ++i) {
3052 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3053 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3058 if (isIdentity) return N->getOperand(1);
3060 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3062 bool isUnary = true;
3063 bool isSplat = true;
3065 unsigned BaseIdx = 0;
3066 for (unsigned i = 0; i != NumElts; ++i)
3067 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3068 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3069 int V = (Idx < NumElts) ? 0 : 1;
3083 SDOperand N0 = N->getOperand(0);
3084 SDOperand N1 = N->getOperand(1);
3085 // Normalize unary shuffle so the RHS is undef.
3086 if (isUnary && VecNum == 1)
3089 // If it is a splat, check if the argument vector is a build_vector with
3090 // all scalar elements the same.
3093 if (V->getOpcode() == ISD::VBIT_CONVERT)
3094 V = V->getOperand(0).Val;
3095 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3096 unsigned NumElems = V->getNumOperands()-2;
3097 if (NumElems > BaseIdx) {
3099 bool AllSame = true;
3100 for (unsigned i = 0; i != NumElems; ++i) {
3101 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3102 Base = V->getOperand(i);
3106 // Splat of <u, u, u, u>, return <u, u, u, u>
3109 for (unsigned i = 0; i != NumElems; ++i) {
3110 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3111 V->getOperand(i) != Base) {
3116 // Splat of <x, x, x, x>, return <x, x, x, x>
3123 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3125 if (isUnary || N0 == N1) {
3126 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3128 SmallVector<SDOperand, 8> MappedOps;
3129 for (unsigned i = 0; i != NumElts; ++i) {
3130 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3131 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3132 MappedOps.push_back(ShufMask.getOperand(i));
3135 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3136 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3139 // Add the type/#elts values.
3140 MappedOps.push_back(ShufMask.getOperand(NumElts));
3141 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3143 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3144 &MappedOps[0], MappedOps.size());
3145 AddToWorkList(ShufMask.Val);
3147 // Build the undef vector.
3148 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3149 for (unsigned i = 0; i != NumElts; ++i)
3150 MappedOps[i] = UDVal;
3151 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3152 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3153 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3154 &MappedOps[0], MappedOps.size());
3156 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3157 N0, UDVal, ShufMask,
3158 MappedOps[NumElts], MappedOps[NumElts+1]);
3164 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3165 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3166 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3167 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3168 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3169 SDOperand LHS = N->getOperand(0);
3170 SDOperand RHS = N->getOperand(1);
3171 if (N->getOpcode() == ISD::VAND) {
3172 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3173 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3174 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3175 RHS = RHS.getOperand(0);
3176 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3177 std::vector<SDOperand> IdxOps;
3178 unsigned NumOps = RHS.getNumOperands();
3179 unsigned NumElts = NumOps-2;
3180 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3181 for (unsigned i = 0; i != NumElts; ++i) {
3182 SDOperand Elt = RHS.getOperand(i);
3183 if (!isa<ConstantSDNode>(Elt))
3185 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3186 IdxOps.push_back(DAG.getConstant(i, EVT));
3187 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3188 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3193 // Let's see if the target supports this vector_shuffle.
3194 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3197 // Return the new VVECTOR_SHUFFLE node.
3198 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3199 SDOperand EVTNode = DAG.getValueType(EVT);
3200 std::vector<SDOperand> Ops;
3201 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3204 AddToWorkList(LHS.Val);
3205 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3206 ZeroOps.push_back(NumEltsNode);
3207 ZeroOps.push_back(EVTNode);
3208 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3209 &ZeroOps[0], ZeroOps.size()));
3210 IdxOps.push_back(NumEltsNode);
3211 IdxOps.push_back(EVTNode);
3212 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3213 &IdxOps[0], IdxOps.size()));
3214 Ops.push_back(NumEltsNode);
3215 Ops.push_back(EVTNode);
3216 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3217 &Ops[0], Ops.size());
3218 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3219 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3220 DstVecSize, DstVecEVT);
3228 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3229 /// the scalar operation of the vop if it is operating on an integer vector
3230 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3231 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3232 ISD::NodeType FPOp) {
3233 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3234 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3235 SDOperand LHS = N->getOperand(0);
3236 SDOperand RHS = N->getOperand(1);
3237 SDOperand Shuffle = XformToShuffleWithZero(N);
3238 if (Shuffle.Val) return Shuffle;
3240 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3242 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3243 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3244 SmallVector<SDOperand, 8> Ops;
3245 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3246 SDOperand LHSOp = LHS.getOperand(i);
3247 SDOperand RHSOp = RHS.getOperand(i);
3248 // If these two elements can't be folded, bail out.
3249 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3250 LHSOp.getOpcode() != ISD::Constant &&
3251 LHSOp.getOpcode() != ISD::ConstantFP) ||
3252 (RHSOp.getOpcode() != ISD::UNDEF &&
3253 RHSOp.getOpcode() != ISD::Constant &&
3254 RHSOp.getOpcode() != ISD::ConstantFP))
3256 // Can't fold divide by zero.
3257 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3258 if ((RHSOp.getOpcode() == ISD::Constant &&
3259 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3260 (RHSOp.getOpcode() == ISD::ConstantFP &&
3261 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3264 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3265 AddToWorkList(Ops.back().Val);
3266 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3267 Ops.back().getOpcode() == ISD::Constant ||
3268 Ops.back().getOpcode() == ISD::ConstantFP) &&
3269 "Scalar binop didn't fold!");
3272 if (Ops.size() == LHS.getNumOperands()-2) {
3273 Ops.push_back(*(LHS.Val->op_end()-2));
3274 Ops.push_back(*(LHS.Val->op_end()-1));
3275 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3282 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3283 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3285 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3286 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3287 // If we got a simplified select_cc node back from SimplifySelectCC, then
3288 // break it down into a new SETCC node, and a new SELECT node, and then return
3289 // the SELECT node, since we were called with a SELECT node.
3291 // Check to see if we got a select_cc back (to turn into setcc/select).
3292 // Otherwise, just return whatever node we got back, like fabs.
3293 if (SCC.getOpcode() == ISD::SELECT_CC) {
3294 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3295 SCC.getOperand(0), SCC.getOperand(1),
3297 AddToWorkList(SETCC.Val);
3298 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3299 SCC.getOperand(3), SETCC);
3306 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3307 /// are the two values being selected between, see if we can simplify the
3308 /// select. Callers of this should assume that TheSelect is deleted if this
3309 /// returns true. As such, they should return the appropriate thing (e.g. the
3310 /// node) back to the top-level of the DAG combiner loop to avoid it being
3313 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3316 // If this is a select from two identical things, try to pull the operation
3317 // through the select.
3318 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3320 std::cerr << "SELECT: ["; LHS.Val->dump();
3321 std::cerr << "] ["; RHS.Val->dump();
3325 // If this is a load and the token chain is identical, replace the select
3326 // of two loads with a load through a select of the address to load from.
3327 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3328 // constants have been dropped into the constant pool.
3329 if ((LHS.getOpcode() == ISD::LOAD ||
3330 LHS.getOpcode() == ISD::LOADX ) &&
3331 // Token chains must be identical.
3332 LHS.getOperand(0) == RHS.getOperand(0) &&
3333 // If this is an EXTLOAD, the VT's must match.
3334 (LHS.getOpcode() == ISD::LOAD ||
3335 LHS.getOperand(3) == RHS.getOperand(3))) {
3336 // FIXME: this conflates two src values, discarding one. This is not
3337 // the right thing to do, but nothing uses srcvalues now. When they do,
3338 // turn SrcValue into a list of locations.
3340 if (TheSelect->getOpcode() == ISD::SELECT)
3341 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
3342 TheSelect->getOperand(0), LHS.getOperand(1),
3345 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
3346 TheSelect->getOperand(0),
3347 TheSelect->getOperand(1),
3348 LHS.getOperand(1), RHS.getOperand(1),
3349 TheSelect->getOperand(4));
3352 if (LHS.getOpcode() == ISD::LOAD)
3353 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
3354 Addr, LHS.getOperand(2));
3356 unsigned LType = LHS.getConstantOperandVal(4);
3357 Load = DAG.getExtLoad((ISD::LoadExtType)LType,
3358 TheSelect->getValueType(0),
3359 LHS.getOperand(0), Addr, LHS.getOperand(2),
3360 cast<VTSDNode>(LHS.getOperand(3))->getVT());
3362 // Users of the select now use the result of the load.
3363 CombineTo(TheSelect, Load);
3365 // Users of the old loads now use the new load's chain. We know the
3366 // old-load value is dead now.
3367 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3368 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3376 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3377 SDOperand N2, SDOperand N3,
3380 MVT::ValueType VT = N2.getValueType();
3381 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3382 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3383 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3385 // Determine if the condition we're dealing with is constant
3386 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3387 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3389 // fold select_cc true, x, y -> x
3390 if (SCCC && SCCC->getValue())
3392 // fold select_cc false, x, y -> y
3393 if (SCCC && SCCC->getValue() == 0)
3396 // Check to see if we can simplify the select into an fabs node
3397 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3398 // Allow either -0.0 or 0.0
3399 if (CFP->getValue() == 0.0) {
3400 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3401 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3402 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3403 N2 == N3.getOperand(0))
3404 return DAG.getNode(ISD::FABS, VT, N0);
3406 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3407 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3408 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3409 N2.getOperand(0) == N3)
3410 return DAG.getNode(ISD::FABS, VT, N3);
3414 // Check to see if we can perform the "gzip trick", transforming
3415 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3416 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3417 MVT::isInteger(N0.getValueType()) &&
3418 MVT::isInteger(N2.getValueType()) &&
3419 (N1C->isNullValue() || // (a < 0) ? b : 0
3420 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3421 MVT::ValueType XType = N0.getValueType();
3422 MVT::ValueType AType = N2.getValueType();
3423 if (XType >= AType) {
3424 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3425 // single-bit constant.
3426 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3427 unsigned ShCtV = Log2_64(N2C->getValue());
3428 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3429 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3430 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3431 AddToWorkList(Shift.Val);
3432 if (XType > AType) {
3433 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3434 AddToWorkList(Shift.Val);
3436 return DAG.getNode(ISD::AND, AType, Shift, N2);
3438 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3439 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3440 TLI.getShiftAmountTy()));
3441 AddToWorkList(Shift.Val);
3442 if (XType > AType) {
3443 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3444 AddToWorkList(Shift.Val);
3446 return DAG.getNode(ISD::AND, AType, Shift, N2);
3450 // fold select C, 16, 0 -> shl C, 4
3451 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3452 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3453 // Get a SetCC of the condition
3454 // FIXME: Should probably make sure that setcc is legal if we ever have a
3455 // target where it isn't.
3456 SDOperand Temp, SCC;
3457 // cast from setcc result type to select result type
3458 if (AfterLegalize) {
3459 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3460 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3462 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3463 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3465 AddToWorkList(SCC.Val);
3466 AddToWorkList(Temp.Val);
3467 // shl setcc result by log2 n2c
3468 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3469 DAG.getConstant(Log2_64(N2C->getValue()),
3470 TLI.getShiftAmountTy()));
3473 // Check to see if this is the equivalent of setcc
3474 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3475 // otherwise, go ahead with the folds.
3476 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3477 MVT::ValueType XType = N0.getValueType();
3478 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3479 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3480 if (Res.getValueType() != VT)
3481 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3485 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3486 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3487 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3488 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3489 return DAG.getNode(ISD::SRL, XType, Ctlz,
3490 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3491 TLI.getShiftAmountTy()));
3493 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3494 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3495 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3497 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3498 DAG.getConstant(~0ULL, XType));
3499 return DAG.getNode(ISD::SRL, XType,
3500 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3501 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3502 TLI.getShiftAmountTy()));
3504 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3505 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3506 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3507 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3508 TLI.getShiftAmountTy()));
3509 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3513 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3514 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3515 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3516 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3517 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3518 MVT::ValueType XType = N0.getValueType();
3519 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3520 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3521 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3522 TLI.getShiftAmountTy()));
3523 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3524 AddToWorkList(Shift.Val);
3525 AddToWorkList(Add.Val);
3526 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3534 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3535 SDOperand N1, ISD::CondCode Cond,
3536 bool foldBooleans) {
3537 // These setcc operations always fold.
3541 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3543 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3546 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3547 uint64_t C1 = N1C->getValue();
3548 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
3549 uint64_t C0 = N0C->getValue();
3551 // Sign extend the operands if required
3552 if (ISD::isSignedIntSetCC(Cond)) {
3553 C0 = N0C->getSignExtended();
3554 C1 = N1C->getSignExtended();
3558 default: assert(0 && "Unknown integer setcc!");
3559 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3560 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3561 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
3562 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
3563 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
3564 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
3565 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
3566 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
3567 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
3568 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
3571 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3572 // equality comparison, then we're just comparing whether X itself is
3574 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
3575 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3576 N0.getOperand(1).getOpcode() == ISD::Constant) {
3577 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
3578 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3579 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
3580 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3581 // (srl (ctlz x), 5) == 0 -> X != 0
3582 // (srl (ctlz x), 5) != 1 -> X != 0
3585 // (srl (ctlz x), 5) != 0 -> X == 0
3586 // (srl (ctlz x), 5) == 1 -> X == 0
3589 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
3590 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
3595 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3596 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3597 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3599 // If the comparison constant has bits in the upper part, the
3600 // zero-extended value could never match.
3601 if (C1 & (~0ULL << InSize)) {
3602 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3606 case ISD::SETEQ: return DAG.getConstant(0, VT);
3609 case ISD::SETNE: return DAG.getConstant(1, VT);
3612 // True if the sign bit of C1 is set.
3613 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3616 // True if the sign bit of C1 isn't set.
3617 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3623 // Otherwise, we can perform the comparison with the low bits.
3631 return DAG.getSetCC(VT, N0.getOperand(0),
3632 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3635 break; // todo, be more careful with signed comparisons
3637 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3638 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3639 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3640 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3641 MVT::ValueType ExtDstTy = N0.getValueType();
3642 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3644 // If the extended part has any inconsistent bits, it cannot ever
3645 // compare equal. In other words, they have to be all ones or all
3648 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3649 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3650 return DAG.getConstant(Cond == ISD::SETNE, VT);
3653 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3654 if (Op0Ty == ExtSrcTy) {
3655 ZextOp = N0.getOperand(0);
3657 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3658 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3659 DAG.getConstant(Imm, Op0Ty));
3661 AddToWorkList(ZextOp.Val);
3662 // Otherwise, make this a use of a zext.
3663 return DAG.getSetCC(VT, ZextOp,
3664 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3667 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3668 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3669 (N0.getOpcode() == ISD::XOR ||
3670 (N0.getOpcode() == ISD::AND &&
3671 N0.getOperand(0).getOpcode() == ISD::XOR &&
3672 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3673 isa<ConstantSDNode>(N0.getOperand(1)) &&
3674 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3675 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
3676 // only do this if the top bits are known zero.
3677 if (TLI.MaskedValueIsZero(N1,
3678 MVT::getIntVTBitMask(N0.getValueType())-1)) {
3679 // Okay, get the un-inverted input value.
3681 if (N0.getOpcode() == ISD::XOR)
3682 Val = N0.getOperand(0);
3684 assert(N0.getOpcode() == ISD::AND &&
3685 N0.getOperand(0).getOpcode() == ISD::XOR);
3686 // ((X^1)&1)^1 -> X & 1
3687 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3688 N0.getOperand(0).getOperand(0), N0.getOperand(1));
3690 return DAG.getSetCC(VT, Val, N1,
3691 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3695 uint64_t MinVal, MaxVal;
3696 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3697 if (ISD::isSignedIntSetCC(Cond)) {
3698 MinVal = 1ULL << (OperandBitSize-1);
3699 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3700 MaxVal = ~0ULL >> (65-OperandBitSize);
3705 MaxVal = ~0ULL >> (64-OperandBitSize);
3708 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3709 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3710 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
3711 --C1; // X >= C0 --> X > (C0-1)
3712 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3713 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
3716 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3717 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
3718 ++C1; // X <= C0 --> X < (C0+1)
3719 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3720 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
3723 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
3724 return DAG.getConstant(0, VT); // X < MIN --> false
3726 // Canonicalize setgt X, Min --> setne X, Min
3727 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
3728 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3729 // Canonicalize setlt X, Max --> setne X, Max
3730 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
3731 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3733 // If we have setult X, 1, turn it into seteq X, 0
3734 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
3735 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
3737 // If we have setugt X, Max-1, turn it into seteq X, Max
3738 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
3739 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
3742 // If we have "setcc X, C0", check to see if we can shrink the immediate
3745 // SETUGT X, SINTMAX -> SETLT X, 0
3746 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
3747 C1 == (~0ULL >> (65-OperandBitSize)))
3748 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
3751 // FIXME: Implement the rest of these.
3753 // Fold bit comparisons when we can.
3754 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3755 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
3756 if (ConstantSDNode *AndRHS =
3757 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3758 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3759 // Perform the xform if the AND RHS is a single bit.
3760 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
3761 return DAG.getNode(ISD::SRL, VT, N0,
3762 DAG.getConstant(Log2_64(AndRHS->getValue()),
3763 TLI.getShiftAmountTy()));
3765 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
3766 // (X & 8) == 8 --> (X & 8) >> 3
3767 // Perform the xform if C1 is a single bit.
3768 if ((C1 & (C1-1)) == 0) {
3769 return DAG.getNode(ISD::SRL, VT, N0,
3770 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
3775 } else if (isa<ConstantSDNode>(N0.Val)) {
3776 // Ensure that the constant occurs on the RHS.
3777 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3780 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
3781 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
3782 double C0 = N0C->getValue(), C1 = N1C->getValue();
3785 default: break; // FIXME: Implement the rest of these!
3786 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3787 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3788 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
3789 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
3790 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
3791 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
3794 // Ensure that the constant occurs on the RHS.
3795 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3799 // We can always fold X == Y for integer setcc's.
3800 if (MVT::isInteger(N0.getValueType()))
3801 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3802 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3803 if (UOF == 2) // FP operators that are undefined on NaNs.
3804 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3805 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
3806 return DAG.getConstant(UOF, VT);
3807 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3808 // if it is not already.
3809 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3810 if (NewCond != Cond)
3811 return DAG.getSetCC(VT, N0, N1, NewCond);
3814 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3815 MVT::isInteger(N0.getValueType())) {
3816 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3817 N0.getOpcode() == ISD::XOR) {
3818 // Simplify (X+Y) == (X+Z) --> Y == Z
3819 if (N0.getOpcode() == N1.getOpcode()) {
3820 if (N0.getOperand(0) == N1.getOperand(0))
3821 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
3822 if (N0.getOperand(1) == N1.getOperand(1))
3823 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
3824 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
3825 // If X op Y == Y op X, try other combinations.
3826 if (N0.getOperand(0) == N1.getOperand(1))
3827 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
3828 if (N0.getOperand(1) == N1.getOperand(0))
3829 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
3833 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3834 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3835 // Turn (X+C1) == C2 --> X == C2-C1
3836 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
3837 return DAG.getSetCC(VT, N0.getOperand(0),
3838 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
3839 N0.getValueType()), Cond);
3842 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3843 if (N0.getOpcode() == ISD::XOR)
3844 // If we know that all of the inverted bits are zero, don't bother
3845 // performing the inversion.
3846 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
3847 return DAG.getSetCC(VT, N0.getOperand(0),
3848 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
3849 N0.getValueType()), Cond);
3852 // Turn (C1-X) == C2 --> X == C1-C2
3853 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3854 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
3855 return DAG.getSetCC(VT, N0.getOperand(1),
3856 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
3857 N0.getValueType()), Cond);
3862 // Simplify (X+Z) == X --> Z == 0
3863 if (N0.getOperand(0) == N1)
3864 return DAG.getSetCC(VT, N0.getOperand(1),
3865 DAG.getConstant(0, N0.getValueType()), Cond);
3866 if (N0.getOperand(1) == N1) {
3867 if (DAG.isCommutativeBinOp(N0.getOpcode()))
3868 return DAG.getSetCC(VT, N0.getOperand(0),
3869 DAG.getConstant(0, N0.getValueType()), Cond);
3871 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
3872 // (Z-X) == X --> Z == X<<1
3873 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
3875 DAG.getConstant(1,TLI.getShiftAmountTy()));
3876 AddToWorkList(SH.Val);
3877 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
3882 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3883 N1.getOpcode() == ISD::XOR) {
3884 // Simplify X == (X+Z) --> Z == 0
3885 if (N1.getOperand(0) == N0) {
3886 return DAG.getSetCC(VT, N1.getOperand(1),
3887 DAG.getConstant(0, N1.getValueType()), Cond);
3888 } else if (N1.getOperand(1) == N0) {
3889 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
3890 return DAG.getSetCC(VT, N1.getOperand(0),
3891 DAG.getConstant(0, N1.getValueType()), Cond);
3893 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
3894 // X == (Z-X) --> X<<1 == Z
3895 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
3896 DAG.getConstant(1,TLI.getShiftAmountTy()));
3897 AddToWorkList(SH.Val);
3898 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
3904 // Fold away ALL boolean setcc's.
3906 if (N0.getValueType() == MVT::i1 && foldBooleans) {
3908 default: assert(0 && "Unknown integer setcc!");
3909 case ISD::SETEQ: // X == Y -> (X^Y)^1
3910 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3911 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
3912 AddToWorkList(Temp.Val);
3914 case ISD::SETNE: // X != Y --> (X^Y)
3915 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3917 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
3918 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
3919 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3920 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
3921 AddToWorkList(Temp.Val);
3923 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
3924 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
3925 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3926 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
3927 AddToWorkList(Temp.Val);
3929 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
3930 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
3931 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3932 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
3933 AddToWorkList(Temp.Val);
3935 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
3936 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
3937 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3938 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
3941 if (VT != MVT::i1) {
3942 AddToWorkList(N0.Val);
3943 // FIXME: If running after legalize, we probably can't do this.
3944 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
3949 // Could not fold it.
3953 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3954 /// return a DAG expression to select that will generate the same value by
3955 /// multiplying by a magic number. See:
3956 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3957 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
3958 std::vector<SDNode*> Built;
3959 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
3961 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3967 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3968 /// return a DAG expression to select that will generate the same value by
3969 /// multiplying by a magic number. See:
3970 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3971 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
3972 std::vector<SDNode*> Built;
3973 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
3975 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3981 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
3982 /// looking for aliasing nodes and adding them to the Aliases vector.
3983 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
3984 SmallVector<SDOperand, 8> &Aliases) {
3985 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
3986 std::set<SDNode *> Visited; // Visited node set.
3988 // Get alias information for node.
3992 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue);
3995 Chains.push_back(OriginalChain);
3997 // Look at each chain and determine if it is an alias. If so, add it to the
3998 // aliases list. If not, then continue up the chain looking for the next
4000 while (!Chains.empty()) {
4001 SDOperand Chain = Chains.back();
4004 // Don't bother if we've been before.
4005 if (Visited.find(Chain.Val) != Visited.end()) continue;
4006 Visited.insert(Chain.Val);
4008 switch (Chain.getOpcode()) {
4009 case ISD::EntryToken:
4010 // Entry token is ideal chain operand, but handled in FindBetterChain.
4015 // Get alias information for Chain.
4018 SDOperand OpSrcValue;
4019 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, OpSrcValue);
4021 // If chain is alias then stop here.
4022 if (!(IsLoad && IsOpLoad) &&
4023 isAlias(Ptr, Size, SrcValue, OpPtr, OpSize, OpSrcValue)) {
4024 Aliases.push_back(Chain);
4026 // Look further up the chain.
4027 Chains.push_back(Chain.getOperand(0));
4028 // Clean up old chain.
4029 AddToWorkList(Chain.Val);
4034 case ISD::TokenFactor:
4035 // We have to check each of the operands of the token factor, so we queue
4036 // then up. Adding the operands to the queue (stack) in reverse order
4037 // maintains the original order and increases the likelihood that getNode
4038 // will find a matching token factor (CSE.)
4039 for (unsigned n = Chain.getNumOperands(); n;)
4040 Chains.push_back(Chain.getOperand(--n));
4041 // Eliminate the token factor if we can.
4042 AddToWorkList(Chain.Val);
4046 // For all other instructions we will just have to take what we can get.
4047 Aliases.push_back(Chain);
4053 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4054 /// for a better chain (aliasing node.)
4055 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4056 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4058 // Accumulate all the aliases to this node.
4059 GatherAllAliases(N, OldChain, Aliases);
4061 if (Aliases.size() == 0) {
4062 // If no operands then chain to entry token.
4063 return DAG.getEntryNode();
4064 } else if (Aliases.size() == 1) {
4065 // If a single operand then chain to it. We don't need to revisit it.
4069 // Construct a custom tailored token factor.
4070 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4071 &Aliases[0], Aliases.size());
4073 // Make sure the old chain gets cleaned up.
4074 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4079 // SelectionDAG::Combine - This is the entry point for the file.
4081 void SelectionDAG::Combine(bool RunningAfterLegalize) {
4082 /// run - This is the main entry point to this class.
4084 DAGCombiner(*this).Run(RunningAfterLegalize);