1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/CommandLine.h"
46 static Statistic<> NodesCombined ("dagcombiner",
47 "Number of dag nodes combined");
50 CombinerAA("combiner-alias-analysis", cl::Hidden,
51 cl::desc("Turn on alias analysis turning testing"));
53 //------------------------------ DAGCombiner ---------------------------------//
55 class VISIBILITY_HIDDEN DAGCombiner {
60 // Worklist of all of the nodes that need to be simplified.
61 std::vector<SDNode*> WorkList;
63 /// AddUsersToWorkList - When an instruction is simplified, add all users of
64 /// the instruction to the work lists because they might get more simplified
67 void AddUsersToWorkList(SDNode *N) {
68 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
73 /// removeFromWorkList - remove all instances of N from the worklist.
75 void removeFromWorkList(SDNode *N) {
76 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
81 /// AddToWorkList - Add to the work list making sure it's instance is at the
82 /// the back (next to be processed.)
83 void AddToWorkList(SDNode *N) {
84 removeFromWorkList(N);
85 WorkList.push_back(N);
88 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo) {
89 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
91 DEBUG(std::cerr << "\nReplacing.1 "; N->dump();
92 std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
93 std::cerr << " and " << NumTo-1 << " other values\n");
94 std::vector<SDNode*> NowDead;
95 DAG.ReplaceAllUsesWith(N, To, &NowDead);
97 // Push the new nodes and any users onto the worklist
98 for (unsigned i = 0, e = NumTo; i != e; ++i) {
99 AddToWorkList(To[i].Val);
100 AddUsersToWorkList(To[i].Val);
103 // Nodes can be reintroduced into the worklist. Make sure we do not
104 // process a node that has been replaced.
105 removeFromWorkList(N);
106 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
107 removeFromWorkList(NowDead[i]);
109 // Finally, since the node is now dead, remove it from the graph.
111 return SDOperand(N, 0);
114 SDOperand CombineTo(SDNode *N, SDOperand Res) {
115 return CombineTo(N, &Res, 1);
118 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
119 SDOperand To[] = { Res0, Res1 };
120 return CombineTo(N, To, 2);
124 /// SimplifyDemandedBits - Check the specified integer node value to see if
125 /// it can be simplified or if things it uses can be simplified by bit
126 /// propagation. If so, return true.
127 bool SimplifyDemandedBits(SDOperand Op) {
128 TargetLowering::TargetLoweringOpt TLO(DAG);
129 uint64_t KnownZero, KnownOne;
130 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
131 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
135 AddToWorkList(Op.Val);
137 // Replace the old value with the new one.
139 DEBUG(std::cerr << "\nReplacing.2 "; TLO.Old.Val->dump();
140 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG);
143 std::vector<SDNode*> NowDead;
144 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
146 // Push the new node and any (possibly new) users onto the worklist.
147 AddToWorkList(TLO.New.Val);
148 AddUsersToWorkList(TLO.New.Val);
150 // Nodes can end up on the worklist more than once. Make sure we do
151 // not process a node that has been replaced.
152 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
153 removeFromWorkList(NowDead[i]);
155 // Finally, if the node is now dead, remove it from the graph. The node
156 // may not be dead if the replacement process recursively simplified to
157 // something else needing this node.
158 if (TLO.Old.Val->use_empty()) {
159 removeFromWorkList(TLO.Old.Val);
160 DAG.DeleteNode(TLO.Old.Val);
165 /// visit - call the node-specific routine that knows how to fold each
166 /// particular type of node.
167 SDOperand visit(SDNode *N);
169 // Visitation implementation - Implement dag node combining for different
170 // node types. The semantics are as follows:
172 // SDOperand.Val == 0 - No change was made
173 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
174 // otherwise - N should be replaced by the returned Operand.
176 SDOperand visitTokenFactor(SDNode *N);
177 SDOperand visitADD(SDNode *N);
178 SDOperand visitSUB(SDNode *N);
179 SDOperand visitMUL(SDNode *N);
180 SDOperand visitSDIV(SDNode *N);
181 SDOperand visitUDIV(SDNode *N);
182 SDOperand visitSREM(SDNode *N);
183 SDOperand visitUREM(SDNode *N);
184 SDOperand visitMULHU(SDNode *N);
185 SDOperand visitMULHS(SDNode *N);
186 SDOperand visitAND(SDNode *N);
187 SDOperand visitOR(SDNode *N);
188 SDOperand visitXOR(SDNode *N);
189 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
190 SDOperand visitSHL(SDNode *N);
191 SDOperand visitSRA(SDNode *N);
192 SDOperand visitSRL(SDNode *N);
193 SDOperand visitCTLZ(SDNode *N);
194 SDOperand visitCTTZ(SDNode *N);
195 SDOperand visitCTPOP(SDNode *N);
196 SDOperand visitSELECT(SDNode *N);
197 SDOperand visitSELECT_CC(SDNode *N);
198 SDOperand visitSETCC(SDNode *N);
199 SDOperand visitSIGN_EXTEND(SDNode *N);
200 SDOperand visitZERO_EXTEND(SDNode *N);
201 SDOperand visitANY_EXTEND(SDNode *N);
202 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
203 SDOperand visitTRUNCATE(SDNode *N);
204 SDOperand visitBIT_CONVERT(SDNode *N);
205 SDOperand visitVBIT_CONVERT(SDNode *N);
206 SDOperand visitFADD(SDNode *N);
207 SDOperand visitFSUB(SDNode *N);
208 SDOperand visitFMUL(SDNode *N);
209 SDOperand visitFDIV(SDNode *N);
210 SDOperand visitFREM(SDNode *N);
211 SDOperand visitFCOPYSIGN(SDNode *N);
212 SDOperand visitSINT_TO_FP(SDNode *N);
213 SDOperand visitUINT_TO_FP(SDNode *N);
214 SDOperand visitFP_TO_SINT(SDNode *N);
215 SDOperand visitFP_TO_UINT(SDNode *N);
216 SDOperand visitFP_ROUND(SDNode *N);
217 SDOperand visitFP_ROUND_INREG(SDNode *N);
218 SDOperand visitFP_EXTEND(SDNode *N);
219 SDOperand visitFNEG(SDNode *N);
220 SDOperand visitFABS(SDNode *N);
221 SDOperand visitBRCOND(SDNode *N);
222 SDOperand visitBR_CC(SDNode *N);
223 SDOperand visitLOAD(SDNode *N);
224 SDOperand visitSTORE(SDNode *N);
225 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
226 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
227 SDOperand visitVBUILD_VECTOR(SDNode *N);
228 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
229 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
231 SDOperand XformToShuffleWithZero(SDNode *N);
232 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
234 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
235 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
236 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
237 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
238 SDOperand N3, ISD::CondCode CC);
239 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
240 ISD::CondCode Cond, bool foldBooleans = true);
241 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
242 SDOperand BuildSDIV(SDNode *N);
243 SDOperand BuildUDIV(SDNode *N);
244 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
246 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
247 /// looking for aliasing nodes and adding them to the Aliases vector.
248 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
249 SmallVector<SDOperand, 8> &Aliases);
251 /// FindAliasInfo - Extracts the relevant alias information from the memory
252 /// node. Returns true if the operand was a load.
253 bool FindAliasInfo(SDNode *N,
254 SDOperand &Ptr, int64_t &Size, const Value *&SrcValue);
256 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
257 /// looking for a better chain (aliasing node.)
258 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
261 DAGCombiner(SelectionDAG &D)
262 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
264 /// Run - runs the dag combiner on all nodes in the work list
265 void Run(bool RunningAfterLegalize);
269 //===----------------------------------------------------------------------===//
270 // TargetLowering::DAGCombinerInfo implementation
271 //===----------------------------------------------------------------------===//
273 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
274 ((DAGCombiner*)DC)->AddToWorkList(N);
277 SDOperand TargetLowering::DAGCombinerInfo::
278 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
279 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
282 SDOperand TargetLowering::DAGCombinerInfo::
283 CombineTo(SDNode *N, SDOperand Res) {
284 return ((DAGCombiner*)DC)->CombineTo(N, Res);
288 SDOperand TargetLowering::DAGCombinerInfo::
289 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
290 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
296 //===----------------------------------------------------------------------===//
299 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
300 // that selects between the values 1 and 0, making it equivalent to a setcc.
301 // Also, set the incoming LHS, RHS, and CC references to the appropriate
302 // nodes based on the type of node we are checking. This simplifies life a
303 // bit for the callers.
304 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
306 if (N.getOpcode() == ISD::SETCC) {
307 LHS = N.getOperand(0);
308 RHS = N.getOperand(1);
309 CC = N.getOperand(2);
312 if (N.getOpcode() == ISD::SELECT_CC &&
313 N.getOperand(2).getOpcode() == ISD::Constant &&
314 N.getOperand(3).getOpcode() == ISD::Constant &&
315 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
316 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
317 LHS = N.getOperand(0);
318 RHS = N.getOperand(1);
319 CC = N.getOperand(4);
325 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
326 // one use. If this is true, it allows the users to invert the operation for
327 // free when it is profitable to do so.
328 static bool isOneUseSetCC(SDOperand N) {
329 SDOperand N0, N1, N2;
330 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
335 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
336 MVT::ValueType VT = N0.getValueType();
337 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
338 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
339 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
340 if (isa<ConstantSDNode>(N1)) {
341 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
342 AddToWorkList(OpNode.Val);
343 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
344 } else if (N0.hasOneUse()) {
345 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
346 AddToWorkList(OpNode.Val);
347 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
350 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
351 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
352 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
353 if (isa<ConstantSDNode>(N0)) {
354 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
355 AddToWorkList(OpNode.Val);
356 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
357 } else if (N1.hasOneUse()) {
358 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
359 AddToWorkList(OpNode.Val);
360 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
366 void DAGCombiner::Run(bool RunningAfterLegalize) {
367 // set the instance variable, so that the various visit routines may use it.
368 AfterLegalize = RunningAfterLegalize;
370 // Add all the dag nodes to the worklist.
371 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
372 E = DAG.allnodes_end(); I != E; ++I)
373 WorkList.push_back(I);
375 // Create a dummy node (which is not added to allnodes), that adds a reference
376 // to the root node, preventing it from being deleted, and tracking any
377 // changes of the root.
378 HandleSDNode Dummy(DAG.getRoot());
381 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
382 TargetLowering::DAGCombinerInfo
383 DagCombineInfo(DAG, !RunningAfterLegalize, this);
385 // while the worklist isn't empty, inspect the node on the end of it and
386 // try and combine it.
387 while (!WorkList.empty()) {
388 SDNode *N = WorkList.back();
391 // If N has no uses, it is dead. Make sure to revisit all N's operands once
392 // N is deleted from the DAG, since they too may now be dead or may have a
393 // reduced number of uses, allowing other xforms.
394 if (N->use_empty() && N != &Dummy) {
395 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
396 AddToWorkList(N->getOperand(i).Val);
402 SDOperand RV = visit(N);
404 // If nothing happened, try a target-specific DAG combine.
406 assert(N->getOpcode() != ISD::DELETED_NODE &&
407 "Node was deleted but visit returned NULL!");
408 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
409 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
410 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
415 // If we get back the same node we passed in, rather than a new node or
416 // zero, we know that the node must have defined multiple values and
417 // CombineTo was used. Since CombineTo takes care of the worklist
418 // mechanics for us, we have no work to do in this case.
420 assert(N->getOpcode() != ISD::DELETED_NODE &&
421 RV.Val->getOpcode() != ISD::DELETED_NODE &&
422 "Node was deleted but visit returned new node!");
424 DEBUG(std::cerr << "\nReplacing.3 "; N->dump();
425 std::cerr << "\nWith: "; RV.Val->dump(&DAG);
427 std::vector<SDNode*> NowDead;
428 if (N->getNumValues() == RV.Val->getNumValues())
429 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
431 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
433 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
436 // Push the new node and any users onto the worklist
437 AddToWorkList(RV.Val);
438 AddUsersToWorkList(RV.Val);
440 // Nodes can be reintroduced into the worklist. Make sure we do not
441 // process a node that has been replaced.
442 removeFromWorkList(N);
443 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
444 removeFromWorkList(NowDead[i]);
446 // Finally, since the node is now dead, remove it from the graph.
452 // If the root changed (e.g. it was a dead load, update the root).
453 DAG.setRoot(Dummy.getValue());
456 SDOperand DAGCombiner::visit(SDNode *N) {
457 switch(N->getOpcode()) {
459 case ISD::TokenFactor: return visitTokenFactor(N);
460 case ISD::ADD: return visitADD(N);
461 case ISD::SUB: return visitSUB(N);
462 case ISD::MUL: return visitMUL(N);
463 case ISD::SDIV: return visitSDIV(N);
464 case ISD::UDIV: return visitUDIV(N);
465 case ISD::SREM: return visitSREM(N);
466 case ISD::UREM: return visitUREM(N);
467 case ISD::MULHU: return visitMULHU(N);
468 case ISD::MULHS: return visitMULHS(N);
469 case ISD::AND: return visitAND(N);
470 case ISD::OR: return visitOR(N);
471 case ISD::XOR: return visitXOR(N);
472 case ISD::SHL: return visitSHL(N);
473 case ISD::SRA: return visitSRA(N);
474 case ISD::SRL: return visitSRL(N);
475 case ISD::CTLZ: return visitCTLZ(N);
476 case ISD::CTTZ: return visitCTTZ(N);
477 case ISD::CTPOP: return visitCTPOP(N);
478 case ISD::SELECT: return visitSELECT(N);
479 case ISD::SELECT_CC: return visitSELECT_CC(N);
480 case ISD::SETCC: return visitSETCC(N);
481 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
482 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
483 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
484 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
485 case ISD::TRUNCATE: return visitTRUNCATE(N);
486 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
487 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
488 case ISD::FADD: return visitFADD(N);
489 case ISD::FSUB: return visitFSUB(N);
490 case ISD::FMUL: return visitFMUL(N);
491 case ISD::FDIV: return visitFDIV(N);
492 case ISD::FREM: return visitFREM(N);
493 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
494 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
495 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
496 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
497 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
498 case ISD::FP_ROUND: return visitFP_ROUND(N);
499 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
500 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
501 case ISD::FNEG: return visitFNEG(N);
502 case ISD::FABS: return visitFABS(N);
503 case ISD::BRCOND: return visitBRCOND(N);
504 case ISD::BR_CC: return visitBR_CC(N);
505 case ISD::LOAD: return visitLOAD(N);
506 // FIXME - Switch over after StoreSDNode comes online.
507 case ISD::TRUNCSTORE: // Fail thru
508 case ISD::STORE: return visitSTORE(N);
509 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
510 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
511 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
512 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
513 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
514 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
515 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
516 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
517 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
518 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
519 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
520 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
521 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
526 /// getInputChainForNode - Given a node, return its input chain if it has one,
527 /// otherwise return a null sd operand.
528 static SDOperand getInputChainForNode(SDNode *N) {
529 if (unsigned NumOps = N->getNumOperands()) {
530 if (N->getOperand(0).getValueType() == MVT::Other)
531 return N->getOperand(0);
532 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
533 return N->getOperand(NumOps-1);
534 for (unsigned i = 1; i < NumOps-1; ++i)
535 if (N->getOperand(i).getValueType() == MVT::Other)
536 return N->getOperand(i);
538 return SDOperand(0, 0);
541 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
542 // If N has two operands, where one has an input chain equal to the other,
543 // the 'other' chain is redundant.
544 if (N->getNumOperands() == 2) {
545 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
546 return N->getOperand(0);
547 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
548 return N->getOperand(1);
552 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
553 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
554 bool Changed = false; // If we should replace this token factor.
556 // Start out with this token factor.
559 // Iterate through token factors. The TFs grows when new token factors are
561 for (unsigned i = 0; i < TFs.size(); ++i) {
564 // Check each of the operands.
565 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
566 SDOperand Op = TF->getOperand(i);
568 switch (Op.getOpcode()) {
569 case ISD::EntryToken:
570 // Entry tokens don't need to be added to the list. They are
575 case ISD::TokenFactor:
576 if ((CombinerAA || Op.hasOneUse()) &&
577 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
578 // Queue up for processing.
579 TFs.push_back(Op.Val);
580 // Clean up in case the token factor is removed.
581 AddToWorkList(Op.Val);
588 // Only add if not there prior.
589 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
598 // If we've change things around then replace token factor.
600 if (Ops.size() == 0) {
601 // The entry token is the only possible outcome.
602 Result = DAG.getEntryNode();
604 // New and improved token factor.
605 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
612 SDOperand DAGCombiner::visitADD(SDNode *N) {
613 SDOperand N0 = N->getOperand(0);
614 SDOperand N1 = N->getOperand(1);
615 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
616 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
617 MVT::ValueType VT = N0.getValueType();
619 // fold (add c1, c2) -> c1+c2
621 return DAG.getNode(ISD::ADD, VT, N0, N1);
622 // canonicalize constant to RHS
624 return DAG.getNode(ISD::ADD, VT, N1, N0);
625 // fold (add x, 0) -> x
626 if (N1C && N1C->isNullValue())
628 // fold ((c1-A)+c2) -> (c1+c2)-A
629 if (N1C && N0.getOpcode() == ISD::SUB)
630 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
631 return DAG.getNode(ISD::SUB, VT,
632 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
635 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
638 // fold ((0-A) + B) -> B-A
639 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
640 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
641 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
642 // fold (A + (0-B)) -> A-B
643 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
644 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
645 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
646 // fold (A+(B-A)) -> B
647 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
648 return N1.getOperand(0);
650 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
651 return SDOperand(N, 0);
653 // fold (a+b) -> (a|b) iff a and b share no bits.
654 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
655 uint64_t LHSZero, LHSOne;
656 uint64_t RHSZero, RHSOne;
657 uint64_t Mask = MVT::getIntVTBitMask(VT);
658 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
660 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
662 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
663 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
664 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
665 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
666 return DAG.getNode(ISD::OR, VT, N0, N1);
673 SDOperand DAGCombiner::visitSUB(SDNode *N) {
674 SDOperand N0 = N->getOperand(0);
675 SDOperand N1 = N->getOperand(1);
676 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
677 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
678 MVT::ValueType VT = N0.getValueType();
680 // fold (sub x, x) -> 0
682 return DAG.getConstant(0, N->getValueType(0));
683 // fold (sub c1, c2) -> c1-c2
685 return DAG.getNode(ISD::SUB, VT, N0, N1);
686 // fold (sub x, c) -> (add x, -c)
688 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
690 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
691 return N0.getOperand(1);
693 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
694 return N0.getOperand(0);
698 SDOperand DAGCombiner::visitMUL(SDNode *N) {
699 SDOperand N0 = N->getOperand(0);
700 SDOperand N1 = N->getOperand(1);
701 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
702 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
703 MVT::ValueType VT = N0.getValueType();
705 // fold (mul c1, c2) -> c1*c2
707 return DAG.getNode(ISD::MUL, VT, N0, N1);
708 // canonicalize constant to RHS
710 return DAG.getNode(ISD::MUL, VT, N1, N0);
711 // fold (mul x, 0) -> 0
712 if (N1C && N1C->isNullValue())
714 // fold (mul x, -1) -> 0-x
715 if (N1C && N1C->isAllOnesValue())
716 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
717 // fold (mul x, (1 << c)) -> x << c
718 if (N1C && isPowerOf2_64(N1C->getValue()))
719 return DAG.getNode(ISD::SHL, VT, N0,
720 DAG.getConstant(Log2_64(N1C->getValue()),
721 TLI.getShiftAmountTy()));
722 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
723 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
724 // FIXME: If the input is something that is easily negated (e.g. a
725 // single-use add), we should put the negate there.
726 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
727 DAG.getNode(ISD::SHL, VT, N0,
728 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
729 TLI.getShiftAmountTy())));
732 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
733 if (N1C && N0.getOpcode() == ISD::SHL &&
734 isa<ConstantSDNode>(N0.getOperand(1))) {
735 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
736 AddToWorkList(C3.Val);
737 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
740 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
743 SDOperand Sh(0,0), Y(0,0);
744 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
745 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
746 N0.Val->hasOneUse()) {
748 } else if (N1.getOpcode() == ISD::SHL &&
749 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
753 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
754 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
757 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
758 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
759 isa<ConstantSDNode>(N0.getOperand(1))) {
760 return DAG.getNode(ISD::ADD, VT,
761 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
762 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
766 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
772 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
773 SDOperand N0 = N->getOperand(0);
774 SDOperand N1 = N->getOperand(1);
775 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
776 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
777 MVT::ValueType VT = N->getValueType(0);
779 // fold (sdiv c1, c2) -> c1/c2
780 if (N0C && N1C && !N1C->isNullValue())
781 return DAG.getNode(ISD::SDIV, VT, N0, N1);
782 // fold (sdiv X, 1) -> X
783 if (N1C && N1C->getSignExtended() == 1LL)
785 // fold (sdiv X, -1) -> 0-X
786 if (N1C && N1C->isAllOnesValue())
787 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
788 // If we know the sign bits of both operands are zero, strength reduce to a
789 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
790 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
791 if (TLI.MaskedValueIsZero(N1, SignBit) &&
792 TLI.MaskedValueIsZero(N0, SignBit))
793 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
794 // fold (sdiv X, pow2) -> simple ops after legalize
795 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
796 (isPowerOf2_64(N1C->getSignExtended()) ||
797 isPowerOf2_64(-N1C->getSignExtended()))) {
798 // If dividing by powers of two is cheap, then don't perform the following
800 if (TLI.isPow2DivCheap())
802 int64_t pow2 = N1C->getSignExtended();
803 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
804 unsigned lg2 = Log2_64(abs2);
805 // Splat the sign bit into the register
806 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
807 DAG.getConstant(MVT::getSizeInBits(VT)-1,
808 TLI.getShiftAmountTy()));
809 AddToWorkList(SGN.Val);
810 // Add (N0 < 0) ? abs2 - 1 : 0;
811 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
812 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
813 TLI.getShiftAmountTy()));
814 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
815 AddToWorkList(SRL.Val);
816 AddToWorkList(ADD.Val); // Divide by pow2
817 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
818 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
819 // If we're dividing by a positive value, we're done. Otherwise, we must
820 // negate the result.
823 AddToWorkList(SRA.Val);
824 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
826 // if integer divide is expensive and we satisfy the requirements, emit an
827 // alternate sequence.
828 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
829 !TLI.isIntDivCheap()) {
830 SDOperand Op = BuildSDIV(N);
831 if (Op.Val) return Op;
836 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
837 SDOperand N0 = N->getOperand(0);
838 SDOperand N1 = N->getOperand(1);
839 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
840 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
841 MVT::ValueType VT = N->getValueType(0);
843 // fold (udiv c1, c2) -> c1/c2
844 if (N0C && N1C && !N1C->isNullValue())
845 return DAG.getNode(ISD::UDIV, VT, N0, N1);
846 // fold (udiv x, (1 << c)) -> x >>u c
847 if (N1C && isPowerOf2_64(N1C->getValue()))
848 return DAG.getNode(ISD::SRL, VT, N0,
849 DAG.getConstant(Log2_64(N1C->getValue()),
850 TLI.getShiftAmountTy()));
851 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
852 if (N1.getOpcode() == ISD::SHL) {
853 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
854 if (isPowerOf2_64(SHC->getValue())) {
855 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
856 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
857 DAG.getConstant(Log2_64(SHC->getValue()),
859 AddToWorkList(Add.Val);
860 return DAG.getNode(ISD::SRL, VT, N0, Add);
864 // fold (udiv x, c) -> alternate
865 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
866 SDOperand Op = BuildUDIV(N);
867 if (Op.Val) return Op;
872 SDOperand DAGCombiner::visitSREM(SDNode *N) {
873 SDOperand N0 = N->getOperand(0);
874 SDOperand N1 = N->getOperand(1);
875 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
876 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
877 MVT::ValueType VT = N->getValueType(0);
879 // fold (srem c1, c2) -> c1%c2
880 if (N0C && N1C && !N1C->isNullValue())
881 return DAG.getNode(ISD::SREM, VT, N0, N1);
882 // If we know the sign bits of both operands are zero, strength reduce to a
883 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
884 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
885 if (TLI.MaskedValueIsZero(N1, SignBit) &&
886 TLI.MaskedValueIsZero(N0, SignBit))
887 return DAG.getNode(ISD::UREM, VT, N0, N1);
891 SDOperand DAGCombiner::visitUREM(SDNode *N) {
892 SDOperand N0 = N->getOperand(0);
893 SDOperand N1 = N->getOperand(1);
894 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
895 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
896 MVT::ValueType VT = N->getValueType(0);
898 // fold (urem c1, c2) -> c1%c2
899 if (N0C && N1C && !N1C->isNullValue())
900 return DAG.getNode(ISD::UREM, VT, N0, N1);
901 // fold (urem x, pow2) -> (and x, pow2-1)
902 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
903 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
904 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
905 if (N1.getOpcode() == ISD::SHL) {
906 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
907 if (isPowerOf2_64(SHC->getValue())) {
908 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
909 AddToWorkList(Add.Val);
910 return DAG.getNode(ISD::AND, VT, N0, Add);
917 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
918 SDOperand N0 = N->getOperand(0);
919 SDOperand N1 = N->getOperand(1);
920 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
922 // fold (mulhs x, 0) -> 0
923 if (N1C && N1C->isNullValue())
925 // fold (mulhs x, 1) -> (sra x, size(x)-1)
926 if (N1C && N1C->getValue() == 1)
927 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
928 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
929 TLI.getShiftAmountTy()));
933 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
934 SDOperand N0 = N->getOperand(0);
935 SDOperand N1 = N->getOperand(1);
936 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
938 // fold (mulhu x, 0) -> 0
939 if (N1C && N1C->isNullValue())
941 // fold (mulhu x, 1) -> 0
942 if (N1C && N1C->getValue() == 1)
943 return DAG.getConstant(0, N0.getValueType());
947 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
948 /// two operands of the same opcode, try to simplify it.
949 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
950 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
951 MVT::ValueType VT = N0.getValueType();
952 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
954 // For each of OP in AND/OR/XOR:
955 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
956 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
957 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
958 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
959 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
960 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
961 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
962 SDOperand ORNode = DAG.getNode(N->getOpcode(),
963 N0.getOperand(0).getValueType(),
964 N0.getOperand(0), N1.getOperand(0));
965 AddToWorkList(ORNode.Val);
966 return DAG.getNode(N0.getOpcode(), VT, ORNode);
969 // For each of OP in SHL/SRL/SRA/AND...
970 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
971 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
972 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
973 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
974 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
975 N0.getOperand(1) == N1.getOperand(1)) {
976 SDOperand ORNode = DAG.getNode(N->getOpcode(),
977 N0.getOperand(0).getValueType(),
978 N0.getOperand(0), N1.getOperand(0));
979 AddToWorkList(ORNode.Val);
980 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
986 SDOperand DAGCombiner::visitAND(SDNode *N) {
987 SDOperand N0 = N->getOperand(0);
988 SDOperand N1 = N->getOperand(1);
989 SDOperand LL, LR, RL, RR, CC0, CC1;
990 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
991 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
992 MVT::ValueType VT = N1.getValueType();
993 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
995 // fold (and c1, c2) -> c1&c2
997 return DAG.getNode(ISD::AND, VT, N0, N1);
998 // canonicalize constant to RHS
1000 return DAG.getNode(ISD::AND, VT, N1, N0);
1001 // fold (and x, -1) -> x
1002 if (N1C && N1C->isAllOnesValue())
1004 // if (and x, c) is known to be zero, return 0
1005 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1006 return DAG.getConstant(0, VT);
1008 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1011 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1012 if (N1C && N0.getOpcode() == ISD::OR)
1013 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1014 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1016 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1017 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1018 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1019 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1020 ~N1C->getValue() & InMask)) {
1021 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1024 // Replace uses of the AND with uses of the Zero extend node.
1027 // We actually want to replace all uses of the any_extend with the
1028 // zero_extend, to avoid duplicating things. This will later cause this
1029 // AND to be folded.
1030 CombineTo(N0.Val, Zext);
1031 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1034 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1035 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1036 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1037 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1039 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1040 MVT::isInteger(LL.getValueType())) {
1041 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1042 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1043 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1044 AddToWorkList(ORNode.Val);
1045 return DAG.getSetCC(VT, ORNode, LR, Op1);
1047 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1048 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1049 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1050 AddToWorkList(ANDNode.Val);
1051 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1053 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1054 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1055 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1056 AddToWorkList(ORNode.Val);
1057 return DAG.getSetCC(VT, ORNode, LR, Op1);
1060 // canonicalize equivalent to ll == rl
1061 if (LL == RR && LR == RL) {
1062 Op1 = ISD::getSetCCSwappedOperands(Op1);
1065 if (LL == RL && LR == RR) {
1066 bool isInteger = MVT::isInteger(LL.getValueType());
1067 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1068 if (Result != ISD::SETCC_INVALID)
1069 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1073 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1074 if (N0.getOpcode() == N1.getOpcode()) {
1075 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1076 if (Tmp.Val) return Tmp;
1079 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1080 // fold (and (sra)) -> (and (srl)) when possible.
1081 if (!MVT::isVector(VT) &&
1082 SimplifyDemandedBits(SDOperand(N, 0)))
1083 return SDOperand(N, 0);
1084 // fold (zext_inreg (extload x)) -> (zextload x)
1085 if (ISD::isEXTLoad(N0.Val)) {
1086 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1087 MVT::ValueType EVT = LN0->getLoadedVT();
1088 // If we zero all the possible extended bits, then we can turn this into
1089 // a zextload if we are running before legalize or the operation is legal.
1090 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1091 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1092 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1093 LN0->getBasePtr(), LN0->getSrcValue(),
1094 LN0->getSrcValueOffset(), EVT);
1096 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1097 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1100 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1101 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
1102 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1103 MVT::ValueType EVT = LN0->getLoadedVT();
1104 // If we zero all the possible extended bits, then we can turn this into
1105 // a zextload if we are running before legalize or the operation is legal.
1106 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1107 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1108 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1109 LN0->getBasePtr(), LN0->getSrcValue(),
1110 LN0->getSrcValueOffset(), EVT);
1112 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1113 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1117 // fold (and (load x), 255) -> (zextload x, i8)
1118 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1119 if (N1C && N0.getOpcode() == ISD::LOAD) {
1120 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1121 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1123 MVT::ValueType EVT, LoadedVT;
1124 if (N1C->getValue() == 255)
1126 else if (N1C->getValue() == 65535)
1128 else if (N1C->getValue() == ~0U)
1133 LoadedVT = LN0->getLoadedVT();
1134 if (EVT != MVT::Other && LoadedVT > EVT &&
1135 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1136 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1137 // For big endian targets, we need to add an offset to the pointer to
1138 // load the correct bytes. For little endian systems, we merely need to
1139 // read fewer bytes from the same pointer.
1141 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1142 SDOperand NewPtr = LN0->getBasePtr();
1143 if (!TLI.isLittleEndian())
1144 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1145 DAG.getConstant(PtrOff, PtrType));
1146 AddToWorkList(NewPtr.Val);
1148 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1149 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1151 CombineTo(N0.Val, Load, Load.getValue(1));
1152 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1160 SDOperand DAGCombiner::visitOR(SDNode *N) {
1161 SDOperand N0 = N->getOperand(0);
1162 SDOperand N1 = N->getOperand(1);
1163 SDOperand LL, LR, RL, RR, CC0, CC1;
1164 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1165 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1166 MVT::ValueType VT = N1.getValueType();
1167 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1169 // fold (or c1, c2) -> c1|c2
1171 return DAG.getNode(ISD::OR, VT, N0, N1);
1172 // canonicalize constant to RHS
1174 return DAG.getNode(ISD::OR, VT, N1, N0);
1175 // fold (or x, 0) -> x
1176 if (N1C && N1C->isNullValue())
1178 // fold (or x, -1) -> -1
1179 if (N1C && N1C->isAllOnesValue())
1181 // fold (or x, c) -> c iff (x & ~c) == 0
1183 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1186 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1189 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1190 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1191 isa<ConstantSDNode>(N0.getOperand(1))) {
1192 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1193 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1195 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1197 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1198 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1199 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1200 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1202 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1203 MVT::isInteger(LL.getValueType())) {
1204 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1205 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1206 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1207 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1208 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1209 AddToWorkList(ORNode.Val);
1210 return DAG.getSetCC(VT, ORNode, LR, Op1);
1212 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1213 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1214 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1215 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1216 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1217 AddToWorkList(ANDNode.Val);
1218 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1221 // canonicalize equivalent to ll == rl
1222 if (LL == RR && LR == RL) {
1223 Op1 = ISD::getSetCCSwappedOperands(Op1);
1226 if (LL == RL && LR == RR) {
1227 bool isInteger = MVT::isInteger(LL.getValueType());
1228 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1229 if (Result != ISD::SETCC_INVALID)
1230 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1234 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1235 if (N0.getOpcode() == N1.getOpcode()) {
1236 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1237 if (Tmp.Val) return Tmp;
1240 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1241 if (N0.getOpcode() == ISD::AND &&
1242 N1.getOpcode() == ISD::AND &&
1243 N0.getOperand(1).getOpcode() == ISD::Constant &&
1244 N1.getOperand(1).getOpcode() == ISD::Constant &&
1245 // Don't increase # computations.
1246 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1247 // We can only do this xform if we know that bits from X that are set in C2
1248 // but not in C1 are already zero. Likewise for Y.
1249 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1250 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1252 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1253 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1254 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1255 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1260 // See if this is some rotate idiom.
1261 if (SDNode *Rot = MatchRotate(N0, N1))
1262 return SDOperand(Rot, 0);
1268 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1269 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1270 if (Op.getOpcode() == ISD::AND) {
1271 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1272 Mask = Op.getOperand(1);
1273 Op = Op.getOperand(0);
1279 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1287 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1288 // idioms for rotate, and if the target supports rotation instructions, generate
1290 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1291 // Must be a legal type. Expanded an promoted things won't work with rotates.
1292 MVT::ValueType VT = LHS.getValueType();
1293 if (!TLI.isTypeLegal(VT)) return 0;
1295 // The target must have at least one rotate flavor.
1296 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1297 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1298 if (!HasROTL && !HasROTR) return 0;
1300 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1301 SDOperand LHSShift; // The shift.
1302 SDOperand LHSMask; // AND value if any.
1303 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1304 return 0; // Not part of a rotate.
1306 SDOperand RHSShift; // The shift.
1307 SDOperand RHSMask; // AND value if any.
1308 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1309 return 0; // Not part of a rotate.
1311 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1312 return 0; // Not shifting the same value.
1314 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1315 return 0; // Shifts must disagree.
1317 // Canonicalize shl to left side in a shl/srl pair.
1318 if (RHSShift.getOpcode() == ISD::SHL) {
1319 std::swap(LHS, RHS);
1320 std::swap(LHSShift, RHSShift);
1321 std::swap(LHSMask , RHSMask );
1324 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1326 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1327 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1328 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1329 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1330 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1331 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1332 if ((LShVal + RShVal) != OpSizeInBits)
1337 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1338 LHSShift.getOperand(1));
1340 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1341 RHSShift.getOperand(1));
1343 // If there is an AND of either shifted operand, apply it to the result.
1344 if (LHSMask.Val || RHSMask.Val) {
1345 uint64_t Mask = MVT::getIntVTBitMask(VT);
1348 uint64_t RHSBits = (1ULL << LShVal)-1;
1349 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1352 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1353 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1356 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1362 // If there is a mask here, and we have a variable shift, we can't be sure
1363 // that we're masking out the right stuff.
1364 if (LHSMask.Val || RHSMask.Val)
1367 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1368 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1369 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1370 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1371 if (ConstantSDNode *SUBC =
1372 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1373 if (SUBC->getValue() == OpSizeInBits)
1375 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1376 LHSShift.getOperand(1)).Val;
1378 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1379 LHSShift.getOperand(1)).Val;
1383 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1384 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1385 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1386 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1387 if (ConstantSDNode *SUBC =
1388 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1389 if (SUBC->getValue() == OpSizeInBits)
1391 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1392 LHSShift.getOperand(1)).Val;
1394 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1395 RHSShift.getOperand(1)).Val;
1403 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1404 SDOperand N0 = N->getOperand(0);
1405 SDOperand N1 = N->getOperand(1);
1406 SDOperand LHS, RHS, CC;
1407 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1408 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1409 MVT::ValueType VT = N0.getValueType();
1411 // fold (xor c1, c2) -> c1^c2
1413 return DAG.getNode(ISD::XOR, VT, N0, N1);
1414 // canonicalize constant to RHS
1416 return DAG.getNode(ISD::XOR, VT, N1, N0);
1417 // fold (xor x, 0) -> x
1418 if (N1C && N1C->isNullValue())
1421 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1424 // fold !(x cc y) -> (x !cc y)
1425 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1426 bool isInt = MVT::isInteger(LHS.getValueType());
1427 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1429 if (N0.getOpcode() == ISD::SETCC)
1430 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1431 if (N0.getOpcode() == ISD::SELECT_CC)
1432 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1433 assert(0 && "Unhandled SetCC Equivalent!");
1436 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1437 if (N1C && N1C->getValue() == 1 &&
1438 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1439 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1440 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1441 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1442 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1443 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1444 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1445 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1448 // fold !(x or y) -> (!x and !y) iff x or y are constants
1449 if (N1C && N1C->isAllOnesValue() &&
1450 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1451 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1452 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1453 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1454 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1455 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1456 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1457 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1460 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1461 if (N1C && N0.getOpcode() == ISD::XOR) {
1462 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1463 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1465 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1466 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1468 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1469 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1471 // fold (xor x, x) -> 0
1473 if (!MVT::isVector(VT)) {
1474 return DAG.getConstant(0, VT);
1475 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1476 // Produce a vector of zeros.
1477 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1478 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1479 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1483 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1484 if (N0.getOpcode() == N1.getOpcode()) {
1485 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1486 if (Tmp.Val) return Tmp;
1489 // Simplify the expression using non-local knowledge.
1490 if (!MVT::isVector(VT) &&
1491 SimplifyDemandedBits(SDOperand(N, 0)))
1492 return SDOperand(N, 0);
1497 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1498 SDOperand N0 = N->getOperand(0);
1499 SDOperand N1 = N->getOperand(1);
1500 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1501 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1502 MVT::ValueType VT = N0.getValueType();
1503 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1505 // fold (shl c1, c2) -> c1<<c2
1507 return DAG.getNode(ISD::SHL, VT, N0, N1);
1508 // fold (shl 0, x) -> 0
1509 if (N0C && N0C->isNullValue())
1511 // fold (shl x, c >= size(x)) -> undef
1512 if (N1C && N1C->getValue() >= OpSizeInBits)
1513 return DAG.getNode(ISD::UNDEF, VT);
1514 // fold (shl x, 0) -> x
1515 if (N1C && N1C->isNullValue())
1517 // if (shl x, c) is known to be zero, return 0
1518 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1519 return DAG.getConstant(0, VT);
1520 if (SimplifyDemandedBits(SDOperand(N, 0)))
1521 return SDOperand(N, 0);
1522 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1523 if (N1C && N0.getOpcode() == ISD::SHL &&
1524 N0.getOperand(1).getOpcode() == ISD::Constant) {
1525 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1526 uint64_t c2 = N1C->getValue();
1527 if (c1 + c2 > OpSizeInBits)
1528 return DAG.getConstant(0, VT);
1529 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1530 DAG.getConstant(c1 + c2, N1.getValueType()));
1532 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1533 // (srl (and x, -1 << c1), c1-c2)
1534 if (N1C && N0.getOpcode() == ISD::SRL &&
1535 N0.getOperand(1).getOpcode() == ISD::Constant) {
1536 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1537 uint64_t c2 = N1C->getValue();
1538 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1539 DAG.getConstant(~0ULL << c1, VT));
1541 return DAG.getNode(ISD::SHL, VT, Mask,
1542 DAG.getConstant(c2-c1, N1.getValueType()));
1544 return DAG.getNode(ISD::SRL, VT, Mask,
1545 DAG.getConstant(c1-c2, N1.getValueType()));
1547 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1548 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1549 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1550 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1551 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1552 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1553 isa<ConstantSDNode>(N0.getOperand(1))) {
1554 return DAG.getNode(ISD::ADD, VT,
1555 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1556 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1561 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1562 SDOperand N0 = N->getOperand(0);
1563 SDOperand N1 = N->getOperand(1);
1564 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1565 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1566 MVT::ValueType VT = N0.getValueType();
1568 // fold (sra c1, c2) -> c1>>c2
1570 return DAG.getNode(ISD::SRA, VT, N0, N1);
1571 // fold (sra 0, x) -> 0
1572 if (N0C && N0C->isNullValue())
1574 // fold (sra -1, x) -> -1
1575 if (N0C && N0C->isAllOnesValue())
1577 // fold (sra x, c >= size(x)) -> undef
1578 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1579 return DAG.getNode(ISD::UNDEF, VT);
1580 // fold (sra x, 0) -> x
1581 if (N1C && N1C->isNullValue())
1583 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1585 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1586 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1589 default: EVT = MVT::Other; break;
1590 case 1: EVT = MVT::i1; break;
1591 case 8: EVT = MVT::i8; break;
1592 case 16: EVT = MVT::i16; break;
1593 case 32: EVT = MVT::i32; break;
1595 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1596 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1597 DAG.getValueType(EVT));
1600 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1601 if (N1C && N0.getOpcode() == ISD::SRA) {
1602 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1603 unsigned Sum = N1C->getValue() + C1->getValue();
1604 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1605 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1606 DAG.getConstant(Sum, N1C->getValueType(0)));
1610 // Simplify, based on bits shifted out of the LHS.
1611 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1612 return SDOperand(N, 0);
1615 // If the sign bit is known to be zero, switch this to a SRL.
1616 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1617 return DAG.getNode(ISD::SRL, VT, N0, N1);
1621 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1622 SDOperand N0 = N->getOperand(0);
1623 SDOperand N1 = N->getOperand(1);
1624 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1625 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1626 MVT::ValueType VT = N0.getValueType();
1627 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1629 // fold (srl c1, c2) -> c1 >>u c2
1631 return DAG.getNode(ISD::SRL, VT, N0, N1);
1632 // fold (srl 0, x) -> 0
1633 if (N0C && N0C->isNullValue())
1635 // fold (srl x, c >= size(x)) -> undef
1636 if (N1C && N1C->getValue() >= OpSizeInBits)
1637 return DAG.getNode(ISD::UNDEF, VT);
1638 // fold (srl x, 0) -> x
1639 if (N1C && N1C->isNullValue())
1641 // if (srl x, c) is known to be zero, return 0
1642 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1643 return DAG.getConstant(0, VT);
1644 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1645 if (N1C && N0.getOpcode() == ISD::SRL &&
1646 N0.getOperand(1).getOpcode() == ISD::Constant) {
1647 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1648 uint64_t c2 = N1C->getValue();
1649 if (c1 + c2 > OpSizeInBits)
1650 return DAG.getConstant(0, VT);
1651 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1652 DAG.getConstant(c1 + c2, N1.getValueType()));
1655 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1656 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1657 // Shifting in all undef bits?
1658 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1659 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1660 return DAG.getNode(ISD::UNDEF, VT);
1662 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1663 AddToWorkList(SmallShift.Val);
1664 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1667 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1668 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1669 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1670 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1671 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1673 // If any of the input bits are KnownOne, then the input couldn't be all
1674 // zeros, thus the result of the srl will always be zero.
1675 if (KnownOne) return DAG.getConstant(0, VT);
1677 // If all of the bits input the to ctlz node are known to be zero, then
1678 // the result of the ctlz is "32" and the result of the shift is one.
1679 uint64_t UnknownBits = ~KnownZero & Mask;
1680 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1682 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1683 if ((UnknownBits & (UnknownBits-1)) == 0) {
1684 // Okay, we know that only that the single bit specified by UnknownBits
1685 // could be set on input to the CTLZ node. If this bit is set, the SRL
1686 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1687 // to an SRL,XOR pair, which is likely to simplify more.
1688 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1689 SDOperand Op = N0.getOperand(0);
1691 Op = DAG.getNode(ISD::SRL, VT, Op,
1692 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1693 AddToWorkList(Op.Val);
1695 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1702 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1703 SDOperand N0 = N->getOperand(0);
1704 MVT::ValueType VT = N->getValueType(0);
1706 // fold (ctlz c1) -> c2
1707 if (isa<ConstantSDNode>(N0))
1708 return DAG.getNode(ISD::CTLZ, VT, N0);
1712 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1713 SDOperand N0 = N->getOperand(0);
1714 MVT::ValueType VT = N->getValueType(0);
1716 // fold (cttz c1) -> c2
1717 if (isa<ConstantSDNode>(N0))
1718 return DAG.getNode(ISD::CTTZ, VT, N0);
1722 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1723 SDOperand N0 = N->getOperand(0);
1724 MVT::ValueType VT = N->getValueType(0);
1726 // fold (ctpop c1) -> c2
1727 if (isa<ConstantSDNode>(N0))
1728 return DAG.getNode(ISD::CTPOP, VT, N0);
1732 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1733 SDOperand N0 = N->getOperand(0);
1734 SDOperand N1 = N->getOperand(1);
1735 SDOperand N2 = N->getOperand(2);
1736 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1737 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1738 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1739 MVT::ValueType VT = N->getValueType(0);
1741 // fold select C, X, X -> X
1744 // fold select true, X, Y -> X
1745 if (N0C && !N0C->isNullValue())
1747 // fold select false, X, Y -> Y
1748 if (N0C && N0C->isNullValue())
1750 // fold select C, 1, X -> C | X
1751 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1752 return DAG.getNode(ISD::OR, VT, N0, N2);
1753 // fold select C, 0, X -> ~C & X
1754 // FIXME: this should check for C type == X type, not i1?
1755 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1756 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1757 AddToWorkList(XORNode.Val);
1758 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1760 // fold select C, X, 1 -> ~C | X
1761 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1762 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1763 AddToWorkList(XORNode.Val);
1764 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1766 // fold select C, X, 0 -> C & X
1767 // FIXME: this should check for C type == X type, not i1?
1768 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1769 return DAG.getNode(ISD::AND, VT, N0, N1);
1770 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1771 if (MVT::i1 == VT && N0 == N1)
1772 return DAG.getNode(ISD::OR, VT, N0, N2);
1773 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1774 if (MVT::i1 == VT && N0 == N2)
1775 return DAG.getNode(ISD::AND, VT, N0, N1);
1777 // If we can fold this based on the true/false value, do so.
1778 if (SimplifySelectOps(N, N1, N2))
1779 return SDOperand(N, 0); // Don't revisit N.
1781 // fold selects based on a setcc into other things, such as min/max/abs
1782 if (N0.getOpcode() == ISD::SETCC)
1784 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1785 // having to say they don't support SELECT_CC on every type the DAG knows
1786 // about, since there is no way to mark an opcode illegal at all value types
1787 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1788 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1789 N1, N2, N0.getOperand(2));
1791 return SimplifySelect(N0, N1, N2);
1795 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1796 SDOperand N0 = N->getOperand(0);
1797 SDOperand N1 = N->getOperand(1);
1798 SDOperand N2 = N->getOperand(2);
1799 SDOperand N3 = N->getOperand(3);
1800 SDOperand N4 = N->getOperand(4);
1801 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1802 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1803 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1804 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1806 // fold select_cc lhs, rhs, x, x, cc -> x
1810 // Determine if the condition we're dealing with is constant
1811 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1813 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1814 if (SCCC->getValue())
1815 return N2; // cond always true -> true val
1817 return N3; // cond always false -> false val
1820 // Fold to a simpler select_cc
1821 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1822 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1823 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1826 // If we can fold this based on the true/false value, do so.
1827 if (SimplifySelectOps(N, N2, N3))
1828 return SDOperand(N, 0); // Don't revisit N.
1830 // fold select_cc into other things, such as min/max/abs
1831 return SimplifySelectCC(N0, N1, N2, N3, CC);
1834 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1835 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1836 cast<CondCodeSDNode>(N->getOperand(2))->get());
1839 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1840 SDOperand N0 = N->getOperand(0);
1841 MVT::ValueType VT = N->getValueType(0);
1843 // fold (sext c1) -> c1
1844 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1845 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1847 // fold (sext (sext x)) -> (sext x)
1848 // fold (sext (aext x)) -> (sext x)
1849 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1850 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1852 // fold (sext (truncate x)) -> (sextinreg x).
1853 if (N0.getOpcode() == ISD::TRUNCATE &&
1854 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
1855 N0.getValueType()))) {
1856 SDOperand Op = N0.getOperand(0);
1857 if (Op.getValueType() < VT) {
1858 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1859 } else if (Op.getValueType() > VT) {
1860 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1862 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
1863 DAG.getValueType(N0.getValueType()));
1866 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1867 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1868 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
1869 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1870 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1871 LN0->getBasePtr(), LN0->getSrcValue(),
1872 LN0->getSrcValueOffset(),
1874 CombineTo(N, ExtLoad);
1875 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1876 ExtLoad.getValue(1));
1877 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1880 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1881 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1882 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1883 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1884 MVT::ValueType EVT = LN0->getLoadedVT();
1885 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1886 LN0->getBasePtr(), LN0->getSrcValue(),
1887 LN0->getSrcValueOffset(), EVT);
1888 CombineTo(N, ExtLoad);
1889 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1890 ExtLoad.getValue(1));
1891 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1897 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1898 SDOperand N0 = N->getOperand(0);
1899 MVT::ValueType VT = N->getValueType(0);
1901 // fold (zext c1) -> c1
1902 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1903 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1904 // fold (zext (zext x)) -> (zext x)
1905 // fold (zext (aext x)) -> (zext x)
1906 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1907 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1909 // fold (zext (truncate x)) -> (and x, mask)
1910 if (N0.getOpcode() == ISD::TRUNCATE &&
1911 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
1912 SDOperand Op = N0.getOperand(0);
1913 if (Op.getValueType() < VT) {
1914 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1915 } else if (Op.getValueType() > VT) {
1916 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1918 return DAG.getZeroExtendInReg(Op, N0.getValueType());
1921 // fold (zext (and (trunc x), cst)) -> (and x, cst).
1922 if (N0.getOpcode() == ISD::AND &&
1923 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1924 N0.getOperand(1).getOpcode() == ISD::Constant) {
1925 SDOperand X = N0.getOperand(0).getOperand(0);
1926 if (X.getValueType() < VT) {
1927 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1928 } else if (X.getValueType() > VT) {
1929 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1931 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1932 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
1935 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1936 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1937 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
1938 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1939 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1940 LN0->getBasePtr(), LN0->getSrcValue(),
1941 LN0->getSrcValueOffset(),
1943 CombineTo(N, ExtLoad);
1944 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1945 ExtLoad.getValue(1));
1946 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1949 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1950 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1951 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1952 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1953 MVT::ValueType EVT = LN0->getLoadedVT();
1954 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1955 LN0->getBasePtr(), LN0->getSrcValue(),
1956 LN0->getSrcValueOffset(), EVT);
1957 CombineTo(N, ExtLoad);
1958 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1959 ExtLoad.getValue(1));
1960 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1965 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
1966 SDOperand N0 = N->getOperand(0);
1967 MVT::ValueType VT = N->getValueType(0);
1969 // fold (aext c1) -> c1
1970 if (isa<ConstantSDNode>(N0))
1971 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
1972 // fold (aext (aext x)) -> (aext x)
1973 // fold (aext (zext x)) -> (zext x)
1974 // fold (aext (sext x)) -> (sext x)
1975 if (N0.getOpcode() == ISD::ANY_EXTEND ||
1976 N0.getOpcode() == ISD::ZERO_EXTEND ||
1977 N0.getOpcode() == ISD::SIGN_EXTEND)
1978 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1980 // fold (aext (truncate x))
1981 if (N0.getOpcode() == ISD::TRUNCATE) {
1982 SDOperand TruncOp = N0.getOperand(0);
1983 if (TruncOp.getValueType() == VT)
1984 return TruncOp; // x iff x size == zext size.
1985 if (TruncOp.getValueType() > VT)
1986 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
1987 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
1990 // fold (aext (and (trunc x), cst)) -> (and x, cst).
1991 if (N0.getOpcode() == ISD::AND &&
1992 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1993 N0.getOperand(1).getOpcode() == ISD::Constant) {
1994 SDOperand X = N0.getOperand(0).getOperand(0);
1995 if (X.getValueType() < VT) {
1996 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1997 } else if (X.getValueType() > VT) {
1998 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2000 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2001 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2004 // fold (aext (load x)) -> (aext (truncate (extload x)))
2005 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2006 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2007 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2008 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2009 LN0->getBasePtr(), LN0->getSrcValue(),
2010 LN0->getSrcValueOffset(),
2012 CombineTo(N, ExtLoad);
2013 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2014 ExtLoad.getValue(1));
2015 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2018 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2019 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2020 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2021 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
2023 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2024 MVT::ValueType EVT = LN0->getLoadedVT();
2025 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2026 LN0->getChain(), LN0->getBasePtr(),
2028 LN0->getSrcValueOffset(), EVT);
2029 CombineTo(N, ExtLoad);
2030 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2031 ExtLoad.getValue(1));
2032 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2038 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2039 SDOperand N0 = N->getOperand(0);
2040 SDOperand N1 = N->getOperand(1);
2041 MVT::ValueType VT = N->getValueType(0);
2042 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2043 unsigned EVTBits = MVT::getSizeInBits(EVT);
2045 // fold (sext_in_reg c1) -> c1
2046 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2047 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2049 // If the input is already sign extended, just drop the extension.
2050 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2053 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2054 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2055 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2056 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2059 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2060 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2061 return DAG.getZeroExtendInReg(N0, EVT);
2063 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2064 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2065 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2066 if (N0.getOpcode() == ISD::SRL) {
2067 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2068 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2069 // We can turn this into an SRA iff the input to the SRL is already sign
2071 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2072 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2073 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2077 // fold (sext_inreg (extload x)) -> (sextload x)
2078 if (ISD::isEXTLoad(N0.Val) &&
2079 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2080 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2081 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2082 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2083 LN0->getBasePtr(), LN0->getSrcValue(),
2084 LN0->getSrcValueOffset(), EVT);
2085 CombineTo(N, ExtLoad);
2086 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2087 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2089 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2090 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
2091 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2092 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2093 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2094 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2095 LN0->getBasePtr(), LN0->getSrcValue(),
2096 LN0->getSrcValueOffset(), EVT);
2097 CombineTo(N, ExtLoad);
2098 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2099 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2104 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2105 SDOperand N0 = N->getOperand(0);
2106 MVT::ValueType VT = N->getValueType(0);
2109 if (N0.getValueType() == N->getValueType(0))
2111 // fold (truncate c1) -> c1
2112 if (isa<ConstantSDNode>(N0))
2113 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2114 // fold (truncate (truncate x)) -> (truncate x)
2115 if (N0.getOpcode() == ISD::TRUNCATE)
2116 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2117 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2118 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2119 N0.getOpcode() == ISD::ANY_EXTEND) {
2120 if (N0.getValueType() < VT)
2121 // if the source is smaller than the dest, we still need an extend
2122 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2123 else if (N0.getValueType() > VT)
2124 // if the source is larger than the dest, than we just need the truncate
2125 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2127 // if the source and dest are the same type, we can drop both the extend
2129 return N0.getOperand(0);
2131 // fold (truncate (load x)) -> (smaller load x)
2132 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2133 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2134 "Cannot truncate to larger type!");
2135 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2136 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2137 // For big endian targets, we need to add an offset to the pointer to load
2138 // the correct bytes. For little endian systems, we merely need to read
2139 // fewer bytes from the same pointer.
2141 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2142 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() :
2143 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2144 DAG.getConstant(PtrOff, PtrType));
2145 AddToWorkList(NewPtr.Val);
2146 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr,
2147 LN0->getSrcValue(), LN0->getSrcValueOffset());
2149 CombineTo(N0.Val, Load, Load.getValue(1));
2150 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2155 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2156 SDOperand N0 = N->getOperand(0);
2157 MVT::ValueType VT = N->getValueType(0);
2159 // If the input is a constant, let getNode() fold it.
2160 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2161 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2162 if (Res.Val != N) return Res;
2165 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2166 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2168 // fold (conv (load x)) -> (load (conv*)x)
2169 // FIXME: These xforms need to know that the resultant load doesn't need a
2170 // higher alignment than the original!
2171 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2172 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2173 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2174 LN0->getSrcValue(), LN0->getSrcValueOffset());
2176 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2184 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2185 SDOperand N0 = N->getOperand(0);
2186 MVT::ValueType VT = N->getValueType(0);
2188 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2189 // First check to see if this is all constant.
2190 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2191 VT == MVT::Vector) {
2192 bool isSimple = true;
2193 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2194 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2195 N0.getOperand(i).getOpcode() != ISD::Constant &&
2196 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2201 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2202 if (isSimple && !MVT::isVector(DestEltVT)) {
2203 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2210 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2211 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2212 /// destination element value type.
2213 SDOperand DAGCombiner::
2214 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2215 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2217 // If this is already the right type, we're done.
2218 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2220 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2221 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2223 // If this is a conversion of N elements of one type to N elements of another
2224 // type, convert each element. This handles FP<->INT cases.
2225 if (SrcBitSize == DstBitSize) {
2226 SmallVector<SDOperand, 8> Ops;
2227 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2228 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2229 AddToWorkList(Ops.back().Val);
2231 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2232 Ops.push_back(DAG.getValueType(DstEltVT));
2233 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2236 // Otherwise, we're growing or shrinking the elements. To avoid having to
2237 // handle annoying details of growing/shrinking FP values, we convert them to
2239 if (MVT::isFloatingPoint(SrcEltVT)) {
2240 // Convert the input float vector to a int vector where the elements are the
2242 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2243 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2244 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2248 // Now we know the input is an integer vector. If the output is a FP type,
2249 // convert to integer first, then to FP of the right size.
2250 if (MVT::isFloatingPoint(DstEltVT)) {
2251 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2252 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2253 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2255 // Next, convert to FP elements of the same size.
2256 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2259 // Okay, we know the src/dst types are both integers of differing types.
2260 // Handling growing first.
2261 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2262 if (SrcBitSize < DstBitSize) {
2263 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2265 SmallVector<SDOperand, 8> Ops;
2266 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2267 i += NumInputsPerOutput) {
2268 bool isLE = TLI.isLittleEndian();
2269 uint64_t NewBits = 0;
2270 bool EltIsUndef = true;
2271 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2272 // Shift the previously computed bits over.
2273 NewBits <<= SrcBitSize;
2274 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2275 if (Op.getOpcode() == ISD::UNDEF) continue;
2278 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2282 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2284 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2287 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2288 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2289 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2292 // Finally, this must be the case where we are shrinking elements: each input
2293 // turns into multiple outputs.
2294 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2295 SmallVector<SDOperand, 8> Ops;
2296 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2297 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2298 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2299 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2302 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2304 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2305 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2306 OpVal >>= DstBitSize;
2307 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2310 // For big endian targets, swap the order of the pieces of each element.
2311 if (!TLI.isLittleEndian())
2312 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2314 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2315 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2316 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2321 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2322 SDOperand N0 = N->getOperand(0);
2323 SDOperand N1 = N->getOperand(1);
2324 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2325 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2326 MVT::ValueType VT = N->getValueType(0);
2328 // fold (fadd c1, c2) -> c1+c2
2330 return DAG.getNode(ISD::FADD, VT, N0, N1);
2331 // canonicalize constant to RHS
2332 if (N0CFP && !N1CFP)
2333 return DAG.getNode(ISD::FADD, VT, N1, N0);
2334 // fold (A + (-B)) -> A-B
2335 if (N1.getOpcode() == ISD::FNEG)
2336 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2337 // fold ((-A) + B) -> B-A
2338 if (N0.getOpcode() == ISD::FNEG)
2339 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2343 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2344 SDOperand N0 = N->getOperand(0);
2345 SDOperand N1 = N->getOperand(1);
2346 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2347 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2348 MVT::ValueType VT = N->getValueType(0);
2350 // fold (fsub c1, c2) -> c1-c2
2352 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2353 // fold (A-(-B)) -> A+B
2354 if (N1.getOpcode() == ISD::FNEG)
2355 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2359 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2360 SDOperand N0 = N->getOperand(0);
2361 SDOperand N1 = N->getOperand(1);
2362 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2363 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2364 MVT::ValueType VT = N->getValueType(0);
2366 // fold (fmul c1, c2) -> c1*c2
2368 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2369 // canonicalize constant to RHS
2370 if (N0CFP && !N1CFP)
2371 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2372 // fold (fmul X, 2.0) -> (fadd X, X)
2373 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2374 return DAG.getNode(ISD::FADD, VT, N0, N0);
2378 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2379 SDOperand N0 = N->getOperand(0);
2380 SDOperand N1 = N->getOperand(1);
2381 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2382 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2383 MVT::ValueType VT = N->getValueType(0);
2385 // fold (fdiv c1, c2) -> c1/c2
2387 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2391 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2392 SDOperand N0 = N->getOperand(0);
2393 SDOperand N1 = N->getOperand(1);
2394 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2395 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2396 MVT::ValueType VT = N->getValueType(0);
2398 // fold (frem c1, c2) -> fmod(c1,c2)
2400 return DAG.getNode(ISD::FREM, VT, N0, N1);
2404 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2405 SDOperand N0 = N->getOperand(0);
2406 SDOperand N1 = N->getOperand(1);
2407 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2408 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2409 MVT::ValueType VT = N->getValueType(0);
2411 if (N0CFP && N1CFP) // Constant fold
2412 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2415 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2416 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2421 u.d = N1CFP->getValue();
2423 return DAG.getNode(ISD::FABS, VT, N0);
2425 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2428 // copysign(fabs(x), y) -> copysign(x, y)
2429 // copysign(fneg(x), y) -> copysign(x, y)
2430 // copysign(copysign(x,z), y) -> copysign(x, y)
2431 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2432 N0.getOpcode() == ISD::FCOPYSIGN)
2433 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2435 // copysign(x, abs(y)) -> abs(x)
2436 if (N1.getOpcode() == ISD::FABS)
2437 return DAG.getNode(ISD::FABS, VT, N0);
2439 // copysign(x, copysign(y,z)) -> copysign(x, z)
2440 if (N1.getOpcode() == ISD::FCOPYSIGN)
2441 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2443 // copysign(x, fp_extend(y)) -> copysign(x, y)
2444 // copysign(x, fp_round(y)) -> copysign(x, y)
2445 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2446 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2453 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2454 SDOperand N0 = N->getOperand(0);
2455 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2456 MVT::ValueType VT = N->getValueType(0);
2458 // fold (sint_to_fp c1) -> c1fp
2460 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2464 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2465 SDOperand N0 = N->getOperand(0);
2466 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2467 MVT::ValueType VT = N->getValueType(0);
2469 // fold (uint_to_fp c1) -> c1fp
2471 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2475 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2476 SDOperand N0 = N->getOperand(0);
2477 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2478 MVT::ValueType VT = N->getValueType(0);
2480 // fold (fp_to_sint c1fp) -> c1
2482 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2486 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2487 SDOperand N0 = N->getOperand(0);
2488 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2489 MVT::ValueType VT = N->getValueType(0);
2491 // fold (fp_to_uint c1fp) -> c1
2493 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2497 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2498 SDOperand N0 = N->getOperand(0);
2499 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2500 MVT::ValueType VT = N->getValueType(0);
2502 // fold (fp_round c1fp) -> c1fp
2504 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2506 // fold (fp_round (fp_extend x)) -> x
2507 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2508 return N0.getOperand(0);
2510 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2511 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2512 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2513 AddToWorkList(Tmp.Val);
2514 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2520 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2521 SDOperand N0 = N->getOperand(0);
2522 MVT::ValueType VT = N->getValueType(0);
2523 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2524 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2526 // fold (fp_round_inreg c1fp) -> c1fp
2528 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2529 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2534 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2535 SDOperand N0 = N->getOperand(0);
2536 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2537 MVT::ValueType VT = N->getValueType(0);
2539 // fold (fp_extend c1fp) -> c1fp
2541 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2543 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2544 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2545 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2546 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2547 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2548 LN0->getBasePtr(), LN0->getSrcValue(),
2549 LN0->getSrcValueOffset(),
2551 CombineTo(N, ExtLoad);
2552 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2553 ExtLoad.getValue(1));
2554 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2561 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2562 SDOperand N0 = N->getOperand(0);
2563 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2564 MVT::ValueType VT = N->getValueType(0);
2566 // fold (fneg c1) -> -c1
2568 return DAG.getNode(ISD::FNEG, VT, N0);
2569 // fold (fneg (sub x, y)) -> (sub y, x)
2570 if (N0.getOpcode() == ISD::SUB)
2571 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2572 // fold (fneg (fneg x)) -> x
2573 if (N0.getOpcode() == ISD::FNEG)
2574 return N0.getOperand(0);
2578 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2579 SDOperand N0 = N->getOperand(0);
2580 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2581 MVT::ValueType VT = N->getValueType(0);
2583 // fold (fabs c1) -> fabs(c1)
2585 return DAG.getNode(ISD::FABS, VT, N0);
2586 // fold (fabs (fabs x)) -> (fabs x)
2587 if (N0.getOpcode() == ISD::FABS)
2588 return N->getOperand(0);
2589 // fold (fabs (fneg x)) -> (fabs x)
2590 // fold (fabs (fcopysign x, y)) -> (fabs x)
2591 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2592 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2597 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2598 SDOperand Chain = N->getOperand(0);
2599 SDOperand N1 = N->getOperand(1);
2600 SDOperand N2 = N->getOperand(2);
2601 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2603 // never taken branch, fold to chain
2604 if (N1C && N1C->isNullValue())
2606 // unconditional branch
2607 if (N1C && N1C->getValue() == 1)
2608 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2609 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2611 if (N1.getOpcode() == ISD::SETCC &&
2612 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2613 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2614 N1.getOperand(0), N1.getOperand(1), N2);
2619 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2621 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2622 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2623 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2625 // Use SimplifySetCC to simplify SETCC's.
2626 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2627 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2629 // fold br_cc true, dest -> br dest (unconditional branch)
2630 if (SCCC && SCCC->getValue())
2631 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2633 // fold br_cc false, dest -> unconditional fall through
2634 if (SCCC && SCCC->isNullValue())
2635 return N->getOperand(0);
2636 // fold to a simpler setcc
2637 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2638 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2639 Simp.getOperand(2), Simp.getOperand(0),
2640 Simp.getOperand(1), N->getOperand(4));
2644 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2645 LoadSDNode *LD = cast<LoadSDNode>(N);
2646 SDOperand Chain = LD->getChain();
2647 SDOperand Ptr = LD->getBasePtr();
2649 // If there are no uses of the loaded value, change uses of the chain value
2650 // into uses of the chain input (i.e. delete the dead load).
2651 if (N->hasNUsesOfValue(0, 0))
2652 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2654 // If this load is directly stored, replace the load value with the stored
2656 // TODO: Handle store large -> read small portion.
2657 // TODO: Handle TRUNCSTORE/LOADEXT
2658 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2659 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2660 Chain.getOperand(1).getValueType() == N->getValueType(0))
2661 return CombineTo(N, Chain.getOperand(1), Chain);
2665 // Walk up chain skipping non-aliasing memory nodes.
2666 SDOperand BetterChain = FindBetterChain(N, Chain);
2668 // If there is a better chain.
2669 if (Chain != BetterChain) {
2672 // Replace the chain to void dependency.
2673 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2674 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
2675 LD->getSrcValue(), LD->getSrcValueOffset());
2677 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
2678 LD->getValueType(0),
2679 BetterChain, Ptr, LD->getSrcValue(),
2680 LD->getSrcValueOffset(),
2684 // Create token factor to keep old chain connected.
2685 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
2686 Chain, ReplLoad.getValue(1));
2688 // Replace uses with load result and token factor.
2689 return CombineTo(N, ReplLoad.getValue(0), Token);
2696 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2697 SDOperand Chain = N->getOperand(0);
2698 SDOperand Value = N->getOperand(1);
2699 SDOperand Ptr = N->getOperand(2);
2700 SDOperand SrcValue = N->getOperand(3);
2702 // FIXME - Switch over after StoreSDNode comes online.
2703 if (N->getOpcode() == ISD::TRUNCSTORE) {
2705 // Walk up chain skipping non-aliasing memory nodes.
2706 SDOperand BetterChain = FindBetterChain(N, Chain);
2708 // If there is a better chain.
2709 if (Chain != BetterChain) {
2710 // Replace the chain to avoid dependency.
2711 SDOperand ReplTStore = DAG.getStore(BetterChain, Value, Ptr, SrcValue);
2712 // Create token to keep both nodes around.
2713 return DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplTStore);
2720 // If this is a store that kills a previous store, remove the previous store.
2721 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2722 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2723 // Make sure that these stores are the same value type:
2724 // FIXME: we really care that the second store is >= size of the first.
2725 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2726 // Create a new store of Value that replaces both stores.
2727 SDNode *PrevStore = Chain.Val;
2728 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2730 SDOperand NewStore = DAG.getStore(PrevStore->getOperand(0), Value, Ptr,
2732 CombineTo(N, NewStore); // Nuke this store.
2733 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2734 return SDOperand(N, 0);
2737 // If this is a store of a bit convert, store the input value.
2738 // FIXME: This needs to know that the resultant store does not need a
2739 // higher alignment than the original.
2740 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
2741 return DAG.getStore(Chain, Value.getOperand(0), Ptr, SrcValue);
2745 // If the store ptr is a frame index and the frame index has a use of one
2746 // and this is a return block, then the store is redundant.
2747 if (Ptr.hasOneUse() && isa<FrameIndexSDNode>(Ptr) &&
2748 DAG.getRoot().getOpcode() == ISD::RET) {
2752 // Walk up chain skipping non-aliasing memory nodes.
2753 SDOperand BetterChain = FindBetterChain(N, Chain);
2755 // If there is a better chain.
2756 if (Chain != BetterChain) {
2757 // Replace the chain to avoid dependency.
2758 SDOperand ReplStore = DAG.getStore(BetterChain, Value, Ptr, SrcValue);
2759 // Create token to keep both nodes around.
2760 return DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
2767 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
2768 SDOperand InVec = N->getOperand(0);
2769 SDOperand InVal = N->getOperand(1);
2770 SDOperand EltNo = N->getOperand(2);
2772 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
2773 // vector with the inserted element.
2774 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2775 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2776 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2777 if (Elt < Ops.size())
2779 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
2780 &Ops[0], Ops.size());
2786 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
2787 SDOperand InVec = N->getOperand(0);
2788 SDOperand InVal = N->getOperand(1);
2789 SDOperand EltNo = N->getOperand(2);
2790 SDOperand NumElts = N->getOperand(3);
2791 SDOperand EltType = N->getOperand(4);
2793 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
2794 // vector with the inserted element.
2795 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2796 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2797 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2798 if (Elt < Ops.size()-2)
2800 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
2801 &Ops[0], Ops.size());
2807 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
2808 unsigned NumInScalars = N->getNumOperands()-2;
2809 SDOperand NumElts = N->getOperand(NumInScalars);
2810 SDOperand EltType = N->getOperand(NumInScalars+1);
2812 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
2813 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
2814 // two distinct vectors, turn this into a shuffle node.
2815 SDOperand VecIn1, VecIn2;
2816 for (unsigned i = 0; i != NumInScalars; ++i) {
2817 // Ignore undef inputs.
2818 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2820 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
2821 // constant index, bail out.
2822 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
2823 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
2824 VecIn1 = VecIn2 = SDOperand(0, 0);
2828 // If the input vector type disagrees with the result of the vbuild_vector,
2829 // we can't make a shuffle.
2830 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
2831 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
2832 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
2833 VecIn1 = VecIn2 = SDOperand(0, 0);
2837 // Otherwise, remember this. We allow up to two distinct input vectors.
2838 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
2841 if (VecIn1.Val == 0) {
2842 VecIn1 = ExtractedFromVec;
2843 } else if (VecIn2.Val == 0) {
2844 VecIn2 = ExtractedFromVec;
2847 VecIn1 = VecIn2 = SDOperand(0, 0);
2852 // If everything is good, we can make a shuffle operation.
2854 SmallVector<SDOperand, 8> BuildVecIndices;
2855 for (unsigned i = 0; i != NumInScalars; ++i) {
2856 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
2857 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2861 SDOperand Extract = N->getOperand(i);
2863 // If extracting from the first vector, just use the index directly.
2864 if (Extract.getOperand(0) == VecIn1) {
2865 BuildVecIndices.push_back(Extract.getOperand(1));
2869 // Otherwise, use InIdx + VecSize
2870 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
2871 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
2874 // Add count and size info.
2875 BuildVecIndices.push_back(NumElts);
2876 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
2878 // Return the new VVECTOR_SHUFFLE node.
2884 // Use an undef vbuild_vector as input for the second operand.
2885 std::vector<SDOperand> UnOps(NumInScalars,
2886 DAG.getNode(ISD::UNDEF,
2887 cast<VTSDNode>(EltType)->getVT()));
2888 UnOps.push_back(NumElts);
2889 UnOps.push_back(EltType);
2890 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2891 &UnOps[0], UnOps.size());
2892 AddToWorkList(Ops[1].Val);
2894 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2895 &BuildVecIndices[0], BuildVecIndices.size());
2898 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
2904 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
2905 SDOperand ShufMask = N->getOperand(2);
2906 unsigned NumElts = ShufMask.getNumOperands();
2908 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2909 bool isIdentity = true;
2910 for (unsigned i = 0; i != NumElts; ++i) {
2911 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2912 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2917 if (isIdentity) return N->getOperand(0);
2919 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2921 for (unsigned i = 0; i != NumElts; ++i) {
2922 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2923 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2928 if (isIdentity) return N->getOperand(1);
2930 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
2932 bool isUnary = true;
2933 bool isSplat = true;
2935 unsigned BaseIdx = 0;
2936 for (unsigned i = 0; i != NumElts; ++i)
2937 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
2938 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
2939 int V = (Idx < NumElts) ? 0 : 1;
2953 SDOperand N0 = N->getOperand(0);
2954 SDOperand N1 = N->getOperand(1);
2955 // Normalize unary shuffle so the RHS is undef.
2956 if (isUnary && VecNum == 1)
2959 // If it is a splat, check if the argument vector is a build_vector with
2960 // all scalar elements the same.
2963 if (V->getOpcode() == ISD::BIT_CONVERT)
2964 V = V->getOperand(0).Val;
2965 if (V->getOpcode() == ISD::BUILD_VECTOR) {
2966 unsigned NumElems = V->getNumOperands()-2;
2967 if (NumElems > BaseIdx) {
2969 bool AllSame = true;
2970 for (unsigned i = 0; i != NumElems; ++i) {
2971 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
2972 Base = V->getOperand(i);
2976 // Splat of <u, u, u, u>, return <u, u, u, u>
2979 for (unsigned i = 0; i != NumElems; ++i) {
2980 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
2981 V->getOperand(i) != Base) {
2986 // Splat of <x, x, x, x>, return <x, x, x, x>
2993 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
2995 if (isUnary || N0 == N1) {
2996 if (N0.getOpcode() == ISD::UNDEF)
2997 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
2998 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3000 SmallVector<SDOperand, 8> MappedOps;
3001 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
3002 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3003 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3004 MappedOps.push_back(ShufMask.getOperand(i));
3007 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3008 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3011 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
3012 &MappedOps[0], MappedOps.size());
3013 AddToWorkList(ShufMask.Val);
3014 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3016 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3023 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3024 SDOperand ShufMask = N->getOperand(2);
3025 unsigned NumElts = ShufMask.getNumOperands()-2;
3027 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3028 bool isIdentity = true;
3029 for (unsigned i = 0; i != NumElts; ++i) {
3030 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3031 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3036 if (isIdentity) return N->getOperand(0);
3038 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3040 for (unsigned i = 0; i != NumElts; ++i) {
3041 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3042 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3047 if (isIdentity) return N->getOperand(1);
3049 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3051 bool isUnary = true;
3052 bool isSplat = true;
3054 unsigned BaseIdx = 0;
3055 for (unsigned i = 0; i != NumElts; ++i)
3056 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3057 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3058 int V = (Idx < NumElts) ? 0 : 1;
3072 SDOperand N0 = N->getOperand(0);
3073 SDOperand N1 = N->getOperand(1);
3074 // Normalize unary shuffle so the RHS is undef.
3075 if (isUnary && VecNum == 1)
3078 // If it is a splat, check if the argument vector is a build_vector with
3079 // all scalar elements the same.
3082 if (V->getOpcode() == ISD::VBIT_CONVERT)
3083 V = V->getOperand(0).Val;
3084 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3085 unsigned NumElems = V->getNumOperands()-2;
3086 if (NumElems > BaseIdx) {
3088 bool AllSame = true;
3089 for (unsigned i = 0; i != NumElems; ++i) {
3090 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3091 Base = V->getOperand(i);
3095 // Splat of <u, u, u, u>, return <u, u, u, u>
3098 for (unsigned i = 0; i != NumElems; ++i) {
3099 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3100 V->getOperand(i) != Base) {
3105 // Splat of <x, x, x, x>, return <x, x, x, x>
3112 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3114 if (isUnary || N0 == N1) {
3115 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3117 SmallVector<SDOperand, 8> MappedOps;
3118 for (unsigned i = 0; i != NumElts; ++i) {
3119 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3120 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3121 MappedOps.push_back(ShufMask.getOperand(i));
3124 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3125 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3128 // Add the type/#elts values.
3129 MappedOps.push_back(ShufMask.getOperand(NumElts));
3130 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3132 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3133 &MappedOps[0], MappedOps.size());
3134 AddToWorkList(ShufMask.Val);
3136 // Build the undef vector.
3137 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3138 for (unsigned i = 0; i != NumElts; ++i)
3139 MappedOps[i] = UDVal;
3140 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3141 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3142 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3143 &MappedOps[0], MappedOps.size());
3145 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3146 N0, UDVal, ShufMask,
3147 MappedOps[NumElts], MappedOps[NumElts+1]);
3153 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3154 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3155 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3156 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3157 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3158 SDOperand LHS = N->getOperand(0);
3159 SDOperand RHS = N->getOperand(1);
3160 if (N->getOpcode() == ISD::VAND) {
3161 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3162 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3163 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3164 RHS = RHS.getOperand(0);
3165 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3166 std::vector<SDOperand> IdxOps;
3167 unsigned NumOps = RHS.getNumOperands();
3168 unsigned NumElts = NumOps-2;
3169 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3170 for (unsigned i = 0; i != NumElts; ++i) {
3171 SDOperand Elt = RHS.getOperand(i);
3172 if (!isa<ConstantSDNode>(Elt))
3174 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3175 IdxOps.push_back(DAG.getConstant(i, EVT));
3176 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3177 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3182 // Let's see if the target supports this vector_shuffle.
3183 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3186 // Return the new VVECTOR_SHUFFLE node.
3187 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3188 SDOperand EVTNode = DAG.getValueType(EVT);
3189 std::vector<SDOperand> Ops;
3190 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3193 AddToWorkList(LHS.Val);
3194 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3195 ZeroOps.push_back(NumEltsNode);
3196 ZeroOps.push_back(EVTNode);
3197 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3198 &ZeroOps[0], ZeroOps.size()));
3199 IdxOps.push_back(NumEltsNode);
3200 IdxOps.push_back(EVTNode);
3201 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3202 &IdxOps[0], IdxOps.size()));
3203 Ops.push_back(NumEltsNode);
3204 Ops.push_back(EVTNode);
3205 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3206 &Ops[0], Ops.size());
3207 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3208 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3209 DstVecSize, DstVecEVT);
3217 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3218 /// the scalar operation of the vop if it is operating on an integer vector
3219 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3220 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3221 ISD::NodeType FPOp) {
3222 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3223 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3224 SDOperand LHS = N->getOperand(0);
3225 SDOperand RHS = N->getOperand(1);
3226 SDOperand Shuffle = XformToShuffleWithZero(N);
3227 if (Shuffle.Val) return Shuffle;
3229 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3231 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3232 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3233 SmallVector<SDOperand, 8> Ops;
3234 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3235 SDOperand LHSOp = LHS.getOperand(i);
3236 SDOperand RHSOp = RHS.getOperand(i);
3237 // If these two elements can't be folded, bail out.
3238 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3239 LHSOp.getOpcode() != ISD::Constant &&
3240 LHSOp.getOpcode() != ISD::ConstantFP) ||
3241 (RHSOp.getOpcode() != ISD::UNDEF &&
3242 RHSOp.getOpcode() != ISD::Constant &&
3243 RHSOp.getOpcode() != ISD::ConstantFP))
3245 // Can't fold divide by zero.
3246 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3247 if ((RHSOp.getOpcode() == ISD::Constant &&
3248 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3249 (RHSOp.getOpcode() == ISD::ConstantFP &&
3250 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3253 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3254 AddToWorkList(Ops.back().Val);
3255 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3256 Ops.back().getOpcode() == ISD::Constant ||
3257 Ops.back().getOpcode() == ISD::ConstantFP) &&
3258 "Scalar binop didn't fold!");
3261 if (Ops.size() == LHS.getNumOperands()-2) {
3262 Ops.push_back(*(LHS.Val->op_end()-2));
3263 Ops.push_back(*(LHS.Val->op_end()-1));
3264 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3271 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3272 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3274 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3275 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3276 // If we got a simplified select_cc node back from SimplifySelectCC, then
3277 // break it down into a new SETCC node, and a new SELECT node, and then return
3278 // the SELECT node, since we were called with a SELECT node.
3280 // Check to see if we got a select_cc back (to turn into setcc/select).
3281 // Otherwise, just return whatever node we got back, like fabs.
3282 if (SCC.getOpcode() == ISD::SELECT_CC) {
3283 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3284 SCC.getOperand(0), SCC.getOperand(1),
3286 AddToWorkList(SETCC.Val);
3287 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3288 SCC.getOperand(3), SETCC);
3295 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3296 /// are the two values being selected between, see if we can simplify the
3297 /// select. Callers of this should assume that TheSelect is deleted if this
3298 /// returns true. As such, they should return the appropriate thing (e.g. the
3299 /// node) back to the top-level of the DAG combiner loop to avoid it being
3302 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3305 // If this is a select from two identical things, try to pull the operation
3306 // through the select.
3307 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3308 // If this is a load and the token chain is identical, replace the select
3309 // of two loads with a load through a select of the address to load from.
3310 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3311 // constants have been dropped into the constant pool.
3312 if (LHS.getOpcode() == ISD::LOAD &&
3313 // Token chains must be identical.
3314 LHS.getOperand(0) == RHS.getOperand(0)) {
3315 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3316 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3318 // If this is an EXTLOAD, the VT's must match.
3319 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3320 // FIXME: this conflates two src values, discarding one. This is not
3321 // the right thing to do, but nothing uses srcvalues now. When they do,
3322 // turn SrcValue into a list of locations.
3324 if (TheSelect->getOpcode() == ISD::SELECT)
3325 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
3326 TheSelect->getOperand(0), LLD->getBasePtr(),
3329 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
3330 TheSelect->getOperand(0),
3331 TheSelect->getOperand(1),
3332 LLD->getBasePtr(), RLD->getBasePtr(),
3333 TheSelect->getOperand(4));
3336 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
3337 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
3338 Addr,LLD->getSrcValue(), LLD->getSrcValueOffset());
3340 Load = DAG.getExtLoad(LLD->getExtensionType(),
3341 TheSelect->getValueType(0),
3342 LLD->getChain(), Addr, LLD->getSrcValue(),
3343 LLD->getSrcValueOffset(),
3344 LLD->getLoadedVT());
3346 // Users of the select now use the result of the load.
3347 CombineTo(TheSelect, Load);
3349 // Users of the old loads now use the new load's chain. We know the
3350 // old-load value is dead now.
3351 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3352 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3361 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3362 SDOperand N2, SDOperand N3,
3365 MVT::ValueType VT = N2.getValueType();
3366 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3367 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3368 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3370 // Determine if the condition we're dealing with is constant
3371 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3372 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3374 // fold select_cc true, x, y -> x
3375 if (SCCC && SCCC->getValue())
3377 // fold select_cc false, x, y -> y
3378 if (SCCC && SCCC->getValue() == 0)
3381 // Check to see if we can simplify the select into an fabs node
3382 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3383 // Allow either -0.0 or 0.0
3384 if (CFP->getValue() == 0.0) {
3385 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3386 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3387 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3388 N2 == N3.getOperand(0))
3389 return DAG.getNode(ISD::FABS, VT, N0);
3391 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3392 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3393 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3394 N2.getOperand(0) == N3)
3395 return DAG.getNode(ISD::FABS, VT, N3);
3399 // Check to see if we can perform the "gzip trick", transforming
3400 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3401 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3402 MVT::isInteger(N0.getValueType()) &&
3403 MVT::isInteger(N2.getValueType()) &&
3404 (N1C->isNullValue() || // (a < 0) ? b : 0
3405 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3406 MVT::ValueType XType = N0.getValueType();
3407 MVT::ValueType AType = N2.getValueType();
3408 if (XType >= AType) {
3409 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3410 // single-bit constant.
3411 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3412 unsigned ShCtV = Log2_64(N2C->getValue());
3413 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3414 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3415 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3416 AddToWorkList(Shift.Val);
3417 if (XType > AType) {
3418 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3419 AddToWorkList(Shift.Val);
3421 return DAG.getNode(ISD::AND, AType, Shift, N2);
3423 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3424 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3425 TLI.getShiftAmountTy()));
3426 AddToWorkList(Shift.Val);
3427 if (XType > AType) {
3428 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3429 AddToWorkList(Shift.Val);
3431 return DAG.getNode(ISD::AND, AType, Shift, N2);
3435 // fold select C, 16, 0 -> shl C, 4
3436 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3437 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3438 // Get a SetCC of the condition
3439 // FIXME: Should probably make sure that setcc is legal if we ever have a
3440 // target where it isn't.
3441 SDOperand Temp, SCC;
3442 // cast from setcc result type to select result type
3443 if (AfterLegalize) {
3444 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3445 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3447 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3448 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3450 AddToWorkList(SCC.Val);
3451 AddToWorkList(Temp.Val);
3452 // shl setcc result by log2 n2c
3453 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3454 DAG.getConstant(Log2_64(N2C->getValue()),
3455 TLI.getShiftAmountTy()));
3458 // Check to see if this is the equivalent of setcc
3459 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3460 // otherwise, go ahead with the folds.
3461 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3462 MVT::ValueType XType = N0.getValueType();
3463 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3464 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3465 if (Res.getValueType() != VT)
3466 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3470 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3471 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3472 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3473 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3474 return DAG.getNode(ISD::SRL, XType, Ctlz,
3475 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3476 TLI.getShiftAmountTy()));
3478 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3479 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3480 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3482 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3483 DAG.getConstant(~0ULL, XType));
3484 return DAG.getNode(ISD::SRL, XType,
3485 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3486 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3487 TLI.getShiftAmountTy()));
3489 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3490 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3491 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3492 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3493 TLI.getShiftAmountTy()));
3494 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3498 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3499 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3500 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3501 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3502 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3503 MVT::ValueType XType = N0.getValueType();
3504 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3505 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3506 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3507 TLI.getShiftAmountTy()));
3508 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3509 AddToWorkList(Shift.Val);
3510 AddToWorkList(Add.Val);
3511 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3519 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3520 SDOperand N1, ISD::CondCode Cond,
3521 bool foldBooleans) {
3522 // These setcc operations always fold.
3526 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3528 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3531 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3532 uint64_t C1 = N1C->getValue();
3533 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
3534 uint64_t C0 = N0C->getValue();
3536 // Sign extend the operands if required
3537 if (ISD::isSignedIntSetCC(Cond)) {
3538 C0 = N0C->getSignExtended();
3539 C1 = N1C->getSignExtended();
3543 default: assert(0 && "Unknown integer setcc!");
3544 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3545 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3546 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
3547 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
3548 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
3549 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
3550 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
3551 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
3552 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
3553 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
3556 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3557 // equality comparison, then we're just comparing whether X itself is
3559 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
3560 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3561 N0.getOperand(1).getOpcode() == ISD::Constant) {
3562 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
3563 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3564 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
3565 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3566 // (srl (ctlz x), 5) == 0 -> X != 0
3567 // (srl (ctlz x), 5) != 1 -> X != 0
3570 // (srl (ctlz x), 5) != 0 -> X == 0
3571 // (srl (ctlz x), 5) == 1 -> X == 0
3574 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
3575 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
3580 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3581 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3582 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3584 // If the comparison constant has bits in the upper part, the
3585 // zero-extended value could never match.
3586 if (C1 & (~0ULL << InSize)) {
3587 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3591 case ISD::SETEQ: return DAG.getConstant(0, VT);
3594 case ISD::SETNE: return DAG.getConstant(1, VT);
3597 // True if the sign bit of C1 is set.
3598 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3601 // True if the sign bit of C1 isn't set.
3602 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3608 // Otherwise, we can perform the comparison with the low bits.
3616 return DAG.getSetCC(VT, N0.getOperand(0),
3617 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3620 break; // todo, be more careful with signed comparisons
3622 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3623 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3624 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3625 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3626 MVT::ValueType ExtDstTy = N0.getValueType();
3627 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3629 // If the extended part has any inconsistent bits, it cannot ever
3630 // compare equal. In other words, they have to be all ones or all
3633 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3634 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3635 return DAG.getConstant(Cond == ISD::SETNE, VT);
3638 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3639 if (Op0Ty == ExtSrcTy) {
3640 ZextOp = N0.getOperand(0);
3642 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3643 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3644 DAG.getConstant(Imm, Op0Ty));
3646 AddToWorkList(ZextOp.Val);
3647 // Otherwise, make this a use of a zext.
3648 return DAG.getSetCC(VT, ZextOp,
3649 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3652 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3653 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3654 (N0.getOpcode() == ISD::XOR ||
3655 (N0.getOpcode() == ISD::AND &&
3656 N0.getOperand(0).getOpcode() == ISD::XOR &&
3657 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3658 isa<ConstantSDNode>(N0.getOperand(1)) &&
3659 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3660 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
3661 // only do this if the top bits are known zero.
3662 if (TLI.MaskedValueIsZero(N1,
3663 MVT::getIntVTBitMask(N0.getValueType())-1)) {
3664 // Okay, get the un-inverted input value.
3666 if (N0.getOpcode() == ISD::XOR)
3667 Val = N0.getOperand(0);
3669 assert(N0.getOpcode() == ISD::AND &&
3670 N0.getOperand(0).getOpcode() == ISD::XOR);
3671 // ((X^1)&1)^1 -> X & 1
3672 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3673 N0.getOperand(0).getOperand(0), N0.getOperand(1));
3675 return DAG.getSetCC(VT, Val, N1,
3676 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3680 uint64_t MinVal, MaxVal;
3681 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3682 if (ISD::isSignedIntSetCC(Cond)) {
3683 MinVal = 1ULL << (OperandBitSize-1);
3684 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3685 MaxVal = ~0ULL >> (65-OperandBitSize);
3690 MaxVal = ~0ULL >> (64-OperandBitSize);
3693 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3694 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3695 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
3696 --C1; // X >= C0 --> X > (C0-1)
3697 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3698 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
3701 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3702 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
3703 ++C1; // X <= C0 --> X < (C0+1)
3704 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3705 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
3708 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
3709 return DAG.getConstant(0, VT); // X < MIN --> false
3711 // Canonicalize setgt X, Min --> setne X, Min
3712 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
3713 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3714 // Canonicalize setlt X, Max --> setne X, Max
3715 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
3716 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3718 // If we have setult X, 1, turn it into seteq X, 0
3719 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
3720 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
3722 // If we have setugt X, Max-1, turn it into seteq X, Max
3723 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
3724 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
3727 // If we have "setcc X, C0", check to see if we can shrink the immediate
3730 // SETUGT X, SINTMAX -> SETLT X, 0
3731 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
3732 C1 == (~0ULL >> (65-OperandBitSize)))
3733 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
3736 // FIXME: Implement the rest of these.
3738 // Fold bit comparisons when we can.
3739 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3740 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
3741 if (ConstantSDNode *AndRHS =
3742 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3743 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3744 // Perform the xform if the AND RHS is a single bit.
3745 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
3746 return DAG.getNode(ISD::SRL, VT, N0,
3747 DAG.getConstant(Log2_64(AndRHS->getValue()),
3748 TLI.getShiftAmountTy()));
3750 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
3751 // (X & 8) == 8 --> (X & 8) >> 3
3752 // Perform the xform if C1 is a single bit.
3753 if ((C1 & (C1-1)) == 0) {
3754 return DAG.getNode(ISD::SRL, VT, N0,
3755 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
3760 } else if (isa<ConstantSDNode>(N0.Val)) {
3761 // Ensure that the constant occurs on the RHS.
3762 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3765 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
3766 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
3767 double C0 = N0C->getValue(), C1 = N1C->getValue();
3770 default: break; // FIXME: Implement the rest of these!
3771 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3772 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3773 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
3774 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
3775 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
3776 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
3779 // Ensure that the constant occurs on the RHS.
3780 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3784 // We can always fold X == Y for integer setcc's.
3785 if (MVT::isInteger(N0.getValueType()))
3786 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3787 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3788 if (UOF == 2) // FP operators that are undefined on NaNs.
3789 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3790 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
3791 return DAG.getConstant(UOF, VT);
3792 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3793 // if it is not already.
3794 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3795 if (NewCond != Cond)
3796 return DAG.getSetCC(VT, N0, N1, NewCond);
3799 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3800 MVT::isInteger(N0.getValueType())) {
3801 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3802 N0.getOpcode() == ISD::XOR) {
3803 // Simplify (X+Y) == (X+Z) --> Y == Z
3804 if (N0.getOpcode() == N1.getOpcode()) {
3805 if (N0.getOperand(0) == N1.getOperand(0))
3806 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
3807 if (N0.getOperand(1) == N1.getOperand(1))
3808 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
3809 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
3810 // If X op Y == Y op X, try other combinations.
3811 if (N0.getOperand(0) == N1.getOperand(1))
3812 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
3813 if (N0.getOperand(1) == N1.getOperand(0))
3814 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
3818 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3819 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3820 // Turn (X+C1) == C2 --> X == C2-C1
3821 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
3822 return DAG.getSetCC(VT, N0.getOperand(0),
3823 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
3824 N0.getValueType()), Cond);
3827 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3828 if (N0.getOpcode() == ISD::XOR)
3829 // If we know that all of the inverted bits are zero, don't bother
3830 // performing the inversion.
3831 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
3832 return DAG.getSetCC(VT, N0.getOperand(0),
3833 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
3834 N0.getValueType()), Cond);
3837 // Turn (C1-X) == C2 --> X == C1-C2
3838 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3839 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
3840 return DAG.getSetCC(VT, N0.getOperand(1),
3841 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
3842 N0.getValueType()), Cond);
3847 // Simplify (X+Z) == X --> Z == 0
3848 if (N0.getOperand(0) == N1)
3849 return DAG.getSetCC(VT, N0.getOperand(1),
3850 DAG.getConstant(0, N0.getValueType()), Cond);
3851 if (N0.getOperand(1) == N1) {
3852 if (DAG.isCommutativeBinOp(N0.getOpcode()))
3853 return DAG.getSetCC(VT, N0.getOperand(0),
3854 DAG.getConstant(0, N0.getValueType()), Cond);
3856 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
3857 // (Z-X) == X --> Z == X<<1
3858 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
3860 DAG.getConstant(1,TLI.getShiftAmountTy()));
3861 AddToWorkList(SH.Val);
3862 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
3867 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3868 N1.getOpcode() == ISD::XOR) {
3869 // Simplify X == (X+Z) --> Z == 0
3870 if (N1.getOperand(0) == N0) {
3871 return DAG.getSetCC(VT, N1.getOperand(1),
3872 DAG.getConstant(0, N1.getValueType()), Cond);
3873 } else if (N1.getOperand(1) == N0) {
3874 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
3875 return DAG.getSetCC(VT, N1.getOperand(0),
3876 DAG.getConstant(0, N1.getValueType()), Cond);
3878 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
3879 // X == (Z-X) --> X<<1 == Z
3880 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
3881 DAG.getConstant(1,TLI.getShiftAmountTy()));
3882 AddToWorkList(SH.Val);
3883 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
3889 // Fold away ALL boolean setcc's.
3891 if (N0.getValueType() == MVT::i1 && foldBooleans) {
3893 default: assert(0 && "Unknown integer setcc!");
3894 case ISD::SETEQ: // X == Y -> (X^Y)^1
3895 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3896 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
3897 AddToWorkList(Temp.Val);
3899 case ISD::SETNE: // X != Y --> (X^Y)
3900 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3902 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
3903 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
3904 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3905 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
3906 AddToWorkList(Temp.Val);
3908 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
3909 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
3910 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3911 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
3912 AddToWorkList(Temp.Val);
3914 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
3915 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
3916 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3917 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
3918 AddToWorkList(Temp.Val);
3920 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
3921 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
3922 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3923 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
3926 if (VT != MVT::i1) {
3927 AddToWorkList(N0.Val);
3928 // FIXME: If running after legalize, we probably can't do this.
3929 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
3934 // Could not fold it.
3938 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3939 /// return a DAG expression to select that will generate the same value by
3940 /// multiplying by a magic number. See:
3941 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3942 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
3943 std::vector<SDNode*> Built;
3944 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
3946 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3952 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3953 /// return a DAG expression to select that will generate the same value by
3954 /// multiplying by a magic number. See:
3955 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3956 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
3957 std::vector<SDNode*> Built;
3958 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
3960 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3966 /// FindBaseOffset - Return true if base is known not to alias with anything
3967 /// but itself. Provides base object and offset as results.
3968 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
3969 // Assume it is a primitive operation.
3970 Base = Ptr; Offset = 0;
3972 // If it's an adding a simple constant then integrate the offset.
3973 if (Base.getOpcode() == ISD::ADD) {
3974 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
3975 Base = Base.getOperand(0);
3976 Offset += C->getValue();
3980 // If it's any of the following then it can't alias with anything but itself.
3981 return isa<FrameIndexSDNode>(Base) ||
3982 isa<ConstantPoolSDNode>(Base) ||
3983 isa<GlobalAddressSDNode>(Base);
3986 /// isAlias - Return true if there is any possibility that the two addresses
3988 static bool isAlias(SDOperand Ptr1, int64_t Size1, const Value *SrcValue1,
3989 SDOperand Ptr2, int64_t Size2, const Value *SrcValue2) {
3990 // If they are the same then they must be aliases.
3991 if (Ptr1 == Ptr2) return true;
3993 // Gather base node and offset information.
3994 SDOperand Base1, Base2;
3995 int64_t Offset1, Offset2;
3996 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
3997 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
3999 // If they have a same base address then...
4000 if (Base1 == Base2) {
4001 // Check to see if the addresses overlap.
4002 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4005 // Otherwise they alias if either is unknown.
4006 return !KnownBase1 || !KnownBase2;
4009 /// FindAliasInfo - Extracts the relevant alias information from the memory
4010 /// node. Returns true if the operand was a load.
4011 bool DAGCombiner::FindAliasInfo(SDNode *N,
4012 SDOperand &Ptr, int64_t &Size, const Value *&SrcValue) {
4013 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4014 Ptr = LD->getBasePtr();
4015 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4016 SrcValue = LD->getSrcValue();
4018 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4019 #if 1 // FIXME - Switch over after StoreSDNode comes online.
4020 Ptr = ST->getOperand(2);
4021 Size = MVT::getSizeInBits(ST->getOperand(1).getValueType()) >> 3;
4024 Ptr = ST->getBasePtr();
4025 Size = MVT::getSizeInBits(ST->getOperand(1).getValueType()) >> 3;
4026 SrcValue = ST->getSrcValue();
4028 // FIXME - Switch over after StoreSDNode comes online.
4029 } else if (N->getOpcode() == ISD::TRUNCSTORE) {
4030 Ptr = N->getOperand(2);
4031 Size = MVT::getSizeInBits(cast<VTSDNode>(N->getOperand(4))->getVT()) >> 3;
4034 assert(0 && "FindAliasInfo expected a memory operand");
4040 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4041 /// looking for aliasing nodes and adding them to the Aliases vector.
4042 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4043 SmallVector<SDOperand, 8> &Aliases) {
4044 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4045 std::set<SDNode *> Visited; // Visited node set.
4047 // Get alias information for node.
4050 const Value *SrcValue;
4051 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue);
4054 Chains.push_back(OriginalChain);
4056 // Look at each chain and determine if it is an alias. If so, add it to the
4057 // aliases list. If not, then continue up the chain looking for the next
4059 while (!Chains.empty()) {
4060 SDOperand Chain = Chains.back();
4063 // Don't bother if we've been before.
4064 if (Visited.find(Chain.Val) != Visited.end()) continue;
4065 Visited.insert(Chain.Val);
4067 switch (Chain.getOpcode()) {
4068 case ISD::EntryToken:
4069 // Entry token is ideal chain operand, but handled in FindBetterChain.
4073 // FIXME - Switch over after StoreSDNode comes online.
4074 case ISD::TRUNCSTORE:
4076 // Get alias information for Chain.
4079 const Value *OpSrcValue;
4080 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, OpSrcValue);
4082 // If chain is alias then stop here.
4083 if (!(IsLoad && IsOpLoad) &&
4084 isAlias(Ptr, Size, SrcValue, OpPtr, OpSize, OpSrcValue)) {
4085 Aliases.push_back(Chain);
4087 // Look further up the chain.
4088 Chains.push_back(Chain.getOperand(0));
4089 // Clean up old chain.
4090 AddToWorkList(Chain.Val);
4095 case ISD::TokenFactor:
4096 // We have to check each of the operands of the token factor, so we queue
4097 // then up. Adding the operands to the queue (stack) in reverse order
4098 // maintains the original order and increases the likelihood that getNode
4099 // will find a matching token factor (CSE.)
4100 for (unsigned n = Chain.getNumOperands(); n;)
4101 Chains.push_back(Chain.getOperand(--n));
4102 // Eliminate the token factor if we can.
4103 AddToWorkList(Chain.Val);
4107 // For all other instructions we will just have to take what we can get.
4108 Aliases.push_back(Chain);
4114 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4115 /// for a better chain (aliasing node.)
4116 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4117 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4119 // Accumulate all the aliases to this node.
4120 GatherAllAliases(N, OldChain, Aliases);
4122 if (Aliases.size() == 0) {
4123 // If no operands then chain to entry token.
4124 return DAG.getEntryNode();
4125 } else if (Aliases.size() == 1) {
4126 // If a single operand then chain to it. We don't need to revisit it.
4130 // Construct a custom tailored token factor.
4131 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4132 &Aliases[0], Aliases.size());
4134 // Make sure the old chain gets cleaned up.
4135 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4140 // SelectionDAG::Combine - This is the entry point for the file.
4142 void SelectionDAG::Combine(bool RunningAfterLegalize) {
4143 /// run - This is the main entry point to this class.
4145 DAGCombiner(*this).Run(RunningAfterLegalize);