1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/CommandLine.h"
46 static Statistic<> NodesCombined ("dagcombiner",
47 "Number of dag nodes combined");
50 CombinerAA("combiner-alias-analysis", cl::Hidden,
51 cl::desc("Turn on alias analysis turning testing"));
53 //------------------------------ DAGCombiner ---------------------------------//
55 class VISIBILITY_HIDDEN DAGCombiner {
60 // Worklist of all of the nodes that need to be simplified.
61 std::vector<SDNode*> WorkList;
63 /// AddUsersToWorkList - When an instruction is simplified, add all users of
64 /// the instruction to the work lists because they might get more simplified
67 void AddUsersToWorkList(SDNode *N) {
68 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
73 /// removeFromWorkList - remove all instances of N from the worklist.
75 void removeFromWorkList(SDNode *N) {
76 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
81 /// AddToWorkList - Add to the work list making sure it's instance is at the
82 /// the back (next to be processed.)
83 void AddToWorkList(SDNode *N) {
84 removeFromWorkList(N);
85 WorkList.push_back(N);
88 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo) {
89 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
91 DEBUG(std::cerr << "\nReplacing.1 "; N->dump();
92 std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
93 std::cerr << " and " << NumTo-1 << " other values\n");
94 std::vector<SDNode*> NowDead;
95 DAG.ReplaceAllUsesWith(N, To, &NowDead);
97 // Push the new nodes and any users onto the worklist
98 for (unsigned i = 0, e = NumTo; i != e; ++i) {
99 AddToWorkList(To[i].Val);
100 AddUsersToWorkList(To[i].Val);
103 // Nodes can be reintroduced into the worklist. Make sure we do not
104 // process a node that has been replaced.
105 removeFromWorkList(N);
106 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
107 removeFromWorkList(NowDead[i]);
109 // Finally, since the node is now dead, remove it from the graph.
111 return SDOperand(N, 0);
114 SDOperand CombineTo(SDNode *N, SDOperand Res) {
115 return CombineTo(N, &Res, 1);
118 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
119 SDOperand To[] = { Res0, Res1 };
120 return CombineTo(N, To, 2);
124 /// SimplifyDemandedBits - Check the specified integer node value to see if
125 /// it can be simplified or if things it uses can be simplified by bit
126 /// propagation. If so, return true.
127 bool SimplifyDemandedBits(SDOperand Op) {
128 TargetLowering::TargetLoweringOpt TLO(DAG);
129 uint64_t KnownZero, KnownOne;
130 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
131 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
135 AddToWorkList(Op.Val);
137 // Replace the old value with the new one.
139 DEBUG(std::cerr << "\nReplacing.2 "; TLO.Old.Val->dump();
140 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG);
143 std::vector<SDNode*> NowDead;
144 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
146 // Push the new node and any (possibly new) users onto the worklist.
147 AddToWorkList(TLO.New.Val);
148 AddUsersToWorkList(TLO.New.Val);
150 // Nodes can end up on the worklist more than once. Make sure we do
151 // not process a node that has been replaced.
152 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
153 removeFromWorkList(NowDead[i]);
155 // Finally, if the node is now dead, remove it from the graph. The node
156 // may not be dead if the replacement process recursively simplified to
157 // something else needing this node.
158 if (TLO.Old.Val->use_empty()) {
159 removeFromWorkList(TLO.Old.Val);
160 DAG.DeleteNode(TLO.Old.Val);
165 /// visit - call the node-specific routine that knows how to fold each
166 /// particular type of node.
167 SDOperand visit(SDNode *N);
169 // Visitation implementation - Implement dag node combining for different
170 // node types. The semantics are as follows:
172 // SDOperand.Val == 0 - No change was made
173 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
174 // otherwise - N should be replaced by the returned Operand.
176 SDOperand visitTokenFactor(SDNode *N);
177 SDOperand visitADD(SDNode *N);
178 SDOperand visitSUB(SDNode *N);
179 SDOperand visitMUL(SDNode *N);
180 SDOperand visitSDIV(SDNode *N);
181 SDOperand visitUDIV(SDNode *N);
182 SDOperand visitSREM(SDNode *N);
183 SDOperand visitUREM(SDNode *N);
184 SDOperand visitMULHU(SDNode *N);
185 SDOperand visitMULHS(SDNode *N);
186 SDOperand visitAND(SDNode *N);
187 SDOperand visitOR(SDNode *N);
188 SDOperand visitXOR(SDNode *N);
189 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
190 SDOperand visitSHL(SDNode *N);
191 SDOperand visitSRA(SDNode *N);
192 SDOperand visitSRL(SDNode *N);
193 SDOperand visitCTLZ(SDNode *N);
194 SDOperand visitCTTZ(SDNode *N);
195 SDOperand visitCTPOP(SDNode *N);
196 SDOperand visitSELECT(SDNode *N);
197 SDOperand visitSELECT_CC(SDNode *N);
198 SDOperand visitSETCC(SDNode *N);
199 SDOperand visitSIGN_EXTEND(SDNode *N);
200 SDOperand visitZERO_EXTEND(SDNode *N);
201 SDOperand visitANY_EXTEND(SDNode *N);
202 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
203 SDOperand visitTRUNCATE(SDNode *N);
204 SDOperand visitBIT_CONVERT(SDNode *N);
205 SDOperand visitVBIT_CONVERT(SDNode *N);
206 SDOperand visitFADD(SDNode *N);
207 SDOperand visitFSUB(SDNode *N);
208 SDOperand visitFMUL(SDNode *N);
209 SDOperand visitFDIV(SDNode *N);
210 SDOperand visitFREM(SDNode *N);
211 SDOperand visitFCOPYSIGN(SDNode *N);
212 SDOperand visitSINT_TO_FP(SDNode *N);
213 SDOperand visitUINT_TO_FP(SDNode *N);
214 SDOperand visitFP_TO_SINT(SDNode *N);
215 SDOperand visitFP_TO_UINT(SDNode *N);
216 SDOperand visitFP_ROUND(SDNode *N);
217 SDOperand visitFP_ROUND_INREG(SDNode *N);
218 SDOperand visitFP_EXTEND(SDNode *N);
219 SDOperand visitFNEG(SDNode *N);
220 SDOperand visitFABS(SDNode *N);
221 SDOperand visitBRCOND(SDNode *N);
222 SDOperand visitBR_CC(SDNode *N);
223 SDOperand visitLOAD(SDNode *N);
224 SDOperand visitSTORE(SDNode *N);
225 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
226 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
227 SDOperand visitVBUILD_VECTOR(SDNode *N);
228 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
229 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
231 SDOperand XformToShuffleWithZero(SDNode *N);
232 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
234 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
235 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
236 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
237 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
238 SDOperand N3, ISD::CondCode CC);
239 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
240 ISD::CondCode Cond, bool foldBooleans = true);
241 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
242 SDOperand BuildSDIV(SDNode *N);
243 SDOperand BuildUDIV(SDNode *N);
244 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
246 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
247 /// looking for aliasing nodes and adding them to the Aliases vector.
248 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
249 SmallVector<SDOperand, 8> &Aliases);
251 /// FindAliasInfo - Extracts the relevant alias information from the memory
252 /// node. Returns true if the operand was a load.
253 bool FindAliasInfo(SDNode *N,
254 SDOperand &Ptr, int64_t &Size, const Value *&SrcValue);
256 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
257 /// looking for a better chain (aliasing node.)
258 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
261 DAGCombiner(SelectionDAG &D)
262 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
264 /// Run - runs the dag combiner on all nodes in the work list
265 void Run(bool RunningAfterLegalize);
269 //===----------------------------------------------------------------------===//
270 // TargetLowering::DAGCombinerInfo implementation
271 //===----------------------------------------------------------------------===//
273 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
274 ((DAGCombiner*)DC)->AddToWorkList(N);
277 SDOperand TargetLowering::DAGCombinerInfo::
278 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
279 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
282 SDOperand TargetLowering::DAGCombinerInfo::
283 CombineTo(SDNode *N, SDOperand Res) {
284 return ((DAGCombiner*)DC)->CombineTo(N, Res);
288 SDOperand TargetLowering::DAGCombinerInfo::
289 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
290 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
296 //===----------------------------------------------------------------------===//
299 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
300 // that selects between the values 1 and 0, making it equivalent to a setcc.
301 // Also, set the incoming LHS, RHS, and CC references to the appropriate
302 // nodes based on the type of node we are checking. This simplifies life a
303 // bit for the callers.
304 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
306 if (N.getOpcode() == ISD::SETCC) {
307 LHS = N.getOperand(0);
308 RHS = N.getOperand(1);
309 CC = N.getOperand(2);
312 if (N.getOpcode() == ISD::SELECT_CC &&
313 N.getOperand(2).getOpcode() == ISD::Constant &&
314 N.getOperand(3).getOpcode() == ISD::Constant &&
315 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
316 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
317 LHS = N.getOperand(0);
318 RHS = N.getOperand(1);
319 CC = N.getOperand(4);
325 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
326 // one use. If this is true, it allows the users to invert the operation for
327 // free when it is profitable to do so.
328 static bool isOneUseSetCC(SDOperand N) {
329 SDOperand N0, N1, N2;
330 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
335 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
336 MVT::ValueType VT = N0.getValueType();
337 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
338 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
339 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
340 if (isa<ConstantSDNode>(N1)) {
341 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
342 AddToWorkList(OpNode.Val);
343 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
344 } else if (N0.hasOneUse()) {
345 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
346 AddToWorkList(OpNode.Val);
347 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
350 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
351 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
352 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
353 if (isa<ConstantSDNode>(N0)) {
354 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
355 AddToWorkList(OpNode.Val);
356 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
357 } else if (N1.hasOneUse()) {
358 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
359 AddToWorkList(OpNode.Val);
360 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
366 void DAGCombiner::Run(bool RunningAfterLegalize) {
367 // set the instance variable, so that the various visit routines may use it.
368 AfterLegalize = RunningAfterLegalize;
370 // Add all the dag nodes to the worklist.
371 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
372 E = DAG.allnodes_end(); I != E; ++I)
373 WorkList.push_back(I);
375 // Create a dummy node (which is not added to allnodes), that adds a reference
376 // to the root node, preventing it from being deleted, and tracking any
377 // changes of the root.
378 HandleSDNode Dummy(DAG.getRoot());
381 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
382 TargetLowering::DAGCombinerInfo
383 DagCombineInfo(DAG, !RunningAfterLegalize, this);
385 // while the worklist isn't empty, inspect the node on the end of it and
386 // try and combine it.
387 while (!WorkList.empty()) {
388 SDNode *N = WorkList.back();
391 // If N has no uses, it is dead. Make sure to revisit all N's operands once
392 // N is deleted from the DAG, since they too may now be dead or may have a
393 // reduced number of uses, allowing other xforms.
394 if (N->use_empty() && N != &Dummy) {
395 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
396 AddToWorkList(N->getOperand(i).Val);
402 SDOperand RV = visit(N);
404 // If nothing happened, try a target-specific DAG combine.
406 assert(N->getOpcode() != ISD::DELETED_NODE &&
407 "Node was deleted but visit returned NULL!");
408 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
409 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
410 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
415 // If we get back the same node we passed in, rather than a new node or
416 // zero, we know that the node must have defined multiple values and
417 // CombineTo was used. Since CombineTo takes care of the worklist
418 // mechanics for us, we have no work to do in this case.
420 assert(N->getOpcode() != ISD::DELETED_NODE &&
421 RV.Val->getOpcode() != ISD::DELETED_NODE &&
422 "Node was deleted but visit returned new node!");
424 DEBUG(std::cerr << "\nReplacing.3 "; N->dump();
425 std::cerr << "\nWith: "; RV.Val->dump(&DAG);
427 std::vector<SDNode*> NowDead;
428 if (N->getNumValues() == RV.Val->getNumValues())
429 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
431 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
433 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
436 // Push the new node and any users onto the worklist
437 AddToWorkList(RV.Val);
438 AddUsersToWorkList(RV.Val);
440 // Nodes can be reintroduced into the worklist. Make sure we do not
441 // process a node that has been replaced.
442 removeFromWorkList(N);
443 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
444 removeFromWorkList(NowDead[i]);
446 // Finally, since the node is now dead, remove it from the graph.
452 // If the root changed (e.g. it was a dead load, update the root).
453 DAG.setRoot(Dummy.getValue());
456 SDOperand DAGCombiner::visit(SDNode *N) {
457 switch(N->getOpcode()) {
459 case ISD::TokenFactor: return visitTokenFactor(N);
460 case ISD::ADD: return visitADD(N);
461 case ISD::SUB: return visitSUB(N);
462 case ISD::MUL: return visitMUL(N);
463 case ISD::SDIV: return visitSDIV(N);
464 case ISD::UDIV: return visitUDIV(N);
465 case ISD::SREM: return visitSREM(N);
466 case ISD::UREM: return visitUREM(N);
467 case ISD::MULHU: return visitMULHU(N);
468 case ISD::MULHS: return visitMULHS(N);
469 case ISD::AND: return visitAND(N);
470 case ISD::OR: return visitOR(N);
471 case ISD::XOR: return visitXOR(N);
472 case ISD::SHL: return visitSHL(N);
473 case ISD::SRA: return visitSRA(N);
474 case ISD::SRL: return visitSRL(N);
475 case ISD::CTLZ: return visitCTLZ(N);
476 case ISD::CTTZ: return visitCTTZ(N);
477 case ISD::CTPOP: return visitCTPOP(N);
478 case ISD::SELECT: return visitSELECT(N);
479 case ISD::SELECT_CC: return visitSELECT_CC(N);
480 case ISD::SETCC: return visitSETCC(N);
481 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
482 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
483 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
484 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
485 case ISD::TRUNCATE: return visitTRUNCATE(N);
486 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
487 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
488 case ISD::FADD: return visitFADD(N);
489 case ISD::FSUB: return visitFSUB(N);
490 case ISD::FMUL: return visitFMUL(N);
491 case ISD::FDIV: return visitFDIV(N);
492 case ISD::FREM: return visitFREM(N);
493 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
494 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
495 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
496 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
497 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
498 case ISD::FP_ROUND: return visitFP_ROUND(N);
499 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
500 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
501 case ISD::FNEG: return visitFNEG(N);
502 case ISD::FABS: return visitFABS(N);
503 case ISD::BRCOND: return visitBRCOND(N);
504 case ISD::BR_CC: return visitBR_CC(N);
505 case ISD::LOAD: return visitLOAD(N);
506 case ISD::STORE: return visitSTORE(N);
507 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
508 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
509 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
510 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
511 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
512 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
513 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
514 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
515 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
516 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
517 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
518 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
519 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
524 /// getInputChainForNode - Given a node, return its input chain if it has one,
525 /// otherwise return a null sd operand.
526 static SDOperand getInputChainForNode(SDNode *N) {
527 if (unsigned NumOps = N->getNumOperands()) {
528 if (N->getOperand(0).getValueType() == MVT::Other)
529 return N->getOperand(0);
530 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
531 return N->getOperand(NumOps-1);
532 for (unsigned i = 1; i < NumOps-1; ++i)
533 if (N->getOperand(i).getValueType() == MVT::Other)
534 return N->getOperand(i);
536 return SDOperand(0, 0);
539 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
540 // If N has two operands, where one has an input chain equal to the other,
541 // the 'other' chain is redundant.
542 if (N->getNumOperands() == 2) {
543 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
544 return N->getOperand(0);
545 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
546 return N->getOperand(1);
550 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
551 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
552 bool Changed = false; // If we should replace this token factor.
554 // Start out with this token factor.
557 // Iterate through token factors. The TFs grows when new token factors are
559 for (unsigned i = 0; i < TFs.size(); ++i) {
562 // Check each of the operands.
563 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
564 SDOperand Op = TF->getOperand(i);
566 switch (Op.getOpcode()) {
567 case ISD::EntryToken:
568 // Entry tokens don't need to be added to the list. They are
573 case ISD::TokenFactor:
574 if ((CombinerAA || Op.hasOneUse()) &&
575 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
576 // Queue up for processing.
577 TFs.push_back(Op.Val);
578 // Clean up in case the token factor is removed.
579 AddToWorkList(Op.Val);
586 // Only add if not there prior.
587 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
596 // If we've change things around then replace token factor.
598 if (Ops.size() == 0) {
599 // The entry token is the only possible outcome.
600 Result = DAG.getEntryNode();
602 // New and improved token factor.
603 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
610 SDOperand DAGCombiner::visitADD(SDNode *N) {
611 SDOperand N0 = N->getOperand(0);
612 SDOperand N1 = N->getOperand(1);
613 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
614 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
615 MVT::ValueType VT = N0.getValueType();
617 // fold (add c1, c2) -> c1+c2
619 return DAG.getNode(ISD::ADD, VT, N0, N1);
620 // canonicalize constant to RHS
622 return DAG.getNode(ISD::ADD, VT, N1, N0);
623 // fold (add x, 0) -> x
624 if (N1C && N1C->isNullValue())
626 // fold ((c1-A)+c2) -> (c1+c2)-A
627 if (N1C && N0.getOpcode() == ISD::SUB)
628 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
629 return DAG.getNode(ISD::SUB, VT,
630 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
633 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
636 // fold ((0-A) + B) -> B-A
637 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
638 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
639 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
640 // fold (A + (0-B)) -> A-B
641 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
642 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
643 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
644 // fold (A+(B-A)) -> B
645 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
646 return N1.getOperand(0);
648 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
649 return SDOperand(N, 0);
651 // fold (a+b) -> (a|b) iff a and b share no bits.
652 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
653 uint64_t LHSZero, LHSOne;
654 uint64_t RHSZero, RHSOne;
655 uint64_t Mask = MVT::getIntVTBitMask(VT);
656 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
658 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
660 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
661 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
662 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
663 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
664 return DAG.getNode(ISD::OR, VT, N0, N1);
671 SDOperand DAGCombiner::visitSUB(SDNode *N) {
672 SDOperand N0 = N->getOperand(0);
673 SDOperand N1 = N->getOperand(1);
674 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
675 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
676 MVT::ValueType VT = N0.getValueType();
678 // fold (sub x, x) -> 0
680 return DAG.getConstant(0, N->getValueType(0));
681 // fold (sub c1, c2) -> c1-c2
683 return DAG.getNode(ISD::SUB, VT, N0, N1);
684 // fold (sub x, c) -> (add x, -c)
686 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
688 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
689 return N0.getOperand(1);
691 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
692 return N0.getOperand(0);
696 SDOperand DAGCombiner::visitMUL(SDNode *N) {
697 SDOperand N0 = N->getOperand(0);
698 SDOperand N1 = N->getOperand(1);
699 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
700 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
701 MVT::ValueType VT = N0.getValueType();
703 // fold (mul c1, c2) -> c1*c2
705 return DAG.getNode(ISD::MUL, VT, N0, N1);
706 // canonicalize constant to RHS
708 return DAG.getNode(ISD::MUL, VT, N1, N0);
709 // fold (mul x, 0) -> 0
710 if (N1C && N1C->isNullValue())
712 // fold (mul x, -1) -> 0-x
713 if (N1C && N1C->isAllOnesValue())
714 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
715 // fold (mul x, (1 << c)) -> x << c
716 if (N1C && isPowerOf2_64(N1C->getValue()))
717 return DAG.getNode(ISD::SHL, VT, N0,
718 DAG.getConstant(Log2_64(N1C->getValue()),
719 TLI.getShiftAmountTy()));
720 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
721 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
722 // FIXME: If the input is something that is easily negated (e.g. a
723 // single-use add), we should put the negate there.
724 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
725 DAG.getNode(ISD::SHL, VT, N0,
726 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
727 TLI.getShiftAmountTy())));
730 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
731 if (N1C && N0.getOpcode() == ISD::SHL &&
732 isa<ConstantSDNode>(N0.getOperand(1))) {
733 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
734 AddToWorkList(C3.Val);
735 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
738 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
741 SDOperand Sh(0,0), Y(0,0);
742 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
743 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
744 N0.Val->hasOneUse()) {
746 } else if (N1.getOpcode() == ISD::SHL &&
747 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
751 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
752 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
755 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
756 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
757 isa<ConstantSDNode>(N0.getOperand(1))) {
758 return DAG.getNode(ISD::ADD, VT,
759 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
760 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
764 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
770 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
771 SDOperand N0 = N->getOperand(0);
772 SDOperand N1 = N->getOperand(1);
773 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
774 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
775 MVT::ValueType VT = N->getValueType(0);
777 // fold (sdiv c1, c2) -> c1/c2
778 if (N0C && N1C && !N1C->isNullValue())
779 return DAG.getNode(ISD::SDIV, VT, N0, N1);
780 // fold (sdiv X, 1) -> X
781 if (N1C && N1C->getSignExtended() == 1LL)
783 // fold (sdiv X, -1) -> 0-X
784 if (N1C && N1C->isAllOnesValue())
785 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
786 // If we know the sign bits of both operands are zero, strength reduce to a
787 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
788 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
789 if (TLI.MaskedValueIsZero(N1, SignBit) &&
790 TLI.MaskedValueIsZero(N0, SignBit))
791 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
792 // fold (sdiv X, pow2) -> simple ops after legalize
793 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
794 (isPowerOf2_64(N1C->getSignExtended()) ||
795 isPowerOf2_64(-N1C->getSignExtended()))) {
796 // If dividing by powers of two is cheap, then don't perform the following
798 if (TLI.isPow2DivCheap())
800 int64_t pow2 = N1C->getSignExtended();
801 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
802 unsigned lg2 = Log2_64(abs2);
803 // Splat the sign bit into the register
804 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
805 DAG.getConstant(MVT::getSizeInBits(VT)-1,
806 TLI.getShiftAmountTy()));
807 AddToWorkList(SGN.Val);
808 // Add (N0 < 0) ? abs2 - 1 : 0;
809 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
810 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
811 TLI.getShiftAmountTy()));
812 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
813 AddToWorkList(SRL.Val);
814 AddToWorkList(ADD.Val); // Divide by pow2
815 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
816 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
817 // If we're dividing by a positive value, we're done. Otherwise, we must
818 // negate the result.
821 AddToWorkList(SRA.Val);
822 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
824 // if integer divide is expensive and we satisfy the requirements, emit an
825 // alternate sequence.
826 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
827 !TLI.isIntDivCheap()) {
828 SDOperand Op = BuildSDIV(N);
829 if (Op.Val) return Op;
834 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
835 SDOperand N0 = N->getOperand(0);
836 SDOperand N1 = N->getOperand(1);
837 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
838 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
839 MVT::ValueType VT = N->getValueType(0);
841 // fold (udiv c1, c2) -> c1/c2
842 if (N0C && N1C && !N1C->isNullValue())
843 return DAG.getNode(ISD::UDIV, VT, N0, N1);
844 // fold (udiv x, (1 << c)) -> x >>u c
845 if (N1C && isPowerOf2_64(N1C->getValue()))
846 return DAG.getNode(ISD::SRL, VT, N0,
847 DAG.getConstant(Log2_64(N1C->getValue()),
848 TLI.getShiftAmountTy()));
849 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
850 if (N1.getOpcode() == ISD::SHL) {
851 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
852 if (isPowerOf2_64(SHC->getValue())) {
853 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
854 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
855 DAG.getConstant(Log2_64(SHC->getValue()),
857 AddToWorkList(Add.Val);
858 return DAG.getNode(ISD::SRL, VT, N0, Add);
862 // fold (udiv x, c) -> alternate
863 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
864 SDOperand Op = BuildUDIV(N);
865 if (Op.Val) return Op;
870 SDOperand DAGCombiner::visitSREM(SDNode *N) {
871 SDOperand N0 = N->getOperand(0);
872 SDOperand N1 = N->getOperand(1);
873 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
874 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
875 MVT::ValueType VT = N->getValueType(0);
877 // fold (srem c1, c2) -> c1%c2
878 if (N0C && N1C && !N1C->isNullValue())
879 return DAG.getNode(ISD::SREM, VT, N0, N1);
880 // If we know the sign bits of both operands are zero, strength reduce to a
881 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
882 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
883 if (TLI.MaskedValueIsZero(N1, SignBit) &&
884 TLI.MaskedValueIsZero(N0, SignBit))
885 return DAG.getNode(ISD::UREM, VT, N0, N1);
889 SDOperand DAGCombiner::visitUREM(SDNode *N) {
890 SDOperand N0 = N->getOperand(0);
891 SDOperand N1 = N->getOperand(1);
892 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
893 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
894 MVT::ValueType VT = N->getValueType(0);
896 // fold (urem c1, c2) -> c1%c2
897 if (N0C && N1C && !N1C->isNullValue())
898 return DAG.getNode(ISD::UREM, VT, N0, N1);
899 // fold (urem x, pow2) -> (and x, pow2-1)
900 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
901 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
902 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
903 if (N1.getOpcode() == ISD::SHL) {
904 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
905 if (isPowerOf2_64(SHC->getValue())) {
906 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
907 AddToWorkList(Add.Val);
908 return DAG.getNode(ISD::AND, VT, N0, Add);
915 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
916 SDOperand N0 = N->getOperand(0);
917 SDOperand N1 = N->getOperand(1);
918 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
920 // fold (mulhs x, 0) -> 0
921 if (N1C && N1C->isNullValue())
923 // fold (mulhs x, 1) -> (sra x, size(x)-1)
924 if (N1C && N1C->getValue() == 1)
925 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
926 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
927 TLI.getShiftAmountTy()));
931 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
932 SDOperand N0 = N->getOperand(0);
933 SDOperand N1 = N->getOperand(1);
934 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
936 // fold (mulhu x, 0) -> 0
937 if (N1C && N1C->isNullValue())
939 // fold (mulhu x, 1) -> 0
940 if (N1C && N1C->getValue() == 1)
941 return DAG.getConstant(0, N0.getValueType());
945 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
946 /// two operands of the same opcode, try to simplify it.
947 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
948 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
949 MVT::ValueType VT = N0.getValueType();
950 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
952 // For each of OP in AND/OR/XOR:
953 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
954 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
955 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
956 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
957 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
958 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
959 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
960 SDOperand ORNode = DAG.getNode(N->getOpcode(),
961 N0.getOperand(0).getValueType(),
962 N0.getOperand(0), N1.getOperand(0));
963 AddToWorkList(ORNode.Val);
964 return DAG.getNode(N0.getOpcode(), VT, ORNode);
967 // For each of OP in SHL/SRL/SRA/AND...
968 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
969 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
970 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
971 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
972 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
973 N0.getOperand(1) == N1.getOperand(1)) {
974 SDOperand ORNode = DAG.getNode(N->getOpcode(),
975 N0.getOperand(0).getValueType(),
976 N0.getOperand(0), N1.getOperand(0));
977 AddToWorkList(ORNode.Val);
978 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
984 SDOperand DAGCombiner::visitAND(SDNode *N) {
985 SDOperand N0 = N->getOperand(0);
986 SDOperand N1 = N->getOperand(1);
987 SDOperand LL, LR, RL, RR, CC0, CC1;
988 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
989 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
990 MVT::ValueType VT = N1.getValueType();
991 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
993 // fold (and c1, c2) -> c1&c2
995 return DAG.getNode(ISD::AND, VT, N0, N1);
996 // canonicalize constant to RHS
998 return DAG.getNode(ISD::AND, VT, N1, N0);
999 // fold (and x, -1) -> x
1000 if (N1C && N1C->isAllOnesValue())
1002 // if (and x, c) is known to be zero, return 0
1003 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1004 return DAG.getConstant(0, VT);
1006 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1009 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1010 if (N1C && N0.getOpcode() == ISD::OR)
1011 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1012 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1014 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1015 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1016 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1017 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1018 ~N1C->getValue() & InMask)) {
1019 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1022 // Replace uses of the AND with uses of the Zero extend node.
1025 // We actually want to replace all uses of the any_extend with the
1026 // zero_extend, to avoid duplicating things. This will later cause this
1027 // AND to be folded.
1028 CombineTo(N0.Val, Zext);
1029 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1032 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1033 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1034 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1035 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1037 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1038 MVT::isInteger(LL.getValueType())) {
1039 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1040 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1041 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1042 AddToWorkList(ORNode.Val);
1043 return DAG.getSetCC(VT, ORNode, LR, Op1);
1045 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1046 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1047 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1048 AddToWorkList(ANDNode.Val);
1049 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1051 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1052 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1053 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1054 AddToWorkList(ORNode.Val);
1055 return DAG.getSetCC(VT, ORNode, LR, Op1);
1058 // canonicalize equivalent to ll == rl
1059 if (LL == RR && LR == RL) {
1060 Op1 = ISD::getSetCCSwappedOperands(Op1);
1063 if (LL == RL && LR == RR) {
1064 bool isInteger = MVT::isInteger(LL.getValueType());
1065 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1066 if (Result != ISD::SETCC_INVALID)
1067 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1071 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1072 if (N0.getOpcode() == N1.getOpcode()) {
1073 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1074 if (Tmp.Val) return Tmp;
1077 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1078 // fold (and (sra)) -> (and (srl)) when possible.
1079 if (!MVT::isVector(VT) &&
1080 SimplifyDemandedBits(SDOperand(N, 0)))
1081 return SDOperand(N, 0);
1082 // fold (zext_inreg (extload x)) -> (zextload x)
1083 if (ISD::isEXTLoad(N0.Val)) {
1084 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1085 MVT::ValueType EVT = LN0->getLoadedVT();
1086 // If we zero all the possible extended bits, then we can turn this into
1087 // a zextload if we are running before legalize or the operation is legal.
1088 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1089 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1090 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1091 LN0->getBasePtr(), LN0->getSrcValue(),
1092 LN0->getSrcValueOffset(), EVT);
1094 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1095 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1098 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1099 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
1100 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1101 MVT::ValueType EVT = LN0->getLoadedVT();
1102 // If we zero all the possible extended bits, then we can turn this into
1103 // a zextload if we are running before legalize or the operation is legal.
1104 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1105 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1106 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1107 LN0->getBasePtr(), LN0->getSrcValue(),
1108 LN0->getSrcValueOffset(), EVT);
1110 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1111 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1115 // fold (and (load x), 255) -> (zextload x, i8)
1116 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1117 if (N1C && N0.getOpcode() == ISD::LOAD) {
1118 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1119 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1121 MVT::ValueType EVT, LoadedVT;
1122 if (N1C->getValue() == 255)
1124 else if (N1C->getValue() == 65535)
1126 else if (N1C->getValue() == ~0U)
1131 LoadedVT = LN0->getLoadedVT();
1132 if (EVT != MVT::Other && LoadedVT > EVT &&
1133 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1134 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1135 // For big endian targets, we need to add an offset to the pointer to
1136 // load the correct bytes. For little endian systems, we merely need to
1137 // read fewer bytes from the same pointer.
1139 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1140 SDOperand NewPtr = LN0->getBasePtr();
1141 if (!TLI.isLittleEndian())
1142 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1143 DAG.getConstant(PtrOff, PtrType));
1144 AddToWorkList(NewPtr.Val);
1146 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1147 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1149 CombineTo(N0.Val, Load, Load.getValue(1));
1150 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1158 SDOperand DAGCombiner::visitOR(SDNode *N) {
1159 SDOperand N0 = N->getOperand(0);
1160 SDOperand N1 = N->getOperand(1);
1161 SDOperand LL, LR, RL, RR, CC0, CC1;
1162 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1163 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1164 MVT::ValueType VT = N1.getValueType();
1165 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1167 // fold (or c1, c2) -> c1|c2
1169 return DAG.getNode(ISD::OR, VT, N0, N1);
1170 // canonicalize constant to RHS
1172 return DAG.getNode(ISD::OR, VT, N1, N0);
1173 // fold (or x, 0) -> x
1174 if (N1C && N1C->isNullValue())
1176 // fold (or x, -1) -> -1
1177 if (N1C && N1C->isAllOnesValue())
1179 // fold (or x, c) -> c iff (x & ~c) == 0
1181 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1184 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1187 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1188 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1189 isa<ConstantSDNode>(N0.getOperand(1))) {
1190 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1191 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1193 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1195 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1196 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1197 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1198 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1200 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1201 MVT::isInteger(LL.getValueType())) {
1202 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1203 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1204 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1205 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1206 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1207 AddToWorkList(ORNode.Val);
1208 return DAG.getSetCC(VT, ORNode, LR, Op1);
1210 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1211 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1212 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1213 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1214 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1215 AddToWorkList(ANDNode.Val);
1216 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1219 // canonicalize equivalent to ll == rl
1220 if (LL == RR && LR == RL) {
1221 Op1 = ISD::getSetCCSwappedOperands(Op1);
1224 if (LL == RL && LR == RR) {
1225 bool isInteger = MVT::isInteger(LL.getValueType());
1226 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1227 if (Result != ISD::SETCC_INVALID)
1228 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1232 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1233 if (N0.getOpcode() == N1.getOpcode()) {
1234 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1235 if (Tmp.Val) return Tmp;
1238 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1239 if (N0.getOpcode() == ISD::AND &&
1240 N1.getOpcode() == ISD::AND &&
1241 N0.getOperand(1).getOpcode() == ISD::Constant &&
1242 N1.getOperand(1).getOpcode() == ISD::Constant &&
1243 // Don't increase # computations.
1244 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1245 // We can only do this xform if we know that bits from X that are set in C2
1246 // but not in C1 are already zero. Likewise for Y.
1247 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1248 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1250 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1251 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1252 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1253 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1258 // See if this is some rotate idiom.
1259 if (SDNode *Rot = MatchRotate(N0, N1))
1260 return SDOperand(Rot, 0);
1266 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1267 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1268 if (Op.getOpcode() == ISD::AND) {
1269 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1270 Mask = Op.getOperand(1);
1271 Op = Op.getOperand(0);
1277 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1285 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1286 // idioms for rotate, and if the target supports rotation instructions, generate
1288 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1289 // Must be a legal type. Expanded an promoted things won't work with rotates.
1290 MVT::ValueType VT = LHS.getValueType();
1291 if (!TLI.isTypeLegal(VT)) return 0;
1293 // The target must have at least one rotate flavor.
1294 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1295 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1296 if (!HasROTL && !HasROTR) return 0;
1298 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1299 SDOperand LHSShift; // The shift.
1300 SDOperand LHSMask; // AND value if any.
1301 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1302 return 0; // Not part of a rotate.
1304 SDOperand RHSShift; // The shift.
1305 SDOperand RHSMask; // AND value if any.
1306 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1307 return 0; // Not part of a rotate.
1309 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1310 return 0; // Not shifting the same value.
1312 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1313 return 0; // Shifts must disagree.
1315 // Canonicalize shl to left side in a shl/srl pair.
1316 if (RHSShift.getOpcode() == ISD::SHL) {
1317 std::swap(LHS, RHS);
1318 std::swap(LHSShift, RHSShift);
1319 std::swap(LHSMask , RHSMask );
1322 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1324 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1325 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1326 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1327 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1328 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1329 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1330 if ((LShVal + RShVal) != OpSizeInBits)
1335 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1336 LHSShift.getOperand(1));
1338 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1339 RHSShift.getOperand(1));
1341 // If there is an AND of either shifted operand, apply it to the result.
1342 if (LHSMask.Val || RHSMask.Val) {
1343 uint64_t Mask = MVT::getIntVTBitMask(VT);
1346 uint64_t RHSBits = (1ULL << LShVal)-1;
1347 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1350 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1351 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1354 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1360 // If there is a mask here, and we have a variable shift, we can't be sure
1361 // that we're masking out the right stuff.
1362 if (LHSMask.Val || RHSMask.Val)
1365 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1366 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1367 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1368 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1369 if (ConstantSDNode *SUBC =
1370 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1371 if (SUBC->getValue() == OpSizeInBits)
1373 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1374 LHSShift.getOperand(1)).Val;
1376 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1377 LHSShift.getOperand(1)).Val;
1381 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1382 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1383 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1384 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1385 if (ConstantSDNode *SUBC =
1386 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1387 if (SUBC->getValue() == OpSizeInBits)
1389 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1390 LHSShift.getOperand(1)).Val;
1392 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1393 RHSShift.getOperand(1)).Val;
1401 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1402 SDOperand N0 = N->getOperand(0);
1403 SDOperand N1 = N->getOperand(1);
1404 SDOperand LHS, RHS, CC;
1405 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1406 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1407 MVT::ValueType VT = N0.getValueType();
1409 // fold (xor c1, c2) -> c1^c2
1411 return DAG.getNode(ISD::XOR, VT, N0, N1);
1412 // canonicalize constant to RHS
1414 return DAG.getNode(ISD::XOR, VT, N1, N0);
1415 // fold (xor x, 0) -> x
1416 if (N1C && N1C->isNullValue())
1419 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1422 // fold !(x cc y) -> (x !cc y)
1423 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1424 bool isInt = MVT::isInteger(LHS.getValueType());
1425 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1427 if (N0.getOpcode() == ISD::SETCC)
1428 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1429 if (N0.getOpcode() == ISD::SELECT_CC)
1430 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1431 assert(0 && "Unhandled SetCC Equivalent!");
1434 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1435 if (N1C && N1C->getValue() == 1 &&
1436 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1437 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1438 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1439 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1440 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1441 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1442 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1443 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1446 // fold !(x or y) -> (!x and !y) iff x or y are constants
1447 if (N1C && N1C->isAllOnesValue() &&
1448 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1449 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1450 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1451 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1452 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1453 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1454 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1455 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1458 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1459 if (N1C && N0.getOpcode() == ISD::XOR) {
1460 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1461 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1463 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1464 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1466 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1467 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1469 // fold (xor x, x) -> 0
1471 if (!MVT::isVector(VT)) {
1472 return DAG.getConstant(0, VT);
1473 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1474 // Produce a vector of zeros.
1475 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1476 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1477 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1481 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1482 if (N0.getOpcode() == N1.getOpcode()) {
1483 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1484 if (Tmp.Val) return Tmp;
1487 // Simplify the expression using non-local knowledge.
1488 if (!MVT::isVector(VT) &&
1489 SimplifyDemandedBits(SDOperand(N, 0)))
1490 return SDOperand(N, 0);
1495 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1496 SDOperand N0 = N->getOperand(0);
1497 SDOperand N1 = N->getOperand(1);
1498 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1499 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1500 MVT::ValueType VT = N0.getValueType();
1501 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1503 // fold (shl c1, c2) -> c1<<c2
1505 return DAG.getNode(ISD::SHL, VT, N0, N1);
1506 // fold (shl 0, x) -> 0
1507 if (N0C && N0C->isNullValue())
1509 // fold (shl x, c >= size(x)) -> undef
1510 if (N1C && N1C->getValue() >= OpSizeInBits)
1511 return DAG.getNode(ISD::UNDEF, VT);
1512 // fold (shl x, 0) -> x
1513 if (N1C && N1C->isNullValue())
1515 // if (shl x, c) is known to be zero, return 0
1516 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1517 return DAG.getConstant(0, VT);
1518 if (SimplifyDemandedBits(SDOperand(N, 0)))
1519 return SDOperand(N, 0);
1520 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1521 if (N1C && N0.getOpcode() == ISD::SHL &&
1522 N0.getOperand(1).getOpcode() == ISD::Constant) {
1523 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1524 uint64_t c2 = N1C->getValue();
1525 if (c1 + c2 > OpSizeInBits)
1526 return DAG.getConstant(0, VT);
1527 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1528 DAG.getConstant(c1 + c2, N1.getValueType()));
1530 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1531 // (srl (and x, -1 << c1), c1-c2)
1532 if (N1C && N0.getOpcode() == ISD::SRL &&
1533 N0.getOperand(1).getOpcode() == ISD::Constant) {
1534 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1535 uint64_t c2 = N1C->getValue();
1536 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1537 DAG.getConstant(~0ULL << c1, VT));
1539 return DAG.getNode(ISD::SHL, VT, Mask,
1540 DAG.getConstant(c2-c1, N1.getValueType()));
1542 return DAG.getNode(ISD::SRL, VT, Mask,
1543 DAG.getConstant(c1-c2, N1.getValueType()));
1545 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1546 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1547 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1548 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1549 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1550 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1551 isa<ConstantSDNode>(N0.getOperand(1))) {
1552 return DAG.getNode(ISD::ADD, VT,
1553 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1554 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1559 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1560 SDOperand N0 = N->getOperand(0);
1561 SDOperand N1 = N->getOperand(1);
1562 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1563 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1564 MVT::ValueType VT = N0.getValueType();
1566 // fold (sra c1, c2) -> c1>>c2
1568 return DAG.getNode(ISD::SRA, VT, N0, N1);
1569 // fold (sra 0, x) -> 0
1570 if (N0C && N0C->isNullValue())
1572 // fold (sra -1, x) -> -1
1573 if (N0C && N0C->isAllOnesValue())
1575 // fold (sra x, c >= size(x)) -> undef
1576 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1577 return DAG.getNode(ISD::UNDEF, VT);
1578 // fold (sra x, 0) -> x
1579 if (N1C && N1C->isNullValue())
1581 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1583 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1584 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1587 default: EVT = MVT::Other; break;
1588 case 1: EVT = MVT::i1; break;
1589 case 8: EVT = MVT::i8; break;
1590 case 16: EVT = MVT::i16; break;
1591 case 32: EVT = MVT::i32; break;
1593 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1594 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1595 DAG.getValueType(EVT));
1598 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1599 if (N1C && N0.getOpcode() == ISD::SRA) {
1600 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1601 unsigned Sum = N1C->getValue() + C1->getValue();
1602 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1603 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1604 DAG.getConstant(Sum, N1C->getValueType(0)));
1608 // Simplify, based on bits shifted out of the LHS.
1609 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1610 return SDOperand(N, 0);
1613 // If the sign bit is known to be zero, switch this to a SRL.
1614 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1615 return DAG.getNode(ISD::SRL, VT, N0, N1);
1619 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1620 SDOperand N0 = N->getOperand(0);
1621 SDOperand N1 = N->getOperand(1);
1622 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1623 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1624 MVT::ValueType VT = N0.getValueType();
1625 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1627 // fold (srl c1, c2) -> c1 >>u c2
1629 return DAG.getNode(ISD::SRL, VT, N0, N1);
1630 // fold (srl 0, x) -> 0
1631 if (N0C && N0C->isNullValue())
1633 // fold (srl x, c >= size(x)) -> undef
1634 if (N1C && N1C->getValue() >= OpSizeInBits)
1635 return DAG.getNode(ISD::UNDEF, VT);
1636 // fold (srl x, 0) -> x
1637 if (N1C && N1C->isNullValue())
1639 // if (srl x, c) is known to be zero, return 0
1640 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1641 return DAG.getConstant(0, VT);
1642 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1643 if (N1C && N0.getOpcode() == ISD::SRL &&
1644 N0.getOperand(1).getOpcode() == ISD::Constant) {
1645 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1646 uint64_t c2 = N1C->getValue();
1647 if (c1 + c2 > OpSizeInBits)
1648 return DAG.getConstant(0, VT);
1649 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1650 DAG.getConstant(c1 + c2, N1.getValueType()));
1653 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1654 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1655 // Shifting in all undef bits?
1656 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1657 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1658 return DAG.getNode(ISD::UNDEF, VT);
1660 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1661 AddToWorkList(SmallShift.Val);
1662 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1665 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1666 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1667 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1668 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1669 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1671 // If any of the input bits are KnownOne, then the input couldn't be all
1672 // zeros, thus the result of the srl will always be zero.
1673 if (KnownOne) return DAG.getConstant(0, VT);
1675 // If all of the bits input the to ctlz node are known to be zero, then
1676 // the result of the ctlz is "32" and the result of the shift is one.
1677 uint64_t UnknownBits = ~KnownZero & Mask;
1678 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1680 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1681 if ((UnknownBits & (UnknownBits-1)) == 0) {
1682 // Okay, we know that only that the single bit specified by UnknownBits
1683 // could be set on input to the CTLZ node. If this bit is set, the SRL
1684 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1685 // to an SRL,XOR pair, which is likely to simplify more.
1686 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1687 SDOperand Op = N0.getOperand(0);
1689 Op = DAG.getNode(ISD::SRL, VT, Op,
1690 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1691 AddToWorkList(Op.Val);
1693 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1700 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1701 SDOperand N0 = N->getOperand(0);
1702 MVT::ValueType VT = N->getValueType(0);
1704 // fold (ctlz c1) -> c2
1705 if (isa<ConstantSDNode>(N0))
1706 return DAG.getNode(ISD::CTLZ, VT, N0);
1710 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1711 SDOperand N0 = N->getOperand(0);
1712 MVT::ValueType VT = N->getValueType(0);
1714 // fold (cttz c1) -> c2
1715 if (isa<ConstantSDNode>(N0))
1716 return DAG.getNode(ISD::CTTZ, VT, N0);
1720 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1721 SDOperand N0 = N->getOperand(0);
1722 MVT::ValueType VT = N->getValueType(0);
1724 // fold (ctpop c1) -> c2
1725 if (isa<ConstantSDNode>(N0))
1726 return DAG.getNode(ISD::CTPOP, VT, N0);
1730 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1731 SDOperand N0 = N->getOperand(0);
1732 SDOperand N1 = N->getOperand(1);
1733 SDOperand N2 = N->getOperand(2);
1734 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1735 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1736 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1737 MVT::ValueType VT = N->getValueType(0);
1739 // fold select C, X, X -> X
1742 // fold select true, X, Y -> X
1743 if (N0C && !N0C->isNullValue())
1745 // fold select false, X, Y -> Y
1746 if (N0C && N0C->isNullValue())
1748 // fold select C, 1, X -> C | X
1749 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1750 return DAG.getNode(ISD::OR, VT, N0, N2);
1751 // fold select C, 0, X -> ~C & X
1752 // FIXME: this should check for C type == X type, not i1?
1753 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1754 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1755 AddToWorkList(XORNode.Val);
1756 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1758 // fold select C, X, 1 -> ~C | X
1759 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1760 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1761 AddToWorkList(XORNode.Val);
1762 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1764 // fold select C, X, 0 -> C & X
1765 // FIXME: this should check for C type == X type, not i1?
1766 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1767 return DAG.getNode(ISD::AND, VT, N0, N1);
1768 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1769 if (MVT::i1 == VT && N0 == N1)
1770 return DAG.getNode(ISD::OR, VT, N0, N2);
1771 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1772 if (MVT::i1 == VT && N0 == N2)
1773 return DAG.getNode(ISD::AND, VT, N0, N1);
1775 // If we can fold this based on the true/false value, do so.
1776 if (SimplifySelectOps(N, N1, N2))
1777 return SDOperand(N, 0); // Don't revisit N.
1779 // fold selects based on a setcc into other things, such as min/max/abs
1780 if (N0.getOpcode() == ISD::SETCC)
1782 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1783 // having to say they don't support SELECT_CC on every type the DAG knows
1784 // about, since there is no way to mark an opcode illegal at all value types
1785 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1786 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1787 N1, N2, N0.getOperand(2));
1789 return SimplifySelect(N0, N1, N2);
1793 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1794 SDOperand N0 = N->getOperand(0);
1795 SDOperand N1 = N->getOperand(1);
1796 SDOperand N2 = N->getOperand(2);
1797 SDOperand N3 = N->getOperand(3);
1798 SDOperand N4 = N->getOperand(4);
1799 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1800 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1801 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1802 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1804 // fold select_cc lhs, rhs, x, x, cc -> x
1808 // Determine if the condition we're dealing with is constant
1809 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1811 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1812 if (SCCC->getValue())
1813 return N2; // cond always true -> true val
1815 return N3; // cond always false -> false val
1818 // Fold to a simpler select_cc
1819 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1820 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1821 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1824 // If we can fold this based on the true/false value, do so.
1825 if (SimplifySelectOps(N, N2, N3))
1826 return SDOperand(N, 0); // Don't revisit N.
1828 // fold select_cc into other things, such as min/max/abs
1829 return SimplifySelectCC(N0, N1, N2, N3, CC);
1832 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1833 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1834 cast<CondCodeSDNode>(N->getOperand(2))->get());
1837 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1838 SDOperand N0 = N->getOperand(0);
1839 MVT::ValueType VT = N->getValueType(0);
1841 // fold (sext c1) -> c1
1842 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1843 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1845 // fold (sext (sext x)) -> (sext x)
1846 // fold (sext (aext x)) -> (sext x)
1847 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1848 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1850 // fold (sext (truncate x)) -> (sextinreg x).
1851 if (N0.getOpcode() == ISD::TRUNCATE &&
1852 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
1853 N0.getValueType()))) {
1854 SDOperand Op = N0.getOperand(0);
1855 if (Op.getValueType() < VT) {
1856 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1857 } else if (Op.getValueType() > VT) {
1858 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1860 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
1861 DAG.getValueType(N0.getValueType()));
1864 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1865 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1866 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
1867 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1868 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1869 LN0->getBasePtr(), LN0->getSrcValue(),
1870 LN0->getSrcValueOffset(),
1872 CombineTo(N, ExtLoad);
1873 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1874 ExtLoad.getValue(1));
1875 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1878 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1879 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1880 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1881 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1882 MVT::ValueType EVT = LN0->getLoadedVT();
1883 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1884 LN0->getBasePtr(), LN0->getSrcValue(),
1885 LN0->getSrcValueOffset(), EVT);
1886 CombineTo(N, ExtLoad);
1887 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1888 ExtLoad.getValue(1));
1889 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1895 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1896 SDOperand N0 = N->getOperand(0);
1897 MVT::ValueType VT = N->getValueType(0);
1899 // fold (zext c1) -> c1
1900 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1901 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1902 // fold (zext (zext x)) -> (zext x)
1903 // fold (zext (aext x)) -> (zext x)
1904 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1905 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1907 // fold (zext (truncate x)) -> (and x, mask)
1908 if (N0.getOpcode() == ISD::TRUNCATE &&
1909 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
1910 SDOperand Op = N0.getOperand(0);
1911 if (Op.getValueType() < VT) {
1912 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1913 } else if (Op.getValueType() > VT) {
1914 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1916 return DAG.getZeroExtendInReg(Op, N0.getValueType());
1919 // fold (zext (and (trunc x), cst)) -> (and x, cst).
1920 if (N0.getOpcode() == ISD::AND &&
1921 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1922 N0.getOperand(1).getOpcode() == ISD::Constant) {
1923 SDOperand X = N0.getOperand(0).getOperand(0);
1924 if (X.getValueType() < VT) {
1925 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1926 } else if (X.getValueType() > VT) {
1927 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1929 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1930 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
1933 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1934 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1935 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
1936 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1937 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1938 LN0->getBasePtr(), LN0->getSrcValue(),
1939 LN0->getSrcValueOffset(),
1941 CombineTo(N, ExtLoad);
1942 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1943 ExtLoad.getValue(1));
1944 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1947 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1948 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1949 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1950 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1951 MVT::ValueType EVT = LN0->getLoadedVT();
1952 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1953 LN0->getBasePtr(), LN0->getSrcValue(),
1954 LN0->getSrcValueOffset(), EVT);
1955 CombineTo(N, ExtLoad);
1956 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1957 ExtLoad.getValue(1));
1958 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1963 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
1964 SDOperand N0 = N->getOperand(0);
1965 MVT::ValueType VT = N->getValueType(0);
1967 // fold (aext c1) -> c1
1968 if (isa<ConstantSDNode>(N0))
1969 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
1970 // fold (aext (aext x)) -> (aext x)
1971 // fold (aext (zext x)) -> (zext x)
1972 // fold (aext (sext x)) -> (sext x)
1973 if (N0.getOpcode() == ISD::ANY_EXTEND ||
1974 N0.getOpcode() == ISD::ZERO_EXTEND ||
1975 N0.getOpcode() == ISD::SIGN_EXTEND)
1976 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1978 // fold (aext (truncate x))
1979 if (N0.getOpcode() == ISD::TRUNCATE) {
1980 SDOperand TruncOp = N0.getOperand(0);
1981 if (TruncOp.getValueType() == VT)
1982 return TruncOp; // x iff x size == zext size.
1983 if (TruncOp.getValueType() > VT)
1984 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
1985 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
1988 // fold (aext (and (trunc x), cst)) -> (and x, cst).
1989 if (N0.getOpcode() == ISD::AND &&
1990 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1991 N0.getOperand(1).getOpcode() == ISD::Constant) {
1992 SDOperand X = N0.getOperand(0).getOperand(0);
1993 if (X.getValueType() < VT) {
1994 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1995 } else if (X.getValueType() > VT) {
1996 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1998 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1999 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2002 // fold (aext (load x)) -> (aext (truncate (extload x)))
2003 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2004 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2005 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2006 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2007 LN0->getBasePtr(), LN0->getSrcValue(),
2008 LN0->getSrcValueOffset(),
2010 CombineTo(N, ExtLoad);
2011 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2012 ExtLoad.getValue(1));
2013 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2016 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2017 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2018 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2019 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
2021 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2022 MVT::ValueType EVT = LN0->getLoadedVT();
2023 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2024 LN0->getChain(), LN0->getBasePtr(),
2026 LN0->getSrcValueOffset(), EVT);
2027 CombineTo(N, ExtLoad);
2028 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2029 ExtLoad.getValue(1));
2030 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2036 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2037 SDOperand N0 = N->getOperand(0);
2038 SDOperand N1 = N->getOperand(1);
2039 MVT::ValueType VT = N->getValueType(0);
2040 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2041 unsigned EVTBits = MVT::getSizeInBits(EVT);
2043 // fold (sext_in_reg c1) -> c1
2044 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2045 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2047 // If the input is already sign extended, just drop the extension.
2048 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2051 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2052 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2053 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2054 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2057 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2058 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2059 return DAG.getZeroExtendInReg(N0, EVT);
2061 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2062 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2063 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2064 if (N0.getOpcode() == ISD::SRL) {
2065 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2066 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2067 // We can turn this into an SRA iff the input to the SRL is already sign
2069 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2070 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2071 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2075 // fold (sext_inreg (extload x)) -> (sextload x)
2076 if (ISD::isEXTLoad(N0.Val) &&
2077 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2078 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2079 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2080 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2081 LN0->getBasePtr(), LN0->getSrcValue(),
2082 LN0->getSrcValueOffset(), EVT);
2083 CombineTo(N, ExtLoad);
2084 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2085 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2087 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2088 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
2089 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2090 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2091 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2092 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2093 LN0->getBasePtr(), LN0->getSrcValue(),
2094 LN0->getSrcValueOffset(), EVT);
2095 CombineTo(N, ExtLoad);
2096 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2097 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2102 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2103 SDOperand N0 = N->getOperand(0);
2104 MVT::ValueType VT = N->getValueType(0);
2107 if (N0.getValueType() == N->getValueType(0))
2109 // fold (truncate c1) -> c1
2110 if (isa<ConstantSDNode>(N0))
2111 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2112 // fold (truncate (truncate x)) -> (truncate x)
2113 if (N0.getOpcode() == ISD::TRUNCATE)
2114 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2115 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2116 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2117 N0.getOpcode() == ISD::ANY_EXTEND) {
2118 if (N0.getValueType() < VT)
2119 // if the source is smaller than the dest, we still need an extend
2120 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2121 else if (N0.getValueType() > VT)
2122 // if the source is larger than the dest, than we just need the truncate
2123 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2125 // if the source and dest are the same type, we can drop both the extend
2127 return N0.getOperand(0);
2129 // fold (truncate (load x)) -> (smaller load x)
2130 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2131 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2132 "Cannot truncate to larger type!");
2133 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2134 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2135 // For big endian targets, we need to add an offset to the pointer to load
2136 // the correct bytes. For little endian systems, we merely need to read
2137 // fewer bytes from the same pointer.
2139 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2140 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() :
2141 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2142 DAG.getConstant(PtrOff, PtrType));
2143 AddToWorkList(NewPtr.Val);
2144 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr,
2145 LN0->getSrcValue(), LN0->getSrcValueOffset());
2147 CombineTo(N0.Val, Load, Load.getValue(1));
2148 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2153 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2154 SDOperand N0 = N->getOperand(0);
2155 MVT::ValueType VT = N->getValueType(0);
2157 // If the input is a constant, let getNode() fold it.
2158 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2159 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2160 if (Res.Val != N) return Res;
2163 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2164 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2166 // fold (conv (load x)) -> (load (conv*)x)
2167 // FIXME: These xforms need to know that the resultant load doesn't need a
2168 // higher alignment than the original!
2169 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2170 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2171 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2172 LN0->getSrcValue(), LN0->getSrcValueOffset());
2174 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2182 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2183 SDOperand N0 = N->getOperand(0);
2184 MVT::ValueType VT = N->getValueType(0);
2186 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2187 // First check to see if this is all constant.
2188 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2189 VT == MVT::Vector) {
2190 bool isSimple = true;
2191 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2192 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2193 N0.getOperand(i).getOpcode() != ISD::Constant &&
2194 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2199 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2200 if (isSimple && !MVT::isVector(DestEltVT)) {
2201 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2208 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2209 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2210 /// destination element value type.
2211 SDOperand DAGCombiner::
2212 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2213 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2215 // If this is already the right type, we're done.
2216 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2218 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2219 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2221 // If this is a conversion of N elements of one type to N elements of another
2222 // type, convert each element. This handles FP<->INT cases.
2223 if (SrcBitSize == DstBitSize) {
2224 SmallVector<SDOperand, 8> Ops;
2225 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2226 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2227 AddToWorkList(Ops.back().Val);
2229 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2230 Ops.push_back(DAG.getValueType(DstEltVT));
2231 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2234 // Otherwise, we're growing or shrinking the elements. To avoid having to
2235 // handle annoying details of growing/shrinking FP values, we convert them to
2237 if (MVT::isFloatingPoint(SrcEltVT)) {
2238 // Convert the input float vector to a int vector where the elements are the
2240 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2241 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2242 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2246 // Now we know the input is an integer vector. If the output is a FP type,
2247 // convert to integer first, then to FP of the right size.
2248 if (MVT::isFloatingPoint(DstEltVT)) {
2249 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2250 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2251 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2253 // Next, convert to FP elements of the same size.
2254 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2257 // Okay, we know the src/dst types are both integers of differing types.
2258 // Handling growing first.
2259 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2260 if (SrcBitSize < DstBitSize) {
2261 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2263 SmallVector<SDOperand, 8> Ops;
2264 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2265 i += NumInputsPerOutput) {
2266 bool isLE = TLI.isLittleEndian();
2267 uint64_t NewBits = 0;
2268 bool EltIsUndef = true;
2269 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2270 // Shift the previously computed bits over.
2271 NewBits <<= SrcBitSize;
2272 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2273 if (Op.getOpcode() == ISD::UNDEF) continue;
2276 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2280 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2282 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2285 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2286 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2287 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2290 // Finally, this must be the case where we are shrinking elements: each input
2291 // turns into multiple outputs.
2292 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2293 SmallVector<SDOperand, 8> Ops;
2294 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2295 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2296 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2297 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2300 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2302 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2303 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2304 OpVal >>= DstBitSize;
2305 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2308 // For big endian targets, swap the order of the pieces of each element.
2309 if (!TLI.isLittleEndian())
2310 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2312 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2313 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2314 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2319 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2320 SDOperand N0 = N->getOperand(0);
2321 SDOperand N1 = N->getOperand(1);
2322 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2323 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2324 MVT::ValueType VT = N->getValueType(0);
2326 // fold (fadd c1, c2) -> c1+c2
2328 return DAG.getNode(ISD::FADD, VT, N0, N1);
2329 // canonicalize constant to RHS
2330 if (N0CFP && !N1CFP)
2331 return DAG.getNode(ISD::FADD, VT, N1, N0);
2332 // fold (A + (-B)) -> A-B
2333 if (N1.getOpcode() == ISD::FNEG)
2334 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2335 // fold ((-A) + B) -> B-A
2336 if (N0.getOpcode() == ISD::FNEG)
2337 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2341 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2342 SDOperand N0 = N->getOperand(0);
2343 SDOperand N1 = N->getOperand(1);
2344 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2345 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2346 MVT::ValueType VT = N->getValueType(0);
2348 // fold (fsub c1, c2) -> c1-c2
2350 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2351 // fold (A-(-B)) -> A+B
2352 if (N1.getOpcode() == ISD::FNEG)
2353 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2357 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2358 SDOperand N0 = N->getOperand(0);
2359 SDOperand N1 = N->getOperand(1);
2360 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2361 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2362 MVT::ValueType VT = N->getValueType(0);
2364 // fold (fmul c1, c2) -> c1*c2
2366 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2367 // canonicalize constant to RHS
2368 if (N0CFP && !N1CFP)
2369 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2370 // fold (fmul X, 2.0) -> (fadd X, X)
2371 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2372 return DAG.getNode(ISD::FADD, VT, N0, N0);
2376 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2377 SDOperand N0 = N->getOperand(0);
2378 SDOperand N1 = N->getOperand(1);
2379 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2380 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2381 MVT::ValueType VT = N->getValueType(0);
2383 // fold (fdiv c1, c2) -> c1/c2
2385 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2389 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2390 SDOperand N0 = N->getOperand(0);
2391 SDOperand N1 = N->getOperand(1);
2392 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2393 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2394 MVT::ValueType VT = N->getValueType(0);
2396 // fold (frem c1, c2) -> fmod(c1,c2)
2398 return DAG.getNode(ISD::FREM, VT, N0, N1);
2402 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2403 SDOperand N0 = N->getOperand(0);
2404 SDOperand N1 = N->getOperand(1);
2405 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2406 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2407 MVT::ValueType VT = N->getValueType(0);
2409 if (N0CFP && N1CFP) // Constant fold
2410 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2413 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2414 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2419 u.d = N1CFP->getValue();
2421 return DAG.getNode(ISD::FABS, VT, N0);
2423 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2426 // copysign(fabs(x), y) -> copysign(x, y)
2427 // copysign(fneg(x), y) -> copysign(x, y)
2428 // copysign(copysign(x,z), y) -> copysign(x, y)
2429 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2430 N0.getOpcode() == ISD::FCOPYSIGN)
2431 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2433 // copysign(x, abs(y)) -> abs(x)
2434 if (N1.getOpcode() == ISD::FABS)
2435 return DAG.getNode(ISD::FABS, VT, N0);
2437 // copysign(x, copysign(y,z)) -> copysign(x, z)
2438 if (N1.getOpcode() == ISD::FCOPYSIGN)
2439 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2441 // copysign(x, fp_extend(y)) -> copysign(x, y)
2442 // copysign(x, fp_round(y)) -> copysign(x, y)
2443 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2444 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2451 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2452 SDOperand N0 = N->getOperand(0);
2453 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2454 MVT::ValueType VT = N->getValueType(0);
2456 // fold (sint_to_fp c1) -> c1fp
2458 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2462 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2463 SDOperand N0 = N->getOperand(0);
2464 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2465 MVT::ValueType VT = N->getValueType(0);
2467 // fold (uint_to_fp c1) -> c1fp
2469 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2473 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2474 SDOperand N0 = N->getOperand(0);
2475 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2476 MVT::ValueType VT = N->getValueType(0);
2478 // fold (fp_to_sint c1fp) -> c1
2480 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2484 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2485 SDOperand N0 = N->getOperand(0);
2486 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2487 MVT::ValueType VT = N->getValueType(0);
2489 // fold (fp_to_uint c1fp) -> c1
2491 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2495 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2496 SDOperand N0 = N->getOperand(0);
2497 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2498 MVT::ValueType VT = N->getValueType(0);
2500 // fold (fp_round c1fp) -> c1fp
2502 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2504 // fold (fp_round (fp_extend x)) -> x
2505 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2506 return N0.getOperand(0);
2508 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2509 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2510 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2511 AddToWorkList(Tmp.Val);
2512 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2518 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2519 SDOperand N0 = N->getOperand(0);
2520 MVT::ValueType VT = N->getValueType(0);
2521 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2522 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2524 // fold (fp_round_inreg c1fp) -> c1fp
2526 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2527 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2532 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2533 SDOperand N0 = N->getOperand(0);
2534 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2535 MVT::ValueType VT = N->getValueType(0);
2537 // fold (fp_extend c1fp) -> c1fp
2539 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2541 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2542 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2543 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2544 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2545 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2546 LN0->getBasePtr(), LN0->getSrcValue(),
2547 LN0->getSrcValueOffset(),
2549 CombineTo(N, ExtLoad);
2550 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2551 ExtLoad.getValue(1));
2552 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2559 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2560 SDOperand N0 = N->getOperand(0);
2561 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2562 MVT::ValueType VT = N->getValueType(0);
2564 // fold (fneg c1) -> -c1
2566 return DAG.getNode(ISD::FNEG, VT, N0);
2567 // fold (fneg (sub x, y)) -> (sub y, x)
2568 if (N0.getOpcode() == ISD::SUB)
2569 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2570 // fold (fneg (fneg x)) -> x
2571 if (N0.getOpcode() == ISD::FNEG)
2572 return N0.getOperand(0);
2576 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2577 SDOperand N0 = N->getOperand(0);
2578 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2579 MVT::ValueType VT = N->getValueType(0);
2581 // fold (fabs c1) -> fabs(c1)
2583 return DAG.getNode(ISD::FABS, VT, N0);
2584 // fold (fabs (fabs x)) -> (fabs x)
2585 if (N0.getOpcode() == ISD::FABS)
2586 return N->getOperand(0);
2587 // fold (fabs (fneg x)) -> (fabs x)
2588 // fold (fabs (fcopysign x, y)) -> (fabs x)
2589 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2590 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2595 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2596 SDOperand Chain = N->getOperand(0);
2597 SDOperand N1 = N->getOperand(1);
2598 SDOperand N2 = N->getOperand(2);
2599 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2601 // never taken branch, fold to chain
2602 if (N1C && N1C->isNullValue())
2604 // unconditional branch
2605 if (N1C && N1C->getValue() == 1)
2606 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2607 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2609 if (N1.getOpcode() == ISD::SETCC &&
2610 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2611 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2612 N1.getOperand(0), N1.getOperand(1), N2);
2617 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2619 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2620 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2621 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2623 // Use SimplifySetCC to simplify SETCC's.
2624 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2625 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2627 // fold br_cc true, dest -> br dest (unconditional branch)
2628 if (SCCC && SCCC->getValue())
2629 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2631 // fold br_cc false, dest -> unconditional fall through
2632 if (SCCC && SCCC->isNullValue())
2633 return N->getOperand(0);
2634 // fold to a simpler setcc
2635 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2636 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2637 Simp.getOperand(2), Simp.getOperand(0),
2638 Simp.getOperand(1), N->getOperand(4));
2642 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2643 LoadSDNode *LD = cast<LoadSDNode>(N);
2644 SDOperand Chain = LD->getChain();
2645 SDOperand Ptr = LD->getBasePtr();
2647 // If there are no uses of the loaded value, change uses of the chain value
2648 // into uses of the chain input (i.e. delete the dead load).
2649 if (N->hasNUsesOfValue(0, 0))
2650 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2652 if (!ISD::isNON_EXTLoad(N))
2655 // If this load is directly stored, replace the load value with the stored
2657 // TODO: Handle store large -> read small portion.
2658 // TODO: Handle TRUNCSTORE/EXTLOAD
2659 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2660 Chain.getOperand(1).getValueType() == N->getValueType(0))
2661 return CombineTo(N, Chain.getOperand(1), Chain);
2664 // Walk up chain skipping non-aliasing memory nodes.
2665 SDOperand BetterChain = FindBetterChain(N, Chain);
2667 // If there is a better chain.
2668 if (Chain != BetterChain) {
2669 // Replace the chain to void dependency.
2670 SDOperand ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
2671 LD->getSrcValue(), LD->getSrcValueOffset());
2673 // Create token factor to keep old chain connected.
2674 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
2675 Chain, ReplLoad.getValue(1));
2677 // Replace uses with load result and token factor.
2678 return CombineTo(N, ReplLoad.getValue(0), Token);
2685 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2686 SDOperand Chain = N->getOperand(0);
2687 SDOperand Value = N->getOperand(1);
2688 SDOperand Ptr = N->getOperand(2);
2689 SDOperand SrcValue = N->getOperand(3);
2691 // If this is a store that kills a previous store, remove the previous store.
2692 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2693 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2694 // Make sure that these stores are the same value type:
2695 // FIXME: we really care that the second store is >= size of the first.
2696 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2697 // Create a new store of Value that replaces both stores.
2698 SDNode *PrevStore = Chain.Val;
2699 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2701 SDOperand NewStore = DAG.getStore(PrevStore->getOperand(0), Value, Ptr,
2703 CombineTo(N, NewStore); // Nuke this store.
2704 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2705 return SDOperand(N, 0);
2708 // If this is a store of a bit convert, store the input value.
2709 // FIXME: This needs to know that the resultant store does not need a
2710 // higher alignment than the original.
2711 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
2712 return DAG.getStore(Chain, Value.getOperand(0), Ptr, SrcValue);
2716 // If the store ptr is a frame index and the frame index has a use of one
2717 // and this is a return block, then the store is redundant.
2718 if (Ptr.hasOneUse() && isa<FrameIndexSDNode>(Ptr) &&
2719 DAG.getRoot().getOpcode() == ISD::RET) {
2723 // Walk up chain skipping non-aliasing memory nodes.
2724 SDOperand BetterChain = FindBetterChain(N, Chain);
2726 // If there is a better chain.
2727 if (Chain != BetterChain) {
2728 // Replace the chain to avoid dependency.
2729 SDOperand ReplStore = DAG.getStore(BetterChain, Value, Ptr, SrcValue);
2730 // Create token to keep both nodes around.
2731 return DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
2738 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
2739 SDOperand InVec = N->getOperand(0);
2740 SDOperand InVal = N->getOperand(1);
2741 SDOperand EltNo = N->getOperand(2);
2743 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
2744 // vector with the inserted element.
2745 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2746 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2747 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2748 if (Elt < Ops.size())
2750 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
2751 &Ops[0], Ops.size());
2757 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
2758 SDOperand InVec = N->getOperand(0);
2759 SDOperand InVal = N->getOperand(1);
2760 SDOperand EltNo = N->getOperand(2);
2761 SDOperand NumElts = N->getOperand(3);
2762 SDOperand EltType = N->getOperand(4);
2764 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
2765 // vector with the inserted element.
2766 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2767 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2768 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2769 if (Elt < Ops.size()-2)
2771 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
2772 &Ops[0], Ops.size());
2778 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
2779 unsigned NumInScalars = N->getNumOperands()-2;
2780 SDOperand NumElts = N->getOperand(NumInScalars);
2781 SDOperand EltType = N->getOperand(NumInScalars+1);
2783 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
2784 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
2785 // two distinct vectors, turn this into a shuffle node.
2786 SDOperand VecIn1, VecIn2;
2787 for (unsigned i = 0; i != NumInScalars; ++i) {
2788 // Ignore undef inputs.
2789 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2791 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
2792 // constant index, bail out.
2793 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
2794 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
2795 VecIn1 = VecIn2 = SDOperand(0, 0);
2799 // If the input vector type disagrees with the result of the vbuild_vector,
2800 // we can't make a shuffle.
2801 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
2802 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
2803 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
2804 VecIn1 = VecIn2 = SDOperand(0, 0);
2808 // Otherwise, remember this. We allow up to two distinct input vectors.
2809 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
2812 if (VecIn1.Val == 0) {
2813 VecIn1 = ExtractedFromVec;
2814 } else if (VecIn2.Val == 0) {
2815 VecIn2 = ExtractedFromVec;
2818 VecIn1 = VecIn2 = SDOperand(0, 0);
2823 // If everything is good, we can make a shuffle operation.
2825 SmallVector<SDOperand, 8> BuildVecIndices;
2826 for (unsigned i = 0; i != NumInScalars; ++i) {
2827 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
2828 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2832 SDOperand Extract = N->getOperand(i);
2834 // If extracting from the first vector, just use the index directly.
2835 if (Extract.getOperand(0) == VecIn1) {
2836 BuildVecIndices.push_back(Extract.getOperand(1));
2840 // Otherwise, use InIdx + VecSize
2841 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
2842 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
2845 // Add count and size info.
2846 BuildVecIndices.push_back(NumElts);
2847 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
2849 // Return the new VVECTOR_SHUFFLE node.
2855 // Use an undef vbuild_vector as input for the second operand.
2856 std::vector<SDOperand> UnOps(NumInScalars,
2857 DAG.getNode(ISD::UNDEF,
2858 cast<VTSDNode>(EltType)->getVT()));
2859 UnOps.push_back(NumElts);
2860 UnOps.push_back(EltType);
2861 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2862 &UnOps[0], UnOps.size());
2863 AddToWorkList(Ops[1].Val);
2865 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2866 &BuildVecIndices[0], BuildVecIndices.size());
2869 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
2875 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
2876 SDOperand ShufMask = N->getOperand(2);
2877 unsigned NumElts = ShufMask.getNumOperands();
2879 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2880 bool isIdentity = true;
2881 for (unsigned i = 0; i != NumElts; ++i) {
2882 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2883 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2888 if (isIdentity) return N->getOperand(0);
2890 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2892 for (unsigned i = 0; i != NumElts; ++i) {
2893 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2894 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2899 if (isIdentity) return N->getOperand(1);
2901 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
2903 bool isUnary = true;
2904 bool isSplat = true;
2906 unsigned BaseIdx = 0;
2907 for (unsigned i = 0; i != NumElts; ++i)
2908 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
2909 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
2910 int V = (Idx < NumElts) ? 0 : 1;
2924 SDOperand N0 = N->getOperand(0);
2925 SDOperand N1 = N->getOperand(1);
2926 // Normalize unary shuffle so the RHS is undef.
2927 if (isUnary && VecNum == 1)
2930 // If it is a splat, check if the argument vector is a build_vector with
2931 // all scalar elements the same.
2934 if (V->getOpcode() == ISD::BIT_CONVERT)
2935 V = V->getOperand(0).Val;
2936 if (V->getOpcode() == ISD::BUILD_VECTOR) {
2937 unsigned NumElems = V->getNumOperands()-2;
2938 if (NumElems > BaseIdx) {
2940 bool AllSame = true;
2941 for (unsigned i = 0; i != NumElems; ++i) {
2942 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
2943 Base = V->getOperand(i);
2947 // Splat of <u, u, u, u>, return <u, u, u, u>
2950 for (unsigned i = 0; i != NumElems; ++i) {
2951 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
2952 V->getOperand(i) != Base) {
2957 // Splat of <x, x, x, x>, return <x, x, x, x>
2964 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
2966 if (isUnary || N0 == N1) {
2967 if (N0.getOpcode() == ISD::UNDEF)
2968 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
2969 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
2971 SmallVector<SDOperand, 8> MappedOps;
2972 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
2973 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
2974 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
2975 MappedOps.push_back(ShufMask.getOperand(i));
2978 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
2979 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
2982 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
2983 &MappedOps[0], MappedOps.size());
2984 AddToWorkList(ShufMask.Val);
2985 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
2987 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
2994 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
2995 SDOperand ShufMask = N->getOperand(2);
2996 unsigned NumElts = ShufMask.getNumOperands()-2;
2998 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2999 bool isIdentity = true;
3000 for (unsigned i = 0; i != NumElts; ++i) {
3001 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3002 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3007 if (isIdentity) return N->getOperand(0);
3009 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3011 for (unsigned i = 0; i != NumElts; ++i) {
3012 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3013 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3018 if (isIdentity) return N->getOperand(1);
3020 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3022 bool isUnary = true;
3023 bool isSplat = true;
3025 unsigned BaseIdx = 0;
3026 for (unsigned i = 0; i != NumElts; ++i)
3027 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3028 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3029 int V = (Idx < NumElts) ? 0 : 1;
3043 SDOperand N0 = N->getOperand(0);
3044 SDOperand N1 = N->getOperand(1);
3045 // Normalize unary shuffle so the RHS is undef.
3046 if (isUnary && VecNum == 1)
3049 // If it is a splat, check if the argument vector is a build_vector with
3050 // all scalar elements the same.
3053 if (V->getOpcode() == ISD::VBIT_CONVERT)
3054 V = V->getOperand(0).Val;
3055 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3056 unsigned NumElems = V->getNumOperands()-2;
3057 if (NumElems > BaseIdx) {
3059 bool AllSame = true;
3060 for (unsigned i = 0; i != NumElems; ++i) {
3061 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3062 Base = V->getOperand(i);
3066 // Splat of <u, u, u, u>, return <u, u, u, u>
3069 for (unsigned i = 0; i != NumElems; ++i) {
3070 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3071 V->getOperand(i) != Base) {
3076 // Splat of <x, x, x, x>, return <x, x, x, x>
3083 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3085 if (isUnary || N0 == N1) {
3086 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3088 SmallVector<SDOperand, 8> MappedOps;
3089 for (unsigned i = 0; i != NumElts; ++i) {
3090 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3091 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3092 MappedOps.push_back(ShufMask.getOperand(i));
3095 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3096 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3099 // Add the type/#elts values.
3100 MappedOps.push_back(ShufMask.getOperand(NumElts));
3101 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3103 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3104 &MappedOps[0], MappedOps.size());
3105 AddToWorkList(ShufMask.Val);
3107 // Build the undef vector.
3108 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3109 for (unsigned i = 0; i != NumElts; ++i)
3110 MappedOps[i] = UDVal;
3111 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3112 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3113 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3114 &MappedOps[0], MappedOps.size());
3116 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3117 N0, UDVal, ShufMask,
3118 MappedOps[NumElts], MappedOps[NumElts+1]);
3124 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3125 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3126 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3127 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3128 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3129 SDOperand LHS = N->getOperand(0);
3130 SDOperand RHS = N->getOperand(1);
3131 if (N->getOpcode() == ISD::VAND) {
3132 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3133 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3134 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3135 RHS = RHS.getOperand(0);
3136 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3137 std::vector<SDOperand> IdxOps;
3138 unsigned NumOps = RHS.getNumOperands();
3139 unsigned NumElts = NumOps-2;
3140 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3141 for (unsigned i = 0; i != NumElts; ++i) {
3142 SDOperand Elt = RHS.getOperand(i);
3143 if (!isa<ConstantSDNode>(Elt))
3145 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3146 IdxOps.push_back(DAG.getConstant(i, EVT));
3147 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3148 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3153 // Let's see if the target supports this vector_shuffle.
3154 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3157 // Return the new VVECTOR_SHUFFLE node.
3158 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3159 SDOperand EVTNode = DAG.getValueType(EVT);
3160 std::vector<SDOperand> Ops;
3161 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3164 AddToWorkList(LHS.Val);
3165 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3166 ZeroOps.push_back(NumEltsNode);
3167 ZeroOps.push_back(EVTNode);
3168 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3169 &ZeroOps[0], ZeroOps.size()));
3170 IdxOps.push_back(NumEltsNode);
3171 IdxOps.push_back(EVTNode);
3172 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3173 &IdxOps[0], IdxOps.size()));
3174 Ops.push_back(NumEltsNode);
3175 Ops.push_back(EVTNode);
3176 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3177 &Ops[0], Ops.size());
3178 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3179 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3180 DstVecSize, DstVecEVT);
3188 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3189 /// the scalar operation of the vop if it is operating on an integer vector
3190 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3191 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3192 ISD::NodeType FPOp) {
3193 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3194 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3195 SDOperand LHS = N->getOperand(0);
3196 SDOperand RHS = N->getOperand(1);
3197 SDOperand Shuffle = XformToShuffleWithZero(N);
3198 if (Shuffle.Val) return Shuffle;
3200 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3202 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3203 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3204 SmallVector<SDOperand, 8> Ops;
3205 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3206 SDOperand LHSOp = LHS.getOperand(i);
3207 SDOperand RHSOp = RHS.getOperand(i);
3208 // If these two elements can't be folded, bail out.
3209 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3210 LHSOp.getOpcode() != ISD::Constant &&
3211 LHSOp.getOpcode() != ISD::ConstantFP) ||
3212 (RHSOp.getOpcode() != ISD::UNDEF &&
3213 RHSOp.getOpcode() != ISD::Constant &&
3214 RHSOp.getOpcode() != ISD::ConstantFP))
3216 // Can't fold divide by zero.
3217 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3218 if ((RHSOp.getOpcode() == ISD::Constant &&
3219 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3220 (RHSOp.getOpcode() == ISD::ConstantFP &&
3221 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3224 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3225 AddToWorkList(Ops.back().Val);
3226 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3227 Ops.back().getOpcode() == ISD::Constant ||
3228 Ops.back().getOpcode() == ISD::ConstantFP) &&
3229 "Scalar binop didn't fold!");
3232 if (Ops.size() == LHS.getNumOperands()-2) {
3233 Ops.push_back(*(LHS.Val->op_end()-2));
3234 Ops.push_back(*(LHS.Val->op_end()-1));
3235 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3242 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3243 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3245 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3246 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3247 // If we got a simplified select_cc node back from SimplifySelectCC, then
3248 // break it down into a new SETCC node, and a new SELECT node, and then return
3249 // the SELECT node, since we were called with a SELECT node.
3251 // Check to see if we got a select_cc back (to turn into setcc/select).
3252 // Otherwise, just return whatever node we got back, like fabs.
3253 if (SCC.getOpcode() == ISD::SELECT_CC) {
3254 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3255 SCC.getOperand(0), SCC.getOperand(1),
3257 AddToWorkList(SETCC.Val);
3258 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3259 SCC.getOperand(3), SETCC);
3266 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3267 /// are the two values being selected between, see if we can simplify the
3268 /// select. Callers of this should assume that TheSelect is deleted if this
3269 /// returns true. As such, they should return the appropriate thing (e.g. the
3270 /// node) back to the top-level of the DAG combiner loop to avoid it being
3273 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3276 // If this is a select from two identical things, try to pull the operation
3277 // through the select.
3278 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3279 // If this is a load and the token chain is identical, replace the select
3280 // of two loads with a load through a select of the address to load from.
3281 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3282 // constants have been dropped into the constant pool.
3283 if (LHS.getOpcode() == ISD::LOAD &&
3284 // Token chains must be identical.
3285 LHS.getOperand(0) == RHS.getOperand(0)) {
3286 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3287 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3289 // If this is an EXTLOAD, the VT's must match.
3290 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3291 // FIXME: this conflates two src values, discarding one. This is not
3292 // the right thing to do, but nothing uses srcvalues now. When they do,
3293 // turn SrcValue into a list of locations.
3295 if (TheSelect->getOpcode() == ISD::SELECT)
3296 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
3297 TheSelect->getOperand(0), LLD->getBasePtr(),
3300 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
3301 TheSelect->getOperand(0),
3302 TheSelect->getOperand(1),
3303 LLD->getBasePtr(), RLD->getBasePtr(),
3304 TheSelect->getOperand(4));
3307 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
3308 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
3309 Addr,LLD->getSrcValue(), LLD->getSrcValueOffset());
3311 Load = DAG.getExtLoad(LLD->getExtensionType(),
3312 TheSelect->getValueType(0),
3313 LLD->getChain(), Addr, LLD->getSrcValue(),
3314 LLD->getSrcValueOffset(),
3315 LLD->getLoadedVT());
3317 // Users of the select now use the result of the load.
3318 CombineTo(TheSelect, Load);
3320 // Users of the old loads now use the new load's chain. We know the
3321 // old-load value is dead now.
3322 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3323 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3332 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3333 SDOperand N2, SDOperand N3,
3336 MVT::ValueType VT = N2.getValueType();
3337 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3338 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3339 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3341 // Determine if the condition we're dealing with is constant
3342 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3343 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3345 // fold select_cc true, x, y -> x
3346 if (SCCC && SCCC->getValue())
3348 // fold select_cc false, x, y -> y
3349 if (SCCC && SCCC->getValue() == 0)
3352 // Check to see if we can simplify the select into an fabs node
3353 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3354 // Allow either -0.0 or 0.0
3355 if (CFP->getValue() == 0.0) {
3356 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3357 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3358 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3359 N2 == N3.getOperand(0))
3360 return DAG.getNode(ISD::FABS, VT, N0);
3362 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3363 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3364 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3365 N2.getOperand(0) == N3)
3366 return DAG.getNode(ISD::FABS, VT, N3);
3370 // Check to see if we can perform the "gzip trick", transforming
3371 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3372 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3373 MVT::isInteger(N0.getValueType()) &&
3374 MVT::isInteger(N2.getValueType()) &&
3375 (N1C->isNullValue() || // (a < 0) ? b : 0
3376 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3377 MVT::ValueType XType = N0.getValueType();
3378 MVT::ValueType AType = N2.getValueType();
3379 if (XType >= AType) {
3380 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3381 // single-bit constant.
3382 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3383 unsigned ShCtV = Log2_64(N2C->getValue());
3384 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3385 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3386 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3387 AddToWorkList(Shift.Val);
3388 if (XType > AType) {
3389 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3390 AddToWorkList(Shift.Val);
3392 return DAG.getNode(ISD::AND, AType, Shift, N2);
3394 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3395 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3396 TLI.getShiftAmountTy()));
3397 AddToWorkList(Shift.Val);
3398 if (XType > AType) {
3399 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3400 AddToWorkList(Shift.Val);
3402 return DAG.getNode(ISD::AND, AType, Shift, N2);
3406 // fold select C, 16, 0 -> shl C, 4
3407 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3408 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3409 // Get a SetCC of the condition
3410 // FIXME: Should probably make sure that setcc is legal if we ever have a
3411 // target where it isn't.
3412 SDOperand Temp, SCC;
3413 // cast from setcc result type to select result type
3414 if (AfterLegalize) {
3415 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3416 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3418 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3419 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3421 AddToWorkList(SCC.Val);
3422 AddToWorkList(Temp.Val);
3423 // shl setcc result by log2 n2c
3424 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3425 DAG.getConstant(Log2_64(N2C->getValue()),
3426 TLI.getShiftAmountTy()));
3429 // Check to see if this is the equivalent of setcc
3430 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3431 // otherwise, go ahead with the folds.
3432 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3433 MVT::ValueType XType = N0.getValueType();
3434 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3435 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3436 if (Res.getValueType() != VT)
3437 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3441 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3442 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3443 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3444 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3445 return DAG.getNode(ISD::SRL, XType, Ctlz,
3446 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3447 TLI.getShiftAmountTy()));
3449 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3450 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3451 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3453 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3454 DAG.getConstant(~0ULL, XType));
3455 return DAG.getNode(ISD::SRL, XType,
3456 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3457 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3458 TLI.getShiftAmountTy()));
3460 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3461 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3462 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3463 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3464 TLI.getShiftAmountTy()));
3465 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3469 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3470 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3471 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3472 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3473 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3474 MVT::ValueType XType = N0.getValueType();
3475 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3476 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3477 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3478 TLI.getShiftAmountTy()));
3479 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3480 AddToWorkList(Shift.Val);
3481 AddToWorkList(Add.Val);
3482 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3490 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3491 SDOperand N1, ISD::CondCode Cond,
3492 bool foldBooleans) {
3493 // These setcc operations always fold.
3497 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3499 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3502 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3503 uint64_t C1 = N1C->getValue();
3504 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
3505 uint64_t C0 = N0C->getValue();
3507 // Sign extend the operands if required
3508 if (ISD::isSignedIntSetCC(Cond)) {
3509 C0 = N0C->getSignExtended();
3510 C1 = N1C->getSignExtended();
3514 default: assert(0 && "Unknown integer setcc!");
3515 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3516 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3517 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
3518 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
3519 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
3520 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
3521 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
3522 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
3523 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
3524 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
3527 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3528 // equality comparison, then we're just comparing whether X itself is
3530 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
3531 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3532 N0.getOperand(1).getOpcode() == ISD::Constant) {
3533 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
3534 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3535 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
3536 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3537 // (srl (ctlz x), 5) == 0 -> X != 0
3538 // (srl (ctlz x), 5) != 1 -> X != 0
3541 // (srl (ctlz x), 5) != 0 -> X == 0
3542 // (srl (ctlz x), 5) == 1 -> X == 0
3545 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
3546 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
3551 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3552 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3553 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3555 // If the comparison constant has bits in the upper part, the
3556 // zero-extended value could never match.
3557 if (C1 & (~0ULL << InSize)) {
3558 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3562 case ISD::SETEQ: return DAG.getConstant(0, VT);
3565 case ISD::SETNE: return DAG.getConstant(1, VT);
3568 // True if the sign bit of C1 is set.
3569 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3572 // True if the sign bit of C1 isn't set.
3573 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3579 // Otherwise, we can perform the comparison with the low bits.
3587 return DAG.getSetCC(VT, N0.getOperand(0),
3588 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3591 break; // todo, be more careful with signed comparisons
3593 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3594 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3595 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3596 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3597 MVT::ValueType ExtDstTy = N0.getValueType();
3598 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3600 // If the extended part has any inconsistent bits, it cannot ever
3601 // compare equal. In other words, they have to be all ones or all
3604 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3605 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3606 return DAG.getConstant(Cond == ISD::SETNE, VT);
3609 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3610 if (Op0Ty == ExtSrcTy) {
3611 ZextOp = N0.getOperand(0);
3613 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3614 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3615 DAG.getConstant(Imm, Op0Ty));
3617 AddToWorkList(ZextOp.Val);
3618 // Otherwise, make this a use of a zext.
3619 return DAG.getSetCC(VT, ZextOp,
3620 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3623 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3624 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3625 (N0.getOpcode() == ISD::XOR ||
3626 (N0.getOpcode() == ISD::AND &&
3627 N0.getOperand(0).getOpcode() == ISD::XOR &&
3628 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3629 isa<ConstantSDNode>(N0.getOperand(1)) &&
3630 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3631 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
3632 // only do this if the top bits are known zero.
3633 if (TLI.MaskedValueIsZero(N1,
3634 MVT::getIntVTBitMask(N0.getValueType())-1)) {
3635 // Okay, get the un-inverted input value.
3637 if (N0.getOpcode() == ISD::XOR)
3638 Val = N0.getOperand(0);
3640 assert(N0.getOpcode() == ISD::AND &&
3641 N0.getOperand(0).getOpcode() == ISD::XOR);
3642 // ((X^1)&1)^1 -> X & 1
3643 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3644 N0.getOperand(0).getOperand(0), N0.getOperand(1));
3646 return DAG.getSetCC(VT, Val, N1,
3647 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3651 uint64_t MinVal, MaxVal;
3652 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3653 if (ISD::isSignedIntSetCC(Cond)) {
3654 MinVal = 1ULL << (OperandBitSize-1);
3655 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3656 MaxVal = ~0ULL >> (65-OperandBitSize);
3661 MaxVal = ~0ULL >> (64-OperandBitSize);
3664 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3665 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3666 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
3667 --C1; // X >= C0 --> X > (C0-1)
3668 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3669 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
3672 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3673 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
3674 ++C1; // X <= C0 --> X < (C0+1)
3675 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3676 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
3679 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
3680 return DAG.getConstant(0, VT); // X < MIN --> false
3682 // Canonicalize setgt X, Min --> setne X, Min
3683 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
3684 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3685 // Canonicalize setlt X, Max --> setne X, Max
3686 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
3687 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3689 // If we have setult X, 1, turn it into seteq X, 0
3690 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
3691 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
3693 // If we have setugt X, Max-1, turn it into seteq X, Max
3694 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
3695 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
3698 // If we have "setcc X, C0", check to see if we can shrink the immediate
3701 // SETUGT X, SINTMAX -> SETLT X, 0
3702 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
3703 C1 == (~0ULL >> (65-OperandBitSize)))
3704 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
3707 // FIXME: Implement the rest of these.
3709 // Fold bit comparisons when we can.
3710 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3711 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
3712 if (ConstantSDNode *AndRHS =
3713 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3714 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3715 // Perform the xform if the AND RHS is a single bit.
3716 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
3717 return DAG.getNode(ISD::SRL, VT, N0,
3718 DAG.getConstant(Log2_64(AndRHS->getValue()),
3719 TLI.getShiftAmountTy()));
3721 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
3722 // (X & 8) == 8 --> (X & 8) >> 3
3723 // Perform the xform if C1 is a single bit.
3724 if ((C1 & (C1-1)) == 0) {
3725 return DAG.getNode(ISD::SRL, VT, N0,
3726 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
3731 } else if (isa<ConstantSDNode>(N0.Val)) {
3732 // Ensure that the constant occurs on the RHS.
3733 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3736 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
3737 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
3738 double C0 = N0C->getValue(), C1 = N1C->getValue();
3741 default: break; // FIXME: Implement the rest of these!
3742 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3743 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3744 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
3745 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
3746 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
3747 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
3750 // Ensure that the constant occurs on the RHS.
3751 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3755 // We can always fold X == Y for integer setcc's.
3756 if (MVT::isInteger(N0.getValueType()))
3757 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3758 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3759 if (UOF == 2) // FP operators that are undefined on NaNs.
3760 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3761 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
3762 return DAG.getConstant(UOF, VT);
3763 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3764 // if it is not already.
3765 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3766 if (NewCond != Cond)
3767 return DAG.getSetCC(VT, N0, N1, NewCond);
3770 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3771 MVT::isInteger(N0.getValueType())) {
3772 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3773 N0.getOpcode() == ISD::XOR) {
3774 // Simplify (X+Y) == (X+Z) --> Y == Z
3775 if (N0.getOpcode() == N1.getOpcode()) {
3776 if (N0.getOperand(0) == N1.getOperand(0))
3777 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
3778 if (N0.getOperand(1) == N1.getOperand(1))
3779 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
3780 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
3781 // If X op Y == Y op X, try other combinations.
3782 if (N0.getOperand(0) == N1.getOperand(1))
3783 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
3784 if (N0.getOperand(1) == N1.getOperand(0))
3785 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
3789 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3790 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3791 // Turn (X+C1) == C2 --> X == C2-C1
3792 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
3793 return DAG.getSetCC(VT, N0.getOperand(0),
3794 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
3795 N0.getValueType()), Cond);
3798 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3799 if (N0.getOpcode() == ISD::XOR)
3800 // If we know that all of the inverted bits are zero, don't bother
3801 // performing the inversion.
3802 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
3803 return DAG.getSetCC(VT, N0.getOperand(0),
3804 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
3805 N0.getValueType()), Cond);
3808 // Turn (C1-X) == C2 --> X == C1-C2
3809 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3810 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
3811 return DAG.getSetCC(VT, N0.getOperand(1),
3812 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
3813 N0.getValueType()), Cond);
3818 // Simplify (X+Z) == X --> Z == 0
3819 if (N0.getOperand(0) == N1)
3820 return DAG.getSetCC(VT, N0.getOperand(1),
3821 DAG.getConstant(0, N0.getValueType()), Cond);
3822 if (N0.getOperand(1) == N1) {
3823 if (DAG.isCommutativeBinOp(N0.getOpcode()))
3824 return DAG.getSetCC(VT, N0.getOperand(0),
3825 DAG.getConstant(0, N0.getValueType()), Cond);
3827 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
3828 // (Z-X) == X --> Z == X<<1
3829 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
3831 DAG.getConstant(1,TLI.getShiftAmountTy()));
3832 AddToWorkList(SH.Val);
3833 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
3838 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3839 N1.getOpcode() == ISD::XOR) {
3840 // Simplify X == (X+Z) --> Z == 0
3841 if (N1.getOperand(0) == N0) {
3842 return DAG.getSetCC(VT, N1.getOperand(1),
3843 DAG.getConstant(0, N1.getValueType()), Cond);
3844 } else if (N1.getOperand(1) == N0) {
3845 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
3846 return DAG.getSetCC(VT, N1.getOperand(0),
3847 DAG.getConstant(0, N1.getValueType()), Cond);
3849 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
3850 // X == (Z-X) --> X<<1 == Z
3851 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
3852 DAG.getConstant(1,TLI.getShiftAmountTy()));
3853 AddToWorkList(SH.Val);
3854 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
3860 // Fold away ALL boolean setcc's.
3862 if (N0.getValueType() == MVT::i1 && foldBooleans) {
3864 default: assert(0 && "Unknown integer setcc!");
3865 case ISD::SETEQ: // X == Y -> (X^Y)^1
3866 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3867 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
3868 AddToWorkList(Temp.Val);
3870 case ISD::SETNE: // X != Y --> (X^Y)
3871 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3873 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
3874 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
3875 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3876 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
3877 AddToWorkList(Temp.Val);
3879 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
3880 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
3881 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3882 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
3883 AddToWorkList(Temp.Val);
3885 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
3886 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
3887 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3888 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
3889 AddToWorkList(Temp.Val);
3891 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
3892 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
3893 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3894 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
3897 if (VT != MVT::i1) {
3898 AddToWorkList(N0.Val);
3899 // FIXME: If running after legalize, we probably can't do this.
3900 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
3905 // Could not fold it.
3909 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3910 /// return a DAG expression to select that will generate the same value by
3911 /// multiplying by a magic number. See:
3912 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3913 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
3914 std::vector<SDNode*> Built;
3915 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
3917 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3923 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3924 /// return a DAG expression to select that will generate the same value by
3925 /// multiplying by a magic number. See:
3926 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3927 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
3928 std::vector<SDNode*> Built;
3929 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
3931 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3937 /// FindBaseOffset - Return true if base is known not to alias with anything
3938 /// but itself. Provides base object and offset as results.
3939 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
3940 // Assume it is a primitive operation.
3941 Base = Ptr; Offset = 0;
3943 // If it's an adding a simple constant then integrate the offset.
3944 if (Base.getOpcode() == ISD::ADD) {
3945 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
3946 Base = Base.getOperand(0);
3947 Offset += C->getValue();
3951 // If it's any of the following then it can't alias with anything but itself.
3952 return isa<FrameIndexSDNode>(Base) ||
3953 isa<ConstantPoolSDNode>(Base) ||
3954 isa<GlobalAddressSDNode>(Base);
3957 /// isAlias - Return true if there is any possibility that the two addresses
3959 static bool isAlias(SDOperand Ptr1, int64_t Size1, const Value *SrcValue1,
3960 SDOperand Ptr2, int64_t Size2, const Value *SrcValue2) {
3961 // If they are the same then they must be aliases.
3962 if (Ptr1 == Ptr2) return true;
3964 // Gather base node and offset information.
3965 SDOperand Base1, Base2;
3966 int64_t Offset1, Offset2;
3967 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
3968 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
3970 // If they have a same base address then...
3971 if (Base1 == Base2) {
3972 // Check to see if the addresses overlap.
3973 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
3976 // Otherwise they alias if either is unknown.
3977 return !KnownBase1 || !KnownBase2;
3980 /// FindAliasInfo - Extracts the relevant alias information from the memory
3981 /// node. Returns true if the operand was a load.
3982 bool DAGCombiner::FindAliasInfo(SDNode *N,
3983 SDOperand &Ptr, int64_t &Size, const Value *&SrcValue) {
3984 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3985 Ptr = LD->getBasePtr();
3986 Size = MVT::getSizeInBits(N->getValueType(0)) >> 3;
3987 SrcValue = LD->getSrcValue();
3989 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3990 #if 1 //FIXME - Switch over after StoreSDNode comes online.
3991 Ptr = ST->getOperand(2);
3992 Size = MVT::getSizeInBits(ST->getOperand(1).getValueType()) >> 3;
3995 Ptr = ST->getBasePtr();
3996 Size = MVT::getSizeInBits(ST->getOperand(1).getValueType()) >> 3;
3997 SrcValue = ST->getSrcValue();
4000 assert(0 && "FindAliasInfo expected a memory operand");
4006 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4007 /// looking for aliasing nodes and adding them to the Aliases vector.
4008 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4009 SmallVector<SDOperand, 8> &Aliases) {
4010 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4011 std::set<SDNode *> Visited; // Visited node set.
4013 // Get alias information for node.
4016 const Value *SrcValue;
4017 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue);
4020 Chains.push_back(OriginalChain);
4022 // Look at each chain and determine if it is an alias. If so, add it to the
4023 // aliases list. If not, then continue up the chain looking for the next
4025 while (!Chains.empty()) {
4026 SDOperand Chain = Chains.back();
4029 // Don't bother if we've been before.
4030 if (Visited.find(Chain.Val) != Visited.end()) continue;
4031 Visited.insert(Chain.Val);
4033 switch (Chain.getOpcode()) {
4034 case ISD::EntryToken:
4035 // Entry token is ideal chain operand, but handled in FindBetterChain.
4039 if (!ISD::isNON_EXTLoad(N)) {
4040 Aliases.push_back(Chain);
4045 // Get alias information for Chain.
4048 const Value *OpSrcValue;
4049 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, OpSrcValue);
4051 // If chain is alias then stop here.
4052 if (!(IsLoad && IsOpLoad) &&
4053 isAlias(Ptr, Size, SrcValue, OpPtr, OpSize, OpSrcValue)) {
4054 Aliases.push_back(Chain);
4056 // Look further up the chain.
4057 Chains.push_back(Chain.getOperand(0));
4058 // Clean up old chain.
4059 AddToWorkList(Chain.Val);
4064 case ISD::TokenFactor:
4065 // We have to check each of the operands of the token factor, so we queue
4066 // then up. Adding the operands to the queue (stack) in reverse order
4067 // maintains the original order and increases the likelihood that getNode
4068 // will find a matching token factor (CSE.)
4069 for (unsigned n = Chain.getNumOperands(); n;)
4070 Chains.push_back(Chain.getOperand(--n));
4071 // Eliminate the token factor if we can.
4072 AddToWorkList(Chain.Val);
4076 // For all other instructions we will just have to take what we can get.
4077 Aliases.push_back(Chain);
4083 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4084 /// for a better chain (aliasing node.)
4085 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4086 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4088 // Accumulate all the aliases to this node.
4089 GatherAllAliases(N, OldChain, Aliases);
4091 if (Aliases.size() == 0) {
4092 // If no operands then chain to entry token.
4093 return DAG.getEntryNode();
4094 } else if (Aliases.size() == 1) {
4095 // If a single operand then chain to it. We don't need to revisit it.
4099 // Construct a custom tailored token factor.
4100 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4101 &Aliases[0], Aliases.size());
4103 // Make sure the old chain gets cleaned up.
4104 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4109 // SelectionDAG::Combine - This is the entry point for the file.
4111 void SelectionDAG::Combine(bool RunningAfterLegalize) {
4112 /// run - This is the main entry point to this class.
4114 DAGCombiner(*this).Run(RunningAfterLegalize);