1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: make truncate see through SIGN_EXTEND and AND
26 // FIXME: divide by zero is currently left unfolded. do we want to turn this
28 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "dagcombine"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
44 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
51 // Worklist of all of the nodes that need to be simplified.
52 std::vector<SDNode*> WorkList;
54 /// AddUsersToWorkList - When an instruction is simplified, add all users of
55 /// the instruction to the work lists because they might get more simplified
58 void AddUsersToWorkList(SDNode *N) {
59 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
61 WorkList.push_back(*UI);
64 /// removeFromWorkList - remove all instances of N from the worklist.
66 void removeFromWorkList(SDNode *N) {
67 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
72 void AddToWorkList(SDNode *N) {
73 WorkList.push_back(N);
76 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
78 DEBUG(std::cerr << "\nReplacing "; N->dump();
79 std::cerr << "\nWith: "; To[0].Val->dump();
80 std::cerr << " and " << To.size()-1 << " other values\n");
81 std::vector<SDNode*> NowDead;
82 DAG.ReplaceAllUsesWith(N, To, &NowDead);
84 // Push the new nodes and any users onto the worklist
85 for (unsigned i = 0, e = To.size(); i != e; ++i) {
86 WorkList.push_back(To[i].Val);
87 AddUsersToWorkList(To[i].Val);
90 // Nodes can end up on the worklist more than once. Make sure we do
91 // not process a node that has been replaced.
92 removeFromWorkList(N);
93 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
94 removeFromWorkList(NowDead[i]);
96 // Finally, since the node is now dead, remove it from the graph.
98 return SDOperand(N, 0);
101 SDOperand CombineTo(SDNode *N, SDOperand Res) {
102 std::vector<SDOperand> To;
104 return CombineTo(N, To);
107 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
108 std::vector<SDOperand> To;
111 return CombineTo(N, To);
115 /// SimplifyDemandedBits - Check the specified integer node value to see if
116 /// it can be simplified or if things it uses can be simplified by bit
117 /// propagation. If so, return true.
118 bool SimplifyDemandedBits(SDOperand Op) {
119 TargetLowering::TargetLoweringOpt TLO(DAG);
120 uint64_t KnownZero, KnownOne;
121 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
122 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
126 WorkList.push_back(Op.Val);
128 // Replace the old value with the new one.
130 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump();
131 std::cerr << "\nWith: "; TLO.New.Val->dump());
133 std::vector<SDNode*> NowDead;
134 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
136 // Push the new node and any (possibly new) users onto the worklist.
137 WorkList.push_back(TLO.New.Val);
138 AddUsersToWorkList(TLO.New.Val);
140 // Nodes can end up on the worklist more than once. Make sure we do
141 // not process a node that has been replaced.
142 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
143 removeFromWorkList(NowDead[i]);
145 // Finally, if the node is now dead, remove it from the graph. The node
146 // may not be dead if the replacement process recursively simplified to
147 // something else needing this node.
148 if (TLO.Old.Val->use_empty()) {
149 removeFromWorkList(TLO.Old.Val);
150 DAG.DeleteNode(TLO.Old.Val);
155 /// visit - call the node-specific routine that knows how to fold each
156 /// particular type of node.
157 SDOperand visit(SDNode *N);
159 // Visitation implementation - Implement dag node combining for different
160 // node types. The semantics are as follows:
162 // SDOperand.Val == 0 - No change was made
163 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
164 // otherwise - N should be replaced by the returned Operand.
166 SDOperand visitTokenFactor(SDNode *N);
167 SDOperand visitADD(SDNode *N);
168 SDOperand visitSUB(SDNode *N);
169 SDOperand visitMUL(SDNode *N);
170 SDOperand visitSDIV(SDNode *N);
171 SDOperand visitUDIV(SDNode *N);
172 SDOperand visitSREM(SDNode *N);
173 SDOperand visitUREM(SDNode *N);
174 SDOperand visitMULHU(SDNode *N);
175 SDOperand visitMULHS(SDNode *N);
176 SDOperand visitAND(SDNode *N);
177 SDOperand visitOR(SDNode *N);
178 SDOperand visitXOR(SDNode *N);
179 SDOperand visitSHL(SDNode *N);
180 SDOperand visitSRA(SDNode *N);
181 SDOperand visitSRL(SDNode *N);
182 SDOperand visitCTLZ(SDNode *N);
183 SDOperand visitCTTZ(SDNode *N);
184 SDOperand visitCTPOP(SDNode *N);
185 SDOperand visitSELECT(SDNode *N);
186 SDOperand visitSELECT_CC(SDNode *N);
187 SDOperand visitSETCC(SDNode *N);
188 SDOperand visitSIGN_EXTEND(SDNode *N);
189 SDOperand visitZERO_EXTEND(SDNode *N);
190 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
191 SDOperand visitTRUNCATE(SDNode *N);
192 SDOperand visitBIT_CONVERT(SDNode *N);
193 SDOperand visitFADD(SDNode *N);
194 SDOperand visitFSUB(SDNode *N);
195 SDOperand visitFMUL(SDNode *N);
196 SDOperand visitFDIV(SDNode *N);
197 SDOperand visitFREM(SDNode *N);
198 SDOperand visitFCOPYSIGN(SDNode *N);
199 SDOperand visitSINT_TO_FP(SDNode *N);
200 SDOperand visitUINT_TO_FP(SDNode *N);
201 SDOperand visitFP_TO_SINT(SDNode *N);
202 SDOperand visitFP_TO_UINT(SDNode *N);
203 SDOperand visitFP_ROUND(SDNode *N);
204 SDOperand visitFP_ROUND_INREG(SDNode *N);
205 SDOperand visitFP_EXTEND(SDNode *N);
206 SDOperand visitFNEG(SDNode *N);
207 SDOperand visitFABS(SDNode *N);
208 SDOperand visitBRCOND(SDNode *N);
209 SDOperand visitBR_CC(SDNode *N);
210 SDOperand visitLOAD(SDNode *N);
211 SDOperand visitSTORE(SDNode *N);
213 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
215 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
216 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
217 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
218 SDOperand N3, ISD::CondCode CC);
219 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
220 ISD::CondCode Cond, bool foldBooleans = true);
222 SDOperand BuildSDIV(SDNode *N);
223 SDOperand BuildUDIV(SDNode *N);
225 DAGCombiner(SelectionDAG &D)
226 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
228 /// Run - runs the dag combiner on all nodes in the work list
229 void Run(bool RunningAfterLegalize);
233 //===----------------------------------------------------------------------===//
234 // TargetLowering::DAGCombinerInfo implementation
235 //===----------------------------------------------------------------------===//
237 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
238 ((DAGCombiner*)DC)->AddToWorkList(N);
241 SDOperand TargetLowering::DAGCombinerInfo::
242 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
243 return ((DAGCombiner*)DC)->CombineTo(N, To);
246 SDOperand TargetLowering::DAGCombinerInfo::
247 CombineTo(SDNode *N, SDOperand Res) {
248 return ((DAGCombiner*)DC)->CombineTo(N, Res);
252 SDOperand TargetLowering::DAGCombinerInfo::
253 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
254 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
260 //===----------------------------------------------------------------------===//
264 int64_t m; // magic number
265 int64_t s; // shift amount
269 uint64_t m; // magic number
270 int64_t a; // add indicator
271 int64_t s; // shift amount
274 /// magic - calculate the magic numbers required to codegen an integer sdiv as
275 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
277 static ms magic32(int32_t d) {
279 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
280 const uint32_t two31 = 0x80000000U;
284 t = two31 + ((uint32_t)d >> 31);
285 anc = t - 1 - t%ad; // absolute value of nc
286 p = 31; // initialize p
287 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
288 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
289 q2 = two31/ad; // initialize q2 = 2p/abs(d)
290 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
293 q1 = 2*q1; // update q1 = 2p/abs(nc)
294 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
295 if (r1 >= anc) { // must be unsigned comparison
299 q2 = 2*q2; // update q2 = 2p/abs(d)
300 r2 = 2*r2; // update r2 = rem(2p/abs(d))
301 if (r2 >= ad) { // must be unsigned comparison
306 } while (q1 < delta || (q1 == delta && r1 == 0));
308 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
309 if (d < 0) mag.m = -mag.m; // resulting magic number
310 mag.s = p - 32; // resulting shift
314 /// magicu - calculate the magic numbers required to codegen an integer udiv as
315 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
316 static mu magicu32(uint32_t d) {
318 uint32_t nc, delta, q1, r1, q2, r2;
320 magu.a = 0; // initialize "add" indicator
322 p = 31; // initialize p
323 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
324 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
325 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
326 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
329 if (r1 >= nc - r1 ) {
330 q1 = 2*q1 + 1; // update q1
331 r1 = 2*r1 - nc; // update r1
334 q1 = 2*q1; // update q1
335 r1 = 2*r1; // update r1
337 if (r2 + 1 >= d - r2) {
338 if (q2 >= 0x7FFFFFFF) magu.a = 1;
339 q2 = 2*q2 + 1; // update q2
340 r2 = 2*r2 + 1 - d; // update r2
343 if (q2 >= 0x80000000) magu.a = 1;
344 q2 = 2*q2; // update q2
345 r2 = 2*r2 + 1; // update r2
348 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
349 magu.m = q2 + 1; // resulting magic number
350 magu.s = p - 32; // resulting shift
354 /// magic - calculate the magic numbers required to codegen an integer sdiv as
355 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
357 static ms magic64(int64_t d) {
359 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
360 const uint64_t two63 = 9223372036854775808ULL; // 2^63
363 ad = d >= 0 ? d : -d;
364 t = two63 + ((uint64_t)d >> 63);
365 anc = t - 1 - t%ad; // absolute value of nc
366 p = 63; // initialize p
367 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
368 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
369 q2 = two63/ad; // initialize q2 = 2p/abs(d)
370 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
373 q1 = 2*q1; // update q1 = 2p/abs(nc)
374 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
375 if (r1 >= anc) { // must be unsigned comparison
379 q2 = 2*q2; // update q2 = 2p/abs(d)
380 r2 = 2*r2; // update r2 = rem(2p/abs(d))
381 if (r2 >= ad) { // must be unsigned comparison
386 } while (q1 < delta || (q1 == delta && r1 == 0));
389 if (d < 0) mag.m = -mag.m; // resulting magic number
390 mag.s = p - 64; // resulting shift
394 /// magicu - calculate the magic numbers required to codegen an integer udiv as
395 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
396 static mu magicu64(uint64_t d)
399 uint64_t nc, delta, q1, r1, q2, r2;
401 magu.a = 0; // initialize "add" indicator
403 p = 63; // initialize p
404 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
405 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
406 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
407 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
410 if (r1 >= nc - r1 ) {
411 q1 = 2*q1 + 1; // update q1
412 r1 = 2*r1 - nc; // update r1
415 q1 = 2*q1; // update q1
416 r1 = 2*r1; // update r1
418 if (r2 + 1 >= d - r2) {
419 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
420 q2 = 2*q2 + 1; // update q2
421 r2 = 2*r2 + 1 - d; // update r2
424 if (q2 >= 0x8000000000000000ull) magu.a = 1;
425 q2 = 2*q2; // update q2
426 r2 = 2*r2 + 1; // update r2
429 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
430 magu.m = q2 + 1; // resulting magic number
431 magu.s = p - 64; // resulting shift
435 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
436 // that selects between the values 1 and 0, making it equivalent to a setcc.
437 // Also, set the incoming LHS, RHS, and CC references to the appropriate
438 // nodes based on the type of node we are checking. This simplifies life a
439 // bit for the callers.
440 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
442 if (N.getOpcode() == ISD::SETCC) {
443 LHS = N.getOperand(0);
444 RHS = N.getOperand(1);
445 CC = N.getOperand(2);
448 if (N.getOpcode() == ISD::SELECT_CC &&
449 N.getOperand(2).getOpcode() == ISD::Constant &&
450 N.getOperand(3).getOpcode() == ISD::Constant &&
451 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
452 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
453 LHS = N.getOperand(0);
454 RHS = N.getOperand(1);
455 CC = N.getOperand(4);
461 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
462 // one use. If this is true, it allows the users to invert the operation for
463 // free when it is profitable to do so.
464 static bool isOneUseSetCC(SDOperand N) {
465 SDOperand N0, N1, N2;
466 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
471 // FIXME: This should probably go in the ISD class rather than being duplicated
473 static bool isCommutativeBinOp(unsigned Opcode) {
479 case ISD::XOR: return true;
480 default: return false; // FIXME: Need commutative info for user ops!
484 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
485 MVT::ValueType VT = N0.getValueType();
486 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
487 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
488 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
489 if (isa<ConstantSDNode>(N1)) {
490 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
491 AddToWorkList(OpNode.Val);
492 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
493 } else if (N0.hasOneUse()) {
494 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
495 AddToWorkList(OpNode.Val);
496 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
499 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
500 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
501 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
502 if (isa<ConstantSDNode>(N0)) {
503 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
504 AddToWorkList(OpNode.Val);
505 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
506 } else if (N1.hasOneUse()) {
507 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
508 AddToWorkList(OpNode.Val);
509 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
515 void DAGCombiner::Run(bool RunningAfterLegalize) {
516 // set the instance variable, so that the various visit routines may use it.
517 AfterLegalize = RunningAfterLegalize;
519 // Add all the dag nodes to the worklist.
520 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
521 E = DAG.allnodes_end(); I != E; ++I)
522 WorkList.push_back(I);
524 // Create a dummy node (which is not added to allnodes), that adds a reference
525 // to the root node, preventing it from being deleted, and tracking any
526 // changes of the root.
527 HandleSDNode Dummy(DAG.getRoot());
530 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
531 TargetLowering::DAGCombinerInfo
532 DagCombineInfo(DAG, !RunningAfterLegalize, this);
534 // while the worklist isn't empty, inspect the node on the end of it and
535 // try and combine it.
536 while (!WorkList.empty()) {
537 SDNode *N = WorkList.back();
540 // If N has no uses, it is dead. Make sure to revisit all N's operands once
541 // N is deleted from the DAG, since they too may now be dead or may have a
542 // reduced number of uses, allowing other xforms.
543 if (N->use_empty() && N != &Dummy) {
544 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
545 WorkList.push_back(N->getOperand(i).Val);
547 removeFromWorkList(N);
552 SDOperand RV = visit(N);
554 // If nothing happened, try a target-specific DAG combine.
556 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
557 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
558 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
563 // If we get back the same node we passed in, rather than a new node or
564 // zero, we know that the node must have defined multiple values and
565 // CombineTo was used. Since CombineTo takes care of the worklist
566 // mechanics for us, we have no work to do in this case.
568 DEBUG(std::cerr << "\nReplacing "; N->dump();
569 std::cerr << "\nWith: "; RV.Val->dump();
571 std::vector<SDNode*> NowDead;
572 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
574 // Push the new node and any users onto the worklist
575 WorkList.push_back(RV.Val);
576 AddUsersToWorkList(RV.Val);
578 // Nodes can end up on the worklist more than once. Make sure we do
579 // not process a node that has been replaced.
580 removeFromWorkList(N);
581 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
582 removeFromWorkList(NowDead[i]);
584 // Finally, since the node is now dead, remove it from the graph.
590 // If the root changed (e.g. it was a dead load, update the root).
591 DAG.setRoot(Dummy.getValue());
594 SDOperand DAGCombiner::visit(SDNode *N) {
595 switch(N->getOpcode()) {
597 case ISD::TokenFactor: return visitTokenFactor(N);
598 case ISD::ADD: return visitADD(N);
599 case ISD::SUB: return visitSUB(N);
600 case ISD::MUL: return visitMUL(N);
601 case ISD::SDIV: return visitSDIV(N);
602 case ISD::UDIV: return visitUDIV(N);
603 case ISD::SREM: return visitSREM(N);
604 case ISD::UREM: return visitUREM(N);
605 case ISD::MULHU: return visitMULHU(N);
606 case ISD::MULHS: return visitMULHS(N);
607 case ISD::AND: return visitAND(N);
608 case ISD::OR: return visitOR(N);
609 case ISD::XOR: return visitXOR(N);
610 case ISD::SHL: return visitSHL(N);
611 case ISD::SRA: return visitSRA(N);
612 case ISD::SRL: return visitSRL(N);
613 case ISD::CTLZ: return visitCTLZ(N);
614 case ISD::CTTZ: return visitCTTZ(N);
615 case ISD::CTPOP: return visitCTPOP(N);
616 case ISD::SELECT: return visitSELECT(N);
617 case ISD::SELECT_CC: return visitSELECT_CC(N);
618 case ISD::SETCC: return visitSETCC(N);
619 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
620 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
621 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
622 case ISD::TRUNCATE: return visitTRUNCATE(N);
623 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
624 case ISD::FADD: return visitFADD(N);
625 case ISD::FSUB: return visitFSUB(N);
626 case ISD::FMUL: return visitFMUL(N);
627 case ISD::FDIV: return visitFDIV(N);
628 case ISD::FREM: return visitFREM(N);
629 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
630 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
631 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
632 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
633 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
634 case ISD::FP_ROUND: return visitFP_ROUND(N);
635 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
636 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
637 case ISD::FNEG: return visitFNEG(N);
638 case ISD::FABS: return visitFABS(N);
639 case ISD::BRCOND: return visitBRCOND(N);
640 case ISD::BR_CC: return visitBR_CC(N);
641 case ISD::LOAD: return visitLOAD(N);
642 case ISD::STORE: return visitSTORE(N);
647 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
648 std::vector<SDOperand> Ops;
649 bool Changed = false;
651 // If the token factor has two operands and one is the entry token, replace
652 // the token factor with the other operand.
653 if (N->getNumOperands() == 2) {
654 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
655 return N->getOperand(1);
656 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
657 return N->getOperand(0);
660 // fold (tokenfactor (tokenfactor)) -> tokenfactor
661 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
662 SDOperand Op = N->getOperand(i);
663 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
664 AddToWorkList(Op.Val); // Remove dead node.
666 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
667 Ops.push_back(Op.getOperand(j));
673 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
677 SDOperand DAGCombiner::visitADD(SDNode *N) {
678 SDOperand N0 = N->getOperand(0);
679 SDOperand N1 = N->getOperand(1);
680 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
681 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
682 MVT::ValueType VT = N0.getValueType();
684 // fold (add c1, c2) -> c1+c2
686 return DAG.getNode(ISD::ADD, VT, N0, N1);
687 // canonicalize constant to RHS
689 return DAG.getNode(ISD::ADD, VT, N1, N0);
690 // fold (add x, 0) -> x
691 if (N1C && N1C->isNullValue())
693 // fold ((c1-A)+c2) -> (c1+c2)-A
694 if (N1C && N0.getOpcode() == ISD::SUB)
695 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
696 return DAG.getNode(ISD::SUB, VT,
697 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
700 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
703 // fold ((0-A) + B) -> B-A
704 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
705 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
706 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
707 // fold (A + (0-B)) -> A-B
708 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
709 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
710 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
711 // fold (A+(B-A)) -> B
712 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
713 return N1.getOperand(0);
715 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
718 // fold (a+b) -> (a|b) iff a and b share no bits.
719 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
720 uint64_t LHSZero, LHSOne;
721 uint64_t RHSZero, RHSOne;
722 uint64_t Mask = MVT::getIntVTBitMask(VT);
723 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
725 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
727 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
728 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
729 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
730 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
731 return DAG.getNode(ISD::OR, VT, N0, N1);
738 SDOperand DAGCombiner::visitSUB(SDNode *N) {
739 SDOperand N0 = N->getOperand(0);
740 SDOperand N1 = N->getOperand(1);
741 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
742 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
743 MVT::ValueType VT = N0.getValueType();
745 // fold (sub x, x) -> 0
747 return DAG.getConstant(0, N->getValueType(0));
748 // fold (sub c1, c2) -> c1-c2
750 return DAG.getNode(ISD::SUB, VT, N0, N1);
751 // fold (sub x, c) -> (add x, -c)
753 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
755 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
756 return N0.getOperand(1);
758 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
759 return N0.getOperand(0);
763 SDOperand DAGCombiner::visitMUL(SDNode *N) {
764 SDOperand N0 = N->getOperand(0);
765 SDOperand N1 = N->getOperand(1);
766 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
767 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
768 MVT::ValueType VT = N0.getValueType();
770 // fold (mul c1, c2) -> c1*c2
772 return DAG.getNode(ISD::MUL, VT, N0, N1);
773 // canonicalize constant to RHS
775 return DAG.getNode(ISD::MUL, VT, N1, N0);
776 // fold (mul x, 0) -> 0
777 if (N1C && N1C->isNullValue())
779 // fold (mul x, -1) -> 0-x
780 if (N1C && N1C->isAllOnesValue())
781 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
782 // fold (mul x, (1 << c)) -> x << c
783 if (N1C && isPowerOf2_64(N1C->getValue()))
784 return DAG.getNode(ISD::SHL, VT, N0,
785 DAG.getConstant(Log2_64(N1C->getValue()),
786 TLI.getShiftAmountTy()));
787 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
788 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
789 // FIXME: If the input is something that is easily negated (e.g. a
790 // single-use add), we should put the negate there.
791 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
792 DAG.getNode(ISD::SHL, VT, N0,
793 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
794 TLI.getShiftAmountTy())));
797 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
798 if (N1C && N0.getOpcode() == ISD::SHL &&
799 isa<ConstantSDNode>(N0.getOperand(1))) {
800 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
801 AddToWorkList(C3.Val);
802 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
805 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
808 SDOperand Sh(0,0), Y(0,0);
809 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
810 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
811 N0.Val->hasOneUse()) {
813 } else if (N1.getOpcode() == ISD::SHL &&
814 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
818 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
819 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
822 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
823 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
824 isa<ConstantSDNode>(N0.getOperand(1))) {
825 return DAG.getNode(ISD::ADD, VT,
826 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
827 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
831 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
837 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
838 SDOperand N0 = N->getOperand(0);
839 SDOperand N1 = N->getOperand(1);
840 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
841 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
842 MVT::ValueType VT = N->getValueType(0);
844 // fold (sdiv c1, c2) -> c1/c2
845 if (N0C && N1C && !N1C->isNullValue())
846 return DAG.getNode(ISD::SDIV, VT, N0, N1);
847 // fold (sdiv X, 1) -> X
848 if (N1C && N1C->getSignExtended() == 1LL)
850 // fold (sdiv X, -1) -> 0-X
851 if (N1C && N1C->isAllOnesValue())
852 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
853 // If we know the sign bits of both operands are zero, strength reduce to a
854 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
855 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
856 if (TLI.MaskedValueIsZero(N1, SignBit) &&
857 TLI.MaskedValueIsZero(N0, SignBit))
858 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
859 // fold (sdiv X, pow2) -> simple ops after legalize
860 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
861 (isPowerOf2_64(N1C->getSignExtended()) ||
862 isPowerOf2_64(-N1C->getSignExtended()))) {
863 // If dividing by powers of two is cheap, then don't perform the following
865 if (TLI.isPow2DivCheap())
867 int64_t pow2 = N1C->getSignExtended();
868 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
869 unsigned lg2 = Log2_64(abs2);
870 // Splat the sign bit into the register
871 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
872 DAG.getConstant(MVT::getSizeInBits(VT)-1,
873 TLI.getShiftAmountTy()));
874 AddToWorkList(SGN.Val);
875 // Add (N0 < 0) ? abs2 - 1 : 0;
876 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
877 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
878 TLI.getShiftAmountTy()));
879 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
880 AddToWorkList(SRL.Val);
881 AddToWorkList(ADD.Val); // Divide by pow2
882 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
883 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
884 // If we're dividing by a positive value, we're done. Otherwise, we must
885 // negate the result.
888 AddToWorkList(SRA.Val);
889 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
891 // if integer divide is expensive and we satisfy the requirements, emit an
892 // alternate sequence.
893 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
894 !TLI.isIntDivCheap()) {
895 SDOperand Op = BuildSDIV(N);
896 if (Op.Val) return Op;
901 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
902 SDOperand N0 = N->getOperand(0);
903 SDOperand N1 = N->getOperand(1);
904 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
905 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
906 MVT::ValueType VT = N->getValueType(0);
908 // fold (udiv c1, c2) -> c1/c2
909 if (N0C && N1C && !N1C->isNullValue())
910 return DAG.getNode(ISD::UDIV, VT, N0, N1);
911 // fold (udiv x, (1 << c)) -> x >>u c
912 if (N1C && isPowerOf2_64(N1C->getValue()))
913 return DAG.getNode(ISD::SRL, VT, N0,
914 DAG.getConstant(Log2_64(N1C->getValue()),
915 TLI.getShiftAmountTy()));
916 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
917 if (N1.getOpcode() == ISD::SHL) {
918 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
919 if (isPowerOf2_64(SHC->getValue())) {
920 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
921 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
922 DAG.getConstant(Log2_64(SHC->getValue()),
924 AddToWorkList(Add.Val);
925 return DAG.getNode(ISD::SRL, VT, N0, Add);
929 // fold (udiv x, c) -> alternate
930 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
931 SDOperand Op = BuildUDIV(N);
932 if (Op.Val) return Op;
937 SDOperand DAGCombiner::visitSREM(SDNode *N) {
938 SDOperand N0 = N->getOperand(0);
939 SDOperand N1 = N->getOperand(1);
940 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
941 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
942 MVT::ValueType VT = N->getValueType(0);
944 // fold (srem c1, c2) -> c1%c2
945 if (N0C && N1C && !N1C->isNullValue())
946 return DAG.getNode(ISD::SREM, VT, N0, N1);
947 // If we know the sign bits of both operands are zero, strength reduce to a
948 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
949 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
950 if (TLI.MaskedValueIsZero(N1, SignBit) &&
951 TLI.MaskedValueIsZero(N0, SignBit))
952 return DAG.getNode(ISD::UREM, VT, N0, N1);
956 SDOperand DAGCombiner::visitUREM(SDNode *N) {
957 SDOperand N0 = N->getOperand(0);
958 SDOperand N1 = N->getOperand(1);
959 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
960 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
961 MVT::ValueType VT = N->getValueType(0);
963 // fold (urem c1, c2) -> c1%c2
964 if (N0C && N1C && !N1C->isNullValue())
965 return DAG.getNode(ISD::UREM, VT, N0, N1);
966 // fold (urem x, pow2) -> (and x, pow2-1)
967 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
968 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
969 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
970 if (N1.getOpcode() == ISD::SHL) {
971 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
972 if (isPowerOf2_64(SHC->getValue())) {
973 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
974 AddToWorkList(Add.Val);
975 return DAG.getNode(ISD::AND, VT, N0, Add);
982 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
983 SDOperand N0 = N->getOperand(0);
984 SDOperand N1 = N->getOperand(1);
985 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
987 // fold (mulhs x, 0) -> 0
988 if (N1C && N1C->isNullValue())
990 // fold (mulhs x, 1) -> (sra x, size(x)-1)
991 if (N1C && N1C->getValue() == 1)
992 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
993 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
994 TLI.getShiftAmountTy()));
998 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
999 SDOperand N0 = N->getOperand(0);
1000 SDOperand N1 = N->getOperand(1);
1001 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1003 // fold (mulhu x, 0) -> 0
1004 if (N1C && N1C->isNullValue())
1006 // fold (mulhu x, 1) -> 0
1007 if (N1C && N1C->getValue() == 1)
1008 return DAG.getConstant(0, N0.getValueType());
1012 SDOperand DAGCombiner::visitAND(SDNode *N) {
1013 SDOperand N0 = N->getOperand(0);
1014 SDOperand N1 = N->getOperand(1);
1015 SDOperand LL, LR, RL, RR, CC0, CC1;
1016 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1017 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1018 MVT::ValueType VT = N1.getValueType();
1019 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1021 // fold (and c1, c2) -> c1&c2
1023 return DAG.getNode(ISD::AND, VT, N0, N1);
1024 // canonicalize constant to RHS
1026 return DAG.getNode(ISD::AND, VT, N1, N0);
1027 // fold (and x, -1) -> x
1028 if (N1C && N1C->isAllOnesValue())
1030 // if (and x, c) is known to be zero, return 0
1031 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1032 return DAG.getConstant(0, VT);
1034 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1037 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1038 if (N1C && N0.getOpcode() == ISD::OR)
1039 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1040 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1042 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1043 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1044 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1045 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1046 ~N1C->getValue() & InMask)) {
1047 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1050 // Replace uses of the AND with uses of the Zero extend node.
1053 // We actually want to replace all uses of the any_extend with the
1054 // zero_extend, to avoid duplicating things. This will later cause this
1055 // AND to be folded.
1056 CombineTo(N0.Val, Zext);
1060 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1061 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1062 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1063 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1065 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1066 MVT::isInteger(LL.getValueType())) {
1067 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1068 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1069 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1070 AddToWorkList(ORNode.Val);
1071 return DAG.getSetCC(VT, ORNode, LR, Op1);
1073 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1074 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1075 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1076 AddToWorkList(ANDNode.Val);
1077 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1079 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1080 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1081 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1082 AddToWorkList(ORNode.Val);
1083 return DAG.getSetCC(VT, ORNode, LR, Op1);
1086 // canonicalize equivalent to ll == rl
1087 if (LL == RR && LR == RL) {
1088 Op1 = ISD::getSetCCSwappedOperands(Op1);
1091 if (LL == RL && LR == RR) {
1092 bool isInteger = MVT::isInteger(LL.getValueType());
1093 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1094 if (Result != ISD::SETCC_INVALID)
1095 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1098 // fold (and (zext x), (zext y)) -> (zext (and x, y))
1099 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1100 N1.getOpcode() == ISD::ZERO_EXTEND &&
1101 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1102 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
1103 N0.getOperand(0), N1.getOperand(0));
1104 AddToWorkList(ANDNode.Val);
1105 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
1107 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y))
1108 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1109 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1110 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1111 N0.getOperand(1) == N1.getOperand(1)) {
1112 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
1113 N0.getOperand(0), N1.getOperand(0));
1114 AddToWorkList(ANDNode.Val);
1115 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
1117 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1118 // fold (and (sra)) -> (and (srl)) when possible.
1119 if (SimplifyDemandedBits(SDOperand(N, 0)))
1121 // fold (zext_inreg (extload x)) -> (zextload x)
1122 if (N0.getOpcode() == ISD::EXTLOAD) {
1123 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1124 // If we zero all the possible extended bits, then we can turn this into
1125 // a zextload if we are running before legalize or the operation is legal.
1126 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1127 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1128 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1129 N0.getOperand(1), N0.getOperand(2),
1132 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1136 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1137 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
1138 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1139 // If we zero all the possible extended bits, then we can turn this into
1140 // a zextload if we are running before legalize or the operation is legal.
1141 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1142 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1143 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1144 N0.getOperand(1), N0.getOperand(2),
1147 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1152 // fold (and (load x), 255) -> (zextload x, i8)
1153 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1155 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD ||
1156 N0.getOpcode() == ISD::ZEXTLOAD) &&
1158 MVT::ValueType EVT, LoadedVT;
1159 if (N1C->getValue() == 255)
1161 else if (N1C->getValue() == 65535)
1163 else if (N1C->getValue() == ~0U)
1168 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT :
1169 cast<VTSDNode>(N0.getOperand(3))->getVT();
1170 if (EVT != MVT::Other && LoadedVT > EVT) {
1171 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1172 // For big endian targets, we need to add an offset to the pointer to load
1173 // the correct bytes. For little endian systems, we merely need to read
1174 // fewer bytes from the same pointer.
1176 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1177 SDOperand NewPtr = N0.getOperand(1);
1178 if (!TLI.isLittleEndian())
1179 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1180 DAG.getConstant(PtrOff, PtrType));
1181 AddToWorkList(NewPtr.Val);
1183 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr,
1184 N0.getOperand(2), EVT);
1186 CombineTo(N0.Val, Load, Load.getValue(1));
1194 SDOperand DAGCombiner::visitOR(SDNode *N) {
1195 SDOperand N0 = N->getOperand(0);
1196 SDOperand N1 = N->getOperand(1);
1197 SDOperand LL, LR, RL, RR, CC0, CC1;
1198 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1199 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1200 MVT::ValueType VT = N1.getValueType();
1201 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1203 // fold (or c1, c2) -> c1|c2
1205 return DAG.getNode(ISD::OR, VT, N0, N1);
1206 // canonicalize constant to RHS
1208 return DAG.getNode(ISD::OR, VT, N1, N0);
1209 // fold (or x, 0) -> x
1210 if (N1C && N1C->isNullValue())
1212 // fold (or x, -1) -> -1
1213 if (N1C && N1C->isAllOnesValue())
1215 // fold (or x, c) -> c iff (x & ~c) == 0
1217 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1220 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1223 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1224 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1225 isa<ConstantSDNode>(N0.getOperand(1))) {
1226 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1227 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1229 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1231 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1232 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1233 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1234 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1236 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1237 MVT::isInteger(LL.getValueType())) {
1238 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1239 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1240 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1241 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1242 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1243 AddToWorkList(ORNode.Val);
1244 return DAG.getSetCC(VT, ORNode, LR, Op1);
1246 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1247 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1248 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1249 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1250 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1251 AddToWorkList(ANDNode.Val);
1252 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1255 // canonicalize equivalent to ll == rl
1256 if (LL == RR && LR == RL) {
1257 Op1 = ISD::getSetCCSwappedOperands(Op1);
1260 if (LL == RL && LR == RR) {
1261 bool isInteger = MVT::isInteger(LL.getValueType());
1262 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1263 if (Result != ISD::SETCC_INVALID)
1264 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1267 // fold (or (zext x), (zext y)) -> (zext (or x, y))
1268 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1269 N1.getOpcode() == ISD::ZERO_EXTEND &&
1270 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1271 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1272 N0.getOperand(0), N1.getOperand(0));
1273 AddToWorkList(ORNode.Val);
1274 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
1276 // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y))
1277 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1278 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1279 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1280 N0.getOperand(1) == N1.getOperand(1)) {
1281 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1282 N0.getOperand(0), N1.getOperand(0));
1283 AddToWorkList(ORNode.Val);
1284 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1286 // canonicalize shl to left side in a shl/srl pair, to match rotate
1287 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
1289 // check for rotl, rotr
1290 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
1291 N0.getOperand(0) == N1.getOperand(0) &&
1292 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
1293 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1294 if (N0.getOperand(1).getOpcode() == ISD::Constant &&
1295 N1.getOperand(1).getOpcode() == ISD::Constant) {
1296 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1297 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1298 if ((c1val + c2val) == OpSizeInBits)
1299 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1301 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1302 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
1303 N0.getOperand(1) == N1.getOperand(1).getOperand(1))
1304 if (ConstantSDNode *SUBC =
1305 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
1306 if (SUBC->getValue() == OpSizeInBits)
1307 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1308 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1309 if (N0.getOperand(1).getOpcode() == ISD::SUB &&
1310 N1.getOperand(1) == N0.getOperand(1).getOperand(1))
1311 if (ConstantSDNode *SUBC =
1312 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
1313 if (SUBC->getValue() == OpSizeInBits) {
1314 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
1315 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
1318 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
1325 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1326 SDOperand N0 = N->getOperand(0);
1327 SDOperand N1 = N->getOperand(1);
1328 SDOperand LHS, RHS, CC;
1329 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1330 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1331 MVT::ValueType VT = N0.getValueType();
1333 // fold (xor c1, c2) -> c1^c2
1335 return DAG.getNode(ISD::XOR, VT, N0, N1);
1336 // canonicalize constant to RHS
1338 return DAG.getNode(ISD::XOR, VT, N1, N0);
1339 // fold (xor x, 0) -> x
1340 if (N1C && N1C->isNullValue())
1343 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1346 // fold !(x cc y) -> (x !cc y)
1347 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1348 bool isInt = MVT::isInteger(LHS.getValueType());
1349 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1351 if (N0.getOpcode() == ISD::SETCC)
1352 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1353 if (N0.getOpcode() == ISD::SELECT_CC)
1354 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1355 assert(0 && "Unhandled SetCC Equivalent!");
1358 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1359 if (N1C && N1C->getValue() == 1 &&
1360 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1361 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1362 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1363 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1364 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1365 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1366 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1367 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1370 // fold !(x or y) -> (!x and !y) iff x or y are constants
1371 if (N1C && N1C->isAllOnesValue() &&
1372 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1373 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1374 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1375 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1376 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1377 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1378 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1379 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1382 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1383 if (N1C && N0.getOpcode() == ISD::XOR) {
1384 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1385 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1387 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1388 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1390 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1391 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1393 // fold (xor x, x) -> 0
1395 return DAG.getConstant(0, VT);
1396 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
1397 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1398 N1.getOpcode() == ISD::ZERO_EXTEND &&
1399 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1400 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1401 N0.getOperand(0), N1.getOperand(0));
1402 AddToWorkList(XORNode.Val);
1403 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
1405 // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y))
1406 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1407 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1408 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1409 N0.getOperand(1) == N1.getOperand(1)) {
1410 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1411 N0.getOperand(0), N1.getOperand(0));
1412 AddToWorkList(XORNode.Val);
1413 return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1));
1418 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1419 SDOperand N0 = N->getOperand(0);
1420 SDOperand N1 = N->getOperand(1);
1421 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1422 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1423 MVT::ValueType VT = N0.getValueType();
1424 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1426 // fold (shl c1, c2) -> c1<<c2
1428 return DAG.getNode(ISD::SHL, VT, N0, N1);
1429 // fold (shl 0, x) -> 0
1430 if (N0C && N0C->isNullValue())
1432 // fold (shl x, c >= size(x)) -> undef
1433 if (N1C && N1C->getValue() >= OpSizeInBits)
1434 return DAG.getNode(ISD::UNDEF, VT);
1435 // fold (shl x, 0) -> x
1436 if (N1C && N1C->isNullValue())
1438 // if (shl x, c) is known to be zero, return 0
1439 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1440 return DAG.getConstant(0, VT);
1441 if (SimplifyDemandedBits(SDOperand(N, 0)))
1443 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1444 if (N1C && N0.getOpcode() == ISD::SHL &&
1445 N0.getOperand(1).getOpcode() == ISD::Constant) {
1446 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1447 uint64_t c2 = N1C->getValue();
1448 if (c1 + c2 > OpSizeInBits)
1449 return DAG.getConstant(0, VT);
1450 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1451 DAG.getConstant(c1 + c2, N1.getValueType()));
1453 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1454 // (srl (and x, -1 << c1), c1-c2)
1455 if (N1C && N0.getOpcode() == ISD::SRL &&
1456 N0.getOperand(1).getOpcode() == ISD::Constant) {
1457 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1458 uint64_t c2 = N1C->getValue();
1459 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1460 DAG.getConstant(~0ULL << c1, VT));
1462 return DAG.getNode(ISD::SHL, VT, Mask,
1463 DAG.getConstant(c2-c1, N1.getValueType()));
1465 return DAG.getNode(ISD::SRL, VT, Mask,
1466 DAG.getConstant(c1-c2, N1.getValueType()));
1468 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1469 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1470 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1471 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1472 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1473 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1474 isa<ConstantSDNode>(N0.getOperand(1))) {
1475 return DAG.getNode(ISD::ADD, VT,
1476 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1477 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1482 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1483 SDOperand N0 = N->getOperand(0);
1484 SDOperand N1 = N->getOperand(1);
1485 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1486 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1487 MVT::ValueType VT = N0.getValueType();
1489 // fold (sra c1, c2) -> c1>>c2
1491 return DAG.getNode(ISD::SRA, VT, N0, N1);
1492 // fold (sra 0, x) -> 0
1493 if (N0C && N0C->isNullValue())
1495 // fold (sra -1, x) -> -1
1496 if (N0C && N0C->isAllOnesValue())
1498 // fold (sra x, c >= size(x)) -> undef
1499 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1500 return DAG.getNode(ISD::UNDEF, VT);
1501 // fold (sra x, 0) -> x
1502 if (N1C && N1C->isNullValue())
1504 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1506 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1507 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1510 default: EVT = MVT::Other; break;
1511 case 1: EVT = MVT::i1; break;
1512 case 8: EVT = MVT::i8; break;
1513 case 16: EVT = MVT::i16; break;
1514 case 32: EVT = MVT::i32; break;
1516 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1517 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1518 DAG.getValueType(EVT));
1521 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1522 if (N1C && N0.getOpcode() == ISD::SRA) {
1523 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1524 unsigned Sum = N1C->getValue() + C1->getValue();
1525 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1526 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1527 DAG.getConstant(Sum, N1C->getValueType(0)));
1531 // If the sign bit is known to be zero, switch this to a SRL.
1532 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1533 return DAG.getNode(ISD::SRL, VT, N0, N1);
1537 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1538 SDOperand N0 = N->getOperand(0);
1539 SDOperand N1 = N->getOperand(1);
1540 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1541 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1542 MVT::ValueType VT = N0.getValueType();
1543 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1545 // fold (srl c1, c2) -> c1 >>u c2
1547 return DAG.getNode(ISD::SRL, VT, N0, N1);
1548 // fold (srl 0, x) -> 0
1549 if (N0C && N0C->isNullValue())
1551 // fold (srl x, c >= size(x)) -> undef
1552 if (N1C && N1C->getValue() >= OpSizeInBits)
1553 return DAG.getNode(ISD::UNDEF, VT);
1554 // fold (srl x, 0) -> x
1555 if (N1C && N1C->isNullValue())
1557 // if (srl x, c) is known to be zero, return 0
1558 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1559 return DAG.getConstant(0, VT);
1560 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1561 if (N1C && N0.getOpcode() == ISD::SRL &&
1562 N0.getOperand(1).getOpcode() == ISD::Constant) {
1563 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1564 uint64_t c2 = N1C->getValue();
1565 if (c1 + c2 > OpSizeInBits)
1566 return DAG.getConstant(0, VT);
1567 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1568 DAG.getConstant(c1 + c2, N1.getValueType()));
1573 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1574 SDOperand N0 = N->getOperand(0);
1575 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1576 MVT::ValueType VT = N->getValueType(0);
1578 // fold (ctlz c1) -> c2
1580 return DAG.getNode(ISD::CTLZ, VT, N0);
1584 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1585 SDOperand N0 = N->getOperand(0);
1586 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1587 MVT::ValueType VT = N->getValueType(0);
1589 // fold (cttz c1) -> c2
1591 return DAG.getNode(ISD::CTTZ, VT, N0);
1595 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1596 SDOperand N0 = N->getOperand(0);
1597 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1598 MVT::ValueType VT = N->getValueType(0);
1600 // fold (ctpop c1) -> c2
1602 return DAG.getNode(ISD::CTPOP, VT, N0);
1606 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1607 SDOperand N0 = N->getOperand(0);
1608 SDOperand N1 = N->getOperand(1);
1609 SDOperand N2 = N->getOperand(2);
1610 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1612 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1613 MVT::ValueType VT = N->getValueType(0);
1615 // fold select C, X, X -> X
1618 // fold select true, X, Y -> X
1619 if (N0C && !N0C->isNullValue())
1621 // fold select false, X, Y -> Y
1622 if (N0C && N0C->isNullValue())
1624 // fold select C, 1, X -> C | X
1625 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1626 return DAG.getNode(ISD::OR, VT, N0, N2);
1627 // fold select C, 0, X -> ~C & X
1628 // FIXME: this should check for C type == X type, not i1?
1629 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1630 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1631 AddToWorkList(XORNode.Val);
1632 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1634 // fold select C, X, 1 -> ~C | X
1635 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1636 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1637 AddToWorkList(XORNode.Val);
1638 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1640 // fold select C, X, 0 -> C & X
1641 // FIXME: this should check for C type == X type, not i1?
1642 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1643 return DAG.getNode(ISD::AND, VT, N0, N1);
1644 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1645 if (MVT::i1 == VT && N0 == N1)
1646 return DAG.getNode(ISD::OR, VT, N0, N2);
1647 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1648 if (MVT::i1 == VT && N0 == N2)
1649 return DAG.getNode(ISD::AND, VT, N0, N1);
1650 // If we can fold this based on the true/false value, do so.
1651 if (SimplifySelectOps(N, N1, N2))
1653 // fold selects based on a setcc into other things, such as min/max/abs
1654 if (N0.getOpcode() == ISD::SETCC)
1656 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1657 // having to say they don't support SELECT_CC on every type the DAG knows
1658 // about, since there is no way to mark an opcode illegal at all value types
1659 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1660 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1661 N1, N2, N0.getOperand(2));
1663 return SimplifySelect(N0, N1, N2);
1667 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1668 SDOperand N0 = N->getOperand(0);
1669 SDOperand N1 = N->getOperand(1);
1670 SDOperand N2 = N->getOperand(2);
1671 SDOperand N3 = N->getOperand(3);
1672 SDOperand N4 = N->getOperand(4);
1673 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1674 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1675 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1676 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1678 // Determine if the condition we're dealing with is constant
1679 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1680 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1682 // fold select_cc lhs, rhs, x, x, cc -> x
1686 // If we can fold this based on the true/false value, do so.
1687 if (SimplifySelectOps(N, N2, N3))
1690 // fold select_cc into other things, such as min/max/abs
1691 return SimplifySelectCC(N0, N1, N2, N3, CC);
1694 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1695 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1696 cast<CondCodeSDNode>(N->getOperand(2))->get());
1699 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1700 SDOperand N0 = N->getOperand(0);
1701 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1702 MVT::ValueType VT = N->getValueType(0);
1704 // fold (sext c1) -> c1
1706 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1707 // fold (sext (sext x)) -> (sext x)
1708 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1709 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1710 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
1711 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1713 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
1714 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1715 DAG.getValueType(N0.getValueType()));
1716 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1717 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1718 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
1719 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1720 N0.getOperand(1), N0.getOperand(2),
1722 CombineTo(N, ExtLoad);
1723 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1724 ExtLoad.getValue(1));
1728 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1729 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1730 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1732 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0),
1733 N0.getOperand(1), N0.getOperand(2),
1735 CombineTo(N, ExtLoad);
1736 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1737 ExtLoad.getValue(1));
1744 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1745 SDOperand N0 = N->getOperand(0);
1746 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1747 MVT::ValueType VT = N->getValueType(0);
1749 // fold (zext c1) -> c1
1751 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1752 // fold (zext (zext x)) -> (zext x)
1753 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1754 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1755 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
1756 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1757 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType())))
1758 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
1759 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1760 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1761 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
1762 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1763 N0.getOperand(1), N0.getOperand(2),
1765 CombineTo(N, ExtLoad);
1766 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1767 ExtLoad.getValue(1));
1771 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1772 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1773 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1775 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1776 N0.getOperand(1), N0.getOperand(2),
1778 CombineTo(N, ExtLoad);
1779 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1780 ExtLoad.getValue(1));
1786 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1787 SDOperand N0 = N->getOperand(0);
1788 SDOperand N1 = N->getOperand(1);
1789 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1790 MVT::ValueType VT = N->getValueType(0);
1791 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1792 unsigned EVTBits = MVT::getSizeInBits(EVT);
1794 // fold (sext_in_reg c1) -> c1
1796 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1797 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1799 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1800 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1801 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1804 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1805 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1806 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1807 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1809 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1810 if (N0.getOpcode() == ISD::AssertSext &&
1811 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1814 // fold (sext_in_reg (sextload x)) -> (sextload x)
1815 if (N0.getOpcode() == ISD::SEXTLOAD &&
1816 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1819 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1820 if (N0.getOpcode() == ISD::SETCC &&
1821 TLI.getSetCCResultContents() ==
1822 TargetLowering::ZeroOrNegativeOneSetCCResult)
1824 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1825 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
1826 return DAG.getZeroExtendInReg(N0, EVT);
1827 // fold (sext_in_reg (srl x)) -> sra x
1828 if (N0.getOpcode() == ISD::SRL &&
1829 N0.getOperand(1).getOpcode() == ISD::Constant &&
1830 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1831 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1834 // fold (sext_inreg (extload x)) -> (sextload x)
1835 if (N0.getOpcode() == ISD::EXTLOAD &&
1836 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1837 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1838 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1839 N0.getOperand(1), N0.getOperand(2),
1841 CombineTo(N, ExtLoad);
1842 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1845 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1846 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
1847 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1848 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1849 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1850 N0.getOperand(1), N0.getOperand(2),
1852 CombineTo(N, ExtLoad);
1853 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1859 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1860 SDOperand N0 = N->getOperand(0);
1861 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1862 MVT::ValueType VT = N->getValueType(0);
1865 if (N0.getValueType() == N->getValueType(0))
1867 // fold (truncate c1) -> c1
1869 return DAG.getNode(ISD::TRUNCATE, VT, N0);
1870 // fold (truncate (truncate x)) -> (truncate x)
1871 if (N0.getOpcode() == ISD::TRUNCATE)
1872 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1873 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1874 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1875 if (N0.getValueType() < VT)
1876 // if the source is smaller than the dest, we still need an extend
1877 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1878 else if (N0.getValueType() > VT)
1879 // if the source is larger than the dest, than we just need the truncate
1880 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1882 // if the source and dest are the same type, we can drop both the extend
1884 return N0.getOperand(0);
1886 // fold (truncate (load x)) -> (smaller load x)
1887 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1888 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1889 "Cannot truncate to larger type!");
1890 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1891 // For big endian targets, we need to add an offset to the pointer to load
1892 // the correct bytes. For little endian systems, we merely need to read
1893 // fewer bytes from the same pointer.
1895 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1896 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1897 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1898 DAG.getConstant(PtrOff, PtrType));
1899 AddToWorkList(NewPtr.Val);
1900 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1902 CombineTo(N0.Val, Load, Load.getValue(1));
1908 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
1909 SDOperand N0 = N->getOperand(0);
1910 MVT::ValueType VT = N->getValueType(0);
1912 // If the input is a constant, let getNode() fold it.
1913 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
1914 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
1915 if (Res.Val != N) return Res;
1918 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
1919 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
1921 // fold (conv (load x)) -> (load (conv*)x)
1922 // FIXME: These xforms need to know that the resultant load doesn't need a
1923 // higher alignment than the original!
1924 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1925 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
1928 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
1936 SDOperand DAGCombiner::visitFADD(SDNode *N) {
1937 SDOperand N0 = N->getOperand(0);
1938 SDOperand N1 = N->getOperand(1);
1939 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1940 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1941 MVT::ValueType VT = N->getValueType(0);
1943 // fold (fadd c1, c2) -> c1+c2
1945 return DAG.getNode(ISD::FADD, VT, N0, N1);
1946 // canonicalize constant to RHS
1947 if (N0CFP && !N1CFP)
1948 return DAG.getNode(ISD::FADD, VT, N1, N0);
1949 // fold (A + (-B)) -> A-B
1950 if (N1.getOpcode() == ISD::FNEG)
1951 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1952 // fold ((-A) + B) -> B-A
1953 if (N0.getOpcode() == ISD::FNEG)
1954 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1958 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1959 SDOperand N0 = N->getOperand(0);
1960 SDOperand N1 = N->getOperand(1);
1961 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1962 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1963 MVT::ValueType VT = N->getValueType(0);
1965 // fold (fsub c1, c2) -> c1-c2
1967 return DAG.getNode(ISD::FSUB, VT, N0, N1);
1968 // fold (A-(-B)) -> A+B
1969 if (N1.getOpcode() == ISD::FNEG)
1970 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
1974 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1975 SDOperand N0 = N->getOperand(0);
1976 SDOperand N1 = N->getOperand(1);
1977 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1978 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1979 MVT::ValueType VT = N->getValueType(0);
1981 // fold (fmul c1, c2) -> c1*c2
1983 return DAG.getNode(ISD::FMUL, VT, N0, N1);
1984 // canonicalize constant to RHS
1985 if (N0CFP && !N1CFP)
1986 return DAG.getNode(ISD::FMUL, VT, N1, N0);
1987 // fold (fmul X, 2.0) -> (fadd X, X)
1988 if (N1CFP && N1CFP->isExactlyValue(+2.0))
1989 return DAG.getNode(ISD::FADD, VT, N0, N0);
1993 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1994 SDOperand N0 = N->getOperand(0);
1995 SDOperand N1 = N->getOperand(1);
1996 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1997 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1998 MVT::ValueType VT = N->getValueType(0);
2000 // fold (fdiv c1, c2) -> c1/c2
2002 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2006 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2007 SDOperand N0 = N->getOperand(0);
2008 SDOperand N1 = N->getOperand(1);
2009 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2010 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2011 MVT::ValueType VT = N->getValueType(0);
2013 // fold (frem c1, c2) -> fmod(c1,c2)
2015 return DAG.getNode(ISD::FREM, VT, N0, N1);
2019 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2020 SDOperand N0 = N->getOperand(0);
2021 SDOperand N1 = N->getOperand(1);
2022 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2023 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2024 MVT::ValueType VT = N->getValueType(0);
2026 if (N0CFP && N1CFP) // Constant fold
2027 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2030 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2031 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2036 u.d = N1CFP->getValue();
2038 return DAG.getNode(ISD::FABS, VT, N0);
2040 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2043 // copysign(fabs(x), y) -> copysign(x, y)
2044 // copysign(fneg(x), y) -> copysign(x, y)
2045 // copysign(copysign(x,z), y) -> copysign(x, y)
2046 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2047 N0.getOpcode() == ISD::FCOPYSIGN)
2048 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2050 // copysign(x, abs(y)) -> abs(x)
2051 if (N1.getOpcode() == ISD::FABS)
2052 return DAG.getNode(ISD::FABS, VT, N0);
2054 // copysign(x, copysign(y,z)) -> copysign(x, z)
2055 if (N1.getOpcode() == ISD::FCOPYSIGN)
2056 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2058 // copysign(x, fp_extend(y)) -> copysign(x, y)
2059 // copysign(x, fp_round(y)) -> copysign(x, y)
2060 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2061 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2068 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2069 SDOperand N0 = N->getOperand(0);
2070 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2071 MVT::ValueType VT = N->getValueType(0);
2073 // fold (sint_to_fp c1) -> c1fp
2075 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2079 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2080 SDOperand N0 = N->getOperand(0);
2081 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2082 MVT::ValueType VT = N->getValueType(0);
2084 // fold (uint_to_fp c1) -> c1fp
2086 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2090 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2091 SDOperand N0 = N->getOperand(0);
2092 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2093 MVT::ValueType VT = N->getValueType(0);
2095 // fold (fp_to_sint c1fp) -> c1
2097 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2101 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2102 SDOperand N0 = N->getOperand(0);
2103 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2104 MVT::ValueType VT = N->getValueType(0);
2106 // fold (fp_to_uint c1fp) -> c1
2108 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2112 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2113 SDOperand N0 = N->getOperand(0);
2114 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2115 MVT::ValueType VT = N->getValueType(0);
2117 // fold (fp_round c1fp) -> c1fp
2119 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2121 // fold (fp_round (fp_extend x)) -> x
2122 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2123 return N0.getOperand(0);
2125 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2126 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2127 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2128 AddToWorkList(Tmp.Val);
2129 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2135 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2136 SDOperand N0 = N->getOperand(0);
2137 MVT::ValueType VT = N->getValueType(0);
2138 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2139 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2141 // fold (fp_round_inreg c1fp) -> c1fp
2143 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2144 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2149 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2150 SDOperand N0 = N->getOperand(0);
2151 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2152 MVT::ValueType VT = N->getValueType(0);
2154 // fold (fp_extend c1fp) -> c1fp
2156 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2160 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2161 SDOperand N0 = N->getOperand(0);
2162 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2163 MVT::ValueType VT = N->getValueType(0);
2165 // fold (fneg c1) -> -c1
2167 return DAG.getNode(ISD::FNEG, VT, N0);
2168 // fold (fneg (sub x, y)) -> (sub y, x)
2169 if (N0.getOpcode() == ISD::SUB)
2170 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2171 // fold (fneg (fneg x)) -> x
2172 if (N0.getOpcode() == ISD::FNEG)
2173 return N0.getOperand(0);
2177 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2178 SDOperand N0 = N->getOperand(0);
2179 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2180 MVT::ValueType VT = N->getValueType(0);
2182 // fold (fabs c1) -> fabs(c1)
2184 return DAG.getNode(ISD::FABS, VT, N0);
2185 // fold (fabs (fabs x)) -> (fabs x)
2186 if (N0.getOpcode() == ISD::FABS)
2187 return N->getOperand(0);
2188 // fold (fabs (fneg x)) -> (fabs x)
2189 // fold (fabs (fcopysign x, y)) -> (fabs x)
2190 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2191 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2196 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2197 SDOperand Chain = N->getOperand(0);
2198 SDOperand N1 = N->getOperand(1);
2199 SDOperand N2 = N->getOperand(2);
2200 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2202 // never taken branch, fold to chain
2203 if (N1C && N1C->isNullValue())
2205 // unconditional branch
2206 if (N1C && N1C->getValue() == 1)
2207 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2208 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2210 if (N1.getOpcode() == ISD::SETCC &&
2211 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2212 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2213 N1.getOperand(0), N1.getOperand(1), N2);
2218 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2220 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2221 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2222 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2224 // Use SimplifySetCC to simplify SETCC's.
2225 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2226 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2228 // fold br_cc true, dest -> br dest (unconditional branch)
2229 if (SCCC && SCCC->getValue())
2230 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2232 // fold br_cc false, dest -> unconditional fall through
2233 if (SCCC && SCCC->isNullValue())
2234 return N->getOperand(0);
2235 // fold to a simpler setcc
2236 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2237 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2238 Simp.getOperand(2), Simp.getOperand(0),
2239 Simp.getOperand(1), N->getOperand(4));
2243 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2244 SDOperand Chain = N->getOperand(0);
2245 SDOperand Ptr = N->getOperand(1);
2246 SDOperand SrcValue = N->getOperand(2);
2248 // If this load is directly stored, replace the load value with the stored
2250 // TODO: Handle store large -> read small portion.
2251 // TODO: Handle TRUNCSTORE/EXTLOAD
2252 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2253 Chain.getOperand(1).getValueType() == N->getValueType(0))
2254 return CombineTo(N, Chain.getOperand(1), Chain);
2259 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2260 SDOperand Chain = N->getOperand(0);
2261 SDOperand Value = N->getOperand(1);
2262 SDOperand Ptr = N->getOperand(2);
2263 SDOperand SrcValue = N->getOperand(3);
2265 // If this is a store that kills a previous store, remove the previous store.
2266 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2267 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2268 // Make sure that these stores are the same value type:
2269 // FIXME: we really care that the second store is >= size of the first.
2270 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2271 // Create a new store of Value that replaces both stores.
2272 SDNode *PrevStore = Chain.Val;
2273 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2275 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
2276 PrevStore->getOperand(0), Value, Ptr,
2278 CombineTo(N, NewStore); // Nuke this store.
2279 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2280 return SDOperand(N, 0);
2283 // If this is a store of a bit convert, store the input value.
2284 // FIXME: This needs to know that the resultant store does not need a
2285 // higher alignment than the original.
2286 if (0 && Value.getOpcode() == ISD::BIT_CONVERT)
2287 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
2293 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
2294 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
2296 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
2297 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2298 // If we got a simplified select_cc node back from SimplifySelectCC, then
2299 // break it down into a new SETCC node, and a new SELECT node, and then return
2300 // the SELECT node, since we were called with a SELECT node.
2302 // Check to see if we got a select_cc back (to turn into setcc/select).
2303 // Otherwise, just return whatever node we got back, like fabs.
2304 if (SCC.getOpcode() == ISD::SELECT_CC) {
2305 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
2306 SCC.getOperand(0), SCC.getOperand(1),
2308 AddToWorkList(SETCC.Val);
2309 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
2310 SCC.getOperand(3), SETCC);
2317 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
2318 /// are the two values being selected between, see if we can simplify the
2321 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
2324 // If this is a select from two identical things, try to pull the operation
2325 // through the select.
2326 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
2328 std::cerr << "SELECT: ["; LHS.Val->dump();
2329 std::cerr << "] ["; RHS.Val->dump();
2333 // If this is a load and the token chain is identical, replace the select
2334 // of two loads with a load through a select of the address to load from.
2335 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
2336 // constants have been dropped into the constant pool.
2337 if ((LHS.getOpcode() == ISD::LOAD ||
2338 LHS.getOpcode() == ISD::EXTLOAD ||
2339 LHS.getOpcode() == ISD::ZEXTLOAD ||
2340 LHS.getOpcode() == ISD::SEXTLOAD) &&
2341 // Token chains must be identical.
2342 LHS.getOperand(0) == RHS.getOperand(0) &&
2343 // If this is an EXTLOAD, the VT's must match.
2344 (LHS.getOpcode() == ISD::LOAD ||
2345 LHS.getOperand(3) == RHS.getOperand(3))) {
2346 // FIXME: this conflates two src values, discarding one. This is not
2347 // the right thing to do, but nothing uses srcvalues now. When they do,
2348 // turn SrcValue into a list of locations.
2350 if (TheSelect->getOpcode() == ISD::SELECT)
2351 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
2352 TheSelect->getOperand(0), LHS.getOperand(1),
2355 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
2356 TheSelect->getOperand(0),
2357 TheSelect->getOperand(1),
2358 LHS.getOperand(1), RHS.getOperand(1),
2359 TheSelect->getOperand(4));
2362 if (LHS.getOpcode() == ISD::LOAD)
2363 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
2364 Addr, LHS.getOperand(2));
2366 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
2367 LHS.getOperand(0), Addr, LHS.getOperand(2),
2368 cast<VTSDNode>(LHS.getOperand(3))->getVT());
2369 // Users of the select now use the result of the load.
2370 CombineTo(TheSelect, Load);
2372 // Users of the old loads now use the new load's chain. We know the
2373 // old-load value is dead now.
2374 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
2375 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
2383 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
2384 SDOperand N2, SDOperand N3,
2387 MVT::ValueType VT = N2.getValueType();
2388 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
2389 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
2390 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
2391 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
2393 // Determine if the condition we're dealing with is constant
2394 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2395 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2397 // fold select_cc true, x, y -> x
2398 if (SCCC && SCCC->getValue())
2400 // fold select_cc false, x, y -> y
2401 if (SCCC && SCCC->getValue() == 0)
2404 // Check to see if we can simplify the select into an fabs node
2405 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
2406 // Allow either -0.0 or 0.0
2407 if (CFP->getValue() == 0.0) {
2408 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
2409 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
2410 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
2411 N2 == N3.getOperand(0))
2412 return DAG.getNode(ISD::FABS, VT, N0);
2414 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
2415 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
2416 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
2417 N2.getOperand(0) == N3)
2418 return DAG.getNode(ISD::FABS, VT, N3);
2422 // Check to see if we can perform the "gzip trick", transforming
2423 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
2424 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
2425 MVT::isInteger(N0.getValueType()) &&
2426 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
2427 MVT::ValueType XType = N0.getValueType();
2428 MVT::ValueType AType = N2.getValueType();
2429 if (XType >= AType) {
2430 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
2431 // single-bit constant.
2432 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
2433 unsigned ShCtV = Log2_64(N2C->getValue());
2434 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
2435 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
2436 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
2437 AddToWorkList(Shift.Val);
2438 if (XType > AType) {
2439 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2440 AddToWorkList(Shift.Val);
2442 return DAG.getNode(ISD::AND, AType, Shift, N2);
2444 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2445 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2446 TLI.getShiftAmountTy()));
2447 AddToWorkList(Shift.Val);
2448 if (XType > AType) {
2449 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2450 AddToWorkList(Shift.Val);
2452 return DAG.getNode(ISD::AND, AType, Shift, N2);
2456 // fold select C, 16, 0 -> shl C, 4
2457 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
2458 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
2459 // Get a SetCC of the condition
2460 // FIXME: Should probably make sure that setcc is legal if we ever have a
2461 // target where it isn't.
2462 SDOperand Temp, SCC;
2463 // cast from setcc result type to select result type
2464 if (AfterLegalize) {
2465 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2466 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
2468 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
2469 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
2471 AddToWorkList(SCC.Val);
2472 AddToWorkList(Temp.Val);
2473 // shl setcc result by log2 n2c
2474 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
2475 DAG.getConstant(Log2_64(N2C->getValue()),
2476 TLI.getShiftAmountTy()));
2479 // Check to see if this is the equivalent of setcc
2480 // FIXME: Turn all of these into setcc if setcc if setcc is legal
2481 // otherwise, go ahead with the folds.
2482 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
2483 MVT::ValueType XType = N0.getValueType();
2484 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
2485 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2486 if (Res.getValueType() != VT)
2487 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
2491 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
2492 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
2493 TLI.isOperationLegal(ISD::CTLZ, XType)) {
2494 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
2495 return DAG.getNode(ISD::SRL, XType, Ctlz,
2496 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
2497 TLI.getShiftAmountTy()));
2499 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
2500 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
2501 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
2503 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
2504 DAG.getConstant(~0ULL, XType));
2505 return DAG.getNode(ISD::SRL, XType,
2506 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
2507 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2508 TLI.getShiftAmountTy()));
2510 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
2511 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
2512 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
2513 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2514 TLI.getShiftAmountTy()));
2515 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
2519 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
2520 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2521 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
2522 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
2523 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
2524 MVT::ValueType XType = N0.getValueType();
2525 if (SubC->isNullValue() && MVT::isInteger(XType)) {
2526 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2527 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2528 TLI.getShiftAmountTy()));
2529 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
2530 AddToWorkList(Shift.Val);
2531 AddToWorkList(Add.Val);
2532 return DAG.getNode(ISD::XOR, XType, Add, Shift);
2540 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
2541 SDOperand N1, ISD::CondCode Cond,
2542 bool foldBooleans) {
2543 // These setcc operations always fold.
2547 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
2549 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
2552 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
2553 uint64_t C1 = N1C->getValue();
2554 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
2555 uint64_t C0 = N0C->getValue();
2557 // Sign extend the operands if required
2558 if (ISD::isSignedIntSetCC(Cond)) {
2559 C0 = N0C->getSignExtended();
2560 C1 = N1C->getSignExtended();
2564 default: assert(0 && "Unknown integer setcc!");
2565 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2566 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2567 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
2568 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
2569 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
2570 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
2571 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
2572 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
2573 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
2574 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
2577 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2578 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2579 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
2581 // If the comparison constant has bits in the upper part, the
2582 // zero-extended value could never match.
2583 if (C1 & (~0ULL << InSize)) {
2584 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
2588 case ISD::SETEQ: return DAG.getConstant(0, VT);
2591 case ISD::SETNE: return DAG.getConstant(1, VT);
2594 // True if the sign bit of C1 is set.
2595 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
2598 // True if the sign bit of C1 isn't set.
2599 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
2605 // Otherwise, we can perform the comparison with the low bits.
2613 return DAG.getSetCC(VT, N0.getOperand(0),
2614 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
2617 break; // todo, be more careful with signed comparisons
2619 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2620 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2621 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2622 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
2623 MVT::ValueType ExtDstTy = N0.getValueType();
2624 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
2626 // If the extended part has any inconsistent bits, it cannot ever
2627 // compare equal. In other words, they have to be all ones or all
2630 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
2631 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
2632 return DAG.getConstant(Cond == ISD::SETNE, VT);
2635 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
2636 if (Op0Ty == ExtSrcTy) {
2637 ZextOp = N0.getOperand(0);
2639 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
2640 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
2641 DAG.getConstant(Imm, Op0Ty));
2643 AddToWorkList(ZextOp.Val);
2644 // Otherwise, make this a use of a zext.
2645 return DAG.getSetCC(VT, ZextOp,
2646 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
2649 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
2650 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2651 (N0.getOpcode() == ISD::XOR ||
2652 (N0.getOpcode() == ISD::AND &&
2653 N0.getOperand(0).getOpcode() == ISD::XOR &&
2654 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2655 isa<ConstantSDNode>(N0.getOperand(1)) &&
2656 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
2657 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
2658 // only do this if the top bits are known zero.
2659 if (TLI.MaskedValueIsZero(N1,
2660 MVT::getIntVTBitMask(N0.getValueType())-1)) {
2661 // Okay, get the un-inverted input value.
2663 if (N0.getOpcode() == ISD::XOR)
2664 Val = N0.getOperand(0);
2666 assert(N0.getOpcode() == ISD::AND &&
2667 N0.getOperand(0).getOpcode() == ISD::XOR);
2668 // ((X^1)&1)^1 -> X & 1
2669 Val = DAG.getNode(ISD::AND, N0.getValueType(),
2670 N0.getOperand(0).getOperand(0), N0.getOperand(1));
2672 return DAG.getSetCC(VT, Val, N1,
2673 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2677 uint64_t MinVal, MaxVal;
2678 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
2679 if (ISD::isSignedIntSetCC(Cond)) {
2680 MinVal = 1ULL << (OperandBitSize-1);
2681 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
2682 MaxVal = ~0ULL >> (65-OperandBitSize);
2687 MaxVal = ~0ULL >> (64-OperandBitSize);
2690 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2691 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2692 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2693 --C1; // X >= C0 --> X > (C0-1)
2694 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2695 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2698 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2699 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2700 ++C1; // X <= C0 --> X < (C0+1)
2701 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2702 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2705 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2706 return DAG.getConstant(0, VT); // X < MIN --> false
2708 // Canonicalize setgt X, Min --> setne X, Min
2709 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2710 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2711 // Canonicalize setlt X, Max --> setne X, Max
2712 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2713 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2715 // If we have setult X, 1, turn it into seteq X, 0
2716 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2717 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
2719 // If we have setugt X, Max-1, turn it into seteq X, Max
2720 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2721 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
2724 // If we have "setcc X, C0", check to see if we can shrink the immediate
2727 // SETUGT X, SINTMAX -> SETLT X, 0
2728 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
2729 C1 == (~0ULL >> (65-OperandBitSize)))
2730 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
2733 // FIXME: Implement the rest of these.
2735 // Fold bit comparisons when we can.
2736 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2737 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
2738 if (ConstantSDNode *AndRHS =
2739 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2740 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2741 // Perform the xform if the AND RHS is a single bit.
2742 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
2743 return DAG.getNode(ISD::SRL, VT, N0,
2744 DAG.getConstant(Log2_64(AndRHS->getValue()),
2745 TLI.getShiftAmountTy()));
2747 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
2748 // (X & 8) == 8 --> (X & 8) >> 3
2749 // Perform the xform if C1 is a single bit.
2750 if ((C1 & (C1-1)) == 0) {
2751 return DAG.getNode(ISD::SRL, VT, N0,
2752 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
2757 } else if (isa<ConstantSDNode>(N0.Val)) {
2758 // Ensure that the constant occurs on the RHS.
2759 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2762 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
2763 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
2764 double C0 = N0C->getValue(), C1 = N1C->getValue();
2767 default: break; // FIXME: Implement the rest of these!
2768 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2769 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2770 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
2771 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
2772 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
2773 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
2776 // Ensure that the constant occurs on the RHS.
2777 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2781 // We can always fold X == Y for integer setcc's.
2782 if (MVT::isInteger(N0.getValueType()))
2783 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2784 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2785 if (UOF == 2) // FP operators that are undefined on NaNs.
2786 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2787 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2788 return DAG.getConstant(UOF, VT);
2789 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2790 // if it is not already.
2791 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2792 if (NewCond != Cond)
2793 return DAG.getSetCC(VT, N0, N1, NewCond);
2796 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2797 MVT::isInteger(N0.getValueType())) {
2798 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2799 N0.getOpcode() == ISD::XOR) {
2800 // Simplify (X+Y) == (X+Z) --> Y == Z
2801 if (N0.getOpcode() == N1.getOpcode()) {
2802 if (N0.getOperand(0) == N1.getOperand(0))
2803 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2804 if (N0.getOperand(1) == N1.getOperand(1))
2805 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2806 if (isCommutativeBinOp(N0.getOpcode())) {
2807 // If X op Y == Y op X, try other combinations.
2808 if (N0.getOperand(0) == N1.getOperand(1))
2809 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2810 if (N0.getOperand(1) == N1.getOperand(0))
2811 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
2815 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2816 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2817 // Turn (X+C1) == C2 --> X == C2-C1
2818 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
2819 return DAG.getSetCC(VT, N0.getOperand(0),
2820 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
2821 N0.getValueType()), Cond);
2824 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2825 if (N0.getOpcode() == ISD::XOR)
2826 // If we know that all of the inverted bits are zero, don't bother
2827 // performing the inversion.
2828 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
2829 return DAG.getSetCC(VT, N0.getOperand(0),
2830 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
2831 N0.getValueType()), Cond);
2834 // Turn (C1-X) == C2 --> X == C1-C2
2835 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2836 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
2837 return DAG.getSetCC(VT, N0.getOperand(1),
2838 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
2839 N0.getValueType()), Cond);
2844 // Simplify (X+Z) == X --> Z == 0
2845 if (N0.getOperand(0) == N1)
2846 return DAG.getSetCC(VT, N0.getOperand(1),
2847 DAG.getConstant(0, N0.getValueType()), Cond);
2848 if (N0.getOperand(1) == N1) {
2849 if (isCommutativeBinOp(N0.getOpcode()))
2850 return DAG.getSetCC(VT, N0.getOperand(0),
2851 DAG.getConstant(0, N0.getValueType()), Cond);
2853 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2854 // (Z-X) == X --> Z == X<<1
2855 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2857 DAG.getConstant(1,TLI.getShiftAmountTy()));
2858 AddToWorkList(SH.Val);
2859 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2864 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2865 N1.getOpcode() == ISD::XOR) {
2866 // Simplify X == (X+Z) --> Z == 0
2867 if (N1.getOperand(0) == N0) {
2868 return DAG.getSetCC(VT, N1.getOperand(1),
2869 DAG.getConstant(0, N1.getValueType()), Cond);
2870 } else if (N1.getOperand(1) == N0) {
2871 if (isCommutativeBinOp(N1.getOpcode())) {
2872 return DAG.getSetCC(VT, N1.getOperand(0),
2873 DAG.getConstant(0, N1.getValueType()), Cond);
2875 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2876 // X == (Z-X) --> X<<1 == Z
2877 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2878 DAG.getConstant(1,TLI.getShiftAmountTy()));
2879 AddToWorkList(SH.Val);
2880 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2886 // Fold away ALL boolean setcc's.
2888 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2890 default: assert(0 && "Unknown integer setcc!");
2891 case ISD::SETEQ: // X == Y -> (X^Y)^1
2892 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2893 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2894 AddToWorkList(Temp.Val);
2896 case ISD::SETNE: // X != Y --> (X^Y)
2897 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2899 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
2900 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
2901 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2902 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2903 AddToWorkList(Temp.Val);
2905 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
2906 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
2907 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2908 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2909 AddToWorkList(Temp.Val);
2911 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
2912 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
2913 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2914 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2915 AddToWorkList(Temp.Val);
2917 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
2918 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
2919 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2920 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2923 if (VT != MVT::i1) {
2924 AddToWorkList(N0.Val);
2925 // FIXME: If running after legalize, we probably can't do this.
2926 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2931 // Could not fold it.
2935 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2936 /// return a DAG expression to select that will generate the same value by
2937 /// multiplying by a magic number. See:
2938 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2939 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
2940 MVT::ValueType VT = N->getValueType(0);
2942 // Check to see if we can do this.
2943 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2944 return SDOperand(); // BuildSDIV only operates on i32 or i64
2945 if (!TLI.isOperationLegal(ISD::MULHS, VT))
2946 return SDOperand(); // Make sure the target supports MULHS.
2948 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
2949 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
2951 // Multiply the numerator (operand 0) by the magic value
2952 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
2953 DAG.getConstant(magics.m, VT));
2954 // If d > 0 and m < 0, add the numerator
2955 if (d > 0 && magics.m < 0) {
2956 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
2957 AddToWorkList(Q.Val);
2959 // If d < 0 and m > 0, subtract the numerator.
2960 if (d < 0 && magics.m > 0) {
2961 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
2962 AddToWorkList(Q.Val);
2964 // Shift right algebraic if shift value is nonzero
2966 Q = DAG.getNode(ISD::SRA, VT, Q,
2967 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2968 AddToWorkList(Q.Val);
2970 // Extract the sign bit and add it to the quotient
2972 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
2973 TLI.getShiftAmountTy()));
2974 AddToWorkList(T.Val);
2975 return DAG.getNode(ISD::ADD, VT, Q, T);
2978 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2979 /// return a DAG expression to select that will generate the same value by
2980 /// multiplying by a magic number. See:
2981 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2982 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
2983 MVT::ValueType VT = N->getValueType(0);
2985 // Check to see if we can do this.
2986 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2987 return SDOperand(); // BuildUDIV only operates on i32 or i64
2988 if (!TLI.isOperationLegal(ISD::MULHU, VT))
2989 return SDOperand(); // Make sure the target supports MULHU.
2991 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
2992 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
2994 // Multiply the numerator (operand 0) by the magic value
2995 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
2996 DAG.getConstant(magics.m, VT));
2997 AddToWorkList(Q.Val);
2999 if (magics.a == 0) {
3000 return DAG.getNode(ISD::SRL, VT, Q,
3001 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
3003 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
3004 AddToWorkList(NPQ.Val);
3005 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
3006 DAG.getConstant(1, TLI.getShiftAmountTy()));
3007 AddToWorkList(NPQ.Val);
3008 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
3009 AddToWorkList(NPQ.Val);
3010 return DAG.getNode(ISD::SRL, VT, NPQ,
3011 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
3015 // SelectionDAG::Combine - This is the entry point for the file.
3017 void SelectionDAG::Combine(bool RunningAfterLegalize) {
3018 /// run - This is the main entry point to this class.
3020 DAGCombiner(*this).Run(RunningAfterLegalize);