1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "dagcombine"
16 #include "llvm/CodeGen/SelectionDAG.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/Analysis/AliasAnalysis.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetFrameInfo.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/SmallPtrSet.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
35 STATISTIC(NodesCombined , "Number of dag nodes combined");
36 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
37 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
41 CombinerAA("combiner-alias-analysis", cl::Hidden,
42 cl::desc("Turn on alias analysis during testing"));
45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
46 cl::desc("Include global information in alias analysis"));
48 //------------------------------ DAGCombiner ---------------------------------//
50 class VISIBILITY_HIDDEN DAGCombiner {
52 const TargetLowering &TLI;
58 // Worklist of all of the nodes that need to be simplified.
59 std::vector<SDNode*> WorkList;
61 // AA - Used for DAG load/store alias analysis.
64 /// AddUsersToWorkList - When an instruction is simplified, add all users of
65 /// the instruction to the work lists because they might get more simplified
68 void AddUsersToWorkList(SDNode *N) {
69 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
74 /// visit - call the node-specific routine that knows how to fold each
75 /// particular type of node.
76 SDValue visit(SDNode *N);
79 /// AddToWorkList - Add to the work list making sure it's instance is at the
80 /// the back (next to be processed.)
81 void AddToWorkList(SDNode *N) {
82 removeFromWorkList(N);
83 WorkList.push_back(N);
86 /// removeFromWorkList - remove all instances of N from the worklist.
88 void removeFromWorkList(SDNode *N) {
89 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
93 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
96 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
97 return CombineTo(N, &Res, 1, AddTo);
100 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
102 SDValue To[] = { Res0, Res1 };
103 return CombineTo(N, To, 2, AddTo);
106 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
110 /// SimplifyDemandedBits - Check the specified integer node value to see if
111 /// it can be simplified or if things it uses can be simplified by bit
112 /// propagation. If so, return true.
113 bool SimplifyDemandedBits(SDValue Op) {
114 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits());
115 return SimplifyDemandedBits(Op, Demanded);
118 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
120 bool CombineToPreIndexedLoadStore(SDNode *N);
121 bool CombineToPostIndexedLoadStore(SDNode *N);
124 /// combine - call the node-specific routine that knows how to fold each
125 /// particular type of node. If that doesn't do anything, try the
126 /// target-specific DAG combines.
127 SDValue combine(SDNode *N);
129 // Visitation implementation - Implement dag node combining for different
130 // node types. The semantics are as follows:
132 // SDValue.getNode() == 0 - No change was made
133 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
134 // otherwise - N should be replaced by the returned Operand.
136 SDValue visitTokenFactor(SDNode *N);
137 SDValue visitMERGE_VALUES(SDNode *N);
138 SDValue visitADD(SDNode *N);
139 SDValue visitSUB(SDNode *N);
140 SDValue visitADDC(SDNode *N);
141 SDValue visitADDE(SDNode *N);
142 SDValue visitMUL(SDNode *N);
143 SDValue visitSDIV(SDNode *N);
144 SDValue visitUDIV(SDNode *N);
145 SDValue visitSREM(SDNode *N);
146 SDValue visitUREM(SDNode *N);
147 SDValue visitMULHU(SDNode *N);
148 SDValue visitMULHS(SDNode *N);
149 SDValue visitSMUL_LOHI(SDNode *N);
150 SDValue visitUMUL_LOHI(SDNode *N);
151 SDValue visitSDIVREM(SDNode *N);
152 SDValue visitUDIVREM(SDNode *N);
153 SDValue visitAND(SDNode *N);
154 SDValue visitOR(SDNode *N);
155 SDValue visitXOR(SDNode *N);
156 SDValue SimplifyVBinOp(SDNode *N);
157 SDValue visitSHL(SDNode *N);
158 SDValue visitSRA(SDNode *N);
159 SDValue visitSRL(SDNode *N);
160 SDValue visitCTLZ(SDNode *N);
161 SDValue visitCTTZ(SDNode *N);
162 SDValue visitCTPOP(SDNode *N);
163 SDValue visitSELECT(SDNode *N);
164 SDValue visitSELECT_CC(SDNode *N);
165 SDValue visitSETCC(SDNode *N);
166 SDValue visitSIGN_EXTEND(SDNode *N);
167 SDValue visitZERO_EXTEND(SDNode *N);
168 SDValue visitANY_EXTEND(SDNode *N);
169 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
170 SDValue visitTRUNCATE(SDNode *N);
171 SDValue visitBIT_CONVERT(SDNode *N);
172 SDValue visitBUILD_PAIR(SDNode *N);
173 SDValue visitFADD(SDNode *N);
174 SDValue visitFSUB(SDNode *N);
175 SDValue visitFMUL(SDNode *N);
176 SDValue visitFDIV(SDNode *N);
177 SDValue visitFREM(SDNode *N);
178 SDValue visitFCOPYSIGN(SDNode *N);
179 SDValue visitSINT_TO_FP(SDNode *N);
180 SDValue visitUINT_TO_FP(SDNode *N);
181 SDValue visitFP_TO_SINT(SDNode *N);
182 SDValue visitFP_TO_UINT(SDNode *N);
183 SDValue visitFP_ROUND(SDNode *N);
184 SDValue visitFP_ROUND_INREG(SDNode *N);
185 SDValue visitFP_EXTEND(SDNode *N);
186 SDValue visitFNEG(SDNode *N);
187 SDValue visitFABS(SDNode *N);
188 SDValue visitBRCOND(SDNode *N);
189 SDValue visitBR_CC(SDNode *N);
190 SDValue visitLOAD(SDNode *N);
191 SDValue visitSTORE(SDNode *N);
192 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
193 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
194 SDValue visitBUILD_VECTOR(SDNode *N);
195 SDValue visitCONCAT_VECTORS(SDNode *N);
196 SDValue visitVECTOR_SHUFFLE(SDNode *N);
198 SDValue XformToShuffleWithZero(SDNode *N);
199 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
201 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
203 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
204 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
205 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2);
206 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2,
207 SDValue N3, ISD::CondCode CC,
208 bool NotExtCompare = false);
209 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
210 bool foldBooleans = true);
211 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
213 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
214 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
215 SDValue BuildSDIV(SDNode *N);
216 SDValue BuildUDIV(SDNode *N);
217 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
218 SDValue ReduceLoadWidth(SDNode *N);
220 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
222 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
223 /// looking for aliasing nodes and adding them to the Aliases vector.
224 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
225 SmallVector<SDValue, 8> &Aliases);
227 /// isAlias - Return true if there is any possibility that the two addresses
229 bool isAlias(SDValue Ptr1, int64_t Size1,
230 const Value *SrcValue1, int SrcValueOffset1,
231 SDValue Ptr2, int64_t Size2,
232 const Value *SrcValue2, int SrcValueOffset2);
234 /// FindAliasInfo - Extracts the relevant alias information from the memory
235 /// node. Returns true if the operand was a load.
236 bool FindAliasInfo(SDNode *N,
237 SDValue &Ptr, int64_t &Size,
238 const Value *&SrcValue, int &SrcValueOffset);
240 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
241 /// looking for a better chain (aliasing node.)
242 SDValue FindBetterChain(SDNode *N, SDValue Chain);
245 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
247 TLI(D.getTargetLoweringInfo()),
249 LegalOperations(false),
254 /// Run - runs the dag combiner on all nodes in the work list
255 void Run(CombineLevel AtLevel);
261 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
262 /// nodes from the worklist.
263 class VISIBILITY_HIDDEN WorkListRemover :
264 public SelectionDAG::DAGUpdateListener {
267 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
269 virtual void NodeDeleted(SDNode *N, SDNode *E) {
270 DC.removeFromWorkList(N);
273 virtual void NodeUpdated(SDNode *N) {
279 //===----------------------------------------------------------------------===//
280 // TargetLowering::DAGCombinerInfo implementation
281 //===----------------------------------------------------------------------===//
283 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
284 ((DAGCombiner*)DC)->AddToWorkList(N);
287 SDValue TargetLowering::DAGCombinerInfo::
288 CombineTo(SDNode *N, const std::vector<SDValue> &To) {
289 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
292 SDValue TargetLowering::DAGCombinerInfo::
293 CombineTo(SDNode *N, SDValue Res) {
294 return ((DAGCombiner*)DC)->CombineTo(N, Res);
298 SDValue TargetLowering::DAGCombinerInfo::
299 CombineTo(SDNode *N, SDValue Res0, SDValue Res1) {
300 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
303 void TargetLowering::DAGCombinerInfo::
304 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
305 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
308 //===----------------------------------------------------------------------===//
310 //===----------------------------------------------------------------------===//
312 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
313 /// specified expression for the same cost as the expression itself, or 2 if we
314 /// can compute the negated form more cheaply than the expression itself.
315 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
316 unsigned Depth = 0) {
317 // No compile time optimizations on this type.
318 if (Op.getValueType() == MVT::ppcf128)
321 // fneg is removable even if it has multiple uses.
322 if (Op.getOpcode() == ISD::FNEG) return 2;
324 // Don't allow anything with multiple uses.
325 if (!Op.hasOneUse()) return 0;
327 // Don't recurse exponentially.
328 if (Depth > 6) return 0;
330 switch (Op.getOpcode()) {
331 default: return false;
332 case ISD::ConstantFP:
333 // Don't invert constant FP values after legalize. The negated constant
334 // isn't necessarily legal.
335 return LegalOperations ? 0 : 1;
337 // FIXME: determine better conditions for this xform.
338 if (!UnsafeFPMath) return 0;
341 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
344 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
346 // We can't turn -(A-B) into B-A when we honor signed zeros.
347 if (!UnsafeFPMath) return 0;
354 if (HonorSignDependentRoundingFPMath()) return 0;
356 // -(X*Y) -> (-X * Y) or (X*-Y)
357 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
360 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
365 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
369 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
370 /// returns the newly negated expression.
371 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
372 bool LegalOperations, unsigned Depth = 0) {
373 // fneg is removable even if it has multiple uses.
374 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
376 // Don't allow anything with multiple uses.
377 assert(Op.hasOneUse() && "Unknown reuse!");
379 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
380 switch (Op.getOpcode()) {
381 default: assert(0 && "Unknown code");
382 case ISD::ConstantFP: {
383 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
385 return DAG.getConstantFP(V, Op.getValueType());
388 // FIXME: determine better conditions for this xform.
389 assert(UnsafeFPMath);
392 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
393 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
394 GetNegatedExpression(Op.getOperand(0), DAG,
395 LegalOperations, Depth+1),
398 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
399 GetNegatedExpression(Op.getOperand(1), DAG,
400 LegalOperations, Depth+1),
403 // We can't turn -(A-B) into B-A when we honor signed zeros.
404 assert(UnsafeFPMath);
407 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
408 if (N0CFP->getValueAPF().isZero())
409 return Op.getOperand(1);
412 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
413 Op.getOperand(1), Op.getOperand(0));
417 assert(!HonorSignDependentRoundingFPMath());
420 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
421 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
422 GetNegatedExpression(Op.getOperand(0), DAG,
423 LegalOperations, Depth+1),
427 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
429 GetNegatedExpression(Op.getOperand(1), DAG,
430 LegalOperations, Depth+1));
434 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
435 GetNegatedExpression(Op.getOperand(0), DAG,
436 LegalOperations, Depth+1));
438 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
439 GetNegatedExpression(Op.getOperand(0), DAG,
440 LegalOperations, Depth+1),
446 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
447 // that selects between the values 1 and 0, making it equivalent to a setcc.
448 // Also, set the incoming LHS, RHS, and CC references to the appropriate
449 // nodes based on the type of node we are checking. This simplifies life a
450 // bit for the callers.
451 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
453 if (N.getOpcode() == ISD::SETCC) {
454 LHS = N.getOperand(0);
455 RHS = N.getOperand(1);
456 CC = N.getOperand(2);
459 if (N.getOpcode() == ISD::SELECT_CC &&
460 N.getOperand(2).getOpcode() == ISD::Constant &&
461 N.getOperand(3).getOpcode() == ISD::Constant &&
462 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
463 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
464 LHS = N.getOperand(0);
465 RHS = N.getOperand(1);
466 CC = N.getOperand(4);
472 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
473 // one use. If this is true, it allows the users to invert the operation for
474 // free when it is profitable to do so.
475 static bool isOneUseSetCC(SDValue N) {
477 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
482 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
483 SDValue N0, SDValue N1) {
484 MVT VT = N0.getValueType();
485 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
486 if (isa<ConstantSDNode>(N1)) {
487 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
489 DAG.FoldConstantArithmetic(Opc, VT,
490 cast<ConstantSDNode>(N0.getOperand(1)),
491 cast<ConstantSDNode>(N1));
492 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
493 } else if (N0.hasOneUse()) {
494 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
495 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
496 N0.getOperand(0), N1);
497 AddToWorkList(OpNode.getNode());
498 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
502 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
503 if (isa<ConstantSDNode>(N0)) {
504 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
506 DAG.FoldConstantArithmetic(Opc, VT,
507 cast<ConstantSDNode>(N1.getOperand(1)),
508 cast<ConstantSDNode>(N0));
509 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
510 } else if (N1.hasOneUse()) {
511 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
512 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
513 N1.getOperand(0), N0);
514 AddToWorkList(OpNode.getNode());
515 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
522 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
524 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
526 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
527 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG));
528 DOUT << " and " << NumTo-1 << " other values\n";
529 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i)
530 assert(N->getValueType(i) == To[i].getValueType() &&
531 "Cannot combine value to value of different type!"));
532 WorkListRemover DeadNodes(*this);
533 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
536 // Push the new nodes and any users onto the worklist
537 for (unsigned i = 0, e = NumTo; i != e; ++i) {
538 AddToWorkList(To[i].getNode());
539 AddUsersToWorkList(To[i].getNode());
543 // Finally, if the node is now dead, remove it from the graph. The node
544 // may not be dead if the replacement process recursively simplified to
545 // something else needing this node.
546 if (N->use_empty()) {
547 // Nodes can be reintroduced into the worklist. Make sure we do not
548 // process a node that has been replaced.
549 removeFromWorkList(N);
551 // Finally, since the node is now dead, remove it from the graph.
554 return SDValue(N, 0);
558 DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &
560 // Replace all uses. If any nodes become isomorphic to other nodes and
561 // are deleted, make sure to remove them from our worklist.
562 WorkListRemover DeadNodes(*this);
563 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
565 // Push the new node and any (possibly new) users onto the worklist.
566 AddToWorkList(TLO.New.getNode());
567 AddUsersToWorkList(TLO.New.getNode());
569 // Finally, if the node is now dead, remove it from the graph. The node
570 // may not be dead if the replacement process recursively simplified to
571 // something else needing this node.
572 if (TLO.Old.getNode()->use_empty()) {
573 removeFromWorkList(TLO.Old.getNode());
575 // If the operands of this node are only used by the node, they will now
576 // be dead. Make sure to visit them first to delete dead nodes early.
577 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
578 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
579 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
581 DAG.DeleteNode(TLO.Old.getNode());
585 /// SimplifyDemandedBits - Check the specified integer node value to see if
586 /// it can be simplified or if things it uses can be simplified by bit
587 /// propagation. If so, return true.
588 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
589 TargetLowering::TargetLoweringOpt TLO(DAG);
590 APInt KnownZero, KnownOne;
591 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
595 AddToWorkList(Op.getNode());
597 // Replace the old value with the new one.
599 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
600 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
603 CommitTargetLoweringOpt(TLO);
607 //===----------------------------------------------------------------------===//
608 // Main DAG Combiner implementation
609 //===----------------------------------------------------------------------===//
611 void DAGCombiner::Run(CombineLevel AtLevel) {
612 // set the instance variables, so that the various visit routines may use it.
614 LegalOperations = Level >= NoIllegalOperations;
615 LegalTypes = Level >= NoIllegalTypes;
617 // Add all the dag nodes to the worklist.
618 WorkList.reserve(DAG.allnodes_size());
619 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
620 E = DAG.allnodes_end(); I != E; ++I)
621 WorkList.push_back(I);
623 // Create a dummy node (which is not added to allnodes), that adds a reference
624 // to the root node, preventing it from being deleted, and tracking any
625 // changes of the root.
626 HandleSDNode Dummy(DAG.getRoot());
628 // The root of the dag may dangle to deleted nodes until the dag combiner is
629 // done. Set it to null to avoid confusion.
630 DAG.setRoot(SDValue());
632 // while the worklist isn't empty, inspect the node on the end of it and
633 // try and combine it.
634 while (!WorkList.empty()) {
635 SDNode *N = WorkList.back();
638 // If N has no uses, it is dead. Make sure to revisit all N's operands once
639 // N is deleted from the DAG, since they too may now be dead or may have a
640 // reduced number of uses, allowing other xforms.
641 if (N->use_empty() && N != &Dummy) {
642 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
643 AddToWorkList(N->getOperand(i).getNode());
649 SDValue RV = combine(N);
651 if (RV.getNode() == 0)
656 // If we get back the same node we passed in, rather than a new node or
657 // zero, we know that the node must have defined multiple values and
658 // CombineTo was used. Since CombineTo takes care of the worklist
659 // mechanics for us, we have no work to do in this case.
660 if (RV.getNode() == N)
663 assert(N->getOpcode() != ISD::DELETED_NODE &&
664 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
665 "Node was deleted but visit returned new node!");
667 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
668 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG));
670 WorkListRemover DeadNodes(*this);
671 if (N->getNumValues() == RV.getNode()->getNumValues())
672 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
674 assert(N->getValueType(0) == RV.getValueType() &&
675 N->getNumValues() == 1 && "Type mismatch");
677 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
680 // Push the new node and any users onto the worklist
681 AddToWorkList(RV.getNode());
682 AddUsersToWorkList(RV.getNode());
684 // Add any uses of the old node to the worklist in case this node is the
685 // last one that uses them. They may become dead after this node is
687 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
688 AddToWorkList(N->getOperand(i).getNode());
690 // Finally, if the node is now dead, remove it from the graph. The node
691 // may not be dead if the replacement process recursively simplified to
692 // something else needing this node.
693 if (N->use_empty()) {
694 // Nodes can be reintroduced into the worklist. Make sure we do not
695 // process a node that has been replaced.
696 removeFromWorkList(N);
698 // Finally, since the node is now dead, remove it from the graph.
703 // If the root changed (e.g. it was a dead load, update the root).
704 DAG.setRoot(Dummy.getValue());
707 SDValue DAGCombiner::visit(SDNode *N) {
708 switch(N->getOpcode()) {
710 case ISD::TokenFactor: return visitTokenFactor(N);
711 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
712 case ISD::ADD: return visitADD(N);
713 case ISD::SUB: return visitSUB(N);
714 case ISD::ADDC: return visitADDC(N);
715 case ISD::ADDE: return visitADDE(N);
716 case ISD::MUL: return visitMUL(N);
717 case ISD::SDIV: return visitSDIV(N);
718 case ISD::UDIV: return visitUDIV(N);
719 case ISD::SREM: return visitSREM(N);
720 case ISD::UREM: return visitUREM(N);
721 case ISD::MULHU: return visitMULHU(N);
722 case ISD::MULHS: return visitMULHS(N);
723 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
724 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
725 case ISD::SDIVREM: return visitSDIVREM(N);
726 case ISD::UDIVREM: return visitUDIVREM(N);
727 case ISD::AND: return visitAND(N);
728 case ISD::OR: return visitOR(N);
729 case ISD::XOR: return visitXOR(N);
730 case ISD::SHL: return visitSHL(N);
731 case ISD::SRA: return visitSRA(N);
732 case ISD::SRL: return visitSRL(N);
733 case ISD::CTLZ: return visitCTLZ(N);
734 case ISD::CTTZ: return visitCTTZ(N);
735 case ISD::CTPOP: return visitCTPOP(N);
736 case ISD::SELECT: return visitSELECT(N);
737 case ISD::SELECT_CC: return visitSELECT_CC(N);
738 case ISD::SETCC: return visitSETCC(N);
739 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
740 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
741 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
742 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
743 case ISD::TRUNCATE: return visitTRUNCATE(N);
744 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
745 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
746 case ISD::FADD: return visitFADD(N);
747 case ISD::FSUB: return visitFSUB(N);
748 case ISD::FMUL: return visitFMUL(N);
749 case ISD::FDIV: return visitFDIV(N);
750 case ISD::FREM: return visitFREM(N);
751 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
752 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
753 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
754 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
755 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
756 case ISD::FP_ROUND: return visitFP_ROUND(N);
757 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
758 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
759 case ISD::FNEG: return visitFNEG(N);
760 case ISD::FABS: return visitFABS(N);
761 case ISD::BRCOND: return visitBRCOND(N);
762 case ISD::BR_CC: return visitBR_CC(N);
763 case ISD::LOAD: return visitLOAD(N);
764 case ISD::STORE: return visitSTORE(N);
765 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
766 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
767 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
768 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
769 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
774 SDValue DAGCombiner::combine(SDNode *N) {
775 SDValue RV = visit(N);
777 // If nothing happened, try a target-specific DAG combine.
778 if (RV.getNode() == 0) {
779 assert(N->getOpcode() != ISD::DELETED_NODE &&
780 "Node was deleted but visit returned NULL!");
782 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
783 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
785 // Expose the DAG combiner to the target combiner impls.
786 TargetLowering::DAGCombinerInfo
787 DagCombineInfo(DAG, Level == Unrestricted, false, this);
789 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
793 // If N is a commutative binary node, try commuting it to enable more
795 if (RV.getNode() == 0 &&
796 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
797 N->getNumValues() == 1) {
798 SDValue N0 = N->getOperand(0);
799 SDValue N1 = N->getOperand(1);
801 // Constant operands are canonicalized to RHS.
802 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
803 SDValue Ops[] = { N1, N0 };
804 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
807 return SDValue(CSENode, 0);
814 /// getInputChainForNode - Given a node, return its input chain if it has one,
815 /// otherwise return a null sd operand.
816 static SDValue getInputChainForNode(SDNode *N) {
817 if (unsigned NumOps = N->getNumOperands()) {
818 if (N->getOperand(0).getValueType() == MVT::Other)
819 return N->getOperand(0);
820 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
821 return N->getOperand(NumOps-1);
822 for (unsigned i = 1; i < NumOps-1; ++i)
823 if (N->getOperand(i).getValueType() == MVT::Other)
824 return N->getOperand(i);
829 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
830 // If N has two operands, where one has an input chain equal to the other,
831 // the 'other' chain is redundant.
832 if (N->getNumOperands() == 2) {
833 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
834 return N->getOperand(0);
835 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
836 return N->getOperand(1);
839 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
840 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
841 SmallPtrSet<SDNode*, 16> SeenOps;
842 bool Changed = false; // If we should replace this token factor.
844 // Start out with this token factor.
847 // Iterate through token factors. The TFs grows when new token factors are
849 for (unsigned i = 0; i < TFs.size(); ++i) {
852 // Check each of the operands.
853 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
854 SDValue Op = TF->getOperand(i);
856 switch (Op.getOpcode()) {
857 case ISD::EntryToken:
858 // Entry tokens don't need to be added to the list. They are
863 case ISD::TokenFactor:
864 if ((CombinerAA || Op.hasOneUse()) &&
865 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
866 // Queue up for processing.
867 TFs.push_back(Op.getNode());
868 // Clean up in case the token factor is removed.
869 AddToWorkList(Op.getNode());
876 // Only add if it isn't already in the list.
877 if (SeenOps.insert(Op.getNode()))
888 // If we've change things around then replace token factor.
891 // The entry token is the only possible outcome.
892 Result = DAG.getEntryNode();
894 // New and improved token factor.
895 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
896 MVT::Other, &Ops[0], Ops.size());
899 // Don't add users to work list.
900 return CombineTo(N, Result, false);
906 /// MERGE_VALUES can always be eliminated.
907 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
908 WorkListRemover DeadNodes(*this);
909 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
910 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
912 removeFromWorkList(N);
914 return SDValue(N, 0); // Return N so it doesn't get rechecked!
918 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
920 MVT VT = N0.getValueType();
921 SDValue N00 = N0.getOperand(0);
922 SDValue N01 = N0.getOperand(1);
923 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
925 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
926 isa<ConstantSDNode>(N00.getOperand(1))) {
927 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
928 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
929 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
930 N00.getOperand(0), N01),
931 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
932 N00.getOperand(1), N01));
933 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
940 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
941 SelectionDAG &DAG, const TargetLowering &TLI,
942 bool LegalOperations) {
943 MVT VT = N->getValueType(0);
944 unsigned Opc = N->getOpcode();
945 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
946 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
947 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
948 ISD::CondCode CC = ISD::SETCC_INVALID;
951 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
953 SDValue CCOp = Slct.getOperand(0);
954 if (CCOp.getOpcode() == ISD::SETCC)
955 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
958 bool DoXform = false;
960 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
963 if (LHS.getOpcode() == ISD::Constant &&
964 cast<ConstantSDNode>(LHS)->isNullValue()) {
966 } else if (CC != ISD::SETCC_INVALID &&
967 RHS.getOpcode() == ISD::Constant &&
968 cast<ConstantSDNode>(RHS)->isNullValue()) {
970 SDValue Op0 = Slct.getOperand(0);
971 MVT OpVT = isSlctCC ? Op0.getValueType() :
972 Op0.getOperand(0).getValueType();
973 bool isInt = OpVT.isInteger();
974 CC = ISD::getSetCCInverse(CC, isInt);
976 if (LegalOperations && !TLI.isCondCodeLegal(CC, OpVT))
977 return SDValue(); // Inverse operator isn't legal.
984 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
986 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
987 Slct.getOperand(0), Slct.getOperand(1), CC);
988 SDValue CCOp = Slct.getOperand(0);
990 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
991 CCOp.getOperand(0), CCOp.getOperand(1), CC);
992 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
993 CCOp, OtherOp, Result);
998 SDValue DAGCombiner::visitADD(SDNode *N) {
999 SDValue N0 = N->getOperand(0);
1000 SDValue N1 = N->getOperand(1);
1001 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1002 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1003 MVT VT = N0.getValueType();
1006 if (VT.isVector()) {
1007 SDValue FoldedVOp = SimplifyVBinOp(N);
1008 if (FoldedVOp.getNode()) return FoldedVOp;
1011 // fold (add x, undef) -> undef
1012 if (N0.getOpcode() == ISD::UNDEF)
1014 if (N1.getOpcode() == ISD::UNDEF)
1016 // fold (add c1, c2) -> c1+c2
1018 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1019 // canonicalize constant to RHS
1021 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1022 // fold (add x, 0) -> x
1023 if (N1C && N1C->isNullValue())
1025 // fold (add Sym, c) -> Sym+c
1026 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1027 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1028 GA->getOpcode() == ISD::GlobalAddress)
1029 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1031 (uint64_t)N1C->getSExtValue());
1032 // fold ((c1-A)+c2) -> (c1+c2)-A
1033 if (N1C && N0.getOpcode() == ISD::SUB)
1034 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1035 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1036 DAG.getConstant(N1C->getAPIntValue()+
1037 N0C->getAPIntValue(), VT),
1040 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1041 if (RADD.getNode() != 0)
1043 // fold ((0-A) + B) -> B-A
1044 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1045 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1046 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1047 // fold (A + (0-B)) -> A-B
1048 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1049 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1050 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1051 // fold (A+(B-A)) -> B
1052 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1053 return N1.getOperand(0);
1054 // fold ((B-A)+A) -> B
1055 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1056 return N0.getOperand(0);
1057 // fold (A+(B-(A+C))) to (B-C)
1058 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1059 N0 == N1.getOperand(1).getOperand(0))
1060 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1061 N1.getOperand(1).getOperand(1));
1062 // fold (A+(B-(C+A))) to (B-C)
1063 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1064 N0 == N1.getOperand(1).getOperand(1))
1065 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1066 N1.getOperand(1).getOperand(0));
1067 // fold (A+((B-A)+or-C)) to (B+or-C)
1068 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1069 N1.getOperand(0).getOpcode() == ISD::SUB &&
1070 N0 == N1.getOperand(0).getOperand(1))
1071 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1072 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1074 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1075 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1076 SDValue N00 = N0.getOperand(0);
1077 SDValue N01 = N0.getOperand(1);
1078 SDValue N10 = N1.getOperand(0);
1079 SDValue N11 = N1.getOperand(1);
1081 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1082 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1083 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1084 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1087 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1088 return SDValue(N, 0);
1090 // fold (a+b) -> (a|b) iff a and b share no bits.
1091 if (VT.isInteger() && !VT.isVector()) {
1092 APInt LHSZero, LHSOne;
1093 APInt RHSZero, RHSOne;
1094 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1095 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1097 if (LHSZero.getBoolValue()) {
1098 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1100 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1101 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1102 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1103 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1104 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1108 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1109 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1110 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1111 if (Result.getNode()) return Result;
1113 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1114 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1115 if (Result.getNode()) return Result;
1118 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
1119 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
1120 SDValue Result = combineSelectAndUse(N, N0, N1, DAG, TLI, LegalOperations);
1121 if (Result.getNode()) return Result;
1123 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1124 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations);
1125 if (Result.getNode()) return Result;
1131 SDValue DAGCombiner::visitADDC(SDNode *N) {
1132 SDValue N0 = N->getOperand(0);
1133 SDValue N1 = N->getOperand(1);
1134 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1135 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1136 MVT VT = N0.getValueType();
1138 // If the flag result is dead, turn this into an ADD.
1139 if (N->hasNUsesOfValue(0, 1))
1140 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1141 DAG.getNode(ISD::CARRY_FALSE,
1142 N->getDebugLoc(), MVT::Flag));
1144 // canonicalize constant to RHS.
1146 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1148 // fold (addc x, 0) -> x + no carry out
1149 if (N1C && N1C->isNullValue())
1150 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1151 N->getDebugLoc(), MVT::Flag));
1153 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1154 APInt LHSZero, LHSOne;
1155 APInt RHSZero, RHSOne;
1156 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1157 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1159 if (LHSZero.getBoolValue()) {
1160 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1162 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1163 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1164 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1165 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1166 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1167 DAG.getNode(ISD::CARRY_FALSE,
1168 N->getDebugLoc(), MVT::Flag));
1174 SDValue DAGCombiner::visitADDE(SDNode *N) {
1175 SDValue N0 = N->getOperand(0);
1176 SDValue N1 = N->getOperand(1);
1177 SDValue CarryIn = N->getOperand(2);
1178 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1179 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1181 // canonicalize constant to RHS
1183 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1186 // fold (adde x, y, false) -> (addc x, y)
1187 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1188 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1193 SDValue DAGCombiner::visitSUB(SDNode *N) {
1194 SDValue N0 = N->getOperand(0);
1195 SDValue N1 = N->getOperand(1);
1196 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1197 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1198 MVT VT = N0.getValueType();
1201 if (VT.isVector()) {
1202 SDValue FoldedVOp = SimplifyVBinOp(N);
1203 if (FoldedVOp.getNode()) return FoldedVOp;
1206 // fold (sub x, x) -> 0
1208 return DAG.getConstant(0, N->getValueType(0));
1209 // fold (sub c1, c2) -> c1-c2
1211 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1212 // fold (sub x, c) -> (add x, -c)
1214 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1215 DAG.getConstant(-N1C->getAPIntValue(), VT));
1216 // fold (A+B)-A -> B
1217 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1218 return N0.getOperand(1);
1219 // fold (A+B)-B -> A
1220 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1221 return N0.getOperand(0);
1222 // fold ((A+(B+or-C))-B) -> A+or-C
1223 if (N0.getOpcode() == ISD::ADD &&
1224 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1225 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1226 N0.getOperand(1).getOperand(0) == N1)
1227 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1228 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1229 // fold ((A+(C+B))-B) -> A+C
1230 if (N0.getOpcode() == ISD::ADD &&
1231 N0.getOperand(1).getOpcode() == ISD::ADD &&
1232 N0.getOperand(1).getOperand(1) == N1)
1233 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1234 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1235 // fold ((A-(B-C))-C) -> A-B
1236 if (N0.getOpcode() == ISD::SUB &&
1237 N0.getOperand(1).getOpcode() == ISD::SUB &&
1238 N0.getOperand(1).getOperand(1) == N1)
1239 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1240 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1241 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1242 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
1243 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations);
1244 if (Result.getNode()) return Result;
1247 // If either operand of a sub is undef, the result is undef
1248 if (N0.getOpcode() == ISD::UNDEF)
1250 if (N1.getOpcode() == ISD::UNDEF)
1253 // If the relocation model supports it, consider symbol offsets.
1254 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1255 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1256 // fold (sub Sym, c) -> Sym-c
1257 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1258 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1260 (uint64_t)N1C->getSExtValue());
1261 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1262 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1263 if (GA->getGlobal() == GB->getGlobal())
1264 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1271 SDValue DAGCombiner::visitMUL(SDNode *N) {
1272 SDValue N0 = N->getOperand(0);
1273 SDValue N1 = N->getOperand(1);
1274 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1275 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1276 MVT VT = N0.getValueType();
1279 if (VT.isVector()) {
1280 SDValue FoldedVOp = SimplifyVBinOp(N);
1281 if (FoldedVOp.getNode()) return FoldedVOp;
1284 // fold (mul x, undef) -> 0
1285 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1286 return DAG.getConstant(0, VT);
1287 // fold (mul c1, c2) -> c1*c2
1289 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1290 // canonicalize constant to RHS
1292 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1293 // fold (mul x, 0) -> 0
1294 if (N1C && N1C->isNullValue())
1296 // fold (mul x, -1) -> 0-x
1297 if (N1C && N1C->isAllOnesValue())
1298 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1299 DAG.getConstant(0, VT), N0);
1300 // fold (mul x, (1 << c)) -> x << c
1301 if (N1C && N1C->getAPIntValue().isPowerOf2())
1302 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1303 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1304 TLI.getShiftAmountTy()));
1305 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1306 if (N1C && isPowerOf2_64(-N1C->getSExtValue()))
1307 // FIXME: If the input is something that is easily negated (e.g. a
1308 // single-use add), we should put the negate there.
1309 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1310 DAG.getConstant(0, VT),
1311 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1312 DAG.getConstant(Log2_64(-N1C->getSExtValue()),
1313 TLI.getShiftAmountTy())));
1314 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1315 if (N1C && N0.getOpcode() == ISD::SHL &&
1316 isa<ConstantSDNode>(N0.getOperand(1))) {
1317 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1318 N1, N0.getOperand(1));
1319 AddToWorkList(C3.getNode());
1320 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1321 N0.getOperand(0), C3);
1324 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1327 SDValue Sh(0,0), Y(0,0);
1328 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1329 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1330 N0.getNode()->hasOneUse()) {
1332 } else if (N1.getOpcode() == ISD::SHL &&
1333 isa<ConstantSDNode>(N1.getOperand(1)) &&
1334 N1.getNode()->hasOneUse()) {
1339 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1340 Sh.getOperand(0), Y);
1341 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1342 Mul, Sh.getOperand(1));
1346 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1347 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1348 isa<ConstantSDNode>(N0.getOperand(1)))
1349 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1350 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1351 N0.getOperand(0), N1),
1352 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1353 N0.getOperand(1), N1));
1356 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1357 if (RMUL.getNode() != 0)
1363 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1364 SDValue N0 = N->getOperand(0);
1365 SDValue N1 = N->getOperand(1);
1366 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1367 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1368 MVT VT = N->getValueType(0);
1371 if (VT.isVector()) {
1372 SDValue FoldedVOp = SimplifyVBinOp(N);
1373 if (FoldedVOp.getNode()) return FoldedVOp;
1376 // fold (sdiv c1, c2) -> c1/c2
1377 if (N0C && N1C && !N1C->isNullValue())
1378 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1379 // fold (sdiv X, 1) -> X
1380 if (N1C && N1C->getSExtValue() == 1LL)
1382 // fold (sdiv X, -1) -> 0-X
1383 if (N1C && N1C->isAllOnesValue())
1384 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1385 DAG.getConstant(0, VT), N0);
1386 // If we know the sign bits of both operands are zero, strength reduce to a
1387 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1388 if (!VT.isVector()) {
1389 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1390 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1393 // fold (sdiv X, pow2) -> simple ops after legalize
1394 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1395 (isPowerOf2_64(N1C->getSExtValue()) ||
1396 isPowerOf2_64(-N1C->getSExtValue()))) {
1397 // If dividing by powers of two is cheap, then don't perform the following
1399 if (TLI.isPow2DivCheap())
1402 int64_t pow2 = N1C->getSExtValue();
1403 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1404 unsigned lg2 = Log2_64(abs2);
1406 // Splat the sign bit into the register
1407 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1408 DAG.getConstant(VT.getSizeInBits()-1,
1409 TLI.getShiftAmountTy()));
1410 AddToWorkList(SGN.getNode());
1412 // Add (N0 < 0) ? abs2 - 1 : 0;
1413 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1414 DAG.getConstant(VT.getSizeInBits() - lg2,
1415 TLI.getShiftAmountTy()));
1416 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1417 AddToWorkList(SRL.getNode());
1418 AddToWorkList(ADD.getNode()); // Divide by pow2
1419 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1420 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1422 // If we're dividing by a positive value, we're done. Otherwise, we must
1423 // negate the result.
1427 AddToWorkList(SRA.getNode());
1428 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1429 DAG.getConstant(0, VT), SRA);
1432 // if integer divide is expensive and we satisfy the requirements, emit an
1433 // alternate sequence.
1434 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1435 !TLI.isIntDivCheap()) {
1436 SDValue Op = BuildSDIV(N);
1437 if (Op.getNode()) return Op;
1441 if (N0.getOpcode() == ISD::UNDEF)
1442 return DAG.getConstant(0, VT);
1443 // X / undef -> undef
1444 if (N1.getOpcode() == ISD::UNDEF)
1450 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1451 SDValue N0 = N->getOperand(0);
1452 SDValue N1 = N->getOperand(1);
1453 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1454 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1455 MVT VT = N->getValueType(0);
1458 if (VT.isVector()) {
1459 SDValue FoldedVOp = SimplifyVBinOp(N);
1460 if (FoldedVOp.getNode()) return FoldedVOp;
1463 // fold (udiv c1, c2) -> c1/c2
1464 if (N0C && N1C && !N1C->isNullValue())
1465 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1466 // fold (udiv x, (1 << c)) -> x >>u c
1467 if (N1C && N1C->getAPIntValue().isPowerOf2())
1468 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1469 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1470 TLI.getShiftAmountTy()));
1471 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1472 if (N1.getOpcode() == ISD::SHL) {
1473 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1474 if (SHC->getAPIntValue().isPowerOf2()) {
1475 MVT ADDVT = N1.getOperand(1).getValueType();
1476 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1478 DAG.getConstant(SHC->getAPIntValue()
1481 AddToWorkList(Add.getNode());
1482 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1486 // fold (udiv x, c) -> alternate
1487 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1488 SDValue Op = BuildUDIV(N);
1489 if (Op.getNode()) return Op;
1493 if (N0.getOpcode() == ISD::UNDEF)
1494 return DAG.getConstant(0, VT);
1495 // X / undef -> undef
1496 if (N1.getOpcode() == ISD::UNDEF)
1502 SDValue DAGCombiner::visitSREM(SDNode *N) {
1503 SDValue N0 = N->getOperand(0);
1504 SDValue N1 = N->getOperand(1);
1505 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1506 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1507 MVT VT = N->getValueType(0);
1509 // fold (srem c1, c2) -> c1%c2
1510 if (N0C && N1C && !N1C->isNullValue())
1511 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1512 // If we know the sign bits of both operands are zero, strength reduce to a
1513 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1514 if (!VT.isVector()) {
1515 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1516 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1519 // If X/C can be simplified by the division-by-constant logic, lower
1520 // X%C to the equivalent of X-X/C*C.
1521 if (N1C && !N1C->isNullValue()) {
1522 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1523 AddToWorkList(Div.getNode());
1524 SDValue OptimizedDiv = combine(Div.getNode());
1525 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1526 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1528 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1529 AddToWorkList(Mul.getNode());
1535 if (N0.getOpcode() == ISD::UNDEF)
1536 return DAG.getConstant(0, VT);
1537 // X % undef -> undef
1538 if (N1.getOpcode() == ISD::UNDEF)
1544 SDValue DAGCombiner::visitUREM(SDNode *N) {
1545 SDValue N0 = N->getOperand(0);
1546 SDValue N1 = N->getOperand(1);
1547 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1549 MVT VT = N->getValueType(0);
1551 // fold (urem c1, c2) -> c1%c2
1552 if (N0C && N1C && !N1C->isNullValue())
1553 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1554 // fold (urem x, pow2) -> (and x, pow2-1)
1555 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1556 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1557 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1558 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1559 if (N1.getOpcode() == ISD::SHL) {
1560 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1561 if (SHC->getAPIntValue().isPowerOf2()) {
1563 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1564 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1566 AddToWorkList(Add.getNode());
1567 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1572 // If X/C can be simplified by the division-by-constant logic, lower
1573 // X%C to the equivalent of X-X/C*C.
1574 if (N1C && !N1C->isNullValue()) {
1575 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1576 AddToWorkList(Div.getNode());
1577 SDValue OptimizedDiv = combine(Div.getNode());
1578 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1579 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1581 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1582 AddToWorkList(Mul.getNode());
1588 if (N0.getOpcode() == ISD::UNDEF)
1589 return DAG.getConstant(0, VT);
1590 // X % undef -> undef
1591 if (N1.getOpcode() == ISD::UNDEF)
1597 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1598 SDValue N0 = N->getOperand(0);
1599 SDValue N1 = N->getOperand(1);
1600 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1601 MVT VT = N->getValueType(0);
1603 // fold (mulhs x, 0) -> 0
1604 if (N1C && N1C->isNullValue())
1606 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1607 if (N1C && N1C->getAPIntValue() == 1)
1608 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1609 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1610 TLI.getShiftAmountTy()));
1611 // fold (mulhs x, undef) -> 0
1612 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1613 return DAG.getConstant(0, VT);
1618 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1619 SDValue N0 = N->getOperand(0);
1620 SDValue N1 = N->getOperand(1);
1621 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1622 MVT VT = N->getValueType(0);
1624 // fold (mulhu x, 0) -> 0
1625 if (N1C && N1C->isNullValue())
1627 // fold (mulhu x, 1) -> 0
1628 if (N1C && N1C->getAPIntValue() == 1)
1629 return DAG.getConstant(0, N0.getValueType());
1630 // fold (mulhu x, undef) -> 0
1631 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1632 return DAG.getConstant(0, VT);
1637 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1638 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1639 /// that are being performed. Return true if a simplification was made.
1641 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1643 // If the high half is not needed, just compute the low half.
1644 bool HiExists = N->hasAnyUseOfValue(1);
1646 (!LegalOperations ||
1647 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1648 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1649 N->op_begin(), N->getNumOperands());
1650 return CombineTo(N, Res, Res);
1653 // If the low half is not needed, just compute the high half.
1654 bool LoExists = N->hasAnyUseOfValue(0);
1656 (!LegalOperations ||
1657 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1658 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1659 N->op_begin(), N->getNumOperands());
1660 return CombineTo(N, Res, Res);
1663 // If both halves are used, return as it is.
1664 if (LoExists && HiExists)
1667 // If the two computed results can be simplified separately, separate them.
1669 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1670 N->op_begin(), N->getNumOperands());
1671 AddToWorkList(Lo.getNode());
1672 SDValue LoOpt = combine(Lo.getNode());
1673 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1674 (!LegalOperations ||
1675 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1676 return CombineTo(N, LoOpt, LoOpt);
1680 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1681 N->op_begin(), N->getNumOperands());
1682 AddToWorkList(Hi.getNode());
1683 SDValue HiOpt = combine(Hi.getNode());
1684 if (HiOpt.getNode() && HiOpt != Hi &&
1685 (!LegalOperations ||
1686 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1687 return CombineTo(N, HiOpt, HiOpt);
1693 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1694 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1695 if (Res.getNode()) return Res;
1700 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1701 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1702 if (Res.getNode()) return Res;
1707 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
1708 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1709 if (Res.getNode()) return Res;
1714 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
1715 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1716 if (Res.getNode()) return Res;
1721 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1722 /// two operands of the same opcode, try to simplify it.
1723 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1724 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1725 MVT VT = N0.getValueType();
1726 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1728 // For each of OP in AND/OR/XOR:
1729 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1730 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1731 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1732 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1733 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1734 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1735 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1736 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1737 N0.getOperand(0).getValueType(),
1738 N0.getOperand(0), N1.getOperand(0));
1739 AddToWorkList(ORNode.getNode());
1740 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
1743 // For each of OP in SHL/SRL/SRA/AND...
1744 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1745 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1746 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1747 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1748 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1749 N0.getOperand(1) == N1.getOperand(1)) {
1750 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1751 N0.getOperand(0).getValueType(),
1752 N0.getOperand(0), N1.getOperand(0));
1753 AddToWorkList(ORNode.getNode());
1754 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
1755 ORNode, N0.getOperand(1));
1761 SDValue DAGCombiner::visitAND(SDNode *N) {
1762 SDValue N0 = N->getOperand(0);
1763 SDValue N1 = N->getOperand(1);
1764 SDValue LL, LR, RL, RR, CC0, CC1;
1765 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1766 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1767 MVT VT = N1.getValueType();
1768 unsigned BitWidth = VT.getSizeInBits();
1771 if (VT.isVector()) {
1772 SDValue FoldedVOp = SimplifyVBinOp(N);
1773 if (FoldedVOp.getNode()) return FoldedVOp;
1776 // fold (and x, undef) -> 0
1777 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1778 return DAG.getConstant(0, VT);
1779 // fold (and c1, c2) -> c1&c2
1781 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
1782 // canonicalize constant to RHS
1784 return DAG.getNode(ISD::AND, VT, N1, N0);
1785 // fold (and x, -1) -> x
1786 if (N1C && N1C->isAllOnesValue())
1788 // if (and x, c) is known to be zero, return 0
1789 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
1790 APInt::getAllOnesValue(BitWidth)))
1791 return DAG.getConstant(0, VT);
1793 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
1794 if (RAND.getNode() != 0)
1796 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1797 if (N1C && N0.getOpcode() == ISD::OR)
1798 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1799 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
1801 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1802 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1803 SDValue N0Op0 = N0.getOperand(0);
1804 APInt Mask = ~N1C->getAPIntValue();
1805 Mask.trunc(N0Op0.getValueSizeInBits());
1806 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
1807 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
1808 N0.getValueType(), N0Op0);
1810 // Replace uses of the AND with uses of the Zero extend node.
1813 // We actually want to replace all uses of the any_extend with the
1814 // zero_extend, to avoid duplicating things. This will later cause this
1815 // AND to be folded.
1816 CombineTo(N0.getNode(), Zext);
1817 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1820 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1821 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1822 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1823 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1825 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1826 LL.getValueType().isInteger()) {
1827 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
1828 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
1829 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1830 LR.getValueType(), LL, RL);
1831 AddToWorkList(ORNode.getNode());
1832 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1834 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
1835 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1836 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
1837 LR.getValueType(), LL, RL);
1838 AddToWorkList(ANDNode.getNode());
1839 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1841 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
1842 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1843 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1844 LR.getValueType(), LL, RL);
1845 AddToWorkList(ORNode.getNode());
1846 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1849 // canonicalize equivalent to ll == rl
1850 if (LL == RR && LR == RL) {
1851 Op1 = ISD::getSetCCSwappedOperands(Op1);
1854 if (LL == RL && LR == RR) {
1855 bool isInteger = LL.getValueType().isInteger();
1856 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1857 if (Result != ISD::SETCC_INVALID &&
1858 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
1859 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
1864 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
1865 if (N0.getOpcode() == N1.getOpcode()) {
1866 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1867 if (Tmp.getNode()) return Tmp;
1870 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1871 // fold (and (sra)) -> (and (srl)) when possible.
1872 if (!VT.isVector() &&
1873 SimplifyDemandedBits(SDValue(N, 0)))
1874 return SDValue(N, 0);
1875 // fold (zext_inreg (extload x)) -> (zextload x)
1876 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
1877 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1878 MVT EVT = LN0->getMemoryVT();
1879 // If we zero all the possible extended bits, then we can turn this into
1880 // a zextload if we are running before legalize or the operation is legal.
1881 unsigned BitWidth = N1.getValueSizeInBits();
1882 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1883 BitWidth - EVT.getSizeInBits())) &&
1884 ((!LegalOperations && !LN0->isVolatile()) ||
1885 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1886 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1887 LN0->getChain(), LN0->getBasePtr(),
1889 LN0->getSrcValueOffset(), EVT,
1890 LN0->isVolatile(), LN0->getAlignment());
1892 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1893 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1896 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1897 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
1899 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1900 MVT EVT = LN0->getMemoryVT();
1901 // If we zero all the possible extended bits, then we can turn this into
1902 // a zextload if we are running before legalize or the operation is legal.
1903 unsigned BitWidth = N1.getValueSizeInBits();
1904 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1905 BitWidth - EVT.getSizeInBits())) &&
1906 ((!LegalOperations && !LN0->isVolatile()) ||
1907 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1908 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1910 LN0->getBasePtr(), LN0->getSrcValue(),
1911 LN0->getSrcValueOffset(), EVT,
1912 LN0->isVolatile(), LN0->getAlignment());
1914 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1915 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1919 // fold (and (load x), 255) -> (zextload x, i8)
1920 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1921 if (N1C && N0.getOpcode() == ISD::LOAD) {
1922 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1923 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1924 LN0->isUnindexed() && N0.hasOneUse() &&
1925 // Do not change the width of a volatile load.
1926 !LN0->isVolatile()) {
1927 MVT EVT = MVT::Other;
1928 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
1929 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
1930 EVT = MVT::getIntegerVT(ActiveBits);
1932 MVT LoadedVT = LN0->getMemoryVT();
1934 // Do not generate loads of non-round integer types since these can
1935 // be expensive (and would be wrong if the type is not byte sized).
1936 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() &&
1937 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1938 MVT PtrType = N0.getOperand(1).getValueType();
1940 // For big endian targets, we need to add an offset to the pointer to
1941 // load the correct bytes. For little endian systems, we merely need to
1942 // read fewer bytes from the same pointer.
1943 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
1944 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
1945 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1946 unsigned Alignment = LN0->getAlignment();
1947 SDValue NewPtr = LN0->getBasePtr();
1949 if (TLI.isBigEndian()) {
1950 NewPtr = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(), PtrType,
1951 NewPtr, DAG.getConstant(PtrOff, PtrType));
1952 Alignment = MinAlign(Alignment, PtrOff);
1955 AddToWorkList(NewPtr.getNode());
1957 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(),
1958 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(),
1959 EVT, LN0->isVolatile(), Alignment);
1961 CombineTo(N0.getNode(), Load, Load.getValue(1));
1962 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1970 SDValue DAGCombiner::visitOR(SDNode *N) {
1971 SDValue N0 = N->getOperand(0);
1972 SDValue N1 = N->getOperand(1);
1973 SDValue LL, LR, RL, RR, CC0, CC1;
1974 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1975 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1976 MVT VT = N1.getValueType();
1979 if (VT.isVector()) {
1980 SDValue FoldedVOp = SimplifyVBinOp(N);
1981 if (FoldedVOp.getNode()) return FoldedVOp;
1984 // fold (or x, undef) -> -1
1985 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1986 return DAG.getConstant(~0ULL, VT);
1987 // fold (or c1, c2) -> c1|c2
1989 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
1990 // canonicalize constant to RHS
1992 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
1993 // fold (or x, 0) -> x
1994 if (N1C && N1C->isNullValue())
1996 // fold (or x, -1) -> -1
1997 if (N1C && N1C->isAllOnesValue())
1999 // fold (or x, c) -> c iff (x & ~c) == 0
2000 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2003 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2004 if (ROR.getNode() != 0)
2006 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2007 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2008 isa<ConstantSDNode>(N0.getOperand(1))) {
2009 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2010 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2011 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2012 N0.getOperand(0), N1),
2013 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2015 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2016 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2017 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2018 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2020 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2021 LL.getValueType().isInteger()) {
2022 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2023 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2024 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2025 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2026 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2027 LR.getValueType(), LL, RL);
2028 AddToWorkList(ORNode.getNode());
2029 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2031 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2032 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2033 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2034 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2035 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2036 LR.getValueType(), LL, RL);
2037 AddToWorkList(ANDNode.getNode());
2038 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2041 // canonicalize equivalent to ll == rl
2042 if (LL == RR && LR == RL) {
2043 Op1 = ISD::getSetCCSwappedOperands(Op1);
2046 if (LL == RL && LR == RR) {
2047 bool isInteger = LL.getValueType().isInteger();
2048 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2049 if (Result != ISD::SETCC_INVALID &&
2050 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2051 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2056 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2057 if (N0.getOpcode() == N1.getOpcode()) {
2058 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2059 if (Tmp.getNode()) return Tmp;
2062 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2063 if (N0.getOpcode() == ISD::AND &&
2064 N1.getOpcode() == ISD::AND &&
2065 N0.getOperand(1).getOpcode() == ISD::Constant &&
2066 N1.getOperand(1).getOpcode() == ISD::Constant &&
2067 // Don't increase # computations.
2068 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2069 // We can only do this xform if we know that bits from X that are set in C2
2070 // but not in C1 are already zero. Likewise for Y.
2071 const APInt &LHSMask =
2072 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2073 const APInt &RHSMask =
2074 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2076 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2077 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2078 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2079 N0.getOperand(0), N1.getOperand(0));
2080 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2081 DAG.getConstant(LHSMask | RHSMask, VT));
2085 // See if this is some rotate idiom.
2086 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2087 return SDValue(Rot, 0);
2092 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2093 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2094 if (Op.getOpcode() == ISD::AND) {
2095 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2096 Mask = Op.getOperand(1);
2097 Op = Op.getOperand(0);
2103 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2111 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2112 // idioms for rotate, and if the target supports rotation instructions, generate
2114 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2115 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2116 MVT VT = LHS.getValueType();
2117 if (!TLI.isTypeLegal(VT)) return 0;
2119 // The target must have at least one rotate flavor.
2120 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2121 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2122 if (!HasROTL && !HasROTR) return 0;
2124 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2125 SDValue LHSShift; // The shift.
2126 SDValue LHSMask; // AND value if any.
2127 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2128 return 0; // Not part of a rotate.
2130 SDValue RHSShift; // The shift.
2131 SDValue RHSMask; // AND value if any.
2132 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2133 return 0; // Not part of a rotate.
2135 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2136 return 0; // Not shifting the same value.
2138 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2139 return 0; // Shifts must disagree.
2141 // Canonicalize shl to left side in a shl/srl pair.
2142 if (RHSShift.getOpcode() == ISD::SHL) {
2143 std::swap(LHS, RHS);
2144 std::swap(LHSShift, RHSShift);
2145 std::swap(LHSMask , RHSMask );
2148 unsigned OpSizeInBits = VT.getSizeInBits();
2149 SDValue LHSShiftArg = LHSShift.getOperand(0);
2150 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2151 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2153 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2154 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2155 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2156 RHSShiftAmt.getOpcode() == ISD::Constant) {
2157 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2158 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2159 if ((LShVal + RShVal) != OpSizeInBits)
2164 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2166 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2168 // If there is an AND of either shifted operand, apply it to the result.
2169 if (LHSMask.getNode() || RHSMask.getNode()) {
2170 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2172 if (LHSMask.getNode()) {
2173 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2174 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2176 if (RHSMask.getNode()) {
2177 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2178 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2181 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2184 return Rot.getNode();
2187 // If there is a mask here, and we have a variable shift, we can't be sure
2188 // that we're masking out the right stuff.
2189 if (LHSMask.getNode() || RHSMask.getNode())
2192 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2193 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2194 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2195 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2196 if (ConstantSDNode *SUBC =
2197 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2198 if (SUBC->getAPIntValue() == OpSizeInBits) {
2200 return DAG.getNode(ISD::ROTL, DL, VT,
2201 LHSShiftArg, LHSShiftAmt).getNode();
2203 return DAG.getNode(ISD::ROTR, DL, VT,
2204 LHSShiftArg, RHSShiftAmt).getNode();
2209 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2210 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2211 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2212 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2213 if (ConstantSDNode *SUBC =
2214 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2215 if (SUBC->getAPIntValue() == OpSizeInBits) {
2217 return DAG.getNode(ISD::ROTR, DL, VT,
2218 LHSShiftArg, RHSShiftAmt).getNode();
2220 return DAG.getNode(ISD::ROTL, DL, VT,
2221 LHSShiftArg, LHSShiftAmt).getNode();
2226 // Look for sign/zext/any-extended or truncate cases:
2227 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2228 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2229 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2230 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2231 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2232 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2233 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2234 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2235 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2236 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2237 if (RExtOp0.getOpcode() == ISD::SUB &&
2238 RExtOp0.getOperand(1) == LExtOp0) {
2239 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2241 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2242 // (rotr x, (sub 32, y))
2243 if (ConstantSDNode *SUBC =
2244 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2245 if (SUBC->getAPIntValue() == OpSizeInBits) {
2246 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2248 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2251 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2252 RExtOp0 == LExtOp0.getOperand(1)) {
2253 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2255 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2256 // (rotl x, (sub 32, y))
2257 if (ConstantSDNode *SUBC =
2258 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2259 if (SUBC->getAPIntValue() == OpSizeInBits) {
2260 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2262 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2271 SDValue DAGCombiner::visitXOR(SDNode *N) {
2272 SDValue N0 = N->getOperand(0);
2273 SDValue N1 = N->getOperand(1);
2274 SDValue LHS, RHS, CC;
2275 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2276 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2277 MVT VT = N0.getValueType();
2280 if (VT.isVector()) {
2281 SDValue FoldedVOp = SimplifyVBinOp(N);
2282 if (FoldedVOp.getNode()) return FoldedVOp;
2285 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2286 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2287 return DAG.getConstant(0, VT);
2288 // fold (xor x, undef) -> undef
2289 if (N0.getOpcode() == ISD::UNDEF)
2291 if (N1.getOpcode() == ISD::UNDEF)
2293 // fold (xor c1, c2) -> c1^c2
2295 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2296 // canonicalize constant to RHS
2298 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2299 // fold (xor x, 0) -> x
2300 if (N1C && N1C->isNullValue())
2303 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2304 if (RXOR.getNode() != 0)
2307 // fold !(x cc y) -> (x !cc y)
2308 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2309 bool isInt = LHS.getValueType().isInteger();
2310 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2313 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2314 switch (N0.getOpcode()) {
2316 assert(0 && "Unhandled SetCC Equivalent!");
2319 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2320 case ISD::SELECT_CC:
2321 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2322 N0.getOperand(3), NotCC);
2327 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2328 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2329 N0.getNode()->hasOneUse() &&
2330 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2331 SDValue V = N0.getOperand(0);
2332 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2333 DAG.getConstant(1, V.getValueType()));
2334 AddToWorkList(V.getNode());
2335 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2338 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2339 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2340 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2341 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2342 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2343 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2344 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2345 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2346 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2347 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2350 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2351 if (N1C && N1C->isAllOnesValue() &&
2352 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2353 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2354 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2355 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2356 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2357 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2358 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2359 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2362 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2363 if (N1C && N0.getOpcode() == ISD::XOR) {
2364 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2365 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2367 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2368 DAG.getConstant(N1C->getAPIntValue() ^
2369 N00C->getAPIntValue(), VT));
2371 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2372 DAG.getConstant(N1C->getAPIntValue() ^
2373 N01C->getAPIntValue(), VT));
2375 // fold (xor x, x) -> 0
2377 if (!VT.isVector()) {
2378 return DAG.getConstant(0, VT);
2379 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2380 // Produce a vector of zeros.
2381 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2382 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2383 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2384 &Ops[0], Ops.size());
2388 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2389 if (N0.getOpcode() == N1.getOpcode()) {
2390 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2391 if (Tmp.getNode()) return Tmp;
2394 // Simplify the expression using non-local knowledge.
2395 if (!VT.isVector() &&
2396 SimplifyDemandedBits(SDValue(N, 0)))
2397 return SDValue(N, 0);
2402 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2403 /// the shift amount is a constant.
2404 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2405 SDNode *LHS = N->getOperand(0).getNode();
2406 if (!LHS->hasOneUse()) return SDValue();
2408 // We want to pull some binops through shifts, so that we have (and (shift))
2409 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2410 // thing happens with address calculations, so it's important to canonicalize
2412 bool HighBitSet = false; // Can we transform this if the high bit is set?
2414 switch (LHS->getOpcode()) {
2415 default: return SDValue();
2418 HighBitSet = false; // We can only transform sra if the high bit is clear.
2421 HighBitSet = true; // We can only transform sra if the high bit is set.
2424 if (N->getOpcode() != ISD::SHL)
2425 return SDValue(); // only shl(add) not sr[al](add).
2426 HighBitSet = false; // We can only transform sra if the high bit is clear.
2430 // We require the RHS of the binop to be a constant as well.
2431 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2432 if (!BinOpCst) return SDValue();
2434 // FIXME: disable this unless the input to the binop is a shift by a constant.
2435 // If it is not a shift, it pessimizes some common cases like:
2437 // void foo(int *X, int i) { X[i & 1235] = 1; }
2438 // int bar(int *X, int i) { return X[i & 255]; }
2439 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2440 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2441 BinOpLHSVal->getOpcode() != ISD::SRA &&
2442 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2443 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2446 MVT VT = N->getValueType(0);
2448 // If this is a signed shift right, and the high bit is modified by the
2449 // logical operation, do not perform the transformation. The highBitSet
2450 // boolean indicates the value of the high bit of the constant which would
2451 // cause it to be modified for this operation.
2452 if (N->getOpcode() == ISD::SRA) {
2453 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2454 if (BinOpRHSSignSet != HighBitSet)
2458 // Fold the constants, shifting the binop RHS by the shift amount.
2459 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2461 LHS->getOperand(1), N->getOperand(1));
2463 // Create the new shift.
2464 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2465 VT, LHS->getOperand(0), N->getOperand(1));
2467 // Create the new binop.
2468 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2471 SDValue DAGCombiner::visitSHL(SDNode *N) {
2472 SDValue N0 = N->getOperand(0);
2473 SDValue N1 = N->getOperand(1);
2474 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2475 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2476 MVT VT = N0.getValueType();
2477 unsigned OpSizeInBits = VT.getSizeInBits();
2479 // fold (shl c1, c2) -> c1<<c2
2481 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2482 // fold (shl 0, x) -> 0
2483 if (N0C && N0C->isNullValue())
2485 // fold (shl x, c >= size(x)) -> undef
2486 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2487 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT);
2488 // fold (shl x, 0) -> x
2489 if (N1C && N1C->isNullValue())
2491 // if (shl x, c) is known to be zero, return 0
2492 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2493 APInt::getAllOnesValue(VT.getSizeInBits())))
2494 return DAG.getConstant(0, VT);
2495 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c))
2496 // iff (trunc c) == c
2497 if (N1.getOpcode() == ISD::TRUNCATE &&
2498 N1.getOperand(0).getOpcode() == ISD::AND &&
2499 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2500 SDValue N101 = N1.getOperand(0).getOperand(1);
2501 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2502 MVT TruncVT = N1.getValueType();
2503 SDValue N100 = N1.getOperand(0).getOperand(0);
2504 uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
2505 N101C->getZExtValue();
2506 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2507 DAG.getNode(ISD::AND, TruncVT,
2508 DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
2509 DAG.getConstant(TruncC, TruncVT)));
2513 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2514 return SDValue(N, 0);
2516 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2517 if (N1C && N0.getOpcode() == ISD::SHL &&
2518 N0.getOperand(1).getOpcode() == ISD::Constant) {
2519 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2520 uint64_t c2 = N1C->getZExtValue();
2521 if (c1 + c2 > OpSizeInBits)
2522 return DAG.getConstant(0, VT);
2523 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2524 DAG.getConstant(c1 + c2, N1.getValueType()));
2526 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2527 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2528 if (N1C && N0.getOpcode() == ISD::SRL &&
2529 N0.getOperand(1).getOpcode() == ISD::Constant) {
2530 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2531 uint64_t c2 = N1C->getZExtValue();
2532 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0),
2533 DAG.getConstant(~0ULL << c1, VT));
2535 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2536 DAG.getConstant(c2-c1, N1.getValueType()));
2538 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2539 DAG.getConstant(c1-c2, N1.getValueType()));
2541 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2542 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2543 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2544 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT));
2546 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2549 SDValue DAGCombiner::visitSRA(SDNode *N) {
2550 SDValue N0 = N->getOperand(0);
2551 SDValue N1 = N->getOperand(1);
2552 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2553 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2554 MVT VT = N0.getValueType();
2556 // fold (sra c1, c2) -> (sra c1, c2)
2558 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2559 // fold (sra 0, x) -> 0
2560 if (N0C && N0C->isNullValue())
2562 // fold (sra -1, x) -> -1
2563 if (N0C && N0C->isAllOnesValue())
2565 // fold (sra x, (setge c, size(x))) -> undef
2566 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits())
2567 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT);
2568 // fold (sra x, 0) -> x
2569 if (N1C && N1C->isNullValue())
2571 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2573 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2574 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
2575 MVT EVT = MVT::getIntegerVT(LowBits);
2576 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
2577 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2578 N0.getOperand(0), DAG.getValueType(EVT));
2581 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2582 if (N1C && N0.getOpcode() == ISD::SRA) {
2583 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2584 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2585 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
2586 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2587 DAG.getConstant(Sum, N1C->getValueType(0)));
2591 // fold (sra (shl X, m), (sub result_size, n))
2592 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2593 // result_size - n != m.
2594 // If truncate is free for the target sext(shl) is likely to result in better
2596 if (N0.getOpcode() == ISD::SHL) {
2597 // Get the two constanst of the shifts, CN0 = m, CN = n.
2598 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2600 // Determine what the truncate's result bitsize and type would be.
2601 unsigned VTValSize = VT.getSizeInBits();
2603 MVT::getIntegerVT(VTValSize - N1C->getZExtValue());
2604 // Determine the residual right-shift amount.
2605 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2607 // If the shift is not a no-op (in which case this should be just a sign
2608 // extend already), the truncated to type is legal, sign_extend is legal
2609 // on that type, and the the truncate to that type is both legal and free,
2610 // perform the transform.
2612 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2613 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
2614 TLI.isTruncateFree(VT, TruncVT)) {
2616 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy());
2617 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
2618 N0.getOperand(0), Amt);
2619 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
2621 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
2622 N->getValueType(0), Trunc);
2627 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c))
2628 // iff (trunc c) == c
2629 if (N1.getOpcode() == ISD::TRUNCATE &&
2630 N1.getOperand(0).getOpcode() == ISD::AND &&
2631 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2632 SDValue N101 = N1.getOperand(0).getOperand(1);
2633 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2634 MVT TruncVT = N1.getValueType();
2635 SDValue N100 = N1.getOperand(0).getOperand(0);
2636 uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
2637 N101C->getZExtValue();
2638 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
2639 DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(),
2641 DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
2642 DAG.getConstant(TruncC, TruncVT)));
2646 // Simplify, based on bits shifted out of the LHS.
2647 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2648 return SDValue(N, 0);
2651 // If the sign bit is known to be zero, switch this to a SRL.
2652 if (DAG.SignBitIsZero(N0))
2653 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
2655 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2658 SDValue DAGCombiner::visitSRL(SDNode *N) {
2659 SDValue N0 = N->getOperand(0);
2660 SDValue N1 = N->getOperand(1);
2661 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2662 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2663 MVT VT = N0.getValueType();
2664 unsigned OpSizeInBits = VT.getSizeInBits();
2666 // fold (srl c1, c2) -> c1 >>u c2
2668 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
2669 // fold (srl 0, x) -> 0
2670 if (N0C && N0C->isNullValue())
2672 // fold (srl x, c >= size(x)) -> undef
2673 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2674 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT);
2675 // fold (srl x, 0) -> x
2676 if (N1C && N1C->isNullValue())
2678 // if (srl x, c) is known to be zero, return 0
2679 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2680 APInt::getAllOnesValue(OpSizeInBits)))
2681 return DAG.getConstant(0, VT);
2683 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
2684 if (N1C && N0.getOpcode() == ISD::SRL &&
2685 N0.getOperand(1).getOpcode() == ISD::Constant) {
2686 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2687 uint64_t c2 = N1C->getZExtValue();
2688 if (c1 + c2 > OpSizeInBits)
2689 return DAG.getConstant(0, VT);
2690 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
2691 DAG.getConstant(c1 + c2, N1.getValueType()));
2694 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2695 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2696 // Shifting in all undef bits?
2697 MVT SmallVT = N0.getOperand(0).getValueType();
2698 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
2699 return DAG.getNode(ISD::UNDEF, N->getDebugLoc(), VT);
2701 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
2702 N0.getOperand(0), N1);
2703 AddToWorkList(SmallShift.getNode());
2704 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
2707 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2708 // bit, which is unmodified by sra.
2709 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
2710 if (N0.getOpcode() == ISD::SRA)
2711 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
2714 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2715 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2716 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
2717 APInt KnownZero, KnownOne;
2718 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
2719 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2721 // If any of the input bits are KnownOne, then the input couldn't be all
2722 // zeros, thus the result of the srl will always be zero.
2723 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
2725 // If all of the bits input the to ctlz node are known to be zero, then
2726 // the result of the ctlz is "32" and the result of the shift is one.
2727 APInt UnknownBits = ~KnownZero & Mask;
2728 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2730 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2731 if ((UnknownBits & (UnknownBits - 1)) == 0) {
2732 // Okay, we know that only that the single bit specified by UnknownBits
2733 // could be set on input to the CTLZ node. If this bit is set, the SRL
2734 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2735 // to an SRL/XOR pair, which is likely to simplify more.
2736 unsigned ShAmt = UnknownBits.countTrailingZeros();
2737 SDValue Op = N0.getOperand(0);
2740 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
2741 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2742 AddToWorkList(Op.getNode());
2745 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
2746 Op, DAG.getConstant(1, VT));
2750 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c))
2751 // iff (trunc c) == c
2752 if (N1.getOpcode() == ISD::TRUNCATE &&
2753 N1.getOperand(0).getOpcode() == ISD::AND &&
2754 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2755 SDValue N101 = N1.getOperand(0).getOperand(1);
2756 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2757 MVT TruncVT = N1.getValueType();
2758 SDValue N100 = N1.getOperand(0).getOperand(0);
2759 uint64_t TruncC = TruncVT.getIntegerVTBitMask() &
2760 N101C->getZExtValue();
2761 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
2762 DAG.getNode(ISD::AND, DebugLoc::getUnknownLoc(),
2764 DAG.getNode(ISD::TRUNCATE, TruncVT, N100),
2765 DAG.getConstant(TruncC, TruncVT)));
2769 // fold operands of srl based on knowledge that the low bits are not
2771 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2772 return SDValue(N, 0);
2774 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2777 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
2778 SDValue N0 = N->getOperand(0);
2779 MVT VT = N->getValueType(0);
2781 // fold (ctlz c1) -> c2
2782 if (isa<ConstantSDNode>(N0))
2783 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
2787 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
2788 SDValue N0 = N->getOperand(0);
2789 MVT VT = N->getValueType(0);
2791 // fold (cttz c1) -> c2
2792 if (isa<ConstantSDNode>(N0))
2793 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
2797 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
2798 SDValue N0 = N->getOperand(0);
2799 MVT VT = N->getValueType(0);
2801 // fold (ctpop c1) -> c2
2802 if (isa<ConstantSDNode>(N0))
2803 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
2807 SDValue DAGCombiner::visitSELECT(SDNode *N) {
2808 SDValue N0 = N->getOperand(0);
2809 SDValue N1 = N->getOperand(1);
2810 SDValue N2 = N->getOperand(2);
2811 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2812 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2813 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2814 MVT VT = N->getValueType(0);
2815 MVT VT0 = N0.getValueType();
2817 // fold (select C, X, X) -> X
2820 // fold (select true, X, Y) -> X
2821 if (N0C && !N0C->isNullValue())
2823 // fold (select false, X, Y) -> Y
2824 if (N0C && N0C->isNullValue())
2826 // fold (select C, 1, X) -> (or C, X)
2827 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
2828 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2829 // fold (select C, 0, 1) -> (xor C, 1)
2830 if (VT.isInteger() &&
2833 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
2834 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
2837 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
2838 N0, DAG.getConstant(1, VT0));
2839 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
2840 N0, DAG.getConstant(1, VT0));
2841 AddToWorkList(XORNode.getNode());
2843 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
2844 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
2846 // fold (select C, 0, X) -> (and (not C), X)
2847 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2848 SDValue NOTNode = DAG.getNOT(N0, VT);
2849 AddToWorkList(NOTNode.getNode());
2850 return DAG.getNode(ISD::AND, VT, NOTNode, N2);
2852 // fold (select C, X, 1) -> (or (not C), X)
2853 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
2854 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2855 AddToWorkList(NOTNode.getNode());
2856 return DAG.getNode(ISD::OR, VT, NOTNode, N1);
2858 // fold (select C, X, 0) -> (and C, X)
2859 if (VT == MVT::i1 && N2C && N2C->isNullValue())
2860 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2861 // fold (select X, X, Y) -> (or X, Y)
2862 // fold (select X, 1, Y) -> (or X, Y)
2863 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
2864 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2865 // fold (select X, Y, X) -> (and X, Y)
2866 // fold (select X, Y, 0) -> (and X, Y)
2867 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
2868 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2870 // If we can fold this based on the true/false value, do so.
2871 if (SimplifySelectOps(N, N1, N2))
2872 return SDValue(N, 0); // Don't revisit N.
2874 // fold selects based on a setcc into other things, such as min/max/abs
2875 if (N0.getOpcode() == ISD::SETCC) {
2877 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2878 // having to say they don't support SELECT_CC on every type the DAG knows
2879 // about, since there is no way to mark an opcode illegal at all value types
2880 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other))
2881 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
2882 N0.getOperand(0), N0.getOperand(1),
2883 N1, N2, N0.getOperand(2));
2885 return SimplifySelect(N0, N1, N2);
2891 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
2892 SDValue N0 = N->getOperand(0);
2893 SDValue N1 = N->getOperand(1);
2894 SDValue N2 = N->getOperand(2);
2895 SDValue N3 = N->getOperand(3);
2896 SDValue N4 = N->getOperand(4);
2897 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2899 // fold select_cc lhs, rhs, x, x, cc -> x
2903 // Determine if the condition we're dealing with is constant
2904 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
2906 if (SCC.getNode()) AddToWorkList(SCC.getNode());
2908 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
2909 if (!SCCC->isNullValue())
2910 return N2; // cond always true -> true val
2912 return N3; // cond always false -> false val
2915 // Fold to a simpler select_cc
2916 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
2917 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
2918 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2921 // If we can fold this based on the true/false value, do so.
2922 if (SimplifySelectOps(N, N2, N3))
2923 return SDValue(N, 0); // Don't revisit N.
2925 // fold select_cc into other things, such as min/max/abs
2926 return SimplifySelectCC(N0, N1, N2, N3, CC);
2929 SDValue DAGCombiner::visitSETCC(SDNode *N) {
2930 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2931 cast<CondCodeSDNode>(N->getOperand(2))->get());
2934 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2935 // "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))"
2936 // transformation. Returns true if extension are possible and the above
2937 // mentioned transformation is profitable.
2938 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
2940 SmallVector<SDNode*, 4> &ExtendNodes,
2941 const TargetLowering &TLI) {
2942 bool HasCopyToRegUses = false;
2943 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2944 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
2945 UE = N0.getNode()->use_end();
2950 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2951 if (User->getOpcode() == ISD::SETCC) {
2952 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2953 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2954 // Sign bits will be lost after a zext.
2957 for (unsigned i = 0; i != 2; ++i) {
2958 SDValue UseOp = User->getOperand(i);
2961 if (!isa<ConstantSDNode>(UseOp))
2966 ExtendNodes.push_back(User);
2968 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2969 SDValue UseOp = User->getOperand(i);
2971 // If truncate from extended type to original load type is free
2972 // on this target, then it's ok to extend a CopyToReg.
2973 if (isTruncFree && User->getOpcode() == ISD::CopyToReg)
2974 HasCopyToRegUses = true;
2982 if (HasCopyToRegUses) {
2983 bool BothLiveOut = false;
2984 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2987 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2988 SDValue UseOp = User->getOperand(i);
2989 if (UseOp.getNode() == N && UseOp.getResNo() == 0) {
2996 // Both unextended and extended values are live out. There had better be
2997 // good a reason for the transformation.
2998 return ExtendNodes.size();
3003 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3004 SDValue N0 = N->getOperand(0);
3005 MVT VT = N->getValueType(0);
3007 // fold (sext c1) -> c1
3008 if (isa<ConstantSDNode>(N0))
3009 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3011 // fold (sext (sext x)) -> (sext x)
3012 // fold (sext (aext x)) -> (sext x)
3013 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3014 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3017 if (N0.getOpcode() == ISD::TRUNCATE) {
3018 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3019 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3020 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3021 if (NarrowLoad.getNode()) {
3022 if (NarrowLoad.getNode() != N0.getNode())
3023 CombineTo(N0.getNode(), NarrowLoad);
3024 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3027 // See if the value being truncated is already sign extended. If so, just
3028 // eliminate the trunc/sext pair.
3029 SDValue Op = N0.getOperand(0);
3030 unsigned OpBits = Op.getValueType().getSizeInBits();
3031 unsigned MidBits = N0.getValueType().getSizeInBits();
3032 unsigned DestBits = VT.getSizeInBits();
3033 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3035 if (OpBits == DestBits) {
3036 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3037 // bits, it is already ready.
3038 if (NumSignBits > DestBits-MidBits)
3040 } else if (OpBits < DestBits) {
3041 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3042 // bits, just sext from i32.
3043 if (NumSignBits > OpBits-MidBits)
3044 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3046 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3047 // bits, just truncate to i32.
3048 if (NumSignBits > OpBits-MidBits)
3049 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3052 // fold (sext (truncate x)) -> (sextinreg x).
3053 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3054 N0.getValueType())) {
3055 if (Op.getValueType().bitsLT(VT))
3056 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3057 else if (Op.getValueType().bitsGT(VT))
3058 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3059 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3060 DAG.getValueType(N0.getValueType()));
3064 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3065 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3066 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3067 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3068 bool DoXform = true;
3069 SmallVector<SDNode*, 4> SetCCs;
3070 if (!N0.hasOneUse())
3071 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3073 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3074 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(),
3075 VT, LN0->getChain(),
3076 LN0->getBasePtr(), LN0->getSrcValue(),
3077 LN0->getSrcValueOffset(),
3079 LN0->isVolatile(), LN0->getAlignment());
3080 CombineTo(N, ExtLoad);
3081 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3082 N0.getValueType(), ExtLoad);
3083 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3085 // Extend SetCC uses if necessary.
3086 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3087 SDNode *SetCC = SetCCs[i];
3088 SmallVector<SDValue, 4> Ops;
3090 for (unsigned j = 0; j != 2; ++j) {
3091 SDValue SOp = SetCC->getOperand(j);
3093 Ops.push_back(ExtLoad);
3095 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, DebugLoc::getUnknownLoc(),
3099 Ops.push_back(SetCC->getOperand(2));
3100 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DebugLoc::getUnknownLoc(),
3101 SetCC->getValueType(0),
3102 &Ops[0], Ops.size()));
3105 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3109 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3110 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3111 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3112 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3113 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3114 MVT EVT = LN0->getMemoryVT();
3115 if ((!LegalOperations && !LN0->isVolatile()) ||
3116 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) {
3117 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3119 LN0->getBasePtr(), LN0->getSrcValue(),
3120 LN0->getSrcValueOffset(), EVT,
3121 LN0->isVolatile(), LN0->getAlignment());
3122 CombineTo(N, ExtLoad);
3123 CombineTo(N0.getNode(),
3124 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3125 N0.getValueType(), ExtLoad),
3126 ExtLoad.getValue(1));
3127 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3131 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3132 if (N0.getOpcode() == ISD::SETCC) {
3134 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
3135 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
3136 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3137 if (SCC.getNode()) return SCC;
3140 // fold (sext x) -> (zext x) if the sign bit is known zero.
3141 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3142 DAG.SignBitIsZero(N0))
3143 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3148 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3149 SDValue N0 = N->getOperand(0);
3150 MVT VT = N->getValueType(0);
3152 // fold (zext c1) -> c1
3153 if (isa<ConstantSDNode>(N0))
3154 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3155 // fold (zext (zext x)) -> (zext x)
3156 // fold (zext (aext x)) -> (zext x)
3157 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3158 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3161 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3162 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3163 if (N0.getOpcode() == ISD::TRUNCATE) {
3164 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3165 if (NarrowLoad.getNode()) {
3166 if (NarrowLoad.getNode() != N0.getNode())
3167 CombineTo(N0.getNode(), NarrowLoad);
3168 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3172 // fold (zext (truncate x)) -> (and x, mask)
3173 if (N0.getOpcode() == ISD::TRUNCATE &&
3174 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
3175 SDValue Op = N0.getOperand(0);
3176 if (Op.getValueType().bitsLT(VT)) {
3177 Op = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, Op);
3178 } else if (Op.getValueType().bitsGT(VT)) {
3179 Op = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, Op);
3181 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType());
3184 // fold (zext (and (trunc x), cst)) -> (and x, cst).
3185 if (N0.getOpcode() == ISD::AND &&
3186 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3187 N0.getOperand(1).getOpcode() == ISD::Constant) {
3188 SDValue X = N0.getOperand(0).getOperand(0);
3189 if (X.getValueType().bitsLT(VT)) {
3190 X = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, X);
3191 } else if (X.getValueType().bitsGT(VT)) {
3192 X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X);
3194 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3195 Mask.zext(VT.getSizeInBits());
3196 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3197 X, DAG.getConstant(Mask, VT));
3200 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3201 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3202 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3203 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3204 bool DoXform = true;
3205 SmallVector<SDNode*, 4> SetCCs;
3206 if (!N0.hasOneUse())
3207 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3209 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3210 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3212 LN0->getBasePtr(), LN0->getSrcValue(),
3213 LN0->getSrcValueOffset(),
3215 LN0->isVolatile(), LN0->getAlignment());
3216 CombineTo(N, ExtLoad);
3217 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3218 N0.getValueType(), ExtLoad);
3219 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3221 // Extend SetCC uses if necessary.
3222 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3223 SDNode *SetCC = SetCCs[i];
3224 SmallVector<SDValue, 4> Ops;
3226 for (unsigned j = 0; j != 2; ++j) {
3227 SDValue SOp = SetCC->getOperand(j);
3229 Ops.push_back(ExtLoad);
3231 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp));
3234 Ops.push_back(SetCC->getOperand(2));
3235 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DebugLoc::getUnknownLoc(),
3236 SetCC->getValueType(0),
3237 &Ops[0], Ops.size()));
3240 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3244 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3245 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3246 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3247 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3248 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3249 MVT EVT = LN0->getMemoryVT();
3250 if ((!LegalOperations && !LN0->isVolatile()) ||
3251 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) {
3252 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3254 LN0->getBasePtr(), LN0->getSrcValue(),
3255 LN0->getSrcValueOffset(), EVT,
3256 LN0->isVolatile(), LN0->getAlignment());
3257 CombineTo(N, ExtLoad);
3258 CombineTo(N0.getNode(),
3259 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3261 ExtLoad.getValue(1));
3262 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3266 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3267 if (N0.getOpcode() == ISD::SETCC) {
3269 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
3270 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3271 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3272 if (SCC.getNode()) return SCC;
3278 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3279 SDValue N0 = N->getOperand(0);
3280 MVT VT = N->getValueType(0);
3282 // fold (aext c1) -> c1
3283 if (isa<ConstantSDNode>(N0))
3284 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
3285 // fold (aext (aext x)) -> (aext x)
3286 // fold (aext (zext x)) -> (zext x)
3287 // fold (aext (sext x)) -> (sext x)
3288 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3289 N0.getOpcode() == ISD::ZERO_EXTEND ||
3290 N0.getOpcode() == ISD::SIGN_EXTEND)
3291 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3293 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3294 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3295 if (N0.getOpcode() == ISD::TRUNCATE) {
3296 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3297 if (NarrowLoad.getNode()) {
3298 if (NarrowLoad.getNode() != N0.getNode())
3299 CombineTo(N0.getNode(), NarrowLoad);
3300 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3304 // fold (aext (truncate x))
3305 if (N0.getOpcode() == ISD::TRUNCATE) {
3306 SDValue TruncOp = N0.getOperand(0);
3307 if (TruncOp.getValueType() == VT)
3308 return TruncOp; // x iff x size == zext size.
3309 if (TruncOp.getValueType().bitsGT(VT))
3310 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3311 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3314 // fold (aext (and (trunc x), cst)) -> (and x, cst).
3315 if (N0.getOpcode() == ISD::AND &&
3316 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3317 N0.getOperand(1).getOpcode() == ISD::Constant) {
3318 SDValue X = N0.getOperand(0).getOperand(0);
3319 if (X.getValueType().bitsLT(VT)) {
3320 X = DAG.getNode(ISD::ANY_EXTEND, DebugLoc::getUnknownLoc(), VT, X);
3321 } else if (X.getValueType().bitsGT(VT)) {
3322 X = DAG.getNode(ISD::TRUNCATE, DebugLoc::getUnknownLoc(), VT, X);
3324 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3325 Mask.zext(VT.getSizeInBits());
3326 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3327 X, DAG.getConstant(Mask, VT));
3330 // fold (aext (load x)) -> (aext (truncate (extload x)))
3331 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
3332 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3333 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3334 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3335 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
3337 LN0->getBasePtr(), LN0->getSrcValue(),
3338 LN0->getSrcValueOffset(),
3340 LN0->isVolatile(), LN0->getAlignment());
3341 CombineTo(N, ExtLoad);
3342 // Redirect any chain users to the new load.
3343 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1),
3344 SDValue(ExtLoad.getNode(), 1));
3345 // If any node needs the original loaded value, recompute it.
3346 if (!LN0->use_empty())
3347 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3348 N0.getValueType(), ExtLoad),
3349 ExtLoad.getValue(1));
3350 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3353 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3354 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3355 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3356 if (N0.getOpcode() == ISD::LOAD &&
3357 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3359 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3360 MVT EVT = LN0->getMemoryVT();
3361 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
3362 VT, LN0->getChain(), LN0->getBasePtr(),
3364 LN0->getSrcValueOffset(), EVT,
3365 LN0->isVolatile(), LN0->getAlignment());
3366 CombineTo(N, ExtLoad);
3367 CombineTo(N0.getNode(),
3368 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3369 N0.getValueType(), ExtLoad),
3370 ExtLoad.getValue(1));
3371 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3374 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3375 if (N0.getOpcode() == ISD::SETCC) {
3377 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
3378 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3379 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3387 /// GetDemandedBits - See if the specified operand can be simplified with the
3388 /// knowledge that only the bits specified by Mask are used. If so, return the
3389 /// simpler operand, otherwise return a null SDValue.
3390 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
3391 switch (V.getOpcode()) {
3395 // If the LHS or RHS don't contribute bits to the or, drop them.
3396 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3397 return V.getOperand(1);
3398 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3399 return V.getOperand(0);
3402 // Only look at single-use SRLs.
3403 if (!V.getNode()->hasOneUse())
3405 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3406 // See if we can recursively simplify the LHS.
3407 unsigned Amt = RHSC->getZExtValue();
3409 // Watch out for shift count overflow though.
3410 if (Amt >= Mask.getBitWidth()) break;
3411 APInt NewMask = Mask << Amt;
3412 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
3413 if (SimplifyLHS.getNode())
3414 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
3415 SimplifyLHS, V.getOperand(1));
3421 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3422 /// bits and then truncated to a narrower type and where N is a multiple
3423 /// of number of bits of the narrower type, transform it to a narrower load
3424 /// from address + N / num of bits of new type. If the result is to be
3425 /// extended, also fold the extension to form a extending load.
3426 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
3427 unsigned Opc = N->getOpcode();
3428 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3429 SDValue N0 = N->getOperand(0);
3430 MVT VT = N->getValueType(0);
3433 // This transformation isn't valid for vector loads.
3437 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3439 if (Opc == ISD::SIGN_EXTEND_INREG) {
3440 ExtType = ISD::SEXTLOAD;
3441 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3442 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))
3446 unsigned EVTBits = EVT.getSizeInBits();
3448 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3449 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3450 ShAmt = N01->getZExtValue();
3451 // Is the shift amount a multiple of size of VT?
3452 if ((ShAmt & (EVTBits-1)) == 0) {
3453 N0 = N0.getOperand(0);
3454 if (N0.getValueType().getSizeInBits() <= EVTBits)
3460 // Do not generate loads of non-round integer types since these can
3461 // be expensive (and would be wrong if the type is not byte sized).
3462 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() &&
3463 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
3464 // Do not change the width of a volatile load.
3465 !cast<LoadSDNode>(N0)->isVolatile()) {
3466 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3467 MVT PtrType = N0.getOperand(1).getValueType();
3469 // For big endian targets, we need to adjust the offset to the pointer to
3470 // load the correct bytes.
3471 if (TLI.isBigEndian()) {
3472 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
3473 unsigned EVTStoreBits = EVT.getStoreSizeInBits();
3474 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3477 uint64_t PtrOff = ShAmt / 8;
3478 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3479 SDValue NewPtr = DAG.getNode(ISD::ADD, DebugLoc::getUnknownLoc(),
3480 PtrType, LN0->getBasePtr(),
3481 DAG.getConstant(PtrOff, PtrType));
3482 AddToWorkList(NewPtr.getNode());
3484 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
3485 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
3486 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3487 LN0->isVolatile(), NewAlign)
3488 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
3489 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3490 EVT, LN0->isVolatile(), NewAlign);
3492 // Replace the old load's chain with the new load's chain.
3493 WorkListRemover DeadNodes(*this);
3494 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
3497 // Return the new loaded value.
3504 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3505 SDValue N0 = N->getOperand(0);
3506 SDValue N1 = N->getOperand(1);
3507 MVT VT = N->getValueType(0);
3508 MVT EVT = cast<VTSDNode>(N1)->getVT();
3509 unsigned VTBits = VT.getSizeInBits();
3510 unsigned EVTBits = EVT.getSizeInBits();
3512 // fold (sext_in_reg c1) -> c1
3513 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3514 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
3516 // If the input is already sign extended, just drop the extension.
3517 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
3520 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3521 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3522 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
3523 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3524 N0.getOperand(0), N1);
3527 // fold (sext_in_reg (sext x)) -> (sext x)
3528 // fold (sext_in_reg (aext x)) -> (sext x)
3529 // if x is small enough.
3530 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
3531 SDValue N00 = N0.getOperand(0);
3532 if (N00.getValueType().getSizeInBits() < EVTBits)
3533 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
3536 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3537 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
3538 return DAG.getZeroExtendInReg(N0, EVT);
3540 // fold operands of sext_in_reg based on knowledge that the top bits are not
3542 if (SimplifyDemandedBits(SDValue(N, 0)))
3543 return SDValue(N, 0);
3545 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3546 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3547 SDValue NarrowLoad = ReduceLoadWidth(N);
3548 if (NarrowLoad.getNode())
3551 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
3552 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
3553 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3554 if (N0.getOpcode() == ISD::SRL) {
3555 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3556 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) {
3557 // We can turn this into an SRA iff the input to the SRL is already sign
3559 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3560 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
3561 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
3562 N0.getOperand(0), N0.getOperand(1));
3566 // fold (sext_inreg (extload x)) -> (sextload x)
3567 if (ISD::isEXTLoad(N0.getNode()) &&
3568 ISD::isUNINDEXEDLoad(N0.getNode()) &&
3569 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3570 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3571 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3572 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3573 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3575 LN0->getBasePtr(), LN0->getSrcValue(),
3576 LN0->getSrcValueOffset(), EVT,
3577 LN0->isVolatile(), LN0->getAlignment());
3578 CombineTo(N, ExtLoad);
3579 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3580 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3582 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3583 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3585 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3586 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3587 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3588 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3589 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3591 LN0->getBasePtr(), LN0->getSrcValue(),
3592 LN0->getSrcValueOffset(), EVT,
3593 LN0->isVolatile(), LN0->getAlignment());
3594 CombineTo(N, ExtLoad);
3595 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3596 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3601 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
3602 SDValue N0 = N->getOperand(0);
3603 MVT VT = N->getValueType(0);
3606 if (N0.getValueType() == N->getValueType(0))
3608 // fold (truncate c1) -> c1
3609 if (isa<ConstantSDNode>(N0))
3610 return DAG.getNode(ISD::TRUNCATE, VT, N0);
3611 // fold (truncate (truncate x)) -> (truncate x)
3612 if (N0.getOpcode() == ISD::TRUNCATE)
3613 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3614 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3615 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3616 N0.getOpcode() == ISD::ANY_EXTEND) {
3617 if (N0.getOperand(0).getValueType().bitsLT(VT))
3618 // if the source is smaller than the dest, we still need an extend
3619 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
3620 else if (N0.getOperand(0).getValueType().bitsGT(VT))
3621 // if the source is larger than the dest, than we just need the truncate
3622 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
3624 // if the source and dest are the same type, we can drop both the extend
3626 return N0.getOperand(0);
3629 // See if we can simplify the input to this truncate through knowledge that
3630 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3633 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3634 VT.getSizeInBits()));
3635 if (Shorter.getNode())
3636 return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
3638 // fold (truncate (load x)) -> (smaller load x)
3639 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3640 return ReduceLoadWidth(N);
3643 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
3644 SDValue Elt = N->getOperand(i);
3645 if (Elt.getOpcode() != ISD::MERGE_VALUES)
3646 return Elt.getNode();
3647 return Elt.getOperand(Elt.getResNo()).getNode();
3650 /// CombineConsecutiveLoads - build_pair (load, load) -> load
3651 /// if load locations are consecutive.
3652 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
3653 assert(N->getOpcode() == ISD::BUILD_PAIR);
3655 SDNode *LD1 = getBuildPairElt(N, 0);
3656 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
3658 MVT LD1VT = LD1->getValueType(0);
3659 SDNode *LD2 = getBuildPairElt(N, 1);
3660 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3661 if (ISD::isNON_EXTLoad(LD2) &&
3663 // If both are volatile this would reduce the number of volatile loads.
3664 // If one is volatile it might be ok, but play conservative and bail out.
3665 !cast<LoadSDNode>(LD1)->isVolatile() &&
3666 !cast<LoadSDNode>(LD2)->isVolatile() &&
3667 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
3668 LoadSDNode *LD = cast<LoadSDNode>(LD1);
3669 unsigned Align = LD->getAlignment();
3670 unsigned NewAlign = TLI.getTargetData()->
3671 getABITypeAlignment(VT.getTypeForMVT());
3672 if (NewAlign <= Align &&
3673 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
3674 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(),
3675 LD->getSrcValue(), LD->getSrcValueOffset(),
3681 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3682 SDValue N0 = N->getOperand(0);
3683 MVT VT = N->getValueType(0);
3685 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3686 // Only do this before legalize, since afterward the target may be depending
3687 // on the bitconvert.
3688 // First check to see if this is all constant.
3690 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
3692 bool isSimple = true;
3693 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3694 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3695 N0.getOperand(i).getOpcode() != ISD::Constant &&
3696 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3701 MVT DestEltVT = N->getValueType(0).getVectorElementType();
3702 assert(!DestEltVT.isVector() &&
3703 "Element type of vector ValueType must not be vector!");
3705 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
3709 // If the input is a constant, let getNode fold it.
3710 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3711 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
3712 if (Res.getNode() != N) return Res;
3715 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
3716 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3718 // fold (conv (load x)) -> (load (conv*)x)
3719 // If the resultant load doesn't need a higher alignment than the original!
3720 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
3721 // Do not change the width of a volatile load.
3722 !cast<LoadSDNode>(N0)->isVolatile() &&
3723 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
3724 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3725 unsigned Align = TLI.getTargetData()->
3726 getABITypeAlignment(VT.getTypeForMVT());
3727 unsigned OrigAlign = LN0->getAlignment();
3728 if (Align <= OrigAlign) {
3729 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
3730 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3731 LN0->isVolatile(), OrigAlign);
3733 CombineTo(N0.getNode(),
3734 DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
3740 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit)
3741 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit)
3742 // This often reduces constant pool loads.
3743 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3744 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
3745 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3746 AddToWorkList(NewConv.getNode());
3748 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3749 if (N0.getOpcode() == ISD::FNEG)
3750 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT));
3751 assert(N0.getOpcode() == ISD::FABS);
3752 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT));
3755 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign'
3756 // Note that we don't handle copysign(x,cst) because this can always be folded
3757 // to an fneg or fabs.
3758 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
3759 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
3760 VT.isInteger() && !VT.isVector()) {
3761 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
3762 MVT IntXVT = MVT::getIntegerVT(OrigXWidth);
3763 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) {
3764 SDValue X = DAG.getNode(ISD::BIT_CONVERT, IntXVT, N0.getOperand(1));
3765 AddToWorkList(X.getNode());
3767 // If X has a different width than the result/lhs, sext it or truncate it.
3768 unsigned VTWidth = VT.getSizeInBits();
3769 if (OrigXWidth < VTWidth) {
3770 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X);
3771 AddToWorkList(X.getNode());
3772 } else if (OrigXWidth > VTWidth) {
3773 // To get the sign bit in the right place, we have to shift it right
3774 // before truncating.
3775 X = DAG.getNode(ISD::SRL, X.getValueType(), X,
3776 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
3777 AddToWorkList(X.getNode());
3778 X = DAG.getNode(ISD::TRUNCATE, VT, X);
3779 AddToWorkList(X.getNode());
3782 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3783 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
3784 AddToWorkList(X.getNode());
3786 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
3787 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT));
3788 AddToWorkList(Cst.getNode());
3790 return DAG.getNode(ISD::OR, VT, X, Cst);
3794 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
3795 if (N0.getOpcode() == ISD::BUILD_PAIR) {
3796 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
3797 if (CombineLD.getNode())
3804 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
3805 MVT VT = N->getValueType(0);
3806 return CombineConsecutiveLoads(N, VT);
3809 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3810 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3811 /// destination element value type.
3812 SDValue DAGCombiner::
3813 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
3814 MVT SrcEltVT = BV->getOperand(0).getValueType();
3816 // If this is already the right type, we're done.
3817 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
3819 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
3820 unsigned DstBitSize = DstEltVT.getSizeInBits();
3822 // If this is a conversion of N elements of one type to N elements of another
3823 // type, convert each element. This handles FP<->INT cases.
3824 if (SrcBitSize == DstBitSize) {
3825 SmallVector<SDValue, 8> Ops;
3826 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3827 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
3828 AddToWorkList(Ops.back().getNode());
3830 MVT VT = MVT::getVectorVT(DstEltVT,
3831 BV->getValueType(0).getVectorNumElements());
3832 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3835 // Otherwise, we're growing or shrinking the elements. To avoid having to
3836 // handle annoying details of growing/shrinking FP values, we convert them to
3838 if (SrcEltVT.isFloatingPoint()) {
3839 // Convert the input float vector to a int vector where the elements are the
3841 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3842 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
3843 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
3847 // Now we know the input is an integer vector. If the output is a FP type,
3848 // convert to integer first, then to FP of the right size.
3849 if (DstEltVT.isFloatingPoint()) {
3850 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3851 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
3852 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
3854 // Next, convert to FP elements of the same size.
3855 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3858 // Okay, we know the src/dst types are both integers of differing types.
3859 // Handling growing first.
3860 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
3861 if (SrcBitSize < DstBitSize) {
3862 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3864 SmallVector<SDValue, 8> Ops;
3865 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3866 i += NumInputsPerOutput) {
3867 bool isLE = TLI.isLittleEndian();
3868 APInt NewBits = APInt(DstBitSize, 0);
3869 bool EltIsUndef = true;
3870 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3871 // Shift the previously computed bits over.
3872 NewBits <<= SrcBitSize;
3873 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3874 if (Op.getOpcode() == ISD::UNDEF) continue;
3878 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize);
3882 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3884 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3887 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size());
3888 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3891 // Finally, this must be the case where we are shrinking elements: each input
3892 // turns into multiple outputs.
3893 bool isS2V = ISD::isScalarToVector(BV);
3894 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3895 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
3896 SmallVector<SDValue, 8> Ops;
3897 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3898 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3899 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3900 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3903 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue();
3904 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3905 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
3906 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3907 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
3908 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
3909 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]);
3910 OpVal = OpVal.lshr(DstBitSize);
3913 // For big endian targets, swap the order of the pieces of each element.
3914 if (TLI.isBigEndian())
3915 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3917 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3922 SDValue DAGCombiner::visitFADD(SDNode *N) {
3923 SDValue N0 = N->getOperand(0);
3924 SDValue N1 = N->getOperand(1);
3925 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3926 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3927 MVT VT = N->getValueType(0);
3930 if (VT.isVector()) {
3931 SDValue FoldedVOp = SimplifyVBinOp(N);
3932 if (FoldedVOp.getNode()) return FoldedVOp;
3935 // fold (fadd c1, c2) -> c1+c2
3936 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3937 return DAG.getNode(ISD::FADD, VT, N0, N1);
3938 // canonicalize constant to RHS
3939 if (N0CFP && !N1CFP)
3940 return DAG.getNode(ISD::FADD, VT, N1, N0);
3941 // fold (A + 0) -> A
3942 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
3944 // fold (A + (-B)) -> A-B
3945 if (isNegatibleForFree(N1, LegalOperations) == 2)
3946 return DAG.getNode(ISD::FSUB, VT, N0,
3947 GetNegatedExpression(N1, DAG, LegalOperations));
3948 // fold ((-A) + B) -> B-A
3949 if (isNegatibleForFree(N0, LegalOperations) == 2)
3950 return DAG.getNode(ISD::FSUB, VT, N1,
3951 GetNegatedExpression(N0, DAG, LegalOperations));
3953 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3954 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3955 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3956 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3957 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3962 SDValue DAGCombiner::visitFSUB(SDNode *N) {
3963 SDValue N0 = N->getOperand(0);
3964 SDValue N1 = N->getOperand(1);
3965 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3966 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3967 MVT VT = N->getValueType(0);
3970 if (VT.isVector()) {
3971 SDValue FoldedVOp = SimplifyVBinOp(N);
3972 if (FoldedVOp.getNode()) return FoldedVOp;
3975 // fold (fsub c1, c2) -> c1-c2
3976 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3977 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3979 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
3982 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3983 if (isNegatibleForFree(N1, LegalOperations))
3984 return GetNegatedExpression(N1, DAG, LegalOperations);
3985 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
3986 return DAG.getNode(ISD::FNEG, VT, N1);
3988 // fold (A-(-B)) -> A+B
3989 if (isNegatibleForFree(N1, LegalOperations))
3990 return DAG.getNode(ISD::FADD, VT, N0,
3991 GetNegatedExpression(N1, DAG, LegalOperations));
3996 SDValue DAGCombiner::visitFMUL(SDNode *N) {
3997 SDValue N0 = N->getOperand(0);
3998 SDValue N1 = N->getOperand(1);
3999 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4000 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4001 MVT VT = N->getValueType(0);
4004 if (VT.isVector()) {
4005 SDValue FoldedVOp = SimplifyVBinOp(N);
4006 if (FoldedVOp.getNode()) return FoldedVOp;
4009 // fold (fmul c1, c2) -> c1*c2
4010 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4011 return DAG.getNode(ISD::FMUL, VT, N0, N1);
4012 // canonicalize constant to RHS
4013 if (N0CFP && !N1CFP)
4014 return DAG.getNode(ISD::FMUL, VT, N1, N0);
4015 // fold (A * 0) -> 0
4016 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4018 // fold (fmul X, 2.0) -> (fadd X, X)
4019 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4020 return DAG.getNode(ISD::FADD, VT, N0, N0);
4021 // fold (fmul X, -1.0) -> (fneg X)
4022 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4023 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4024 return DAG.getNode(ISD::FNEG, VT, N0);
4027 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4028 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4029 // Both can be negated for free, check to see if at least one is cheaper
4031 if (LHSNeg == 2 || RHSNeg == 2)
4032 return DAG.getNode(ISD::FMUL, VT,
4033 GetNegatedExpression(N0, DAG, LegalOperations),
4034 GetNegatedExpression(N1, DAG, LegalOperations));
4038 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4039 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4040 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4041 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
4042 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
4047 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4048 SDValue N0 = N->getOperand(0);
4049 SDValue N1 = N->getOperand(1);
4050 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4051 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4052 MVT VT = N->getValueType(0);
4055 if (VT.isVector()) {
4056 SDValue FoldedVOp = SimplifyVBinOp(N);
4057 if (FoldedVOp.getNode()) return FoldedVOp;
4060 // fold (fdiv c1, c2) -> c1/c2
4061 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4062 return DAG.getNode(ISD::FDIV, VT, N0, N1);
4066 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4067 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4068 // Both can be negated for free, check to see if at least one is cheaper
4070 if (LHSNeg == 2 || RHSNeg == 2)
4071 return DAG.getNode(ISD::FDIV, VT,
4072 GetNegatedExpression(N0, DAG, LegalOperations),
4073 GetNegatedExpression(N1, DAG, LegalOperations));
4080 SDValue DAGCombiner::visitFREM(SDNode *N) {
4081 SDValue N0 = N->getOperand(0);
4082 SDValue N1 = N->getOperand(1);
4083 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4084 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4085 MVT VT = N->getValueType(0);
4087 // fold (frem c1, c2) -> fmod(c1,c2)
4088 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4089 return DAG.getNode(ISD::FREM, VT, N0, N1);
4094 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4095 SDValue N0 = N->getOperand(0);
4096 SDValue N1 = N->getOperand(1);
4097 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4098 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4099 MVT VT = N->getValueType(0);
4101 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4102 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
4105 const APFloat& V = N1CFP->getValueAPF();
4106 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4107 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4108 if (!V.isNegative()) {
4109 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4110 return DAG.getNode(ISD::FABS, VT, N0);
4112 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4113 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
4117 // copysign(fabs(x), y) -> copysign(x, y)
4118 // copysign(fneg(x), y) -> copysign(x, y)
4119 // copysign(copysign(x,z), y) -> copysign(x, y)
4120 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4121 N0.getOpcode() == ISD::FCOPYSIGN)
4122 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
4124 // copysign(x, abs(y)) -> abs(x)
4125 if (N1.getOpcode() == ISD::FABS)
4126 return DAG.getNode(ISD::FABS, VT, N0);
4128 // copysign(x, copysign(y,z)) -> copysign(x, z)
4129 if (N1.getOpcode() == ISD::FCOPYSIGN)
4130 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
4132 // copysign(x, fp_extend(y)) -> copysign(x, y)
4133 // copysign(x, fp_round(y)) -> copysign(x, y)
4134 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4135 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
4142 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4143 SDValue N0 = N->getOperand(0);
4144 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4145 MVT VT = N->getValueType(0);
4146 MVT OpVT = N0.getValueType();
4148 // fold (sint_to_fp c1) -> c1fp
4149 if (N0C && OpVT != MVT::ppcf128)
4150 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
4152 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4153 // but UINT_TO_FP is legal on this target, try to convert.
4154 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4155 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4156 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4157 if (DAG.SignBitIsZero(N0))
4158 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
4165 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4166 SDValue N0 = N->getOperand(0);
4167 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4168 MVT VT = N->getValueType(0);
4169 MVT OpVT = N0.getValueType();
4171 // fold (uint_to_fp c1) -> c1fp
4172 if (N0C && OpVT != MVT::ppcf128)
4173 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
4175 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
4176 // but SINT_TO_FP is legal on this target, try to convert.
4177 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4178 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4179 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4180 if (DAG.SignBitIsZero(N0))
4181 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
4187 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4188 SDValue N0 = N->getOperand(0);
4189 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4190 MVT VT = N->getValueType(0);
4192 // fold (fp_to_sint c1fp) -> c1
4194 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
4198 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4199 SDValue N0 = N->getOperand(0);
4200 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4201 MVT VT = N->getValueType(0);
4203 // fold (fp_to_uint c1fp) -> c1
4204 if (N0CFP && VT != MVT::ppcf128)
4205 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
4209 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4210 SDValue N0 = N->getOperand(0);
4211 SDValue N1 = N->getOperand(1);
4212 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4213 MVT VT = N->getValueType(0);
4215 // fold (fp_round c1fp) -> c1fp
4216 if (N0CFP && N0.getValueType() != MVT::ppcf128)
4217 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1);
4219 // fold (fp_round (fp_extend x)) -> x
4220 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4221 return N0.getOperand(0);
4223 // fold (fp_round (fp_round x)) -> (fp_round x)
4224 if (N0.getOpcode() == ISD::FP_ROUND) {
4225 // This is a value preserving truncation if both round's are.
4226 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4227 N0.getNode()->getConstantOperandVal(1) == 1;
4228 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0),
4229 DAG.getIntPtrConstant(IsTrunc));
4232 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4233 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4234 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1);
4235 AddToWorkList(Tmp.getNode());
4236 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
4242 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4243 SDValue N0 = N->getOperand(0);
4244 MVT VT = N->getValueType(0);
4245 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4246 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4248 // fold (fp_round_inreg c1fp) -> c1fp
4249 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) {
4250 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4251 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
4256 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4257 SDValue N0 = N->getOperand(0);
4258 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4259 MVT VT = N->getValueType(0);
4261 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4262 if (N->hasOneUse() &&
4263 N->use_begin()->getOpcode() == ISD::FP_ROUND)
4266 // fold (fp_extend c1fp) -> c1fp
4267 if (N0CFP && VT != MVT::ppcf128)
4268 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
4270 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4272 if (N0.getOpcode() == ISD::FP_ROUND
4273 && N0.getNode()->getConstantOperandVal(1) == 1) {
4274 SDValue In = N0.getOperand(0);
4275 if (In.getValueType() == VT) return In;
4276 if (VT.bitsLT(In.getValueType()))
4277 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1));
4278 return DAG.getNode(ISD::FP_EXTEND, VT, In);
4281 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
4282 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
4283 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4284 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4285 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4286 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
4287 LN0->getBasePtr(), LN0->getSrcValue(),
4288 LN0->getSrcValueOffset(),
4290 LN0->isVolatile(), LN0->getAlignment());
4291 CombineTo(N, ExtLoad);
4292 CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(),
4293 ExtLoad, DAG.getIntPtrConstant(1)),
4294 ExtLoad.getValue(1));
4295 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4301 SDValue DAGCombiner::visitFNEG(SDNode *N) {
4302 SDValue N0 = N->getOperand(0);
4304 if (isNegatibleForFree(N0, LegalOperations))
4305 return GetNegatedExpression(N0, DAG, LegalOperations);
4307 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
4308 // constant pool values.
4309 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4310 N0.getOperand(0).getValueType().isInteger() &&
4311 !N0.getOperand(0).getValueType().isVector()) {
4312 SDValue Int = N0.getOperand(0);
4313 MVT IntVT = Int.getValueType();
4314 if (IntVT.isInteger() && !IntVT.isVector()) {
4315 Int = DAG.getNode(ISD::XOR, IntVT, Int,
4316 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT));
4317 AddToWorkList(Int.getNode());
4318 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
4325 SDValue DAGCombiner::visitFABS(SDNode *N) {
4326 SDValue N0 = N->getOperand(0);
4327 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4328 MVT VT = N->getValueType(0);
4330 // fold (fabs c1) -> fabs(c1)
4331 if (N0CFP && VT != MVT::ppcf128)
4332 return DAG.getNode(ISD::FABS, VT, N0);
4333 // fold (fabs (fabs x)) -> (fabs x)
4334 if (N0.getOpcode() == ISD::FABS)
4335 return N->getOperand(0);
4336 // fold (fabs (fneg x)) -> (fabs x)
4337 // fold (fabs (fcopysign x, y)) -> (fabs x)
4338 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
4339 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
4341 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
4342 // constant pool values.
4343 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4344 N0.getOperand(0).getValueType().isInteger() &&
4345 !N0.getOperand(0).getValueType().isVector()) {
4346 SDValue Int = N0.getOperand(0);
4347 MVT IntVT = Int.getValueType();
4348 if (IntVT.isInteger() && !IntVT.isVector()) {
4349 Int = DAG.getNode(ISD::AND, IntVT, Int,
4350 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT));
4351 AddToWorkList(Int.getNode());
4352 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
4359 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
4360 SDValue Chain = N->getOperand(0);
4361 SDValue N1 = N->getOperand(1);
4362 SDValue N2 = N->getOperand(2);
4363 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4365 // never taken branch, fold to chain
4366 if (N1C && N1C->isNullValue())
4368 // unconditional branch
4369 if (N1C && N1C->getAPIntValue() == 1)
4370 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
4371 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
4373 if (N1.getOpcode() == ISD::SETCC &&
4374 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
4375 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
4376 N1.getOperand(0), N1.getOperand(1), N2);
4381 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
4383 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
4384 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
4385 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
4387 // Use SimplifySetCC to simplify SETCC's.
4388 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
4389 CondLHS, CondRHS, CC->get(), false);
4390 if (Simp.getNode()) AddToWorkList(Simp.getNode());
4392 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
4394 // fold br_cc true, dest -> br dest (unconditional branch)
4395 if (SCCC && !SCCC->isNullValue())
4396 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
4398 // fold br_cc false, dest -> unconditional fall through
4399 if (SCCC && SCCC->isNullValue())
4400 return N->getOperand(0);
4402 // fold to a simpler setcc
4403 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
4404 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
4405 Simp.getOperand(2), Simp.getOperand(0),
4406 Simp.getOperand(1), N->getOperand(4));
4411 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
4412 /// pre-indexed load / store when the base pointer is an add or subtract
4413 /// and it has other uses besides the load / store. After the
4414 /// transformation, the new indexed load / store has effectively folded
4415 /// the add / subtract in and all of its other uses are redirected to the
4416 /// new load / store.
4417 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
4418 if (!LegalOperations)
4424 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4425 if (LD->isIndexed())
4427 VT = LD->getMemoryVT();
4428 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
4429 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
4431 Ptr = LD->getBasePtr();
4432 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4433 if (ST->isIndexed())
4435 VT = ST->getMemoryVT();
4436 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
4437 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
4439 Ptr = ST->getBasePtr();
4444 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
4445 // out. There is no reason to make this a preinc/predec.
4446 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
4447 Ptr.getNode()->hasOneUse())
4450 // Ask the target to do addressing mode selection.
4453 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4454 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
4456 // Don't create a indexed load / store with zero offset.
4457 if (isa<ConstantSDNode>(Offset) &&
4458 cast<ConstantSDNode>(Offset)->isNullValue())
4461 // Try turning it into a pre-indexed load / store except when:
4462 // 1) The new base ptr is a frame index.
4463 // 2) If N is a store and the new base ptr is either the same as or is a
4464 // predecessor of the value being stored.
4465 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
4466 // that would create a cycle.
4467 // 4) All uses are load / store ops that use it as old base ptr.
4469 // Check #1. Preinc'ing a frame index would require copying the stack pointer
4470 // (plus the implicit offset) to a register to preinc anyway.
4471 if (isa<FrameIndexSDNode>(BasePtr))
4476 SDValue Val = cast<StoreSDNode>(N)->getValue();
4477 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
4481 // Now check for #3 and #4.
4482 bool RealUse = false;
4483 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4484 E = Ptr.getNode()->use_end(); I != E; ++I) {
4488 if (Use->isPredecessorOf(N))
4491 if (!((Use->getOpcode() == ISD::LOAD &&
4492 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
4493 (Use->getOpcode() == ISD::STORE &&
4494 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
4502 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM);
4504 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM);
4507 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
4508 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4510 WorkListRemover DeadNodes(*this);
4512 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4514 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4517 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4521 // Finally, since the node is now dead, remove it from the graph.
4524 // Replace the uses of Ptr with uses of the updated base value.
4525 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
4527 removeFromWorkList(Ptr.getNode());
4528 DAG.DeleteNode(Ptr.getNode());
4533 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
4534 /// add / sub of the base pointer node into a post-indexed load / store.
4535 /// The transformation folded the add / subtract into the new indexed
4536 /// load / store effectively and all of its uses are redirected to the
4537 /// new load / store.
4538 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
4539 if (!LegalOperations)
4545 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4546 if (LD->isIndexed())
4548 VT = LD->getMemoryVT();
4549 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
4550 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
4552 Ptr = LD->getBasePtr();
4553 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4554 if (ST->isIndexed())
4556 VT = ST->getMemoryVT();
4557 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
4558 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
4560 Ptr = ST->getBasePtr();
4565 if (Ptr.getNode()->hasOneUse())
4568 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4569 E = Ptr.getNode()->use_end(); I != E; ++I) {
4572 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
4577 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4578 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
4580 std::swap(BasePtr, Offset);
4583 // Don't create a indexed load / store with zero offset.
4584 if (isa<ConstantSDNode>(Offset) &&
4585 cast<ConstantSDNode>(Offset)->isNullValue())
4588 // Try turning it into a post-indexed load / store except when
4589 // 1) All uses are load / store ops that use it as base ptr.
4590 // 2) Op must be independent of N, i.e. Op is neither a predecessor
4591 // nor a successor of N. Otherwise, if Op is folded that would
4595 bool TryNext = false;
4596 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
4597 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
4599 if (Use == Ptr.getNode())
4602 // If all the uses are load / store addresses, then don't do the
4604 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
4605 bool RealUse = false;
4606 for (SDNode::use_iterator III = Use->use_begin(),
4607 EEE = Use->use_end(); III != EEE; ++III) {
4608 SDNode *UseUse = *III;
4609 if (!((UseUse->getOpcode() == ISD::LOAD &&
4610 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
4611 (UseUse->getOpcode() == ISD::STORE &&
4612 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
4626 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
4627 SDValue Result = isLoad
4628 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM)
4629 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM);
4632 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4633 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4635 WorkListRemover DeadNodes(*this);
4637 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4639 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4642 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4646 // Finally, since the node is now dead, remove it from the graph.
4649 // Replace the uses of Use with uses of the updated base value.
4650 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
4651 Result.getValue(isLoad ? 1 : 0),
4653 removeFromWorkList(Op);
4662 /// InferAlignment - If we can infer some alignment information from this
4663 /// pointer, return it.
4664 static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) {
4665 // If this is a direct reference to a stack slot, use information about the
4666 // stack slot's alignment.
4667 int FrameIdx = 1 << 31;
4668 int64_t FrameOffset = 0;
4669 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) {
4670 FrameIdx = FI->getIndex();
4671 } else if (Ptr.getOpcode() == ISD::ADD &&
4672 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4673 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4674 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4675 FrameOffset = Ptr.getConstantOperandVal(1);
4678 if (FrameIdx != (1 << 31)) {
4679 // FIXME: Handle FI+CST.
4680 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
4681 if (MFI.isFixedObjectIndex(FrameIdx)) {
4682 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset;
4684 // The alignment of the frame index can be determined from its offset from
4685 // the incoming frame position. If the frame object is at offset 32 and
4686 // the stack is guaranteed to be 16-byte aligned, then we know that the
4687 // object is 16-byte aligned.
4688 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment();
4689 unsigned Align = MinAlign(ObjectOffset, StackAlign);
4691 // Finally, the frame object itself may have a known alignment. Factor
4692 // the alignment + offset into a new alignment. For example, if we know
4693 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a
4694 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte
4695 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc.
4696 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
4698 return std::max(Align, FIInfoAlign);
4705 SDValue DAGCombiner::visitLOAD(SDNode *N) {
4706 LoadSDNode *LD = cast<LoadSDNode>(N);
4707 SDValue Chain = LD->getChain();
4708 SDValue Ptr = LD->getBasePtr();
4710 // Try to infer better alignment information than the load already has.
4711 if (!Fast && LD->isUnindexed()) {
4712 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4713 if (Align > LD->getAlignment())
4714 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0),
4715 Chain, Ptr, LD->getSrcValue(),
4716 LD->getSrcValueOffset(), LD->getMemoryVT(),
4717 LD->isVolatile(), Align);
4722 // If load is not volatile and there are no uses of the loaded value (and
4723 // the updated indexed value in case of indexed loads), change uses of the
4724 // chain value into uses of the chain input (i.e. delete the dead load).
4725 if (!LD->isVolatile()) {
4726 if (N->getValueType(1) == MVT::Other) {
4728 if (N->hasNUsesOfValue(0, 0)) {
4729 // It's not safe to use the two value CombineTo variant here. e.g.
4730 // v1, chain2 = load chain1, loc
4731 // v2, chain3 = load chain2, loc
4733 // Now we replace use of chain2 with chain1. This makes the second load
4734 // isomorphic to the one we are deleting, and thus makes this load live.
4735 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4736 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG));
4738 WorkListRemover DeadNodes(*this);
4739 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
4740 if (N->use_empty()) {
4741 removeFromWorkList(N);
4744 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4748 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4749 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4750 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0));
4751 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4752 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
4753 DOUT << " and 2 other values\n";
4754 WorkListRemover DeadNodes(*this);
4755 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
4756 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
4757 DAG.getNode(ISD::UNDEF, N->getValueType(1)),
4759 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
4760 removeFromWorkList(N);
4762 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4767 // If this load is directly stored, replace the load value with the stored
4769 // TODO: Handle store large -> read small portion.
4770 // TODO: Handle TRUNCSTORE/LOADEXT
4771 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
4772 !LD->isVolatile()) {
4773 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
4774 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4775 if (PrevST->getBasePtr() == Ptr &&
4776 PrevST->getValue().getValueType() == N->getValueType(0))
4777 return CombineTo(N, Chain.getOperand(1), Chain);
4782 // Walk up chain skipping non-aliasing memory nodes.
4783 SDValue BetterChain = FindBetterChain(N, Chain);
4785 // If there is a better chain.
4786 if (Chain != BetterChain) {
4789 // Replace the chain to void dependency.
4790 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4791 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
4792 LD->getSrcValue(), LD->getSrcValueOffset(),
4793 LD->isVolatile(), LD->getAlignment());
4795 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
4796 LD->getValueType(0),
4797 BetterChain, Ptr, LD->getSrcValue(),
4798 LD->getSrcValueOffset(),
4801 LD->getAlignment());
4804 // Create token factor to keep old chain connected.
4805 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
4806 Chain, ReplLoad.getValue(1));
4808 // Replace uses with load result and token factor. Don't add users
4810 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4814 // Try transforming N to an indexed load.
4815 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4816 return SDValue(N, 0);
4822 SDValue DAGCombiner::visitSTORE(SDNode *N) {
4823 StoreSDNode *ST = cast<StoreSDNode>(N);
4824 SDValue Chain = ST->getChain();
4825 SDValue Value = ST->getValue();
4826 SDValue Ptr = ST->getBasePtr();
4828 // Try to infer better alignment information than the store already has.
4829 if (!Fast && ST->isUnindexed()) {
4830 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4831 if (Align > ST->getAlignment())
4832 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(),
4833 ST->getSrcValueOffset(), ST->getMemoryVT(),
4834 ST->isVolatile(), Align);
4838 // If this is a store of a bit convert, store the input value if the
4839 // resultant store does not need a higher alignment than the original.
4840 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
4841 ST->isUnindexed()) {
4842 unsigned Align = ST->getAlignment();
4843 MVT SVT = Value.getOperand(0).getValueType();
4844 unsigned OrigAlign = TLI.getTargetData()->
4845 getABITypeAlignment(SVT.getTypeForMVT());
4846 if (Align <= OrigAlign &&
4847 ((!LegalOperations && !ST->isVolatile()) ||
4848 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
4849 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4850 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign);
4853 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
4854 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
4855 // NOTE: If the original store is volatile, this transform must not increase
4856 // the number of stores. For example, on x86-32 an f64 can be stored in one
4857 // processor operation but an i64 (which is not legal) requires two. So the
4858 // transform should not be done in this case.
4859 if (Value.getOpcode() != ISD::TargetConstantFP) {
4861 switch (CFP->getValueType(0).getSimpleVT()) {
4862 default: assert(0 && "Unknown FP type");
4863 case MVT::f80: // We don't do this for these yet.
4868 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
4869 !ST->isVolatile()) ||
4870 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
4871 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
4872 bitcastToAPInt().getZExtValue(), MVT::i32);
4873 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4874 ST->getSrcValueOffset(), ST->isVolatile(),
4875 ST->getAlignment());
4879 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
4880 !ST->isVolatile()) ||
4881 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
4882 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
4883 getZExtValue(), MVT::i64);
4884 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
4885 ST->getSrcValueOffset(), ST->isVolatile(),
4886 ST->getAlignment());
4887 } else if (!ST->isVolatile() &&
4888 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
4889 // Many FP stores are not made apparent until after legalize, e.g. for
4890 // argument passing. Since this is so common, custom legalize the
4891 // 64-bit integer store into two 32-bit stores.
4892 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
4893 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
4894 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
4895 if (TLI.isBigEndian()) std::swap(Lo, Hi);
4897 int SVOffset = ST->getSrcValueOffset();
4898 unsigned Alignment = ST->getAlignment();
4899 bool isVolatile = ST->isVolatile();
4901 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
4902 ST->getSrcValueOffset(),
4903 isVolatile, ST->getAlignment());
4904 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4905 DAG.getConstant(4, Ptr.getValueType()));
4907 Alignment = MinAlign(Alignment, 4U);
4908 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
4909 SVOffset, isVolatile, Alignment);
4910 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
4918 // Walk up chain skipping non-aliasing memory nodes.
4919 SDValue BetterChain = FindBetterChain(N, Chain);
4921 // If there is a better chain.
4922 if (Chain != BetterChain) {
4923 // Replace the chain to avoid dependency.
4925 if (ST->isTruncatingStore()) {
4926 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
4927 ST->getSrcValue(),ST->getSrcValueOffset(),
4929 ST->isVolatile(), ST->getAlignment());
4931 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
4932 ST->getSrcValue(), ST->getSrcValueOffset(),
4933 ST->isVolatile(), ST->getAlignment());
4936 // Create token to keep both nodes around.
4938 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
4940 // Don't add users to work list.
4941 return CombineTo(N, Token, false);
4945 // Try transforming N to an indexed store.
4946 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4947 return SDValue(N, 0);
4949 // FIXME: is there such a thing as a truncating indexed store?
4950 if (ST->isTruncatingStore() && ST->isUnindexed() &&
4951 Value.getValueType().isInteger()) {
4952 // See if we can simplify the input to this truncstore with knowledge that
4953 // only the low bits are being used. For example:
4954 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
4956 GetDemandedBits(Value,
4957 APInt::getLowBitsSet(Value.getValueSizeInBits(),
4958 ST->getMemoryVT().getSizeInBits()));
4959 AddToWorkList(Value.getNode());
4960 if (Shorter.getNode())
4961 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
4962 ST->getSrcValueOffset(), ST->getMemoryVT(),
4963 ST->isVolatile(), ST->getAlignment());
4965 // Otherwise, see if we can simplify the operation with
4966 // SimplifyDemandedBits, which only works if the value has a single use.
4967 if (SimplifyDemandedBits(Value,
4968 APInt::getLowBitsSet(
4969 Value.getValueSizeInBits(),
4970 ST->getMemoryVT().getSizeInBits())))
4971 return SDValue(N, 0);
4974 // If this is a load followed by a store to the same location, then the store
4976 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
4977 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
4978 ST->isUnindexed() && !ST->isVolatile() &&
4979 // There can't be any side effects between the load and store, such as
4981 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
4982 // The store is dead, remove it.
4987 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
4988 // truncating store. We can do this even if this is already a truncstore.
4989 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
4990 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
4991 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
4992 ST->getMemoryVT())) {
4993 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
4994 ST->getSrcValueOffset(), ST->getMemoryVT(),
4995 ST->isVolatile(), ST->getAlignment());
5001 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
5002 SDValue InVec = N->getOperand(0);
5003 SDValue InVal = N->getOperand(1);
5004 SDValue EltNo = N->getOperand(2);
5006 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
5007 // vector with the inserted element.
5008 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
5009 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5010 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
5011 InVec.getNode()->op_end());
5012 if (Elt < Ops.size())
5014 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
5015 &Ops[0], Ops.size());
5021 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
5022 // (vextract (scalar_to_vector val, 0) -> val
5023 SDValue InVec = N->getOperand(0);
5025 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR)
5026 return InVec.getOperand(0);
5028 // Perform only after legalization to ensure build_vector / vector_shuffle
5029 // optimizations have already been done.
5030 if (!LegalOperations) return SDValue();
5032 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
5033 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
5034 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
5035 SDValue EltNo = N->getOperand(1);
5037 if (isa<ConstantSDNode>(EltNo)) {
5038 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5039 bool NewLoad = false;
5040 bool BCNumEltsChanged = false;
5041 MVT VT = InVec.getValueType();
5042 MVT EVT = VT.getVectorElementType();
5044 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
5045 MVT BCVT = InVec.getOperand(0).getValueType();
5046 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
5048 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
5049 BCNumEltsChanged = true;
5050 InVec = InVec.getOperand(0);
5051 EVT = BCVT.getVectorElementType();
5055 LoadSDNode *LN0 = NULL;
5056 if (ISD::isNormalLoad(InVec.getNode()))
5057 LN0 = cast<LoadSDNode>(InVec);
5058 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5059 InVec.getOperand(0).getValueType() == EVT &&
5060 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
5061 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
5062 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
5063 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
5065 // (load $addr+1*size)
5067 // If the bit convert changed the number of elements, it is unsafe
5068 // to examine the mask.
5069 if (BCNumEltsChanged)
5071 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2).
5072 getOperand(Elt))->getZExtValue();
5073 unsigned NumElems = InVec.getOperand(2).getNumOperands();
5074 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
5075 if (InVec.getOpcode() == ISD::BIT_CONVERT)
5076 InVec = InVec.getOperand(0);
5077 if (ISD::isNormalLoad(InVec.getNode())) {
5078 LN0 = cast<LoadSDNode>(InVec);
5079 Elt = (Idx < NumElems) ? Idx : Idx - NumElems;
5082 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
5085 unsigned Align = LN0->getAlignment();
5087 // Check the resultant load doesn't need a higher alignment than the
5089 unsigned NewAlign = TLI.getTargetData()->
5090 getABITypeAlignment(LVT.getTypeForMVT());
5091 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
5096 SDValue NewPtr = LN0->getBasePtr();
5098 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
5099 MVT PtrType = NewPtr.getValueType();
5100 if (TLI.isBigEndian())
5101 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
5102 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
5103 DAG.getConstant(PtrOff, PtrType));
5105 return DAG.getLoad(LVT, LN0->getChain(), NewPtr,
5106 LN0->getSrcValue(), LN0->getSrcValueOffset(),
5107 LN0->isVolatile(), Align);
5113 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
5114 unsigned NumInScalars = N->getNumOperands();
5115 MVT VT = N->getValueType(0);
5116 unsigned NumElts = VT.getVectorNumElements();
5117 MVT EltType = VT.getVectorElementType();
5119 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
5120 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
5121 // at most two distinct vectors, turn this into a shuffle node.
5122 SDValue VecIn1, VecIn2;
5123 for (unsigned i = 0; i != NumInScalars; ++i) {
5124 // Ignore undef inputs.
5125 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5127 // If this input is something other than a EXTRACT_VECTOR_ELT with a
5128 // constant index, bail out.
5129 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5130 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
5131 VecIn1 = VecIn2 = SDValue(0, 0);
5135 // If the input vector type disagrees with the result of the build_vector,
5136 // we can't make a shuffle.
5137 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
5138 if (ExtractedFromVec.getValueType() != VT) {
5139 VecIn1 = VecIn2 = SDValue(0, 0);
5143 // Otherwise, remember this. We allow up to two distinct input vectors.
5144 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
5147 if (VecIn1.getNode() == 0) {
5148 VecIn1 = ExtractedFromVec;
5149 } else if (VecIn2.getNode() == 0) {
5150 VecIn2 = ExtractedFromVec;
5153 VecIn1 = VecIn2 = SDValue(0, 0);
5158 // If everything is good, we can make a shuffle operation.
5159 if (VecIn1.getNode()) {
5160 SmallVector<SDValue, 8> BuildVecIndices;
5161 for (unsigned i = 0; i != NumInScalars; ++i) {
5162 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
5163 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
5167 SDValue Extract = N->getOperand(i);
5169 // If extracting from the first vector, just use the index directly.
5170 if (Extract.getOperand(0) == VecIn1) {
5171 BuildVecIndices.push_back(Extract.getOperand(1));
5175 // Otherwise, use InIdx + VecSize
5177 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue();
5178 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars));
5181 // Add count and size info.
5182 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
5183 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes)
5186 // Return the new VECTOR_SHUFFLE node.
5189 if (VecIn2.getNode()) {
5192 // Use an undef build_vector as input for the second operand.
5193 std::vector<SDValue> UnOps(NumInScalars,
5194 DAG.getNode(ISD::UNDEF,
5196 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
5197 &UnOps[0], UnOps.size());
5198 AddToWorkList(Ops[1].getNode());
5200 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
5201 &BuildVecIndices[0], BuildVecIndices.size());
5202 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
5208 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
5209 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
5210 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
5211 // inputs come from at most two distinct vectors, turn this into a shuffle
5214 // If we only have one input vector, we don't need to do any concatenation.
5215 if (N->getNumOperands() == 1) {
5216 return N->getOperand(0);
5222 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
5223 SDValue ShufMask = N->getOperand(2);
5224 unsigned NumElts = ShufMask.getNumOperands();
5226 SDValue N0 = N->getOperand(0);
5227 SDValue N1 = N->getOperand(1);
5229 assert(N0.getValueType().getVectorNumElements() == NumElts &&
5230 "Vector shuffle must be normalized in DAG");
5232 // If the shuffle mask is an identity operation on the LHS, return the LHS.
5233 bool isIdentity = true;
5234 for (unsigned i = 0; i != NumElts; ++i) {
5235 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
5236 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) {
5241 if (isIdentity) return N->getOperand(0);
5243 // If the shuffle mask is an identity operation on the RHS, return the RHS.
5245 for (unsigned i = 0; i != NumElts; ++i) {
5246 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
5247 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() !=
5253 if (isIdentity) return N->getOperand(1);
5255 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
5257 bool isUnary = true;
5258 bool isSplat = true;
5260 unsigned BaseIdx = 0;
5261 for (unsigned i = 0; i != NumElts; ++i)
5262 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
5263 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue();
5264 int V = (Idx < NumElts) ? 0 : 1;
5278 // Normalize unary shuffle so the RHS is undef.
5279 if (isUnary && VecNum == 1)
5282 // If it is a splat, check if the argument vector is a build_vector with
5283 // all scalar elements the same.
5285 SDNode *V = N0.getNode();
5287 // If this is a bit convert that changes the element type of the vector but
5288 // not the number of vector elements, look through it. Be careful not to
5289 // look though conversions that change things like v4f32 to v2f64.
5290 if (V->getOpcode() == ISD::BIT_CONVERT) {
5291 SDValue ConvInput = V->getOperand(0);
5292 if (ConvInput.getValueType().isVector() &&
5293 ConvInput.getValueType().getVectorNumElements() == NumElts)
5294 V = ConvInput.getNode();
5297 if (V->getOpcode() == ISD::BUILD_VECTOR) {
5298 unsigned NumElems = V->getNumOperands();
5299 if (NumElems > BaseIdx) {
5301 bool AllSame = true;
5302 for (unsigned i = 0; i != NumElems; ++i) {
5303 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
5304 Base = V->getOperand(i);
5308 // Splat of <u, u, u, u>, return <u, u, u, u>
5309 if (!Base.getNode())
5311 for (unsigned i = 0; i != NumElems; ++i) {
5312 if (V->getOperand(i) != Base) {
5317 // Splat of <x, x, x, x>, return <x, x, x, x>
5324 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
5326 if (isUnary || N0 == N1) {
5327 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
5329 SmallVector<SDValue, 8> MappedOps;
5330 for (unsigned i = 0; i != NumElts; ++i) {
5331 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
5332 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() <
5334 MappedOps.push_back(ShufMask.getOperand(i));
5337 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() -
5339 MappedOps.push_back(DAG.getConstant(NewIdx,
5340 ShufMask.getOperand(i).getValueType()));
5343 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
5344 &MappedOps[0], MappedOps.size());
5345 AddToWorkList(ShufMask.getNode());
5346 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
5348 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
5355 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
5356 /// an AND to a vector_shuffle with the destination vector and a zero vector.
5357 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
5358 /// vector_shuffle V, Zero, <0, 4, 2, 4>
5359 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
5360 SDValue LHS = N->getOperand(0);
5361 SDValue RHS = N->getOperand(1);
5362 if (N->getOpcode() == ISD::AND) {
5363 if (RHS.getOpcode() == ISD::BIT_CONVERT)
5364 RHS = RHS.getOperand(0);
5365 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
5366 std::vector<SDValue> IdxOps;
5367 unsigned NumOps = RHS.getNumOperands();
5368 unsigned NumElts = NumOps;
5369 for (unsigned i = 0; i != NumElts; ++i) {
5370 SDValue Elt = RHS.getOperand(i);
5371 if (!isa<ConstantSDNode>(Elt))
5373 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
5374 IdxOps.push_back(DAG.getIntPtrConstant(i));
5375 else if (cast<ConstantSDNode>(Elt)->isNullValue())
5376 IdxOps.push_back(DAG.getIntPtrConstant(NumElts));
5381 // Let's see if the target supports this vector_shuffle.
5382 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG))
5385 // Return the new VECTOR_SHUFFLE node.
5386 MVT EVT = RHS.getValueType().getVectorElementType();
5387 MVT VT = MVT::getVectorVT(EVT, NumElts);
5388 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
5389 std::vector<SDValue> Ops;
5390 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
5392 AddToWorkList(LHS.getNode());
5393 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
5394 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
5395 &ZeroOps[0], ZeroOps.size()));
5396 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5397 &IdxOps[0], IdxOps.size()));
5398 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
5399 &Ops[0], Ops.size());
5400 if (VT != N->getValueType(0))
5401 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result);
5408 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
5409 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
5410 // After legalize, the target may be depending on adds and other
5411 // binary ops to provide legal ways to construct constants or other
5412 // things. Simplifying them may result in a loss of legality.
5413 if (LegalOperations) return SDValue();
5415 MVT VT = N->getValueType(0);
5416 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
5418 MVT EltType = VT.getVectorElementType();
5419 SDValue LHS = N->getOperand(0);
5420 SDValue RHS = N->getOperand(1);
5421 SDValue Shuffle = XformToShuffleWithZero(N);
5422 if (Shuffle.getNode()) return Shuffle;
5424 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
5426 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
5427 RHS.getOpcode() == ISD::BUILD_VECTOR) {
5428 SmallVector<SDValue, 8> Ops;
5429 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
5430 SDValue LHSOp = LHS.getOperand(i);
5431 SDValue RHSOp = RHS.getOperand(i);
5432 // If these two elements can't be folded, bail out.
5433 if ((LHSOp.getOpcode() != ISD::UNDEF &&
5434 LHSOp.getOpcode() != ISD::Constant &&
5435 LHSOp.getOpcode() != ISD::ConstantFP) ||
5436 (RHSOp.getOpcode() != ISD::UNDEF &&
5437 RHSOp.getOpcode() != ISD::Constant &&
5438 RHSOp.getOpcode() != ISD::ConstantFP))
5440 // Can't fold divide by zero.
5441 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
5442 N->getOpcode() == ISD::FDIV) {
5443 if ((RHSOp.getOpcode() == ISD::Constant &&
5444 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
5445 (RHSOp.getOpcode() == ISD::ConstantFP &&
5446 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
5449 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
5450 AddToWorkList(Ops.back().getNode());
5451 assert((Ops.back().getOpcode() == ISD::UNDEF ||
5452 Ops.back().getOpcode() == ISD::Constant ||
5453 Ops.back().getOpcode() == ISD::ConstantFP) &&
5454 "Scalar binop didn't fold!");
5457 if (Ops.size() == LHS.getNumOperands()) {
5458 MVT VT = LHS.getValueType();
5459 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
5466 SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){
5467 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
5469 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
5470 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5471 // If we got a simplified select_cc node back from SimplifySelectCC, then
5472 // break it down into a new SETCC node, and a new SELECT node, and then return
5473 // the SELECT node, since we were called with a SELECT node.
5474 if (SCC.getNode()) {
5475 // Check to see if we got a select_cc back (to turn into setcc/select).
5476 // Otherwise, just return whatever node we got back, like fabs.
5477 if (SCC.getOpcode() == ISD::SELECT_CC) {
5478 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
5479 SCC.getOperand(0), SCC.getOperand(1),
5481 AddToWorkList(SETCC.getNode());
5482 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
5483 SCC.getOperand(3), SETCC);
5490 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
5491 /// are the two values being selected between, see if we can simplify the
5492 /// select. Callers of this should assume that TheSelect is deleted if this
5493 /// returns true. As such, they should return the appropriate thing (e.g. the
5494 /// node) back to the top-level of the DAG combiner loop to avoid it being
5497 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
5500 // If this is a select from two identical things, try to pull the operation
5501 // through the select.
5502 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
5503 // If this is a load and the token chain is identical, replace the select
5504 // of two loads with a load through a select of the address to load from.
5505 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
5506 // constants have been dropped into the constant pool.
5507 if (LHS.getOpcode() == ISD::LOAD &&
5508 // Do not let this transformation reduce the number of volatile loads.
5509 !cast<LoadSDNode>(LHS)->isVolatile() &&
5510 !cast<LoadSDNode>(RHS)->isVolatile() &&
5511 // Token chains must be identical.
5512 LHS.getOperand(0) == RHS.getOperand(0)) {
5513 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
5514 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
5516 // If this is an EXTLOAD, the VT's must match.
5517 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
5518 // FIXME: this conflates two src values, discarding one. This is not
5519 // the right thing to do, but nothing uses srcvalues now. When they do,
5520 // turn SrcValue into a list of locations.
5522 if (TheSelect->getOpcode() == ISD::SELECT) {
5523 // Check that the condition doesn't reach either load. If so, folding
5524 // this will induce a cycle into the DAG.
5525 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5526 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) {
5527 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
5528 TheSelect->getOperand(0), LLD->getBasePtr(),
5532 // Check that the condition doesn't reach either load. If so, folding
5533 // this will induce a cycle into the DAG.
5534 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5535 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5536 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) &&
5537 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) {
5538 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
5539 TheSelect->getOperand(0),
5540 TheSelect->getOperand(1),
5541 LLD->getBasePtr(), RLD->getBasePtr(),
5542 TheSelect->getOperand(4));
5546 if (Addr.getNode()) {
5548 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
5549 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
5550 Addr,LLD->getSrcValue(),
5551 LLD->getSrcValueOffset(),
5553 LLD->getAlignment());
5555 Load = DAG.getExtLoad(LLD->getExtensionType(),
5556 TheSelect->getValueType(0),
5557 LLD->getChain(), Addr, LLD->getSrcValue(),
5558 LLD->getSrcValueOffset(),
5561 LLD->getAlignment());
5563 // Users of the select now use the result of the load.
5564 CombineTo(TheSelect, Load);
5566 // Users of the old loads now use the new load's chain. We know the
5567 // old-load value is dead now.
5568 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
5569 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
5579 SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1,
5580 SDValue N2, SDValue N3,
5581 ISD::CondCode CC, bool NotExtCompare) {
5583 MVT VT = N2.getValueType();
5584 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
5585 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
5586 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
5588 // Determine if the condition we're dealing with is constant
5589 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
5591 if (SCC.getNode()) AddToWorkList(SCC.getNode());
5592 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
5594 // fold select_cc true, x, y -> x
5595 if (SCCC && !SCCC->isNullValue())
5597 // fold select_cc false, x, y -> y
5598 if (SCCC && SCCC->isNullValue())
5601 // Check to see if we can simplify the select into an fabs node
5602 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
5603 // Allow either -0.0 or 0.0
5604 if (CFP->getValueAPF().isZero()) {
5605 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
5606 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
5607 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
5608 N2 == N3.getOperand(0))
5609 return DAG.getNode(ISD::FABS, VT, N0);
5611 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
5612 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
5613 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
5614 N2.getOperand(0) == N3)
5615 return DAG.getNode(ISD::FABS, VT, N3);
5619 // Check to see if we can perform the "gzip trick", transforming
5620 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
5621 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
5622 N0.getValueType().isInteger() &&
5623 N2.getValueType().isInteger() &&
5624 (N1C->isNullValue() || // (a < 0) ? b : 0
5625 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
5626 MVT XType = N0.getValueType();
5627 MVT AType = N2.getValueType();
5628 if (XType.bitsGE(AType)) {
5629 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
5630 // single-bit constant.
5631 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
5632 unsigned ShCtV = N2C->getAPIntValue().logBase2();
5633 ShCtV = XType.getSizeInBits()-ShCtV-1;
5634 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
5635 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
5636 AddToWorkList(Shift.getNode());
5637 if (XType.bitsGT(AType)) {
5638 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
5639 AddToWorkList(Shift.getNode());
5641 return DAG.getNode(ISD::AND, AType, Shift, N2);
5643 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
5644 DAG.getConstant(XType.getSizeInBits()-1,
5645 TLI.getShiftAmountTy()));
5646 AddToWorkList(Shift.getNode());
5647 if (XType.bitsGT(AType)) {
5648 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
5649 AddToWorkList(Shift.getNode());
5651 return DAG.getNode(ISD::AND, AType, Shift, N2);
5655 // fold select C, 16, 0 -> shl C, 4
5656 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
5657 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
5659 // If the caller doesn't want us to simplify this into a zext of a compare,
5661 if (NotExtCompare && N2C->getAPIntValue() == 1)
5664 // Get a SetCC of the condition
5665 // FIXME: Should probably make sure that setcc is legal if we ever have a
5666 // target where it isn't.
5668 // cast from setcc result type to select result type
5670 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0.getValueType()),
5672 if (N2.getValueType().bitsLT(SCC.getValueType()))
5673 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
5675 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
5677 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
5678 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
5680 AddToWorkList(SCC.getNode());
5681 AddToWorkList(Temp.getNode());
5683 if (N2C->getAPIntValue() == 1)
5685 // shl setcc result by log2 n2c
5686 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
5687 DAG.getConstant(N2C->getAPIntValue().logBase2(),
5688 TLI.getShiftAmountTy()));
5691 // Check to see if this is the equivalent of setcc
5692 // FIXME: Turn all of these into setcc if setcc if setcc is legal
5693 // otherwise, go ahead with the folds.
5694 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
5695 MVT XType = N0.getValueType();
5696 if (!LegalOperations ||
5697 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
5698 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(XType), N0, N1, CC);
5699 if (Res.getValueType() != VT)
5700 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
5704 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
5705 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
5706 (!LegalOperations ||
5707 TLI.isOperationLegal(ISD::CTLZ, XType))) {
5708 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
5709 return DAG.getNode(ISD::SRL, XType, Ctlz,
5710 DAG.getConstant(Log2_32(XType.getSizeInBits()),
5711 TLI.getShiftAmountTy()));
5713 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
5714 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
5715 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
5717 SDValue NotN0 = DAG.getNOT(N0, XType);
5718 return DAG.getNode(ISD::SRL, XType,
5719 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
5720 DAG.getConstant(XType.getSizeInBits()-1,
5721 TLI.getShiftAmountTy()));
5723 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
5724 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
5725 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0,
5726 DAG.getConstant(XType.getSizeInBits()-1,
5727 TLI.getShiftAmountTy()));
5728 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
5732 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
5733 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5734 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
5735 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
5736 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
5737 MVT XType = N0.getValueType();
5738 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
5739 DAG.getConstant(XType.getSizeInBits()-1,
5740 TLI.getShiftAmountTy()));
5741 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5742 AddToWorkList(Shift.getNode());
5743 AddToWorkList(Add.getNode());
5744 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5746 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
5747 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5748 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
5749 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
5750 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
5751 MVT XType = N0.getValueType();
5752 if (SubC->isNullValue() && XType.isInteger()) {
5753 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0,
5754 DAG.getConstant(XType.getSizeInBits()-1,
5755 TLI.getShiftAmountTy()));
5756 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
5757 AddToWorkList(Shift.getNode());
5758 AddToWorkList(Add.getNode());
5759 return DAG.getNode(ISD::XOR, XType, Add, Shift);
5767 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
5768 SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0,
5769 SDValue N1, ISD::CondCode Cond,
5770 bool foldBooleans) {
5771 TargetLowering::DAGCombinerInfo
5772 DagCombineInfo(DAG, Level == Unrestricted, false, this);
5773 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
5776 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
5777 /// return a DAG expression to select that will generate the same value by
5778 /// multiplying by a magic number. See:
5779 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5780 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
5781 std::vector<SDNode*> Built;
5782 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
5784 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5790 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
5791 /// return a DAG expression to select that will generate the same value by
5792 /// multiplying by a magic number. See:
5793 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5794 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
5795 std::vector<SDNode*> Built;
5796 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
5798 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5804 /// FindBaseOffset - Return true if base is known not to alias with anything
5805 /// but itself. Provides base object and offset as results.
5806 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
5807 // Assume it is a primitive operation.
5808 Base = Ptr; Offset = 0;
5810 // If it's an adding a simple constant then integrate the offset.
5811 if (Base.getOpcode() == ISD::ADD) {
5812 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
5813 Base = Base.getOperand(0);
5814 Offset += C->getZExtValue();
5818 // If it's any of the following then it can't alias with anything but itself.
5819 return isa<FrameIndexSDNode>(Base) ||
5820 isa<ConstantPoolSDNode>(Base) ||
5821 isa<GlobalAddressSDNode>(Base);
5824 /// isAlias - Return true if there is any possibility that the two addresses
5826 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
5827 const Value *SrcValue1, int SrcValueOffset1,
5828 SDValue Ptr2, int64_t Size2,
5829 const Value *SrcValue2, int SrcValueOffset2)
5831 // If they are the same then they must be aliases.
5832 if (Ptr1 == Ptr2) return true;
5834 // Gather base node and offset information.
5835 SDValue Base1, Base2;
5836 int64_t Offset1, Offset2;
5837 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
5838 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
5840 // If they have a same base address then...
5841 if (Base1 == Base2) {
5842 // Check to see if the addresses overlap.
5843 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
5846 // If we know both bases then they can't alias.
5847 if (KnownBase1 && KnownBase2) return false;
5849 if (CombinerGlobalAA) {
5850 // Use alias analysis information.
5851 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
5852 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
5853 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
5854 AliasAnalysis::AliasResult AAResult =
5855 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
5856 if (AAResult == AliasAnalysis::NoAlias)
5860 // Otherwise we have to assume they alias.
5864 /// FindAliasInfo - Extracts the relevant alias information from the memory
5865 /// node. Returns true if the operand was a load.
5866 bool DAGCombiner::FindAliasInfo(SDNode *N,
5867 SDValue &Ptr, int64_t &Size,
5868 const Value *&SrcValue, int &SrcValueOffset) {
5869 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5870 Ptr = LD->getBasePtr();
5871 Size = LD->getMemoryVT().getSizeInBits() >> 3;
5872 SrcValue = LD->getSrcValue();
5873 SrcValueOffset = LD->getSrcValueOffset();
5875 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5876 Ptr = ST->getBasePtr();
5877 Size = ST->getMemoryVT().getSizeInBits() >> 3;
5878 SrcValue = ST->getSrcValue();
5879 SrcValueOffset = ST->getSrcValueOffset();
5881 assert(0 && "FindAliasInfo expected a memory operand");
5887 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
5888 /// looking for aliasing nodes and adding them to the Aliases vector.
5889 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
5890 SmallVector<SDValue, 8> &Aliases) {
5891 SmallVector<SDValue, 8> Chains; // List of chains to visit.
5892 std::set<SDNode *> Visited; // Visited node set.
5894 // Get alias information for node.
5897 const Value *SrcValue;
5899 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
5902 Chains.push_back(OriginalChain);
5904 // Look at each chain and determine if it is an alias. If so, add it to the
5905 // aliases list. If not, then continue up the chain looking for the next
5907 while (!Chains.empty()) {
5908 SDValue Chain = Chains.back();
5911 // Don't bother if we've been before.
5912 if (Visited.find(Chain.getNode()) != Visited.end()) continue;
5913 Visited.insert(Chain.getNode());
5915 switch (Chain.getOpcode()) {
5916 case ISD::EntryToken:
5917 // Entry token is ideal chain operand, but handled in FindBetterChain.
5922 // Get alias information for Chain.
5925 const Value *OpSrcValue;
5926 int OpSrcValueOffset;
5927 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
5928 OpSrcValue, OpSrcValueOffset);
5930 // If chain is alias then stop here.
5931 if (!(IsLoad && IsOpLoad) &&
5932 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
5933 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
5934 Aliases.push_back(Chain);
5936 // Look further up the chain.
5937 Chains.push_back(Chain.getOperand(0));
5938 // Clean up old chain.
5939 AddToWorkList(Chain.getNode());
5944 case ISD::TokenFactor:
5945 // We have to check each of the operands of the token factor, so we queue
5946 // then up. Adding the operands to the queue (stack) in reverse order
5947 // maintains the original order and increases the likelihood that getNode
5948 // will find a matching token factor (CSE.)
5949 for (unsigned n = Chain.getNumOperands(); n;)
5950 Chains.push_back(Chain.getOperand(--n));
5951 // Eliminate the token factor if we can.
5952 AddToWorkList(Chain.getNode());
5956 // For all other instructions we will just have to take what we can get.
5957 Aliases.push_back(Chain);
5963 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
5964 /// for a better chain (aliasing node.)
5965 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
5966 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
5968 // Accumulate all the aliases to this node.
5969 GatherAllAliases(N, OldChain, Aliases);
5971 if (Aliases.size() == 0) {
5972 // If no operands then chain to entry token.
5973 return DAG.getEntryNode();
5974 } else if (Aliases.size() == 1) {
5975 // If a single operand then chain to it. We don't need to revisit it.
5979 // Construct a custom tailored token factor.
5980 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5981 &Aliases[0], Aliases.size());
5983 // Make sure the old chain gets cleaned up.
5984 if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
5989 // SelectionDAG::Combine - This is the entry point for the file.
5991 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) {
5992 /// run - This is the main entry point to this class.
5994 DAGCombiner(*this, AA, Fast).Run(Level);