1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/CommandLine.h"
46 static Statistic<> NodesCombined ("dagcombiner",
47 "Number of dag nodes combined");
50 CombinerAA("combiner-alias-analysis", cl::Hidden,
51 cl::desc("Turn on alias analysis turning testing"));
53 //------------------------------ DAGCombiner ---------------------------------//
55 class VISIBILITY_HIDDEN DAGCombiner {
60 // Worklist of all of the nodes that need to be simplified.
61 std::vector<SDNode*> WorkList;
63 /// AddUsersToWorkList - When an instruction is simplified, add all users of
64 /// the instruction to the work lists because they might get more simplified
67 void AddUsersToWorkList(SDNode *N) {
68 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
73 /// removeFromWorkList - remove all instances of N from the worklist.
75 void removeFromWorkList(SDNode *N) {
76 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
81 /// AddToWorkList - Add to the work list making sure it's instance is at the
82 /// the back (next to be processed.)
83 void AddToWorkList(SDNode *N) {
84 removeFromWorkList(N);
85 WorkList.push_back(N);
88 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo) {
89 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
91 DEBUG(std::cerr << "\nReplacing.1 "; N->dump();
92 std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
93 std::cerr << " and " << NumTo-1 << " other values\n");
94 std::vector<SDNode*> NowDead;
95 DAG.ReplaceAllUsesWith(N, To, &NowDead);
97 // Push the new nodes and any users onto the worklist
98 for (unsigned i = 0, e = NumTo; i != e; ++i) {
99 AddToWorkList(To[i].Val);
100 AddUsersToWorkList(To[i].Val);
103 // Nodes can be reintroduced into the worklist. Make sure we do not
104 // process a node that has been replaced.
105 removeFromWorkList(N);
106 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
107 removeFromWorkList(NowDead[i]);
109 // Finally, since the node is now dead, remove it from the graph.
111 return SDOperand(N, 0);
114 SDOperand CombineTo(SDNode *N, SDOperand Res) {
115 return CombineTo(N, &Res, 1);
118 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
119 SDOperand To[] = { Res0, Res1 };
120 return CombineTo(N, To, 2);
124 /// SimplifyDemandedBits - Check the specified integer node value to see if
125 /// it can be simplified or if things it uses can be simplified by bit
126 /// propagation. If so, return true.
127 bool SimplifyDemandedBits(SDOperand Op) {
128 TargetLowering::TargetLoweringOpt TLO(DAG);
129 uint64_t KnownZero, KnownOne;
130 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
131 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
135 AddToWorkList(Op.Val);
137 // Replace the old value with the new one.
139 DEBUG(std::cerr << "\nReplacing.2 "; TLO.Old.Val->dump();
140 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG);
143 std::vector<SDNode*> NowDead;
144 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
146 // Push the new node and any (possibly new) users onto the worklist.
147 AddToWorkList(TLO.New.Val);
148 AddUsersToWorkList(TLO.New.Val);
150 // Nodes can end up on the worklist more than once. Make sure we do
151 // not process a node that has been replaced.
152 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
153 removeFromWorkList(NowDead[i]);
155 // Finally, if the node is now dead, remove it from the graph. The node
156 // may not be dead if the replacement process recursively simplified to
157 // something else needing this node.
158 if (TLO.Old.Val->use_empty()) {
159 removeFromWorkList(TLO.Old.Val);
160 DAG.DeleteNode(TLO.Old.Val);
165 /// visit - call the node-specific routine that knows how to fold each
166 /// particular type of node.
167 SDOperand visit(SDNode *N);
169 // Visitation implementation - Implement dag node combining for different
170 // node types. The semantics are as follows:
172 // SDOperand.Val == 0 - No change was made
173 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
174 // otherwise - N should be replaced by the returned Operand.
176 SDOperand visitTokenFactor(SDNode *N);
177 SDOperand visitADD(SDNode *N);
178 SDOperand visitSUB(SDNode *N);
179 SDOperand visitMUL(SDNode *N);
180 SDOperand visitSDIV(SDNode *N);
181 SDOperand visitUDIV(SDNode *N);
182 SDOperand visitSREM(SDNode *N);
183 SDOperand visitUREM(SDNode *N);
184 SDOperand visitMULHU(SDNode *N);
185 SDOperand visitMULHS(SDNode *N);
186 SDOperand visitAND(SDNode *N);
187 SDOperand visitOR(SDNode *N);
188 SDOperand visitXOR(SDNode *N);
189 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
190 SDOperand visitSHL(SDNode *N);
191 SDOperand visitSRA(SDNode *N);
192 SDOperand visitSRL(SDNode *N);
193 SDOperand visitCTLZ(SDNode *N);
194 SDOperand visitCTTZ(SDNode *N);
195 SDOperand visitCTPOP(SDNode *N);
196 SDOperand visitSELECT(SDNode *N);
197 SDOperand visitSELECT_CC(SDNode *N);
198 SDOperand visitSETCC(SDNode *N);
199 SDOperand visitSIGN_EXTEND(SDNode *N);
200 SDOperand visitZERO_EXTEND(SDNode *N);
201 SDOperand visitANY_EXTEND(SDNode *N);
202 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
203 SDOperand visitTRUNCATE(SDNode *N);
204 SDOperand visitBIT_CONVERT(SDNode *N);
205 SDOperand visitVBIT_CONVERT(SDNode *N);
206 SDOperand visitFADD(SDNode *N);
207 SDOperand visitFSUB(SDNode *N);
208 SDOperand visitFMUL(SDNode *N);
209 SDOperand visitFDIV(SDNode *N);
210 SDOperand visitFREM(SDNode *N);
211 SDOperand visitFCOPYSIGN(SDNode *N);
212 SDOperand visitSINT_TO_FP(SDNode *N);
213 SDOperand visitUINT_TO_FP(SDNode *N);
214 SDOperand visitFP_TO_SINT(SDNode *N);
215 SDOperand visitFP_TO_UINT(SDNode *N);
216 SDOperand visitFP_ROUND(SDNode *N);
217 SDOperand visitFP_ROUND_INREG(SDNode *N);
218 SDOperand visitFP_EXTEND(SDNode *N);
219 SDOperand visitFNEG(SDNode *N);
220 SDOperand visitFABS(SDNode *N);
221 SDOperand visitBRCOND(SDNode *N);
222 SDOperand visitBR_CC(SDNode *N);
223 SDOperand visitLOAD(SDNode *N);
224 SDOperand visitSTORE(SDNode *N);
225 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
226 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
227 SDOperand visitVBUILD_VECTOR(SDNode *N);
228 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
229 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
231 SDOperand XformToShuffleWithZero(SDNode *N);
232 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
234 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
235 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
236 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
237 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
238 SDOperand N3, ISD::CondCode CC);
239 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
240 ISD::CondCode Cond, bool foldBooleans = true);
241 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
242 SDOperand BuildSDIV(SDNode *N);
243 SDOperand BuildUDIV(SDNode *N);
244 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
246 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
247 /// looking for aliasing nodes and adding them to the Aliases vector.
248 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
249 SmallVector<SDOperand, 8> &Aliases);
251 /// FindAliasInfo - Extracts the relevant alias information from the memory
252 /// node. Returns true if the operand was a load.
253 bool FindAliasInfo(SDNode *N,
254 SDOperand &Ptr, int64_t &Size, const Value *&SrcValue);
256 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
257 /// looking for a better chain (aliasing node.)
258 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
261 DAGCombiner(SelectionDAG &D)
262 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
264 /// Run - runs the dag combiner on all nodes in the work list
265 void Run(bool RunningAfterLegalize);
269 //===----------------------------------------------------------------------===//
270 // TargetLowering::DAGCombinerInfo implementation
271 //===----------------------------------------------------------------------===//
273 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
274 ((DAGCombiner*)DC)->AddToWorkList(N);
277 SDOperand TargetLowering::DAGCombinerInfo::
278 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
279 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
282 SDOperand TargetLowering::DAGCombinerInfo::
283 CombineTo(SDNode *N, SDOperand Res) {
284 return ((DAGCombiner*)DC)->CombineTo(N, Res);
288 SDOperand TargetLowering::DAGCombinerInfo::
289 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
290 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
296 //===----------------------------------------------------------------------===//
299 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
300 // that selects between the values 1 and 0, making it equivalent to a setcc.
301 // Also, set the incoming LHS, RHS, and CC references to the appropriate
302 // nodes based on the type of node we are checking. This simplifies life a
303 // bit for the callers.
304 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
306 if (N.getOpcode() == ISD::SETCC) {
307 LHS = N.getOperand(0);
308 RHS = N.getOperand(1);
309 CC = N.getOperand(2);
312 if (N.getOpcode() == ISD::SELECT_CC &&
313 N.getOperand(2).getOpcode() == ISD::Constant &&
314 N.getOperand(3).getOpcode() == ISD::Constant &&
315 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
316 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
317 LHS = N.getOperand(0);
318 RHS = N.getOperand(1);
319 CC = N.getOperand(4);
325 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
326 // one use. If this is true, it allows the users to invert the operation for
327 // free when it is profitable to do so.
328 static bool isOneUseSetCC(SDOperand N) {
329 SDOperand N0, N1, N2;
330 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
335 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
336 MVT::ValueType VT = N0.getValueType();
337 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
338 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
339 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
340 if (isa<ConstantSDNode>(N1)) {
341 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
342 AddToWorkList(OpNode.Val);
343 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
344 } else if (N0.hasOneUse()) {
345 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
346 AddToWorkList(OpNode.Val);
347 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
350 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
351 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
352 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
353 if (isa<ConstantSDNode>(N0)) {
354 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
355 AddToWorkList(OpNode.Val);
356 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
357 } else if (N1.hasOneUse()) {
358 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
359 AddToWorkList(OpNode.Val);
360 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
366 void DAGCombiner::Run(bool RunningAfterLegalize) {
367 // set the instance variable, so that the various visit routines may use it.
368 AfterLegalize = RunningAfterLegalize;
370 // Add all the dag nodes to the worklist.
371 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
372 E = DAG.allnodes_end(); I != E; ++I)
373 WorkList.push_back(I);
375 // Create a dummy node (which is not added to allnodes), that adds a reference
376 // to the root node, preventing it from being deleted, and tracking any
377 // changes of the root.
378 HandleSDNode Dummy(DAG.getRoot());
381 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
382 TargetLowering::DAGCombinerInfo
383 DagCombineInfo(DAG, !RunningAfterLegalize, this);
385 // while the worklist isn't empty, inspect the node on the end of it and
386 // try and combine it.
387 while (!WorkList.empty()) {
388 SDNode *N = WorkList.back();
391 // If N has no uses, it is dead. Make sure to revisit all N's operands once
392 // N is deleted from the DAG, since they too may now be dead or may have a
393 // reduced number of uses, allowing other xforms.
394 if (N->use_empty() && N != &Dummy) {
395 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
396 AddToWorkList(N->getOperand(i).Val);
402 SDOperand RV = visit(N);
404 // If nothing happened, try a target-specific DAG combine.
406 assert(N->getOpcode() != ISD::DELETED_NODE &&
407 "Node was deleted but visit returned NULL!");
408 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
409 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
410 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
415 // If we get back the same node we passed in, rather than a new node or
416 // zero, we know that the node must have defined multiple values and
417 // CombineTo was used. Since CombineTo takes care of the worklist
418 // mechanics for us, we have no work to do in this case.
420 assert(N->getOpcode() != ISD::DELETED_NODE &&
421 RV.Val->getOpcode() != ISD::DELETED_NODE &&
422 "Node was deleted but visit returned new node!");
424 DEBUG(std::cerr << "\nReplacing.3 "; N->dump();
425 std::cerr << "\nWith: "; RV.Val->dump(&DAG);
427 std::vector<SDNode*> NowDead;
428 if (N->getNumValues() == RV.Val->getNumValues())
429 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
431 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
433 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
436 // Push the new node and any users onto the worklist
437 AddToWorkList(RV.Val);
438 AddUsersToWorkList(RV.Val);
440 // Nodes can be reintroduced into the worklist. Make sure we do not
441 // process a node that has been replaced.
442 removeFromWorkList(N);
443 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
444 removeFromWorkList(NowDead[i]);
446 // Finally, since the node is now dead, remove it from the graph.
452 // If the root changed (e.g. it was a dead load, update the root).
453 DAG.setRoot(Dummy.getValue());
456 SDOperand DAGCombiner::visit(SDNode *N) {
457 switch(N->getOpcode()) {
459 case ISD::TokenFactor: return visitTokenFactor(N);
460 case ISD::ADD: return visitADD(N);
461 case ISD::SUB: return visitSUB(N);
462 case ISD::MUL: return visitMUL(N);
463 case ISD::SDIV: return visitSDIV(N);
464 case ISD::UDIV: return visitUDIV(N);
465 case ISD::SREM: return visitSREM(N);
466 case ISD::UREM: return visitUREM(N);
467 case ISD::MULHU: return visitMULHU(N);
468 case ISD::MULHS: return visitMULHS(N);
469 case ISD::AND: return visitAND(N);
470 case ISD::OR: return visitOR(N);
471 case ISD::XOR: return visitXOR(N);
472 case ISD::SHL: return visitSHL(N);
473 case ISD::SRA: return visitSRA(N);
474 case ISD::SRL: return visitSRL(N);
475 case ISD::CTLZ: return visitCTLZ(N);
476 case ISD::CTTZ: return visitCTTZ(N);
477 case ISD::CTPOP: return visitCTPOP(N);
478 case ISD::SELECT: return visitSELECT(N);
479 case ISD::SELECT_CC: return visitSELECT_CC(N);
480 case ISD::SETCC: return visitSETCC(N);
481 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
482 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
483 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
484 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
485 case ISD::TRUNCATE: return visitTRUNCATE(N);
486 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
487 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
488 case ISD::FADD: return visitFADD(N);
489 case ISD::FSUB: return visitFSUB(N);
490 case ISD::FMUL: return visitFMUL(N);
491 case ISD::FDIV: return visitFDIV(N);
492 case ISD::FREM: return visitFREM(N);
493 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
494 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
495 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
496 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
497 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
498 case ISD::FP_ROUND: return visitFP_ROUND(N);
499 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
500 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
501 case ISD::FNEG: return visitFNEG(N);
502 case ISD::FABS: return visitFABS(N);
503 case ISD::BRCOND: return visitBRCOND(N);
504 case ISD::BR_CC: return visitBR_CC(N);
505 case ISD::LOAD: return visitLOAD(N);
506 case ISD::STORE: return visitSTORE(N);
507 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
508 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
509 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
510 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
511 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
512 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
513 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
514 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
515 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
516 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
517 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
518 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
519 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
524 /// getInputChainForNode - Given a node, return its input chain if it has one,
525 /// otherwise return a null sd operand.
526 static SDOperand getInputChainForNode(SDNode *N) {
527 if (unsigned NumOps = N->getNumOperands()) {
528 if (N->getOperand(0).getValueType() == MVT::Other)
529 return N->getOperand(0);
530 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
531 return N->getOperand(NumOps-1);
532 for (unsigned i = 1; i < NumOps-1; ++i)
533 if (N->getOperand(i).getValueType() == MVT::Other)
534 return N->getOperand(i);
536 return SDOperand(0, 0);
539 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
540 // If N has two operands, where one has an input chain equal to the other,
541 // the 'other' chain is redundant.
542 if (N->getNumOperands() == 2) {
543 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
544 return N->getOperand(0);
545 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
546 return N->getOperand(1);
550 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
551 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
552 bool Changed = false; // If we should replace this token factor.
554 // Start out with this token factor.
557 // Iterate through token factors. The TFs grows when new token factors are
559 for (unsigned i = 0; i < TFs.size(); ++i) {
562 // Check each of the operands.
563 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
564 SDOperand Op = TF->getOperand(i);
566 switch (Op.getOpcode()) {
567 case ISD::EntryToken:
568 // Entry tokens don't need to be added to the list. They are
573 case ISD::TokenFactor:
574 if ((CombinerAA || Op.hasOneUse()) &&
575 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
576 // Queue up for processing.
577 TFs.push_back(Op.Val);
578 // Clean up in case the token factor is removed.
579 AddToWorkList(Op.Val);
586 // Only add if not there prior.
587 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
596 // If we've change things around then replace token factor.
598 if (Ops.size() == 0) {
599 // The entry token is the only possible outcome.
600 Result = DAG.getEntryNode();
602 // New and improved token factor.
603 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
610 SDOperand DAGCombiner::visitADD(SDNode *N) {
611 SDOperand N0 = N->getOperand(0);
612 SDOperand N1 = N->getOperand(1);
613 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
614 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
615 MVT::ValueType VT = N0.getValueType();
617 // fold (add c1, c2) -> c1+c2
619 return DAG.getNode(ISD::ADD, VT, N0, N1);
620 // canonicalize constant to RHS
622 return DAG.getNode(ISD::ADD, VT, N1, N0);
623 // fold (add x, 0) -> x
624 if (N1C && N1C->isNullValue())
626 // fold ((c1-A)+c2) -> (c1+c2)-A
627 if (N1C && N0.getOpcode() == ISD::SUB)
628 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
629 return DAG.getNode(ISD::SUB, VT,
630 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
633 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
636 // fold ((0-A) + B) -> B-A
637 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
638 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
639 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
640 // fold (A + (0-B)) -> A-B
641 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
642 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
643 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
644 // fold (A+(B-A)) -> B
645 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
646 return N1.getOperand(0);
648 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
649 return SDOperand(N, 0);
651 // fold (a+b) -> (a|b) iff a and b share no bits.
652 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
653 uint64_t LHSZero, LHSOne;
654 uint64_t RHSZero, RHSOne;
655 uint64_t Mask = MVT::getIntVTBitMask(VT);
656 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
658 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
660 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
661 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
662 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
663 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
664 return DAG.getNode(ISD::OR, VT, N0, N1);
671 SDOperand DAGCombiner::visitSUB(SDNode *N) {
672 SDOperand N0 = N->getOperand(0);
673 SDOperand N1 = N->getOperand(1);
674 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
675 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
676 MVT::ValueType VT = N0.getValueType();
678 // fold (sub x, x) -> 0
680 return DAG.getConstant(0, N->getValueType(0));
681 // fold (sub c1, c2) -> c1-c2
683 return DAG.getNode(ISD::SUB, VT, N0, N1);
684 // fold (sub x, c) -> (add x, -c)
686 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
688 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
689 return N0.getOperand(1);
691 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
692 return N0.getOperand(0);
696 SDOperand DAGCombiner::visitMUL(SDNode *N) {
697 SDOperand N0 = N->getOperand(0);
698 SDOperand N1 = N->getOperand(1);
699 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
700 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
701 MVT::ValueType VT = N0.getValueType();
703 // fold (mul c1, c2) -> c1*c2
705 return DAG.getNode(ISD::MUL, VT, N0, N1);
706 // canonicalize constant to RHS
708 return DAG.getNode(ISD::MUL, VT, N1, N0);
709 // fold (mul x, 0) -> 0
710 if (N1C && N1C->isNullValue())
712 // fold (mul x, -1) -> 0-x
713 if (N1C && N1C->isAllOnesValue())
714 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
715 // fold (mul x, (1 << c)) -> x << c
716 if (N1C && isPowerOf2_64(N1C->getValue()))
717 return DAG.getNode(ISD::SHL, VT, N0,
718 DAG.getConstant(Log2_64(N1C->getValue()),
719 TLI.getShiftAmountTy()));
720 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
721 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
722 // FIXME: If the input is something that is easily negated (e.g. a
723 // single-use add), we should put the negate there.
724 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
725 DAG.getNode(ISD::SHL, VT, N0,
726 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
727 TLI.getShiftAmountTy())));
730 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
731 if (N1C && N0.getOpcode() == ISD::SHL &&
732 isa<ConstantSDNode>(N0.getOperand(1))) {
733 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
734 AddToWorkList(C3.Val);
735 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
738 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
741 SDOperand Sh(0,0), Y(0,0);
742 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
743 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
744 N0.Val->hasOneUse()) {
746 } else if (N1.getOpcode() == ISD::SHL &&
747 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
751 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
752 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
755 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
756 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
757 isa<ConstantSDNode>(N0.getOperand(1))) {
758 return DAG.getNode(ISD::ADD, VT,
759 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
760 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
764 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
770 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
771 SDOperand N0 = N->getOperand(0);
772 SDOperand N1 = N->getOperand(1);
773 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
774 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
775 MVT::ValueType VT = N->getValueType(0);
777 // fold (sdiv c1, c2) -> c1/c2
778 if (N0C && N1C && !N1C->isNullValue())
779 return DAG.getNode(ISD::SDIV, VT, N0, N1);
780 // fold (sdiv X, 1) -> X
781 if (N1C && N1C->getSignExtended() == 1LL)
783 // fold (sdiv X, -1) -> 0-X
784 if (N1C && N1C->isAllOnesValue())
785 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
786 // If we know the sign bits of both operands are zero, strength reduce to a
787 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
788 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
789 if (TLI.MaskedValueIsZero(N1, SignBit) &&
790 TLI.MaskedValueIsZero(N0, SignBit))
791 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
792 // fold (sdiv X, pow2) -> simple ops after legalize
793 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
794 (isPowerOf2_64(N1C->getSignExtended()) ||
795 isPowerOf2_64(-N1C->getSignExtended()))) {
796 // If dividing by powers of two is cheap, then don't perform the following
798 if (TLI.isPow2DivCheap())
800 int64_t pow2 = N1C->getSignExtended();
801 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
802 unsigned lg2 = Log2_64(abs2);
803 // Splat the sign bit into the register
804 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
805 DAG.getConstant(MVT::getSizeInBits(VT)-1,
806 TLI.getShiftAmountTy()));
807 AddToWorkList(SGN.Val);
808 // Add (N0 < 0) ? abs2 - 1 : 0;
809 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
810 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
811 TLI.getShiftAmountTy()));
812 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
813 AddToWorkList(SRL.Val);
814 AddToWorkList(ADD.Val); // Divide by pow2
815 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
816 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
817 // If we're dividing by a positive value, we're done. Otherwise, we must
818 // negate the result.
821 AddToWorkList(SRA.Val);
822 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
824 // if integer divide is expensive and we satisfy the requirements, emit an
825 // alternate sequence.
826 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
827 !TLI.isIntDivCheap()) {
828 SDOperand Op = BuildSDIV(N);
829 if (Op.Val) return Op;
834 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
835 SDOperand N0 = N->getOperand(0);
836 SDOperand N1 = N->getOperand(1);
837 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
838 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
839 MVT::ValueType VT = N->getValueType(0);
841 // fold (udiv c1, c2) -> c1/c2
842 if (N0C && N1C && !N1C->isNullValue())
843 return DAG.getNode(ISD::UDIV, VT, N0, N1);
844 // fold (udiv x, (1 << c)) -> x >>u c
845 if (N1C && isPowerOf2_64(N1C->getValue()))
846 return DAG.getNode(ISD::SRL, VT, N0,
847 DAG.getConstant(Log2_64(N1C->getValue()),
848 TLI.getShiftAmountTy()));
849 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
850 if (N1.getOpcode() == ISD::SHL) {
851 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
852 if (isPowerOf2_64(SHC->getValue())) {
853 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
854 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
855 DAG.getConstant(Log2_64(SHC->getValue()),
857 AddToWorkList(Add.Val);
858 return DAG.getNode(ISD::SRL, VT, N0, Add);
862 // fold (udiv x, c) -> alternate
863 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
864 SDOperand Op = BuildUDIV(N);
865 if (Op.Val) return Op;
870 SDOperand DAGCombiner::visitSREM(SDNode *N) {
871 SDOperand N0 = N->getOperand(0);
872 SDOperand N1 = N->getOperand(1);
873 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
874 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
875 MVT::ValueType VT = N->getValueType(0);
877 // fold (srem c1, c2) -> c1%c2
878 if (N0C && N1C && !N1C->isNullValue())
879 return DAG.getNode(ISD::SREM, VT, N0, N1);
880 // If we know the sign bits of both operands are zero, strength reduce to a
881 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
882 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
883 if (TLI.MaskedValueIsZero(N1, SignBit) &&
884 TLI.MaskedValueIsZero(N0, SignBit))
885 return DAG.getNode(ISD::UREM, VT, N0, N1);
887 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
888 // the remainder operation.
889 if (N1C && !N1C->isNullValue()) {
890 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
891 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
892 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
893 AddToWorkList(Div.Val);
894 AddToWorkList(Mul.Val);
901 SDOperand DAGCombiner::visitUREM(SDNode *N) {
902 SDOperand N0 = N->getOperand(0);
903 SDOperand N1 = N->getOperand(1);
904 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
905 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
906 MVT::ValueType VT = N->getValueType(0);
908 // fold (urem c1, c2) -> c1%c2
909 if (N0C && N1C && !N1C->isNullValue())
910 return DAG.getNode(ISD::UREM, VT, N0, N1);
911 // fold (urem x, pow2) -> (and x, pow2-1)
912 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
913 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
914 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
915 if (N1.getOpcode() == ISD::SHL) {
916 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
917 if (isPowerOf2_64(SHC->getValue())) {
918 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
919 AddToWorkList(Add.Val);
920 return DAG.getNode(ISD::AND, VT, N0, Add);
925 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
926 // the remainder operation.
927 if (N1C && !N1C->isNullValue()) {
928 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
929 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
930 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
931 AddToWorkList(Div.Val);
932 AddToWorkList(Mul.Val);
939 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
940 SDOperand N0 = N->getOperand(0);
941 SDOperand N1 = N->getOperand(1);
942 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
944 // fold (mulhs x, 0) -> 0
945 if (N1C && N1C->isNullValue())
947 // fold (mulhs x, 1) -> (sra x, size(x)-1)
948 if (N1C && N1C->getValue() == 1)
949 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
950 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
951 TLI.getShiftAmountTy()));
955 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
956 SDOperand N0 = N->getOperand(0);
957 SDOperand N1 = N->getOperand(1);
958 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
960 // fold (mulhu x, 0) -> 0
961 if (N1C && N1C->isNullValue())
963 // fold (mulhu x, 1) -> 0
964 if (N1C && N1C->getValue() == 1)
965 return DAG.getConstant(0, N0.getValueType());
969 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
970 /// two operands of the same opcode, try to simplify it.
971 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
972 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
973 MVT::ValueType VT = N0.getValueType();
974 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
976 // For each of OP in AND/OR/XOR:
977 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
978 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
979 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
980 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
981 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
982 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
983 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
984 SDOperand ORNode = DAG.getNode(N->getOpcode(),
985 N0.getOperand(0).getValueType(),
986 N0.getOperand(0), N1.getOperand(0));
987 AddToWorkList(ORNode.Val);
988 return DAG.getNode(N0.getOpcode(), VT, ORNode);
991 // For each of OP in SHL/SRL/SRA/AND...
992 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
993 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
994 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
995 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
996 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
997 N0.getOperand(1) == N1.getOperand(1)) {
998 SDOperand ORNode = DAG.getNode(N->getOpcode(),
999 N0.getOperand(0).getValueType(),
1000 N0.getOperand(0), N1.getOperand(0));
1001 AddToWorkList(ORNode.Val);
1002 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1008 SDOperand DAGCombiner::visitAND(SDNode *N) {
1009 SDOperand N0 = N->getOperand(0);
1010 SDOperand N1 = N->getOperand(1);
1011 SDOperand LL, LR, RL, RR, CC0, CC1;
1012 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1013 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1014 MVT::ValueType VT = N1.getValueType();
1015 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1017 // fold (and c1, c2) -> c1&c2
1019 return DAG.getNode(ISD::AND, VT, N0, N1);
1020 // canonicalize constant to RHS
1022 return DAG.getNode(ISD::AND, VT, N1, N0);
1023 // fold (and x, -1) -> x
1024 if (N1C && N1C->isAllOnesValue())
1026 // if (and x, c) is known to be zero, return 0
1027 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1028 return DAG.getConstant(0, VT);
1030 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1033 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1034 if (N1C && N0.getOpcode() == ISD::OR)
1035 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1036 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1038 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1039 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1040 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1041 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1042 ~N1C->getValue() & InMask)) {
1043 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1046 // Replace uses of the AND with uses of the Zero extend node.
1049 // We actually want to replace all uses of the any_extend with the
1050 // zero_extend, to avoid duplicating things. This will later cause this
1051 // AND to be folded.
1052 CombineTo(N0.Val, Zext);
1053 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1056 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1057 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1058 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1059 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1061 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1062 MVT::isInteger(LL.getValueType())) {
1063 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1064 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1065 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1066 AddToWorkList(ORNode.Val);
1067 return DAG.getSetCC(VT, ORNode, LR, Op1);
1069 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1070 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1071 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1072 AddToWorkList(ANDNode.Val);
1073 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1075 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1076 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1077 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1078 AddToWorkList(ORNode.Val);
1079 return DAG.getSetCC(VT, ORNode, LR, Op1);
1082 // canonicalize equivalent to ll == rl
1083 if (LL == RR && LR == RL) {
1084 Op1 = ISD::getSetCCSwappedOperands(Op1);
1087 if (LL == RL && LR == RR) {
1088 bool isInteger = MVT::isInteger(LL.getValueType());
1089 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1090 if (Result != ISD::SETCC_INVALID)
1091 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1095 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1096 if (N0.getOpcode() == N1.getOpcode()) {
1097 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1098 if (Tmp.Val) return Tmp;
1101 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1102 // fold (and (sra)) -> (and (srl)) when possible.
1103 if (!MVT::isVector(VT) &&
1104 SimplifyDemandedBits(SDOperand(N, 0)))
1105 return SDOperand(N, 0);
1106 // fold (zext_inreg (extload x)) -> (zextload x)
1107 if (ISD::isEXTLoad(N0.Val)) {
1108 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1109 MVT::ValueType EVT = LN0->getLoadedVT();
1110 // If we zero all the possible extended bits, then we can turn this into
1111 // a zextload if we are running before legalize or the operation is legal.
1112 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1113 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1114 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1115 LN0->getBasePtr(), LN0->getSrcValue(),
1116 LN0->getSrcValueOffset(), EVT);
1118 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1119 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1122 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1123 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
1124 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1125 MVT::ValueType EVT = LN0->getLoadedVT();
1126 // If we zero all the possible extended bits, then we can turn this into
1127 // a zextload if we are running before legalize or the operation is legal.
1128 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1129 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1130 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1131 LN0->getBasePtr(), LN0->getSrcValue(),
1132 LN0->getSrcValueOffset(), EVT);
1134 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1135 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1139 // fold (and (load x), 255) -> (zextload x, i8)
1140 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1141 if (N1C && N0.getOpcode() == ISD::LOAD) {
1142 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1143 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1145 MVT::ValueType EVT, LoadedVT;
1146 if (N1C->getValue() == 255)
1148 else if (N1C->getValue() == 65535)
1150 else if (N1C->getValue() == ~0U)
1155 LoadedVT = LN0->getLoadedVT();
1156 if (EVT != MVT::Other && LoadedVT > EVT &&
1157 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1158 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1159 // For big endian targets, we need to add an offset to the pointer to
1160 // load the correct bytes. For little endian systems, we merely need to
1161 // read fewer bytes from the same pointer.
1163 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1164 SDOperand NewPtr = LN0->getBasePtr();
1165 if (!TLI.isLittleEndian())
1166 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1167 DAG.getConstant(PtrOff, PtrType));
1168 AddToWorkList(NewPtr.Val);
1170 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1171 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1173 CombineTo(N0.Val, Load, Load.getValue(1));
1174 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1182 SDOperand DAGCombiner::visitOR(SDNode *N) {
1183 SDOperand N0 = N->getOperand(0);
1184 SDOperand N1 = N->getOperand(1);
1185 SDOperand LL, LR, RL, RR, CC0, CC1;
1186 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1187 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1188 MVT::ValueType VT = N1.getValueType();
1189 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1191 // fold (or c1, c2) -> c1|c2
1193 return DAG.getNode(ISD::OR, VT, N0, N1);
1194 // canonicalize constant to RHS
1196 return DAG.getNode(ISD::OR, VT, N1, N0);
1197 // fold (or x, 0) -> x
1198 if (N1C && N1C->isNullValue())
1200 // fold (or x, -1) -> -1
1201 if (N1C && N1C->isAllOnesValue())
1203 // fold (or x, c) -> c iff (x & ~c) == 0
1205 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1208 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1211 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1212 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1213 isa<ConstantSDNode>(N0.getOperand(1))) {
1214 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1215 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1217 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1219 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1220 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1221 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1222 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1224 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1225 MVT::isInteger(LL.getValueType())) {
1226 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1227 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1228 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1229 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1230 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1231 AddToWorkList(ORNode.Val);
1232 return DAG.getSetCC(VT, ORNode, LR, Op1);
1234 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1235 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1236 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1237 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1238 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1239 AddToWorkList(ANDNode.Val);
1240 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1243 // canonicalize equivalent to ll == rl
1244 if (LL == RR && LR == RL) {
1245 Op1 = ISD::getSetCCSwappedOperands(Op1);
1248 if (LL == RL && LR == RR) {
1249 bool isInteger = MVT::isInteger(LL.getValueType());
1250 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1251 if (Result != ISD::SETCC_INVALID)
1252 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1256 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1257 if (N0.getOpcode() == N1.getOpcode()) {
1258 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1259 if (Tmp.Val) return Tmp;
1262 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1263 if (N0.getOpcode() == ISD::AND &&
1264 N1.getOpcode() == ISD::AND &&
1265 N0.getOperand(1).getOpcode() == ISD::Constant &&
1266 N1.getOperand(1).getOpcode() == ISD::Constant &&
1267 // Don't increase # computations.
1268 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1269 // We can only do this xform if we know that bits from X that are set in C2
1270 // but not in C1 are already zero. Likewise for Y.
1271 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1272 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1274 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1275 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1276 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1277 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1282 // See if this is some rotate idiom.
1283 if (SDNode *Rot = MatchRotate(N0, N1))
1284 return SDOperand(Rot, 0);
1290 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1291 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1292 if (Op.getOpcode() == ISD::AND) {
1293 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1294 Mask = Op.getOperand(1);
1295 Op = Op.getOperand(0);
1301 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1309 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1310 // idioms for rotate, and if the target supports rotation instructions, generate
1312 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1313 // Must be a legal type. Expanded an promoted things won't work with rotates.
1314 MVT::ValueType VT = LHS.getValueType();
1315 if (!TLI.isTypeLegal(VT)) return 0;
1317 // The target must have at least one rotate flavor.
1318 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1319 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1320 if (!HasROTL && !HasROTR) return 0;
1322 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1323 SDOperand LHSShift; // The shift.
1324 SDOperand LHSMask; // AND value if any.
1325 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1326 return 0; // Not part of a rotate.
1328 SDOperand RHSShift; // The shift.
1329 SDOperand RHSMask; // AND value if any.
1330 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1331 return 0; // Not part of a rotate.
1333 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1334 return 0; // Not shifting the same value.
1336 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1337 return 0; // Shifts must disagree.
1339 // Canonicalize shl to left side in a shl/srl pair.
1340 if (RHSShift.getOpcode() == ISD::SHL) {
1341 std::swap(LHS, RHS);
1342 std::swap(LHSShift, RHSShift);
1343 std::swap(LHSMask , RHSMask );
1346 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1348 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1349 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1350 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1351 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1352 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1353 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1354 if ((LShVal + RShVal) != OpSizeInBits)
1359 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1360 LHSShift.getOperand(1));
1362 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1363 RHSShift.getOperand(1));
1365 // If there is an AND of either shifted operand, apply it to the result.
1366 if (LHSMask.Val || RHSMask.Val) {
1367 uint64_t Mask = MVT::getIntVTBitMask(VT);
1370 uint64_t RHSBits = (1ULL << LShVal)-1;
1371 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1374 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1375 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1378 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1384 // If there is a mask here, and we have a variable shift, we can't be sure
1385 // that we're masking out the right stuff.
1386 if (LHSMask.Val || RHSMask.Val)
1389 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1390 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1391 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1392 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1393 if (ConstantSDNode *SUBC =
1394 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1395 if (SUBC->getValue() == OpSizeInBits)
1397 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1398 LHSShift.getOperand(1)).Val;
1400 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1401 LHSShift.getOperand(1)).Val;
1405 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1406 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1407 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1408 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1409 if (ConstantSDNode *SUBC =
1410 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1411 if (SUBC->getValue() == OpSizeInBits)
1413 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1414 LHSShift.getOperand(1)).Val;
1416 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1417 RHSShift.getOperand(1)).Val;
1425 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1426 SDOperand N0 = N->getOperand(0);
1427 SDOperand N1 = N->getOperand(1);
1428 SDOperand LHS, RHS, CC;
1429 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1430 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1431 MVT::ValueType VT = N0.getValueType();
1433 // fold (xor c1, c2) -> c1^c2
1435 return DAG.getNode(ISD::XOR, VT, N0, N1);
1436 // canonicalize constant to RHS
1438 return DAG.getNode(ISD::XOR, VT, N1, N0);
1439 // fold (xor x, 0) -> x
1440 if (N1C && N1C->isNullValue())
1443 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1446 // fold !(x cc y) -> (x !cc y)
1447 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1448 bool isInt = MVT::isInteger(LHS.getValueType());
1449 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1451 if (N0.getOpcode() == ISD::SETCC)
1452 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1453 if (N0.getOpcode() == ISD::SELECT_CC)
1454 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1455 assert(0 && "Unhandled SetCC Equivalent!");
1458 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1459 if (N1C && N1C->getValue() == 1 &&
1460 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1461 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1462 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1463 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1464 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1465 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1466 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1467 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1470 // fold !(x or y) -> (!x and !y) iff x or y are constants
1471 if (N1C && N1C->isAllOnesValue() &&
1472 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1473 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1474 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1475 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1476 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1477 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1478 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1479 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1482 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1483 if (N1C && N0.getOpcode() == ISD::XOR) {
1484 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1485 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1487 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1488 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1490 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1491 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1493 // fold (xor x, x) -> 0
1495 if (!MVT::isVector(VT)) {
1496 return DAG.getConstant(0, VT);
1497 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1498 // Produce a vector of zeros.
1499 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1500 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1501 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1505 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1506 if (N0.getOpcode() == N1.getOpcode()) {
1507 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1508 if (Tmp.Val) return Tmp;
1511 // Simplify the expression using non-local knowledge.
1512 if (!MVT::isVector(VT) &&
1513 SimplifyDemandedBits(SDOperand(N, 0)))
1514 return SDOperand(N, 0);
1519 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1520 SDOperand N0 = N->getOperand(0);
1521 SDOperand N1 = N->getOperand(1);
1522 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1523 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1524 MVT::ValueType VT = N0.getValueType();
1525 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1527 // fold (shl c1, c2) -> c1<<c2
1529 return DAG.getNode(ISD::SHL, VT, N0, N1);
1530 // fold (shl 0, x) -> 0
1531 if (N0C && N0C->isNullValue())
1533 // fold (shl x, c >= size(x)) -> undef
1534 if (N1C && N1C->getValue() >= OpSizeInBits)
1535 return DAG.getNode(ISD::UNDEF, VT);
1536 // fold (shl x, 0) -> x
1537 if (N1C && N1C->isNullValue())
1539 // if (shl x, c) is known to be zero, return 0
1540 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1541 return DAG.getConstant(0, VT);
1542 if (SimplifyDemandedBits(SDOperand(N, 0)))
1543 return SDOperand(N, 0);
1544 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1545 if (N1C && N0.getOpcode() == ISD::SHL &&
1546 N0.getOperand(1).getOpcode() == ISD::Constant) {
1547 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1548 uint64_t c2 = N1C->getValue();
1549 if (c1 + c2 > OpSizeInBits)
1550 return DAG.getConstant(0, VT);
1551 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1552 DAG.getConstant(c1 + c2, N1.getValueType()));
1554 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1555 // (srl (and x, -1 << c1), c1-c2)
1556 if (N1C && N0.getOpcode() == ISD::SRL &&
1557 N0.getOperand(1).getOpcode() == ISD::Constant) {
1558 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1559 uint64_t c2 = N1C->getValue();
1560 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1561 DAG.getConstant(~0ULL << c1, VT));
1563 return DAG.getNode(ISD::SHL, VT, Mask,
1564 DAG.getConstant(c2-c1, N1.getValueType()));
1566 return DAG.getNode(ISD::SRL, VT, Mask,
1567 DAG.getConstant(c1-c2, N1.getValueType()));
1569 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1570 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1571 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1572 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1573 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1574 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1575 isa<ConstantSDNode>(N0.getOperand(1))) {
1576 return DAG.getNode(ISD::ADD, VT,
1577 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1578 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1583 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1584 SDOperand N0 = N->getOperand(0);
1585 SDOperand N1 = N->getOperand(1);
1586 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1587 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1588 MVT::ValueType VT = N0.getValueType();
1590 // fold (sra c1, c2) -> c1>>c2
1592 return DAG.getNode(ISD::SRA, VT, N0, N1);
1593 // fold (sra 0, x) -> 0
1594 if (N0C && N0C->isNullValue())
1596 // fold (sra -1, x) -> -1
1597 if (N0C && N0C->isAllOnesValue())
1599 // fold (sra x, c >= size(x)) -> undef
1600 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1601 return DAG.getNode(ISD::UNDEF, VT);
1602 // fold (sra x, 0) -> x
1603 if (N1C && N1C->isNullValue())
1605 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1607 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1608 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1611 default: EVT = MVT::Other; break;
1612 case 1: EVT = MVT::i1; break;
1613 case 8: EVT = MVT::i8; break;
1614 case 16: EVT = MVT::i16; break;
1615 case 32: EVT = MVT::i32; break;
1617 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1618 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1619 DAG.getValueType(EVT));
1622 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1623 if (N1C && N0.getOpcode() == ISD::SRA) {
1624 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1625 unsigned Sum = N1C->getValue() + C1->getValue();
1626 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1627 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1628 DAG.getConstant(Sum, N1C->getValueType(0)));
1632 // Simplify, based on bits shifted out of the LHS.
1633 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1634 return SDOperand(N, 0);
1637 // If the sign bit is known to be zero, switch this to a SRL.
1638 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1639 return DAG.getNode(ISD::SRL, VT, N0, N1);
1643 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1644 SDOperand N0 = N->getOperand(0);
1645 SDOperand N1 = N->getOperand(1);
1646 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1647 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1648 MVT::ValueType VT = N0.getValueType();
1649 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1651 // fold (srl c1, c2) -> c1 >>u c2
1653 return DAG.getNode(ISD::SRL, VT, N0, N1);
1654 // fold (srl 0, x) -> 0
1655 if (N0C && N0C->isNullValue())
1657 // fold (srl x, c >= size(x)) -> undef
1658 if (N1C && N1C->getValue() >= OpSizeInBits)
1659 return DAG.getNode(ISD::UNDEF, VT);
1660 // fold (srl x, 0) -> x
1661 if (N1C && N1C->isNullValue())
1663 // if (srl x, c) is known to be zero, return 0
1664 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1665 return DAG.getConstant(0, VT);
1666 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1667 if (N1C && N0.getOpcode() == ISD::SRL &&
1668 N0.getOperand(1).getOpcode() == ISD::Constant) {
1669 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1670 uint64_t c2 = N1C->getValue();
1671 if (c1 + c2 > OpSizeInBits)
1672 return DAG.getConstant(0, VT);
1673 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1674 DAG.getConstant(c1 + c2, N1.getValueType()));
1677 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1678 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1679 // Shifting in all undef bits?
1680 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1681 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1682 return DAG.getNode(ISD::UNDEF, VT);
1684 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1685 AddToWorkList(SmallShift.Val);
1686 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1689 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
1690 // bit, which is unmodified by sra.
1691 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
1692 if (N0.getOpcode() == ISD::SRA)
1693 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
1696 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1697 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1698 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1699 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1700 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1702 // If any of the input bits are KnownOne, then the input couldn't be all
1703 // zeros, thus the result of the srl will always be zero.
1704 if (KnownOne) return DAG.getConstant(0, VT);
1706 // If all of the bits input the to ctlz node are known to be zero, then
1707 // the result of the ctlz is "32" and the result of the shift is one.
1708 uint64_t UnknownBits = ~KnownZero & Mask;
1709 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1711 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1712 if ((UnknownBits & (UnknownBits-1)) == 0) {
1713 // Okay, we know that only that the single bit specified by UnknownBits
1714 // could be set on input to the CTLZ node. If this bit is set, the SRL
1715 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1716 // to an SRL,XOR pair, which is likely to simplify more.
1717 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1718 SDOperand Op = N0.getOperand(0);
1720 Op = DAG.getNode(ISD::SRL, VT, Op,
1721 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1722 AddToWorkList(Op.Val);
1724 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1731 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1732 SDOperand N0 = N->getOperand(0);
1733 MVT::ValueType VT = N->getValueType(0);
1735 // fold (ctlz c1) -> c2
1736 if (isa<ConstantSDNode>(N0))
1737 return DAG.getNode(ISD::CTLZ, VT, N0);
1741 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1742 SDOperand N0 = N->getOperand(0);
1743 MVT::ValueType VT = N->getValueType(0);
1745 // fold (cttz c1) -> c2
1746 if (isa<ConstantSDNode>(N0))
1747 return DAG.getNode(ISD::CTTZ, VT, N0);
1751 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1752 SDOperand N0 = N->getOperand(0);
1753 MVT::ValueType VT = N->getValueType(0);
1755 // fold (ctpop c1) -> c2
1756 if (isa<ConstantSDNode>(N0))
1757 return DAG.getNode(ISD::CTPOP, VT, N0);
1761 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1762 SDOperand N0 = N->getOperand(0);
1763 SDOperand N1 = N->getOperand(1);
1764 SDOperand N2 = N->getOperand(2);
1765 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1766 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1767 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1768 MVT::ValueType VT = N->getValueType(0);
1770 // fold select C, X, X -> X
1773 // fold select true, X, Y -> X
1774 if (N0C && !N0C->isNullValue())
1776 // fold select false, X, Y -> Y
1777 if (N0C && N0C->isNullValue())
1779 // fold select C, 1, X -> C | X
1780 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1781 return DAG.getNode(ISD::OR, VT, N0, N2);
1782 // fold select C, 0, X -> ~C & X
1783 // FIXME: this should check for C type == X type, not i1?
1784 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1785 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1786 AddToWorkList(XORNode.Val);
1787 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1789 // fold select C, X, 1 -> ~C | X
1790 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1791 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1792 AddToWorkList(XORNode.Val);
1793 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1795 // fold select C, X, 0 -> C & X
1796 // FIXME: this should check for C type == X type, not i1?
1797 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1798 return DAG.getNode(ISD::AND, VT, N0, N1);
1799 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1800 if (MVT::i1 == VT && N0 == N1)
1801 return DAG.getNode(ISD::OR, VT, N0, N2);
1802 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1803 if (MVT::i1 == VT && N0 == N2)
1804 return DAG.getNode(ISD::AND, VT, N0, N1);
1806 // If we can fold this based on the true/false value, do so.
1807 if (SimplifySelectOps(N, N1, N2))
1808 return SDOperand(N, 0); // Don't revisit N.
1810 // fold selects based on a setcc into other things, such as min/max/abs
1811 if (N0.getOpcode() == ISD::SETCC)
1813 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1814 // having to say they don't support SELECT_CC on every type the DAG knows
1815 // about, since there is no way to mark an opcode illegal at all value types
1816 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1817 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1818 N1, N2, N0.getOperand(2));
1820 return SimplifySelect(N0, N1, N2);
1824 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1825 SDOperand N0 = N->getOperand(0);
1826 SDOperand N1 = N->getOperand(1);
1827 SDOperand N2 = N->getOperand(2);
1828 SDOperand N3 = N->getOperand(3);
1829 SDOperand N4 = N->getOperand(4);
1830 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1831 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1832 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1833 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1835 // fold select_cc lhs, rhs, x, x, cc -> x
1839 // Determine if the condition we're dealing with is constant
1840 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1842 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1843 if (SCCC->getValue())
1844 return N2; // cond always true -> true val
1846 return N3; // cond always false -> false val
1849 // Fold to a simpler select_cc
1850 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1851 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1852 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1855 // If we can fold this based on the true/false value, do so.
1856 if (SimplifySelectOps(N, N2, N3))
1857 return SDOperand(N, 0); // Don't revisit N.
1859 // fold select_cc into other things, such as min/max/abs
1860 return SimplifySelectCC(N0, N1, N2, N3, CC);
1863 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1864 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1865 cast<CondCodeSDNode>(N->getOperand(2))->get());
1868 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1869 SDOperand N0 = N->getOperand(0);
1870 MVT::ValueType VT = N->getValueType(0);
1872 // fold (sext c1) -> c1
1873 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1874 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1876 // fold (sext (sext x)) -> (sext x)
1877 // fold (sext (aext x)) -> (sext x)
1878 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1879 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1881 // fold (sext (truncate x)) -> (sextinreg x).
1882 if (N0.getOpcode() == ISD::TRUNCATE &&
1883 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
1884 N0.getValueType()))) {
1885 SDOperand Op = N0.getOperand(0);
1886 if (Op.getValueType() < VT) {
1887 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1888 } else if (Op.getValueType() > VT) {
1889 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1891 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
1892 DAG.getValueType(N0.getValueType()));
1895 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1896 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1897 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
1898 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1899 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1900 LN0->getBasePtr(), LN0->getSrcValue(),
1901 LN0->getSrcValueOffset(),
1903 CombineTo(N, ExtLoad);
1904 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1905 ExtLoad.getValue(1));
1906 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1909 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1910 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1911 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1912 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1913 MVT::ValueType EVT = LN0->getLoadedVT();
1914 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1915 LN0->getBasePtr(), LN0->getSrcValue(),
1916 LN0->getSrcValueOffset(), EVT);
1917 CombineTo(N, ExtLoad);
1918 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1919 ExtLoad.getValue(1));
1920 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1926 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1927 SDOperand N0 = N->getOperand(0);
1928 MVT::ValueType VT = N->getValueType(0);
1930 // fold (zext c1) -> c1
1931 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1932 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1933 // fold (zext (zext x)) -> (zext x)
1934 // fold (zext (aext x)) -> (zext x)
1935 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1936 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1938 // fold (zext (truncate x)) -> (and x, mask)
1939 if (N0.getOpcode() == ISD::TRUNCATE &&
1940 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
1941 SDOperand Op = N0.getOperand(0);
1942 if (Op.getValueType() < VT) {
1943 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1944 } else if (Op.getValueType() > VT) {
1945 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1947 return DAG.getZeroExtendInReg(Op, N0.getValueType());
1950 // fold (zext (and (trunc x), cst)) -> (and x, cst).
1951 if (N0.getOpcode() == ISD::AND &&
1952 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1953 N0.getOperand(1).getOpcode() == ISD::Constant) {
1954 SDOperand X = N0.getOperand(0).getOperand(0);
1955 if (X.getValueType() < VT) {
1956 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1957 } else if (X.getValueType() > VT) {
1958 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1960 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1961 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
1964 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1965 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1966 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
1967 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1968 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1969 LN0->getBasePtr(), LN0->getSrcValue(),
1970 LN0->getSrcValueOffset(),
1972 CombineTo(N, ExtLoad);
1973 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1974 ExtLoad.getValue(1));
1975 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1978 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1979 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1980 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1981 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1982 MVT::ValueType EVT = LN0->getLoadedVT();
1983 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1984 LN0->getBasePtr(), LN0->getSrcValue(),
1985 LN0->getSrcValueOffset(), EVT);
1986 CombineTo(N, ExtLoad);
1987 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1988 ExtLoad.getValue(1));
1989 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1994 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
1995 SDOperand N0 = N->getOperand(0);
1996 MVT::ValueType VT = N->getValueType(0);
1998 // fold (aext c1) -> c1
1999 if (isa<ConstantSDNode>(N0))
2000 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2001 // fold (aext (aext x)) -> (aext x)
2002 // fold (aext (zext x)) -> (zext x)
2003 // fold (aext (sext x)) -> (sext x)
2004 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2005 N0.getOpcode() == ISD::ZERO_EXTEND ||
2006 N0.getOpcode() == ISD::SIGN_EXTEND)
2007 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2009 // fold (aext (truncate x))
2010 if (N0.getOpcode() == ISD::TRUNCATE) {
2011 SDOperand TruncOp = N0.getOperand(0);
2012 if (TruncOp.getValueType() == VT)
2013 return TruncOp; // x iff x size == zext size.
2014 if (TruncOp.getValueType() > VT)
2015 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2016 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2019 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2020 if (N0.getOpcode() == ISD::AND &&
2021 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2022 N0.getOperand(1).getOpcode() == ISD::Constant) {
2023 SDOperand X = N0.getOperand(0).getOperand(0);
2024 if (X.getValueType() < VT) {
2025 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2026 } else if (X.getValueType() > VT) {
2027 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2029 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2030 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2033 // fold (aext (load x)) -> (aext (truncate (extload x)))
2034 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2035 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2036 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2037 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2038 LN0->getBasePtr(), LN0->getSrcValue(),
2039 LN0->getSrcValueOffset(),
2041 CombineTo(N, ExtLoad);
2042 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2043 ExtLoad.getValue(1));
2044 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2047 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2048 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2049 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2050 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
2052 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2053 MVT::ValueType EVT = LN0->getLoadedVT();
2054 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2055 LN0->getChain(), LN0->getBasePtr(),
2057 LN0->getSrcValueOffset(), EVT);
2058 CombineTo(N, ExtLoad);
2059 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2060 ExtLoad.getValue(1));
2061 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2067 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2068 SDOperand N0 = N->getOperand(0);
2069 SDOperand N1 = N->getOperand(1);
2070 MVT::ValueType VT = N->getValueType(0);
2071 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2072 unsigned EVTBits = MVT::getSizeInBits(EVT);
2074 // fold (sext_in_reg c1) -> c1
2075 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2076 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2078 // If the input is already sign extended, just drop the extension.
2079 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2082 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2083 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2084 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2085 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2088 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2089 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2090 return DAG.getZeroExtendInReg(N0, EVT);
2092 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2093 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2094 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2095 if (N0.getOpcode() == ISD::SRL) {
2096 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2097 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2098 // We can turn this into an SRA iff the input to the SRL is already sign
2100 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2101 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2102 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2106 // fold (sext_inreg (extload x)) -> (sextload x)
2107 if (ISD::isEXTLoad(N0.Val) &&
2108 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2109 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2110 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2111 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2112 LN0->getBasePtr(), LN0->getSrcValue(),
2113 LN0->getSrcValueOffset(), EVT);
2114 CombineTo(N, ExtLoad);
2115 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2116 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2118 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2119 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
2120 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2121 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2122 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2123 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2124 LN0->getBasePtr(), LN0->getSrcValue(),
2125 LN0->getSrcValueOffset(), EVT);
2126 CombineTo(N, ExtLoad);
2127 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2128 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2133 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2134 SDOperand N0 = N->getOperand(0);
2135 MVT::ValueType VT = N->getValueType(0);
2138 if (N0.getValueType() == N->getValueType(0))
2140 // fold (truncate c1) -> c1
2141 if (isa<ConstantSDNode>(N0))
2142 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2143 // fold (truncate (truncate x)) -> (truncate x)
2144 if (N0.getOpcode() == ISD::TRUNCATE)
2145 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2146 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2147 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2148 N0.getOpcode() == ISD::ANY_EXTEND) {
2149 if (N0.getValueType() < VT)
2150 // if the source is smaller than the dest, we still need an extend
2151 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2152 else if (N0.getValueType() > VT)
2153 // if the source is larger than the dest, than we just need the truncate
2154 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2156 // if the source and dest are the same type, we can drop both the extend
2158 return N0.getOperand(0);
2160 // fold (truncate (load x)) -> (smaller load x)
2161 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2162 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2163 "Cannot truncate to larger type!");
2164 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2165 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2166 // For big endian targets, we need to add an offset to the pointer to load
2167 // the correct bytes. For little endian systems, we merely need to read
2168 // fewer bytes from the same pointer.
2170 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2171 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() :
2172 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2173 DAG.getConstant(PtrOff, PtrType));
2174 AddToWorkList(NewPtr.Val);
2175 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr,
2176 LN0->getSrcValue(), LN0->getSrcValueOffset());
2178 CombineTo(N0.Val, Load, Load.getValue(1));
2179 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2184 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2185 SDOperand N0 = N->getOperand(0);
2186 MVT::ValueType VT = N->getValueType(0);
2188 // If the input is a constant, let getNode() fold it.
2189 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2190 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2191 if (Res.Val != N) return Res;
2194 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2195 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2197 // fold (conv (load x)) -> (load (conv*)x)
2198 // FIXME: These xforms need to know that the resultant load doesn't need a
2199 // higher alignment than the original!
2200 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2201 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2202 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2203 LN0->getSrcValue(), LN0->getSrcValueOffset());
2205 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2213 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2214 SDOperand N0 = N->getOperand(0);
2215 MVT::ValueType VT = N->getValueType(0);
2217 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2218 // First check to see if this is all constant.
2219 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2220 VT == MVT::Vector) {
2221 bool isSimple = true;
2222 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2223 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2224 N0.getOperand(i).getOpcode() != ISD::Constant &&
2225 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2230 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2231 if (isSimple && !MVT::isVector(DestEltVT)) {
2232 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2239 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2240 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2241 /// destination element value type.
2242 SDOperand DAGCombiner::
2243 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2244 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2246 // If this is already the right type, we're done.
2247 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2249 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2250 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2252 // If this is a conversion of N elements of one type to N elements of another
2253 // type, convert each element. This handles FP<->INT cases.
2254 if (SrcBitSize == DstBitSize) {
2255 SmallVector<SDOperand, 8> Ops;
2256 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2257 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2258 AddToWorkList(Ops.back().Val);
2260 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2261 Ops.push_back(DAG.getValueType(DstEltVT));
2262 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2265 // Otherwise, we're growing or shrinking the elements. To avoid having to
2266 // handle annoying details of growing/shrinking FP values, we convert them to
2268 if (MVT::isFloatingPoint(SrcEltVT)) {
2269 // Convert the input float vector to a int vector where the elements are the
2271 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2272 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2273 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2277 // Now we know the input is an integer vector. If the output is a FP type,
2278 // convert to integer first, then to FP of the right size.
2279 if (MVT::isFloatingPoint(DstEltVT)) {
2280 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2281 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2282 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2284 // Next, convert to FP elements of the same size.
2285 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2288 // Okay, we know the src/dst types are both integers of differing types.
2289 // Handling growing first.
2290 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2291 if (SrcBitSize < DstBitSize) {
2292 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2294 SmallVector<SDOperand, 8> Ops;
2295 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2296 i += NumInputsPerOutput) {
2297 bool isLE = TLI.isLittleEndian();
2298 uint64_t NewBits = 0;
2299 bool EltIsUndef = true;
2300 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2301 // Shift the previously computed bits over.
2302 NewBits <<= SrcBitSize;
2303 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2304 if (Op.getOpcode() == ISD::UNDEF) continue;
2307 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2311 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2313 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2316 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2317 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2318 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2321 // Finally, this must be the case where we are shrinking elements: each input
2322 // turns into multiple outputs.
2323 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2324 SmallVector<SDOperand, 8> Ops;
2325 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2326 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2327 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2328 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2331 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2333 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2334 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2335 OpVal >>= DstBitSize;
2336 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2339 // For big endian targets, swap the order of the pieces of each element.
2340 if (!TLI.isLittleEndian())
2341 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2343 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2344 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2345 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2350 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2351 SDOperand N0 = N->getOperand(0);
2352 SDOperand N1 = N->getOperand(1);
2353 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2354 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2355 MVT::ValueType VT = N->getValueType(0);
2357 // fold (fadd c1, c2) -> c1+c2
2359 return DAG.getNode(ISD::FADD, VT, N0, N1);
2360 // canonicalize constant to RHS
2361 if (N0CFP && !N1CFP)
2362 return DAG.getNode(ISD::FADD, VT, N1, N0);
2363 // fold (A + (-B)) -> A-B
2364 if (N1.getOpcode() == ISD::FNEG)
2365 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2366 // fold ((-A) + B) -> B-A
2367 if (N0.getOpcode() == ISD::FNEG)
2368 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2372 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2373 SDOperand N0 = N->getOperand(0);
2374 SDOperand N1 = N->getOperand(1);
2375 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2376 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2377 MVT::ValueType VT = N->getValueType(0);
2379 // fold (fsub c1, c2) -> c1-c2
2381 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2382 // fold (A-(-B)) -> A+B
2383 if (N1.getOpcode() == ISD::FNEG)
2384 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2388 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2389 SDOperand N0 = N->getOperand(0);
2390 SDOperand N1 = N->getOperand(1);
2391 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2392 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2393 MVT::ValueType VT = N->getValueType(0);
2395 // fold (fmul c1, c2) -> c1*c2
2397 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2398 // canonicalize constant to RHS
2399 if (N0CFP && !N1CFP)
2400 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2401 // fold (fmul X, 2.0) -> (fadd X, X)
2402 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2403 return DAG.getNode(ISD::FADD, VT, N0, N0);
2407 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2408 SDOperand N0 = N->getOperand(0);
2409 SDOperand N1 = N->getOperand(1);
2410 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2411 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2412 MVT::ValueType VT = N->getValueType(0);
2414 // fold (fdiv c1, c2) -> c1/c2
2416 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2420 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2421 SDOperand N0 = N->getOperand(0);
2422 SDOperand N1 = N->getOperand(1);
2423 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2424 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2425 MVT::ValueType VT = N->getValueType(0);
2427 // fold (frem c1, c2) -> fmod(c1,c2)
2429 return DAG.getNode(ISD::FREM, VT, N0, N1);
2433 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2434 SDOperand N0 = N->getOperand(0);
2435 SDOperand N1 = N->getOperand(1);
2436 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2437 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2438 MVT::ValueType VT = N->getValueType(0);
2440 if (N0CFP && N1CFP) // Constant fold
2441 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2444 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2445 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2450 u.d = N1CFP->getValue();
2452 return DAG.getNode(ISD::FABS, VT, N0);
2454 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2457 // copysign(fabs(x), y) -> copysign(x, y)
2458 // copysign(fneg(x), y) -> copysign(x, y)
2459 // copysign(copysign(x,z), y) -> copysign(x, y)
2460 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2461 N0.getOpcode() == ISD::FCOPYSIGN)
2462 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2464 // copysign(x, abs(y)) -> abs(x)
2465 if (N1.getOpcode() == ISD::FABS)
2466 return DAG.getNode(ISD::FABS, VT, N0);
2468 // copysign(x, copysign(y,z)) -> copysign(x, z)
2469 if (N1.getOpcode() == ISD::FCOPYSIGN)
2470 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2472 // copysign(x, fp_extend(y)) -> copysign(x, y)
2473 // copysign(x, fp_round(y)) -> copysign(x, y)
2474 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2475 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2482 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2483 SDOperand N0 = N->getOperand(0);
2484 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2485 MVT::ValueType VT = N->getValueType(0);
2487 // fold (sint_to_fp c1) -> c1fp
2489 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2493 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2494 SDOperand N0 = N->getOperand(0);
2495 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2496 MVT::ValueType VT = N->getValueType(0);
2498 // fold (uint_to_fp c1) -> c1fp
2500 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2504 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2505 SDOperand N0 = N->getOperand(0);
2506 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2507 MVT::ValueType VT = N->getValueType(0);
2509 // fold (fp_to_sint c1fp) -> c1
2511 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2515 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2516 SDOperand N0 = N->getOperand(0);
2517 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2518 MVT::ValueType VT = N->getValueType(0);
2520 // fold (fp_to_uint c1fp) -> c1
2522 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2526 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2527 SDOperand N0 = N->getOperand(0);
2528 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2529 MVT::ValueType VT = N->getValueType(0);
2531 // fold (fp_round c1fp) -> c1fp
2533 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2535 // fold (fp_round (fp_extend x)) -> x
2536 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2537 return N0.getOperand(0);
2539 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2540 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2541 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2542 AddToWorkList(Tmp.Val);
2543 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2549 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2550 SDOperand N0 = N->getOperand(0);
2551 MVT::ValueType VT = N->getValueType(0);
2552 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2553 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2555 // fold (fp_round_inreg c1fp) -> c1fp
2557 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2558 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2563 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2564 SDOperand N0 = N->getOperand(0);
2565 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2566 MVT::ValueType VT = N->getValueType(0);
2568 // fold (fp_extend c1fp) -> c1fp
2570 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2572 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2573 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2574 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2575 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2576 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2577 LN0->getBasePtr(), LN0->getSrcValue(),
2578 LN0->getSrcValueOffset(),
2580 CombineTo(N, ExtLoad);
2581 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2582 ExtLoad.getValue(1));
2583 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2590 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2591 SDOperand N0 = N->getOperand(0);
2592 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2593 MVT::ValueType VT = N->getValueType(0);
2595 // fold (fneg c1) -> -c1
2597 return DAG.getNode(ISD::FNEG, VT, N0);
2598 // fold (fneg (sub x, y)) -> (sub y, x)
2599 if (N0.getOpcode() == ISD::SUB)
2600 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2601 // fold (fneg (fneg x)) -> x
2602 if (N0.getOpcode() == ISD::FNEG)
2603 return N0.getOperand(0);
2607 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2608 SDOperand N0 = N->getOperand(0);
2609 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2610 MVT::ValueType VT = N->getValueType(0);
2612 // fold (fabs c1) -> fabs(c1)
2614 return DAG.getNode(ISD::FABS, VT, N0);
2615 // fold (fabs (fabs x)) -> (fabs x)
2616 if (N0.getOpcode() == ISD::FABS)
2617 return N->getOperand(0);
2618 // fold (fabs (fneg x)) -> (fabs x)
2619 // fold (fabs (fcopysign x, y)) -> (fabs x)
2620 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2621 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2626 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2627 SDOperand Chain = N->getOperand(0);
2628 SDOperand N1 = N->getOperand(1);
2629 SDOperand N2 = N->getOperand(2);
2630 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2632 // never taken branch, fold to chain
2633 if (N1C && N1C->isNullValue())
2635 // unconditional branch
2636 if (N1C && N1C->getValue() == 1)
2637 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2638 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2640 if (N1.getOpcode() == ISD::SETCC &&
2641 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2642 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2643 N1.getOperand(0), N1.getOperand(1), N2);
2648 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2650 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2651 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2652 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2654 // Use SimplifySetCC to simplify SETCC's.
2655 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2656 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2658 // fold br_cc true, dest -> br dest (unconditional branch)
2659 if (SCCC && SCCC->getValue())
2660 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2662 // fold br_cc false, dest -> unconditional fall through
2663 if (SCCC && SCCC->isNullValue())
2664 return N->getOperand(0);
2665 // fold to a simpler setcc
2666 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2667 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2668 Simp.getOperand(2), Simp.getOperand(0),
2669 Simp.getOperand(1), N->getOperand(4));
2673 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2674 LoadSDNode *LD = cast<LoadSDNode>(N);
2675 SDOperand Chain = LD->getChain();
2676 SDOperand Ptr = LD->getBasePtr();
2678 // If there are no uses of the loaded value, change uses of the chain value
2679 // into uses of the chain input (i.e. delete the dead load).
2680 if (N->hasNUsesOfValue(0, 0))
2681 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2683 // If this load is directly stored, replace the load value with the stored
2685 // TODO: Handle store large -> read small portion.
2686 // TODO: Handle TRUNCSTORE/LOADEXT
2687 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2688 if (ISD::isNON_TRUNCStore(Chain.Val)) {
2689 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
2690 if (PrevST->getBasePtr() == Ptr &&
2691 PrevST->getValue().getValueType() == N->getValueType(0))
2692 return CombineTo(N, Chain.getOperand(1), Chain);
2697 // Walk up chain skipping non-aliasing memory nodes.
2698 SDOperand BetterChain = FindBetterChain(N, Chain);
2700 // If there is a better chain.
2701 if (Chain != BetterChain) {
2704 // Replace the chain to void dependency.
2705 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2706 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
2707 LD->getSrcValue(), LD->getSrcValueOffset());
2709 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
2710 LD->getValueType(0),
2711 BetterChain, Ptr, LD->getSrcValue(),
2712 LD->getSrcValueOffset(),
2716 // Create token factor to keep old chain connected.
2717 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
2718 Chain, ReplLoad.getValue(1));
2720 // Replace uses with load result and token factor.
2721 return CombineTo(N, ReplLoad.getValue(0), Token);
2728 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2729 StoreSDNode *ST = cast<StoreSDNode>(N);
2730 SDOperand Chain = ST->getChain();
2731 SDOperand Value = ST->getValue();
2732 SDOperand Ptr = ST->getBasePtr();
2734 // FIXME - Switch over after StoreSDNode comes online.
2735 if (ST->isTruncatingStore()) {
2737 // Walk up chain skipping non-aliasing memory nodes.
2738 SDOperand BetterChain = FindBetterChain(N, Chain);
2740 // If there is a better chain.
2741 if (Chain != BetterChain) {
2742 // Replace the chain to avoid dependency.
2743 SDOperand ReplTStore =
2744 DAG.getTruncStore(BetterChain, Value, Ptr, ST->getSrcValue(),
2745 ST->getSrcValueOffset(), ST->getStoredVT());
2747 // Create token to keep both nodes around.
2748 return DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplTStore);
2755 // If this is a store that kills a previous store, remove the previous store.
2756 if (ISD::isNON_TRUNCStore(Chain.Val)) {
2757 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
2758 if (PrevST->getBasePtr() == Ptr &&
2759 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2760 // Make sure that these stores are the same value type:
2761 // FIXME: we really care that the second store is >= size of the first.
2762 Value.getValueType() == PrevST->getValue().getValueType()) {
2763 // Create a new store of Value that replaces both stores.
2764 if (PrevST->getValue() == Value) // Same value multiply stored.
2766 SDOperand NewStore = DAG.getStore(PrevST->getChain(), Value, Ptr,
2767 ST->getSrcValue(), ST->getSrcValueOffset());
2768 CombineTo(N, NewStore); // Nuke this store.
2769 CombineTo(Chain.Val, NewStore); // Nuke the previous store.
2770 return SDOperand(N, 0);
2774 // If this is a store of a bit convert, store the input value.
2775 // FIXME: This needs to know that the resultant store does not need a
2776 // higher alignment than the original.
2777 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
2778 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
2779 ST->getSrcValueOffset());
2783 // If the store ptr is a frame index and the frame index has a use of one
2784 // and this is a return block, then the store is redundant.
2785 if (Ptr.hasOneUse() && isa<FrameIndexSDNode>(Ptr) &&
2786 DAG.getRoot().getOpcode() == ISD::RET) {
2790 // Walk up chain skipping non-aliasing memory nodes.
2791 SDOperand BetterChain = FindBetterChain(N, Chain);
2793 // If there is a better chain.
2794 if (Chain != BetterChain) {
2795 // Replace the chain to avoid dependency.
2796 SDOperand ReplStore = DAG.getStore(BetterChain, Value, Ptr,
2797 ST->getSrcValue(), ST->getSrcValueOffset());
2798 // Create token to keep both nodes around.
2799 return DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
2806 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
2807 SDOperand InVec = N->getOperand(0);
2808 SDOperand InVal = N->getOperand(1);
2809 SDOperand EltNo = N->getOperand(2);
2811 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
2812 // vector with the inserted element.
2813 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2814 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2815 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2816 if (Elt < Ops.size())
2818 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
2819 &Ops[0], Ops.size());
2825 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
2826 SDOperand InVec = N->getOperand(0);
2827 SDOperand InVal = N->getOperand(1);
2828 SDOperand EltNo = N->getOperand(2);
2829 SDOperand NumElts = N->getOperand(3);
2830 SDOperand EltType = N->getOperand(4);
2832 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
2833 // vector with the inserted element.
2834 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2835 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2836 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2837 if (Elt < Ops.size()-2)
2839 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
2840 &Ops[0], Ops.size());
2846 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
2847 unsigned NumInScalars = N->getNumOperands()-2;
2848 SDOperand NumElts = N->getOperand(NumInScalars);
2849 SDOperand EltType = N->getOperand(NumInScalars+1);
2851 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
2852 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
2853 // two distinct vectors, turn this into a shuffle node.
2854 SDOperand VecIn1, VecIn2;
2855 for (unsigned i = 0; i != NumInScalars; ++i) {
2856 // Ignore undef inputs.
2857 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2859 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
2860 // constant index, bail out.
2861 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
2862 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
2863 VecIn1 = VecIn2 = SDOperand(0, 0);
2867 // If the input vector type disagrees with the result of the vbuild_vector,
2868 // we can't make a shuffle.
2869 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
2870 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
2871 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
2872 VecIn1 = VecIn2 = SDOperand(0, 0);
2876 // Otherwise, remember this. We allow up to two distinct input vectors.
2877 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
2880 if (VecIn1.Val == 0) {
2881 VecIn1 = ExtractedFromVec;
2882 } else if (VecIn2.Val == 0) {
2883 VecIn2 = ExtractedFromVec;
2886 VecIn1 = VecIn2 = SDOperand(0, 0);
2891 // If everything is good, we can make a shuffle operation.
2893 SmallVector<SDOperand, 8> BuildVecIndices;
2894 for (unsigned i = 0; i != NumInScalars; ++i) {
2895 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
2896 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2900 SDOperand Extract = N->getOperand(i);
2902 // If extracting from the first vector, just use the index directly.
2903 if (Extract.getOperand(0) == VecIn1) {
2904 BuildVecIndices.push_back(Extract.getOperand(1));
2908 // Otherwise, use InIdx + VecSize
2909 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
2910 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
2913 // Add count and size info.
2914 BuildVecIndices.push_back(NumElts);
2915 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
2917 // Return the new VVECTOR_SHUFFLE node.
2923 // Use an undef vbuild_vector as input for the second operand.
2924 std::vector<SDOperand> UnOps(NumInScalars,
2925 DAG.getNode(ISD::UNDEF,
2926 cast<VTSDNode>(EltType)->getVT()));
2927 UnOps.push_back(NumElts);
2928 UnOps.push_back(EltType);
2929 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2930 &UnOps[0], UnOps.size());
2931 AddToWorkList(Ops[1].Val);
2933 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
2934 &BuildVecIndices[0], BuildVecIndices.size());
2937 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
2943 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
2944 SDOperand ShufMask = N->getOperand(2);
2945 unsigned NumElts = ShufMask.getNumOperands();
2947 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2948 bool isIdentity = true;
2949 for (unsigned i = 0; i != NumElts; ++i) {
2950 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2951 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2956 if (isIdentity) return N->getOperand(0);
2958 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2960 for (unsigned i = 0; i != NumElts; ++i) {
2961 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2962 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2967 if (isIdentity) return N->getOperand(1);
2969 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
2971 bool isUnary = true;
2972 bool isSplat = true;
2974 unsigned BaseIdx = 0;
2975 for (unsigned i = 0; i != NumElts; ++i)
2976 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
2977 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
2978 int V = (Idx < NumElts) ? 0 : 1;
2992 SDOperand N0 = N->getOperand(0);
2993 SDOperand N1 = N->getOperand(1);
2994 // Normalize unary shuffle so the RHS is undef.
2995 if (isUnary && VecNum == 1)
2998 // If it is a splat, check if the argument vector is a build_vector with
2999 // all scalar elements the same.
3002 if (V->getOpcode() == ISD::BIT_CONVERT)
3003 V = V->getOperand(0).Val;
3004 if (V->getOpcode() == ISD::BUILD_VECTOR) {
3005 unsigned NumElems = V->getNumOperands()-2;
3006 if (NumElems > BaseIdx) {
3008 bool AllSame = true;
3009 for (unsigned i = 0; i != NumElems; ++i) {
3010 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3011 Base = V->getOperand(i);
3015 // Splat of <u, u, u, u>, return <u, u, u, u>
3018 for (unsigned i = 0; i != NumElems; ++i) {
3019 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3020 V->getOperand(i) != Base) {
3025 // Splat of <x, x, x, x>, return <x, x, x, x>
3032 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3034 if (isUnary || N0 == N1) {
3035 if (N0.getOpcode() == ISD::UNDEF)
3036 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
3037 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3039 SmallVector<SDOperand, 8> MappedOps;
3040 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
3041 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3042 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3043 MappedOps.push_back(ShufMask.getOperand(i));
3046 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3047 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3050 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
3051 &MappedOps[0], MappedOps.size());
3052 AddToWorkList(ShufMask.Val);
3053 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3055 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3062 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3063 SDOperand ShufMask = N->getOperand(2);
3064 unsigned NumElts = ShufMask.getNumOperands()-2;
3066 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3067 bool isIdentity = true;
3068 for (unsigned i = 0; i != NumElts; ++i) {
3069 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3070 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3075 if (isIdentity) return N->getOperand(0);
3077 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3079 for (unsigned i = 0; i != NumElts; ++i) {
3080 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3081 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3086 if (isIdentity) return N->getOperand(1);
3088 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3090 bool isUnary = true;
3091 bool isSplat = true;
3093 unsigned BaseIdx = 0;
3094 for (unsigned i = 0; i != NumElts; ++i)
3095 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3096 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3097 int V = (Idx < NumElts) ? 0 : 1;
3111 SDOperand N0 = N->getOperand(0);
3112 SDOperand N1 = N->getOperand(1);
3113 // Normalize unary shuffle so the RHS is undef.
3114 if (isUnary && VecNum == 1)
3117 // If it is a splat, check if the argument vector is a build_vector with
3118 // all scalar elements the same.
3121 if (V->getOpcode() == ISD::VBIT_CONVERT)
3122 V = V->getOperand(0).Val;
3123 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3124 unsigned NumElems = V->getNumOperands()-2;
3125 if (NumElems > BaseIdx) {
3127 bool AllSame = true;
3128 for (unsigned i = 0; i != NumElems; ++i) {
3129 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3130 Base = V->getOperand(i);
3134 // Splat of <u, u, u, u>, return <u, u, u, u>
3137 for (unsigned i = 0; i != NumElems; ++i) {
3138 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3139 V->getOperand(i) != Base) {
3144 // Splat of <x, x, x, x>, return <x, x, x, x>
3151 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3153 if (isUnary || N0 == N1) {
3154 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3156 SmallVector<SDOperand, 8> MappedOps;
3157 for (unsigned i = 0; i != NumElts; ++i) {
3158 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3159 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3160 MappedOps.push_back(ShufMask.getOperand(i));
3163 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3164 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3167 // Add the type/#elts values.
3168 MappedOps.push_back(ShufMask.getOperand(NumElts));
3169 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3171 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3172 &MappedOps[0], MappedOps.size());
3173 AddToWorkList(ShufMask.Val);
3175 // Build the undef vector.
3176 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3177 for (unsigned i = 0; i != NumElts; ++i)
3178 MappedOps[i] = UDVal;
3179 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3180 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3181 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3182 &MappedOps[0], MappedOps.size());
3184 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3185 N0, UDVal, ShufMask,
3186 MappedOps[NumElts], MappedOps[NumElts+1]);
3192 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3193 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3194 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3195 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3196 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3197 SDOperand LHS = N->getOperand(0);
3198 SDOperand RHS = N->getOperand(1);
3199 if (N->getOpcode() == ISD::VAND) {
3200 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3201 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3202 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3203 RHS = RHS.getOperand(0);
3204 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3205 std::vector<SDOperand> IdxOps;
3206 unsigned NumOps = RHS.getNumOperands();
3207 unsigned NumElts = NumOps-2;
3208 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3209 for (unsigned i = 0; i != NumElts; ++i) {
3210 SDOperand Elt = RHS.getOperand(i);
3211 if (!isa<ConstantSDNode>(Elt))
3213 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3214 IdxOps.push_back(DAG.getConstant(i, EVT));
3215 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3216 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3221 // Let's see if the target supports this vector_shuffle.
3222 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3225 // Return the new VVECTOR_SHUFFLE node.
3226 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3227 SDOperand EVTNode = DAG.getValueType(EVT);
3228 std::vector<SDOperand> Ops;
3229 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3232 AddToWorkList(LHS.Val);
3233 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3234 ZeroOps.push_back(NumEltsNode);
3235 ZeroOps.push_back(EVTNode);
3236 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3237 &ZeroOps[0], ZeroOps.size()));
3238 IdxOps.push_back(NumEltsNode);
3239 IdxOps.push_back(EVTNode);
3240 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3241 &IdxOps[0], IdxOps.size()));
3242 Ops.push_back(NumEltsNode);
3243 Ops.push_back(EVTNode);
3244 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3245 &Ops[0], Ops.size());
3246 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3247 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3248 DstVecSize, DstVecEVT);
3256 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3257 /// the scalar operation of the vop if it is operating on an integer vector
3258 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3259 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3260 ISD::NodeType FPOp) {
3261 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3262 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3263 SDOperand LHS = N->getOperand(0);
3264 SDOperand RHS = N->getOperand(1);
3265 SDOperand Shuffle = XformToShuffleWithZero(N);
3266 if (Shuffle.Val) return Shuffle;
3268 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3270 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3271 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3272 SmallVector<SDOperand, 8> Ops;
3273 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3274 SDOperand LHSOp = LHS.getOperand(i);
3275 SDOperand RHSOp = RHS.getOperand(i);
3276 // If these two elements can't be folded, bail out.
3277 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3278 LHSOp.getOpcode() != ISD::Constant &&
3279 LHSOp.getOpcode() != ISD::ConstantFP) ||
3280 (RHSOp.getOpcode() != ISD::UNDEF &&
3281 RHSOp.getOpcode() != ISD::Constant &&
3282 RHSOp.getOpcode() != ISD::ConstantFP))
3284 // Can't fold divide by zero.
3285 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3286 if ((RHSOp.getOpcode() == ISD::Constant &&
3287 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3288 (RHSOp.getOpcode() == ISD::ConstantFP &&
3289 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3292 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3293 AddToWorkList(Ops.back().Val);
3294 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3295 Ops.back().getOpcode() == ISD::Constant ||
3296 Ops.back().getOpcode() == ISD::ConstantFP) &&
3297 "Scalar binop didn't fold!");
3300 if (Ops.size() == LHS.getNumOperands()-2) {
3301 Ops.push_back(*(LHS.Val->op_end()-2));
3302 Ops.push_back(*(LHS.Val->op_end()-1));
3303 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3310 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3311 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3313 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3314 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3315 // If we got a simplified select_cc node back from SimplifySelectCC, then
3316 // break it down into a new SETCC node, and a new SELECT node, and then return
3317 // the SELECT node, since we were called with a SELECT node.
3319 // Check to see if we got a select_cc back (to turn into setcc/select).
3320 // Otherwise, just return whatever node we got back, like fabs.
3321 if (SCC.getOpcode() == ISD::SELECT_CC) {
3322 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3323 SCC.getOperand(0), SCC.getOperand(1),
3325 AddToWorkList(SETCC.Val);
3326 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3327 SCC.getOperand(3), SETCC);
3334 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3335 /// are the two values being selected between, see if we can simplify the
3336 /// select. Callers of this should assume that TheSelect is deleted if this
3337 /// returns true. As such, they should return the appropriate thing (e.g. the
3338 /// node) back to the top-level of the DAG combiner loop to avoid it being
3341 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3344 // If this is a select from two identical things, try to pull the operation
3345 // through the select.
3346 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3347 // If this is a load and the token chain is identical, replace the select
3348 // of two loads with a load through a select of the address to load from.
3349 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3350 // constants have been dropped into the constant pool.
3351 if (LHS.getOpcode() == ISD::LOAD &&
3352 // Token chains must be identical.
3353 LHS.getOperand(0) == RHS.getOperand(0)) {
3354 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3355 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3357 // If this is an EXTLOAD, the VT's must match.
3358 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3359 // FIXME: this conflates two src values, discarding one. This is not
3360 // the right thing to do, but nothing uses srcvalues now. When they do,
3361 // turn SrcValue into a list of locations.
3363 if (TheSelect->getOpcode() == ISD::SELECT)
3364 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
3365 TheSelect->getOperand(0), LLD->getBasePtr(),
3368 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
3369 TheSelect->getOperand(0),
3370 TheSelect->getOperand(1),
3371 LLD->getBasePtr(), RLD->getBasePtr(),
3372 TheSelect->getOperand(4));
3375 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
3376 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
3377 Addr,LLD->getSrcValue(), LLD->getSrcValueOffset());
3379 Load = DAG.getExtLoad(LLD->getExtensionType(),
3380 TheSelect->getValueType(0),
3381 LLD->getChain(), Addr, LLD->getSrcValue(),
3382 LLD->getSrcValueOffset(),
3383 LLD->getLoadedVT());
3385 // Users of the select now use the result of the load.
3386 CombineTo(TheSelect, Load);
3388 // Users of the old loads now use the new load's chain. We know the
3389 // old-load value is dead now.
3390 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3391 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3400 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3401 SDOperand N2, SDOperand N3,
3404 MVT::ValueType VT = N2.getValueType();
3405 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3406 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3407 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3409 // Determine if the condition we're dealing with is constant
3410 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3411 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3413 // fold select_cc true, x, y -> x
3414 if (SCCC && SCCC->getValue())
3416 // fold select_cc false, x, y -> y
3417 if (SCCC && SCCC->getValue() == 0)
3420 // Check to see if we can simplify the select into an fabs node
3421 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3422 // Allow either -0.0 or 0.0
3423 if (CFP->getValue() == 0.0) {
3424 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3425 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3426 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3427 N2 == N3.getOperand(0))
3428 return DAG.getNode(ISD::FABS, VT, N0);
3430 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3431 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3432 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3433 N2.getOperand(0) == N3)
3434 return DAG.getNode(ISD::FABS, VT, N3);
3438 // Check to see if we can perform the "gzip trick", transforming
3439 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3440 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3441 MVT::isInteger(N0.getValueType()) &&
3442 MVT::isInteger(N2.getValueType()) &&
3443 (N1C->isNullValue() || // (a < 0) ? b : 0
3444 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3445 MVT::ValueType XType = N0.getValueType();
3446 MVT::ValueType AType = N2.getValueType();
3447 if (XType >= AType) {
3448 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3449 // single-bit constant.
3450 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3451 unsigned ShCtV = Log2_64(N2C->getValue());
3452 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3453 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3454 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3455 AddToWorkList(Shift.Val);
3456 if (XType > AType) {
3457 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3458 AddToWorkList(Shift.Val);
3460 return DAG.getNode(ISD::AND, AType, Shift, N2);
3462 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3463 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3464 TLI.getShiftAmountTy()));
3465 AddToWorkList(Shift.Val);
3466 if (XType > AType) {
3467 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3468 AddToWorkList(Shift.Val);
3470 return DAG.getNode(ISD::AND, AType, Shift, N2);
3474 // fold select C, 16, 0 -> shl C, 4
3475 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3476 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3477 // Get a SetCC of the condition
3478 // FIXME: Should probably make sure that setcc is legal if we ever have a
3479 // target where it isn't.
3480 SDOperand Temp, SCC;
3481 // cast from setcc result type to select result type
3482 if (AfterLegalize) {
3483 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3484 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3486 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3487 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3489 AddToWorkList(SCC.Val);
3490 AddToWorkList(Temp.Val);
3491 // shl setcc result by log2 n2c
3492 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3493 DAG.getConstant(Log2_64(N2C->getValue()),
3494 TLI.getShiftAmountTy()));
3497 // Check to see if this is the equivalent of setcc
3498 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3499 // otherwise, go ahead with the folds.
3500 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3501 MVT::ValueType XType = N0.getValueType();
3502 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3503 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3504 if (Res.getValueType() != VT)
3505 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3509 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3510 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3511 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3512 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3513 return DAG.getNode(ISD::SRL, XType, Ctlz,
3514 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3515 TLI.getShiftAmountTy()));
3517 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3518 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3519 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3521 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3522 DAG.getConstant(~0ULL, XType));
3523 return DAG.getNode(ISD::SRL, XType,
3524 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3525 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3526 TLI.getShiftAmountTy()));
3528 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3529 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3530 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3531 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3532 TLI.getShiftAmountTy()));
3533 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3537 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3538 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3539 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3540 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3541 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3542 MVT::ValueType XType = N0.getValueType();
3543 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3544 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3545 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3546 TLI.getShiftAmountTy()));
3547 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3548 AddToWorkList(Shift.Val);
3549 AddToWorkList(Add.Val);
3550 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3558 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3559 SDOperand N1, ISD::CondCode Cond,
3560 bool foldBooleans) {
3561 // These setcc operations always fold.
3565 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3567 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3570 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3571 uint64_t C1 = N1C->getValue();
3572 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
3573 uint64_t C0 = N0C->getValue();
3575 // Sign extend the operands if required
3576 if (ISD::isSignedIntSetCC(Cond)) {
3577 C0 = N0C->getSignExtended();
3578 C1 = N1C->getSignExtended();
3582 default: assert(0 && "Unknown integer setcc!");
3583 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3584 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3585 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
3586 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
3587 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
3588 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
3589 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
3590 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
3591 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
3592 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
3595 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3596 // equality comparison, then we're just comparing whether X itself is
3598 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
3599 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3600 N0.getOperand(1).getOpcode() == ISD::Constant) {
3601 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
3602 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3603 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
3604 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3605 // (srl (ctlz x), 5) == 0 -> X != 0
3606 // (srl (ctlz x), 5) != 1 -> X != 0
3609 // (srl (ctlz x), 5) != 0 -> X == 0
3610 // (srl (ctlz x), 5) == 1 -> X == 0
3613 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
3614 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
3619 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3620 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3621 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3623 // If the comparison constant has bits in the upper part, the
3624 // zero-extended value could never match.
3625 if (C1 & (~0ULL << InSize)) {
3626 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3630 case ISD::SETEQ: return DAG.getConstant(0, VT);
3633 case ISD::SETNE: return DAG.getConstant(1, VT);
3636 // True if the sign bit of C1 is set.
3637 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3640 // True if the sign bit of C1 isn't set.
3641 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3647 // Otherwise, we can perform the comparison with the low bits.
3655 return DAG.getSetCC(VT, N0.getOperand(0),
3656 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3659 break; // todo, be more careful with signed comparisons
3661 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3662 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3663 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3664 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3665 MVT::ValueType ExtDstTy = N0.getValueType();
3666 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3668 // If the extended part has any inconsistent bits, it cannot ever
3669 // compare equal. In other words, they have to be all ones or all
3672 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3673 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3674 return DAG.getConstant(Cond == ISD::SETNE, VT);
3677 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3678 if (Op0Ty == ExtSrcTy) {
3679 ZextOp = N0.getOperand(0);
3681 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3682 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3683 DAG.getConstant(Imm, Op0Ty));
3685 AddToWorkList(ZextOp.Val);
3686 // Otherwise, make this a use of a zext.
3687 return DAG.getSetCC(VT, ZextOp,
3688 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3691 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3692 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3693 (N0.getOpcode() == ISD::XOR ||
3694 (N0.getOpcode() == ISD::AND &&
3695 N0.getOperand(0).getOpcode() == ISD::XOR &&
3696 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3697 isa<ConstantSDNode>(N0.getOperand(1)) &&
3698 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3699 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
3700 // only do this if the top bits are known zero.
3701 if (TLI.MaskedValueIsZero(N1,
3702 MVT::getIntVTBitMask(N0.getValueType())-1)) {
3703 // Okay, get the un-inverted input value.
3705 if (N0.getOpcode() == ISD::XOR)
3706 Val = N0.getOperand(0);
3708 assert(N0.getOpcode() == ISD::AND &&
3709 N0.getOperand(0).getOpcode() == ISD::XOR);
3710 // ((X^1)&1)^1 -> X & 1
3711 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3712 N0.getOperand(0).getOperand(0), N0.getOperand(1));
3714 return DAG.getSetCC(VT, Val, N1,
3715 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3719 uint64_t MinVal, MaxVal;
3720 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3721 if (ISD::isSignedIntSetCC(Cond)) {
3722 MinVal = 1ULL << (OperandBitSize-1);
3723 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3724 MaxVal = ~0ULL >> (65-OperandBitSize);
3729 MaxVal = ~0ULL >> (64-OperandBitSize);
3732 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3733 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3734 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
3735 --C1; // X >= C0 --> X > (C0-1)
3736 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3737 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
3740 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3741 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
3742 ++C1; // X <= C0 --> X < (C0+1)
3743 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3744 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
3747 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
3748 return DAG.getConstant(0, VT); // X < MIN --> false
3750 // Canonicalize setgt X, Min --> setne X, Min
3751 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
3752 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3753 // Canonicalize setlt X, Max --> setne X, Max
3754 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
3755 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3757 // If we have setult X, 1, turn it into seteq X, 0
3758 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
3759 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
3761 // If we have setugt X, Max-1, turn it into seteq X, Max
3762 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
3763 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
3766 // If we have "setcc X, C0", check to see if we can shrink the immediate
3769 // SETUGT X, SINTMAX -> SETLT X, 0
3770 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
3771 C1 == (~0ULL >> (65-OperandBitSize)))
3772 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
3775 // FIXME: Implement the rest of these.
3777 // Fold bit comparisons when we can.
3778 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3779 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
3780 if (ConstantSDNode *AndRHS =
3781 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3782 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3783 // Perform the xform if the AND RHS is a single bit.
3784 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
3785 return DAG.getNode(ISD::SRL, VT, N0,
3786 DAG.getConstant(Log2_64(AndRHS->getValue()),
3787 TLI.getShiftAmountTy()));
3789 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
3790 // (X & 8) == 8 --> (X & 8) >> 3
3791 // Perform the xform if C1 is a single bit.
3792 if ((C1 & (C1-1)) == 0) {
3793 return DAG.getNode(ISD::SRL, VT, N0,
3794 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
3799 } else if (isa<ConstantSDNode>(N0.Val)) {
3800 // Ensure that the constant occurs on the RHS.
3801 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3804 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
3805 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
3806 double C0 = N0C->getValue(), C1 = N1C->getValue();
3809 default: break; // FIXME: Implement the rest of these!
3810 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3811 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3812 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
3813 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
3814 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
3815 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
3818 // Ensure that the constant occurs on the RHS.
3819 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3823 // We can always fold X == Y for integer setcc's.
3824 if (MVT::isInteger(N0.getValueType()))
3825 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3826 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3827 if (UOF == 2) // FP operators that are undefined on NaNs.
3828 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3829 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
3830 return DAG.getConstant(UOF, VT);
3831 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3832 // if it is not already.
3833 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3834 if (NewCond != Cond)
3835 return DAG.getSetCC(VT, N0, N1, NewCond);
3838 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3839 MVT::isInteger(N0.getValueType())) {
3840 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3841 N0.getOpcode() == ISD::XOR) {
3842 // Simplify (X+Y) == (X+Z) --> Y == Z
3843 if (N0.getOpcode() == N1.getOpcode()) {
3844 if (N0.getOperand(0) == N1.getOperand(0))
3845 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
3846 if (N0.getOperand(1) == N1.getOperand(1))
3847 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
3848 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
3849 // If X op Y == Y op X, try other combinations.
3850 if (N0.getOperand(0) == N1.getOperand(1))
3851 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
3852 if (N0.getOperand(1) == N1.getOperand(0))
3853 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
3857 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3858 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3859 // Turn (X+C1) == C2 --> X == C2-C1
3860 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
3861 return DAG.getSetCC(VT, N0.getOperand(0),
3862 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
3863 N0.getValueType()), Cond);
3866 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3867 if (N0.getOpcode() == ISD::XOR)
3868 // If we know that all of the inverted bits are zero, don't bother
3869 // performing the inversion.
3870 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
3871 return DAG.getSetCC(VT, N0.getOperand(0),
3872 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
3873 N0.getValueType()), Cond);
3876 // Turn (C1-X) == C2 --> X == C1-C2
3877 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3878 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
3879 return DAG.getSetCC(VT, N0.getOperand(1),
3880 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
3881 N0.getValueType()), Cond);
3886 // Simplify (X+Z) == X --> Z == 0
3887 if (N0.getOperand(0) == N1)
3888 return DAG.getSetCC(VT, N0.getOperand(1),
3889 DAG.getConstant(0, N0.getValueType()), Cond);
3890 if (N0.getOperand(1) == N1) {
3891 if (DAG.isCommutativeBinOp(N0.getOpcode()))
3892 return DAG.getSetCC(VT, N0.getOperand(0),
3893 DAG.getConstant(0, N0.getValueType()), Cond);
3895 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
3896 // (Z-X) == X --> Z == X<<1
3897 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
3899 DAG.getConstant(1,TLI.getShiftAmountTy()));
3900 AddToWorkList(SH.Val);
3901 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
3906 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3907 N1.getOpcode() == ISD::XOR) {
3908 // Simplify X == (X+Z) --> Z == 0
3909 if (N1.getOperand(0) == N0) {
3910 return DAG.getSetCC(VT, N1.getOperand(1),
3911 DAG.getConstant(0, N1.getValueType()), Cond);
3912 } else if (N1.getOperand(1) == N0) {
3913 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
3914 return DAG.getSetCC(VT, N1.getOperand(0),
3915 DAG.getConstant(0, N1.getValueType()), Cond);
3917 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
3918 // X == (Z-X) --> X<<1 == Z
3919 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
3920 DAG.getConstant(1,TLI.getShiftAmountTy()));
3921 AddToWorkList(SH.Val);
3922 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
3928 // Fold away ALL boolean setcc's.
3930 if (N0.getValueType() == MVT::i1 && foldBooleans) {
3932 default: assert(0 && "Unknown integer setcc!");
3933 case ISD::SETEQ: // X == Y -> (X^Y)^1
3934 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3935 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
3936 AddToWorkList(Temp.Val);
3938 case ISD::SETNE: // X != Y --> (X^Y)
3939 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3941 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
3942 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
3943 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3944 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
3945 AddToWorkList(Temp.Val);
3947 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
3948 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
3949 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3950 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
3951 AddToWorkList(Temp.Val);
3953 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
3954 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
3955 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3956 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
3957 AddToWorkList(Temp.Val);
3959 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
3960 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
3961 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3962 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
3965 if (VT != MVT::i1) {
3966 AddToWorkList(N0.Val);
3967 // FIXME: If running after legalize, we probably can't do this.
3968 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
3973 // Could not fold it.
3977 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3978 /// return a DAG expression to select that will generate the same value by
3979 /// multiplying by a magic number. See:
3980 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3981 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
3982 std::vector<SDNode*> Built;
3983 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
3985 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3991 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3992 /// return a DAG expression to select that will generate the same value by
3993 /// multiplying by a magic number. See:
3994 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3995 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
3996 std::vector<SDNode*> Built;
3997 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
3999 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4005 /// FindBaseOffset - Return true if base is known not to alias with anything
4006 /// but itself. Provides base object and offset as results.
4007 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4008 // Assume it is a primitive operation.
4009 Base = Ptr; Offset = 0;
4011 // If it's an adding a simple constant then integrate the offset.
4012 if (Base.getOpcode() == ISD::ADD) {
4013 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4014 Base = Base.getOperand(0);
4015 Offset += C->getValue();
4019 // If it's any of the following then it can't alias with anything but itself.
4020 return isa<FrameIndexSDNode>(Base) ||
4021 isa<ConstantPoolSDNode>(Base) ||
4022 isa<GlobalAddressSDNode>(Base);
4025 /// isAlias - Return true if there is any possibility that the two addresses
4027 static bool isAlias(SDOperand Ptr1, int64_t Size1, const Value *SrcValue1,
4028 SDOperand Ptr2, int64_t Size2, const Value *SrcValue2) {
4029 // If they are the same then they must be aliases.
4030 if (Ptr1 == Ptr2) return true;
4032 // Gather base node and offset information.
4033 SDOperand Base1, Base2;
4034 int64_t Offset1, Offset2;
4035 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4036 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4038 // If they have a same base address then...
4039 if (Base1 == Base2) {
4040 // Check to see if the addresses overlap.
4041 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4044 // Otherwise they alias if either is unknown.
4045 return !KnownBase1 || !KnownBase2;
4048 /// FindAliasInfo - Extracts the relevant alias information from the memory
4049 /// node. Returns true if the operand was a load.
4050 bool DAGCombiner::FindAliasInfo(SDNode *N,
4051 SDOperand &Ptr, int64_t &Size, const Value *&SrcValue) {
4052 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4053 Ptr = LD->getBasePtr();
4054 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4055 SrcValue = LD->getSrcValue();
4057 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4058 Ptr = ST->getBasePtr();
4059 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4060 SrcValue = ST->getSrcValue();
4062 assert(0 && "FindAliasInfo expected a memory operand");
4068 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4069 /// looking for aliasing nodes and adding them to the Aliases vector.
4070 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4071 SmallVector<SDOperand, 8> &Aliases) {
4072 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4073 std::set<SDNode *> Visited; // Visited node set.
4075 // Get alias information for node.
4078 const Value *SrcValue;
4079 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue);
4082 Chains.push_back(OriginalChain);
4084 // Look at each chain and determine if it is an alias. If so, add it to the
4085 // aliases list. If not, then continue up the chain looking for the next
4087 while (!Chains.empty()) {
4088 SDOperand Chain = Chains.back();
4091 // Don't bother if we've been before.
4092 if (Visited.find(Chain.Val) != Visited.end()) continue;
4093 Visited.insert(Chain.Val);
4095 switch (Chain.getOpcode()) {
4096 case ISD::EntryToken:
4097 // Entry token is ideal chain operand, but handled in FindBetterChain.
4102 // Get alias information for Chain.
4105 const Value *OpSrcValue;
4106 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, OpSrcValue);
4108 // If chain is alias then stop here.
4109 if (!(IsLoad && IsOpLoad) &&
4110 isAlias(Ptr, Size, SrcValue, OpPtr, OpSize, OpSrcValue)) {
4111 Aliases.push_back(Chain);
4113 // Look further up the chain.
4114 Chains.push_back(Chain.getOperand(0));
4115 // Clean up old chain.
4116 AddToWorkList(Chain.Val);
4121 case ISD::TokenFactor:
4122 // We have to check each of the operands of the token factor, so we queue
4123 // then up. Adding the operands to the queue (stack) in reverse order
4124 // maintains the original order and increases the likelihood that getNode
4125 // will find a matching token factor (CSE.)
4126 for (unsigned n = Chain.getNumOperands(); n;)
4127 Chains.push_back(Chain.getOperand(--n));
4128 // Eliminate the token factor if we can.
4129 AddToWorkList(Chain.Val);
4133 // For all other instructions we will just have to take what we can get.
4134 Aliases.push_back(Chain);
4140 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4141 /// for a better chain (aliasing node.)
4142 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4143 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4145 // Accumulate all the aliases to this node.
4146 GatherAllAliases(N, OldChain, Aliases);
4148 if (Aliases.size() == 0) {
4149 // If no operands then chain to entry token.
4150 return DAG.getEntryNode();
4151 } else if (Aliases.size() == 1) {
4152 // If a single operand then chain to it. We don't need to revisit it.
4156 // Construct a custom tailored token factor.
4157 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4158 &Aliases[0], Aliases.size());
4160 // Make sure the old chain gets cleaned up.
4161 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4166 // SelectionDAG::Combine - This is the entry point for the file.
4168 void SelectionDAG::Combine(bool RunningAfterLegalize) {
4169 /// run - This is the main entry point to this class.
4171 DAGCombiner(*this).Run(RunningAfterLegalize);