1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/CommandLine.h"
46 static Statistic NodesCombined ("dagcombiner",
47 "Number of dag nodes combined");
49 static Statistic PreIndexedNodes ("pre_indexed_ops",
50 "Number of pre-indexed nodes created");
51 static Statistic PostIndexedNodes ("post_indexed_ops",
52 "Number of post-indexed nodes created");
55 CombinerAA("combiner-alias-analysis", cl::Hidden,
56 cl::desc("Turn on alias analysis during testing"));
59 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
60 cl::desc("Include global information in alias analysis"));
62 //------------------------------ DAGCombiner ---------------------------------//
64 class VISIBILITY_HIDDEN DAGCombiner {
69 // Worklist of all of the nodes that need to be simplified.
70 std::vector<SDNode*> WorkList;
72 // AA - Used for DAG load/store alias analysis.
75 /// AddUsersToWorkList - When an instruction is simplified, add all users of
76 /// the instruction to the work lists because they might get more simplified
79 void AddUsersToWorkList(SDNode *N) {
80 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
85 /// removeFromWorkList - remove all instances of N from the worklist.
87 void removeFromWorkList(SDNode *N) {
88 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
93 /// AddToWorkList - Add to the work list making sure it's instance is at the
94 /// the back (next to be processed.)
95 void AddToWorkList(SDNode *N) {
96 removeFromWorkList(N);
97 WorkList.push_back(N);
100 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
102 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
104 DEBUG(std::cerr << "\nReplacing.1 "; N->dump();
105 std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
106 std::cerr << " and " << NumTo-1 << " other values\n");
107 std::vector<SDNode*> NowDead;
108 DAG.ReplaceAllUsesWith(N, To, &NowDead);
111 // Push the new nodes and any users onto the worklist
112 for (unsigned i = 0, e = NumTo; i != e; ++i) {
113 AddToWorkList(To[i].Val);
114 AddUsersToWorkList(To[i].Val);
118 // Nodes can be reintroduced into the worklist. Make sure we do not
119 // process a node that has been replaced.
120 removeFromWorkList(N);
121 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
122 removeFromWorkList(NowDead[i]);
124 // Finally, since the node is now dead, remove it from the graph.
126 return SDOperand(N, 0);
129 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
130 return CombineTo(N, &Res, 1, AddTo);
133 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
135 SDOperand To[] = { Res0, Res1 };
136 return CombineTo(N, To, 2, AddTo);
140 /// SimplifyDemandedBits - Check the specified integer node value to see if
141 /// it can be simplified or if things it uses can be simplified by bit
142 /// propagation. If so, return true.
143 bool SimplifyDemandedBits(SDOperand Op) {
144 TargetLowering::TargetLoweringOpt TLO(DAG);
145 uint64_t KnownZero, KnownOne;
146 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
147 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
151 AddToWorkList(Op.Val);
153 // Replace the old value with the new one.
155 DEBUG(std::cerr << "\nReplacing.2 "; TLO.Old.Val->dump();
156 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG);
159 std::vector<SDNode*> NowDead;
160 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
162 // Push the new node and any (possibly new) users onto the worklist.
163 AddToWorkList(TLO.New.Val);
164 AddUsersToWorkList(TLO.New.Val);
166 // Nodes can end up on the worklist more than once. Make sure we do
167 // not process a node that has been replaced.
168 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
169 removeFromWorkList(NowDead[i]);
171 // Finally, if the node is now dead, remove it from the graph. The node
172 // may not be dead if the replacement process recursively simplified to
173 // something else needing this node.
174 if (TLO.Old.Val->use_empty()) {
175 removeFromWorkList(TLO.Old.Val);
176 DAG.DeleteNode(TLO.Old.Val);
181 bool CombineToPreIndexedLoadStore(SDNode *N);
182 bool CombineToPostIndexedLoadStore(SDNode *N);
185 /// visit - call the node-specific routine that knows how to fold each
186 /// particular type of node.
187 SDOperand visit(SDNode *N);
189 // Visitation implementation - Implement dag node combining for different
190 // node types. The semantics are as follows:
192 // SDOperand.Val == 0 - No change was made
193 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
194 // otherwise - N should be replaced by the returned Operand.
196 SDOperand visitTokenFactor(SDNode *N);
197 SDOperand visitADD(SDNode *N);
198 SDOperand visitSUB(SDNode *N);
199 SDOperand visitMUL(SDNode *N);
200 SDOperand visitSDIV(SDNode *N);
201 SDOperand visitUDIV(SDNode *N);
202 SDOperand visitSREM(SDNode *N);
203 SDOperand visitUREM(SDNode *N);
204 SDOperand visitMULHU(SDNode *N);
205 SDOperand visitMULHS(SDNode *N);
206 SDOperand visitAND(SDNode *N);
207 SDOperand visitOR(SDNode *N);
208 SDOperand visitXOR(SDNode *N);
209 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
210 SDOperand visitSHL(SDNode *N);
211 SDOperand visitSRA(SDNode *N);
212 SDOperand visitSRL(SDNode *N);
213 SDOperand visitCTLZ(SDNode *N);
214 SDOperand visitCTTZ(SDNode *N);
215 SDOperand visitCTPOP(SDNode *N);
216 SDOperand visitSELECT(SDNode *N);
217 SDOperand visitSELECT_CC(SDNode *N);
218 SDOperand visitSETCC(SDNode *N);
219 SDOperand visitSIGN_EXTEND(SDNode *N);
220 SDOperand visitZERO_EXTEND(SDNode *N);
221 SDOperand visitANY_EXTEND(SDNode *N);
222 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
223 SDOperand visitTRUNCATE(SDNode *N);
224 SDOperand visitBIT_CONVERT(SDNode *N);
225 SDOperand visitVBIT_CONVERT(SDNode *N);
226 SDOperand visitFADD(SDNode *N);
227 SDOperand visitFSUB(SDNode *N);
228 SDOperand visitFMUL(SDNode *N);
229 SDOperand visitFDIV(SDNode *N);
230 SDOperand visitFREM(SDNode *N);
231 SDOperand visitFCOPYSIGN(SDNode *N);
232 SDOperand visitSINT_TO_FP(SDNode *N);
233 SDOperand visitUINT_TO_FP(SDNode *N);
234 SDOperand visitFP_TO_SINT(SDNode *N);
235 SDOperand visitFP_TO_UINT(SDNode *N);
236 SDOperand visitFP_ROUND(SDNode *N);
237 SDOperand visitFP_ROUND_INREG(SDNode *N);
238 SDOperand visitFP_EXTEND(SDNode *N);
239 SDOperand visitFNEG(SDNode *N);
240 SDOperand visitFABS(SDNode *N);
241 SDOperand visitBRCOND(SDNode *N);
242 SDOperand visitBR_CC(SDNode *N);
243 SDOperand visitLOAD(SDNode *N);
244 SDOperand visitSTORE(SDNode *N);
245 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
246 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
247 SDOperand visitVBUILD_VECTOR(SDNode *N);
248 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
249 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
251 SDOperand XformToShuffleWithZero(SDNode *N);
252 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
254 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
255 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
256 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
257 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
258 SDOperand N3, ISD::CondCode CC);
259 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
260 ISD::CondCode Cond, bool foldBooleans = true);
261 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
262 SDOperand BuildSDIV(SDNode *N);
263 SDOperand BuildUDIV(SDNode *N);
264 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
266 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
267 /// looking for aliasing nodes and adding them to the Aliases vector.
268 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
269 SmallVector<SDOperand, 8> &Aliases);
271 /// isAlias - Return true if there is any possibility that the two addresses
273 bool isAlias(SDOperand Ptr1, int64_t Size1,
274 const Value *SrcValue1, int SrcValueOffset1,
275 SDOperand Ptr2, int64_t Size2,
276 const Value *SrcValue2, int SrcValueOffset2);
278 /// FindAliasInfo - Extracts the relevant alias information from the memory
279 /// node. Returns true if the operand was a load.
280 bool FindAliasInfo(SDNode *N,
281 SDOperand &Ptr, int64_t &Size,
282 const Value *&SrcValue, int &SrcValueOffset);
284 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
285 /// looking for a better chain (aliasing node.)
286 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
289 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
291 TLI(D.getTargetLoweringInfo()),
292 AfterLegalize(false),
295 /// Run - runs the dag combiner on all nodes in the work list
296 void Run(bool RunningAfterLegalize);
300 //===----------------------------------------------------------------------===//
301 // TargetLowering::DAGCombinerInfo implementation
302 //===----------------------------------------------------------------------===//
304 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
305 ((DAGCombiner*)DC)->AddToWorkList(N);
308 SDOperand TargetLowering::DAGCombinerInfo::
309 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
310 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
313 SDOperand TargetLowering::DAGCombinerInfo::
314 CombineTo(SDNode *N, SDOperand Res) {
315 return ((DAGCombiner*)DC)->CombineTo(N, Res);
319 SDOperand TargetLowering::DAGCombinerInfo::
320 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
321 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
327 //===----------------------------------------------------------------------===//
330 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
331 // that selects between the values 1 and 0, making it equivalent to a setcc.
332 // Also, set the incoming LHS, RHS, and CC references to the appropriate
333 // nodes based on the type of node we are checking. This simplifies life a
334 // bit for the callers.
335 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
337 if (N.getOpcode() == ISD::SETCC) {
338 LHS = N.getOperand(0);
339 RHS = N.getOperand(1);
340 CC = N.getOperand(2);
343 if (N.getOpcode() == ISD::SELECT_CC &&
344 N.getOperand(2).getOpcode() == ISD::Constant &&
345 N.getOperand(3).getOpcode() == ISD::Constant &&
346 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
347 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
348 LHS = N.getOperand(0);
349 RHS = N.getOperand(1);
350 CC = N.getOperand(4);
356 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
357 // one use. If this is true, it allows the users to invert the operation for
358 // free when it is profitable to do so.
359 static bool isOneUseSetCC(SDOperand N) {
360 SDOperand N0, N1, N2;
361 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
366 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
367 MVT::ValueType VT = N0.getValueType();
368 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
369 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
370 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
371 if (isa<ConstantSDNode>(N1)) {
372 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
373 AddToWorkList(OpNode.Val);
374 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
375 } else if (N0.hasOneUse()) {
376 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
377 AddToWorkList(OpNode.Val);
378 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
381 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
382 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
383 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
384 if (isa<ConstantSDNode>(N0)) {
385 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
386 AddToWorkList(OpNode.Val);
387 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
388 } else if (N1.hasOneUse()) {
389 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
390 AddToWorkList(OpNode.Val);
391 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
397 void DAGCombiner::Run(bool RunningAfterLegalize) {
398 // set the instance variable, so that the various visit routines may use it.
399 AfterLegalize = RunningAfterLegalize;
401 // Add all the dag nodes to the worklist.
402 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
403 E = DAG.allnodes_end(); I != E; ++I)
404 WorkList.push_back(I);
406 // Create a dummy node (which is not added to allnodes), that adds a reference
407 // to the root node, preventing it from being deleted, and tracking any
408 // changes of the root.
409 HandleSDNode Dummy(DAG.getRoot());
411 // The root of the dag may dangle to deleted nodes until the dag combiner is
412 // done. Set it to null to avoid confusion.
413 DAG.setRoot(SDOperand());
415 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
416 TargetLowering::DAGCombinerInfo
417 DagCombineInfo(DAG, !RunningAfterLegalize, this);
419 // while the worklist isn't empty, inspect the node on the end of it and
420 // try and combine it.
421 while (!WorkList.empty()) {
422 SDNode *N = WorkList.back();
425 // If N has no uses, it is dead. Make sure to revisit all N's operands once
426 // N is deleted from the DAG, since they too may now be dead or may have a
427 // reduced number of uses, allowing other xforms.
428 if (N->use_empty() && N != &Dummy) {
429 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
430 AddToWorkList(N->getOperand(i).Val);
436 SDOperand RV = visit(N);
438 // If nothing happened, try a target-specific DAG combine.
440 assert(N->getOpcode() != ISD::DELETED_NODE &&
441 "Node was deleted but visit returned NULL!");
442 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
443 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
444 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
449 // If we get back the same node we passed in, rather than a new node or
450 // zero, we know that the node must have defined multiple values and
451 // CombineTo was used. Since CombineTo takes care of the worklist
452 // mechanics for us, we have no work to do in this case.
454 assert(N->getOpcode() != ISD::DELETED_NODE &&
455 RV.Val->getOpcode() != ISD::DELETED_NODE &&
456 "Node was deleted but visit returned new node!");
458 DEBUG(std::cerr << "\nReplacing.3 "; N->dump();
459 std::cerr << "\nWith: "; RV.Val->dump(&DAG);
461 std::vector<SDNode*> NowDead;
462 if (N->getNumValues() == RV.Val->getNumValues())
463 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
465 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
467 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
470 // Push the new node and any users onto the worklist
471 AddToWorkList(RV.Val);
472 AddUsersToWorkList(RV.Val);
474 // Nodes can be reintroduced into the worklist. Make sure we do not
475 // process a node that has been replaced.
476 removeFromWorkList(N);
477 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
478 removeFromWorkList(NowDead[i]);
480 // Finally, since the node is now dead, remove it from the graph.
486 // If the root changed (e.g. it was a dead load, update the root).
487 DAG.setRoot(Dummy.getValue());
490 SDOperand DAGCombiner::visit(SDNode *N) {
491 switch(N->getOpcode()) {
493 case ISD::TokenFactor: return visitTokenFactor(N);
494 case ISD::ADD: return visitADD(N);
495 case ISD::SUB: return visitSUB(N);
496 case ISD::MUL: return visitMUL(N);
497 case ISD::SDIV: return visitSDIV(N);
498 case ISD::UDIV: return visitUDIV(N);
499 case ISD::SREM: return visitSREM(N);
500 case ISD::UREM: return visitUREM(N);
501 case ISD::MULHU: return visitMULHU(N);
502 case ISD::MULHS: return visitMULHS(N);
503 case ISD::AND: return visitAND(N);
504 case ISD::OR: return visitOR(N);
505 case ISD::XOR: return visitXOR(N);
506 case ISD::SHL: return visitSHL(N);
507 case ISD::SRA: return visitSRA(N);
508 case ISD::SRL: return visitSRL(N);
509 case ISD::CTLZ: return visitCTLZ(N);
510 case ISD::CTTZ: return visitCTTZ(N);
511 case ISD::CTPOP: return visitCTPOP(N);
512 case ISD::SELECT: return visitSELECT(N);
513 case ISD::SELECT_CC: return visitSELECT_CC(N);
514 case ISD::SETCC: return visitSETCC(N);
515 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
516 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
517 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
518 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
519 case ISD::TRUNCATE: return visitTRUNCATE(N);
520 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
521 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
522 case ISD::FADD: return visitFADD(N);
523 case ISD::FSUB: return visitFSUB(N);
524 case ISD::FMUL: return visitFMUL(N);
525 case ISD::FDIV: return visitFDIV(N);
526 case ISD::FREM: return visitFREM(N);
527 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
528 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
529 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
530 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
531 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
532 case ISD::FP_ROUND: return visitFP_ROUND(N);
533 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
534 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
535 case ISD::FNEG: return visitFNEG(N);
536 case ISD::FABS: return visitFABS(N);
537 case ISD::BRCOND: return visitBRCOND(N);
538 case ISD::BR_CC: return visitBR_CC(N);
539 case ISD::LOAD: return visitLOAD(N);
540 case ISD::STORE: return visitSTORE(N);
541 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
542 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
543 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
544 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
545 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
546 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
547 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
548 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
549 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
550 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
551 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
552 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
553 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
558 /// getInputChainForNode - Given a node, return its input chain if it has one,
559 /// otherwise return a null sd operand.
560 static SDOperand getInputChainForNode(SDNode *N) {
561 if (unsigned NumOps = N->getNumOperands()) {
562 if (N->getOperand(0).getValueType() == MVT::Other)
563 return N->getOperand(0);
564 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
565 return N->getOperand(NumOps-1);
566 for (unsigned i = 1; i < NumOps-1; ++i)
567 if (N->getOperand(i).getValueType() == MVT::Other)
568 return N->getOperand(i);
570 return SDOperand(0, 0);
573 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
574 // If N has two operands, where one has an input chain equal to the other,
575 // the 'other' chain is redundant.
576 if (N->getNumOperands() == 2) {
577 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
578 return N->getOperand(0);
579 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
580 return N->getOperand(1);
584 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
585 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
586 bool Changed = false; // If we should replace this token factor.
588 // Start out with this token factor.
591 // Iterate through token factors. The TFs grows when new token factors are
593 for (unsigned i = 0; i < TFs.size(); ++i) {
596 // Check each of the operands.
597 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
598 SDOperand Op = TF->getOperand(i);
600 switch (Op.getOpcode()) {
601 case ISD::EntryToken:
602 // Entry tokens don't need to be added to the list. They are
607 case ISD::TokenFactor:
608 if ((CombinerAA || Op.hasOneUse()) &&
609 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
610 // Queue up for processing.
611 TFs.push_back(Op.Val);
612 // Clean up in case the token factor is removed.
613 AddToWorkList(Op.Val);
620 // Only add if not there prior.
621 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
630 // If we've change things around then replace token factor.
632 if (Ops.size() == 0) {
633 // The entry token is the only possible outcome.
634 Result = DAG.getEntryNode();
636 // New and improved token factor.
637 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
640 // Don't add users to work list.
641 return CombineTo(N, Result, false);
647 SDOperand DAGCombiner::visitADD(SDNode *N) {
648 SDOperand N0 = N->getOperand(0);
649 SDOperand N1 = N->getOperand(1);
650 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
651 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
652 MVT::ValueType VT = N0.getValueType();
654 // fold (add c1, c2) -> c1+c2
656 return DAG.getNode(ISD::ADD, VT, N0, N1);
657 // canonicalize constant to RHS
659 return DAG.getNode(ISD::ADD, VT, N1, N0);
660 // fold (add x, 0) -> x
661 if (N1C && N1C->isNullValue())
663 // fold ((c1-A)+c2) -> (c1+c2)-A
664 if (N1C && N0.getOpcode() == ISD::SUB)
665 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
666 return DAG.getNode(ISD::SUB, VT,
667 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
670 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
673 // fold ((0-A) + B) -> B-A
674 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
675 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
676 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
677 // fold (A + (0-B)) -> A-B
678 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
679 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
680 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
681 // fold (A+(B-A)) -> B
682 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
683 return N1.getOperand(0);
685 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
686 return SDOperand(N, 0);
688 // fold (a+b) -> (a|b) iff a and b share no bits.
689 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
690 uint64_t LHSZero, LHSOne;
691 uint64_t RHSZero, RHSOne;
692 uint64_t Mask = MVT::getIntVTBitMask(VT);
693 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
695 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
697 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
698 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
699 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
700 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
701 return DAG.getNode(ISD::OR, VT, N0, N1);
708 SDOperand DAGCombiner::visitSUB(SDNode *N) {
709 SDOperand N0 = N->getOperand(0);
710 SDOperand N1 = N->getOperand(1);
711 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
712 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
713 MVT::ValueType VT = N0.getValueType();
715 // fold (sub x, x) -> 0
717 return DAG.getConstant(0, N->getValueType(0));
718 // fold (sub c1, c2) -> c1-c2
720 return DAG.getNode(ISD::SUB, VT, N0, N1);
721 // fold (sub x, c) -> (add x, -c)
723 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
725 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
726 return N0.getOperand(1);
728 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
729 return N0.getOperand(0);
733 SDOperand DAGCombiner::visitMUL(SDNode *N) {
734 SDOperand N0 = N->getOperand(0);
735 SDOperand N1 = N->getOperand(1);
736 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
737 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
738 MVT::ValueType VT = N0.getValueType();
740 // fold (mul c1, c2) -> c1*c2
742 return DAG.getNode(ISD::MUL, VT, N0, N1);
743 // canonicalize constant to RHS
745 return DAG.getNode(ISD::MUL, VT, N1, N0);
746 // fold (mul x, 0) -> 0
747 if (N1C && N1C->isNullValue())
749 // fold (mul x, -1) -> 0-x
750 if (N1C && N1C->isAllOnesValue())
751 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
752 // fold (mul x, (1 << c)) -> x << c
753 if (N1C && isPowerOf2_64(N1C->getValue()))
754 return DAG.getNode(ISD::SHL, VT, N0,
755 DAG.getConstant(Log2_64(N1C->getValue()),
756 TLI.getShiftAmountTy()));
757 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
758 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
759 // FIXME: If the input is something that is easily negated (e.g. a
760 // single-use add), we should put the negate there.
761 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
762 DAG.getNode(ISD::SHL, VT, N0,
763 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
764 TLI.getShiftAmountTy())));
767 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
768 if (N1C && N0.getOpcode() == ISD::SHL &&
769 isa<ConstantSDNode>(N0.getOperand(1))) {
770 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
771 AddToWorkList(C3.Val);
772 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
775 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
778 SDOperand Sh(0,0), Y(0,0);
779 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
780 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
781 N0.Val->hasOneUse()) {
783 } else if (N1.getOpcode() == ISD::SHL &&
784 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
788 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
789 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
792 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
793 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
794 isa<ConstantSDNode>(N0.getOperand(1))) {
795 return DAG.getNode(ISD::ADD, VT,
796 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
797 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
801 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
807 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
808 SDOperand N0 = N->getOperand(0);
809 SDOperand N1 = N->getOperand(1);
810 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
811 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
812 MVT::ValueType VT = N->getValueType(0);
814 // fold (sdiv c1, c2) -> c1/c2
815 if (N0C && N1C && !N1C->isNullValue())
816 return DAG.getNode(ISD::SDIV, VT, N0, N1);
817 // fold (sdiv X, 1) -> X
818 if (N1C && N1C->getSignExtended() == 1LL)
820 // fold (sdiv X, -1) -> 0-X
821 if (N1C && N1C->isAllOnesValue())
822 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
823 // If we know the sign bits of both operands are zero, strength reduce to a
824 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
825 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
826 if (TLI.MaskedValueIsZero(N1, SignBit) &&
827 TLI.MaskedValueIsZero(N0, SignBit))
828 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
829 // fold (sdiv X, pow2) -> simple ops after legalize
830 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
831 (isPowerOf2_64(N1C->getSignExtended()) ||
832 isPowerOf2_64(-N1C->getSignExtended()))) {
833 // If dividing by powers of two is cheap, then don't perform the following
835 if (TLI.isPow2DivCheap())
837 int64_t pow2 = N1C->getSignExtended();
838 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
839 unsigned lg2 = Log2_64(abs2);
840 // Splat the sign bit into the register
841 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
842 DAG.getConstant(MVT::getSizeInBits(VT)-1,
843 TLI.getShiftAmountTy()));
844 AddToWorkList(SGN.Val);
845 // Add (N0 < 0) ? abs2 - 1 : 0;
846 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
847 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
848 TLI.getShiftAmountTy()));
849 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
850 AddToWorkList(SRL.Val);
851 AddToWorkList(ADD.Val); // Divide by pow2
852 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
853 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
854 // If we're dividing by a positive value, we're done. Otherwise, we must
855 // negate the result.
858 AddToWorkList(SRA.Val);
859 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
861 // if integer divide is expensive and we satisfy the requirements, emit an
862 // alternate sequence.
863 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
864 !TLI.isIntDivCheap()) {
865 SDOperand Op = BuildSDIV(N);
866 if (Op.Val) return Op;
871 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
872 SDOperand N0 = N->getOperand(0);
873 SDOperand N1 = N->getOperand(1);
874 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
875 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
876 MVT::ValueType VT = N->getValueType(0);
878 // fold (udiv c1, c2) -> c1/c2
879 if (N0C && N1C && !N1C->isNullValue())
880 return DAG.getNode(ISD::UDIV, VT, N0, N1);
881 // fold (udiv x, (1 << c)) -> x >>u c
882 if (N1C && isPowerOf2_64(N1C->getValue()))
883 return DAG.getNode(ISD::SRL, VT, N0,
884 DAG.getConstant(Log2_64(N1C->getValue()),
885 TLI.getShiftAmountTy()));
886 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
887 if (N1.getOpcode() == ISD::SHL) {
888 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
889 if (isPowerOf2_64(SHC->getValue())) {
890 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
891 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
892 DAG.getConstant(Log2_64(SHC->getValue()),
894 AddToWorkList(Add.Val);
895 return DAG.getNode(ISD::SRL, VT, N0, Add);
899 // fold (udiv x, c) -> alternate
900 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
901 SDOperand Op = BuildUDIV(N);
902 if (Op.Val) return Op;
907 SDOperand DAGCombiner::visitSREM(SDNode *N) {
908 SDOperand N0 = N->getOperand(0);
909 SDOperand N1 = N->getOperand(1);
910 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
911 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
912 MVT::ValueType VT = N->getValueType(0);
914 // fold (srem c1, c2) -> c1%c2
915 if (N0C && N1C && !N1C->isNullValue())
916 return DAG.getNode(ISD::SREM, VT, N0, N1);
917 // If we know the sign bits of both operands are zero, strength reduce to a
918 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
919 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
920 if (TLI.MaskedValueIsZero(N1, SignBit) &&
921 TLI.MaskedValueIsZero(N0, SignBit))
922 return DAG.getNode(ISD::UREM, VT, N0, N1);
924 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
925 // the remainder operation.
926 if (N1C && !N1C->isNullValue()) {
927 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
928 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
929 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
930 AddToWorkList(Div.Val);
931 AddToWorkList(Mul.Val);
938 SDOperand DAGCombiner::visitUREM(SDNode *N) {
939 SDOperand N0 = N->getOperand(0);
940 SDOperand N1 = N->getOperand(1);
941 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
942 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
943 MVT::ValueType VT = N->getValueType(0);
945 // fold (urem c1, c2) -> c1%c2
946 if (N0C && N1C && !N1C->isNullValue())
947 return DAG.getNode(ISD::UREM, VT, N0, N1);
948 // fold (urem x, pow2) -> (and x, pow2-1)
949 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
950 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
951 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
952 if (N1.getOpcode() == ISD::SHL) {
953 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
954 if (isPowerOf2_64(SHC->getValue())) {
955 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
956 AddToWorkList(Add.Val);
957 return DAG.getNode(ISD::AND, VT, N0, Add);
962 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
963 // the remainder operation.
964 if (N1C && !N1C->isNullValue()) {
965 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
966 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
967 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
968 AddToWorkList(Div.Val);
969 AddToWorkList(Mul.Val);
976 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
977 SDOperand N0 = N->getOperand(0);
978 SDOperand N1 = N->getOperand(1);
979 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
981 // fold (mulhs x, 0) -> 0
982 if (N1C && N1C->isNullValue())
984 // fold (mulhs x, 1) -> (sra x, size(x)-1)
985 if (N1C && N1C->getValue() == 1)
986 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
987 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
988 TLI.getShiftAmountTy()));
992 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
993 SDOperand N0 = N->getOperand(0);
994 SDOperand N1 = N->getOperand(1);
995 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
997 // fold (mulhu x, 0) -> 0
998 if (N1C && N1C->isNullValue())
1000 // fold (mulhu x, 1) -> 0
1001 if (N1C && N1C->getValue() == 1)
1002 return DAG.getConstant(0, N0.getValueType());
1006 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1007 /// two operands of the same opcode, try to simplify it.
1008 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1009 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1010 MVT::ValueType VT = N0.getValueType();
1011 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1013 // For each of OP in AND/OR/XOR:
1014 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1015 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1016 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1017 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1018 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1019 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1020 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1021 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1022 N0.getOperand(0).getValueType(),
1023 N0.getOperand(0), N1.getOperand(0));
1024 AddToWorkList(ORNode.Val);
1025 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1028 // For each of OP in SHL/SRL/SRA/AND...
1029 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1030 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1031 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1032 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1033 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1034 N0.getOperand(1) == N1.getOperand(1)) {
1035 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1036 N0.getOperand(0).getValueType(),
1037 N0.getOperand(0), N1.getOperand(0));
1038 AddToWorkList(ORNode.Val);
1039 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1045 SDOperand DAGCombiner::visitAND(SDNode *N) {
1046 SDOperand N0 = N->getOperand(0);
1047 SDOperand N1 = N->getOperand(1);
1048 SDOperand LL, LR, RL, RR, CC0, CC1;
1049 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1050 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1051 MVT::ValueType VT = N1.getValueType();
1053 // fold (and c1, c2) -> c1&c2
1055 return DAG.getNode(ISD::AND, VT, N0, N1);
1056 // canonicalize constant to RHS
1058 return DAG.getNode(ISD::AND, VT, N1, N0);
1059 // fold (and x, -1) -> x
1060 if (N1C && N1C->isAllOnesValue())
1062 // if (and x, c) is known to be zero, return 0
1063 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1064 return DAG.getConstant(0, VT);
1066 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1069 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1070 if (N1C && N0.getOpcode() == ISD::OR)
1071 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1072 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1074 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1075 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1076 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1077 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1078 ~N1C->getValue() & InMask)) {
1079 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1082 // Replace uses of the AND with uses of the Zero extend node.
1085 // We actually want to replace all uses of the any_extend with the
1086 // zero_extend, to avoid duplicating things. This will later cause this
1087 // AND to be folded.
1088 CombineTo(N0.Val, Zext);
1089 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1092 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1093 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1094 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1095 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1097 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1098 MVT::isInteger(LL.getValueType())) {
1099 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1100 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1101 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1102 AddToWorkList(ORNode.Val);
1103 return DAG.getSetCC(VT, ORNode, LR, Op1);
1105 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1106 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1107 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1108 AddToWorkList(ANDNode.Val);
1109 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1111 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1112 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1113 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1114 AddToWorkList(ORNode.Val);
1115 return DAG.getSetCC(VT, ORNode, LR, Op1);
1118 // canonicalize equivalent to ll == rl
1119 if (LL == RR && LR == RL) {
1120 Op1 = ISD::getSetCCSwappedOperands(Op1);
1123 if (LL == RL && LR == RR) {
1124 bool isInteger = MVT::isInteger(LL.getValueType());
1125 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1126 if (Result != ISD::SETCC_INVALID)
1127 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1131 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1132 if (N0.getOpcode() == N1.getOpcode()) {
1133 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1134 if (Tmp.Val) return Tmp;
1137 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1138 // fold (and (sra)) -> (and (srl)) when possible.
1139 if (!MVT::isVector(VT) &&
1140 SimplifyDemandedBits(SDOperand(N, 0)))
1141 return SDOperand(N, 0);
1142 // fold (zext_inreg (extload x)) -> (zextload x)
1143 if (ISD::isEXTLoad(N0.Val)) {
1144 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1145 MVT::ValueType EVT = LN0->getLoadedVT();
1146 // If we zero all the possible extended bits, then we can turn this into
1147 // a zextload if we are running before legalize or the operation is legal.
1148 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1149 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1150 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1151 LN0->getBasePtr(), LN0->getSrcValue(),
1152 LN0->getSrcValueOffset(), EVT);
1154 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1155 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1158 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1159 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
1160 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1161 MVT::ValueType EVT = LN0->getLoadedVT();
1162 // If we zero all the possible extended bits, then we can turn this into
1163 // a zextload if we are running before legalize or the operation is legal.
1164 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1165 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1166 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1167 LN0->getBasePtr(), LN0->getSrcValue(),
1168 LN0->getSrcValueOffset(), EVT);
1170 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1171 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1175 // fold (and (load x), 255) -> (zextload x, i8)
1176 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1177 if (N1C && N0.getOpcode() == ISD::LOAD) {
1178 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1179 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1181 MVT::ValueType EVT, LoadedVT;
1182 if (N1C->getValue() == 255)
1184 else if (N1C->getValue() == 65535)
1186 else if (N1C->getValue() == ~0U)
1191 LoadedVT = LN0->getLoadedVT();
1192 if (EVT != MVT::Other && LoadedVT > EVT &&
1193 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1194 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1195 // For big endian targets, we need to add an offset to the pointer to
1196 // load the correct bytes. For little endian systems, we merely need to
1197 // read fewer bytes from the same pointer.
1199 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1200 SDOperand NewPtr = LN0->getBasePtr();
1201 if (!TLI.isLittleEndian())
1202 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1203 DAG.getConstant(PtrOff, PtrType));
1204 AddToWorkList(NewPtr.Val);
1206 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1207 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1209 CombineTo(N0.Val, Load, Load.getValue(1));
1210 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1218 SDOperand DAGCombiner::visitOR(SDNode *N) {
1219 SDOperand N0 = N->getOperand(0);
1220 SDOperand N1 = N->getOperand(1);
1221 SDOperand LL, LR, RL, RR, CC0, CC1;
1222 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1223 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1224 MVT::ValueType VT = N1.getValueType();
1225 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1227 // fold (or c1, c2) -> c1|c2
1229 return DAG.getNode(ISD::OR, VT, N0, N1);
1230 // canonicalize constant to RHS
1232 return DAG.getNode(ISD::OR, VT, N1, N0);
1233 // fold (or x, 0) -> x
1234 if (N1C && N1C->isNullValue())
1236 // fold (or x, -1) -> -1
1237 if (N1C && N1C->isAllOnesValue())
1239 // fold (or x, c) -> c iff (x & ~c) == 0
1241 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1244 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1247 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1248 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1249 isa<ConstantSDNode>(N0.getOperand(1))) {
1250 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1251 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1253 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1255 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1256 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1257 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1258 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1260 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1261 MVT::isInteger(LL.getValueType())) {
1262 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1263 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1264 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1265 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1266 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1267 AddToWorkList(ORNode.Val);
1268 return DAG.getSetCC(VT, ORNode, LR, Op1);
1270 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1271 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1272 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1273 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1274 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1275 AddToWorkList(ANDNode.Val);
1276 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1279 // canonicalize equivalent to ll == rl
1280 if (LL == RR && LR == RL) {
1281 Op1 = ISD::getSetCCSwappedOperands(Op1);
1284 if (LL == RL && LR == RR) {
1285 bool isInteger = MVT::isInteger(LL.getValueType());
1286 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1287 if (Result != ISD::SETCC_INVALID)
1288 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1292 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1293 if (N0.getOpcode() == N1.getOpcode()) {
1294 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1295 if (Tmp.Val) return Tmp;
1298 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1299 if (N0.getOpcode() == ISD::AND &&
1300 N1.getOpcode() == ISD::AND &&
1301 N0.getOperand(1).getOpcode() == ISD::Constant &&
1302 N1.getOperand(1).getOpcode() == ISD::Constant &&
1303 // Don't increase # computations.
1304 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1305 // We can only do this xform if we know that bits from X that are set in C2
1306 // but not in C1 are already zero. Likewise for Y.
1307 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1308 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1310 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1311 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1312 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1313 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1318 // See if this is some rotate idiom.
1319 if (SDNode *Rot = MatchRotate(N0, N1))
1320 return SDOperand(Rot, 0);
1326 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1327 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1328 if (Op.getOpcode() == ISD::AND) {
1329 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1330 Mask = Op.getOperand(1);
1331 Op = Op.getOperand(0);
1337 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1345 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1346 // idioms for rotate, and if the target supports rotation instructions, generate
1348 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1349 // Must be a legal type. Expanded an promoted things won't work with rotates.
1350 MVT::ValueType VT = LHS.getValueType();
1351 if (!TLI.isTypeLegal(VT)) return 0;
1353 // The target must have at least one rotate flavor.
1354 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1355 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1356 if (!HasROTL && !HasROTR) return 0;
1358 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1359 SDOperand LHSShift; // The shift.
1360 SDOperand LHSMask; // AND value if any.
1361 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1362 return 0; // Not part of a rotate.
1364 SDOperand RHSShift; // The shift.
1365 SDOperand RHSMask; // AND value if any.
1366 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1367 return 0; // Not part of a rotate.
1369 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1370 return 0; // Not shifting the same value.
1372 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1373 return 0; // Shifts must disagree.
1375 // Canonicalize shl to left side in a shl/srl pair.
1376 if (RHSShift.getOpcode() == ISD::SHL) {
1377 std::swap(LHS, RHS);
1378 std::swap(LHSShift, RHSShift);
1379 std::swap(LHSMask , RHSMask );
1382 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1384 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1385 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1386 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1387 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1388 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1389 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1390 if ((LShVal + RShVal) != OpSizeInBits)
1395 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1396 LHSShift.getOperand(1));
1398 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1399 RHSShift.getOperand(1));
1401 // If there is an AND of either shifted operand, apply it to the result.
1402 if (LHSMask.Val || RHSMask.Val) {
1403 uint64_t Mask = MVT::getIntVTBitMask(VT);
1406 uint64_t RHSBits = (1ULL << LShVal)-1;
1407 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1410 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1411 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1414 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1420 // If there is a mask here, and we have a variable shift, we can't be sure
1421 // that we're masking out the right stuff.
1422 if (LHSMask.Val || RHSMask.Val)
1425 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1426 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1427 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1428 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1429 if (ConstantSDNode *SUBC =
1430 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1431 if (SUBC->getValue() == OpSizeInBits)
1433 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1434 LHSShift.getOperand(1)).Val;
1436 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1437 LHSShift.getOperand(1)).Val;
1441 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1442 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1443 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1444 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1445 if (ConstantSDNode *SUBC =
1446 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1447 if (SUBC->getValue() == OpSizeInBits)
1449 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1450 LHSShift.getOperand(1)).Val;
1452 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1453 RHSShift.getOperand(1)).Val;
1461 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1462 SDOperand N0 = N->getOperand(0);
1463 SDOperand N1 = N->getOperand(1);
1464 SDOperand LHS, RHS, CC;
1465 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1466 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1467 MVT::ValueType VT = N0.getValueType();
1469 // fold (xor c1, c2) -> c1^c2
1471 return DAG.getNode(ISD::XOR, VT, N0, N1);
1472 // canonicalize constant to RHS
1474 return DAG.getNode(ISD::XOR, VT, N1, N0);
1475 // fold (xor x, 0) -> x
1476 if (N1C && N1C->isNullValue())
1479 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1482 // fold !(x cc y) -> (x !cc y)
1483 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1484 bool isInt = MVT::isInteger(LHS.getValueType());
1485 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1487 if (N0.getOpcode() == ISD::SETCC)
1488 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1489 if (N0.getOpcode() == ISD::SELECT_CC)
1490 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1491 assert(0 && "Unhandled SetCC Equivalent!");
1494 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1495 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
1496 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1497 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1498 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1499 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1500 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1501 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1502 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1503 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1506 // fold !(x or y) -> (!x and !y) iff x or y are constants
1507 if (N1C && N1C->isAllOnesValue() &&
1508 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1509 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1510 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1511 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1512 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1513 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1514 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1515 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1518 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1519 if (N1C && N0.getOpcode() == ISD::XOR) {
1520 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1521 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1523 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1524 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1526 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1527 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1529 // fold (xor x, x) -> 0
1531 if (!MVT::isVector(VT)) {
1532 return DAG.getConstant(0, VT);
1533 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1534 // Produce a vector of zeros.
1535 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1536 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1537 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1541 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1542 if (N0.getOpcode() == N1.getOpcode()) {
1543 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1544 if (Tmp.Val) return Tmp;
1547 // Simplify the expression using non-local knowledge.
1548 if (!MVT::isVector(VT) &&
1549 SimplifyDemandedBits(SDOperand(N, 0)))
1550 return SDOperand(N, 0);
1555 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1556 SDOperand N0 = N->getOperand(0);
1557 SDOperand N1 = N->getOperand(1);
1558 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1559 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1560 MVT::ValueType VT = N0.getValueType();
1561 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1563 // fold (shl c1, c2) -> c1<<c2
1565 return DAG.getNode(ISD::SHL, VT, N0, N1);
1566 // fold (shl 0, x) -> 0
1567 if (N0C && N0C->isNullValue())
1569 // fold (shl x, c >= size(x)) -> undef
1570 if (N1C && N1C->getValue() >= OpSizeInBits)
1571 return DAG.getNode(ISD::UNDEF, VT);
1572 // fold (shl x, 0) -> x
1573 if (N1C && N1C->isNullValue())
1575 // if (shl x, c) is known to be zero, return 0
1576 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1577 return DAG.getConstant(0, VT);
1578 if (SimplifyDemandedBits(SDOperand(N, 0)))
1579 return SDOperand(N, 0);
1580 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1581 if (N1C && N0.getOpcode() == ISD::SHL &&
1582 N0.getOperand(1).getOpcode() == ISD::Constant) {
1583 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1584 uint64_t c2 = N1C->getValue();
1585 if (c1 + c2 > OpSizeInBits)
1586 return DAG.getConstant(0, VT);
1587 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1588 DAG.getConstant(c1 + c2, N1.getValueType()));
1590 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1591 // (srl (and x, -1 << c1), c1-c2)
1592 if (N1C && N0.getOpcode() == ISD::SRL &&
1593 N0.getOperand(1).getOpcode() == ISD::Constant) {
1594 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1595 uint64_t c2 = N1C->getValue();
1596 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1597 DAG.getConstant(~0ULL << c1, VT));
1599 return DAG.getNode(ISD::SHL, VT, Mask,
1600 DAG.getConstant(c2-c1, N1.getValueType()));
1602 return DAG.getNode(ISD::SRL, VT, Mask,
1603 DAG.getConstant(c1-c2, N1.getValueType()));
1605 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1606 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1607 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1608 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1609 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1610 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1611 isa<ConstantSDNode>(N0.getOperand(1))) {
1612 return DAG.getNode(ISD::ADD, VT,
1613 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1614 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1619 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1620 SDOperand N0 = N->getOperand(0);
1621 SDOperand N1 = N->getOperand(1);
1622 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1623 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1624 MVT::ValueType VT = N0.getValueType();
1626 // fold (sra c1, c2) -> c1>>c2
1628 return DAG.getNode(ISD::SRA, VT, N0, N1);
1629 // fold (sra 0, x) -> 0
1630 if (N0C && N0C->isNullValue())
1632 // fold (sra -1, x) -> -1
1633 if (N0C && N0C->isAllOnesValue())
1635 // fold (sra x, c >= size(x)) -> undef
1636 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1637 return DAG.getNode(ISD::UNDEF, VT);
1638 // fold (sra x, 0) -> x
1639 if (N1C && N1C->isNullValue())
1641 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1643 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1644 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1647 default: EVT = MVT::Other; break;
1648 case 1: EVT = MVT::i1; break;
1649 case 8: EVT = MVT::i8; break;
1650 case 16: EVT = MVT::i16; break;
1651 case 32: EVT = MVT::i32; break;
1653 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1654 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1655 DAG.getValueType(EVT));
1658 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1659 if (N1C && N0.getOpcode() == ISD::SRA) {
1660 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1661 unsigned Sum = N1C->getValue() + C1->getValue();
1662 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1663 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1664 DAG.getConstant(Sum, N1C->getValueType(0)));
1668 // Simplify, based on bits shifted out of the LHS.
1669 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1670 return SDOperand(N, 0);
1673 // If the sign bit is known to be zero, switch this to a SRL.
1674 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1675 return DAG.getNode(ISD::SRL, VT, N0, N1);
1679 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1680 SDOperand N0 = N->getOperand(0);
1681 SDOperand N1 = N->getOperand(1);
1682 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1683 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1684 MVT::ValueType VT = N0.getValueType();
1685 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1687 // fold (srl c1, c2) -> c1 >>u c2
1689 return DAG.getNode(ISD::SRL, VT, N0, N1);
1690 // fold (srl 0, x) -> 0
1691 if (N0C && N0C->isNullValue())
1693 // fold (srl x, c >= size(x)) -> undef
1694 if (N1C && N1C->getValue() >= OpSizeInBits)
1695 return DAG.getNode(ISD::UNDEF, VT);
1696 // fold (srl x, 0) -> x
1697 if (N1C && N1C->isNullValue())
1699 // if (srl x, c) is known to be zero, return 0
1700 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1701 return DAG.getConstant(0, VT);
1702 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1703 if (N1C && N0.getOpcode() == ISD::SRL &&
1704 N0.getOperand(1).getOpcode() == ISD::Constant) {
1705 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1706 uint64_t c2 = N1C->getValue();
1707 if (c1 + c2 > OpSizeInBits)
1708 return DAG.getConstant(0, VT);
1709 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1710 DAG.getConstant(c1 + c2, N1.getValueType()));
1713 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1714 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1715 // Shifting in all undef bits?
1716 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1717 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1718 return DAG.getNode(ISD::UNDEF, VT);
1720 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1721 AddToWorkList(SmallShift.Val);
1722 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1725 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
1726 // bit, which is unmodified by sra.
1727 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
1728 if (N0.getOpcode() == ISD::SRA)
1729 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
1732 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1733 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1734 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1735 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1736 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1738 // If any of the input bits are KnownOne, then the input couldn't be all
1739 // zeros, thus the result of the srl will always be zero.
1740 if (KnownOne) return DAG.getConstant(0, VT);
1742 // If all of the bits input the to ctlz node are known to be zero, then
1743 // the result of the ctlz is "32" and the result of the shift is one.
1744 uint64_t UnknownBits = ~KnownZero & Mask;
1745 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1747 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1748 if ((UnknownBits & (UnknownBits-1)) == 0) {
1749 // Okay, we know that only that the single bit specified by UnknownBits
1750 // could be set on input to the CTLZ node. If this bit is set, the SRL
1751 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1752 // to an SRL,XOR pair, which is likely to simplify more.
1753 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1754 SDOperand Op = N0.getOperand(0);
1756 Op = DAG.getNode(ISD::SRL, VT, Op,
1757 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1758 AddToWorkList(Op.Val);
1760 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1767 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1768 SDOperand N0 = N->getOperand(0);
1769 MVT::ValueType VT = N->getValueType(0);
1771 // fold (ctlz c1) -> c2
1772 if (isa<ConstantSDNode>(N0))
1773 return DAG.getNode(ISD::CTLZ, VT, N0);
1777 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1778 SDOperand N0 = N->getOperand(0);
1779 MVT::ValueType VT = N->getValueType(0);
1781 // fold (cttz c1) -> c2
1782 if (isa<ConstantSDNode>(N0))
1783 return DAG.getNode(ISD::CTTZ, VT, N0);
1787 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1788 SDOperand N0 = N->getOperand(0);
1789 MVT::ValueType VT = N->getValueType(0);
1791 // fold (ctpop c1) -> c2
1792 if (isa<ConstantSDNode>(N0))
1793 return DAG.getNode(ISD::CTPOP, VT, N0);
1797 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1798 SDOperand N0 = N->getOperand(0);
1799 SDOperand N1 = N->getOperand(1);
1800 SDOperand N2 = N->getOperand(2);
1801 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1802 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1803 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1804 MVT::ValueType VT = N->getValueType(0);
1806 // fold select C, X, X -> X
1809 // fold select true, X, Y -> X
1810 if (N0C && !N0C->isNullValue())
1812 // fold select false, X, Y -> Y
1813 if (N0C && N0C->isNullValue())
1815 // fold select C, 1, X -> C | X
1816 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1817 return DAG.getNode(ISD::OR, VT, N0, N2);
1818 // fold select C, 0, X -> ~C & X
1819 // FIXME: this should check for C type == X type, not i1?
1820 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1821 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1822 AddToWorkList(XORNode.Val);
1823 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1825 // fold select C, X, 1 -> ~C | X
1826 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1827 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1828 AddToWorkList(XORNode.Val);
1829 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1831 // fold select C, X, 0 -> C & X
1832 // FIXME: this should check for C type == X type, not i1?
1833 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1834 return DAG.getNode(ISD::AND, VT, N0, N1);
1835 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1836 if (MVT::i1 == VT && N0 == N1)
1837 return DAG.getNode(ISD::OR, VT, N0, N2);
1838 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1839 if (MVT::i1 == VT && N0 == N2)
1840 return DAG.getNode(ISD::AND, VT, N0, N1);
1842 // If we can fold this based on the true/false value, do so.
1843 if (SimplifySelectOps(N, N1, N2))
1844 return SDOperand(N, 0); // Don't revisit N.
1846 // fold selects based on a setcc into other things, such as min/max/abs
1847 if (N0.getOpcode() == ISD::SETCC)
1849 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1850 // having to say they don't support SELECT_CC on every type the DAG knows
1851 // about, since there is no way to mark an opcode illegal at all value types
1852 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1853 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1854 N1, N2, N0.getOperand(2));
1856 return SimplifySelect(N0, N1, N2);
1860 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1861 SDOperand N0 = N->getOperand(0);
1862 SDOperand N1 = N->getOperand(1);
1863 SDOperand N2 = N->getOperand(2);
1864 SDOperand N3 = N->getOperand(3);
1865 SDOperand N4 = N->getOperand(4);
1866 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1868 // fold select_cc lhs, rhs, x, x, cc -> x
1872 // Determine if the condition we're dealing with is constant
1873 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1874 if (SCC.Val) AddToWorkList(SCC.Val);
1876 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1877 if (SCCC->getValue())
1878 return N2; // cond always true -> true val
1880 return N3; // cond always false -> false val
1883 // Fold to a simpler select_cc
1884 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1885 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1886 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1889 // If we can fold this based on the true/false value, do so.
1890 if (SimplifySelectOps(N, N2, N3))
1891 return SDOperand(N, 0); // Don't revisit N.
1893 // fold select_cc into other things, such as min/max/abs
1894 return SimplifySelectCC(N0, N1, N2, N3, CC);
1897 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1898 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1899 cast<CondCodeSDNode>(N->getOperand(2))->get());
1902 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1903 SDOperand N0 = N->getOperand(0);
1904 MVT::ValueType VT = N->getValueType(0);
1906 // fold (sext c1) -> c1
1907 if (isa<ConstantSDNode>(N0))
1908 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1910 // fold (sext (sext x)) -> (sext x)
1911 // fold (sext (aext x)) -> (sext x)
1912 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1913 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1915 // fold (sext (truncate x)) -> (sextinreg x).
1916 if (N0.getOpcode() == ISD::TRUNCATE &&
1917 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
1918 N0.getValueType()))) {
1919 SDOperand Op = N0.getOperand(0);
1920 if (Op.getValueType() < VT) {
1921 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1922 } else if (Op.getValueType() > VT) {
1923 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1925 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
1926 DAG.getValueType(N0.getValueType()));
1929 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1930 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1931 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
1932 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1933 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1934 LN0->getBasePtr(), LN0->getSrcValue(),
1935 LN0->getSrcValueOffset(),
1937 CombineTo(N, ExtLoad);
1938 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1939 ExtLoad.getValue(1));
1940 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1943 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1944 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1945 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1946 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1947 MVT::ValueType EVT = LN0->getLoadedVT();
1948 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1949 LN0->getBasePtr(), LN0->getSrcValue(),
1950 LN0->getSrcValueOffset(), EVT);
1951 CombineTo(N, ExtLoad);
1952 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1953 ExtLoad.getValue(1));
1954 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1960 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1961 SDOperand N0 = N->getOperand(0);
1962 MVT::ValueType VT = N->getValueType(0);
1964 // fold (zext c1) -> c1
1965 if (isa<ConstantSDNode>(N0))
1966 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1967 // fold (zext (zext x)) -> (zext x)
1968 // fold (zext (aext x)) -> (zext x)
1969 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1970 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1972 // fold (zext (truncate x)) -> (and x, mask)
1973 if (N0.getOpcode() == ISD::TRUNCATE &&
1974 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
1975 SDOperand Op = N0.getOperand(0);
1976 if (Op.getValueType() < VT) {
1977 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1978 } else if (Op.getValueType() > VT) {
1979 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1981 return DAG.getZeroExtendInReg(Op, N0.getValueType());
1984 // fold (zext (and (trunc x), cst)) -> (and x, cst).
1985 if (N0.getOpcode() == ISD::AND &&
1986 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1987 N0.getOperand(1).getOpcode() == ISD::Constant) {
1988 SDOperand X = N0.getOperand(0).getOperand(0);
1989 if (X.getValueType() < VT) {
1990 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1991 } else if (X.getValueType() > VT) {
1992 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1994 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1995 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
1998 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1999 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2000 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2001 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2002 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2003 LN0->getBasePtr(), LN0->getSrcValue(),
2004 LN0->getSrcValueOffset(),
2006 CombineTo(N, ExtLoad);
2007 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2008 ExtLoad.getValue(1));
2009 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2012 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2013 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2014 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
2015 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2016 MVT::ValueType EVT = LN0->getLoadedVT();
2017 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2018 LN0->getBasePtr(), LN0->getSrcValue(),
2019 LN0->getSrcValueOffset(), EVT);
2020 CombineTo(N, ExtLoad);
2021 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2022 ExtLoad.getValue(1));
2023 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2028 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2029 SDOperand N0 = N->getOperand(0);
2030 MVT::ValueType VT = N->getValueType(0);
2032 // fold (aext c1) -> c1
2033 if (isa<ConstantSDNode>(N0))
2034 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2035 // fold (aext (aext x)) -> (aext x)
2036 // fold (aext (zext x)) -> (zext x)
2037 // fold (aext (sext x)) -> (sext x)
2038 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2039 N0.getOpcode() == ISD::ZERO_EXTEND ||
2040 N0.getOpcode() == ISD::SIGN_EXTEND)
2041 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2043 // fold (aext (truncate x))
2044 if (N0.getOpcode() == ISD::TRUNCATE) {
2045 SDOperand TruncOp = N0.getOperand(0);
2046 if (TruncOp.getValueType() == VT)
2047 return TruncOp; // x iff x size == zext size.
2048 if (TruncOp.getValueType() > VT)
2049 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2050 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2053 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2054 if (N0.getOpcode() == ISD::AND &&
2055 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2056 N0.getOperand(1).getOpcode() == ISD::Constant) {
2057 SDOperand X = N0.getOperand(0).getOperand(0);
2058 if (X.getValueType() < VT) {
2059 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2060 } else if (X.getValueType() > VT) {
2061 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2063 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2064 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2067 // fold (aext (load x)) -> (aext (truncate (extload x)))
2068 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2069 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2070 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2071 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2072 LN0->getBasePtr(), LN0->getSrcValue(),
2073 LN0->getSrcValueOffset(),
2075 CombineTo(N, ExtLoad);
2076 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2077 ExtLoad.getValue(1));
2078 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2081 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2082 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2083 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2084 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
2086 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2087 MVT::ValueType EVT = LN0->getLoadedVT();
2088 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2089 LN0->getChain(), LN0->getBasePtr(),
2091 LN0->getSrcValueOffset(), EVT);
2092 CombineTo(N, ExtLoad);
2093 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2094 ExtLoad.getValue(1));
2095 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2101 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2102 SDOperand N0 = N->getOperand(0);
2103 SDOperand N1 = N->getOperand(1);
2104 MVT::ValueType VT = N->getValueType(0);
2105 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2106 unsigned EVTBits = MVT::getSizeInBits(EVT);
2108 // fold (sext_in_reg c1) -> c1
2109 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2110 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2112 // If the input is already sign extended, just drop the extension.
2113 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2116 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2117 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2118 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2119 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2122 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2123 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2124 return DAG.getZeroExtendInReg(N0, EVT);
2126 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2127 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2128 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2129 if (N0.getOpcode() == ISD::SRL) {
2130 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2131 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2132 // We can turn this into an SRA iff the input to the SRL is already sign
2134 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2135 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2136 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2140 // fold (sext_inreg (extload x)) -> (sextload x)
2141 if (ISD::isEXTLoad(N0.Val) &&
2142 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2143 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2144 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2145 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2146 LN0->getBasePtr(), LN0->getSrcValue(),
2147 LN0->getSrcValueOffset(), EVT);
2148 CombineTo(N, ExtLoad);
2149 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2150 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2152 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2153 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
2154 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2155 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2156 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2157 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2158 LN0->getBasePtr(), LN0->getSrcValue(),
2159 LN0->getSrcValueOffset(), EVT);
2160 CombineTo(N, ExtLoad);
2161 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2162 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2167 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2168 SDOperand N0 = N->getOperand(0);
2169 MVT::ValueType VT = N->getValueType(0);
2172 if (N0.getValueType() == N->getValueType(0))
2174 // fold (truncate c1) -> c1
2175 if (isa<ConstantSDNode>(N0))
2176 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2177 // fold (truncate (truncate x)) -> (truncate x)
2178 if (N0.getOpcode() == ISD::TRUNCATE)
2179 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2180 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2181 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2182 N0.getOpcode() == ISD::ANY_EXTEND) {
2183 if (N0.getOperand(0).getValueType() < VT)
2184 // if the source is smaller than the dest, we still need an extend
2185 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2186 else if (N0.getOperand(0).getValueType() > VT)
2187 // if the source is larger than the dest, than we just need the truncate
2188 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2190 // if the source and dest are the same type, we can drop both the extend
2192 return N0.getOperand(0);
2194 // fold (truncate (load x)) -> (smaller load x)
2195 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2196 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
2197 // zero extended form: by shrinking the load, we lose track of the fact
2198 // that it is already zero extended.
2199 // FIXME: This should be reevaluated.
2201 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2202 "Cannot truncate to larger type!");
2203 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2204 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2205 // For big endian targets, we need to add an offset to the pointer to load
2206 // the correct bytes. For little endian systems, we merely need to read
2207 // fewer bytes from the same pointer.
2209 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2210 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() :
2211 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2212 DAG.getConstant(PtrOff, PtrType));
2213 AddToWorkList(NewPtr.Val);
2214 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr,
2215 LN0->getSrcValue(), LN0->getSrcValueOffset());
2217 CombineTo(N0.Val, Load, Load.getValue(1));
2218 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2223 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2224 SDOperand N0 = N->getOperand(0);
2225 MVT::ValueType VT = N->getValueType(0);
2227 // If the input is a constant, let getNode() fold it.
2228 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2229 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2230 if (Res.Val != N) return Res;
2233 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2234 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2236 // fold (conv (load x)) -> (load (conv*)x)
2237 // FIXME: These xforms need to know that the resultant load doesn't need a
2238 // higher alignment than the original!
2239 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2240 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2241 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2242 LN0->getSrcValue(), LN0->getSrcValueOffset());
2244 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2252 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2253 SDOperand N0 = N->getOperand(0);
2254 MVT::ValueType VT = N->getValueType(0);
2256 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2257 // First check to see if this is all constant.
2258 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2259 VT == MVT::Vector) {
2260 bool isSimple = true;
2261 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2262 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2263 N0.getOperand(i).getOpcode() != ISD::Constant &&
2264 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2269 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2270 if (isSimple && !MVT::isVector(DestEltVT)) {
2271 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2278 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2279 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2280 /// destination element value type.
2281 SDOperand DAGCombiner::
2282 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2283 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2285 // If this is already the right type, we're done.
2286 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2288 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2289 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2291 // If this is a conversion of N elements of one type to N elements of another
2292 // type, convert each element. This handles FP<->INT cases.
2293 if (SrcBitSize == DstBitSize) {
2294 SmallVector<SDOperand, 8> Ops;
2295 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2296 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2297 AddToWorkList(Ops.back().Val);
2299 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2300 Ops.push_back(DAG.getValueType(DstEltVT));
2301 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2304 // Otherwise, we're growing or shrinking the elements. To avoid having to
2305 // handle annoying details of growing/shrinking FP values, we convert them to
2307 if (MVT::isFloatingPoint(SrcEltVT)) {
2308 // Convert the input float vector to a int vector where the elements are the
2310 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2311 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2312 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2316 // Now we know the input is an integer vector. If the output is a FP type,
2317 // convert to integer first, then to FP of the right size.
2318 if (MVT::isFloatingPoint(DstEltVT)) {
2319 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2320 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2321 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2323 // Next, convert to FP elements of the same size.
2324 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2327 // Okay, we know the src/dst types are both integers of differing types.
2328 // Handling growing first.
2329 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2330 if (SrcBitSize < DstBitSize) {
2331 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2333 SmallVector<SDOperand, 8> Ops;
2334 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2335 i += NumInputsPerOutput) {
2336 bool isLE = TLI.isLittleEndian();
2337 uint64_t NewBits = 0;
2338 bool EltIsUndef = true;
2339 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2340 // Shift the previously computed bits over.
2341 NewBits <<= SrcBitSize;
2342 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2343 if (Op.getOpcode() == ISD::UNDEF) continue;
2346 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2350 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2352 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2355 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2356 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2357 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2360 // Finally, this must be the case where we are shrinking elements: each input
2361 // turns into multiple outputs.
2362 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2363 SmallVector<SDOperand, 8> Ops;
2364 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2365 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2366 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2367 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2370 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2372 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2373 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2374 OpVal >>= DstBitSize;
2375 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2378 // For big endian targets, swap the order of the pieces of each element.
2379 if (!TLI.isLittleEndian())
2380 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2382 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2383 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2384 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2389 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2390 SDOperand N0 = N->getOperand(0);
2391 SDOperand N1 = N->getOperand(1);
2392 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2393 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2394 MVT::ValueType VT = N->getValueType(0);
2396 // fold (fadd c1, c2) -> c1+c2
2398 return DAG.getNode(ISD::FADD, VT, N0, N1);
2399 // canonicalize constant to RHS
2400 if (N0CFP && !N1CFP)
2401 return DAG.getNode(ISD::FADD, VT, N1, N0);
2402 // fold (A + (-B)) -> A-B
2403 if (N1.getOpcode() == ISD::FNEG)
2404 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2405 // fold ((-A) + B) -> B-A
2406 if (N0.getOpcode() == ISD::FNEG)
2407 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2411 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2412 SDOperand N0 = N->getOperand(0);
2413 SDOperand N1 = N->getOperand(1);
2414 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2415 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2416 MVT::ValueType VT = N->getValueType(0);
2418 // fold (fsub c1, c2) -> c1-c2
2420 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2421 // fold (A-(-B)) -> A+B
2422 if (N1.getOpcode() == ISD::FNEG)
2423 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2427 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2428 SDOperand N0 = N->getOperand(0);
2429 SDOperand N1 = N->getOperand(1);
2430 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2431 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2432 MVT::ValueType VT = N->getValueType(0);
2434 // fold (fmul c1, c2) -> c1*c2
2436 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2437 // canonicalize constant to RHS
2438 if (N0CFP && !N1CFP)
2439 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2440 // fold (fmul X, 2.0) -> (fadd X, X)
2441 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2442 return DAG.getNode(ISD::FADD, VT, N0, N0);
2446 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2447 SDOperand N0 = N->getOperand(0);
2448 SDOperand N1 = N->getOperand(1);
2449 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2450 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2451 MVT::ValueType VT = N->getValueType(0);
2453 // fold (fdiv c1, c2) -> c1/c2
2455 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2459 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2460 SDOperand N0 = N->getOperand(0);
2461 SDOperand N1 = N->getOperand(1);
2462 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2463 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2464 MVT::ValueType VT = N->getValueType(0);
2466 // fold (frem c1, c2) -> fmod(c1,c2)
2468 return DAG.getNode(ISD::FREM, VT, N0, N1);
2472 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2473 SDOperand N0 = N->getOperand(0);
2474 SDOperand N1 = N->getOperand(1);
2475 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2476 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2477 MVT::ValueType VT = N->getValueType(0);
2479 if (N0CFP && N1CFP) // Constant fold
2480 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2483 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2484 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2489 u.d = N1CFP->getValue();
2491 return DAG.getNode(ISD::FABS, VT, N0);
2493 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2496 // copysign(fabs(x), y) -> copysign(x, y)
2497 // copysign(fneg(x), y) -> copysign(x, y)
2498 // copysign(copysign(x,z), y) -> copysign(x, y)
2499 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2500 N0.getOpcode() == ISD::FCOPYSIGN)
2501 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2503 // copysign(x, abs(y)) -> abs(x)
2504 if (N1.getOpcode() == ISD::FABS)
2505 return DAG.getNode(ISD::FABS, VT, N0);
2507 // copysign(x, copysign(y,z)) -> copysign(x, z)
2508 if (N1.getOpcode() == ISD::FCOPYSIGN)
2509 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2511 // copysign(x, fp_extend(y)) -> copysign(x, y)
2512 // copysign(x, fp_round(y)) -> copysign(x, y)
2513 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2514 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2521 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2522 SDOperand N0 = N->getOperand(0);
2523 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2524 MVT::ValueType VT = N->getValueType(0);
2526 // fold (sint_to_fp c1) -> c1fp
2528 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2532 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2533 SDOperand N0 = N->getOperand(0);
2534 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2535 MVT::ValueType VT = N->getValueType(0);
2537 // fold (uint_to_fp c1) -> c1fp
2539 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2543 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2544 SDOperand N0 = N->getOperand(0);
2545 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2546 MVT::ValueType VT = N->getValueType(0);
2548 // fold (fp_to_sint c1fp) -> c1
2550 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2554 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2555 SDOperand N0 = N->getOperand(0);
2556 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2557 MVT::ValueType VT = N->getValueType(0);
2559 // fold (fp_to_uint c1fp) -> c1
2561 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2565 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2566 SDOperand N0 = N->getOperand(0);
2567 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2568 MVT::ValueType VT = N->getValueType(0);
2570 // fold (fp_round c1fp) -> c1fp
2572 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2574 // fold (fp_round (fp_extend x)) -> x
2575 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2576 return N0.getOperand(0);
2578 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2579 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2580 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2581 AddToWorkList(Tmp.Val);
2582 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2588 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2589 SDOperand N0 = N->getOperand(0);
2590 MVT::ValueType VT = N->getValueType(0);
2591 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2592 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2594 // fold (fp_round_inreg c1fp) -> c1fp
2596 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2597 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2602 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2603 SDOperand N0 = N->getOperand(0);
2604 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2605 MVT::ValueType VT = N->getValueType(0);
2607 // fold (fp_extend c1fp) -> c1fp
2609 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2611 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2612 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2613 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2614 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2615 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2616 LN0->getBasePtr(), LN0->getSrcValue(),
2617 LN0->getSrcValueOffset(),
2619 CombineTo(N, ExtLoad);
2620 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2621 ExtLoad.getValue(1));
2622 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2629 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2630 SDOperand N0 = N->getOperand(0);
2631 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2632 MVT::ValueType VT = N->getValueType(0);
2634 // fold (fneg c1) -> -c1
2636 return DAG.getNode(ISD::FNEG, VT, N0);
2637 // fold (fneg (sub x, y)) -> (sub y, x)
2638 if (N0.getOpcode() == ISD::SUB)
2639 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2640 // fold (fneg (fneg x)) -> x
2641 if (N0.getOpcode() == ISD::FNEG)
2642 return N0.getOperand(0);
2646 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2647 SDOperand N0 = N->getOperand(0);
2648 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2649 MVT::ValueType VT = N->getValueType(0);
2651 // fold (fabs c1) -> fabs(c1)
2653 return DAG.getNode(ISD::FABS, VT, N0);
2654 // fold (fabs (fabs x)) -> (fabs x)
2655 if (N0.getOpcode() == ISD::FABS)
2656 return N->getOperand(0);
2657 // fold (fabs (fneg x)) -> (fabs x)
2658 // fold (fabs (fcopysign x, y)) -> (fabs x)
2659 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2660 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2665 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2666 SDOperand Chain = N->getOperand(0);
2667 SDOperand N1 = N->getOperand(1);
2668 SDOperand N2 = N->getOperand(2);
2669 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2671 // never taken branch, fold to chain
2672 if (N1C && N1C->isNullValue())
2674 // unconditional branch
2675 if (N1C && N1C->getValue() == 1)
2676 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2677 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2679 if (N1.getOpcode() == ISD::SETCC &&
2680 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2681 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2682 N1.getOperand(0), N1.getOperand(1), N2);
2687 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2689 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2690 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2691 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2693 // Use SimplifySetCC to simplify SETCC's.
2694 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2695 if (Simp.Val) AddToWorkList(Simp.Val);
2697 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2699 // fold br_cc true, dest -> br dest (unconditional branch)
2700 if (SCCC && SCCC->getValue())
2701 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2703 // fold br_cc false, dest -> unconditional fall through
2704 if (SCCC && SCCC->isNullValue())
2705 return N->getOperand(0);
2707 // fold to a simpler setcc
2708 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2709 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2710 Simp.getOperand(2), Simp.getOperand(0),
2711 Simp.getOperand(1), N->getOperand(4));
2716 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
2717 /// pre-indexed load / store when the base pointer is a add or subtract
2718 /// and it has other uses besides the load / store. After the
2719 /// transformation, the new indexed load / store has effectively folded
2720 /// the add / subtract in and all of its other uses are redirected to the
2721 /// new load / store.
2722 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
2729 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2730 VT = LD->getLoadedVT();
2731 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
2732 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
2734 Ptr = LD->getBasePtr();
2735 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2736 VT = ST->getStoredVT();
2737 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
2738 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
2740 Ptr = ST->getBasePtr();
2745 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
2746 // out. There is no reason to make this a preinc/predec.
2747 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
2748 Ptr.Val->hasOneUse())
2751 // Ask the target to do addressing mode selection.
2754 ISD::MemIndexedMode AM = ISD::UNINDEXED;
2755 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
2758 // Try turning it into a pre-indexed load / store except when:
2759 // 1) The base is a frame index.
2760 // 2) If N is a store and the ptr is either the same as or is a
2761 // predecessor of the value being stored.
2762 // 3) Another use of base ptr is a predecessor of N. If ptr is folded
2763 // that would create a cycle.
2764 // 4) All uses are load / store ops that use it as base ptr.
2766 // Check #1. Preinc'ing a frame index would require copying the stack pointer
2767 // (plus the implicit offset) to a register to preinc anyway.
2768 if (isa<FrameIndexSDNode>(BasePtr))
2773 SDOperand Val = cast<StoreSDNode>(N)->getValue();
2774 if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val))
2778 // Now check for #2 and #3.
2779 bool RealUse = false;
2780 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
2781 E = Ptr.Val->use_end(); I != E; ++I) {
2785 if (Use->isPredecessor(N))
2788 if (!((Use->getOpcode() == ISD::LOAD &&
2789 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
2790 (Use->getOpcode() == ISD::STORE) &&
2791 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
2799 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
2801 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
2804 DEBUG(std::cerr << "\nReplacing.4 "; N->dump();
2805 std::cerr << "\nWith: "; Result.Val->dump(&DAG);
2807 std::vector<SDNode*> NowDead;
2809 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
2811 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
2814 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
2818 // Nodes can end up on the worklist more than once. Make sure we do
2819 // not process a node that has been replaced.
2820 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
2821 removeFromWorkList(NowDead[i]);
2822 // Finally, since the node is now dead, remove it from the graph.
2825 // Replace the uses of Ptr with uses of the updated base value.
2826 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
2828 removeFromWorkList(Ptr.Val);
2829 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
2830 removeFromWorkList(NowDead[i]);
2831 DAG.DeleteNode(Ptr.Val);
2836 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
2837 /// add / sub of the base pointer node into a post-indexed load / store.
2838 /// The transformation folded the add / subtract into the new indexed
2839 /// load / store effectively and all of its uses are redirected to the
2840 /// new load / store.
2841 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
2848 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2849 VT = LD->getLoadedVT();
2850 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
2851 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
2853 Ptr = LD->getBasePtr();
2854 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2855 VT = ST->getStoredVT();
2856 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
2857 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
2859 Ptr = ST->getBasePtr();
2864 if (Ptr.Val->hasOneUse())
2867 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
2868 E = Ptr.Val->use_end(); I != E; ++I) {
2871 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
2876 ISD::MemIndexedMode AM = ISD::UNINDEXED;
2877 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
2879 std::swap(BasePtr, Offset);
2883 // Try turning it into a post-indexed load / store except when
2884 // 1) All uses are load / store ops that use it as base ptr.
2885 // 2) Op must be independent of N, i.e. Op is neither a predecessor
2886 // nor a successor of N. Otherwise, if Op is folded that would
2890 bool TryNext = false;
2891 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
2892 EE = BasePtr.Val->use_end(); II != EE; ++II) {
2897 // If all the uses are load / store addresses, then don't do the
2899 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
2900 bool RealUse = false;
2901 for (SDNode::use_iterator III = Use->use_begin(),
2902 EEE = Use->use_end(); III != EEE; ++III) {
2903 SDNode *UseUse = *III;
2904 if (!((UseUse->getOpcode() == ISD::LOAD &&
2905 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
2906 (UseUse->getOpcode() == ISD::STORE) &&
2907 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
2921 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
2922 SDOperand Result = isLoad
2923 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
2924 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
2927 DEBUG(std::cerr << "\nReplacing.5 "; N->dump();
2928 std::cerr << "\nWith: "; Result.Val->dump(&DAG);
2930 std::vector<SDNode*> NowDead;
2932 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
2934 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
2937 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
2941 // Nodes can end up on the worklist more than once. Make sure we do
2942 // not process a node that has been replaced.
2943 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
2944 removeFromWorkList(NowDead[i]);
2945 // Finally, since the node is now dead, remove it from the graph.
2948 // Replace the uses of Use with uses of the updated base value.
2949 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
2950 Result.getValue(isLoad ? 1 : 0),
2952 removeFromWorkList(Op);
2953 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
2954 removeFromWorkList(NowDead[i]);
2965 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2966 LoadSDNode *LD = cast<LoadSDNode>(N);
2967 SDOperand Chain = LD->getChain();
2968 SDOperand Ptr = LD->getBasePtr();
2970 // If there are no uses of the loaded value, change uses of the chain value
2971 // into uses of the chain input (i.e. delete the dead load).
2972 if (N->hasNUsesOfValue(0, 0))
2973 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2975 // If this load is directly stored, replace the load value with the stored
2977 // TODO: Handle store large -> read small portion.
2978 // TODO: Handle TRUNCSTORE/LOADEXT
2979 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2980 if (ISD::isNON_TRUNCStore(Chain.Val)) {
2981 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
2982 if (PrevST->getBasePtr() == Ptr &&
2983 PrevST->getValue().getValueType() == N->getValueType(0))
2984 return CombineTo(N, Chain.getOperand(1), Chain);
2989 // Walk up chain skipping non-aliasing memory nodes.
2990 SDOperand BetterChain = FindBetterChain(N, Chain);
2992 // If there is a better chain.
2993 if (Chain != BetterChain) {
2996 // Replace the chain to void dependency.
2997 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2998 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
2999 LD->getSrcValue(), LD->getSrcValueOffset());
3001 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
3002 LD->getValueType(0),
3003 BetterChain, Ptr, LD->getSrcValue(),
3004 LD->getSrcValueOffset(),
3008 // Create token factor to keep old chain connected.
3009 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
3010 Chain, ReplLoad.getValue(1));
3012 // Replace uses with load result and token factor. Don't add users
3014 return CombineTo(N, ReplLoad.getValue(0), Token, false);
3018 // Try transforming N to an indexed load.
3019 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3020 return SDOperand(N, 0);
3025 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
3026 StoreSDNode *ST = cast<StoreSDNode>(N);
3027 SDOperand Chain = ST->getChain();
3028 SDOperand Value = ST->getValue();
3029 SDOperand Ptr = ST->getBasePtr();
3031 // If this is a store of a bit convert, store the input value.
3032 // FIXME: This needs to know that the resultant store does not need a
3033 // higher alignment than the original.
3034 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
3035 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
3036 ST->getSrcValueOffset());
3040 // Walk up chain skipping non-aliasing memory nodes.
3041 SDOperand BetterChain = FindBetterChain(N, Chain);
3043 // If there is a better chain.
3044 if (Chain != BetterChain) {
3045 // Replace the chain to avoid dependency.
3046 SDOperand ReplStore;
3047 if (ST->isTruncatingStore()) {
3048 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
3049 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT());
3051 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
3052 ST->getSrcValue(), ST->getSrcValueOffset());
3055 // Create token to keep both nodes around.
3057 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
3059 // Don't add users to work list.
3060 return CombineTo(N, Token, false);
3064 // Try transforming N to an indexed store.
3065 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3066 return SDOperand(N, 0);
3071 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
3072 SDOperand InVec = N->getOperand(0);
3073 SDOperand InVal = N->getOperand(1);
3074 SDOperand EltNo = N->getOperand(2);
3076 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
3077 // vector with the inserted element.
3078 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3079 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3080 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3081 if (Elt < Ops.size())
3083 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
3084 &Ops[0], Ops.size());
3090 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
3091 SDOperand InVec = N->getOperand(0);
3092 SDOperand InVal = N->getOperand(1);
3093 SDOperand EltNo = N->getOperand(2);
3094 SDOperand NumElts = N->getOperand(3);
3095 SDOperand EltType = N->getOperand(4);
3097 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
3098 // vector with the inserted element.
3099 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3100 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3101 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3102 if (Elt < Ops.size()-2)
3104 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
3105 &Ops[0], Ops.size());
3111 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
3112 unsigned NumInScalars = N->getNumOperands()-2;
3113 SDOperand NumElts = N->getOperand(NumInScalars);
3114 SDOperand EltType = N->getOperand(NumInScalars+1);
3116 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
3117 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
3118 // two distinct vectors, turn this into a shuffle node.
3119 SDOperand VecIn1, VecIn2;
3120 for (unsigned i = 0; i != NumInScalars; ++i) {
3121 // Ignore undef inputs.
3122 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3124 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
3125 // constant index, bail out.
3126 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
3127 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
3128 VecIn1 = VecIn2 = SDOperand(0, 0);
3132 // If the input vector type disagrees with the result of the vbuild_vector,
3133 // we can't make a shuffle.
3134 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
3135 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
3136 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
3137 VecIn1 = VecIn2 = SDOperand(0, 0);
3141 // Otherwise, remember this. We allow up to two distinct input vectors.
3142 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
3145 if (VecIn1.Val == 0) {
3146 VecIn1 = ExtractedFromVec;
3147 } else if (VecIn2.Val == 0) {
3148 VecIn2 = ExtractedFromVec;
3151 VecIn1 = VecIn2 = SDOperand(0, 0);
3156 // If everything is good, we can make a shuffle operation.
3158 SmallVector<SDOperand, 8> BuildVecIndices;
3159 for (unsigned i = 0; i != NumInScalars; ++i) {
3160 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
3161 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
3165 SDOperand Extract = N->getOperand(i);
3167 // If extracting from the first vector, just use the index directly.
3168 if (Extract.getOperand(0) == VecIn1) {
3169 BuildVecIndices.push_back(Extract.getOperand(1));
3173 // Otherwise, use InIdx + VecSize
3174 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
3175 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
3178 // Add count and size info.
3179 BuildVecIndices.push_back(NumElts);
3180 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
3182 // Return the new VVECTOR_SHUFFLE node.
3188 // Use an undef vbuild_vector as input for the second operand.
3189 std::vector<SDOperand> UnOps(NumInScalars,
3190 DAG.getNode(ISD::UNDEF,
3191 cast<VTSDNode>(EltType)->getVT()));
3192 UnOps.push_back(NumElts);
3193 UnOps.push_back(EltType);
3194 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3195 &UnOps[0], UnOps.size());
3196 AddToWorkList(Ops[1].Val);
3198 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3199 &BuildVecIndices[0], BuildVecIndices.size());
3202 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
3208 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
3209 SDOperand ShufMask = N->getOperand(2);
3210 unsigned NumElts = ShufMask.getNumOperands();
3212 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3213 bool isIdentity = true;
3214 for (unsigned i = 0; i != NumElts; ++i) {
3215 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3216 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3221 if (isIdentity) return N->getOperand(0);
3223 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3225 for (unsigned i = 0; i != NumElts; ++i) {
3226 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3227 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3232 if (isIdentity) return N->getOperand(1);
3234 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3236 bool isUnary = true;
3237 bool isSplat = true;
3239 unsigned BaseIdx = 0;
3240 for (unsigned i = 0; i != NumElts; ++i)
3241 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3242 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3243 int V = (Idx < NumElts) ? 0 : 1;
3257 SDOperand N0 = N->getOperand(0);
3258 SDOperand N1 = N->getOperand(1);
3259 // Normalize unary shuffle so the RHS is undef.
3260 if (isUnary && VecNum == 1)
3263 // If it is a splat, check if the argument vector is a build_vector with
3264 // all scalar elements the same.
3267 if (V->getOpcode() == ISD::BIT_CONVERT)
3268 V = V->getOperand(0).Val;
3269 if (V->getOpcode() == ISD::BUILD_VECTOR) {
3270 unsigned NumElems = V->getNumOperands()-2;
3271 if (NumElems > BaseIdx) {
3273 bool AllSame = true;
3274 for (unsigned i = 0; i != NumElems; ++i) {
3275 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3276 Base = V->getOperand(i);
3280 // Splat of <u, u, u, u>, return <u, u, u, u>
3283 for (unsigned i = 0; i != NumElems; ++i) {
3284 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3285 V->getOperand(i) != Base) {
3290 // Splat of <x, x, x, x>, return <x, x, x, x>
3297 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3299 if (isUnary || N0 == N1) {
3300 if (N0.getOpcode() == ISD::UNDEF)
3301 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
3302 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3304 SmallVector<SDOperand, 8> MappedOps;
3305 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
3306 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3307 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3308 MappedOps.push_back(ShufMask.getOperand(i));
3311 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3312 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3315 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
3316 &MappedOps[0], MappedOps.size());
3317 AddToWorkList(ShufMask.Val);
3318 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3320 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3327 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3328 SDOperand ShufMask = N->getOperand(2);
3329 unsigned NumElts = ShufMask.getNumOperands()-2;
3331 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3332 bool isIdentity = true;
3333 for (unsigned i = 0; i != NumElts; ++i) {
3334 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3335 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3340 if (isIdentity) return N->getOperand(0);
3342 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3344 for (unsigned i = 0; i != NumElts; ++i) {
3345 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3346 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3351 if (isIdentity) return N->getOperand(1);
3353 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3355 bool isUnary = true;
3356 bool isSplat = true;
3358 unsigned BaseIdx = 0;
3359 for (unsigned i = 0; i != NumElts; ++i)
3360 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3361 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3362 int V = (Idx < NumElts) ? 0 : 1;
3376 SDOperand N0 = N->getOperand(0);
3377 SDOperand N1 = N->getOperand(1);
3378 // Normalize unary shuffle so the RHS is undef.
3379 if (isUnary && VecNum == 1)
3382 // If it is a splat, check if the argument vector is a build_vector with
3383 // all scalar elements the same.
3387 // If this is a vbit convert that changes the element type of the vector but
3388 // not the number of vector elements, look through it. Be careful not to
3389 // look though conversions that change things like v4f32 to v2f64.
3390 if (V->getOpcode() == ISD::VBIT_CONVERT) {
3391 SDOperand ConvInput = V->getOperand(0);
3392 if (ConvInput.getValueType() == MVT::Vector &&
3394 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2))
3398 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3399 unsigned NumElems = V->getNumOperands()-2;
3400 if (NumElems > BaseIdx) {
3402 bool AllSame = true;
3403 for (unsigned i = 0; i != NumElems; ++i) {
3404 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3405 Base = V->getOperand(i);
3409 // Splat of <u, u, u, u>, return <u, u, u, u>
3412 for (unsigned i = 0; i != NumElems; ++i) {
3413 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3414 V->getOperand(i) != Base) {
3419 // Splat of <x, x, x, x>, return <x, x, x, x>
3426 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3428 if (isUnary || N0 == N1) {
3429 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3431 SmallVector<SDOperand, 8> MappedOps;
3432 for (unsigned i = 0; i != NumElts; ++i) {
3433 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3434 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3435 MappedOps.push_back(ShufMask.getOperand(i));
3438 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3439 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3442 // Add the type/#elts values.
3443 MappedOps.push_back(ShufMask.getOperand(NumElts));
3444 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3446 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3447 &MappedOps[0], MappedOps.size());
3448 AddToWorkList(ShufMask.Val);
3450 // Build the undef vector.
3451 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3452 for (unsigned i = 0; i != NumElts; ++i)
3453 MappedOps[i] = UDVal;
3454 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3455 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3456 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3457 &MappedOps[0], MappedOps.size());
3459 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3460 N0, UDVal, ShufMask,
3461 MappedOps[NumElts], MappedOps[NumElts+1]);
3467 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3468 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3469 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3470 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3471 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3472 SDOperand LHS = N->getOperand(0);
3473 SDOperand RHS = N->getOperand(1);
3474 if (N->getOpcode() == ISD::VAND) {
3475 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3476 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3477 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3478 RHS = RHS.getOperand(0);
3479 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3480 std::vector<SDOperand> IdxOps;
3481 unsigned NumOps = RHS.getNumOperands();
3482 unsigned NumElts = NumOps-2;
3483 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3484 for (unsigned i = 0; i != NumElts; ++i) {
3485 SDOperand Elt = RHS.getOperand(i);
3486 if (!isa<ConstantSDNode>(Elt))
3488 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3489 IdxOps.push_back(DAG.getConstant(i, EVT));
3490 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3491 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3496 // Let's see if the target supports this vector_shuffle.
3497 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3500 // Return the new VVECTOR_SHUFFLE node.
3501 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3502 SDOperand EVTNode = DAG.getValueType(EVT);
3503 std::vector<SDOperand> Ops;
3504 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3507 AddToWorkList(LHS.Val);
3508 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3509 ZeroOps.push_back(NumEltsNode);
3510 ZeroOps.push_back(EVTNode);
3511 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3512 &ZeroOps[0], ZeroOps.size()));
3513 IdxOps.push_back(NumEltsNode);
3514 IdxOps.push_back(EVTNode);
3515 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3516 &IdxOps[0], IdxOps.size()));
3517 Ops.push_back(NumEltsNode);
3518 Ops.push_back(EVTNode);
3519 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3520 &Ops[0], Ops.size());
3521 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3522 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3523 DstVecSize, DstVecEVT);
3531 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3532 /// the scalar operation of the vop if it is operating on an integer vector
3533 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3534 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3535 ISD::NodeType FPOp) {
3536 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3537 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3538 SDOperand LHS = N->getOperand(0);
3539 SDOperand RHS = N->getOperand(1);
3540 SDOperand Shuffle = XformToShuffleWithZero(N);
3541 if (Shuffle.Val) return Shuffle;
3543 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3545 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3546 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3547 SmallVector<SDOperand, 8> Ops;
3548 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3549 SDOperand LHSOp = LHS.getOperand(i);
3550 SDOperand RHSOp = RHS.getOperand(i);
3551 // If these two elements can't be folded, bail out.
3552 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3553 LHSOp.getOpcode() != ISD::Constant &&
3554 LHSOp.getOpcode() != ISD::ConstantFP) ||
3555 (RHSOp.getOpcode() != ISD::UNDEF &&
3556 RHSOp.getOpcode() != ISD::Constant &&
3557 RHSOp.getOpcode() != ISD::ConstantFP))
3559 // Can't fold divide by zero.
3560 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3561 if ((RHSOp.getOpcode() == ISD::Constant &&
3562 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3563 (RHSOp.getOpcode() == ISD::ConstantFP &&
3564 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3567 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3568 AddToWorkList(Ops.back().Val);
3569 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3570 Ops.back().getOpcode() == ISD::Constant ||
3571 Ops.back().getOpcode() == ISD::ConstantFP) &&
3572 "Scalar binop didn't fold!");
3575 if (Ops.size() == LHS.getNumOperands()-2) {
3576 Ops.push_back(*(LHS.Val->op_end()-2));
3577 Ops.push_back(*(LHS.Val->op_end()-1));
3578 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3585 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3586 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3588 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3589 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3590 // If we got a simplified select_cc node back from SimplifySelectCC, then
3591 // break it down into a new SETCC node, and a new SELECT node, and then return
3592 // the SELECT node, since we were called with a SELECT node.
3594 // Check to see if we got a select_cc back (to turn into setcc/select).
3595 // Otherwise, just return whatever node we got back, like fabs.
3596 if (SCC.getOpcode() == ISD::SELECT_CC) {
3597 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3598 SCC.getOperand(0), SCC.getOperand(1),
3600 AddToWorkList(SETCC.Val);
3601 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3602 SCC.getOperand(3), SETCC);
3609 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3610 /// are the two values being selected between, see if we can simplify the
3611 /// select. Callers of this should assume that TheSelect is deleted if this
3612 /// returns true. As such, they should return the appropriate thing (e.g. the
3613 /// node) back to the top-level of the DAG combiner loop to avoid it being
3616 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3619 // If this is a select from two identical things, try to pull the operation
3620 // through the select.
3621 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3622 // If this is a load and the token chain is identical, replace the select
3623 // of two loads with a load through a select of the address to load from.
3624 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3625 // constants have been dropped into the constant pool.
3626 if (LHS.getOpcode() == ISD::LOAD &&
3627 // Token chains must be identical.
3628 LHS.getOperand(0) == RHS.getOperand(0)) {
3629 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3630 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3632 // If this is an EXTLOAD, the VT's must match.
3633 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3634 // FIXME: this conflates two src values, discarding one. This is not
3635 // the right thing to do, but nothing uses srcvalues now. When they do,
3636 // turn SrcValue into a list of locations.
3638 if (TheSelect->getOpcode() == ISD::SELECT)
3639 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
3640 TheSelect->getOperand(0), LLD->getBasePtr(),
3643 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
3644 TheSelect->getOperand(0),
3645 TheSelect->getOperand(1),
3646 LLD->getBasePtr(), RLD->getBasePtr(),
3647 TheSelect->getOperand(4));
3650 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
3651 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
3652 Addr,LLD->getSrcValue(), LLD->getSrcValueOffset());
3654 Load = DAG.getExtLoad(LLD->getExtensionType(),
3655 TheSelect->getValueType(0),
3656 LLD->getChain(), Addr, LLD->getSrcValue(),
3657 LLD->getSrcValueOffset(),
3658 LLD->getLoadedVT());
3660 // Users of the select now use the result of the load.
3661 CombineTo(TheSelect, Load);
3663 // Users of the old loads now use the new load's chain. We know the
3664 // old-load value is dead now.
3665 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3666 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3675 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3676 SDOperand N2, SDOperand N3,
3679 MVT::ValueType VT = N2.getValueType();
3680 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3681 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3682 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3684 // Determine if the condition we're dealing with is constant
3685 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3686 if (SCC.Val) AddToWorkList(SCC.Val);
3687 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3689 // fold select_cc true, x, y -> x
3690 if (SCCC && SCCC->getValue())
3692 // fold select_cc false, x, y -> y
3693 if (SCCC && SCCC->getValue() == 0)
3696 // Check to see if we can simplify the select into an fabs node
3697 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3698 // Allow either -0.0 or 0.0
3699 if (CFP->getValue() == 0.0) {
3700 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3701 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3702 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3703 N2 == N3.getOperand(0))
3704 return DAG.getNode(ISD::FABS, VT, N0);
3706 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3707 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3708 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3709 N2.getOperand(0) == N3)
3710 return DAG.getNode(ISD::FABS, VT, N3);
3714 // Check to see if we can perform the "gzip trick", transforming
3715 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3716 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3717 MVT::isInteger(N0.getValueType()) &&
3718 MVT::isInteger(N2.getValueType()) &&
3719 (N1C->isNullValue() || // (a < 0) ? b : 0
3720 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3721 MVT::ValueType XType = N0.getValueType();
3722 MVT::ValueType AType = N2.getValueType();
3723 if (XType >= AType) {
3724 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3725 // single-bit constant.
3726 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3727 unsigned ShCtV = Log2_64(N2C->getValue());
3728 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3729 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3730 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3731 AddToWorkList(Shift.Val);
3732 if (XType > AType) {
3733 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3734 AddToWorkList(Shift.Val);
3736 return DAG.getNode(ISD::AND, AType, Shift, N2);
3738 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3739 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3740 TLI.getShiftAmountTy()));
3741 AddToWorkList(Shift.Val);
3742 if (XType > AType) {
3743 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3744 AddToWorkList(Shift.Val);
3746 return DAG.getNode(ISD::AND, AType, Shift, N2);
3750 // fold select C, 16, 0 -> shl C, 4
3751 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3752 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3753 // Get a SetCC of the condition
3754 // FIXME: Should probably make sure that setcc is legal if we ever have a
3755 // target where it isn't.
3756 SDOperand Temp, SCC;
3757 // cast from setcc result type to select result type
3758 if (AfterLegalize) {
3759 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3760 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3762 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3763 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3765 AddToWorkList(SCC.Val);
3766 AddToWorkList(Temp.Val);
3767 // shl setcc result by log2 n2c
3768 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3769 DAG.getConstant(Log2_64(N2C->getValue()),
3770 TLI.getShiftAmountTy()));
3773 // Check to see if this is the equivalent of setcc
3774 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3775 // otherwise, go ahead with the folds.
3776 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3777 MVT::ValueType XType = N0.getValueType();
3778 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3779 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3780 if (Res.getValueType() != VT)
3781 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3785 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3786 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3787 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3788 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3789 return DAG.getNode(ISD::SRL, XType, Ctlz,
3790 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3791 TLI.getShiftAmountTy()));
3793 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3794 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3795 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3797 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3798 DAG.getConstant(~0ULL, XType));
3799 return DAG.getNode(ISD::SRL, XType,
3800 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3801 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3802 TLI.getShiftAmountTy()));
3804 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3805 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3806 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3807 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3808 TLI.getShiftAmountTy()));
3809 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3813 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3814 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3815 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3816 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3817 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3818 MVT::ValueType XType = N0.getValueType();
3819 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3820 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3821 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3822 TLI.getShiftAmountTy()));
3823 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3824 AddToWorkList(Shift.Val);
3825 AddToWorkList(Add.Val);
3826 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3834 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3835 SDOperand N1, ISD::CondCode Cond,
3836 bool foldBooleans) {
3837 // These setcc operations always fold.
3841 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3843 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3846 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3847 uint64_t C1 = N1C->getValue();
3848 if (isa<ConstantSDNode>(N0.Val)) {
3849 return DAG.FoldSetCC(VT, N0, N1, Cond);
3851 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3852 // equality comparison, then we're just comparing whether X itself is
3854 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
3855 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3856 N0.getOperand(1).getOpcode() == ISD::Constant) {
3857 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
3858 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3859 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
3860 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3861 // (srl (ctlz x), 5) == 0 -> X != 0
3862 // (srl (ctlz x), 5) != 1 -> X != 0
3865 // (srl (ctlz x), 5) != 0 -> X == 0
3866 // (srl (ctlz x), 5) == 1 -> X == 0
3869 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
3870 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
3875 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3876 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3877 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3879 // If the comparison constant has bits in the upper part, the
3880 // zero-extended value could never match.
3881 if (C1 & (~0ULL << InSize)) {
3882 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3886 case ISD::SETEQ: return DAG.getConstant(0, VT);
3889 case ISD::SETNE: return DAG.getConstant(1, VT);
3892 // True if the sign bit of C1 is set.
3893 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3896 // True if the sign bit of C1 isn't set.
3897 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3903 // Otherwise, we can perform the comparison with the low bits.
3911 return DAG.getSetCC(VT, N0.getOperand(0),
3912 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3915 break; // todo, be more careful with signed comparisons
3917 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3918 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3919 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3920 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3921 MVT::ValueType ExtDstTy = N0.getValueType();
3922 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3924 // If the extended part has any inconsistent bits, it cannot ever
3925 // compare equal. In other words, they have to be all ones or all
3928 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3929 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3930 return DAG.getConstant(Cond == ISD::SETNE, VT);
3933 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3934 if (Op0Ty == ExtSrcTy) {
3935 ZextOp = N0.getOperand(0);
3937 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3938 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3939 DAG.getConstant(Imm, Op0Ty));
3941 AddToWorkList(ZextOp.Val);
3942 // Otherwise, make this a use of a zext.
3943 return DAG.getSetCC(VT, ZextOp,
3944 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3947 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3948 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3950 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
3951 if (N0.getOpcode() == ISD::SETCC) {
3952 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
3956 // Invert the condition.
3957 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
3958 CC = ISD::getSetCCInverse(CC,
3959 MVT::isInteger(N0.getOperand(0).getValueType()));
3960 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
3963 if ((N0.getOpcode() == ISD::XOR ||
3964 (N0.getOpcode() == ISD::AND &&
3965 N0.getOperand(0).getOpcode() == ISD::XOR &&
3966 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3967 isa<ConstantSDNode>(N0.getOperand(1)) &&
3968 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3969 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
3970 // can only do this if the top bits are known zero.
3971 if (TLI.MaskedValueIsZero(N0,
3972 MVT::getIntVTBitMask(N0.getValueType())-1)){
3973 // Okay, get the un-inverted input value.
3975 if (N0.getOpcode() == ISD::XOR)
3976 Val = N0.getOperand(0);
3978 assert(N0.getOpcode() == ISD::AND &&
3979 N0.getOperand(0).getOpcode() == ISD::XOR);
3980 // ((X^1)&1)^1 -> X & 1
3981 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3982 N0.getOperand(0).getOperand(0),
3985 return DAG.getSetCC(VT, Val, N1,
3986 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3991 uint64_t MinVal, MaxVal;
3992 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3993 if (ISD::isSignedIntSetCC(Cond)) {
3994 MinVal = 1ULL << (OperandBitSize-1);
3995 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3996 MaxVal = ~0ULL >> (65-OperandBitSize);
4001 MaxVal = ~0ULL >> (64-OperandBitSize);
4004 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
4005 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
4006 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
4007 --C1; // X >= C0 --> X > (C0-1)
4008 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
4009 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
4012 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
4013 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
4014 ++C1; // X <= C0 --> X < (C0+1)
4015 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
4016 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
4019 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
4020 return DAG.getConstant(0, VT); // X < MIN --> false
4022 // Canonicalize setgt X, Min --> setne X, Min
4023 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
4024 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
4025 // Canonicalize setlt X, Max --> setne X, Max
4026 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
4027 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
4029 // If we have setult X, 1, turn it into seteq X, 0
4030 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
4031 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
4033 // If we have setugt X, Max-1, turn it into seteq X, Max
4034 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
4035 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
4038 // If we have "setcc X, C0", check to see if we can shrink the immediate
4041 // SETUGT X, SINTMAX -> SETLT X, 0
4042 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
4043 C1 == (~0ULL >> (65-OperandBitSize)))
4044 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
4047 // FIXME: Implement the rest of these.
4049 // Fold bit comparisons when we can.
4050 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
4051 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
4052 if (ConstantSDNode *AndRHS =
4053 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4054 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
4055 // Perform the xform if the AND RHS is a single bit.
4056 if (isPowerOf2_64(AndRHS->getValue())) {
4057 return DAG.getNode(ISD::SRL, VT, N0,
4058 DAG.getConstant(Log2_64(AndRHS->getValue()),
4059 TLI.getShiftAmountTy()));
4061 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
4062 // (X & 8) == 8 --> (X & 8) >> 3
4063 // Perform the xform if C1 is a single bit.
4064 if (isPowerOf2_64(C1)) {
4065 return DAG.getNode(ISD::SRL, VT, N0,
4066 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
4071 } else if (isa<ConstantSDNode>(N0.Val)) {
4072 // Ensure that the constant occurs on the RHS.
4073 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
4076 if (isa<ConstantFPSDNode>(N0.Val)) {
4077 // Constant fold or commute setcc.
4078 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
4079 if (O.Val) return O;
4083 // We can always fold X == X for integer setcc's.
4084 if (MVT::isInteger(N0.getValueType()))
4085 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
4086 unsigned UOF = ISD::getUnorderedFlavor(Cond);
4087 if (UOF == 2) // FP operators that are undefined on NaNs.
4088 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
4089 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
4090 return DAG.getConstant(UOF, VT);
4091 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
4092 // if it is not already.
4093 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
4094 if (NewCond != Cond)
4095 return DAG.getSetCC(VT, N0, N1, NewCond);
4098 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
4099 MVT::isInteger(N0.getValueType())) {
4100 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
4101 N0.getOpcode() == ISD::XOR) {
4102 // Simplify (X+Y) == (X+Z) --> Y == Z
4103 if (N0.getOpcode() == N1.getOpcode()) {
4104 if (N0.getOperand(0) == N1.getOperand(0))
4105 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
4106 if (N0.getOperand(1) == N1.getOperand(1))
4107 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
4108 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
4109 // If X op Y == Y op X, try other combinations.
4110 if (N0.getOperand(0) == N1.getOperand(1))
4111 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
4112 if (N0.getOperand(1) == N1.getOperand(0))
4113 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
4117 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
4118 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4119 // Turn (X+C1) == C2 --> X == C2-C1
4120 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
4121 return DAG.getSetCC(VT, N0.getOperand(0),
4122 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
4123 N0.getValueType()), Cond);
4126 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
4127 if (N0.getOpcode() == ISD::XOR)
4128 // If we know that all of the inverted bits are zero, don't bother
4129 // performing the inversion.
4130 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
4131 return DAG.getSetCC(VT, N0.getOperand(0),
4132 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
4133 N0.getValueType()), Cond);
4136 // Turn (C1-X) == C2 --> X == C1-C2
4137 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
4138 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
4139 return DAG.getSetCC(VT, N0.getOperand(1),
4140 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
4141 N0.getValueType()), Cond);
4146 // Simplify (X+Z) == X --> Z == 0
4147 if (N0.getOperand(0) == N1)
4148 return DAG.getSetCC(VT, N0.getOperand(1),
4149 DAG.getConstant(0, N0.getValueType()), Cond);
4150 if (N0.getOperand(1) == N1) {
4151 if (DAG.isCommutativeBinOp(N0.getOpcode()))
4152 return DAG.getSetCC(VT, N0.getOperand(0),
4153 DAG.getConstant(0, N0.getValueType()), Cond);
4155 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
4156 // (Z-X) == X --> Z == X<<1
4157 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
4159 DAG.getConstant(1,TLI.getShiftAmountTy()));
4160 AddToWorkList(SH.Val);
4161 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
4166 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
4167 N1.getOpcode() == ISD::XOR) {
4168 // Simplify X == (X+Z) --> Z == 0
4169 if (N1.getOperand(0) == N0) {
4170 return DAG.getSetCC(VT, N1.getOperand(1),
4171 DAG.getConstant(0, N1.getValueType()), Cond);
4172 } else if (N1.getOperand(1) == N0) {
4173 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
4174 return DAG.getSetCC(VT, N1.getOperand(0),
4175 DAG.getConstant(0, N1.getValueType()), Cond);
4177 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
4178 // X == (Z-X) --> X<<1 == Z
4179 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
4180 DAG.getConstant(1,TLI.getShiftAmountTy()));
4181 AddToWorkList(SH.Val);
4182 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
4188 // Fold away ALL boolean setcc's.
4190 if (N0.getValueType() == MVT::i1 && foldBooleans) {
4192 default: assert(0 && "Unknown integer setcc!");
4193 case ISD::SETEQ: // X == Y -> (X^Y)^1
4194 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
4195 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
4196 AddToWorkList(Temp.Val);
4198 case ISD::SETNE: // X != Y --> (X^Y)
4199 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
4201 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
4202 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
4203 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
4204 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
4205 AddToWorkList(Temp.Val);
4207 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
4208 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
4209 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
4210 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
4211 AddToWorkList(Temp.Val);
4213 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
4214 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
4215 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
4216 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
4217 AddToWorkList(Temp.Val);
4219 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
4220 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
4221 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
4222 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
4225 if (VT != MVT::i1) {
4226 AddToWorkList(N0.Val);
4227 // FIXME: If running after legalize, we probably can't do this.
4228 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
4233 // Could not fold it.
4237 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4238 /// return a DAG expression to select that will generate the same value by
4239 /// multiplying by a magic number. See:
4240 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4241 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4242 std::vector<SDNode*> Built;
4243 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4245 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4251 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4252 /// return a DAG expression to select that will generate the same value by
4253 /// multiplying by a magic number. See:
4254 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4255 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4256 std::vector<SDNode*> Built;
4257 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4259 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4265 /// FindBaseOffset - Return true if base is known not to alias with anything
4266 /// but itself. Provides base object and offset as results.
4267 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4268 // Assume it is a primitive operation.
4269 Base = Ptr; Offset = 0;
4271 // If it's an adding a simple constant then integrate the offset.
4272 if (Base.getOpcode() == ISD::ADD) {
4273 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4274 Base = Base.getOperand(0);
4275 Offset += C->getValue();
4279 // If it's any of the following then it can't alias with anything but itself.
4280 return isa<FrameIndexSDNode>(Base) ||
4281 isa<ConstantPoolSDNode>(Base) ||
4282 isa<GlobalAddressSDNode>(Base);
4285 /// isAlias - Return true if there is any possibility that the two addresses
4287 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4288 const Value *SrcValue1, int SrcValueOffset1,
4289 SDOperand Ptr2, int64_t Size2,
4290 const Value *SrcValue2, int SrcValueOffset2)
4292 // If they are the same then they must be aliases.
4293 if (Ptr1 == Ptr2) return true;
4295 // Gather base node and offset information.
4296 SDOperand Base1, Base2;
4297 int64_t Offset1, Offset2;
4298 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4299 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4301 // If they have a same base address then...
4302 if (Base1 == Base2) {
4303 // Check to see if the addresses overlap.
4304 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4307 // If we know both bases then they can't alias.
4308 if (KnownBase1 && KnownBase2) return false;
4310 if (CombinerGlobalAA) {
4311 // Use alias analysis information.
4312 int Overlap1 = Size1 + SrcValueOffset1 + Offset1;
4313 int Overlap2 = Size2 + SrcValueOffset2 + Offset2;
4314 AliasAnalysis::AliasResult AAResult =
4315 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4316 if (AAResult == AliasAnalysis::NoAlias)
4320 // Otherwise we have to assume they alias.
4324 /// FindAliasInfo - Extracts the relevant alias information from the memory
4325 /// node. Returns true if the operand was a load.
4326 bool DAGCombiner::FindAliasInfo(SDNode *N,
4327 SDOperand &Ptr, int64_t &Size,
4328 const Value *&SrcValue, int &SrcValueOffset) {
4329 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4330 Ptr = LD->getBasePtr();
4331 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4332 SrcValue = LD->getSrcValue();
4333 SrcValueOffset = LD->getSrcValueOffset();
4335 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4336 Ptr = ST->getBasePtr();
4337 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4338 SrcValue = ST->getSrcValue();
4339 SrcValueOffset = ST->getSrcValueOffset();
4341 assert(0 && "FindAliasInfo expected a memory operand");
4347 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4348 /// looking for aliasing nodes and adding them to the Aliases vector.
4349 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4350 SmallVector<SDOperand, 8> &Aliases) {
4351 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4352 std::set<SDNode *> Visited; // Visited node set.
4354 // Get alias information for node.
4357 const Value *SrcValue;
4359 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4362 Chains.push_back(OriginalChain);
4364 // Look at each chain and determine if it is an alias. If so, add it to the
4365 // aliases list. If not, then continue up the chain looking for the next
4367 while (!Chains.empty()) {
4368 SDOperand Chain = Chains.back();
4371 // Don't bother if we've been before.
4372 if (Visited.find(Chain.Val) != Visited.end()) continue;
4373 Visited.insert(Chain.Val);
4375 switch (Chain.getOpcode()) {
4376 case ISD::EntryToken:
4377 // Entry token is ideal chain operand, but handled in FindBetterChain.
4382 // Get alias information for Chain.
4385 const Value *OpSrcValue;
4386 int OpSrcValueOffset;
4387 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4388 OpSrcValue, OpSrcValueOffset);
4390 // If chain is alias then stop here.
4391 if (!(IsLoad && IsOpLoad) &&
4392 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4393 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4394 Aliases.push_back(Chain);
4396 // Look further up the chain.
4397 Chains.push_back(Chain.getOperand(0));
4398 // Clean up old chain.
4399 AddToWorkList(Chain.Val);
4404 case ISD::TokenFactor:
4405 // We have to check each of the operands of the token factor, so we queue
4406 // then up. Adding the operands to the queue (stack) in reverse order
4407 // maintains the original order and increases the likelihood that getNode
4408 // will find a matching token factor (CSE.)
4409 for (unsigned n = Chain.getNumOperands(); n;)
4410 Chains.push_back(Chain.getOperand(--n));
4411 // Eliminate the token factor if we can.
4412 AddToWorkList(Chain.Val);
4416 // For all other instructions we will just have to take what we can get.
4417 Aliases.push_back(Chain);
4423 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4424 /// for a better chain (aliasing node.)
4425 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4426 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4428 // Accumulate all the aliases to this node.
4429 GatherAllAliases(N, OldChain, Aliases);
4431 if (Aliases.size() == 0) {
4432 // If no operands then chain to entry token.
4433 return DAG.getEntryNode();
4434 } else if (Aliases.size() == 1) {
4435 // If a single operand then chain to it. We don't need to revisit it.
4439 // Construct a custom tailored token factor.
4440 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4441 &Aliases[0], Aliases.size());
4443 // Make sure the old chain gets cleaned up.
4444 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4449 // SelectionDAG::Combine - This is the entry point for the file.
4451 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4452 /// run - This is the main entry point to this class.
4454 DAGCombiner(*this, AA).Run(RunningAfterLegalize);