1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/Support/Compiler.h"
40 #include "llvm/Support/CommandLine.h"
44 STATISTIC(NodesCombined , "Number of dag nodes combined");
45 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
46 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
51 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
52 cl::desc("Pop up a window to show dags before the first "
55 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
56 cl::desc("Pop up a window to show dags before the second "
59 static const bool ViewDAGCombine1 = false;
60 static const bool ViewDAGCombine2 = false;
64 CombinerAA("combiner-alias-analysis", cl::Hidden,
65 cl::desc("Turn on alias analysis during testing"));
68 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
69 cl::desc("Include global information in alias analysis"));
71 //------------------------------ DAGCombiner ---------------------------------//
73 class VISIBILITY_HIDDEN DAGCombiner {
78 // Worklist of all of the nodes that need to be simplified.
79 std::vector<SDNode*> WorkList;
81 // AA - Used for DAG load/store alias analysis.
84 /// AddUsersToWorkList - When an instruction is simplified, add all users of
85 /// the instruction to the work lists because they might get more simplified
88 void AddUsersToWorkList(SDNode *N) {
89 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
102 /// AddToWorkList - Add to the work list making sure it's instance is at the
103 /// the back (next to be processed.)
104 void AddToWorkList(SDNode *N) {
105 removeFromWorkList(N);
106 WorkList.push_back(N);
109 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
111 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
113 DOUT << "\nReplacing.1 "; DEBUG(N->dump());
114 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
115 DOUT << " and " << NumTo-1 << " other values\n";
116 std::vector<SDNode*> NowDead;
117 DAG.ReplaceAllUsesWith(N, To, &NowDead);
120 // Push the new nodes and any users onto the worklist
121 for (unsigned i = 0, e = NumTo; i != e; ++i) {
122 AddToWorkList(To[i].Val);
123 AddUsersToWorkList(To[i].Val);
127 // Nodes can be reintroduced into the worklist. Make sure we do not
128 // process a node that has been replaced.
129 removeFromWorkList(N);
130 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
131 removeFromWorkList(NowDead[i]);
133 // Finally, since the node is now dead, remove it from the graph.
135 return SDOperand(N, 0);
138 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
139 return CombineTo(N, &Res, 1, AddTo);
142 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
144 SDOperand To[] = { Res0, Res1 };
145 return CombineTo(N, To, 2, AddTo);
149 /// SimplifyDemandedBits - Check the specified integer node value to see if
150 /// it can be simplified or if things it uses can be simplified by bit
151 /// propagation. If so, return true.
152 bool SimplifyDemandedBits(SDOperand Op) {
153 TargetLowering::TargetLoweringOpt TLO(DAG);
154 uint64_t KnownZero, KnownOne;
155 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
156 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
160 AddToWorkList(Op.Val);
162 // Replace the old value with the new one.
164 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump());
165 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
168 std::vector<SDNode*> NowDead;
169 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
171 // Push the new node and any (possibly new) users onto the worklist.
172 AddToWorkList(TLO.New.Val);
173 AddUsersToWorkList(TLO.New.Val);
175 // Nodes can end up on the worklist more than once. Make sure we do
176 // not process a node that has been replaced.
177 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
178 removeFromWorkList(NowDead[i]);
180 // Finally, if the node is now dead, remove it from the graph. The node
181 // may not be dead if the replacement process recursively simplified to
182 // something else needing this node.
183 if (TLO.Old.Val->use_empty()) {
184 removeFromWorkList(TLO.Old.Val);
185 DAG.DeleteNode(TLO.Old.Val);
190 bool CombineToPreIndexedLoadStore(SDNode *N);
191 bool CombineToPostIndexedLoadStore(SDNode *N);
194 /// visit - call the node-specific routine that knows how to fold each
195 /// particular type of node.
196 SDOperand visit(SDNode *N);
198 // Visitation implementation - Implement dag node combining for different
199 // node types. The semantics are as follows:
201 // SDOperand.Val == 0 - No change was made
202 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
203 // otherwise - N should be replaced by the returned Operand.
205 SDOperand visitTokenFactor(SDNode *N);
206 SDOperand visitADD(SDNode *N);
207 SDOperand visitSUB(SDNode *N);
208 SDOperand visitADDC(SDNode *N);
209 SDOperand visitADDE(SDNode *N);
210 SDOperand visitMUL(SDNode *N);
211 SDOperand visitSDIV(SDNode *N);
212 SDOperand visitUDIV(SDNode *N);
213 SDOperand visitSREM(SDNode *N);
214 SDOperand visitUREM(SDNode *N);
215 SDOperand visitMULHU(SDNode *N);
216 SDOperand visitMULHS(SDNode *N);
217 SDOperand visitAND(SDNode *N);
218 SDOperand visitOR(SDNode *N);
219 SDOperand visitXOR(SDNode *N);
220 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
221 SDOperand visitSHL(SDNode *N);
222 SDOperand visitSRA(SDNode *N);
223 SDOperand visitSRL(SDNode *N);
224 SDOperand visitCTLZ(SDNode *N);
225 SDOperand visitCTTZ(SDNode *N);
226 SDOperand visitCTPOP(SDNode *N);
227 SDOperand visitSELECT(SDNode *N);
228 SDOperand visitSELECT_CC(SDNode *N);
229 SDOperand visitSETCC(SDNode *N);
230 SDOperand visitSIGN_EXTEND(SDNode *N);
231 SDOperand visitZERO_EXTEND(SDNode *N);
232 SDOperand visitANY_EXTEND(SDNode *N);
233 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
234 SDOperand visitTRUNCATE(SDNode *N);
235 SDOperand visitBIT_CONVERT(SDNode *N);
236 SDOperand visitVBIT_CONVERT(SDNode *N);
237 SDOperand visitFADD(SDNode *N);
238 SDOperand visitFSUB(SDNode *N);
239 SDOperand visitFMUL(SDNode *N);
240 SDOperand visitFDIV(SDNode *N);
241 SDOperand visitFREM(SDNode *N);
242 SDOperand visitFCOPYSIGN(SDNode *N);
243 SDOperand visitSINT_TO_FP(SDNode *N);
244 SDOperand visitUINT_TO_FP(SDNode *N);
245 SDOperand visitFP_TO_SINT(SDNode *N);
246 SDOperand visitFP_TO_UINT(SDNode *N);
247 SDOperand visitFP_ROUND(SDNode *N);
248 SDOperand visitFP_ROUND_INREG(SDNode *N);
249 SDOperand visitFP_EXTEND(SDNode *N);
250 SDOperand visitFNEG(SDNode *N);
251 SDOperand visitFABS(SDNode *N);
252 SDOperand visitBRCOND(SDNode *N);
253 SDOperand visitBR_CC(SDNode *N);
254 SDOperand visitLOAD(SDNode *N);
255 SDOperand visitSTORE(SDNode *N);
256 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
257 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
258 SDOperand visitVBUILD_VECTOR(SDNode *N);
259 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
260 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
262 SDOperand XformToShuffleWithZero(SDNode *N);
263 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
265 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
266 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
267 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
268 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
269 SDOperand N3, ISD::CondCode CC);
270 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
271 ISD::CondCode Cond, bool foldBooleans = true);
272 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
273 SDOperand BuildSDIV(SDNode *N);
274 SDOperand BuildUDIV(SDNode *N);
275 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
277 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
278 /// looking for aliasing nodes and adding them to the Aliases vector.
279 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
280 SmallVector<SDOperand, 8> &Aliases);
282 /// isAlias - Return true if there is any possibility that the two addresses
284 bool isAlias(SDOperand Ptr1, int64_t Size1,
285 const Value *SrcValue1, int SrcValueOffset1,
286 SDOperand Ptr2, int64_t Size2,
287 const Value *SrcValue2, int SrcValueOffset2);
289 /// FindAliasInfo - Extracts the relevant alias information from the memory
290 /// node. Returns true if the operand was a load.
291 bool FindAliasInfo(SDNode *N,
292 SDOperand &Ptr, int64_t &Size,
293 const Value *&SrcValue, int &SrcValueOffset);
295 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
296 /// looking for a better chain (aliasing node.)
297 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
300 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
302 TLI(D.getTargetLoweringInfo()),
303 AfterLegalize(false),
306 /// Run - runs the dag combiner on all nodes in the work list
307 void Run(bool RunningAfterLegalize);
311 //===----------------------------------------------------------------------===//
312 // TargetLowering::DAGCombinerInfo implementation
313 //===----------------------------------------------------------------------===//
315 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
316 ((DAGCombiner*)DC)->AddToWorkList(N);
319 SDOperand TargetLowering::DAGCombinerInfo::
320 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
321 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
324 SDOperand TargetLowering::DAGCombinerInfo::
325 CombineTo(SDNode *N, SDOperand Res) {
326 return ((DAGCombiner*)DC)->CombineTo(N, Res);
330 SDOperand TargetLowering::DAGCombinerInfo::
331 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
332 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
338 //===----------------------------------------------------------------------===//
341 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
342 // that selects between the values 1 and 0, making it equivalent to a setcc.
343 // Also, set the incoming LHS, RHS, and CC references to the appropriate
344 // nodes based on the type of node we are checking. This simplifies life a
345 // bit for the callers.
346 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
348 if (N.getOpcode() == ISD::SETCC) {
349 LHS = N.getOperand(0);
350 RHS = N.getOperand(1);
351 CC = N.getOperand(2);
354 if (N.getOpcode() == ISD::SELECT_CC &&
355 N.getOperand(2).getOpcode() == ISD::Constant &&
356 N.getOperand(3).getOpcode() == ISD::Constant &&
357 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
358 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
359 LHS = N.getOperand(0);
360 RHS = N.getOperand(1);
361 CC = N.getOperand(4);
367 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
368 // one use. If this is true, it allows the users to invert the operation for
369 // free when it is profitable to do so.
370 static bool isOneUseSetCC(SDOperand N) {
371 SDOperand N0, N1, N2;
372 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
377 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
378 MVT::ValueType VT = N0.getValueType();
379 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
380 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
381 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
382 if (isa<ConstantSDNode>(N1)) {
383 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
384 AddToWorkList(OpNode.Val);
385 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
386 } else if (N0.hasOneUse()) {
387 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
388 AddToWorkList(OpNode.Val);
389 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
392 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
393 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
394 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
395 if (isa<ConstantSDNode>(N0)) {
396 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
397 AddToWorkList(OpNode.Val);
398 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
399 } else if (N1.hasOneUse()) {
400 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
401 AddToWorkList(OpNode.Val);
402 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
408 void DAGCombiner::Run(bool RunningAfterLegalize) {
409 // set the instance variable, so that the various visit routines may use it.
410 AfterLegalize = RunningAfterLegalize;
412 // Add all the dag nodes to the worklist.
413 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
414 E = DAG.allnodes_end(); I != E; ++I)
415 WorkList.push_back(I);
417 // Create a dummy node (which is not added to allnodes), that adds a reference
418 // to the root node, preventing it from being deleted, and tracking any
419 // changes of the root.
420 HandleSDNode Dummy(DAG.getRoot());
422 // The root of the dag may dangle to deleted nodes until the dag combiner is
423 // done. Set it to null to avoid confusion.
424 DAG.setRoot(SDOperand());
426 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
427 TargetLowering::DAGCombinerInfo
428 DagCombineInfo(DAG, !RunningAfterLegalize, false, this);
430 // while the worklist isn't empty, inspect the node on the end of it and
431 // try and combine it.
432 while (!WorkList.empty()) {
433 SDNode *N = WorkList.back();
436 // If N has no uses, it is dead. Make sure to revisit all N's operands once
437 // N is deleted from the DAG, since they too may now be dead or may have a
438 // reduced number of uses, allowing other xforms.
439 if (N->use_empty() && N != &Dummy) {
440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
441 AddToWorkList(N->getOperand(i).Val);
447 SDOperand RV = visit(N);
449 // If nothing happened, try a target-specific DAG combine.
451 assert(N->getOpcode() != ISD::DELETED_NODE &&
452 "Node was deleted but visit returned NULL!");
453 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
454 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
455 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
460 // If we get back the same node we passed in, rather than a new node or
461 // zero, we know that the node must have defined multiple values and
462 // CombineTo was used. Since CombineTo takes care of the worklist
463 // mechanics for us, we have no work to do in this case.
465 assert(N->getOpcode() != ISD::DELETED_NODE &&
466 RV.Val->getOpcode() != ISD::DELETED_NODE &&
467 "Node was deleted but visit returned new node!");
469 DOUT << "\nReplacing.3 "; DEBUG(N->dump());
470 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
472 std::vector<SDNode*> NowDead;
473 if (N->getNumValues() == RV.Val->getNumValues())
474 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
476 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
478 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
481 // Push the new node and any users onto the worklist
482 AddToWorkList(RV.Val);
483 AddUsersToWorkList(RV.Val);
485 // Nodes can be reintroduced into the worklist. Make sure we do not
486 // process a node that has been replaced.
487 removeFromWorkList(N);
488 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
489 removeFromWorkList(NowDead[i]);
491 // Finally, since the node is now dead, remove it from the graph.
497 // If the root changed (e.g. it was a dead load, update the root).
498 DAG.setRoot(Dummy.getValue());
501 SDOperand DAGCombiner::visit(SDNode *N) {
502 switch(N->getOpcode()) {
504 case ISD::TokenFactor: return visitTokenFactor(N);
505 case ISD::ADD: return visitADD(N);
506 case ISD::SUB: return visitSUB(N);
507 case ISD::ADDC: return visitADDC(N);
508 case ISD::ADDE: return visitADDE(N);
509 case ISD::MUL: return visitMUL(N);
510 case ISD::SDIV: return visitSDIV(N);
511 case ISD::UDIV: return visitUDIV(N);
512 case ISD::SREM: return visitSREM(N);
513 case ISD::UREM: return visitUREM(N);
514 case ISD::MULHU: return visitMULHU(N);
515 case ISD::MULHS: return visitMULHS(N);
516 case ISD::AND: return visitAND(N);
517 case ISD::OR: return visitOR(N);
518 case ISD::XOR: return visitXOR(N);
519 case ISD::SHL: return visitSHL(N);
520 case ISD::SRA: return visitSRA(N);
521 case ISD::SRL: return visitSRL(N);
522 case ISD::CTLZ: return visitCTLZ(N);
523 case ISD::CTTZ: return visitCTTZ(N);
524 case ISD::CTPOP: return visitCTPOP(N);
525 case ISD::SELECT: return visitSELECT(N);
526 case ISD::SELECT_CC: return visitSELECT_CC(N);
527 case ISD::SETCC: return visitSETCC(N);
528 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
529 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
530 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
531 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
532 case ISD::TRUNCATE: return visitTRUNCATE(N);
533 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
534 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
535 case ISD::FADD: return visitFADD(N);
536 case ISD::FSUB: return visitFSUB(N);
537 case ISD::FMUL: return visitFMUL(N);
538 case ISD::FDIV: return visitFDIV(N);
539 case ISD::FREM: return visitFREM(N);
540 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
541 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
542 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
543 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
544 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
545 case ISD::FP_ROUND: return visitFP_ROUND(N);
546 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
547 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
548 case ISD::FNEG: return visitFNEG(N);
549 case ISD::FABS: return visitFABS(N);
550 case ISD::BRCOND: return visitBRCOND(N);
551 case ISD::BR_CC: return visitBR_CC(N);
552 case ISD::LOAD: return visitLOAD(N);
553 case ISD::STORE: return visitSTORE(N);
554 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
555 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
556 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
557 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
558 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
559 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
560 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
561 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
562 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
563 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
564 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
565 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
566 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
571 /// getInputChainForNode - Given a node, return its input chain if it has one,
572 /// otherwise return a null sd operand.
573 static SDOperand getInputChainForNode(SDNode *N) {
574 if (unsigned NumOps = N->getNumOperands()) {
575 if (N->getOperand(0).getValueType() == MVT::Other)
576 return N->getOperand(0);
577 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
578 return N->getOperand(NumOps-1);
579 for (unsigned i = 1; i < NumOps-1; ++i)
580 if (N->getOperand(i).getValueType() == MVT::Other)
581 return N->getOperand(i);
583 return SDOperand(0, 0);
586 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
587 // If N has two operands, where one has an input chain equal to the other,
588 // the 'other' chain is redundant.
589 if (N->getNumOperands() == 2) {
590 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
591 return N->getOperand(0);
592 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
593 return N->getOperand(1);
597 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
598 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
599 bool Changed = false; // If we should replace this token factor.
601 // Start out with this token factor.
604 // Iterate through token factors. The TFs grows when new token factors are
606 for (unsigned i = 0; i < TFs.size(); ++i) {
609 // Check each of the operands.
610 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
611 SDOperand Op = TF->getOperand(i);
613 switch (Op.getOpcode()) {
614 case ISD::EntryToken:
615 // Entry tokens don't need to be added to the list. They are
620 case ISD::TokenFactor:
621 if ((CombinerAA || Op.hasOneUse()) &&
622 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
623 // Queue up for processing.
624 TFs.push_back(Op.Val);
625 // Clean up in case the token factor is removed.
626 AddToWorkList(Op.Val);
633 // Only add if not there prior.
634 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
643 // If we've change things around then replace token factor.
645 if (Ops.size() == 0) {
646 // The entry token is the only possible outcome.
647 Result = DAG.getEntryNode();
649 // New and improved token factor.
650 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
653 // Don't add users to work list.
654 return CombineTo(N, Result, false);
661 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
662 MVT::ValueType VT = N0.getValueType();
663 SDOperand N00 = N0.getOperand(0);
664 SDOperand N01 = N0.getOperand(1);
665 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
666 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
667 isa<ConstantSDNode>(N00.getOperand(1))) {
668 N0 = DAG.getNode(ISD::ADD, VT,
669 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
670 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
671 return DAG.getNode(ISD::ADD, VT, N0, N1);
676 SDOperand DAGCombiner::visitADD(SDNode *N) {
677 SDOperand N0 = N->getOperand(0);
678 SDOperand N1 = N->getOperand(1);
679 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
680 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
681 MVT::ValueType VT = N0.getValueType();
683 // fold (add c1, c2) -> c1+c2
685 return DAG.getNode(ISD::ADD, VT, N0, N1);
686 // canonicalize constant to RHS
688 return DAG.getNode(ISD::ADD, VT, N1, N0);
689 // fold (add x, 0) -> x
690 if (N1C && N1C->isNullValue())
692 // fold ((c1-A)+c2) -> (c1+c2)-A
693 if (N1C && N0.getOpcode() == ISD::SUB)
694 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
695 return DAG.getNode(ISD::SUB, VT,
696 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
699 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
702 // fold ((0-A) + B) -> B-A
703 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
704 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
705 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
706 // fold (A + (0-B)) -> A-B
707 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
708 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
709 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
710 // fold (A+(B-A)) -> B
711 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
712 return N1.getOperand(0);
714 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
715 return SDOperand(N, 0);
717 // fold (a+b) -> (a|b) iff a and b share no bits.
718 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
719 uint64_t LHSZero, LHSOne;
720 uint64_t RHSZero, RHSOne;
721 uint64_t Mask = MVT::getIntVTBitMask(VT);
722 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
724 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
726 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
727 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
728 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
729 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
730 return DAG.getNode(ISD::OR, VT, N0, N1);
734 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
735 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
736 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
737 if (Result.Val) return Result;
739 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
740 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
741 if (Result.Val) return Result;
747 SDOperand DAGCombiner::visitADDC(SDNode *N) {
748 SDOperand N0 = N->getOperand(0);
749 SDOperand N1 = N->getOperand(1);
750 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
751 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
752 MVT::ValueType VT = N0.getValueType();
754 // If the flag result is dead, turn this into an ADD.
755 if (N->hasNUsesOfValue(0, 1))
756 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
757 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
759 // canonicalize constant to RHS.
761 SDOperand Ops[] = { N1, N0 };
762 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
765 // fold (addc x, 0) -> x + no carry out
766 if (N1C && N1C->isNullValue())
767 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
769 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
770 uint64_t LHSZero, LHSOne;
771 uint64_t RHSZero, RHSOne;
772 uint64_t Mask = MVT::getIntVTBitMask(VT);
773 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
775 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
777 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
778 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
779 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
780 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
781 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
782 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
788 SDOperand DAGCombiner::visitADDE(SDNode *N) {
789 SDOperand N0 = N->getOperand(0);
790 SDOperand N1 = N->getOperand(1);
791 SDOperand CarryIn = N->getOperand(2);
792 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
793 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
794 //MVT::ValueType VT = N0.getValueType();
796 // canonicalize constant to RHS
798 SDOperand Ops[] = { N1, N0, CarryIn };
799 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
802 // fold (adde x, y, false) -> (addc x, y)
803 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
804 SDOperand Ops[] = { N1, N0 };
805 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
813 SDOperand DAGCombiner::visitSUB(SDNode *N) {
814 SDOperand N0 = N->getOperand(0);
815 SDOperand N1 = N->getOperand(1);
816 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
817 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
818 MVT::ValueType VT = N0.getValueType();
820 // fold (sub x, x) -> 0
822 return DAG.getConstant(0, N->getValueType(0));
823 // fold (sub c1, c2) -> c1-c2
825 return DAG.getNode(ISD::SUB, VT, N0, N1);
826 // fold (sub x, c) -> (add x, -c)
828 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
830 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
831 return N0.getOperand(1);
833 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
834 return N0.getOperand(0);
838 SDOperand DAGCombiner::visitMUL(SDNode *N) {
839 SDOperand N0 = N->getOperand(0);
840 SDOperand N1 = N->getOperand(1);
841 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
842 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
843 MVT::ValueType VT = N0.getValueType();
845 // fold (mul c1, c2) -> c1*c2
847 return DAG.getNode(ISD::MUL, VT, N0, N1);
848 // canonicalize constant to RHS
850 return DAG.getNode(ISD::MUL, VT, N1, N0);
851 // fold (mul x, 0) -> 0
852 if (N1C && N1C->isNullValue())
854 // fold (mul x, -1) -> 0-x
855 if (N1C && N1C->isAllOnesValue())
856 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
857 // fold (mul x, (1 << c)) -> x << c
858 if (N1C && isPowerOf2_64(N1C->getValue()))
859 return DAG.getNode(ISD::SHL, VT, N0,
860 DAG.getConstant(Log2_64(N1C->getValue()),
861 TLI.getShiftAmountTy()));
862 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
863 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
864 // FIXME: If the input is something that is easily negated (e.g. a
865 // single-use add), we should put the negate there.
866 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
867 DAG.getNode(ISD::SHL, VT, N0,
868 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
869 TLI.getShiftAmountTy())));
872 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
873 if (N1C && N0.getOpcode() == ISD::SHL &&
874 isa<ConstantSDNode>(N0.getOperand(1))) {
875 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
876 AddToWorkList(C3.Val);
877 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
880 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
883 SDOperand Sh(0,0), Y(0,0);
884 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
885 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
886 N0.Val->hasOneUse()) {
888 } else if (N1.getOpcode() == ISD::SHL &&
889 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
893 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
894 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
897 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
898 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
899 isa<ConstantSDNode>(N0.getOperand(1))) {
900 return DAG.getNode(ISD::ADD, VT,
901 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
902 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
906 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
912 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
913 SDOperand N0 = N->getOperand(0);
914 SDOperand N1 = N->getOperand(1);
915 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
916 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
917 MVT::ValueType VT = N->getValueType(0);
919 // fold (sdiv c1, c2) -> c1/c2
920 if (N0C && N1C && !N1C->isNullValue())
921 return DAG.getNode(ISD::SDIV, VT, N0, N1);
922 // fold (sdiv X, 1) -> X
923 if (N1C && N1C->getSignExtended() == 1LL)
925 // fold (sdiv X, -1) -> 0-X
926 if (N1C && N1C->isAllOnesValue())
927 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
928 // If we know the sign bits of both operands are zero, strength reduce to a
929 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
930 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
931 if (TLI.MaskedValueIsZero(N1, SignBit) &&
932 TLI.MaskedValueIsZero(N0, SignBit))
933 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
934 // fold (sdiv X, pow2) -> simple ops after legalize
935 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
936 (isPowerOf2_64(N1C->getSignExtended()) ||
937 isPowerOf2_64(-N1C->getSignExtended()))) {
938 // If dividing by powers of two is cheap, then don't perform the following
940 if (TLI.isPow2DivCheap())
942 int64_t pow2 = N1C->getSignExtended();
943 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
944 unsigned lg2 = Log2_64(abs2);
945 // Splat the sign bit into the register
946 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
947 DAG.getConstant(MVT::getSizeInBits(VT)-1,
948 TLI.getShiftAmountTy()));
949 AddToWorkList(SGN.Val);
950 // Add (N0 < 0) ? abs2 - 1 : 0;
951 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
952 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
953 TLI.getShiftAmountTy()));
954 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
955 AddToWorkList(SRL.Val);
956 AddToWorkList(ADD.Val); // Divide by pow2
957 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
958 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
959 // If we're dividing by a positive value, we're done. Otherwise, we must
960 // negate the result.
963 AddToWorkList(SRA.Val);
964 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
966 // if integer divide is expensive and we satisfy the requirements, emit an
967 // alternate sequence.
968 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
969 !TLI.isIntDivCheap()) {
970 SDOperand Op = BuildSDIV(N);
971 if (Op.Val) return Op;
976 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
977 SDOperand N0 = N->getOperand(0);
978 SDOperand N1 = N->getOperand(1);
979 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
980 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
981 MVT::ValueType VT = N->getValueType(0);
983 // fold (udiv c1, c2) -> c1/c2
984 if (N0C && N1C && !N1C->isNullValue())
985 return DAG.getNode(ISD::UDIV, VT, N0, N1);
986 // fold (udiv x, (1 << c)) -> x >>u c
987 if (N1C && isPowerOf2_64(N1C->getValue()))
988 return DAG.getNode(ISD::SRL, VT, N0,
989 DAG.getConstant(Log2_64(N1C->getValue()),
990 TLI.getShiftAmountTy()));
991 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
992 if (N1.getOpcode() == ISD::SHL) {
993 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
994 if (isPowerOf2_64(SHC->getValue())) {
995 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
996 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
997 DAG.getConstant(Log2_64(SHC->getValue()),
999 AddToWorkList(Add.Val);
1000 return DAG.getNode(ISD::SRL, VT, N0, Add);
1004 // fold (udiv x, c) -> alternate
1005 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1006 SDOperand Op = BuildUDIV(N);
1007 if (Op.Val) return Op;
1012 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1013 SDOperand N0 = N->getOperand(0);
1014 SDOperand N1 = N->getOperand(1);
1015 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1016 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1017 MVT::ValueType VT = N->getValueType(0);
1019 // fold (srem c1, c2) -> c1%c2
1020 if (N0C && N1C && !N1C->isNullValue())
1021 return DAG.getNode(ISD::SREM, VT, N0, N1);
1022 // If we know the sign bits of both operands are zero, strength reduce to a
1023 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1024 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1025 if (TLI.MaskedValueIsZero(N1, SignBit) &&
1026 TLI.MaskedValueIsZero(N0, SignBit))
1027 return DAG.getNode(ISD::UREM, VT, N0, N1);
1029 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1030 // the remainder operation.
1031 if (N1C && !N1C->isNullValue()) {
1032 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1033 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1034 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1035 AddToWorkList(Div.Val);
1036 AddToWorkList(Mul.Val);
1043 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1044 SDOperand N0 = N->getOperand(0);
1045 SDOperand N1 = N->getOperand(1);
1046 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1047 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1048 MVT::ValueType VT = N->getValueType(0);
1050 // fold (urem c1, c2) -> c1%c2
1051 if (N0C && N1C && !N1C->isNullValue())
1052 return DAG.getNode(ISD::UREM, VT, N0, N1);
1053 // fold (urem x, pow2) -> (and x, pow2-1)
1054 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1055 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1056 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1057 if (N1.getOpcode() == ISD::SHL) {
1058 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1059 if (isPowerOf2_64(SHC->getValue())) {
1060 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1061 AddToWorkList(Add.Val);
1062 return DAG.getNode(ISD::AND, VT, N0, Add);
1067 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1068 // the remainder operation.
1069 if (N1C && !N1C->isNullValue()) {
1070 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1071 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1072 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1073 AddToWorkList(Div.Val);
1074 AddToWorkList(Mul.Val);
1081 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1082 SDOperand N0 = N->getOperand(0);
1083 SDOperand N1 = N->getOperand(1);
1084 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1086 // fold (mulhs x, 0) -> 0
1087 if (N1C && N1C->isNullValue())
1089 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1090 if (N1C && N1C->getValue() == 1)
1091 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1092 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1093 TLI.getShiftAmountTy()));
1097 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1098 SDOperand N0 = N->getOperand(0);
1099 SDOperand N1 = N->getOperand(1);
1100 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1102 // fold (mulhu x, 0) -> 0
1103 if (N1C && N1C->isNullValue())
1105 // fold (mulhu x, 1) -> 0
1106 if (N1C && N1C->getValue() == 1)
1107 return DAG.getConstant(0, N0.getValueType());
1111 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1112 /// two operands of the same opcode, try to simplify it.
1113 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1114 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1115 MVT::ValueType VT = N0.getValueType();
1116 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1118 // For each of OP in AND/OR/XOR:
1119 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1120 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1121 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1122 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1123 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1124 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1125 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1126 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1127 N0.getOperand(0).getValueType(),
1128 N0.getOperand(0), N1.getOperand(0));
1129 AddToWorkList(ORNode.Val);
1130 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1133 // For each of OP in SHL/SRL/SRA/AND...
1134 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1135 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1136 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1137 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1138 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1139 N0.getOperand(1) == N1.getOperand(1)) {
1140 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1141 N0.getOperand(0).getValueType(),
1142 N0.getOperand(0), N1.getOperand(0));
1143 AddToWorkList(ORNode.Val);
1144 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1150 SDOperand DAGCombiner::visitAND(SDNode *N) {
1151 SDOperand N0 = N->getOperand(0);
1152 SDOperand N1 = N->getOperand(1);
1153 SDOperand LL, LR, RL, RR, CC0, CC1;
1154 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1155 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1156 MVT::ValueType VT = N1.getValueType();
1158 // fold (and c1, c2) -> c1&c2
1160 return DAG.getNode(ISD::AND, VT, N0, N1);
1161 // canonicalize constant to RHS
1163 return DAG.getNode(ISD::AND, VT, N1, N0);
1164 // fold (and x, -1) -> x
1165 if (N1C && N1C->isAllOnesValue())
1167 // if (and x, c) is known to be zero, return 0
1168 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1169 return DAG.getConstant(0, VT);
1171 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1174 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1175 if (N1C && N0.getOpcode() == ISD::OR)
1176 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1177 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1179 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1180 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1181 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1182 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1183 ~N1C->getValue() & InMask)) {
1184 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1187 // Replace uses of the AND with uses of the Zero extend node.
1190 // We actually want to replace all uses of the any_extend with the
1191 // zero_extend, to avoid duplicating things. This will later cause this
1192 // AND to be folded.
1193 CombineTo(N0.Val, Zext);
1194 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1197 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1198 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1199 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1200 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1202 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1203 MVT::isInteger(LL.getValueType())) {
1204 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1205 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1206 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1207 AddToWorkList(ORNode.Val);
1208 return DAG.getSetCC(VT, ORNode, LR, Op1);
1210 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1211 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1212 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1213 AddToWorkList(ANDNode.Val);
1214 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1216 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1217 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1218 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1219 AddToWorkList(ORNode.Val);
1220 return DAG.getSetCC(VT, ORNode, LR, Op1);
1223 // canonicalize equivalent to ll == rl
1224 if (LL == RR && LR == RL) {
1225 Op1 = ISD::getSetCCSwappedOperands(Op1);
1228 if (LL == RL && LR == RR) {
1229 bool isInteger = MVT::isInteger(LL.getValueType());
1230 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1231 if (Result != ISD::SETCC_INVALID)
1232 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1236 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1237 if (N0.getOpcode() == N1.getOpcode()) {
1238 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1239 if (Tmp.Val) return Tmp;
1242 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1243 // fold (and (sra)) -> (and (srl)) when possible.
1244 if (!MVT::isVector(VT) &&
1245 SimplifyDemandedBits(SDOperand(N, 0)))
1246 return SDOperand(N, 0);
1247 // fold (zext_inreg (extload x)) -> (zextload x)
1248 if (ISD::isEXTLoad(N0.Val)) {
1249 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1250 MVT::ValueType EVT = LN0->getLoadedVT();
1251 // If we zero all the possible extended bits, then we can turn this into
1252 // a zextload if we are running before legalize or the operation is legal.
1253 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1254 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1255 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1256 LN0->getBasePtr(), LN0->getSrcValue(),
1257 LN0->getSrcValueOffset(), EVT);
1259 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1260 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1263 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1264 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
1265 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1266 MVT::ValueType EVT = LN0->getLoadedVT();
1267 // If we zero all the possible extended bits, then we can turn this into
1268 // a zextload if we are running before legalize or the operation is legal.
1269 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1270 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1271 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1272 LN0->getBasePtr(), LN0->getSrcValue(),
1273 LN0->getSrcValueOffset(), EVT);
1275 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1276 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1280 // fold (and (load x), 255) -> (zextload x, i8)
1281 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1282 if (N1C && N0.getOpcode() == ISD::LOAD) {
1283 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1284 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1286 MVT::ValueType EVT, LoadedVT;
1287 if (N1C->getValue() == 255)
1289 else if (N1C->getValue() == 65535)
1291 else if (N1C->getValue() == ~0U)
1296 LoadedVT = LN0->getLoadedVT();
1297 if (EVT != MVT::Other && LoadedVT > EVT &&
1298 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1299 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1300 // For big endian targets, we need to add an offset to the pointer to
1301 // load the correct bytes. For little endian systems, we merely need to
1302 // read fewer bytes from the same pointer.
1304 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1305 SDOperand NewPtr = LN0->getBasePtr();
1306 if (!TLI.isLittleEndian())
1307 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1308 DAG.getConstant(PtrOff, PtrType));
1309 AddToWorkList(NewPtr.Val);
1311 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1312 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1314 CombineTo(N0.Val, Load, Load.getValue(1));
1315 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1323 SDOperand DAGCombiner::visitOR(SDNode *N) {
1324 SDOperand N0 = N->getOperand(0);
1325 SDOperand N1 = N->getOperand(1);
1326 SDOperand LL, LR, RL, RR, CC0, CC1;
1327 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1328 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1329 MVT::ValueType VT = N1.getValueType();
1330 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1332 // fold (or c1, c2) -> c1|c2
1334 return DAG.getNode(ISD::OR, VT, N0, N1);
1335 // canonicalize constant to RHS
1337 return DAG.getNode(ISD::OR, VT, N1, N0);
1338 // fold (or x, 0) -> x
1339 if (N1C && N1C->isNullValue())
1341 // fold (or x, -1) -> -1
1342 if (N1C && N1C->isAllOnesValue())
1344 // fold (or x, c) -> c iff (x & ~c) == 0
1346 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1349 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1352 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1353 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1354 isa<ConstantSDNode>(N0.getOperand(1))) {
1355 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1356 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1358 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1360 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1361 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1362 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1363 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1365 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1366 MVT::isInteger(LL.getValueType())) {
1367 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1368 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1369 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1370 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1371 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1372 AddToWorkList(ORNode.Val);
1373 return DAG.getSetCC(VT, ORNode, LR, Op1);
1375 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1376 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1377 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1378 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1379 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1380 AddToWorkList(ANDNode.Val);
1381 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1384 // canonicalize equivalent to ll == rl
1385 if (LL == RR && LR == RL) {
1386 Op1 = ISD::getSetCCSwappedOperands(Op1);
1389 if (LL == RL && LR == RR) {
1390 bool isInteger = MVT::isInteger(LL.getValueType());
1391 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1392 if (Result != ISD::SETCC_INVALID)
1393 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1397 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1398 if (N0.getOpcode() == N1.getOpcode()) {
1399 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1400 if (Tmp.Val) return Tmp;
1403 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1404 if (N0.getOpcode() == ISD::AND &&
1405 N1.getOpcode() == ISD::AND &&
1406 N0.getOperand(1).getOpcode() == ISD::Constant &&
1407 N1.getOperand(1).getOpcode() == ISD::Constant &&
1408 // Don't increase # computations.
1409 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1410 // We can only do this xform if we know that bits from X that are set in C2
1411 // but not in C1 are already zero. Likewise for Y.
1412 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1413 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1415 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1416 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1417 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1418 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1423 // See if this is some rotate idiom.
1424 if (SDNode *Rot = MatchRotate(N0, N1))
1425 return SDOperand(Rot, 0);
1431 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1432 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1433 if (Op.getOpcode() == ISD::AND) {
1434 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1435 Mask = Op.getOperand(1);
1436 Op = Op.getOperand(0);
1442 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1450 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1451 // idioms for rotate, and if the target supports rotation instructions, generate
1453 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1454 // Must be a legal type. Expanded an promoted things won't work with rotates.
1455 MVT::ValueType VT = LHS.getValueType();
1456 if (!TLI.isTypeLegal(VT)) return 0;
1458 // The target must have at least one rotate flavor.
1459 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1460 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1461 if (!HasROTL && !HasROTR) return 0;
1463 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1464 SDOperand LHSShift; // The shift.
1465 SDOperand LHSMask; // AND value if any.
1466 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1467 return 0; // Not part of a rotate.
1469 SDOperand RHSShift; // The shift.
1470 SDOperand RHSMask; // AND value if any.
1471 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1472 return 0; // Not part of a rotate.
1474 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1475 return 0; // Not shifting the same value.
1477 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1478 return 0; // Shifts must disagree.
1480 // Canonicalize shl to left side in a shl/srl pair.
1481 if (RHSShift.getOpcode() == ISD::SHL) {
1482 std::swap(LHS, RHS);
1483 std::swap(LHSShift, RHSShift);
1484 std::swap(LHSMask , RHSMask );
1487 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1489 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1490 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1491 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1492 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1493 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1494 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1495 if ((LShVal + RShVal) != OpSizeInBits)
1500 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1501 LHSShift.getOperand(1));
1503 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1504 RHSShift.getOperand(1));
1506 // If there is an AND of either shifted operand, apply it to the result.
1507 if (LHSMask.Val || RHSMask.Val) {
1508 uint64_t Mask = MVT::getIntVTBitMask(VT);
1511 uint64_t RHSBits = (1ULL << LShVal)-1;
1512 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1515 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1516 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1519 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1525 // If there is a mask here, and we have a variable shift, we can't be sure
1526 // that we're masking out the right stuff.
1527 if (LHSMask.Val || RHSMask.Val)
1530 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1531 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1532 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1533 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1534 if (ConstantSDNode *SUBC =
1535 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1536 if (SUBC->getValue() == OpSizeInBits)
1538 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1539 LHSShift.getOperand(1)).Val;
1541 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1542 LHSShift.getOperand(1)).Val;
1546 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1547 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1548 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1549 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1550 if (ConstantSDNode *SUBC =
1551 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1552 if (SUBC->getValue() == OpSizeInBits)
1554 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1555 LHSShift.getOperand(1)).Val;
1557 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1558 RHSShift.getOperand(1)).Val;
1566 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1567 SDOperand N0 = N->getOperand(0);
1568 SDOperand N1 = N->getOperand(1);
1569 SDOperand LHS, RHS, CC;
1570 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1571 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1572 MVT::ValueType VT = N0.getValueType();
1574 // fold (xor c1, c2) -> c1^c2
1576 return DAG.getNode(ISD::XOR, VT, N0, N1);
1577 // canonicalize constant to RHS
1579 return DAG.getNode(ISD::XOR, VT, N1, N0);
1580 // fold (xor x, 0) -> x
1581 if (N1C && N1C->isNullValue())
1584 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1587 // fold !(x cc y) -> (x !cc y)
1588 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1589 bool isInt = MVT::isInteger(LHS.getValueType());
1590 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1592 if (N0.getOpcode() == ISD::SETCC)
1593 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1594 if (N0.getOpcode() == ISD::SELECT_CC)
1595 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1596 assert(0 && "Unhandled SetCC Equivalent!");
1599 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1600 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
1601 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1602 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1603 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1604 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1605 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1606 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1607 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1608 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1611 // fold !(x or y) -> (!x and !y) iff x or y are constants
1612 if (N1C && N1C->isAllOnesValue() &&
1613 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1614 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1615 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1616 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1617 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1618 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1619 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1620 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1623 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1624 if (N1C && N0.getOpcode() == ISD::XOR) {
1625 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1626 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1628 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1629 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1631 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1632 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1634 // fold (xor x, x) -> 0
1636 if (!MVT::isVector(VT)) {
1637 return DAG.getConstant(0, VT);
1638 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1639 // Produce a vector of zeros.
1640 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1641 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1642 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1646 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1647 if (N0.getOpcode() == N1.getOpcode()) {
1648 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1649 if (Tmp.Val) return Tmp;
1652 // Simplify the expression using non-local knowledge.
1653 if (!MVT::isVector(VT) &&
1654 SimplifyDemandedBits(SDOperand(N, 0)))
1655 return SDOperand(N, 0);
1660 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1661 SDOperand N0 = N->getOperand(0);
1662 SDOperand N1 = N->getOperand(1);
1663 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1664 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1665 MVT::ValueType VT = N0.getValueType();
1666 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1668 // fold (shl c1, c2) -> c1<<c2
1670 return DAG.getNode(ISD::SHL, VT, N0, N1);
1671 // fold (shl 0, x) -> 0
1672 if (N0C && N0C->isNullValue())
1674 // fold (shl x, c >= size(x)) -> undef
1675 if (N1C && N1C->getValue() >= OpSizeInBits)
1676 return DAG.getNode(ISD::UNDEF, VT);
1677 // fold (shl x, 0) -> x
1678 if (N1C && N1C->isNullValue())
1680 // if (shl x, c) is known to be zero, return 0
1681 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1682 return DAG.getConstant(0, VT);
1683 if (SimplifyDemandedBits(SDOperand(N, 0)))
1684 return SDOperand(N, 0);
1685 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1686 if (N1C && N0.getOpcode() == ISD::SHL &&
1687 N0.getOperand(1).getOpcode() == ISD::Constant) {
1688 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1689 uint64_t c2 = N1C->getValue();
1690 if (c1 + c2 > OpSizeInBits)
1691 return DAG.getConstant(0, VT);
1692 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1693 DAG.getConstant(c1 + c2, N1.getValueType()));
1695 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1696 // (srl (and x, -1 << c1), c1-c2)
1697 if (N1C && N0.getOpcode() == ISD::SRL &&
1698 N0.getOperand(1).getOpcode() == ISD::Constant) {
1699 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1700 uint64_t c2 = N1C->getValue();
1701 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1702 DAG.getConstant(~0ULL << c1, VT));
1704 return DAG.getNode(ISD::SHL, VT, Mask,
1705 DAG.getConstant(c2-c1, N1.getValueType()));
1707 return DAG.getNode(ISD::SRL, VT, Mask,
1708 DAG.getConstant(c1-c2, N1.getValueType()));
1710 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1711 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1712 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1713 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1717 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1718 SDOperand N0 = N->getOperand(0);
1719 SDOperand N1 = N->getOperand(1);
1720 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1721 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1722 MVT::ValueType VT = N0.getValueType();
1724 // fold (sra c1, c2) -> c1>>c2
1726 return DAG.getNode(ISD::SRA, VT, N0, N1);
1727 // fold (sra 0, x) -> 0
1728 if (N0C && N0C->isNullValue())
1730 // fold (sra -1, x) -> -1
1731 if (N0C && N0C->isAllOnesValue())
1733 // fold (sra x, c >= size(x)) -> undef
1734 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1735 return DAG.getNode(ISD::UNDEF, VT);
1736 // fold (sra x, 0) -> x
1737 if (N1C && N1C->isNullValue())
1739 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1741 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1742 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1745 default: EVT = MVT::Other; break;
1746 case 1: EVT = MVT::i1; break;
1747 case 8: EVT = MVT::i8; break;
1748 case 16: EVT = MVT::i16; break;
1749 case 32: EVT = MVT::i32; break;
1751 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1752 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1753 DAG.getValueType(EVT));
1756 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1757 if (N1C && N0.getOpcode() == ISD::SRA) {
1758 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1759 unsigned Sum = N1C->getValue() + C1->getValue();
1760 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1761 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1762 DAG.getConstant(Sum, N1C->getValueType(0)));
1766 // Simplify, based on bits shifted out of the LHS.
1767 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1768 return SDOperand(N, 0);
1771 // If the sign bit is known to be zero, switch this to a SRL.
1772 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1773 return DAG.getNode(ISD::SRL, VT, N0, N1);
1777 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1778 SDOperand N0 = N->getOperand(0);
1779 SDOperand N1 = N->getOperand(1);
1780 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1781 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1782 MVT::ValueType VT = N0.getValueType();
1783 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1785 // fold (srl c1, c2) -> c1 >>u c2
1787 return DAG.getNode(ISD::SRL, VT, N0, N1);
1788 // fold (srl 0, x) -> 0
1789 if (N0C && N0C->isNullValue())
1791 // fold (srl x, c >= size(x)) -> undef
1792 if (N1C && N1C->getValue() >= OpSizeInBits)
1793 return DAG.getNode(ISD::UNDEF, VT);
1794 // fold (srl x, 0) -> x
1795 if (N1C && N1C->isNullValue())
1797 // if (srl x, c) is known to be zero, return 0
1798 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1799 return DAG.getConstant(0, VT);
1800 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1801 if (N1C && N0.getOpcode() == ISD::SRL &&
1802 N0.getOperand(1).getOpcode() == ISD::Constant) {
1803 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1804 uint64_t c2 = N1C->getValue();
1805 if (c1 + c2 > OpSizeInBits)
1806 return DAG.getConstant(0, VT);
1807 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1808 DAG.getConstant(c1 + c2, N1.getValueType()));
1811 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1812 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1813 // Shifting in all undef bits?
1814 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1815 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1816 return DAG.getNode(ISD::UNDEF, VT);
1818 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1819 AddToWorkList(SmallShift.Val);
1820 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1823 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
1824 // bit, which is unmodified by sra.
1825 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
1826 if (N0.getOpcode() == ISD::SRA)
1827 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
1830 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1831 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1832 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1833 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1834 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1836 // If any of the input bits are KnownOne, then the input couldn't be all
1837 // zeros, thus the result of the srl will always be zero.
1838 if (KnownOne) return DAG.getConstant(0, VT);
1840 // If all of the bits input the to ctlz node are known to be zero, then
1841 // the result of the ctlz is "32" and the result of the shift is one.
1842 uint64_t UnknownBits = ~KnownZero & Mask;
1843 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1845 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1846 if ((UnknownBits & (UnknownBits-1)) == 0) {
1847 // Okay, we know that only that the single bit specified by UnknownBits
1848 // could be set on input to the CTLZ node. If this bit is set, the SRL
1849 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1850 // to an SRL,XOR pair, which is likely to simplify more.
1851 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1852 SDOperand Op = N0.getOperand(0);
1854 Op = DAG.getNode(ISD::SRL, VT, Op,
1855 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1856 AddToWorkList(Op.Val);
1858 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1865 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1866 SDOperand N0 = N->getOperand(0);
1867 MVT::ValueType VT = N->getValueType(0);
1869 // fold (ctlz c1) -> c2
1870 if (isa<ConstantSDNode>(N0))
1871 return DAG.getNode(ISD::CTLZ, VT, N0);
1875 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1876 SDOperand N0 = N->getOperand(0);
1877 MVT::ValueType VT = N->getValueType(0);
1879 // fold (cttz c1) -> c2
1880 if (isa<ConstantSDNode>(N0))
1881 return DAG.getNode(ISD::CTTZ, VT, N0);
1885 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1886 SDOperand N0 = N->getOperand(0);
1887 MVT::ValueType VT = N->getValueType(0);
1889 // fold (ctpop c1) -> c2
1890 if (isa<ConstantSDNode>(N0))
1891 return DAG.getNode(ISD::CTPOP, VT, N0);
1895 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1896 SDOperand N0 = N->getOperand(0);
1897 SDOperand N1 = N->getOperand(1);
1898 SDOperand N2 = N->getOperand(2);
1899 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1900 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1901 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1902 MVT::ValueType VT = N->getValueType(0);
1904 // fold select C, X, X -> X
1907 // fold select true, X, Y -> X
1908 if (N0C && !N0C->isNullValue())
1910 // fold select false, X, Y -> Y
1911 if (N0C && N0C->isNullValue())
1913 // fold select C, 1, X -> C | X
1914 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1915 return DAG.getNode(ISD::OR, VT, N0, N2);
1916 // fold select C, 0, X -> ~C & X
1917 // FIXME: this should check for C type == X type, not i1?
1918 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1919 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1920 AddToWorkList(XORNode.Val);
1921 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1923 // fold select C, X, 1 -> ~C | X
1924 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1925 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1926 AddToWorkList(XORNode.Val);
1927 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1929 // fold select C, X, 0 -> C & X
1930 // FIXME: this should check for C type == X type, not i1?
1931 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1932 return DAG.getNode(ISD::AND, VT, N0, N1);
1933 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1934 if (MVT::i1 == VT && N0 == N1)
1935 return DAG.getNode(ISD::OR, VT, N0, N2);
1936 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1937 if (MVT::i1 == VT && N0 == N2)
1938 return DAG.getNode(ISD::AND, VT, N0, N1);
1940 // If we can fold this based on the true/false value, do so.
1941 if (SimplifySelectOps(N, N1, N2))
1942 return SDOperand(N, 0); // Don't revisit N.
1944 // fold selects based on a setcc into other things, such as min/max/abs
1945 if (N0.getOpcode() == ISD::SETCC)
1947 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1948 // having to say they don't support SELECT_CC on every type the DAG knows
1949 // about, since there is no way to mark an opcode illegal at all value types
1950 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1951 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1952 N1, N2, N0.getOperand(2));
1954 return SimplifySelect(N0, N1, N2);
1958 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1959 SDOperand N0 = N->getOperand(0);
1960 SDOperand N1 = N->getOperand(1);
1961 SDOperand N2 = N->getOperand(2);
1962 SDOperand N3 = N->getOperand(3);
1963 SDOperand N4 = N->getOperand(4);
1964 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1966 // fold select_cc lhs, rhs, x, x, cc -> x
1970 // Determine if the condition we're dealing with is constant
1971 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1972 if (SCC.Val) AddToWorkList(SCC.Val);
1974 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1975 if (SCCC->getValue())
1976 return N2; // cond always true -> true val
1978 return N3; // cond always false -> false val
1981 // Fold to a simpler select_cc
1982 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1983 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1984 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1987 // If we can fold this based on the true/false value, do so.
1988 if (SimplifySelectOps(N, N2, N3))
1989 return SDOperand(N, 0); // Don't revisit N.
1991 // fold select_cc into other things, such as min/max/abs
1992 return SimplifySelectCC(N0, N1, N2, N3, CC);
1995 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1996 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1997 cast<CondCodeSDNode>(N->getOperand(2))->get());
2000 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2001 SDOperand N0 = N->getOperand(0);
2002 MVT::ValueType VT = N->getValueType(0);
2004 // fold (sext c1) -> c1
2005 if (isa<ConstantSDNode>(N0))
2006 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2008 // fold (sext (sext x)) -> (sext x)
2009 // fold (sext (aext x)) -> (sext x)
2010 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2011 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2013 if (N0.getOpcode() == ISD::TRUNCATE) {
2014 // See if the value being truncated is already sign extended. If so, just
2015 // eliminate the trunc/sext pair.
2016 SDOperand Op = N0.getOperand(0);
2017 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2018 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2019 unsigned DestBits = MVT::getSizeInBits(VT);
2020 unsigned NumSignBits = TLI.ComputeNumSignBits(Op);
2022 if (OpBits == DestBits) {
2023 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2024 // bits, it is already ready.
2025 if (NumSignBits > DestBits-MidBits)
2027 } else if (OpBits < DestBits) {
2028 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2029 // bits, just sext from i32.
2030 if (NumSignBits > OpBits-MidBits)
2031 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2033 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2034 // bits, just truncate to i32.
2035 if (NumSignBits > OpBits-MidBits)
2036 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2039 // fold (sext (truncate x)) -> (sextinreg x).
2040 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2041 N0.getValueType())) {
2042 if (Op.getValueType() < VT)
2043 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2044 else if (Op.getValueType() > VT)
2045 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2046 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2047 DAG.getValueType(N0.getValueType()));
2051 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2052 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2053 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2054 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2055 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2056 LN0->getBasePtr(), LN0->getSrcValue(),
2057 LN0->getSrcValueOffset(),
2059 CombineTo(N, ExtLoad);
2060 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2061 ExtLoad.getValue(1));
2062 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2065 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2066 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2067 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
2068 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2069 MVT::ValueType EVT = LN0->getLoadedVT();
2070 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2071 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2072 LN0->getBasePtr(), LN0->getSrcValue(),
2073 LN0->getSrcValueOffset(), EVT);
2074 CombineTo(N, ExtLoad);
2075 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2076 ExtLoad.getValue(1));
2077 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2084 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2085 SDOperand N0 = N->getOperand(0);
2086 MVT::ValueType VT = N->getValueType(0);
2088 // fold (zext c1) -> c1
2089 if (isa<ConstantSDNode>(N0))
2090 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2091 // fold (zext (zext x)) -> (zext x)
2092 // fold (zext (aext x)) -> (zext x)
2093 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2094 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2096 // fold (zext (truncate x)) -> (and x, mask)
2097 if (N0.getOpcode() == ISD::TRUNCATE &&
2098 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2099 SDOperand Op = N0.getOperand(0);
2100 if (Op.getValueType() < VT) {
2101 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2102 } else if (Op.getValueType() > VT) {
2103 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2105 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2108 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2109 if (N0.getOpcode() == ISD::AND &&
2110 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2111 N0.getOperand(1).getOpcode() == ISD::Constant) {
2112 SDOperand X = N0.getOperand(0).getOperand(0);
2113 if (X.getValueType() < VT) {
2114 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2115 } else if (X.getValueType() > VT) {
2116 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2118 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2119 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2122 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2123 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2124 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2125 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2126 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2127 LN0->getBasePtr(), LN0->getSrcValue(),
2128 LN0->getSrcValueOffset(),
2130 CombineTo(N, ExtLoad);
2131 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2132 ExtLoad.getValue(1));
2133 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2136 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2137 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2138 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
2139 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2140 MVT::ValueType EVT = LN0->getLoadedVT();
2141 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2142 LN0->getBasePtr(), LN0->getSrcValue(),
2143 LN0->getSrcValueOffset(), EVT);
2144 CombineTo(N, ExtLoad);
2145 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2146 ExtLoad.getValue(1));
2147 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2152 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2153 SDOperand N0 = N->getOperand(0);
2154 MVT::ValueType VT = N->getValueType(0);
2156 // fold (aext c1) -> c1
2157 if (isa<ConstantSDNode>(N0))
2158 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2159 // fold (aext (aext x)) -> (aext x)
2160 // fold (aext (zext x)) -> (zext x)
2161 // fold (aext (sext x)) -> (sext x)
2162 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2163 N0.getOpcode() == ISD::ZERO_EXTEND ||
2164 N0.getOpcode() == ISD::SIGN_EXTEND)
2165 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2167 // fold (aext (truncate x))
2168 if (N0.getOpcode() == ISD::TRUNCATE) {
2169 SDOperand TruncOp = N0.getOperand(0);
2170 if (TruncOp.getValueType() == VT)
2171 return TruncOp; // x iff x size == zext size.
2172 if (TruncOp.getValueType() > VT)
2173 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2174 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2177 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2178 if (N0.getOpcode() == ISD::AND &&
2179 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2180 N0.getOperand(1).getOpcode() == ISD::Constant) {
2181 SDOperand X = N0.getOperand(0).getOperand(0);
2182 if (X.getValueType() < VT) {
2183 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2184 } else if (X.getValueType() > VT) {
2185 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2187 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2188 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2191 // fold (aext (load x)) -> (aext (truncate (extload x)))
2192 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2193 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2194 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2195 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2196 LN0->getBasePtr(), LN0->getSrcValue(),
2197 LN0->getSrcValueOffset(),
2199 CombineTo(N, ExtLoad);
2200 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2201 ExtLoad.getValue(1));
2202 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2205 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2206 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2207 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2208 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
2210 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2211 MVT::ValueType EVT = LN0->getLoadedVT();
2212 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2213 LN0->getChain(), LN0->getBasePtr(),
2215 LN0->getSrcValueOffset(), EVT);
2216 CombineTo(N, ExtLoad);
2217 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2218 ExtLoad.getValue(1));
2219 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2225 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2226 SDOperand N0 = N->getOperand(0);
2227 SDOperand N1 = N->getOperand(1);
2228 MVT::ValueType VT = N->getValueType(0);
2229 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2230 unsigned EVTBits = MVT::getSizeInBits(EVT);
2232 // fold (sext_in_reg c1) -> c1
2233 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2234 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2236 // If the input is already sign extended, just drop the extension.
2237 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2240 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2241 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2242 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2243 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2246 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2247 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2248 return DAG.getZeroExtendInReg(N0, EVT);
2250 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2251 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2252 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2253 if (N0.getOpcode() == ISD::SRL) {
2254 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2255 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2256 // We can turn this into an SRA iff the input to the SRL is already sign
2258 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2259 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2260 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2264 // fold (sext_inreg (extload x)) -> (sextload x)
2265 if (ISD::isEXTLoad(N0.Val) &&
2266 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2267 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2268 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2269 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2270 LN0->getBasePtr(), LN0->getSrcValue(),
2271 LN0->getSrcValueOffset(), EVT);
2272 CombineTo(N, ExtLoad);
2273 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2274 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2276 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2277 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
2278 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2279 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2280 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2281 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2282 LN0->getBasePtr(), LN0->getSrcValue(),
2283 LN0->getSrcValueOffset(), EVT);
2284 CombineTo(N, ExtLoad);
2285 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2286 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2291 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2292 SDOperand N0 = N->getOperand(0);
2293 MVT::ValueType VT = N->getValueType(0);
2296 if (N0.getValueType() == N->getValueType(0))
2298 // fold (truncate c1) -> c1
2299 if (isa<ConstantSDNode>(N0))
2300 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2301 // fold (truncate (truncate x)) -> (truncate x)
2302 if (N0.getOpcode() == ISD::TRUNCATE)
2303 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2304 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2305 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2306 N0.getOpcode() == ISD::ANY_EXTEND) {
2307 if (N0.getOperand(0).getValueType() < VT)
2308 // if the source is smaller than the dest, we still need an extend
2309 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2310 else if (N0.getOperand(0).getValueType() > VT)
2311 // if the source is larger than the dest, than we just need the truncate
2312 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2314 // if the source and dest are the same type, we can drop both the extend
2316 return N0.getOperand(0);
2318 // fold (truncate (load x)) -> (smaller load x)
2319 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2320 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
2321 // zero extended form: by shrinking the load, we lose track of the fact
2322 // that it is already zero extended.
2323 // FIXME: This should be reevaluated.
2325 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2326 "Cannot truncate to larger type!");
2327 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2328 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2329 // For big endian targets, we need to add an offset to the pointer to load
2330 // the correct bytes. For little endian systems, we merely need to read
2331 // fewer bytes from the same pointer.
2333 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2334 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() :
2335 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2336 DAG.getConstant(PtrOff, PtrType));
2337 AddToWorkList(NewPtr.Val);
2338 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr,
2339 LN0->getSrcValue(), LN0->getSrcValueOffset());
2341 CombineTo(N0.Val, Load, Load.getValue(1));
2342 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2347 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2348 SDOperand N0 = N->getOperand(0);
2349 MVT::ValueType VT = N->getValueType(0);
2351 // If the input is a constant, let getNode() fold it.
2352 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2353 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2354 if (Res.Val != N) return Res;
2357 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2358 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2360 // fold (conv (load x)) -> (load (conv*)x)
2361 // FIXME: These xforms need to know that the resultant load doesn't need a
2362 // higher alignment than the original!
2363 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2364 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2365 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2366 LN0->getSrcValue(), LN0->getSrcValueOffset());
2368 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2376 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2377 SDOperand N0 = N->getOperand(0);
2378 MVT::ValueType VT = N->getValueType(0);
2380 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2381 // First check to see if this is all constant.
2382 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2383 VT == MVT::Vector) {
2384 bool isSimple = true;
2385 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2386 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2387 N0.getOperand(i).getOpcode() != ISD::Constant &&
2388 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2393 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2394 if (isSimple && !MVT::isVector(DestEltVT)) {
2395 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2402 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2403 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2404 /// destination element value type.
2405 SDOperand DAGCombiner::
2406 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2407 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2409 // If this is already the right type, we're done.
2410 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2412 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2413 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2415 // If this is a conversion of N elements of one type to N elements of another
2416 // type, convert each element. This handles FP<->INT cases.
2417 if (SrcBitSize == DstBitSize) {
2418 SmallVector<SDOperand, 8> Ops;
2419 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2420 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2421 AddToWorkList(Ops.back().Val);
2423 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2424 Ops.push_back(DAG.getValueType(DstEltVT));
2425 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2428 // Otherwise, we're growing or shrinking the elements. To avoid having to
2429 // handle annoying details of growing/shrinking FP values, we convert them to
2431 if (MVT::isFloatingPoint(SrcEltVT)) {
2432 // Convert the input float vector to a int vector where the elements are the
2434 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2435 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2436 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2440 // Now we know the input is an integer vector. If the output is a FP type,
2441 // convert to integer first, then to FP of the right size.
2442 if (MVT::isFloatingPoint(DstEltVT)) {
2443 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2444 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2445 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2447 // Next, convert to FP elements of the same size.
2448 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2451 // Okay, we know the src/dst types are both integers of differing types.
2452 // Handling growing first.
2453 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2454 if (SrcBitSize < DstBitSize) {
2455 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2457 SmallVector<SDOperand, 8> Ops;
2458 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2459 i += NumInputsPerOutput) {
2460 bool isLE = TLI.isLittleEndian();
2461 uint64_t NewBits = 0;
2462 bool EltIsUndef = true;
2463 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2464 // Shift the previously computed bits over.
2465 NewBits <<= SrcBitSize;
2466 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2467 if (Op.getOpcode() == ISD::UNDEF) continue;
2470 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2474 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2476 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2479 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2480 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2481 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2484 // Finally, this must be the case where we are shrinking elements: each input
2485 // turns into multiple outputs.
2486 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2487 SmallVector<SDOperand, 8> Ops;
2488 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2489 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2490 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2491 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2494 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2496 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2497 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2498 OpVal >>= DstBitSize;
2499 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2502 // For big endian targets, swap the order of the pieces of each element.
2503 if (!TLI.isLittleEndian())
2504 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2506 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2507 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2508 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2513 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2514 SDOperand N0 = N->getOperand(0);
2515 SDOperand N1 = N->getOperand(1);
2516 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2517 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2518 MVT::ValueType VT = N->getValueType(0);
2520 // fold (fadd c1, c2) -> c1+c2
2522 return DAG.getNode(ISD::FADD, VT, N0, N1);
2523 // canonicalize constant to RHS
2524 if (N0CFP && !N1CFP)
2525 return DAG.getNode(ISD::FADD, VT, N1, N0);
2526 // fold (A + (-B)) -> A-B
2527 if (N1.getOpcode() == ISD::FNEG)
2528 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2529 // fold ((-A) + B) -> B-A
2530 if (N0.getOpcode() == ISD::FNEG)
2531 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2533 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
2534 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
2535 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
2536 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
2537 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
2542 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2543 SDOperand N0 = N->getOperand(0);
2544 SDOperand N1 = N->getOperand(1);
2545 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2546 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2547 MVT::ValueType VT = N->getValueType(0);
2549 // fold (fsub c1, c2) -> c1-c2
2551 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2552 // fold (A-(-B)) -> A+B
2553 if (N1.getOpcode() == ISD::FNEG)
2554 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2558 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2559 SDOperand N0 = N->getOperand(0);
2560 SDOperand N1 = N->getOperand(1);
2561 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2562 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2563 MVT::ValueType VT = N->getValueType(0);
2565 // fold (fmul c1, c2) -> c1*c2
2567 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2568 // canonicalize constant to RHS
2569 if (N0CFP && !N1CFP)
2570 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2571 // fold (fmul X, 2.0) -> (fadd X, X)
2572 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2573 return DAG.getNode(ISD::FADD, VT, N0, N0);
2575 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
2576 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
2577 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
2578 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
2579 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
2584 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2585 SDOperand N0 = N->getOperand(0);
2586 SDOperand N1 = N->getOperand(1);
2587 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2588 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2589 MVT::ValueType VT = N->getValueType(0);
2591 // fold (fdiv c1, c2) -> c1/c2
2593 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2597 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2598 SDOperand N0 = N->getOperand(0);
2599 SDOperand N1 = N->getOperand(1);
2600 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2601 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2602 MVT::ValueType VT = N->getValueType(0);
2604 // fold (frem c1, c2) -> fmod(c1,c2)
2606 return DAG.getNode(ISD::FREM, VT, N0, N1);
2610 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2611 SDOperand N0 = N->getOperand(0);
2612 SDOperand N1 = N->getOperand(1);
2613 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2614 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2615 MVT::ValueType VT = N->getValueType(0);
2617 if (N0CFP && N1CFP) // Constant fold
2618 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2621 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2622 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2627 u.d = N1CFP->getValue();
2629 return DAG.getNode(ISD::FABS, VT, N0);
2631 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2634 // copysign(fabs(x), y) -> copysign(x, y)
2635 // copysign(fneg(x), y) -> copysign(x, y)
2636 // copysign(copysign(x,z), y) -> copysign(x, y)
2637 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2638 N0.getOpcode() == ISD::FCOPYSIGN)
2639 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2641 // copysign(x, abs(y)) -> abs(x)
2642 if (N1.getOpcode() == ISD::FABS)
2643 return DAG.getNode(ISD::FABS, VT, N0);
2645 // copysign(x, copysign(y,z)) -> copysign(x, z)
2646 if (N1.getOpcode() == ISD::FCOPYSIGN)
2647 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2649 // copysign(x, fp_extend(y)) -> copysign(x, y)
2650 // copysign(x, fp_round(y)) -> copysign(x, y)
2651 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2652 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2659 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2660 SDOperand N0 = N->getOperand(0);
2661 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2662 MVT::ValueType VT = N->getValueType(0);
2664 // fold (sint_to_fp c1) -> c1fp
2666 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2670 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2671 SDOperand N0 = N->getOperand(0);
2672 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2673 MVT::ValueType VT = N->getValueType(0);
2675 // fold (uint_to_fp c1) -> c1fp
2677 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2681 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2682 SDOperand N0 = N->getOperand(0);
2683 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2684 MVT::ValueType VT = N->getValueType(0);
2686 // fold (fp_to_sint c1fp) -> c1
2688 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2692 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2693 SDOperand N0 = N->getOperand(0);
2694 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2695 MVT::ValueType VT = N->getValueType(0);
2697 // fold (fp_to_uint c1fp) -> c1
2699 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2703 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2704 SDOperand N0 = N->getOperand(0);
2705 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2706 MVT::ValueType VT = N->getValueType(0);
2708 // fold (fp_round c1fp) -> c1fp
2710 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2712 // fold (fp_round (fp_extend x)) -> x
2713 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2714 return N0.getOperand(0);
2716 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2717 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2718 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2719 AddToWorkList(Tmp.Val);
2720 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2726 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2727 SDOperand N0 = N->getOperand(0);
2728 MVT::ValueType VT = N->getValueType(0);
2729 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2730 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2732 // fold (fp_round_inreg c1fp) -> c1fp
2734 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2735 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2740 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2741 SDOperand N0 = N->getOperand(0);
2742 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2743 MVT::ValueType VT = N->getValueType(0);
2745 // fold (fp_extend c1fp) -> c1fp
2747 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2749 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2750 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2751 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2752 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2753 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2754 LN0->getBasePtr(), LN0->getSrcValue(),
2755 LN0->getSrcValueOffset(),
2757 CombineTo(N, ExtLoad);
2758 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2759 ExtLoad.getValue(1));
2760 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2767 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2768 SDOperand N0 = N->getOperand(0);
2769 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2770 MVT::ValueType VT = N->getValueType(0);
2772 // fold (fneg c1) -> -c1
2774 return DAG.getNode(ISD::FNEG, VT, N0);
2775 // fold (fneg (sub x, y)) -> (sub y, x)
2776 if (N0.getOpcode() == ISD::SUB)
2777 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2778 // fold (fneg (fneg x)) -> x
2779 if (N0.getOpcode() == ISD::FNEG)
2780 return N0.getOperand(0);
2784 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2785 SDOperand N0 = N->getOperand(0);
2786 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2787 MVT::ValueType VT = N->getValueType(0);
2789 // fold (fabs c1) -> fabs(c1)
2791 return DAG.getNode(ISD::FABS, VT, N0);
2792 // fold (fabs (fabs x)) -> (fabs x)
2793 if (N0.getOpcode() == ISD::FABS)
2794 return N->getOperand(0);
2795 // fold (fabs (fneg x)) -> (fabs x)
2796 // fold (fabs (fcopysign x, y)) -> (fabs x)
2797 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2798 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2803 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2804 SDOperand Chain = N->getOperand(0);
2805 SDOperand N1 = N->getOperand(1);
2806 SDOperand N2 = N->getOperand(2);
2807 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2809 // never taken branch, fold to chain
2810 if (N1C && N1C->isNullValue())
2812 // unconditional branch
2813 if (N1C && N1C->getValue() == 1)
2814 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2815 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2817 if (N1.getOpcode() == ISD::SETCC &&
2818 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2819 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2820 N1.getOperand(0), N1.getOperand(1), N2);
2825 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2827 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2828 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2829 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2831 // Use SimplifySetCC to simplify SETCC's.
2832 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2833 if (Simp.Val) AddToWorkList(Simp.Val);
2835 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2837 // fold br_cc true, dest -> br dest (unconditional branch)
2838 if (SCCC && SCCC->getValue())
2839 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2841 // fold br_cc false, dest -> unconditional fall through
2842 if (SCCC && SCCC->isNullValue())
2843 return N->getOperand(0);
2845 // fold to a simpler setcc
2846 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2847 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2848 Simp.getOperand(2), Simp.getOperand(0),
2849 Simp.getOperand(1), N->getOperand(4));
2854 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
2855 /// pre-indexed load / store when the base pointer is a add or subtract
2856 /// and it has other uses besides the load / store. After the
2857 /// transformation, the new indexed load / store has effectively folded
2858 /// the add / subtract in and all of its other uses are redirected to the
2859 /// new load / store.
2860 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
2867 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2868 if (LD->getAddressingMode() != ISD::UNINDEXED)
2870 VT = LD->getLoadedVT();
2871 if (LD->getAddressingMode() != ISD::UNINDEXED &&
2872 !TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
2873 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
2875 Ptr = LD->getBasePtr();
2876 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2877 if (ST->getAddressingMode() != ISD::UNINDEXED)
2879 VT = ST->getStoredVT();
2880 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
2881 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
2883 Ptr = ST->getBasePtr();
2888 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
2889 // out. There is no reason to make this a preinc/predec.
2890 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
2891 Ptr.Val->hasOneUse())
2894 // Ask the target to do addressing mode selection.
2897 ISD::MemIndexedMode AM = ISD::UNINDEXED;
2898 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
2901 // Try turning it into a pre-indexed load / store except when:
2902 // 1) The base is a frame index.
2903 // 2) If N is a store and the ptr is either the same as or is a
2904 // predecessor of the value being stored.
2905 // 3) Another use of base ptr is a predecessor of N. If ptr is folded
2906 // that would create a cycle.
2907 // 4) All uses are load / store ops that use it as base ptr.
2909 // Check #1. Preinc'ing a frame index would require copying the stack pointer
2910 // (plus the implicit offset) to a register to preinc anyway.
2911 if (isa<FrameIndexSDNode>(BasePtr))
2916 SDOperand Val = cast<StoreSDNode>(N)->getValue();
2917 if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val))
2921 // Now check for #2 and #3.
2922 bool RealUse = false;
2923 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
2924 E = Ptr.Val->use_end(); I != E; ++I) {
2928 if (Use->isPredecessor(N))
2931 if (!((Use->getOpcode() == ISD::LOAD &&
2932 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
2933 (Use->getOpcode() == ISD::STORE) &&
2934 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
2942 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
2944 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
2947 DOUT << "\nReplacing.4 "; DEBUG(N->dump());
2948 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
2950 std::vector<SDNode*> NowDead;
2952 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
2954 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
2957 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
2961 // Nodes can end up on the worklist more than once. Make sure we do
2962 // not process a node that has been replaced.
2963 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
2964 removeFromWorkList(NowDead[i]);
2965 // Finally, since the node is now dead, remove it from the graph.
2968 // Replace the uses of Ptr with uses of the updated base value.
2969 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
2971 removeFromWorkList(Ptr.Val);
2972 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
2973 removeFromWorkList(NowDead[i]);
2974 DAG.DeleteNode(Ptr.Val);
2979 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
2980 /// add / sub of the base pointer node into a post-indexed load / store.
2981 /// The transformation folded the add / subtract into the new indexed
2982 /// load / store effectively and all of its uses are redirected to the
2983 /// new load / store.
2984 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
2991 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2992 if (LD->getAddressingMode() != ISD::UNINDEXED)
2994 VT = LD->getLoadedVT();
2995 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
2996 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
2998 Ptr = LD->getBasePtr();
2999 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3000 if (ST->getAddressingMode() != ISD::UNINDEXED)
3002 VT = ST->getStoredVT();
3003 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3004 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3006 Ptr = ST->getBasePtr();
3011 if (Ptr.Val->hasOneUse())
3014 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3015 E = Ptr.Val->use_end(); I != E; ++I) {
3018 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3023 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3024 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3026 std::swap(BasePtr, Offset);
3030 // Try turning it into a post-indexed load / store except when
3031 // 1) All uses are load / store ops that use it as base ptr.
3032 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3033 // nor a successor of N. Otherwise, if Op is folded that would
3037 bool TryNext = false;
3038 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
3039 EE = BasePtr.Val->use_end(); II != EE; ++II) {
3044 // If all the uses are load / store addresses, then don't do the
3046 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
3047 bool RealUse = false;
3048 for (SDNode::use_iterator III = Use->use_begin(),
3049 EEE = Use->use_end(); III != EEE; ++III) {
3050 SDNode *UseUse = *III;
3051 if (!((UseUse->getOpcode() == ISD::LOAD &&
3052 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
3053 (UseUse->getOpcode() == ISD::STORE) &&
3054 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
3068 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
3069 SDOperand Result = isLoad
3070 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
3071 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3074 DOUT << "\nReplacing.5 "; DEBUG(N->dump());
3075 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3077 std::vector<SDNode*> NowDead;
3079 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3081 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3084 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3088 // Nodes can end up on the worklist more than once. Make sure we do
3089 // not process a node that has been replaced.
3090 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3091 removeFromWorkList(NowDead[i]);
3092 // Finally, since the node is now dead, remove it from the graph.
3095 // Replace the uses of Use with uses of the updated base value.
3096 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
3097 Result.getValue(isLoad ? 1 : 0),
3099 removeFromWorkList(Op);
3100 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3101 removeFromWorkList(NowDead[i]);
3112 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
3113 LoadSDNode *LD = cast<LoadSDNode>(N);
3114 SDOperand Chain = LD->getChain();
3115 SDOperand Ptr = LD->getBasePtr();
3117 // If there are no uses of the loaded value, change uses of the chain value
3118 // into uses of the chain input (i.e. delete the dead load).
3119 if (N->hasNUsesOfValue(0, 0))
3120 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
3122 // If this load is directly stored, replace the load value with the stored
3124 // TODO: Handle store large -> read small portion.
3125 // TODO: Handle TRUNCSTORE/LOADEXT
3126 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3127 if (ISD::isNON_TRUNCStore(Chain.Val)) {
3128 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
3129 if (PrevST->getBasePtr() == Ptr &&
3130 PrevST->getValue().getValueType() == N->getValueType(0))
3131 return CombineTo(N, Chain.getOperand(1), Chain);
3136 // Walk up chain skipping non-aliasing memory nodes.
3137 SDOperand BetterChain = FindBetterChain(N, Chain);
3139 // If there is a better chain.
3140 if (Chain != BetterChain) {
3143 // Replace the chain to void dependency.
3144 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3145 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
3146 LD->getSrcValue(), LD->getSrcValueOffset());
3148 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
3149 LD->getValueType(0),
3150 BetterChain, Ptr, LD->getSrcValue(),
3151 LD->getSrcValueOffset(),
3155 // Create token factor to keep old chain connected.
3156 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
3157 Chain, ReplLoad.getValue(1));
3159 // Replace uses with load result and token factor. Don't add users
3161 return CombineTo(N, ReplLoad.getValue(0), Token, false);
3165 // Try transforming N to an indexed load.
3166 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3167 return SDOperand(N, 0);
3172 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
3173 StoreSDNode *ST = cast<StoreSDNode>(N);
3174 SDOperand Chain = ST->getChain();
3175 SDOperand Value = ST->getValue();
3176 SDOperand Ptr = ST->getBasePtr();
3178 // If this is a store of a bit convert, store the input value.
3179 // FIXME: This needs to know that the resultant store does not need a
3180 // higher alignment than the original.
3181 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
3182 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
3183 ST->getSrcValueOffset());
3186 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
3187 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
3188 if (Value.getOpcode() != ISD::TargetConstantFP) {
3190 switch (CFP->getValueType(0)) {
3191 default: assert(0 && "Unknown FP type");
3193 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
3194 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
3195 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3196 ST->getSrcValueOffset());
3200 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
3201 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
3202 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3203 ST->getSrcValueOffset());
3204 } else if (TLI.isTypeLegal(MVT::i32)) {
3205 // Many FP stores are not make apparent until after legalize, e.g. for
3206 // argument passing. Since this is so common, custom legalize the
3207 // 64-bit integer store into two 32-bit stores.
3208 uint64_t Val = DoubleToBits(CFP->getValue());
3209 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
3210 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
3211 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
3213 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
3214 ST->getSrcValueOffset());
3215 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3216 DAG.getConstant(4, Ptr.getValueType()));
3217 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
3218 ST->getSrcValueOffset()+4);
3219 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
3227 // Walk up chain skipping non-aliasing memory nodes.
3228 SDOperand BetterChain = FindBetterChain(N, Chain);
3230 // If there is a better chain.
3231 if (Chain != BetterChain) {
3232 // Replace the chain to avoid dependency.
3233 SDOperand ReplStore;
3234 if (ST->isTruncatingStore()) {
3235 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
3236 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT());
3238 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
3239 ST->getSrcValue(), ST->getSrcValueOffset());
3242 // Create token to keep both nodes around.
3244 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
3246 // Don't add users to work list.
3247 return CombineTo(N, Token, false);
3251 // Try transforming N to an indexed store.
3252 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3253 return SDOperand(N, 0);
3258 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
3259 SDOperand InVec = N->getOperand(0);
3260 SDOperand InVal = N->getOperand(1);
3261 SDOperand EltNo = N->getOperand(2);
3263 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
3264 // vector with the inserted element.
3265 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3266 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3267 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3268 if (Elt < Ops.size())
3270 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
3271 &Ops[0], Ops.size());
3277 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
3278 SDOperand InVec = N->getOperand(0);
3279 SDOperand InVal = N->getOperand(1);
3280 SDOperand EltNo = N->getOperand(2);
3281 SDOperand NumElts = N->getOperand(3);
3282 SDOperand EltType = N->getOperand(4);
3284 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
3285 // vector with the inserted element.
3286 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3287 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3288 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3289 if (Elt < Ops.size()-2)
3291 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
3292 &Ops[0], Ops.size());
3298 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
3299 unsigned NumInScalars = N->getNumOperands()-2;
3300 SDOperand NumElts = N->getOperand(NumInScalars);
3301 SDOperand EltType = N->getOperand(NumInScalars+1);
3303 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
3304 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
3305 // two distinct vectors, turn this into a shuffle node.
3306 SDOperand VecIn1, VecIn2;
3307 for (unsigned i = 0; i != NumInScalars; ++i) {
3308 // Ignore undef inputs.
3309 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3311 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
3312 // constant index, bail out.
3313 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
3314 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
3315 VecIn1 = VecIn2 = SDOperand(0, 0);
3319 // If the input vector type disagrees with the result of the vbuild_vector,
3320 // we can't make a shuffle.
3321 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
3322 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
3323 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
3324 VecIn1 = VecIn2 = SDOperand(0, 0);
3328 // Otherwise, remember this. We allow up to two distinct input vectors.
3329 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
3332 if (VecIn1.Val == 0) {
3333 VecIn1 = ExtractedFromVec;
3334 } else if (VecIn2.Val == 0) {
3335 VecIn2 = ExtractedFromVec;
3338 VecIn1 = VecIn2 = SDOperand(0, 0);
3343 // If everything is good, we can make a shuffle operation.
3345 SmallVector<SDOperand, 8> BuildVecIndices;
3346 for (unsigned i = 0; i != NumInScalars; ++i) {
3347 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
3348 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
3352 SDOperand Extract = N->getOperand(i);
3354 // If extracting from the first vector, just use the index directly.
3355 if (Extract.getOperand(0) == VecIn1) {
3356 BuildVecIndices.push_back(Extract.getOperand(1));
3360 // Otherwise, use InIdx + VecSize
3361 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
3362 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
3363 TLI.getPointerTy()));
3366 // Add count and size info.
3367 BuildVecIndices.push_back(NumElts);
3368 BuildVecIndices.push_back(DAG.getValueType(TLI.getPointerTy()));
3370 // Return the new VVECTOR_SHUFFLE node.
3376 // Use an undef vbuild_vector as input for the second operand.
3377 std::vector<SDOperand> UnOps(NumInScalars,
3378 DAG.getNode(ISD::UNDEF,
3379 cast<VTSDNode>(EltType)->getVT()));
3380 UnOps.push_back(NumElts);
3381 UnOps.push_back(EltType);
3382 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3383 &UnOps[0], UnOps.size());
3384 AddToWorkList(Ops[1].Val);
3386 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3387 &BuildVecIndices[0], BuildVecIndices.size());
3390 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
3396 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
3397 SDOperand ShufMask = N->getOperand(2);
3398 unsigned NumElts = ShufMask.getNumOperands();
3400 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3401 bool isIdentity = true;
3402 for (unsigned i = 0; i != NumElts; ++i) {
3403 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3404 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3409 if (isIdentity) return N->getOperand(0);
3411 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3413 for (unsigned i = 0; i != NumElts; ++i) {
3414 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3415 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3420 if (isIdentity) return N->getOperand(1);
3422 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3424 bool isUnary = true;
3425 bool isSplat = true;
3427 unsigned BaseIdx = 0;
3428 for (unsigned i = 0; i != NumElts; ++i)
3429 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3430 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3431 int V = (Idx < NumElts) ? 0 : 1;
3445 SDOperand N0 = N->getOperand(0);
3446 SDOperand N1 = N->getOperand(1);
3447 // Normalize unary shuffle so the RHS is undef.
3448 if (isUnary && VecNum == 1)
3451 // If it is a splat, check if the argument vector is a build_vector with
3452 // all scalar elements the same.
3455 if (V->getOpcode() == ISD::BIT_CONVERT)
3456 V = V->getOperand(0).Val;
3457 if (V->getOpcode() == ISD::BUILD_VECTOR) {
3458 unsigned NumElems = V->getNumOperands()-2;
3459 if (NumElems > BaseIdx) {
3461 bool AllSame = true;
3462 for (unsigned i = 0; i != NumElems; ++i) {
3463 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3464 Base = V->getOperand(i);
3468 // Splat of <u, u, u, u>, return <u, u, u, u>
3471 for (unsigned i = 0; i != NumElems; ++i) {
3472 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3473 V->getOperand(i) != Base) {
3478 // Splat of <x, x, x, x>, return <x, x, x, x>
3485 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3487 if (isUnary || N0 == N1) {
3488 if (N0.getOpcode() == ISD::UNDEF)
3489 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
3490 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3492 SmallVector<SDOperand, 8> MappedOps;
3493 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
3494 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3495 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3496 MappedOps.push_back(ShufMask.getOperand(i));
3499 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3500 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3503 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
3504 &MappedOps[0], MappedOps.size());
3505 AddToWorkList(ShufMask.Val);
3506 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3508 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3515 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3516 SDOperand ShufMask = N->getOperand(2);
3517 unsigned NumElts = ShufMask.getNumOperands()-2;
3519 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3520 bool isIdentity = true;
3521 for (unsigned i = 0; i != NumElts; ++i) {
3522 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3523 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3528 if (isIdentity) return N->getOperand(0);
3530 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3532 for (unsigned i = 0; i != NumElts; ++i) {
3533 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3534 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3539 if (isIdentity) return N->getOperand(1);
3541 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3543 bool isUnary = true;
3544 bool isSplat = true;
3546 unsigned BaseIdx = 0;
3547 for (unsigned i = 0; i != NumElts; ++i)
3548 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3549 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3550 int V = (Idx < NumElts) ? 0 : 1;
3564 SDOperand N0 = N->getOperand(0);
3565 SDOperand N1 = N->getOperand(1);
3566 // Normalize unary shuffle so the RHS is undef.
3567 if (isUnary && VecNum == 1)
3570 // If it is a splat, check if the argument vector is a build_vector with
3571 // all scalar elements the same.
3575 // If this is a vbit convert that changes the element type of the vector but
3576 // not the number of vector elements, look through it. Be careful not to
3577 // look though conversions that change things like v4f32 to v2f64.
3578 if (V->getOpcode() == ISD::VBIT_CONVERT) {
3579 SDOperand ConvInput = V->getOperand(0);
3580 if (ConvInput.getValueType() == MVT::Vector &&
3582 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2))
3586 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3587 unsigned NumElems = V->getNumOperands()-2;
3588 if (NumElems > BaseIdx) {
3590 bool AllSame = true;
3591 for (unsigned i = 0; i != NumElems; ++i) {
3592 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3593 Base = V->getOperand(i);
3597 // Splat of <u, u, u, u>, return <u, u, u, u>
3600 for (unsigned i = 0; i != NumElems; ++i) {
3601 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3602 V->getOperand(i) != Base) {
3607 // Splat of <x, x, x, x>, return <x, x, x, x>
3614 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3616 if (isUnary || N0 == N1) {
3617 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3619 SmallVector<SDOperand, 8> MappedOps;
3620 for (unsigned i = 0; i != NumElts; ++i) {
3621 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3622 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3623 MappedOps.push_back(ShufMask.getOperand(i));
3626 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3627 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3630 // Add the type/#elts values.
3631 MappedOps.push_back(ShufMask.getOperand(NumElts));
3632 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3634 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3635 &MappedOps[0], MappedOps.size());
3636 AddToWorkList(ShufMask.Val);
3638 // Build the undef vector.
3639 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3640 for (unsigned i = 0; i != NumElts; ++i)
3641 MappedOps[i] = UDVal;
3642 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3643 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3644 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3645 &MappedOps[0], MappedOps.size());
3647 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3648 N0, UDVal, ShufMask,
3649 MappedOps[NumElts], MappedOps[NumElts+1]);
3655 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3656 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3657 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3658 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3659 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3660 SDOperand LHS = N->getOperand(0);
3661 SDOperand RHS = N->getOperand(1);
3662 if (N->getOpcode() == ISD::VAND) {
3663 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3664 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3665 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3666 RHS = RHS.getOperand(0);
3667 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3668 std::vector<SDOperand> IdxOps;
3669 unsigned NumOps = RHS.getNumOperands();
3670 unsigned NumElts = NumOps-2;
3671 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3672 for (unsigned i = 0; i != NumElts; ++i) {
3673 SDOperand Elt = RHS.getOperand(i);
3674 if (!isa<ConstantSDNode>(Elt))
3676 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3677 IdxOps.push_back(DAG.getConstant(i, EVT));
3678 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3679 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3684 // Let's see if the target supports this vector_shuffle.
3685 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3688 // Return the new VVECTOR_SHUFFLE node.
3689 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3690 SDOperand EVTNode = DAG.getValueType(EVT);
3691 std::vector<SDOperand> Ops;
3692 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3695 AddToWorkList(LHS.Val);
3696 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3697 ZeroOps.push_back(NumEltsNode);
3698 ZeroOps.push_back(EVTNode);
3699 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3700 &ZeroOps[0], ZeroOps.size()));
3701 IdxOps.push_back(NumEltsNode);
3702 IdxOps.push_back(EVTNode);
3703 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3704 &IdxOps[0], IdxOps.size()));
3705 Ops.push_back(NumEltsNode);
3706 Ops.push_back(EVTNode);
3707 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3708 &Ops[0], Ops.size());
3709 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3710 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3711 DstVecSize, DstVecEVT);
3719 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3720 /// the scalar operation of the vop if it is operating on an integer vector
3721 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3722 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3723 ISD::NodeType FPOp) {
3724 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3725 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3726 SDOperand LHS = N->getOperand(0);
3727 SDOperand RHS = N->getOperand(1);
3728 SDOperand Shuffle = XformToShuffleWithZero(N);
3729 if (Shuffle.Val) return Shuffle;
3731 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3733 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3734 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3735 SmallVector<SDOperand, 8> Ops;
3736 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3737 SDOperand LHSOp = LHS.getOperand(i);
3738 SDOperand RHSOp = RHS.getOperand(i);
3739 // If these two elements can't be folded, bail out.
3740 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3741 LHSOp.getOpcode() != ISD::Constant &&
3742 LHSOp.getOpcode() != ISD::ConstantFP) ||
3743 (RHSOp.getOpcode() != ISD::UNDEF &&
3744 RHSOp.getOpcode() != ISD::Constant &&
3745 RHSOp.getOpcode() != ISD::ConstantFP))
3747 // Can't fold divide by zero.
3748 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3749 if ((RHSOp.getOpcode() == ISD::Constant &&
3750 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3751 (RHSOp.getOpcode() == ISD::ConstantFP &&
3752 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3755 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3756 AddToWorkList(Ops.back().Val);
3757 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3758 Ops.back().getOpcode() == ISD::Constant ||
3759 Ops.back().getOpcode() == ISD::ConstantFP) &&
3760 "Scalar binop didn't fold!");
3763 if (Ops.size() == LHS.getNumOperands()-2) {
3764 Ops.push_back(*(LHS.Val->op_end()-2));
3765 Ops.push_back(*(LHS.Val->op_end()-1));
3766 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3773 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3774 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3776 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3777 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3778 // If we got a simplified select_cc node back from SimplifySelectCC, then
3779 // break it down into a new SETCC node, and a new SELECT node, and then return
3780 // the SELECT node, since we were called with a SELECT node.
3782 // Check to see if we got a select_cc back (to turn into setcc/select).
3783 // Otherwise, just return whatever node we got back, like fabs.
3784 if (SCC.getOpcode() == ISD::SELECT_CC) {
3785 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3786 SCC.getOperand(0), SCC.getOperand(1),
3788 AddToWorkList(SETCC.Val);
3789 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3790 SCC.getOperand(3), SETCC);
3797 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3798 /// are the two values being selected between, see if we can simplify the
3799 /// select. Callers of this should assume that TheSelect is deleted if this
3800 /// returns true. As such, they should return the appropriate thing (e.g. the
3801 /// node) back to the top-level of the DAG combiner loop to avoid it being
3804 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3807 // If this is a select from two identical things, try to pull the operation
3808 // through the select.
3809 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3810 // If this is a load and the token chain is identical, replace the select
3811 // of two loads with a load through a select of the address to load from.
3812 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3813 // constants have been dropped into the constant pool.
3814 if (LHS.getOpcode() == ISD::LOAD &&
3815 // Token chains must be identical.
3816 LHS.getOperand(0) == RHS.getOperand(0)) {
3817 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3818 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3820 // If this is an EXTLOAD, the VT's must match.
3821 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3822 // FIXME: this conflates two src values, discarding one. This is not
3823 // the right thing to do, but nothing uses srcvalues now. When they do,
3824 // turn SrcValue into a list of locations.
3826 if (TheSelect->getOpcode() == ISD::SELECT) {
3827 // Check that the condition doesn't reach either load. If so, folding
3828 // this will induce a cycle into the DAG.
3829 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
3830 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
3831 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
3832 TheSelect->getOperand(0), LLD->getBasePtr(),
3836 // Check that the condition doesn't reach either load. If so, folding
3837 // this will induce a cycle into the DAG.
3838 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
3839 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
3840 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
3841 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
3842 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
3843 TheSelect->getOperand(0),
3844 TheSelect->getOperand(1),
3845 LLD->getBasePtr(), RLD->getBasePtr(),
3846 TheSelect->getOperand(4));
3852 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
3853 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
3854 Addr,LLD->getSrcValue(),
3855 LLD->getSrcValueOffset());
3857 Load = DAG.getExtLoad(LLD->getExtensionType(),
3858 TheSelect->getValueType(0),
3859 LLD->getChain(), Addr, LLD->getSrcValue(),
3860 LLD->getSrcValueOffset(),
3861 LLD->getLoadedVT());
3863 // Users of the select now use the result of the load.
3864 CombineTo(TheSelect, Load);
3866 // Users of the old loads now use the new load's chain. We know the
3867 // old-load value is dead now.
3868 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3869 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3879 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3880 SDOperand N2, SDOperand N3,
3883 MVT::ValueType VT = N2.getValueType();
3884 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3885 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3886 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3888 // Determine if the condition we're dealing with is constant
3889 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3890 if (SCC.Val) AddToWorkList(SCC.Val);
3891 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3893 // fold select_cc true, x, y -> x
3894 if (SCCC && SCCC->getValue())
3896 // fold select_cc false, x, y -> y
3897 if (SCCC && SCCC->getValue() == 0)
3900 // Check to see if we can simplify the select into an fabs node
3901 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3902 // Allow either -0.0 or 0.0
3903 if (CFP->getValue() == 0.0) {
3904 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3905 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3906 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3907 N2 == N3.getOperand(0))
3908 return DAG.getNode(ISD::FABS, VT, N0);
3910 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3911 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3912 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3913 N2.getOperand(0) == N3)
3914 return DAG.getNode(ISD::FABS, VT, N3);
3918 // Check to see if we can perform the "gzip trick", transforming
3919 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3920 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3921 MVT::isInteger(N0.getValueType()) &&
3922 MVT::isInteger(N2.getValueType()) &&
3923 (N1C->isNullValue() || // (a < 0) ? b : 0
3924 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3925 MVT::ValueType XType = N0.getValueType();
3926 MVT::ValueType AType = N2.getValueType();
3927 if (XType >= AType) {
3928 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3929 // single-bit constant.
3930 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3931 unsigned ShCtV = Log2_64(N2C->getValue());
3932 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3933 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3934 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3935 AddToWorkList(Shift.Val);
3936 if (XType > AType) {
3937 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3938 AddToWorkList(Shift.Val);
3940 return DAG.getNode(ISD::AND, AType, Shift, N2);
3942 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3943 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3944 TLI.getShiftAmountTy()));
3945 AddToWorkList(Shift.Val);
3946 if (XType > AType) {
3947 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3948 AddToWorkList(Shift.Val);
3950 return DAG.getNode(ISD::AND, AType, Shift, N2);
3954 // fold select C, 16, 0 -> shl C, 4
3955 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3956 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3957 // Get a SetCC of the condition
3958 // FIXME: Should probably make sure that setcc is legal if we ever have a
3959 // target where it isn't.
3960 SDOperand Temp, SCC;
3961 // cast from setcc result type to select result type
3962 if (AfterLegalize) {
3963 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3964 if (N2.getValueType() < SCC.getValueType())
3965 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3967 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3969 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3970 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3972 AddToWorkList(SCC.Val);
3973 AddToWorkList(Temp.Val);
3974 // shl setcc result by log2 n2c
3975 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3976 DAG.getConstant(Log2_64(N2C->getValue()),
3977 TLI.getShiftAmountTy()));
3980 // Check to see if this is the equivalent of setcc
3981 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3982 // otherwise, go ahead with the folds.
3983 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3984 MVT::ValueType XType = N0.getValueType();
3985 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3986 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3987 if (Res.getValueType() != VT)
3988 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3992 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3993 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3994 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3995 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3996 return DAG.getNode(ISD::SRL, XType, Ctlz,
3997 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3998 TLI.getShiftAmountTy()));
4000 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4001 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4002 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
4004 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
4005 DAG.getConstant(~0ULL, XType));
4006 return DAG.getNode(ISD::SRL, XType,
4007 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
4008 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4009 TLI.getShiftAmountTy()));
4011 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
4012 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
4013 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
4014 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4015 TLI.getShiftAmountTy()));
4016 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
4020 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
4021 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4022 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
4023 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
4024 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
4025 MVT::ValueType XType = N0.getValueType();
4026 if (SubC->isNullValue() && MVT::isInteger(XType)) {
4027 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4028 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4029 TLI.getShiftAmountTy()));
4030 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4031 AddToWorkList(Shift.Val);
4032 AddToWorkList(Add.Val);
4033 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4041 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
4042 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
4043 SDOperand N1, ISD::CondCode Cond,
4044 bool foldBooleans) {
4045 TargetLowering::DAGCombinerInfo
4046 DagCombineInfo(DAG, !AfterLegalize, false, this);
4047 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
4050 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4051 /// return a DAG expression to select that will generate the same value by
4052 /// multiplying by a magic number. See:
4053 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4054 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4055 std::vector<SDNode*> Built;
4056 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4058 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4064 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4065 /// return a DAG expression to select that will generate the same value by
4066 /// multiplying by a magic number. See:
4067 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4068 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4069 std::vector<SDNode*> Built;
4070 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4072 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4078 /// FindBaseOffset - Return true if base is known not to alias with anything
4079 /// but itself. Provides base object and offset as results.
4080 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4081 // Assume it is a primitive operation.
4082 Base = Ptr; Offset = 0;
4084 // If it's an adding a simple constant then integrate the offset.
4085 if (Base.getOpcode() == ISD::ADD) {
4086 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4087 Base = Base.getOperand(0);
4088 Offset += C->getValue();
4092 // If it's any of the following then it can't alias with anything but itself.
4093 return isa<FrameIndexSDNode>(Base) ||
4094 isa<ConstantPoolSDNode>(Base) ||
4095 isa<GlobalAddressSDNode>(Base);
4098 /// isAlias - Return true if there is any possibility that the two addresses
4100 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4101 const Value *SrcValue1, int SrcValueOffset1,
4102 SDOperand Ptr2, int64_t Size2,
4103 const Value *SrcValue2, int SrcValueOffset2)
4105 // If they are the same then they must be aliases.
4106 if (Ptr1 == Ptr2) return true;
4108 // Gather base node and offset information.
4109 SDOperand Base1, Base2;
4110 int64_t Offset1, Offset2;
4111 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4112 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4114 // If they have a same base address then...
4115 if (Base1 == Base2) {
4116 // Check to see if the addresses overlap.
4117 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4120 // If we know both bases then they can't alias.
4121 if (KnownBase1 && KnownBase2) return false;
4123 if (CombinerGlobalAA) {
4124 // Use alias analysis information.
4125 int Overlap1 = Size1 + SrcValueOffset1 + Offset1;
4126 int Overlap2 = Size2 + SrcValueOffset2 + Offset2;
4127 AliasAnalysis::AliasResult AAResult =
4128 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4129 if (AAResult == AliasAnalysis::NoAlias)
4133 // Otherwise we have to assume they alias.
4137 /// FindAliasInfo - Extracts the relevant alias information from the memory
4138 /// node. Returns true if the operand was a load.
4139 bool DAGCombiner::FindAliasInfo(SDNode *N,
4140 SDOperand &Ptr, int64_t &Size,
4141 const Value *&SrcValue, int &SrcValueOffset) {
4142 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4143 Ptr = LD->getBasePtr();
4144 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4145 SrcValue = LD->getSrcValue();
4146 SrcValueOffset = LD->getSrcValueOffset();
4148 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4149 Ptr = ST->getBasePtr();
4150 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4151 SrcValue = ST->getSrcValue();
4152 SrcValueOffset = ST->getSrcValueOffset();
4154 assert(0 && "FindAliasInfo expected a memory operand");
4160 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4161 /// looking for aliasing nodes and adding them to the Aliases vector.
4162 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4163 SmallVector<SDOperand, 8> &Aliases) {
4164 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4165 std::set<SDNode *> Visited; // Visited node set.
4167 // Get alias information for node.
4170 const Value *SrcValue;
4172 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4175 Chains.push_back(OriginalChain);
4177 // Look at each chain and determine if it is an alias. If so, add it to the
4178 // aliases list. If not, then continue up the chain looking for the next
4180 while (!Chains.empty()) {
4181 SDOperand Chain = Chains.back();
4184 // Don't bother if we've been before.
4185 if (Visited.find(Chain.Val) != Visited.end()) continue;
4186 Visited.insert(Chain.Val);
4188 switch (Chain.getOpcode()) {
4189 case ISD::EntryToken:
4190 // Entry token is ideal chain operand, but handled in FindBetterChain.
4195 // Get alias information for Chain.
4198 const Value *OpSrcValue;
4199 int OpSrcValueOffset;
4200 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4201 OpSrcValue, OpSrcValueOffset);
4203 // If chain is alias then stop here.
4204 if (!(IsLoad && IsOpLoad) &&
4205 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4206 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4207 Aliases.push_back(Chain);
4209 // Look further up the chain.
4210 Chains.push_back(Chain.getOperand(0));
4211 // Clean up old chain.
4212 AddToWorkList(Chain.Val);
4217 case ISD::TokenFactor:
4218 // We have to check each of the operands of the token factor, so we queue
4219 // then up. Adding the operands to the queue (stack) in reverse order
4220 // maintains the original order and increases the likelihood that getNode
4221 // will find a matching token factor (CSE.)
4222 for (unsigned n = Chain.getNumOperands(); n;)
4223 Chains.push_back(Chain.getOperand(--n));
4224 // Eliminate the token factor if we can.
4225 AddToWorkList(Chain.Val);
4229 // For all other instructions we will just have to take what we can get.
4230 Aliases.push_back(Chain);
4236 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4237 /// for a better chain (aliasing node.)
4238 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4239 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4241 // Accumulate all the aliases to this node.
4242 GatherAllAliases(N, OldChain, Aliases);
4244 if (Aliases.size() == 0) {
4245 // If no operands then chain to entry token.
4246 return DAG.getEntryNode();
4247 } else if (Aliases.size() == 1) {
4248 // If a single operand then chain to it. We don't need to revisit it.
4252 // Construct a custom tailored token factor.
4253 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4254 &Aliases[0], Aliases.size());
4256 // Make sure the old chain gets cleaned up.
4257 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4262 // SelectionDAG::Combine - This is the entry point for the file.
4264 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4265 if (!RunningAfterLegalize && ViewDAGCombine1)
4267 if (RunningAfterLegalize && ViewDAGCombine2)
4269 /// run - This is the main entry point to this class.
4271 DAGCombiner(*this, AA).Run(RunningAfterLegalize);