1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
41 STATISTIC(NodesCombined , "Number of dag nodes combined");
42 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
43 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
44 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
45 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
67 std::vector<SDNode*> WorkList;
69 // AA - Used for DAG load/store alias analysis.
72 /// AddUsersToWorkList - When an instruction is simplified, add all users of
73 /// the instruction to the work lists because they might get more simplified
76 void AddUsersToWorkList(SDNode *N) {
77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
82 /// visit - call the node-specific routine that knows how to fold each
83 /// particular type of node.
84 SDValue visit(SDNode *N);
87 /// AddToWorkList - Add to the work list making sure it's instance is at the
88 /// the back (next to be processed.)
89 void AddToWorkList(SDNode *N) {
90 removeFromWorkList(N);
91 WorkList.push_back(N);
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
105 return CombineTo(N, &Res, 1, AddTo);
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
110 SDValue To[] = { Res0, Res1 };
111 return CombineTo(N, To, 2, AddTo);
114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
118 /// SimplifyDemandedBits - Check the specified integer node value to see if
119 /// it can be simplified or if things it uses can be simplified by bit
120 /// propagation. If so, return true.
121 bool SimplifyDemandedBits(SDValue Op) {
122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
123 APInt Demanded = APInt::getAllOnesValue(BitWidth);
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
136 SDValue PromoteIntBinOp(SDValue Op);
137 SDValue PromoteIntShiftOp(SDValue Op);
138 SDValue PromoteExtend(SDValue Op);
139 bool PromoteLoad(SDValue Op);
141 /// combine - call the node-specific routine that knows how to fold each
142 /// particular type of node. If that doesn't do anything, try the
143 /// target-specific DAG combines.
144 SDValue combine(SDNode *N);
146 // Visitation implementation - Implement dag node combining for different
147 // node types. The semantics are as follows:
149 // SDValue.getNode() == 0 - No change was made
150 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
151 // otherwise - N should be replaced by the returned Operand.
153 SDValue visitTokenFactor(SDNode *N);
154 SDValue visitMERGE_VALUES(SDNode *N);
155 SDValue visitADD(SDNode *N);
156 SDValue visitSUB(SDNode *N);
157 SDValue visitADDC(SDNode *N);
158 SDValue visitADDE(SDNode *N);
159 SDValue visitMUL(SDNode *N);
160 SDValue visitSDIV(SDNode *N);
161 SDValue visitUDIV(SDNode *N);
162 SDValue visitSREM(SDNode *N);
163 SDValue visitUREM(SDNode *N);
164 SDValue visitMULHU(SDNode *N);
165 SDValue visitMULHS(SDNode *N);
166 SDValue visitSMUL_LOHI(SDNode *N);
167 SDValue visitUMUL_LOHI(SDNode *N);
168 SDValue visitSMULO(SDNode *N);
169 SDValue visitUMULO(SDNode *N);
170 SDValue visitSDIVREM(SDNode *N);
171 SDValue visitUDIVREM(SDNode *N);
172 SDValue visitAND(SDNode *N);
173 SDValue visitOR(SDNode *N);
174 SDValue visitXOR(SDNode *N);
175 SDValue SimplifyVBinOp(SDNode *N);
176 SDValue visitSHL(SDNode *N);
177 SDValue visitSRA(SDNode *N);
178 SDValue visitSRL(SDNode *N);
179 SDValue visitCTLZ(SDNode *N);
180 SDValue visitCTTZ(SDNode *N);
181 SDValue visitCTPOP(SDNode *N);
182 SDValue visitSELECT(SDNode *N);
183 SDValue visitSELECT_CC(SDNode *N);
184 SDValue visitSETCC(SDNode *N);
185 SDValue visitSIGN_EXTEND(SDNode *N);
186 SDValue visitZERO_EXTEND(SDNode *N);
187 SDValue visitANY_EXTEND(SDNode *N);
188 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
189 SDValue visitTRUNCATE(SDNode *N);
190 SDValue visitBITCAST(SDNode *N);
191 SDValue visitBUILD_PAIR(SDNode *N);
192 SDValue visitFADD(SDNode *N);
193 SDValue visitFSUB(SDNode *N);
194 SDValue visitFMUL(SDNode *N);
195 SDValue visitFDIV(SDNode *N);
196 SDValue visitFREM(SDNode *N);
197 SDValue visitFCOPYSIGN(SDNode *N);
198 SDValue visitSINT_TO_FP(SDNode *N);
199 SDValue visitUINT_TO_FP(SDNode *N);
200 SDValue visitFP_TO_SINT(SDNode *N);
201 SDValue visitFP_TO_UINT(SDNode *N);
202 SDValue visitFP_ROUND(SDNode *N);
203 SDValue visitFP_ROUND_INREG(SDNode *N);
204 SDValue visitFP_EXTEND(SDNode *N);
205 SDValue visitFNEG(SDNode *N);
206 SDValue visitFABS(SDNode *N);
207 SDValue visitBRCOND(SDNode *N);
208 SDValue visitBR_CC(SDNode *N);
209 SDValue visitLOAD(SDNode *N);
210 SDValue visitSTORE(SDNode *N);
211 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
212 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
213 SDValue visitBUILD_VECTOR(SDNode *N);
214 SDValue visitCONCAT_VECTORS(SDNode *N);
215 SDValue visitVECTOR_SHUFFLE(SDNode *N);
216 SDValue visitMEMBARRIER(SDNode *N);
218 SDValue XformToShuffleWithZero(SDNode *N);
219 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
221 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
223 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
224 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
225 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
226 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
227 SDValue N3, ISD::CondCode CC,
228 bool NotExtCompare = false);
229 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
230 DebugLoc DL, bool foldBooleans = true);
231 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
233 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
234 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
235 SDValue BuildSDIV(SDNode *N);
236 SDValue BuildUDIV(SDNode *N);
237 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
238 SDValue ReduceLoadWidth(SDNode *N);
239 SDValue ReduceLoadOpStoreWidth(SDNode *N);
240 SDValue TransformFPLoadStorePair(SDNode *N);
242 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
244 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
245 /// looking for aliasing nodes and adding them to the Aliases vector.
246 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
247 SmallVector<SDValue, 8> &Aliases);
249 /// isAlias - Return true if there is any possibility that the two addresses
251 bool isAlias(SDValue Ptr1, int64_t Size1,
252 const Value *SrcValue1, int SrcValueOffset1,
253 unsigned SrcValueAlign1,
254 const MDNode *TBAAInfo1,
255 SDValue Ptr2, int64_t Size2,
256 const Value *SrcValue2, int SrcValueOffset2,
257 unsigned SrcValueAlign2,
258 const MDNode *TBAAInfo2) const;
260 /// FindAliasInfo - Extracts the relevant alias information from the memory
261 /// node. Returns true if the operand was a load.
262 bool FindAliasInfo(SDNode *N,
263 SDValue &Ptr, int64_t &Size,
264 const Value *&SrcValue, int &SrcValueOffset,
265 unsigned &SrcValueAlignment,
266 const MDNode *&TBAAInfo) const;
268 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
269 /// looking for a better chain (aliasing node.)
270 SDValue FindBetterChain(SDNode *N, SDValue Chain);
273 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
274 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted),
275 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
277 /// Run - runs the dag combiner on all nodes in the work list
278 void Run(CombineLevel AtLevel);
280 SelectionDAG &getDAG() const { return DAG; }
282 /// getShiftAmountTy - Returns a type large enough to hold any valid
283 /// shift amount - before type legalization these can be huge.
284 EVT getShiftAmountTy(EVT LHSTy) {
285 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
288 /// isTypeLegal - This method returns true if we are running before type
289 /// legalization or if the specified VT is legal.
290 bool isTypeLegal(const EVT &VT) {
291 if (!LegalTypes) return true;
292 return TLI.isTypeLegal(VT);
299 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
300 /// nodes from the worklist.
301 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
304 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
306 virtual void NodeDeleted(SDNode *N, SDNode *E) {
307 DC.removeFromWorkList(N);
310 virtual void NodeUpdated(SDNode *N) {
316 //===----------------------------------------------------------------------===//
317 // TargetLowering::DAGCombinerInfo implementation
318 //===----------------------------------------------------------------------===//
320 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
321 ((DAGCombiner*)DC)->AddToWorkList(N);
324 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
325 ((DAGCombiner*)DC)->removeFromWorkList(N);
328 SDValue TargetLowering::DAGCombinerInfo::
329 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
330 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
333 SDValue TargetLowering::DAGCombinerInfo::
334 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
335 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
339 SDValue TargetLowering::DAGCombinerInfo::
340 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
341 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
344 void TargetLowering::DAGCombinerInfo::
345 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
346 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
349 //===----------------------------------------------------------------------===//
351 //===----------------------------------------------------------------------===//
353 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
354 /// specified expression for the same cost as the expression itself, or 2 if we
355 /// can compute the negated form more cheaply than the expression itself.
356 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
357 unsigned Depth = 0) {
358 // No compile time optimizations on this type.
359 if (Op.getValueType() == MVT::ppcf128)
362 // fneg is removable even if it has multiple uses.
363 if (Op.getOpcode() == ISD::FNEG) return 2;
365 // Don't allow anything with multiple uses.
366 if (!Op.hasOneUse()) return 0;
368 // Don't recurse exponentially.
369 if (Depth > 6) return 0;
371 switch (Op.getOpcode()) {
372 default: return false;
373 case ISD::ConstantFP:
374 // Don't invert constant FP values after legalize. The negated constant
375 // isn't necessarily legal.
376 return LegalOperations ? 0 : 1;
378 // FIXME: determine better conditions for this xform.
379 if (!UnsafeFPMath) return 0;
381 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
382 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
384 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
385 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
387 // We can't turn -(A-B) into B-A when we honor signed zeros.
388 if (!UnsafeFPMath) return 0;
390 // fold (fneg (fsub A, B)) -> (fsub B, A)
395 if (HonorSignDependentRoundingFPMath()) return 0;
397 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
398 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
401 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
406 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
410 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
411 /// returns the newly negated expression.
412 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
413 bool LegalOperations, unsigned Depth = 0) {
414 // fneg is removable even if it has multiple uses.
415 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
417 // Don't allow anything with multiple uses.
418 assert(Op.hasOneUse() && "Unknown reuse!");
420 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
421 switch (Op.getOpcode()) {
422 default: llvm_unreachable("Unknown code");
423 case ISD::ConstantFP: {
424 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
426 return DAG.getConstantFP(V, Op.getValueType());
429 // FIXME: determine better conditions for this xform.
430 assert(UnsafeFPMath);
432 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
433 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
434 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
435 GetNegatedExpression(Op.getOperand(0), DAG,
436 LegalOperations, Depth+1),
438 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
439 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
440 GetNegatedExpression(Op.getOperand(1), DAG,
441 LegalOperations, Depth+1),
444 // We can't turn -(A-B) into B-A when we honor signed zeros.
445 assert(UnsafeFPMath);
447 // fold (fneg (fsub 0, B)) -> B
448 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
449 if (N0CFP->getValueAPF().isZero())
450 return Op.getOperand(1);
452 // fold (fneg (fsub A, B)) -> (fsub B, A)
453 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
454 Op.getOperand(1), Op.getOperand(0));
458 assert(!HonorSignDependentRoundingFPMath());
460 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
461 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
462 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
463 GetNegatedExpression(Op.getOperand(0), DAG,
464 LegalOperations, Depth+1),
467 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
468 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
470 GetNegatedExpression(Op.getOperand(1), DAG,
471 LegalOperations, Depth+1));
475 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
476 GetNegatedExpression(Op.getOperand(0), DAG,
477 LegalOperations, Depth+1));
479 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
480 GetNegatedExpression(Op.getOperand(0), DAG,
481 LegalOperations, Depth+1),
487 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
488 // that selects between the values 1 and 0, making it equivalent to a setcc.
489 // Also, set the incoming LHS, RHS, and CC references to the appropriate
490 // nodes based on the type of node we are checking. This simplifies life a
491 // bit for the callers.
492 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
494 if (N.getOpcode() == ISD::SETCC) {
495 LHS = N.getOperand(0);
496 RHS = N.getOperand(1);
497 CC = N.getOperand(2);
500 if (N.getOpcode() == ISD::SELECT_CC &&
501 N.getOperand(2).getOpcode() == ISD::Constant &&
502 N.getOperand(3).getOpcode() == ISD::Constant &&
503 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
504 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
505 LHS = N.getOperand(0);
506 RHS = N.getOperand(1);
507 CC = N.getOperand(4);
513 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
514 // one use. If this is true, it allows the users to invert the operation for
515 // free when it is profitable to do so.
516 static bool isOneUseSetCC(SDValue N) {
518 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
523 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
524 SDValue N0, SDValue N1) {
525 EVT VT = N0.getValueType();
526 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
527 if (isa<ConstantSDNode>(N1)) {
528 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
530 DAG.FoldConstantArithmetic(Opc, VT,
531 cast<ConstantSDNode>(N0.getOperand(1)),
532 cast<ConstantSDNode>(N1));
533 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
535 if (N0.hasOneUse()) {
536 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
537 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
538 N0.getOperand(0), N1);
539 AddToWorkList(OpNode.getNode());
540 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
544 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
545 if (isa<ConstantSDNode>(N0)) {
546 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
548 DAG.FoldConstantArithmetic(Opc, VT,
549 cast<ConstantSDNode>(N1.getOperand(1)),
550 cast<ConstantSDNode>(N0));
551 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
553 if (N1.hasOneUse()) {
554 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
555 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
556 N1.getOperand(0), N0);
557 AddToWorkList(OpNode.getNode());
558 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
565 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
567 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
569 DEBUG(dbgs() << "\nReplacing.1 ";
571 dbgs() << "\nWith: ";
572 To[0].getNode()->dump(&DAG);
573 dbgs() << " and " << NumTo-1 << " other values\n";
574 for (unsigned i = 0, e = NumTo; i != e; ++i)
575 assert((!To[i].getNode() ||
576 N->getValueType(i) == To[i].getValueType()) &&
577 "Cannot combine value to value of different type!"));
578 WorkListRemover DeadNodes(*this);
579 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
582 // Push the new nodes and any users onto the worklist
583 for (unsigned i = 0, e = NumTo; i != e; ++i) {
584 if (To[i].getNode()) {
585 AddToWorkList(To[i].getNode());
586 AddUsersToWorkList(To[i].getNode());
591 // Finally, if the node is now dead, remove it from the graph. The node
592 // may not be dead if the replacement process recursively simplified to
593 // something else needing this node.
594 if (N->use_empty()) {
595 // Nodes can be reintroduced into the worklist. Make sure we do not
596 // process a node that has been replaced.
597 removeFromWorkList(N);
599 // Finally, since the node is now dead, remove it from the graph.
602 return SDValue(N, 0);
606 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
607 // Replace all uses. If any nodes become isomorphic to other nodes and
608 // are deleted, make sure to remove them from our worklist.
609 WorkListRemover DeadNodes(*this);
610 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
612 // Push the new node and any (possibly new) users onto the worklist.
613 AddToWorkList(TLO.New.getNode());
614 AddUsersToWorkList(TLO.New.getNode());
616 // Finally, if the node is now dead, remove it from the graph. The node
617 // may not be dead if the replacement process recursively simplified to
618 // something else needing this node.
619 if (TLO.Old.getNode()->use_empty()) {
620 removeFromWorkList(TLO.Old.getNode());
622 // If the operands of this node are only used by the node, they will now
623 // be dead. Make sure to visit them first to delete dead nodes early.
624 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
625 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
626 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
628 DAG.DeleteNode(TLO.Old.getNode());
632 /// SimplifyDemandedBits - Check the specified integer node value to see if
633 /// it can be simplified or if things it uses can be simplified by bit
634 /// propagation. If so, return true.
635 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
636 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
637 APInt KnownZero, KnownOne;
638 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
642 AddToWorkList(Op.getNode());
644 // Replace the old value with the new one.
646 DEBUG(dbgs() << "\nReplacing.2 ";
647 TLO.Old.getNode()->dump(&DAG);
648 dbgs() << "\nWith: ";
649 TLO.New.getNode()->dump(&DAG);
652 CommitTargetLoweringOpt(TLO);
656 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
657 DebugLoc dl = Load->getDebugLoc();
658 EVT VT = Load->getValueType(0);
659 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
661 DEBUG(dbgs() << "\nReplacing.9 ";
663 dbgs() << "\nWith: ";
664 Trunc.getNode()->dump(&DAG);
666 WorkListRemover DeadNodes(*this);
667 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
668 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
670 removeFromWorkList(Load);
671 DAG.DeleteNode(Load);
672 AddToWorkList(Trunc.getNode());
675 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
677 DebugLoc dl = Op.getDebugLoc();
678 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
679 EVT MemVT = LD->getMemoryVT();
680 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
681 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
683 : LD->getExtensionType();
685 return DAG.getExtLoad(ExtType, dl, PVT,
686 LD->getChain(), LD->getBasePtr(),
687 LD->getPointerInfo(),
688 MemVT, LD->isVolatile(),
689 LD->isNonTemporal(), LD->getAlignment());
692 unsigned Opc = Op.getOpcode();
695 case ISD::AssertSext:
696 return DAG.getNode(ISD::AssertSext, dl, PVT,
697 SExtPromoteOperand(Op.getOperand(0), PVT),
699 case ISD::AssertZext:
700 return DAG.getNode(ISD::AssertZext, dl, PVT,
701 ZExtPromoteOperand(Op.getOperand(0), PVT),
703 case ISD::Constant: {
705 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
706 return DAG.getNode(ExtOpc, dl, PVT, Op);
710 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
712 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
715 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
716 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
718 EVT OldVT = Op.getValueType();
719 DebugLoc dl = Op.getDebugLoc();
720 bool Replace = false;
721 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
722 if (NewOp.getNode() == 0)
724 AddToWorkList(NewOp.getNode());
727 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
728 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
729 DAG.getValueType(OldVT));
732 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
733 EVT OldVT = Op.getValueType();
734 DebugLoc dl = Op.getDebugLoc();
735 bool Replace = false;
736 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
737 if (NewOp.getNode() == 0)
739 AddToWorkList(NewOp.getNode());
742 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
743 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
746 /// PromoteIntBinOp - Promote the specified integer binary operation if the
747 /// target indicates it is beneficial. e.g. On x86, it's usually better to
748 /// promote i16 operations to i32 since i16 instructions are longer.
749 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
750 if (!LegalOperations)
753 EVT VT = Op.getValueType();
754 if (VT.isVector() || !VT.isInteger())
757 // If operation type is 'undesirable', e.g. i16 on x86, consider
759 unsigned Opc = Op.getOpcode();
760 if (TLI.isTypeDesirableForOp(Opc, VT))
764 // Consult target whether it is a good idea to promote this operation and
765 // what's the right type to promote it to.
766 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
767 assert(PVT != VT && "Don't know what type to promote to!");
769 bool Replace0 = false;
770 SDValue N0 = Op.getOperand(0);
771 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
772 if (NN0.getNode() == 0)
775 bool Replace1 = false;
776 SDValue N1 = Op.getOperand(1);
781 NN1 = PromoteOperand(N1, PVT, Replace1);
782 if (NN1.getNode() == 0)
786 AddToWorkList(NN0.getNode());
788 AddToWorkList(NN1.getNode());
791 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
793 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
795 DEBUG(dbgs() << "\nPromoting ";
796 Op.getNode()->dump(&DAG));
797 DebugLoc dl = Op.getDebugLoc();
798 return DAG.getNode(ISD::TRUNCATE, dl, VT,
799 DAG.getNode(Opc, dl, PVT, NN0, NN1));
804 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
805 /// target indicates it is beneficial. e.g. On x86, it's usually better to
806 /// promote i16 operations to i32 since i16 instructions are longer.
807 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
808 if (!LegalOperations)
811 EVT VT = Op.getValueType();
812 if (VT.isVector() || !VT.isInteger())
815 // If operation type is 'undesirable', e.g. i16 on x86, consider
817 unsigned Opc = Op.getOpcode();
818 if (TLI.isTypeDesirableForOp(Opc, VT))
822 // Consult target whether it is a good idea to promote this operation and
823 // what's the right type to promote it to.
824 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
825 assert(PVT != VT && "Don't know what type to promote to!");
827 bool Replace = false;
828 SDValue N0 = Op.getOperand(0);
830 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
831 else if (Opc == ISD::SRL)
832 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
834 N0 = PromoteOperand(N0, PVT, Replace);
835 if (N0.getNode() == 0)
838 AddToWorkList(N0.getNode());
840 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
842 DEBUG(dbgs() << "\nPromoting ";
843 Op.getNode()->dump(&DAG));
844 DebugLoc dl = Op.getDebugLoc();
845 return DAG.getNode(ISD::TRUNCATE, dl, VT,
846 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
851 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
852 if (!LegalOperations)
855 EVT VT = Op.getValueType();
856 if (VT.isVector() || !VT.isInteger())
859 // If operation type is 'undesirable', e.g. i16 on x86, consider
861 unsigned Opc = Op.getOpcode();
862 if (TLI.isTypeDesirableForOp(Opc, VT))
866 // Consult target whether it is a good idea to promote this operation and
867 // what's the right type to promote it to.
868 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
869 assert(PVT != VT && "Don't know what type to promote to!");
870 // fold (aext (aext x)) -> (aext x)
871 // fold (aext (zext x)) -> (zext x)
872 // fold (aext (sext x)) -> (sext x)
873 DEBUG(dbgs() << "\nPromoting ";
874 Op.getNode()->dump(&DAG));
875 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
880 bool DAGCombiner::PromoteLoad(SDValue Op) {
881 if (!LegalOperations)
884 EVT VT = Op.getValueType();
885 if (VT.isVector() || !VT.isInteger())
888 // If operation type is 'undesirable', e.g. i16 on x86, consider
890 unsigned Opc = Op.getOpcode();
891 if (TLI.isTypeDesirableForOp(Opc, VT))
895 // Consult target whether it is a good idea to promote this operation and
896 // what's the right type to promote it to.
897 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
898 assert(PVT != VT && "Don't know what type to promote to!");
900 DebugLoc dl = Op.getDebugLoc();
901 SDNode *N = Op.getNode();
902 LoadSDNode *LD = cast<LoadSDNode>(N);
903 EVT MemVT = LD->getMemoryVT();
904 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
905 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
907 : LD->getExtensionType();
908 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
909 LD->getChain(), LD->getBasePtr(),
910 LD->getPointerInfo(),
911 MemVT, LD->isVolatile(),
912 LD->isNonTemporal(), LD->getAlignment());
913 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
915 DEBUG(dbgs() << "\nPromoting ";
918 Result.getNode()->dump(&DAG);
920 WorkListRemover DeadNodes(*this);
921 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
922 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
923 removeFromWorkList(N);
925 AddToWorkList(Result.getNode());
932 //===----------------------------------------------------------------------===//
933 // Main DAG Combiner implementation
934 //===----------------------------------------------------------------------===//
936 void DAGCombiner::Run(CombineLevel AtLevel) {
937 // set the instance variables, so that the various visit routines may use it.
939 LegalOperations = Level >= NoIllegalOperations;
940 LegalTypes = Level >= NoIllegalTypes;
942 // Add all the dag nodes to the worklist.
943 WorkList.reserve(DAG.allnodes_size());
944 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
945 E = DAG.allnodes_end(); I != E; ++I)
946 WorkList.push_back(I);
948 // Create a dummy node (which is not added to allnodes), that adds a reference
949 // to the root node, preventing it from being deleted, and tracking any
950 // changes of the root.
951 HandleSDNode Dummy(DAG.getRoot());
953 // The root of the dag may dangle to deleted nodes until the dag combiner is
954 // done. Set it to null to avoid confusion.
955 DAG.setRoot(SDValue());
957 // while the worklist isn't empty, inspect the node on the end of it and
958 // try and combine it.
959 while (!WorkList.empty()) {
960 SDNode *N = WorkList.back();
963 // If N has no uses, it is dead. Make sure to revisit all N's operands once
964 // N is deleted from the DAG, since they too may now be dead or may have a
965 // reduced number of uses, allowing other xforms.
966 if (N->use_empty() && N != &Dummy) {
967 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
968 AddToWorkList(N->getOperand(i).getNode());
974 SDValue RV = combine(N);
976 if (RV.getNode() == 0)
981 // If we get back the same node we passed in, rather than a new node or
982 // zero, we know that the node must have defined multiple values and
983 // CombineTo was used. Since CombineTo takes care of the worklist
984 // mechanics for us, we have no work to do in this case.
985 if (RV.getNode() == N)
988 assert(N->getOpcode() != ISD::DELETED_NODE &&
989 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
990 "Node was deleted but visit returned new node!");
992 DEBUG(dbgs() << "\nReplacing.3 ";
994 dbgs() << "\nWith: ";
995 RV.getNode()->dump(&DAG);
998 // Transfer debug value.
999 DAG.TransferDbgValues(SDValue(N, 0), RV);
1000 WorkListRemover DeadNodes(*this);
1001 if (N->getNumValues() == RV.getNode()->getNumValues())
1002 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
1004 assert(N->getValueType(0) == RV.getValueType() &&
1005 N->getNumValues() == 1 && "Type mismatch");
1007 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
1010 // Push the new node and any users onto the worklist
1011 AddToWorkList(RV.getNode());
1012 AddUsersToWorkList(RV.getNode());
1014 // Add any uses of the old node to the worklist in case this node is the
1015 // last one that uses them. They may become dead after this node is
1017 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1018 AddToWorkList(N->getOperand(i).getNode());
1020 // Finally, if the node is now dead, remove it from the graph. The node
1021 // may not be dead if the replacement process recursively simplified to
1022 // something else needing this node.
1023 if (N->use_empty()) {
1024 // Nodes can be reintroduced into the worklist. Make sure we do not
1025 // process a node that has been replaced.
1026 removeFromWorkList(N);
1028 // Finally, since the node is now dead, remove it from the graph.
1033 // If the root changed (e.g. it was a dead load, update the root).
1034 DAG.setRoot(Dummy.getValue());
1037 SDValue DAGCombiner::visit(SDNode *N) {
1038 switch (N->getOpcode()) {
1040 case ISD::TokenFactor: return visitTokenFactor(N);
1041 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1042 case ISD::ADD: return visitADD(N);
1043 case ISD::SUB: return visitSUB(N);
1044 case ISD::ADDC: return visitADDC(N);
1045 case ISD::ADDE: return visitADDE(N);
1046 case ISD::MUL: return visitMUL(N);
1047 case ISD::SDIV: return visitSDIV(N);
1048 case ISD::UDIV: return visitUDIV(N);
1049 case ISD::SREM: return visitSREM(N);
1050 case ISD::UREM: return visitUREM(N);
1051 case ISD::MULHU: return visitMULHU(N);
1052 case ISD::MULHS: return visitMULHS(N);
1053 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1054 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1055 case ISD::SMULO: return visitSMULO(N);
1056 case ISD::UMULO: return visitUMULO(N);
1057 case ISD::SDIVREM: return visitSDIVREM(N);
1058 case ISD::UDIVREM: return visitUDIVREM(N);
1059 case ISD::AND: return visitAND(N);
1060 case ISD::OR: return visitOR(N);
1061 case ISD::XOR: return visitXOR(N);
1062 case ISD::SHL: return visitSHL(N);
1063 case ISD::SRA: return visitSRA(N);
1064 case ISD::SRL: return visitSRL(N);
1065 case ISD::CTLZ: return visitCTLZ(N);
1066 case ISD::CTTZ: return visitCTTZ(N);
1067 case ISD::CTPOP: return visitCTPOP(N);
1068 case ISD::SELECT: return visitSELECT(N);
1069 case ISD::SELECT_CC: return visitSELECT_CC(N);
1070 case ISD::SETCC: return visitSETCC(N);
1071 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1072 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1073 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1074 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1075 case ISD::TRUNCATE: return visitTRUNCATE(N);
1076 case ISD::BITCAST: return visitBITCAST(N);
1077 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1078 case ISD::FADD: return visitFADD(N);
1079 case ISD::FSUB: return visitFSUB(N);
1080 case ISD::FMUL: return visitFMUL(N);
1081 case ISD::FDIV: return visitFDIV(N);
1082 case ISD::FREM: return visitFREM(N);
1083 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1084 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1085 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1086 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1087 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1088 case ISD::FP_ROUND: return visitFP_ROUND(N);
1089 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1090 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1091 case ISD::FNEG: return visitFNEG(N);
1092 case ISD::FABS: return visitFABS(N);
1093 case ISD::BRCOND: return visitBRCOND(N);
1094 case ISD::BR_CC: return visitBR_CC(N);
1095 case ISD::LOAD: return visitLOAD(N);
1096 case ISD::STORE: return visitSTORE(N);
1097 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1098 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1099 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1100 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1101 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1102 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1107 SDValue DAGCombiner::combine(SDNode *N) {
1108 SDValue RV = visit(N);
1110 // If nothing happened, try a target-specific DAG combine.
1111 if (RV.getNode() == 0) {
1112 assert(N->getOpcode() != ISD::DELETED_NODE &&
1113 "Node was deleted but visit returned NULL!");
1115 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1116 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1118 // Expose the DAG combiner to the target combiner impls.
1119 TargetLowering::DAGCombinerInfo
1120 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1122 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1126 // If nothing happened still, try promoting the operation.
1127 if (RV.getNode() == 0) {
1128 switch (N->getOpcode()) {
1136 RV = PromoteIntBinOp(SDValue(N, 0));
1141 RV = PromoteIntShiftOp(SDValue(N, 0));
1143 case ISD::SIGN_EXTEND:
1144 case ISD::ZERO_EXTEND:
1145 case ISD::ANY_EXTEND:
1146 RV = PromoteExtend(SDValue(N, 0));
1149 if (PromoteLoad(SDValue(N, 0)))
1155 // If N is a commutative binary node, try commuting it to enable more
1157 if (RV.getNode() == 0 &&
1158 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1159 N->getNumValues() == 1) {
1160 SDValue N0 = N->getOperand(0);
1161 SDValue N1 = N->getOperand(1);
1163 // Constant operands are canonicalized to RHS.
1164 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1165 SDValue Ops[] = { N1, N0 };
1166 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1169 return SDValue(CSENode, 0);
1176 /// getInputChainForNode - Given a node, return its input chain if it has one,
1177 /// otherwise return a null sd operand.
1178 static SDValue getInputChainForNode(SDNode *N) {
1179 if (unsigned NumOps = N->getNumOperands()) {
1180 if (N->getOperand(0).getValueType() == MVT::Other)
1181 return N->getOperand(0);
1182 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1183 return N->getOperand(NumOps-1);
1184 for (unsigned i = 1; i < NumOps-1; ++i)
1185 if (N->getOperand(i).getValueType() == MVT::Other)
1186 return N->getOperand(i);
1191 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1192 // If N has two operands, where one has an input chain equal to the other,
1193 // the 'other' chain is redundant.
1194 if (N->getNumOperands() == 2) {
1195 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1196 return N->getOperand(0);
1197 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1198 return N->getOperand(1);
1201 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1202 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1203 SmallPtrSet<SDNode*, 16> SeenOps;
1204 bool Changed = false; // If we should replace this token factor.
1206 // Start out with this token factor.
1209 // Iterate through token factors. The TFs grows when new token factors are
1211 for (unsigned i = 0; i < TFs.size(); ++i) {
1212 SDNode *TF = TFs[i];
1214 // Check each of the operands.
1215 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1216 SDValue Op = TF->getOperand(i);
1218 switch (Op.getOpcode()) {
1219 case ISD::EntryToken:
1220 // Entry tokens don't need to be added to the list. They are
1225 case ISD::TokenFactor:
1226 if (Op.hasOneUse() &&
1227 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1228 // Queue up for processing.
1229 TFs.push_back(Op.getNode());
1230 // Clean up in case the token factor is removed.
1231 AddToWorkList(Op.getNode());
1238 // Only add if it isn't already in the list.
1239 if (SeenOps.insert(Op.getNode()))
1250 // If we've change things around then replace token factor.
1253 // The entry token is the only possible outcome.
1254 Result = DAG.getEntryNode();
1256 // New and improved token factor.
1257 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1258 MVT::Other, &Ops[0], Ops.size());
1261 // Don't add users to work list.
1262 return CombineTo(N, Result, false);
1268 /// MERGE_VALUES can always be eliminated.
1269 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1270 WorkListRemover DeadNodes(*this);
1271 // Replacing results may cause a different MERGE_VALUES to suddenly
1272 // be CSE'd with N, and carry its uses with it. Iterate until no
1273 // uses remain, to ensure that the node can be safely deleted.
1275 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1276 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1278 } while (!N->use_empty());
1279 removeFromWorkList(N);
1281 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1285 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1286 SelectionDAG &DAG) {
1287 EVT VT = N0.getValueType();
1288 SDValue N00 = N0.getOperand(0);
1289 SDValue N01 = N0.getOperand(1);
1290 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1292 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1293 isa<ConstantSDNode>(N00.getOperand(1))) {
1294 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1295 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1296 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1297 N00.getOperand(0), N01),
1298 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1299 N00.getOperand(1), N01));
1300 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1306 /// isCarryMaterialization - Returns true if V is an ADDE node that is known to
1307 /// return 0 or 1 depending on the carry flag.
1308 static bool isCarryMaterialization(SDValue V) {
1309 if (V.getOpcode() != ISD::ADDE)
1312 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(0));
1313 return C && C->isNullValue() && V.getOperand(0) == V.getOperand(1);
1316 SDValue DAGCombiner::visitADD(SDNode *N) {
1317 SDValue N0 = N->getOperand(0);
1318 SDValue N1 = N->getOperand(1);
1319 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1320 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1321 EVT VT = N0.getValueType();
1324 if (VT.isVector()) {
1325 SDValue FoldedVOp = SimplifyVBinOp(N);
1326 if (FoldedVOp.getNode()) return FoldedVOp;
1329 // fold (add x, undef) -> undef
1330 if (N0.getOpcode() == ISD::UNDEF)
1332 if (N1.getOpcode() == ISD::UNDEF)
1334 // fold (add c1, c2) -> c1+c2
1336 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1337 // canonicalize constant to RHS
1339 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1340 // fold (add x, 0) -> x
1341 if (N1C && N1C->isNullValue())
1343 // fold (add Sym, c) -> Sym+c
1344 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1345 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1346 GA->getOpcode() == ISD::GlobalAddress)
1347 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1349 (uint64_t)N1C->getSExtValue());
1350 // fold ((c1-A)+c2) -> (c1+c2)-A
1351 if (N1C && N0.getOpcode() == ISD::SUB)
1352 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1353 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1354 DAG.getConstant(N1C->getAPIntValue()+
1355 N0C->getAPIntValue(), VT),
1358 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1359 if (RADD.getNode() != 0)
1361 // fold ((0-A) + B) -> B-A
1362 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1363 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1364 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1365 // fold (A + (0-B)) -> A-B
1366 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1367 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1368 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1369 // fold (A+(B-A)) -> B
1370 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1371 return N1.getOperand(0);
1372 // fold ((B-A)+A) -> B
1373 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1374 return N0.getOperand(0);
1375 // fold (A+(B-(A+C))) to (B-C)
1376 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1377 N0 == N1.getOperand(1).getOperand(0))
1378 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1379 N1.getOperand(1).getOperand(1));
1380 // fold (A+(B-(C+A))) to (B-C)
1381 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1382 N0 == N1.getOperand(1).getOperand(1))
1383 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1384 N1.getOperand(1).getOperand(0));
1385 // fold (A+((B-A)+or-C)) to (B+or-C)
1386 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1387 N1.getOperand(0).getOpcode() == ISD::SUB &&
1388 N0 == N1.getOperand(0).getOperand(1))
1389 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1390 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1392 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1393 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1394 SDValue N00 = N0.getOperand(0);
1395 SDValue N01 = N0.getOperand(1);
1396 SDValue N10 = N1.getOperand(0);
1397 SDValue N11 = N1.getOperand(1);
1399 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1400 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1401 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1402 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1405 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1406 return SDValue(N, 0);
1408 // fold (a+b) -> (a|b) iff a and b share no bits.
1409 if (VT.isInteger() && !VT.isVector()) {
1410 APInt LHSZero, LHSOne;
1411 APInt RHSZero, RHSOne;
1412 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1413 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1415 if (LHSZero.getBoolValue()) {
1416 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1418 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1419 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1420 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1421 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1422 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1426 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1427 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1428 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1429 if (Result.getNode()) return Result;
1431 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1432 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1433 if (Result.getNode()) return Result;
1436 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1437 if (N1.getOpcode() == ISD::SHL &&
1438 N1.getOperand(0).getOpcode() == ISD::SUB)
1439 if (ConstantSDNode *C =
1440 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1441 if (C->getAPIntValue() == 0)
1442 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1443 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1444 N1.getOperand(0).getOperand(1),
1446 if (N0.getOpcode() == ISD::SHL &&
1447 N0.getOperand(0).getOpcode() == ISD::SUB)
1448 if (ConstantSDNode *C =
1449 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1450 if (C->getAPIntValue() == 0)
1451 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1452 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1453 N0.getOperand(0).getOperand(1),
1456 if (N1.getOpcode() == ISD::AND) {
1457 SDValue AndOp0 = N1.getOperand(0);
1458 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1459 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1460 unsigned DestBits = VT.getScalarType().getSizeInBits();
1462 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1463 // and similar xforms where the inner op is either ~0 or 0.
1464 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1465 DebugLoc DL = N->getDebugLoc();
1466 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1470 // add (sext i1), X -> sub X, (zext i1)
1471 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1472 N0.getOperand(0).getValueType() == MVT::i1 &&
1473 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1474 DebugLoc DL = N->getDebugLoc();
1475 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1476 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1479 // add (adde 0, 0, glue), X -> adde X, 0, glue
1480 if (N0->hasOneUse() && isCarryMaterialization(N0))
1481 return DAG.getNode(ISD::ADDE, N->getDebugLoc(),
1482 DAG.getVTList(VT, MVT::Glue), N1, N0.getOperand(0),
1485 // add X, (adde 0, 0, glue) -> adde X, 0, glue
1486 if (N1->hasOneUse() && isCarryMaterialization(N1))
1487 return DAG.getNode(ISD::ADDE, N->getDebugLoc(),
1488 DAG.getVTList(VT, MVT::Glue), N0, N1.getOperand(0),
1494 SDValue DAGCombiner::visitADDC(SDNode *N) {
1495 SDValue N0 = N->getOperand(0);
1496 SDValue N1 = N->getOperand(1);
1497 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1498 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1499 EVT VT = N0.getValueType();
1501 // If the flag result is dead, turn this into an ADD.
1502 if (N->hasNUsesOfValue(0, 1))
1503 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1504 DAG.getNode(ISD::CARRY_FALSE,
1505 N->getDebugLoc(), MVT::Glue));
1507 // canonicalize constant to RHS.
1509 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1511 // fold (addc x, 0) -> x + no carry out
1512 if (N1C && N1C->isNullValue())
1513 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1514 N->getDebugLoc(), MVT::Glue));
1516 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1517 APInt LHSZero, LHSOne;
1518 APInt RHSZero, RHSOne;
1519 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1520 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1522 if (LHSZero.getBoolValue()) {
1523 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1525 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1526 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1527 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1528 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1529 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1530 DAG.getNode(ISD::CARRY_FALSE,
1531 N->getDebugLoc(), MVT::Glue));
1534 // addc (adde 0, 0, glue), X -> adde X, 0, glue
1535 if (N0->hasOneUse() && isCarryMaterialization(N0))
1536 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N1,
1537 DAG.getConstant(0, VT), N0.getOperand(2));
1539 // addc X, (adde 0, 0, glue) -> adde X, 0, glue
1540 if (N1->hasOneUse() && isCarryMaterialization(N1))
1541 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N0,
1542 DAG.getConstant(0, VT), N1.getOperand(2));
1547 SDValue DAGCombiner::visitADDE(SDNode *N) {
1548 SDValue N0 = N->getOperand(0);
1549 SDValue N1 = N->getOperand(1);
1550 SDValue CarryIn = N->getOperand(2);
1551 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1552 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1554 // If both operands are null we know that carry out will always be false.
1555 if (N0C && N0C->isNullValue() && N0 == N1)
1556 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), DAG.getNode(ISD::CARRY_FALSE,
1560 // canonicalize constant to RHS
1562 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1565 // fold (adde x, y, false) -> (addc x, y)
1566 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1567 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1572 // Since it may not be valid to emit a fold to zero for vector initializers
1573 // check if we can before folding.
1574 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1575 SelectionDAG &DAG, bool LegalOperations) {
1576 if (!VT.isVector()) {
1577 return DAG.getConstant(0, VT);
1579 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1580 // Produce a vector of zeros.
1581 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1582 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1583 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1584 &Ops[0], Ops.size());
1589 SDValue DAGCombiner::visitSUB(SDNode *N) {
1590 SDValue N0 = N->getOperand(0);
1591 SDValue N1 = N->getOperand(1);
1592 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1593 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1594 EVT VT = N0.getValueType();
1597 if (VT.isVector()) {
1598 SDValue FoldedVOp = SimplifyVBinOp(N);
1599 if (FoldedVOp.getNode()) return FoldedVOp;
1602 // fold (sub x, x) -> 0
1603 // FIXME: Refactor this and xor and other similar operations together.
1605 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1606 // fold (sub c1, c2) -> c1-c2
1608 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1609 // fold (sub x, c) -> (add x, -c)
1611 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1612 DAG.getConstant(-N1C->getAPIntValue(), VT));
1613 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1614 if (N0C && N0C->isAllOnesValue())
1615 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1616 // fold A-(A-B) -> B
1617 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1618 return N1.getOperand(1);
1619 // fold (A+B)-A -> B
1620 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1621 return N0.getOperand(1);
1622 // fold (A+B)-B -> A
1623 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1624 return N0.getOperand(0);
1625 // fold ((A+(B+or-C))-B) -> A+or-C
1626 if (N0.getOpcode() == ISD::ADD &&
1627 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1628 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1629 N0.getOperand(1).getOperand(0) == N1)
1630 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1631 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1632 // fold ((A+(C+B))-B) -> A+C
1633 if (N0.getOpcode() == ISD::ADD &&
1634 N0.getOperand(1).getOpcode() == ISD::ADD &&
1635 N0.getOperand(1).getOperand(1) == N1)
1636 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1637 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1638 // fold ((A-(B-C))-C) -> A-B
1639 if (N0.getOpcode() == ISD::SUB &&
1640 N0.getOperand(1).getOpcode() == ISD::SUB &&
1641 N0.getOperand(1).getOperand(1) == N1)
1642 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1643 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1645 // If either operand of a sub is undef, the result is undef
1646 if (N0.getOpcode() == ISD::UNDEF)
1648 if (N1.getOpcode() == ISD::UNDEF)
1651 // If the relocation model supports it, consider symbol offsets.
1652 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1653 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1654 // fold (sub Sym, c) -> Sym-c
1655 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1656 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1658 (uint64_t)N1C->getSExtValue());
1659 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1660 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1661 if (GA->getGlobal() == GB->getGlobal())
1662 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1669 SDValue DAGCombiner::visitMUL(SDNode *N) {
1670 SDValue N0 = N->getOperand(0);
1671 SDValue N1 = N->getOperand(1);
1672 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1673 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1674 EVT VT = N0.getValueType();
1677 if (VT.isVector()) {
1678 SDValue FoldedVOp = SimplifyVBinOp(N);
1679 if (FoldedVOp.getNode()) return FoldedVOp;
1682 // fold (mul x, undef) -> 0
1683 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1684 return DAG.getConstant(0, VT);
1685 // fold (mul c1, c2) -> c1*c2
1687 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1688 // canonicalize constant to RHS
1690 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1691 // fold (mul x, 0) -> 0
1692 if (N1C && N1C->isNullValue())
1694 // fold (mul x, -1) -> 0-x
1695 if (N1C && N1C->isAllOnesValue())
1696 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1697 DAG.getConstant(0, VT), N0);
1698 // fold (mul x, (1 << c)) -> x << c
1699 if (N1C && N1C->getAPIntValue().isPowerOf2())
1700 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1701 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1702 getShiftAmountTy(N0.getValueType())));
1703 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1704 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1705 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1706 // FIXME: If the input is something that is easily negated (e.g. a
1707 // single-use add), we should put the negate there.
1708 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1709 DAG.getConstant(0, VT),
1710 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1711 DAG.getConstant(Log2Val,
1712 getShiftAmountTy(N0.getValueType()))));
1714 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1715 if (N1C && N0.getOpcode() == ISD::SHL &&
1716 isa<ConstantSDNode>(N0.getOperand(1))) {
1717 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1718 N1, N0.getOperand(1));
1719 AddToWorkList(C3.getNode());
1720 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1721 N0.getOperand(0), C3);
1724 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1727 SDValue Sh(0,0), Y(0,0);
1728 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1729 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1730 N0.getNode()->hasOneUse()) {
1732 } else if (N1.getOpcode() == ISD::SHL &&
1733 isa<ConstantSDNode>(N1.getOperand(1)) &&
1734 N1.getNode()->hasOneUse()) {
1739 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1740 Sh.getOperand(0), Y);
1741 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1742 Mul, Sh.getOperand(1));
1746 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1747 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1748 isa<ConstantSDNode>(N0.getOperand(1)))
1749 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1750 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1751 N0.getOperand(0), N1),
1752 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1753 N0.getOperand(1), N1));
1756 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1757 if (RMUL.getNode() != 0)
1763 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1764 SDValue N0 = N->getOperand(0);
1765 SDValue N1 = N->getOperand(1);
1766 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1767 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1768 EVT VT = N->getValueType(0);
1771 if (VT.isVector()) {
1772 SDValue FoldedVOp = SimplifyVBinOp(N);
1773 if (FoldedVOp.getNode()) return FoldedVOp;
1776 // fold (sdiv c1, c2) -> c1/c2
1777 if (N0C && N1C && !N1C->isNullValue())
1778 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1779 // fold (sdiv X, 1) -> X
1780 if (N1C && N1C->getSExtValue() == 1LL)
1782 // fold (sdiv X, -1) -> 0-X
1783 if (N1C && N1C->isAllOnesValue())
1784 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1785 DAG.getConstant(0, VT), N0);
1786 // If we know the sign bits of both operands are zero, strength reduce to a
1787 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1788 if (!VT.isVector()) {
1789 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1790 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1793 // fold (sdiv X, pow2) -> simple ops after legalize
1794 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1795 (isPowerOf2_64(N1C->getSExtValue()) ||
1796 isPowerOf2_64(-N1C->getSExtValue()))) {
1797 // If dividing by powers of two is cheap, then don't perform the following
1799 if (TLI.isPow2DivCheap())
1802 int64_t pow2 = N1C->getSExtValue();
1803 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1804 unsigned lg2 = Log2_64(abs2);
1806 // Splat the sign bit into the register
1807 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1808 DAG.getConstant(VT.getSizeInBits()-1,
1809 getShiftAmountTy(N0.getValueType())));
1810 AddToWorkList(SGN.getNode());
1812 // Add (N0 < 0) ? abs2 - 1 : 0;
1813 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1814 DAG.getConstant(VT.getSizeInBits() - lg2,
1815 getShiftAmountTy(SGN.getValueType())));
1816 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1817 AddToWorkList(SRL.getNode());
1818 AddToWorkList(ADD.getNode()); // Divide by pow2
1819 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1820 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1822 // If we're dividing by a positive value, we're done. Otherwise, we must
1823 // negate the result.
1827 AddToWorkList(SRA.getNode());
1828 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1829 DAG.getConstant(0, VT), SRA);
1832 // if integer divide is expensive and we satisfy the requirements, emit an
1833 // alternate sequence.
1834 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1835 !TLI.isIntDivCheap()) {
1836 SDValue Op = BuildSDIV(N);
1837 if (Op.getNode()) return Op;
1841 if (N0.getOpcode() == ISD::UNDEF)
1842 return DAG.getConstant(0, VT);
1843 // X / undef -> undef
1844 if (N1.getOpcode() == ISD::UNDEF)
1850 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1851 SDValue N0 = N->getOperand(0);
1852 SDValue N1 = N->getOperand(1);
1853 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1854 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1855 EVT VT = N->getValueType(0);
1858 if (VT.isVector()) {
1859 SDValue FoldedVOp = SimplifyVBinOp(N);
1860 if (FoldedVOp.getNode()) return FoldedVOp;
1863 // fold (udiv c1, c2) -> c1/c2
1864 if (N0C && N1C && !N1C->isNullValue())
1865 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1866 // fold (udiv x, (1 << c)) -> x >>u c
1867 if (N1C && N1C->getAPIntValue().isPowerOf2())
1868 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1869 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1870 getShiftAmountTy(N0.getValueType())));
1871 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1872 if (N1.getOpcode() == ISD::SHL) {
1873 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1874 if (SHC->getAPIntValue().isPowerOf2()) {
1875 EVT ADDVT = N1.getOperand(1).getValueType();
1876 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1878 DAG.getConstant(SHC->getAPIntValue()
1881 AddToWorkList(Add.getNode());
1882 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1886 // fold (udiv x, c) -> alternate
1887 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1888 SDValue Op = BuildUDIV(N);
1889 if (Op.getNode()) return Op;
1893 if (N0.getOpcode() == ISD::UNDEF)
1894 return DAG.getConstant(0, VT);
1895 // X / undef -> undef
1896 if (N1.getOpcode() == ISD::UNDEF)
1902 SDValue DAGCombiner::visitSREM(SDNode *N) {
1903 SDValue N0 = N->getOperand(0);
1904 SDValue N1 = N->getOperand(1);
1905 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1906 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1907 EVT VT = N->getValueType(0);
1909 // fold (srem c1, c2) -> c1%c2
1910 if (N0C && N1C && !N1C->isNullValue())
1911 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1912 // If we know the sign bits of both operands are zero, strength reduce to a
1913 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1914 if (!VT.isVector()) {
1915 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1916 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1919 // If X/C can be simplified by the division-by-constant logic, lower
1920 // X%C to the equivalent of X-X/C*C.
1921 if (N1C && !N1C->isNullValue()) {
1922 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1923 AddToWorkList(Div.getNode());
1924 SDValue OptimizedDiv = combine(Div.getNode());
1925 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1926 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1928 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1929 AddToWorkList(Mul.getNode());
1935 if (N0.getOpcode() == ISD::UNDEF)
1936 return DAG.getConstant(0, VT);
1937 // X % undef -> undef
1938 if (N1.getOpcode() == ISD::UNDEF)
1944 SDValue DAGCombiner::visitUREM(SDNode *N) {
1945 SDValue N0 = N->getOperand(0);
1946 SDValue N1 = N->getOperand(1);
1947 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1948 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1949 EVT VT = N->getValueType(0);
1951 // fold (urem c1, c2) -> c1%c2
1952 if (N0C && N1C && !N1C->isNullValue())
1953 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1954 // fold (urem x, pow2) -> (and x, pow2-1)
1955 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1956 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1957 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1958 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1959 if (N1.getOpcode() == ISD::SHL) {
1960 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1961 if (SHC->getAPIntValue().isPowerOf2()) {
1963 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1964 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1966 AddToWorkList(Add.getNode());
1967 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1972 // If X/C can be simplified by the division-by-constant logic, lower
1973 // X%C to the equivalent of X-X/C*C.
1974 if (N1C && !N1C->isNullValue()) {
1975 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1976 AddToWorkList(Div.getNode());
1977 SDValue OptimizedDiv = combine(Div.getNode());
1978 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1979 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1981 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1982 AddToWorkList(Mul.getNode());
1988 if (N0.getOpcode() == ISD::UNDEF)
1989 return DAG.getConstant(0, VT);
1990 // X % undef -> undef
1991 if (N1.getOpcode() == ISD::UNDEF)
1997 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1998 SDValue N0 = N->getOperand(0);
1999 SDValue N1 = N->getOperand(1);
2000 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2001 EVT VT = N->getValueType(0);
2002 DebugLoc DL = N->getDebugLoc();
2004 // fold (mulhs x, 0) -> 0
2005 if (N1C && N1C->isNullValue())
2007 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2008 if (N1C && N1C->getAPIntValue() == 1)
2009 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
2010 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2011 getShiftAmountTy(N0.getValueType())));
2012 // fold (mulhs x, undef) -> 0
2013 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2014 return DAG.getConstant(0, VT);
2016 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2018 if (VT.isSimple() && !VT.isVector()) {
2019 MVT Simple = VT.getSimpleVT();
2020 unsigned SimpleSize = Simple.getSizeInBits();
2021 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2022 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2023 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2024 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2025 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2026 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2027 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2028 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2035 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2036 SDValue N0 = N->getOperand(0);
2037 SDValue N1 = N->getOperand(1);
2038 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2039 EVT VT = N->getValueType(0);
2040 DebugLoc DL = N->getDebugLoc();
2042 // fold (mulhu x, 0) -> 0
2043 if (N1C && N1C->isNullValue())
2045 // fold (mulhu x, 1) -> 0
2046 if (N1C && N1C->getAPIntValue() == 1)
2047 return DAG.getConstant(0, N0.getValueType());
2048 // fold (mulhu x, undef) -> 0
2049 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2050 return DAG.getConstant(0, VT);
2052 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2054 if (VT.isSimple() && !VT.isVector()) {
2055 MVT Simple = VT.getSimpleVT();
2056 unsigned SimpleSize = Simple.getSizeInBits();
2057 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2058 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2059 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2060 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2061 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2062 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2063 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2064 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2071 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2072 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2073 /// that are being performed. Return true if a simplification was made.
2075 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2077 // If the high half is not needed, just compute the low half.
2078 bool HiExists = N->hasAnyUseOfValue(1);
2080 (!LegalOperations ||
2081 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2082 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2083 N->op_begin(), N->getNumOperands());
2084 return CombineTo(N, Res, Res);
2087 // If the low half is not needed, just compute the high half.
2088 bool LoExists = N->hasAnyUseOfValue(0);
2090 (!LegalOperations ||
2091 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2092 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2093 N->op_begin(), N->getNumOperands());
2094 return CombineTo(N, Res, Res);
2097 // If both halves are used, return as it is.
2098 if (LoExists && HiExists)
2101 // If the two computed results can be simplified separately, separate them.
2103 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2104 N->op_begin(), N->getNumOperands());
2105 AddToWorkList(Lo.getNode());
2106 SDValue LoOpt = combine(Lo.getNode());
2107 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2108 (!LegalOperations ||
2109 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2110 return CombineTo(N, LoOpt, LoOpt);
2114 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2115 N->op_begin(), N->getNumOperands());
2116 AddToWorkList(Hi.getNode());
2117 SDValue HiOpt = combine(Hi.getNode());
2118 if (HiOpt.getNode() && HiOpt != Hi &&
2119 (!LegalOperations ||
2120 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2121 return CombineTo(N, HiOpt, HiOpt);
2127 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2128 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2129 if (Res.getNode()) return Res;
2131 EVT VT = N->getValueType(0);
2132 DebugLoc DL = N->getDebugLoc();
2134 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2136 if (VT.isSimple() && !VT.isVector()) {
2137 MVT Simple = VT.getSimpleVT();
2138 unsigned SimpleSize = Simple.getSizeInBits();
2139 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2140 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2141 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2142 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2143 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2144 // Compute the high part as N1.
2145 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2146 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2147 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2148 // Compute the low part as N0.
2149 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2150 return CombineTo(N, Lo, Hi);
2157 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2158 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2159 if (Res.getNode()) return Res;
2161 EVT VT = N->getValueType(0);
2162 DebugLoc DL = N->getDebugLoc();
2164 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2166 if (VT.isSimple() && !VT.isVector()) {
2167 MVT Simple = VT.getSimpleVT();
2168 unsigned SimpleSize = Simple.getSizeInBits();
2169 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2170 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2171 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2172 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2173 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2174 // Compute the high part as N1.
2175 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2176 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2177 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2178 // Compute the low part as N0.
2179 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2180 return CombineTo(N, Lo, Hi);
2187 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2188 // (smulo x, 2) -> (saddo x, x)
2189 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2190 if (C2->getAPIntValue() == 2)
2191 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2192 N->getOperand(0), N->getOperand(0));
2197 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2198 // (umulo x, 2) -> (uaddo x, x)
2199 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2200 if (C2->getAPIntValue() == 2)
2201 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2202 N->getOperand(0), N->getOperand(0));
2207 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2208 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2209 if (Res.getNode()) return Res;
2214 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2215 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2216 if (Res.getNode()) return Res;
2221 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2222 /// two operands of the same opcode, try to simplify it.
2223 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2224 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2225 EVT VT = N0.getValueType();
2226 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2228 // Bail early if none of these transforms apply.
2229 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2231 // For each of OP in AND/OR/XOR:
2232 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2233 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2234 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2235 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2237 // do not sink logical op inside of a vector extend, since it may combine
2239 EVT Op0VT = N0.getOperand(0).getValueType();
2240 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2241 N0.getOpcode() == ISD::SIGN_EXTEND ||
2242 // Avoid infinite looping with PromoteIntBinOp.
2243 (N0.getOpcode() == ISD::ANY_EXTEND &&
2244 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2245 (N0.getOpcode() == ISD::TRUNCATE &&
2246 (!TLI.isZExtFree(VT, Op0VT) ||
2247 !TLI.isTruncateFree(Op0VT, VT)) &&
2248 TLI.isTypeLegal(Op0VT))) &&
2250 Op0VT == N1.getOperand(0).getValueType() &&
2251 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2252 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2253 N0.getOperand(0).getValueType(),
2254 N0.getOperand(0), N1.getOperand(0));
2255 AddToWorkList(ORNode.getNode());
2256 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2259 // For each of OP in SHL/SRL/SRA/AND...
2260 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2261 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2262 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2263 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2264 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2265 N0.getOperand(1) == N1.getOperand(1)) {
2266 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2267 N0.getOperand(0).getValueType(),
2268 N0.getOperand(0), N1.getOperand(0));
2269 AddToWorkList(ORNode.getNode());
2270 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2271 ORNode, N0.getOperand(1));
2277 SDValue DAGCombiner::visitAND(SDNode *N) {
2278 SDValue N0 = N->getOperand(0);
2279 SDValue N1 = N->getOperand(1);
2280 SDValue LL, LR, RL, RR, CC0, CC1;
2281 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2282 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2283 EVT VT = N1.getValueType();
2284 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2287 if (VT.isVector()) {
2288 SDValue FoldedVOp = SimplifyVBinOp(N);
2289 if (FoldedVOp.getNode()) return FoldedVOp;
2292 // fold (and x, undef) -> 0
2293 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2294 return DAG.getConstant(0, VT);
2295 // fold (and c1, c2) -> c1&c2
2297 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2298 // canonicalize constant to RHS
2300 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2301 // fold (and x, -1) -> x
2302 if (N1C && N1C->isAllOnesValue())
2304 // if (and x, c) is known to be zero, return 0
2305 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2306 APInt::getAllOnesValue(BitWidth)))
2307 return DAG.getConstant(0, VT);
2309 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2310 if (RAND.getNode() != 0)
2312 // fold (and (or x, C), D) -> D if (C & D) == D
2313 if (N1C && N0.getOpcode() == ISD::OR)
2314 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2315 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2317 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2318 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2319 SDValue N0Op0 = N0.getOperand(0);
2320 APInt Mask = ~N1C->getAPIntValue();
2321 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2322 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2323 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2324 N0.getValueType(), N0Op0);
2326 // Replace uses of the AND with uses of the Zero extend node.
2329 // We actually want to replace all uses of the any_extend with the
2330 // zero_extend, to avoid duplicating things. This will later cause this
2331 // AND to be folded.
2332 CombineTo(N0.getNode(), Zext);
2333 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2336 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2337 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2338 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2339 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2341 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2342 LL.getValueType().isInteger()) {
2343 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2344 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2345 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2346 LR.getValueType(), LL, RL);
2347 AddToWorkList(ORNode.getNode());
2348 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2350 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2351 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2352 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2353 LR.getValueType(), LL, RL);
2354 AddToWorkList(ANDNode.getNode());
2355 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2357 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2358 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2359 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2360 LR.getValueType(), LL, RL);
2361 AddToWorkList(ORNode.getNode());
2362 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2365 // canonicalize equivalent to ll == rl
2366 if (LL == RR && LR == RL) {
2367 Op1 = ISD::getSetCCSwappedOperands(Op1);
2370 if (LL == RL && LR == RR) {
2371 bool isInteger = LL.getValueType().isInteger();
2372 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2373 if (Result != ISD::SETCC_INVALID &&
2374 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2375 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2380 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2381 if (N0.getOpcode() == N1.getOpcode()) {
2382 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2383 if (Tmp.getNode()) return Tmp;
2386 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2387 // fold (and (sra)) -> (and (srl)) when possible.
2388 if (!VT.isVector() &&
2389 SimplifyDemandedBits(SDValue(N, 0)))
2390 return SDValue(N, 0);
2392 // fold (zext_inreg (extload x)) -> (zextload x)
2393 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2394 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2395 EVT MemVT = LN0->getMemoryVT();
2396 // If we zero all the possible extended bits, then we can turn this into
2397 // a zextload if we are running before legalize or the operation is legal.
2398 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2399 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2400 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2401 ((!LegalOperations && !LN0->isVolatile()) ||
2402 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2403 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2404 LN0->getChain(), LN0->getBasePtr(),
2405 LN0->getPointerInfo(), MemVT,
2406 LN0->isVolatile(), LN0->isNonTemporal(),
2407 LN0->getAlignment());
2409 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2410 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2413 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2414 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2416 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2417 EVT MemVT = LN0->getMemoryVT();
2418 // If we zero all the possible extended bits, then we can turn this into
2419 // a zextload if we are running before legalize or the operation is legal.
2420 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2421 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2422 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2423 ((!LegalOperations && !LN0->isVolatile()) ||
2424 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2425 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2427 LN0->getBasePtr(), LN0->getPointerInfo(),
2429 LN0->isVolatile(), LN0->isNonTemporal(),
2430 LN0->getAlignment());
2432 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2433 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2437 // fold (and (load x), 255) -> (zextload x, i8)
2438 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2439 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2440 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2441 (N0.getOpcode() == ISD::ANY_EXTEND &&
2442 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2443 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2444 LoadSDNode *LN0 = HasAnyExt
2445 ? cast<LoadSDNode>(N0.getOperand(0))
2446 : cast<LoadSDNode>(N0);
2447 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2448 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2449 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2450 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2451 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2452 EVT LoadedVT = LN0->getMemoryVT();
2454 if (ExtVT == LoadedVT &&
2455 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2456 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2459 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2460 LN0->getChain(), LN0->getBasePtr(),
2461 LN0->getPointerInfo(),
2462 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2463 LN0->getAlignment());
2465 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2466 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2469 // Do not change the width of a volatile load.
2470 // Do not generate loads of non-round integer types since these can
2471 // be expensive (and would be wrong if the type is not byte sized).
2472 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2473 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2474 EVT PtrType = LN0->getOperand(1).getValueType();
2476 unsigned Alignment = LN0->getAlignment();
2477 SDValue NewPtr = LN0->getBasePtr();
2479 // For big endian targets, we need to add an offset to the pointer
2480 // to load the correct bytes. For little endian systems, we merely
2481 // need to read fewer bytes from the same pointer.
2482 if (TLI.isBigEndian()) {
2483 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2484 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2485 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2486 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2487 NewPtr, DAG.getConstant(PtrOff, PtrType));
2488 Alignment = MinAlign(Alignment, PtrOff);
2491 AddToWorkList(NewPtr.getNode());
2493 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2495 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2496 LN0->getChain(), NewPtr,
2497 LN0->getPointerInfo(),
2498 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2501 CombineTo(LN0, Load, Load.getValue(1));
2502 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2511 SDValue DAGCombiner::visitOR(SDNode *N) {
2512 SDValue N0 = N->getOperand(0);
2513 SDValue N1 = N->getOperand(1);
2514 SDValue LL, LR, RL, RR, CC0, CC1;
2515 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2516 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2517 EVT VT = N1.getValueType();
2520 if (VT.isVector()) {
2521 SDValue FoldedVOp = SimplifyVBinOp(N);
2522 if (FoldedVOp.getNode()) return FoldedVOp;
2525 // fold (or x, undef) -> -1
2526 if (!LegalOperations &&
2527 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2528 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2529 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2531 // fold (or c1, c2) -> c1|c2
2533 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2534 // canonicalize constant to RHS
2536 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2537 // fold (or x, 0) -> x
2538 if (N1C && N1C->isNullValue())
2540 // fold (or x, -1) -> -1
2541 if (N1C && N1C->isAllOnesValue())
2543 // fold (or x, c) -> c iff (x & ~c) == 0
2544 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2547 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2548 if (ROR.getNode() != 0)
2550 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2551 // iff (c1 & c2) == 0.
2552 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2553 isa<ConstantSDNode>(N0.getOperand(1))) {
2554 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2555 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2556 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2557 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2558 N0.getOperand(0), N1),
2559 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2561 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2562 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2563 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2564 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2566 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2567 LL.getValueType().isInteger()) {
2568 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2569 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2570 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2571 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2572 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2573 LR.getValueType(), LL, RL);
2574 AddToWorkList(ORNode.getNode());
2575 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2577 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2578 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2579 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2580 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2581 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2582 LR.getValueType(), LL, RL);
2583 AddToWorkList(ANDNode.getNode());
2584 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2587 // canonicalize equivalent to ll == rl
2588 if (LL == RR && LR == RL) {
2589 Op1 = ISD::getSetCCSwappedOperands(Op1);
2592 if (LL == RL && LR == RR) {
2593 bool isInteger = LL.getValueType().isInteger();
2594 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2595 if (Result != ISD::SETCC_INVALID &&
2596 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2597 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2602 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2603 if (N0.getOpcode() == N1.getOpcode()) {
2604 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2605 if (Tmp.getNode()) return Tmp;
2608 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2609 if (N0.getOpcode() == ISD::AND &&
2610 N1.getOpcode() == ISD::AND &&
2611 N0.getOperand(1).getOpcode() == ISD::Constant &&
2612 N1.getOperand(1).getOpcode() == ISD::Constant &&
2613 // Don't increase # computations.
2614 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2615 // We can only do this xform if we know that bits from X that are set in C2
2616 // but not in C1 are already zero. Likewise for Y.
2617 const APInt &LHSMask =
2618 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2619 const APInt &RHSMask =
2620 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2622 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2623 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2624 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2625 N0.getOperand(0), N1.getOperand(0));
2626 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2627 DAG.getConstant(LHSMask | RHSMask, VT));
2631 // See if this is some rotate idiom.
2632 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2633 return SDValue(Rot, 0);
2635 // Simplify the operands using demanded-bits information.
2636 if (!VT.isVector() &&
2637 SimplifyDemandedBits(SDValue(N, 0)))
2638 return SDValue(N, 0);
2643 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2644 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2645 if (Op.getOpcode() == ISD::AND) {
2646 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2647 Mask = Op.getOperand(1);
2648 Op = Op.getOperand(0);
2654 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2662 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2663 // idioms for rotate, and if the target supports rotation instructions, generate
2665 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2666 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2667 EVT VT = LHS.getValueType();
2668 if (!TLI.isTypeLegal(VT)) return 0;
2670 // The target must have at least one rotate flavor.
2671 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2672 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2673 if (!HasROTL && !HasROTR) return 0;
2675 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2676 SDValue LHSShift; // The shift.
2677 SDValue LHSMask; // AND value if any.
2678 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2679 return 0; // Not part of a rotate.
2681 SDValue RHSShift; // The shift.
2682 SDValue RHSMask; // AND value if any.
2683 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2684 return 0; // Not part of a rotate.
2686 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2687 return 0; // Not shifting the same value.
2689 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2690 return 0; // Shifts must disagree.
2692 // Canonicalize shl to left side in a shl/srl pair.
2693 if (RHSShift.getOpcode() == ISD::SHL) {
2694 std::swap(LHS, RHS);
2695 std::swap(LHSShift, RHSShift);
2696 std::swap(LHSMask , RHSMask );
2699 unsigned OpSizeInBits = VT.getSizeInBits();
2700 SDValue LHSShiftArg = LHSShift.getOperand(0);
2701 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2702 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2704 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2705 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2706 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2707 RHSShiftAmt.getOpcode() == ISD::Constant) {
2708 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2709 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2710 if ((LShVal + RShVal) != OpSizeInBits)
2715 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2717 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2719 // If there is an AND of either shifted operand, apply it to the result.
2720 if (LHSMask.getNode() || RHSMask.getNode()) {
2721 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2723 if (LHSMask.getNode()) {
2724 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2725 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2727 if (RHSMask.getNode()) {
2728 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2729 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2732 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2735 return Rot.getNode();
2738 // If there is a mask here, and we have a variable shift, we can't be sure
2739 // that we're masking out the right stuff.
2740 if (LHSMask.getNode() || RHSMask.getNode())
2743 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2744 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2745 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2746 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2747 if (ConstantSDNode *SUBC =
2748 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2749 if (SUBC->getAPIntValue() == OpSizeInBits) {
2751 return DAG.getNode(ISD::ROTL, DL, VT,
2752 LHSShiftArg, LHSShiftAmt).getNode();
2754 return DAG.getNode(ISD::ROTR, DL, VT,
2755 LHSShiftArg, RHSShiftAmt).getNode();
2760 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2761 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2762 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2763 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2764 if (ConstantSDNode *SUBC =
2765 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2766 if (SUBC->getAPIntValue() == OpSizeInBits) {
2768 return DAG.getNode(ISD::ROTR, DL, VT,
2769 LHSShiftArg, RHSShiftAmt).getNode();
2771 return DAG.getNode(ISD::ROTL, DL, VT,
2772 LHSShiftArg, LHSShiftAmt).getNode();
2777 // Look for sign/zext/any-extended or truncate cases:
2778 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2779 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2780 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2781 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2782 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2783 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2784 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2785 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2786 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2787 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2788 if (RExtOp0.getOpcode() == ISD::SUB &&
2789 RExtOp0.getOperand(1) == LExtOp0) {
2790 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2792 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2793 // (rotr x, (sub 32, y))
2794 if (ConstantSDNode *SUBC =
2795 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2796 if (SUBC->getAPIntValue() == OpSizeInBits) {
2797 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2799 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2802 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2803 RExtOp0 == LExtOp0.getOperand(1)) {
2804 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2806 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2807 // (rotl x, (sub 32, y))
2808 if (ConstantSDNode *SUBC =
2809 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2810 if (SUBC->getAPIntValue() == OpSizeInBits) {
2811 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2813 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2822 SDValue DAGCombiner::visitXOR(SDNode *N) {
2823 SDValue N0 = N->getOperand(0);
2824 SDValue N1 = N->getOperand(1);
2825 SDValue LHS, RHS, CC;
2826 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2827 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2828 EVT VT = N0.getValueType();
2831 if (VT.isVector()) {
2832 SDValue FoldedVOp = SimplifyVBinOp(N);
2833 if (FoldedVOp.getNode()) return FoldedVOp;
2836 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2837 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2838 return DAG.getConstant(0, VT);
2839 // fold (xor x, undef) -> undef
2840 if (N0.getOpcode() == ISD::UNDEF)
2842 if (N1.getOpcode() == ISD::UNDEF)
2844 // fold (xor c1, c2) -> c1^c2
2846 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2847 // canonicalize constant to RHS
2849 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2850 // fold (xor x, 0) -> x
2851 if (N1C && N1C->isNullValue())
2854 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2855 if (RXOR.getNode() != 0)
2858 // fold !(x cc y) -> (x !cc y)
2859 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2860 bool isInt = LHS.getValueType().isInteger();
2861 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2864 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2865 switch (N0.getOpcode()) {
2867 llvm_unreachable("Unhandled SetCC Equivalent!");
2869 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2870 case ISD::SELECT_CC:
2871 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2872 N0.getOperand(3), NotCC);
2877 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2878 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2879 N0.getNode()->hasOneUse() &&
2880 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2881 SDValue V = N0.getOperand(0);
2882 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2883 DAG.getConstant(1, V.getValueType()));
2884 AddToWorkList(V.getNode());
2885 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2888 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2889 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2890 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2891 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2892 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2893 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2894 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2895 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2896 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2897 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2900 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2901 if (N1C && N1C->isAllOnesValue() &&
2902 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2903 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2904 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2905 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2906 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2907 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2908 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2909 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2912 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2913 if (N1C && N0.getOpcode() == ISD::XOR) {
2914 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2915 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2917 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2918 DAG.getConstant(N1C->getAPIntValue() ^
2919 N00C->getAPIntValue(), VT));
2921 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2922 DAG.getConstant(N1C->getAPIntValue() ^
2923 N01C->getAPIntValue(), VT));
2925 // fold (xor x, x) -> 0
2927 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
2929 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2930 if (N0.getOpcode() == N1.getOpcode()) {
2931 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2932 if (Tmp.getNode()) return Tmp;
2935 // Simplify the expression using non-local knowledge.
2936 if (!VT.isVector() &&
2937 SimplifyDemandedBits(SDValue(N, 0)))
2938 return SDValue(N, 0);
2943 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2944 /// the shift amount is a constant.
2945 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2946 SDNode *LHS = N->getOperand(0).getNode();
2947 if (!LHS->hasOneUse()) return SDValue();
2949 // We want to pull some binops through shifts, so that we have (and (shift))
2950 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2951 // thing happens with address calculations, so it's important to canonicalize
2953 bool HighBitSet = false; // Can we transform this if the high bit is set?
2955 switch (LHS->getOpcode()) {
2956 default: return SDValue();
2959 HighBitSet = false; // We can only transform sra if the high bit is clear.
2962 HighBitSet = true; // We can only transform sra if the high bit is set.
2965 if (N->getOpcode() != ISD::SHL)
2966 return SDValue(); // only shl(add) not sr[al](add).
2967 HighBitSet = false; // We can only transform sra if the high bit is clear.
2971 // We require the RHS of the binop to be a constant as well.
2972 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2973 if (!BinOpCst) return SDValue();
2975 // FIXME: disable this unless the input to the binop is a shift by a constant.
2976 // If it is not a shift, it pessimizes some common cases like:
2978 // void foo(int *X, int i) { X[i & 1235] = 1; }
2979 // int bar(int *X, int i) { return X[i & 255]; }
2980 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2981 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2982 BinOpLHSVal->getOpcode() != ISD::SRA &&
2983 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2984 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2987 EVT VT = N->getValueType(0);
2989 // If this is a signed shift right, and the high bit is modified by the
2990 // logical operation, do not perform the transformation. The highBitSet
2991 // boolean indicates the value of the high bit of the constant which would
2992 // cause it to be modified for this operation.
2993 if (N->getOpcode() == ISD::SRA) {
2994 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2995 if (BinOpRHSSignSet != HighBitSet)
2999 // Fold the constants, shifting the binop RHS by the shift amount.
3000 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3002 LHS->getOperand(1), N->getOperand(1));
3004 // Create the new shift.
3005 SDValue NewShift = DAG.getNode(N->getOpcode(),
3006 LHS->getOperand(0).getDebugLoc(),
3007 VT, LHS->getOperand(0), N->getOperand(1));
3009 // Create the new binop.
3010 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3013 SDValue DAGCombiner::visitSHL(SDNode *N) {
3014 SDValue N0 = N->getOperand(0);
3015 SDValue N1 = N->getOperand(1);
3016 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3017 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3018 EVT VT = N0.getValueType();
3019 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3021 // fold (shl c1, c2) -> c1<<c2
3023 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3024 // fold (shl 0, x) -> 0
3025 if (N0C && N0C->isNullValue())
3027 // fold (shl x, c >= size(x)) -> undef
3028 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3029 return DAG.getUNDEF(VT);
3030 // fold (shl x, 0) -> x
3031 if (N1C && N1C->isNullValue())
3033 // fold (shl undef, x) -> 0
3034 if (N0.getOpcode() == ISD::UNDEF)
3035 return DAG.getConstant(0, VT);
3036 // if (shl x, c) is known to be zero, return 0
3037 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3038 APInt::getAllOnesValue(OpSizeInBits)))
3039 return DAG.getConstant(0, VT);
3040 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3041 if (N1.getOpcode() == ISD::TRUNCATE &&
3042 N1.getOperand(0).getOpcode() == ISD::AND &&
3043 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3044 SDValue N101 = N1.getOperand(0).getOperand(1);
3045 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3046 EVT TruncVT = N1.getValueType();
3047 SDValue N100 = N1.getOperand(0).getOperand(0);
3048 APInt TruncC = N101C->getAPIntValue();
3049 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3050 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3051 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3052 DAG.getNode(ISD::TRUNCATE,
3055 DAG.getConstant(TruncC, TruncVT)));
3059 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3060 return SDValue(N, 0);
3062 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3063 if (N1C && N0.getOpcode() == ISD::SHL &&
3064 N0.getOperand(1).getOpcode() == ISD::Constant) {
3065 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3066 uint64_t c2 = N1C->getZExtValue();
3067 if (c1 + c2 >= OpSizeInBits)
3068 return DAG.getConstant(0, VT);
3069 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3070 DAG.getConstant(c1 + c2, N1.getValueType()));
3073 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3074 // For this to be valid, the second form must not preserve any of the bits
3075 // that are shifted out by the inner shift in the first form. This means
3076 // the outer shift size must be >= the number of bits added by the ext.
3077 // As a corollary, we don't care what kind of ext it is.
3078 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3079 N0.getOpcode() == ISD::ANY_EXTEND ||
3080 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3081 N0.getOperand(0).getOpcode() == ISD::SHL &&
3082 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3084 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3085 uint64_t c2 = N1C->getZExtValue();
3086 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3087 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3088 if (c2 >= OpSizeInBits - InnerShiftSize) {
3089 if (c1 + c2 >= OpSizeInBits)
3090 return DAG.getConstant(0, VT);
3091 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3092 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3093 N0.getOperand(0)->getOperand(0)),
3094 DAG.getConstant(c1 + c2, N1.getValueType()));
3098 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3099 // (and (srl x, (sub c1, c2), MASK)
3100 if (N1C && N0.getOpcode() == ISD::SRL &&
3101 N0.getOperand(1).getOpcode() == ISD::Constant) {
3102 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3103 if (c1 < VT.getSizeInBits()) {
3104 uint64_t c2 = N1C->getZExtValue();
3105 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3106 VT.getSizeInBits() - c1);
3109 Mask = Mask.shl(c2-c1);
3110 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3111 DAG.getConstant(c2-c1, N1.getValueType()));
3113 Mask = Mask.lshr(c1-c2);
3114 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3115 DAG.getConstant(c1-c2, N1.getValueType()));
3117 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3118 DAG.getConstant(Mask, VT));
3121 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3122 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3123 SDValue HiBitsMask =
3124 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3125 VT.getSizeInBits() -
3126 N1C->getZExtValue()),
3128 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3133 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3134 if (NewSHL.getNode())
3141 SDValue DAGCombiner::visitSRA(SDNode *N) {
3142 SDValue N0 = N->getOperand(0);
3143 SDValue N1 = N->getOperand(1);
3144 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3145 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3146 EVT VT = N0.getValueType();
3147 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3149 // fold (sra c1, c2) -> (sra c1, c2)
3151 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3152 // fold (sra 0, x) -> 0
3153 if (N0C && N0C->isNullValue())
3155 // fold (sra -1, x) -> -1
3156 if (N0C && N0C->isAllOnesValue())
3158 // fold (sra x, (setge c, size(x))) -> undef
3159 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3160 return DAG.getUNDEF(VT);
3161 // fold (sra x, 0) -> x
3162 if (N1C && N1C->isNullValue())
3164 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3166 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3167 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3168 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3170 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3171 ExtVT, VT.getVectorNumElements());
3172 if ((!LegalOperations ||
3173 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3174 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3175 N0.getOperand(0), DAG.getValueType(ExtVT));
3178 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3179 if (N1C && N0.getOpcode() == ISD::SRA) {
3180 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3181 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3182 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3183 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3184 DAG.getConstant(Sum, N1C->getValueType(0)));
3188 // fold (sra (shl X, m), (sub result_size, n))
3189 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3190 // result_size - n != m.
3191 // If truncate is free for the target sext(shl) is likely to result in better
3193 if (N0.getOpcode() == ISD::SHL) {
3194 // Get the two constanst of the shifts, CN0 = m, CN = n.
3195 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3197 // Determine what the truncate's result bitsize and type would be.
3199 EVT::getIntegerVT(*DAG.getContext(),
3200 OpSizeInBits - N1C->getZExtValue());
3201 // Determine the residual right-shift amount.
3202 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3204 // If the shift is not a no-op (in which case this should be just a sign
3205 // extend already), the truncated to type is legal, sign_extend is legal
3206 // on that type, and the truncate to that type is both legal and free,
3207 // perform the transform.
3208 if ((ShiftAmt > 0) &&
3209 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3210 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3211 TLI.isTruncateFree(VT, TruncVT)) {
3213 SDValue Amt = DAG.getConstant(ShiftAmt,
3214 getShiftAmountTy(N0.getOperand(0).getValueType()));
3215 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3216 N0.getOperand(0), Amt);
3217 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3219 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3220 N->getValueType(0), Trunc);
3225 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3226 if (N1.getOpcode() == ISD::TRUNCATE &&
3227 N1.getOperand(0).getOpcode() == ISD::AND &&
3228 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3229 SDValue N101 = N1.getOperand(0).getOperand(1);
3230 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3231 EVT TruncVT = N1.getValueType();
3232 SDValue N100 = N1.getOperand(0).getOperand(0);
3233 APInt TruncC = N101C->getAPIntValue();
3234 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3235 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3236 DAG.getNode(ISD::AND, N->getDebugLoc(),
3238 DAG.getNode(ISD::TRUNCATE,
3241 DAG.getConstant(TruncC, TruncVT)));
3245 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3246 // if c1 is equal to the number of bits the trunc removes
3247 if (N0.getOpcode() == ISD::TRUNCATE &&
3248 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3249 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3250 N0.getOperand(0).hasOneUse() &&
3251 N0.getOperand(0).getOperand(1).hasOneUse() &&
3252 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3253 EVT LargeVT = N0.getOperand(0).getValueType();
3254 ConstantSDNode *LargeShiftAmt =
3255 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3257 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3258 LargeShiftAmt->getZExtValue()) {
3260 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3261 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3262 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3263 N0.getOperand(0).getOperand(0), Amt);
3264 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3268 // Simplify, based on bits shifted out of the LHS.
3269 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3270 return SDValue(N, 0);
3273 // If the sign bit is known to be zero, switch this to a SRL.
3274 if (DAG.SignBitIsZero(N0))
3275 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3278 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3279 if (NewSRA.getNode())
3286 SDValue DAGCombiner::visitSRL(SDNode *N) {
3287 SDValue N0 = N->getOperand(0);
3288 SDValue N1 = N->getOperand(1);
3289 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3290 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3291 EVT VT = N0.getValueType();
3292 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3294 // fold (srl c1, c2) -> c1 >>u c2
3296 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3297 // fold (srl 0, x) -> 0
3298 if (N0C && N0C->isNullValue())
3300 // fold (srl x, c >= size(x)) -> undef
3301 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3302 return DAG.getUNDEF(VT);
3303 // fold (srl x, 0) -> x
3304 if (N1C && N1C->isNullValue())
3306 // if (srl x, c) is known to be zero, return 0
3307 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3308 APInt::getAllOnesValue(OpSizeInBits)))
3309 return DAG.getConstant(0, VT);
3311 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3312 if (N1C && N0.getOpcode() == ISD::SRL &&
3313 N0.getOperand(1).getOpcode() == ISD::Constant) {
3314 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3315 uint64_t c2 = N1C->getZExtValue();
3316 if (c1 + c2 >= OpSizeInBits)
3317 return DAG.getConstant(0, VT);
3318 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3319 DAG.getConstant(c1 + c2, N1.getValueType()));
3322 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3323 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3324 N0.getOperand(0).getOpcode() == ISD::SRL &&
3325 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3327 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3328 uint64_t c2 = N1C->getZExtValue();
3329 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3330 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3331 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3332 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3333 if (c1 + OpSizeInBits == InnerShiftSize) {
3334 if (c1 + c2 >= InnerShiftSize)
3335 return DAG.getConstant(0, VT);
3336 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3337 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3338 N0.getOperand(0)->getOperand(0),
3339 DAG.getConstant(c1 + c2, ShiftCountVT)));
3343 // fold (srl (shl x, c), c) -> (and x, cst2)
3344 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3345 N0.getValueSizeInBits() <= 64) {
3346 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3347 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3348 DAG.getConstant(~0ULL >> ShAmt, VT));
3352 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3353 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3354 // Shifting in all undef bits?
3355 EVT SmallVT = N0.getOperand(0).getValueType();
3356 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3357 return DAG.getUNDEF(VT);
3359 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3360 uint64_t ShiftAmt = N1C->getZExtValue();
3361 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3363 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3364 AddToWorkList(SmallShift.getNode());
3365 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3369 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3370 // bit, which is unmodified by sra.
3371 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3372 if (N0.getOpcode() == ISD::SRA)
3373 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3376 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3377 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3378 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3379 APInt KnownZero, KnownOne;
3380 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3381 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3383 // If any of the input bits are KnownOne, then the input couldn't be all
3384 // zeros, thus the result of the srl will always be zero.
3385 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3387 // If all of the bits input the to ctlz node are known to be zero, then
3388 // the result of the ctlz is "32" and the result of the shift is one.
3389 APInt UnknownBits = ~KnownZero & Mask;
3390 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3392 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3393 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3394 // Okay, we know that only that the single bit specified by UnknownBits
3395 // could be set on input to the CTLZ node. If this bit is set, the SRL
3396 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3397 // to an SRL/XOR pair, which is likely to simplify more.
3398 unsigned ShAmt = UnknownBits.countTrailingZeros();
3399 SDValue Op = N0.getOperand(0);
3402 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3403 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3404 AddToWorkList(Op.getNode());
3407 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3408 Op, DAG.getConstant(1, VT));
3412 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3413 if (N1.getOpcode() == ISD::TRUNCATE &&
3414 N1.getOperand(0).getOpcode() == ISD::AND &&
3415 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3416 SDValue N101 = N1.getOperand(0).getOperand(1);
3417 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3418 EVT TruncVT = N1.getValueType();
3419 SDValue N100 = N1.getOperand(0).getOperand(0);
3420 APInt TruncC = N101C->getAPIntValue();
3421 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3422 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3423 DAG.getNode(ISD::AND, N->getDebugLoc(),
3425 DAG.getNode(ISD::TRUNCATE,
3428 DAG.getConstant(TruncC, TruncVT)));
3432 // fold operands of srl based on knowledge that the low bits are not
3434 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3435 return SDValue(N, 0);
3438 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3439 if (NewSRL.getNode())
3443 // Attempt to convert a srl of a load into a narrower zero-extending load.
3444 SDValue NarrowLoad = ReduceLoadWidth(N);
3445 if (NarrowLoad.getNode())
3448 // Here is a common situation. We want to optimize:
3451 // %b = and i32 %a, 2
3452 // %c = srl i32 %b, 1
3453 // brcond i32 %c ...
3459 // %c = setcc eq %b, 0
3462 // However when after the source operand of SRL is optimized into AND, the SRL
3463 // itself may not be optimized further. Look for it and add the BRCOND into
3465 if (N->hasOneUse()) {
3466 SDNode *Use = *N->use_begin();
3467 if (Use->getOpcode() == ISD::BRCOND)
3469 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3470 // Also look pass the truncate.
3471 Use = *Use->use_begin();
3472 if (Use->getOpcode() == ISD::BRCOND)
3480 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3481 SDValue N0 = N->getOperand(0);
3482 EVT VT = N->getValueType(0);
3484 // fold (ctlz c1) -> c2
3485 if (isa<ConstantSDNode>(N0))
3486 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3490 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3491 SDValue N0 = N->getOperand(0);
3492 EVT VT = N->getValueType(0);
3494 // fold (cttz c1) -> c2
3495 if (isa<ConstantSDNode>(N0))
3496 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3500 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3501 SDValue N0 = N->getOperand(0);
3502 EVT VT = N->getValueType(0);
3504 // fold (ctpop c1) -> c2
3505 if (isa<ConstantSDNode>(N0))
3506 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3510 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3511 SDValue N0 = N->getOperand(0);
3512 SDValue N1 = N->getOperand(1);
3513 SDValue N2 = N->getOperand(2);
3514 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3515 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3516 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3517 EVT VT = N->getValueType(0);
3518 EVT VT0 = N0.getValueType();
3520 // fold (select C, X, X) -> X
3523 // fold (select true, X, Y) -> X
3524 if (N0C && !N0C->isNullValue())
3526 // fold (select false, X, Y) -> Y
3527 if (N0C && N0C->isNullValue())
3529 // fold (select C, 1, X) -> (or C, X)
3530 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3531 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3532 // fold (select C, 0, 1) -> (xor C, 1)
3533 if (VT.isInteger() &&
3536 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
3537 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3540 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3541 N0, DAG.getConstant(1, VT0));
3542 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3543 N0, DAG.getConstant(1, VT0));
3544 AddToWorkList(XORNode.getNode());
3546 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3547 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3549 // fold (select C, 0, X) -> (and (not C), X)
3550 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3551 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3552 AddToWorkList(NOTNode.getNode());
3553 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3555 // fold (select C, X, 1) -> (or (not C), X)
3556 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3557 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3558 AddToWorkList(NOTNode.getNode());
3559 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3561 // fold (select C, X, 0) -> (and C, X)
3562 if (VT == MVT::i1 && N2C && N2C->isNullValue())
3563 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3564 // fold (select X, X, Y) -> (or X, Y)
3565 // fold (select X, 1, Y) -> (or X, Y)
3566 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3567 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3568 // fold (select X, Y, X) -> (and X, Y)
3569 // fold (select X, Y, 0) -> (and X, Y)
3570 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3571 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3573 // If we can fold this based on the true/false value, do so.
3574 if (SimplifySelectOps(N, N1, N2))
3575 return SDValue(N, 0); // Don't revisit N.
3577 // fold selects based on a setcc into other things, such as min/max/abs
3578 if (N0.getOpcode() == ISD::SETCC) {
3580 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3581 // having to say they don't support SELECT_CC on every type the DAG knows
3582 // about, since there is no way to mark an opcode illegal at all value types
3583 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3584 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3585 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3586 N0.getOperand(0), N0.getOperand(1),
3587 N1, N2, N0.getOperand(2));
3588 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3594 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3595 SDValue N0 = N->getOperand(0);
3596 SDValue N1 = N->getOperand(1);
3597 SDValue N2 = N->getOperand(2);
3598 SDValue N3 = N->getOperand(3);
3599 SDValue N4 = N->getOperand(4);
3600 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3602 // fold select_cc lhs, rhs, x, x, cc -> x
3606 // Determine if the condition we're dealing with is constant
3607 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3608 N0, N1, CC, N->getDebugLoc(), false);
3609 if (SCC.getNode()) AddToWorkList(SCC.getNode());
3611 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3612 if (!SCCC->isNullValue())
3613 return N2; // cond always true -> true val
3615 return N3; // cond always false -> false val
3618 // Fold to a simpler select_cc
3619 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3620 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3621 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3624 // If we can fold this based on the true/false value, do so.
3625 if (SimplifySelectOps(N, N2, N3))
3626 return SDValue(N, 0); // Don't revisit N.
3628 // fold select_cc into other things, such as min/max/abs
3629 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3632 SDValue DAGCombiner::visitSETCC(SDNode *N) {
3633 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3634 cast<CondCodeSDNode>(N->getOperand(2))->get(),
3638 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3639 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3640 // transformation. Returns true if extension are possible and the above
3641 // mentioned transformation is profitable.
3642 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3644 SmallVector<SDNode*, 4> &ExtendNodes,
3645 const TargetLowering &TLI) {
3646 bool HasCopyToRegUses = false;
3647 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3648 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3649 UE = N0.getNode()->use_end();
3654 if (UI.getUse().getResNo() != N0.getResNo())
3656 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3657 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3658 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3659 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3660 // Sign bits will be lost after a zext.
3663 for (unsigned i = 0; i != 2; ++i) {
3664 SDValue UseOp = User->getOperand(i);
3667 if (!isa<ConstantSDNode>(UseOp))
3672 ExtendNodes.push_back(User);
3675 // If truncates aren't free and there are users we can't
3676 // extend, it isn't worthwhile.
3679 // Remember if this value is live-out.
3680 if (User->getOpcode() == ISD::CopyToReg)
3681 HasCopyToRegUses = true;
3684 if (HasCopyToRegUses) {
3685 bool BothLiveOut = false;
3686 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3688 SDUse &Use = UI.getUse();
3689 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3695 // Both unextended and extended values are live out. There had better be
3696 // a good reason for the transformation.
3697 return ExtendNodes.size();
3702 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3703 SDValue N0 = N->getOperand(0);
3704 EVT VT = N->getValueType(0);
3706 // fold (sext c1) -> c1
3707 if (isa<ConstantSDNode>(N0))
3708 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3710 // fold (sext (sext x)) -> (sext x)
3711 // fold (sext (aext x)) -> (sext x)
3712 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3713 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3716 if (N0.getOpcode() == ISD::TRUNCATE) {
3717 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3718 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3719 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3720 if (NarrowLoad.getNode()) {
3721 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3722 if (NarrowLoad.getNode() != N0.getNode()) {
3723 CombineTo(N0.getNode(), NarrowLoad);
3724 // CombineTo deleted the truncate, if needed, but not what's under it.
3727 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3730 // See if the value being truncated is already sign extended. If so, just
3731 // eliminate the trunc/sext pair.
3732 SDValue Op = N0.getOperand(0);
3733 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
3734 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
3735 unsigned DestBits = VT.getScalarType().getSizeInBits();
3736 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3738 if (OpBits == DestBits) {
3739 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3740 // bits, it is already ready.
3741 if (NumSignBits > DestBits-MidBits)
3743 } else if (OpBits < DestBits) {
3744 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3745 // bits, just sext from i32.
3746 if (NumSignBits > OpBits-MidBits)
3747 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3749 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3750 // bits, just truncate to i32.
3751 if (NumSignBits > OpBits-MidBits)
3752 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3755 // fold (sext (truncate x)) -> (sextinreg x).
3756 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3757 N0.getValueType())) {
3758 if (OpBits < DestBits)
3759 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3760 else if (OpBits > DestBits)
3761 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3762 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3763 DAG.getValueType(N0.getValueType()));
3767 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3768 // None of the supported targets knows how to perform load and sign extend
3769 // on vectors in one instruction. We only perform this transformation on
3771 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
3772 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3773 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3774 bool DoXform = true;
3775 SmallVector<SDNode*, 4> SetCCs;
3776 if (!N0.hasOneUse())
3777 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3779 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3780 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3782 LN0->getBasePtr(), LN0->getPointerInfo(),
3784 LN0->isVolatile(), LN0->isNonTemporal(),
3785 LN0->getAlignment());
3786 CombineTo(N, ExtLoad);
3787 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3788 N0.getValueType(), ExtLoad);
3789 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3791 // Extend SetCC uses if necessary.
3792 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3793 SDNode *SetCC = SetCCs[i];
3794 SmallVector<SDValue, 4> Ops;
3796 for (unsigned j = 0; j != 2; ++j) {
3797 SDValue SOp = SetCC->getOperand(j);
3799 Ops.push_back(ExtLoad);
3801 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3802 N->getDebugLoc(), VT, SOp));
3805 Ops.push_back(SetCC->getOperand(2));
3806 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3807 SetCC->getValueType(0),
3808 &Ops[0], Ops.size()));
3811 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3815 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3816 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3817 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3818 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3819 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3820 EVT MemVT = LN0->getMemoryVT();
3821 if ((!LegalOperations && !LN0->isVolatile()) ||
3822 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
3823 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3825 LN0->getBasePtr(), LN0->getPointerInfo(),
3827 LN0->isVolatile(), LN0->isNonTemporal(),
3828 LN0->getAlignment());
3829 CombineTo(N, ExtLoad);
3830 CombineTo(N0.getNode(),
3831 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3832 N0.getValueType(), ExtLoad),
3833 ExtLoad.getValue(1));
3834 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3838 if (N0.getOpcode() == ISD::SETCC) {
3839 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
3840 // Only do this before legalize for now.
3841 if (VT.isVector() && !LegalOperations) {
3842 EVT N0VT = N0.getOperand(0).getValueType();
3843 // We know that the # elements of the results is the same as the
3844 // # elements of the compare (and the # elements of the compare result
3845 // for that matter). Check to see that they are the same size. If so,
3846 // we know that the element size of the sext'd result matches the
3847 // element size of the compare operands.
3848 if (VT.getSizeInBits() == N0VT.getSizeInBits())
3849 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3851 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3852 // If the desired elements are smaller or larger than the source
3853 // elements we can use a matching integer vector type and then
3854 // truncate/sign extend
3856 EVT MatchingElementType =
3857 EVT::getIntegerVT(*DAG.getContext(),
3858 N0VT.getScalarType().getSizeInBits());
3859 EVT MatchingVectorType =
3860 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
3861 N0VT.getVectorNumElements());
3863 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
3865 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3866 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
3870 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3871 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
3873 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
3875 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3876 NegOne, DAG.getConstant(0, VT),
3877 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3878 if (SCC.getNode()) return SCC;
3879 if (!LegalOperations ||
3880 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
3881 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3882 DAG.getSetCC(N->getDebugLoc(),
3883 TLI.getSetCCResultType(VT),
3884 N0.getOperand(0), N0.getOperand(1),
3885 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3886 NegOne, DAG.getConstant(0, VT));
3889 // fold (sext x) -> (zext x) if the sign bit is known zero.
3890 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3891 DAG.SignBitIsZero(N0))
3892 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3897 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3898 SDValue N0 = N->getOperand(0);
3899 EVT VT = N->getValueType(0);
3901 // fold (zext c1) -> c1
3902 if (isa<ConstantSDNode>(N0))
3903 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3904 // fold (zext (zext x)) -> (zext x)
3905 // fold (zext (aext x)) -> (zext x)
3906 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3907 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3910 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3911 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3912 if (N0.getOpcode() == ISD::TRUNCATE) {
3913 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3914 if (NarrowLoad.getNode()) {
3915 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3916 if (NarrowLoad.getNode() != N0.getNode()) {
3917 CombineTo(N0.getNode(), NarrowLoad);
3918 // CombineTo deleted the truncate, if needed, but not what's under it.
3921 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3925 // fold (zext (truncate x)) -> (and x, mask)
3926 if (N0.getOpcode() == ISD::TRUNCATE &&
3927 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
3929 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3930 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
3931 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3932 if (NarrowLoad.getNode()) {
3933 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3934 if (NarrowLoad.getNode() != N0.getNode()) {
3935 CombineTo(N0.getNode(), NarrowLoad);
3936 // CombineTo deleted the truncate, if needed, but not what's under it.
3939 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3942 SDValue Op = N0.getOperand(0);
3943 if (Op.getValueType().bitsLT(VT)) {
3944 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3945 } else if (Op.getValueType().bitsGT(VT)) {
3946 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3948 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
3949 N0.getValueType().getScalarType());
3952 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
3953 // if either of the casts is not free.
3954 if (N0.getOpcode() == ISD::AND &&
3955 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3956 N0.getOperand(1).getOpcode() == ISD::Constant &&
3957 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3958 N0.getValueType()) ||
3959 !TLI.isZExtFree(N0.getValueType(), VT))) {
3960 SDValue X = N0.getOperand(0).getOperand(0);
3961 if (X.getValueType().bitsLT(VT)) {
3962 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3963 } else if (X.getValueType().bitsGT(VT)) {
3964 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3966 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3967 Mask = Mask.zext(VT.getSizeInBits());
3968 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3969 X, DAG.getConstant(Mask, VT));
3972 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3973 // None of the supported targets knows how to perform load and vector_zext
3974 // on vectors in one instruction. We only perform this transformation on
3976 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
3977 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3978 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3979 bool DoXform = true;
3980 SmallVector<SDNode*, 4> SetCCs;
3981 if (!N0.hasOneUse())
3982 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3984 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3985 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3987 LN0->getBasePtr(), LN0->getPointerInfo(),
3989 LN0->isVolatile(), LN0->isNonTemporal(),
3990 LN0->getAlignment());
3991 CombineTo(N, ExtLoad);
3992 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3993 N0.getValueType(), ExtLoad);
3994 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3996 // Extend SetCC uses if necessary.
3997 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3998 SDNode *SetCC = SetCCs[i];
3999 SmallVector<SDValue, 4> Ops;
4001 for (unsigned j = 0; j != 2; ++j) {
4002 SDValue SOp = SetCC->getOperand(j);
4004 Ops.push_back(ExtLoad);
4006 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
4007 N->getDebugLoc(), VT, SOp));
4010 Ops.push_back(SetCC->getOperand(2));
4011 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
4012 SetCC->getValueType(0),
4013 &Ops[0], Ops.size()));
4016 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4020 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4021 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4022 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4023 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4024 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4025 EVT MemVT = LN0->getMemoryVT();
4026 if ((!LegalOperations && !LN0->isVolatile()) ||
4027 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4028 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4030 LN0->getBasePtr(), LN0->getPointerInfo(),
4032 LN0->isVolatile(), LN0->isNonTemporal(),
4033 LN0->getAlignment());
4034 CombineTo(N, ExtLoad);
4035 CombineTo(N0.getNode(),
4036 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4038 ExtLoad.getValue(1));
4039 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4043 if (N0.getOpcode() == ISD::SETCC) {
4044 if (!LegalOperations && VT.isVector()) {
4045 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4046 // Only do this before legalize for now.
4047 EVT N0VT = N0.getOperand(0).getValueType();
4048 EVT EltVT = VT.getVectorElementType();
4049 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4050 DAG.getConstant(1, EltVT));
4051 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4052 // We know that the # elements of the results is the same as the
4053 // # elements of the compare (and the # elements of the compare result
4054 // for that matter). Check to see that they are the same size. If so,
4055 // we know that the element size of the sext'd result matches the
4056 // element size of the compare operands.
4057 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4058 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4060 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4061 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4062 &OneOps[0], OneOps.size()));
4064 // If the desired elements are smaller or larger than the source
4065 // elements we can use a matching integer vector type and then
4066 // truncate/sign extend
4067 EVT MatchingElementType =
4068 EVT::getIntegerVT(*DAG.getContext(),
4069 N0VT.getScalarType().getSizeInBits());
4070 EVT MatchingVectorType =
4071 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4072 N0VT.getVectorNumElements());
4074 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4076 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4077 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4078 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4079 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4080 &OneOps[0], OneOps.size()));
4083 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4085 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4086 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4087 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4088 if (SCC.getNode()) return SCC;
4091 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4092 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4093 isa<ConstantSDNode>(N0.getOperand(1)) &&
4094 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4096 SDValue ShAmt = N0.getOperand(1);
4097 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4098 if (N0.getOpcode() == ISD::SHL) {
4099 SDValue InnerZExt = N0.getOperand(0);
4100 // If the original shl may be shifting out bits, do not perform this
4102 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4103 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4104 if (ShAmtVal > KnownZeroBits)
4108 DebugLoc DL = N->getDebugLoc();
4110 // Ensure that the shift amount is wide enough for the shifted value.
4111 if (VT.getSizeInBits() >= 256)
4112 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4114 return DAG.getNode(N0.getOpcode(), DL, VT,
4115 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4122 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4123 SDValue N0 = N->getOperand(0);
4124 EVT VT = N->getValueType(0);
4126 // fold (aext c1) -> c1
4127 if (isa<ConstantSDNode>(N0))
4128 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4129 // fold (aext (aext x)) -> (aext x)
4130 // fold (aext (zext x)) -> (zext x)
4131 // fold (aext (sext x)) -> (sext x)
4132 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4133 N0.getOpcode() == ISD::ZERO_EXTEND ||
4134 N0.getOpcode() == ISD::SIGN_EXTEND)
4135 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4137 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4138 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4139 if (N0.getOpcode() == ISD::TRUNCATE) {
4140 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4141 if (NarrowLoad.getNode()) {
4142 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4143 if (NarrowLoad.getNode() != N0.getNode()) {
4144 CombineTo(N0.getNode(), NarrowLoad);
4145 // CombineTo deleted the truncate, if needed, but not what's under it.
4148 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4152 // fold (aext (truncate x))
4153 if (N0.getOpcode() == ISD::TRUNCATE) {
4154 SDValue TruncOp = N0.getOperand(0);
4155 if (TruncOp.getValueType() == VT)
4156 return TruncOp; // x iff x size == zext size.
4157 if (TruncOp.getValueType().bitsGT(VT))
4158 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4159 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4162 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4163 // if the trunc is not free.
4164 if (N0.getOpcode() == ISD::AND &&
4165 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4166 N0.getOperand(1).getOpcode() == ISD::Constant &&
4167 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4168 N0.getValueType())) {
4169 SDValue X = N0.getOperand(0).getOperand(0);
4170 if (X.getValueType().bitsLT(VT)) {
4171 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4172 } else if (X.getValueType().bitsGT(VT)) {
4173 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4175 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4176 Mask = Mask.zext(VT.getSizeInBits());
4177 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4178 X, DAG.getConstant(Mask, VT));
4181 // fold (aext (load x)) -> (aext (truncate (extload x)))
4182 // None of the supported targets knows how to perform load and any_ext
4183 // on vectors in one instruction. We only perform this transformation on
4185 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4186 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4187 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4188 bool DoXform = true;
4189 SmallVector<SDNode*, 4> SetCCs;
4190 if (!N0.hasOneUse())
4191 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4193 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4194 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4196 LN0->getBasePtr(), LN0->getPointerInfo(),
4198 LN0->isVolatile(), LN0->isNonTemporal(),
4199 LN0->getAlignment());
4200 CombineTo(N, ExtLoad);
4201 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4202 N0.getValueType(), ExtLoad);
4203 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4205 // Extend SetCC uses if necessary.
4206 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
4207 SDNode *SetCC = SetCCs[i];
4208 SmallVector<SDValue, 4> Ops;
4210 for (unsigned j = 0; j != 2; ++j) {
4211 SDValue SOp = SetCC->getOperand(j);
4213 Ops.push_back(ExtLoad);
4215 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
4216 N->getDebugLoc(), VT, SOp));
4219 Ops.push_back(SetCC->getOperand(2));
4220 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
4221 SetCC->getValueType(0),
4222 &Ops[0], Ops.size()));
4225 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4229 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4230 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4231 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4232 if (N0.getOpcode() == ISD::LOAD &&
4233 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4235 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4236 EVT MemVT = LN0->getMemoryVT();
4237 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4238 VT, LN0->getChain(), LN0->getBasePtr(),
4239 LN0->getPointerInfo(), MemVT,
4240 LN0->isVolatile(), LN0->isNonTemporal(),
4241 LN0->getAlignment());
4242 CombineTo(N, ExtLoad);
4243 CombineTo(N0.getNode(),
4244 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4245 N0.getValueType(), ExtLoad),
4246 ExtLoad.getValue(1));
4247 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4250 if (N0.getOpcode() == ISD::SETCC) {
4251 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4252 // Only do this before legalize for now.
4253 if (VT.isVector() && !LegalOperations) {
4254 EVT N0VT = N0.getOperand(0).getValueType();
4255 // We know that the # elements of the results is the same as the
4256 // # elements of the compare (and the # elements of the compare result
4257 // for that matter). Check to see that they are the same size. If so,
4258 // we know that the element size of the sext'd result matches the
4259 // element size of the compare operands.
4260 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4261 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4263 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4264 // If the desired elements are smaller or larger than the source
4265 // elements we can use a matching integer vector type and then
4266 // truncate/sign extend
4268 EVT MatchingElementType =
4269 EVT::getIntegerVT(*DAG.getContext(),
4270 N0VT.getScalarType().getSizeInBits());
4271 EVT MatchingVectorType =
4272 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4273 N0VT.getVectorNumElements());
4275 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4277 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4278 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4282 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4284 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4285 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4286 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4294 /// GetDemandedBits - See if the specified operand can be simplified with the
4295 /// knowledge that only the bits specified by Mask are used. If so, return the
4296 /// simpler operand, otherwise return a null SDValue.
4297 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4298 switch (V.getOpcode()) {
4302 // If the LHS or RHS don't contribute bits to the or, drop them.
4303 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4304 return V.getOperand(1);
4305 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4306 return V.getOperand(0);
4309 // Only look at single-use SRLs.
4310 if (!V.getNode()->hasOneUse())
4312 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4313 // See if we can recursively simplify the LHS.
4314 unsigned Amt = RHSC->getZExtValue();
4316 // Watch out for shift count overflow though.
4317 if (Amt >= Mask.getBitWidth()) break;
4318 APInt NewMask = Mask << Amt;
4319 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4320 if (SimplifyLHS.getNode())
4321 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4322 SimplifyLHS, V.getOperand(1));
4328 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4329 /// bits and then truncated to a narrower type and where N is a multiple
4330 /// of number of bits of the narrower type, transform it to a narrower load
4331 /// from address + N / num of bits of new type. If the result is to be
4332 /// extended, also fold the extension to form a extending load.
4333 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4334 unsigned Opc = N->getOpcode();
4336 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4337 SDValue N0 = N->getOperand(0);
4338 EVT VT = N->getValueType(0);
4341 // This transformation isn't valid for vector loads.
4345 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4347 if (Opc == ISD::SIGN_EXTEND_INREG) {
4348 ExtType = ISD::SEXTLOAD;
4349 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4350 } else if (Opc == ISD::SRL) {
4351 // Another special-case: SRL is basically zero-extending a narrower value.
4352 ExtType = ISD::ZEXTLOAD;
4354 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4355 if (!N01) return SDValue();
4356 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4357 VT.getSizeInBits() - N01->getZExtValue());
4359 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
4362 unsigned EVTBits = ExtVT.getSizeInBits();
4364 // Do not generate loads of non-round integer types since these can
4365 // be expensive (and would be wrong if the type is not byte sized).
4366 if (!ExtVT.isRound())
4370 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4371 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4372 ShAmt = N01->getZExtValue();
4373 // Is the shift amount a multiple of size of VT?
4374 if ((ShAmt & (EVTBits-1)) == 0) {
4375 N0 = N0.getOperand(0);
4376 // Is the load width a multiple of size of VT?
4377 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4381 // At this point, we must have a load or else we can't do the transform.
4382 if (!isa<LoadSDNode>(N0)) return SDValue();
4384 // If the shift amount is larger than the input type then we're not
4385 // accessing any of the loaded bytes. If the load was a zextload/extload
4386 // then the result of the shift+trunc is zero/undef (handled elsewhere).
4387 // If the load was a sextload then the result is a splat of the sign bit
4388 // of the extended byte. This is not worth optimizing for.
4389 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
4394 // If the load is shifted left (and the result isn't shifted back right),
4395 // we can fold the truncate through the shift.
4396 unsigned ShLeftAmt = 0;
4397 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
4398 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
4399 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4400 ShLeftAmt = N01->getZExtValue();
4401 N0 = N0.getOperand(0);
4405 // If we haven't found a load, we can't narrow it. Don't transform one with
4406 // multiple uses, this would require adding a new load.
4407 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
4408 // Don't change the width of a volatile load.
4409 cast<LoadSDNode>(N0)->isVolatile())
4412 // Verify that we are actually reducing a load width here.
4413 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
4416 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4417 EVT PtrType = N0.getOperand(1).getValueType();
4419 // For big endian targets, we need to adjust the offset to the pointer to
4420 // load the correct bytes.
4421 if (TLI.isBigEndian()) {
4422 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4423 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4424 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4427 uint64_t PtrOff = ShAmt / 8;
4428 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4429 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4430 PtrType, LN0->getBasePtr(),
4431 DAG.getConstant(PtrOff, PtrType));
4432 AddToWorkList(NewPtr.getNode());
4435 if (ExtType == ISD::NON_EXTLOAD)
4436 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4437 LN0->getPointerInfo().getWithOffset(PtrOff),
4438 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign);
4440 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
4441 LN0->getPointerInfo().getWithOffset(PtrOff),
4442 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4445 // Replace the old load's chain with the new load's chain.
4446 WorkListRemover DeadNodes(*this);
4447 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4450 // Shift the result left, if we've swallowed a left shift.
4451 SDValue Result = Load;
4452 if (ShLeftAmt != 0) {
4453 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
4454 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
4456 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
4457 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
4460 // Return the new loaded value.
4464 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4465 SDValue N0 = N->getOperand(0);
4466 SDValue N1 = N->getOperand(1);
4467 EVT VT = N->getValueType(0);
4468 EVT EVT = cast<VTSDNode>(N1)->getVT();
4469 unsigned VTBits = VT.getScalarType().getSizeInBits();
4470 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4472 // fold (sext_in_reg c1) -> c1
4473 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4474 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4476 // If the input is already sign extended, just drop the extension.
4477 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4480 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4481 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4482 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4483 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4484 N0.getOperand(0), N1);
4487 // fold (sext_in_reg (sext x)) -> (sext x)
4488 // fold (sext_in_reg (aext x)) -> (sext x)
4489 // if x is small enough.
4490 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4491 SDValue N00 = N0.getOperand(0);
4492 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4493 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4494 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4497 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4498 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4499 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4501 // fold operands of sext_in_reg based on knowledge that the top bits are not
4503 if (SimplifyDemandedBits(SDValue(N, 0)))
4504 return SDValue(N, 0);
4506 // fold (sext_in_reg (load x)) -> (smaller sextload x)
4507 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4508 SDValue NarrowLoad = ReduceLoadWidth(N);
4509 if (NarrowLoad.getNode())
4512 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
4513 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
4514 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
4515 if (N0.getOpcode() == ISD::SRL) {
4516 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
4517 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
4518 // We can turn this into an SRA iff the input to the SRL is already sign
4520 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
4521 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
4522 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
4523 N0.getOperand(0), N0.getOperand(1));
4527 // fold (sext_inreg (extload x)) -> (sextload x)
4528 if (ISD::isEXTLoad(N0.getNode()) &&
4529 ISD::isUNINDEXEDLoad(N0.getNode()) &&
4530 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4531 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4532 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4533 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4534 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4536 LN0->getBasePtr(), LN0->getPointerInfo(),
4538 LN0->isVolatile(), LN0->isNonTemporal(),
4539 LN0->getAlignment());
4540 CombineTo(N, ExtLoad);
4541 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4542 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4544 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
4545 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4547 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4548 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4549 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4550 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4551 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4553 LN0->getBasePtr(), LN0->getPointerInfo(),
4555 LN0->isVolatile(), LN0->isNonTemporal(),
4556 LN0->getAlignment());
4557 CombineTo(N, ExtLoad);
4558 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4559 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4564 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
4565 SDValue N0 = N->getOperand(0);
4566 EVT VT = N->getValueType(0);
4569 if (N0.getValueType() == N->getValueType(0))
4571 // fold (truncate c1) -> c1
4572 if (isa<ConstantSDNode>(N0))
4573 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
4574 // fold (truncate (truncate x)) -> (truncate x)
4575 if (N0.getOpcode() == ISD::TRUNCATE)
4576 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4577 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
4578 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
4579 N0.getOpcode() == ISD::SIGN_EXTEND ||
4580 N0.getOpcode() == ISD::ANY_EXTEND) {
4581 if (N0.getOperand(0).getValueType().bitsLT(VT))
4582 // if the source is smaller than the dest, we still need an extend
4583 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4585 else if (N0.getOperand(0).getValueType().bitsGT(VT))
4586 // if the source is larger than the dest, than we just need the truncate
4587 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4589 // if the source and dest are the same type, we can drop both the extend
4590 // and the truncate.
4591 return N0.getOperand(0);
4594 // See if we can simplify the input to this truncate through knowledge that
4595 // only the low bits are being used.
4596 // For example "trunc (or (shl x, 8), y)" // -> trunc y
4597 // Currently we only perform this optimization on scalars because vectors
4598 // may have different active low bits.
4599 if (!VT.isVector()) {
4601 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
4602 VT.getSizeInBits()));
4603 if (Shorter.getNode())
4604 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
4606 // fold (truncate (load x)) -> (smaller load x)
4607 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
4608 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
4609 SDValue Reduced = ReduceLoadWidth(N);
4610 if (Reduced.getNode())
4614 // Simplify the operands using demanded-bits information.
4615 if (!VT.isVector() &&
4616 SimplifyDemandedBits(SDValue(N, 0)))
4617 return SDValue(N, 0);
4622 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
4623 SDValue Elt = N->getOperand(i);
4624 if (Elt.getOpcode() != ISD::MERGE_VALUES)
4625 return Elt.getNode();
4626 return Elt.getOperand(Elt.getResNo()).getNode();
4629 /// CombineConsecutiveLoads - build_pair (load, load) -> load
4630 /// if load locations are consecutive.
4631 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
4632 assert(N->getOpcode() == ISD::BUILD_PAIR);
4634 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
4635 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
4636 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
4637 LD1->getPointerInfo().getAddrSpace() !=
4638 LD2->getPointerInfo().getAddrSpace())
4640 EVT LD1VT = LD1->getValueType(0);
4642 if (ISD::isNON_EXTLoad(LD2) &&
4644 // If both are volatile this would reduce the number of volatile loads.
4645 // If one is volatile it might be ok, but play conservative and bail out.
4646 !LD1->isVolatile() &&
4647 !LD2->isVolatile() &&
4648 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
4649 unsigned Align = LD1->getAlignment();
4650 unsigned NewAlign = TLI.getTargetData()->
4651 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4653 if (NewAlign <= Align &&
4654 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
4655 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
4656 LD1->getBasePtr(), LD1->getPointerInfo(),
4657 false, false, Align);
4663 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
4664 SDValue N0 = N->getOperand(0);
4665 EVT VT = N->getValueType(0);
4667 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
4668 // Only do this before legalize, since afterward the target may be depending
4669 // on the bitconvert.
4670 // First check to see if this is all constant.
4672 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
4674 bool isSimple = true;
4675 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
4676 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
4677 N0.getOperand(i).getOpcode() != ISD::Constant &&
4678 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
4683 EVT DestEltVT = N->getValueType(0).getVectorElementType();
4684 assert(!DestEltVT.isVector() &&
4685 "Element type of vector ValueType must not be vector!");
4687 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
4690 // If the input is a constant, let getNode fold it.
4691 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
4692 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
4693 if (Res.getNode() != N) {
4694 if (!LegalOperations ||
4695 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
4698 // Folding it resulted in an illegal node, and it's too late to
4699 // do that. Clean up the old node and forego the transformation.
4700 // Ideally this won't happen very often, because instcombine
4701 // and the earlier dagcombine runs (where illegal nodes are
4702 // permitted) should have folded most of them already.
4703 DAG.DeleteNode(Res.getNode());
4707 // (conv (conv x, t1), t2) -> (conv x, t2)
4708 if (N0.getOpcode() == ISD::BITCAST)
4709 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
4712 // fold (conv (load x)) -> (load (conv*)x)
4713 // If the resultant load doesn't need a higher alignment than the original!
4714 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
4715 // Do not change the width of a volatile load.
4716 !cast<LoadSDNode>(N0)->isVolatile() &&
4717 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
4718 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4719 unsigned Align = TLI.getTargetData()->
4720 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4721 unsigned OrigAlign = LN0->getAlignment();
4723 if (Align <= OrigAlign) {
4724 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
4725 LN0->getBasePtr(), LN0->getPointerInfo(),
4726 LN0->isVolatile(), LN0->isNonTemporal(),
4729 CombineTo(N0.getNode(),
4730 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
4731 N0.getValueType(), Load),
4737 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
4738 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
4739 // This often reduces constant pool loads.
4740 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
4741 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
4742 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
4744 AddToWorkList(NewConv.getNode());
4746 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4747 if (N0.getOpcode() == ISD::FNEG)
4748 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
4749 NewConv, DAG.getConstant(SignBit, VT));
4750 assert(N0.getOpcode() == ISD::FABS);
4751 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4752 NewConv, DAG.getConstant(~SignBit, VT));
4755 // fold (bitconvert (fcopysign cst, x)) ->
4756 // (or (and (bitconvert x), sign), (and cst, (not sign)))
4757 // Note that we don't handle (copysign x, cst) because this can always be
4758 // folded to an fneg or fabs.
4759 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
4760 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
4761 VT.isInteger() && !VT.isVector()) {
4762 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
4763 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
4764 if (isTypeLegal(IntXVT)) {
4765 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
4766 IntXVT, N0.getOperand(1));
4767 AddToWorkList(X.getNode());
4769 // If X has a different width than the result/lhs, sext it or truncate it.
4770 unsigned VTWidth = VT.getSizeInBits();
4771 if (OrigXWidth < VTWidth) {
4772 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
4773 AddToWorkList(X.getNode());
4774 } else if (OrigXWidth > VTWidth) {
4775 // To get the sign bit in the right place, we have to shift it right
4776 // before truncating.
4777 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
4778 X.getValueType(), X,
4779 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
4780 AddToWorkList(X.getNode());
4781 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4782 AddToWorkList(X.getNode());
4785 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4786 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
4787 X, DAG.getConstant(SignBit, VT));
4788 AddToWorkList(X.getNode());
4790 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
4791 VT, N0.getOperand(0));
4792 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
4793 Cst, DAG.getConstant(~SignBit, VT));
4794 AddToWorkList(Cst.getNode());
4796 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
4800 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
4801 if (N0.getOpcode() == ISD::BUILD_PAIR) {
4802 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
4803 if (CombineLD.getNode())
4810 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
4811 EVT VT = N->getValueType(0);
4812 return CombineConsecutiveLoads(N, VT);
4815 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
4816 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
4817 /// destination element value type.
4818 SDValue DAGCombiner::
4819 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
4820 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
4822 // If this is already the right type, we're done.
4823 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
4825 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
4826 unsigned DstBitSize = DstEltVT.getSizeInBits();
4828 // If this is a conversion of N elements of one type to N elements of another
4829 // type, convert each element. This handles FP<->INT cases.
4830 if (SrcBitSize == DstBitSize) {
4831 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4832 BV->getValueType(0).getVectorNumElements());
4834 // Due to the FP element handling below calling this routine recursively,
4835 // we can end up with a scalar-to-vector node here.
4836 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
4837 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4838 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
4839 DstEltVT, BV->getOperand(0)));
4841 SmallVector<SDValue, 8> Ops;
4842 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4843 SDValue Op = BV->getOperand(i);
4844 // If the vector element type is not legal, the BUILD_VECTOR operands
4845 // are promoted and implicitly truncated. Make that explicit here.
4846 if (Op.getValueType() != SrcEltVT)
4847 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
4848 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
4850 AddToWorkList(Ops.back().getNode());
4852 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4853 &Ops[0], Ops.size());
4856 // Otherwise, we're growing or shrinking the elements. To avoid having to
4857 // handle annoying details of growing/shrinking FP values, we convert them to
4859 if (SrcEltVT.isFloatingPoint()) {
4860 // Convert the input float vector to a int vector where the elements are the
4862 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
4863 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
4864 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
4868 // Now we know the input is an integer vector. If the output is a FP type,
4869 // convert to integer first, then to FP of the right size.
4870 if (DstEltVT.isFloatingPoint()) {
4871 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
4872 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
4873 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
4875 // Next, convert to FP elements of the same size.
4876 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
4879 // Okay, we know the src/dst types are both integers of differing types.
4880 // Handling growing first.
4881 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
4882 if (SrcBitSize < DstBitSize) {
4883 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
4885 SmallVector<SDValue, 8> Ops;
4886 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
4887 i += NumInputsPerOutput) {
4888 bool isLE = TLI.isLittleEndian();
4889 APInt NewBits = APInt(DstBitSize, 0);
4890 bool EltIsUndef = true;
4891 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
4892 // Shift the previously computed bits over.
4893 NewBits <<= SrcBitSize;
4894 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
4895 if (Op.getOpcode() == ISD::UNDEF) continue;
4898 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
4899 zextOrTrunc(SrcBitSize).zext(DstBitSize);
4903 Ops.push_back(DAG.getUNDEF(DstEltVT));
4905 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
4908 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
4909 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4910 &Ops[0], Ops.size());
4913 // Finally, this must be the case where we are shrinking elements: each input
4914 // turns into multiple outputs.
4915 bool isS2V = ISD::isScalarToVector(BV);
4916 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
4917 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4918 NumOutputsPerInput*BV->getNumOperands());
4919 SmallVector<SDValue, 8> Ops;
4921 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4922 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
4923 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
4924 Ops.push_back(DAG.getUNDEF(DstEltVT));
4928 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
4929 getAPIntValue().zextOrTrunc(SrcBitSize);
4931 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
4932 APInt ThisVal = OpVal.trunc(DstBitSize);
4933 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
4934 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
4935 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
4936 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4938 OpVal = OpVal.lshr(DstBitSize);
4941 // For big endian targets, swap the order of the pieces of each element.
4942 if (TLI.isBigEndian())
4943 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
4946 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4947 &Ops[0], Ops.size());
4950 SDValue DAGCombiner::visitFADD(SDNode *N) {
4951 SDValue N0 = N->getOperand(0);
4952 SDValue N1 = N->getOperand(1);
4953 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4954 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4955 EVT VT = N->getValueType(0);
4958 if (VT.isVector()) {
4959 SDValue FoldedVOp = SimplifyVBinOp(N);
4960 if (FoldedVOp.getNode()) return FoldedVOp;
4963 // fold (fadd c1, c2) -> (fadd c1, c2)
4964 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4965 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
4966 // canonicalize constant to RHS
4967 if (N0CFP && !N1CFP)
4968 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
4969 // fold (fadd A, 0) -> A
4970 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4972 // fold (fadd A, (fneg B)) -> (fsub A, B)
4973 if (isNegatibleForFree(N1, LegalOperations) == 2)
4974 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
4975 GetNegatedExpression(N1, DAG, LegalOperations));
4976 // fold (fadd (fneg A), B) -> (fsub B, A)
4977 if (isNegatibleForFree(N0, LegalOperations) == 2)
4978 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
4979 GetNegatedExpression(N0, DAG, LegalOperations));
4981 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
4982 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
4983 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4984 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
4985 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
4986 N0.getOperand(1), N1));
4991 SDValue DAGCombiner::visitFSUB(SDNode *N) {
4992 SDValue N0 = N->getOperand(0);
4993 SDValue N1 = N->getOperand(1);
4994 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4995 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4996 EVT VT = N->getValueType(0);
4999 if (VT.isVector()) {
5000 SDValue FoldedVOp = SimplifyVBinOp(N);
5001 if (FoldedVOp.getNode()) return FoldedVOp;
5004 // fold (fsub c1, c2) -> c1-c2
5005 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5006 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5007 // fold (fsub A, 0) -> A
5008 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5010 // fold (fsub 0, B) -> -B
5011 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
5012 if (isNegatibleForFree(N1, LegalOperations))
5013 return GetNegatedExpression(N1, DAG, LegalOperations);
5014 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5015 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
5017 // fold (fsub A, (fneg B)) -> (fadd A, B)
5018 if (isNegatibleForFree(N1, LegalOperations))
5019 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
5020 GetNegatedExpression(N1, DAG, LegalOperations));
5025 SDValue DAGCombiner::visitFMUL(SDNode *N) {
5026 SDValue N0 = N->getOperand(0);
5027 SDValue N1 = N->getOperand(1);
5028 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5029 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5030 EVT VT = N->getValueType(0);
5033 if (VT.isVector()) {
5034 SDValue FoldedVOp = SimplifyVBinOp(N);
5035 if (FoldedVOp.getNode()) return FoldedVOp;
5038 // fold (fmul c1, c2) -> c1*c2
5039 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5040 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5041 // canonicalize constant to RHS
5042 if (N0CFP && !N1CFP)
5043 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5044 // fold (fmul A, 0) -> 0
5045 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5047 // fold (fmul A, 0) -> 0, vector edition.
5048 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
5050 // fold (fmul X, 2.0) -> (fadd X, X)
5051 if (N1CFP && N1CFP->isExactlyValue(+2.0))
5052 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5053 // fold (fmul X, -1.0) -> (fneg X)
5054 if (N1CFP && N1CFP->isExactlyValue(-1.0))
5055 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5056 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5058 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5059 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5060 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5061 // Both can be negated for free, check to see if at least one is cheaper
5063 if (LHSNeg == 2 || RHSNeg == 2)
5064 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5065 GetNegatedExpression(N0, DAG, LegalOperations),
5066 GetNegatedExpression(N1, DAG, LegalOperations));
5070 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5071 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
5072 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5073 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5074 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5075 N0.getOperand(1), N1));
5080 SDValue DAGCombiner::visitFDIV(SDNode *N) {
5081 SDValue N0 = N->getOperand(0);
5082 SDValue N1 = N->getOperand(1);
5083 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5084 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5085 EVT VT = N->getValueType(0);
5088 if (VT.isVector()) {
5089 SDValue FoldedVOp = SimplifyVBinOp(N);
5090 if (FoldedVOp.getNode()) return FoldedVOp;
5093 // fold (fdiv c1, c2) -> c1/c2
5094 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5095 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
5098 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
5099 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5100 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5101 // Both can be negated for free, check to see if at least one is cheaper
5103 if (LHSNeg == 2 || RHSNeg == 2)
5104 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
5105 GetNegatedExpression(N0, DAG, LegalOperations),
5106 GetNegatedExpression(N1, DAG, LegalOperations));
5113 SDValue DAGCombiner::visitFREM(SDNode *N) {
5114 SDValue N0 = N->getOperand(0);
5115 SDValue N1 = N->getOperand(1);
5116 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5117 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5118 EVT VT = N->getValueType(0);
5120 // fold (frem c1, c2) -> fmod(c1,c2)
5121 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5122 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
5127 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
5128 SDValue N0 = N->getOperand(0);
5129 SDValue N1 = N->getOperand(1);
5130 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5131 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5132 EVT VT = N->getValueType(0);
5134 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
5135 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
5138 const APFloat& V = N1CFP->getValueAPF();
5139 // copysign(x, c1) -> fabs(x) iff ispos(c1)
5140 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
5141 if (!V.isNegative()) {
5142 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
5143 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5145 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5146 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
5147 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
5151 // copysign(fabs(x), y) -> copysign(x, y)
5152 // copysign(fneg(x), y) -> copysign(x, y)
5153 // copysign(copysign(x,z), y) -> copysign(x, y)
5154 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
5155 N0.getOpcode() == ISD::FCOPYSIGN)
5156 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5157 N0.getOperand(0), N1);
5159 // copysign(x, abs(y)) -> abs(x)
5160 if (N1.getOpcode() == ISD::FABS)
5161 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5163 // copysign(x, copysign(y,z)) -> copysign(x, z)
5164 if (N1.getOpcode() == ISD::FCOPYSIGN)
5165 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5166 N0, N1.getOperand(1));
5168 // copysign(x, fp_extend(y)) -> copysign(x, y)
5169 // copysign(x, fp_round(y)) -> copysign(x, y)
5170 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
5171 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5172 N0, N1.getOperand(0));
5177 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
5178 SDValue N0 = N->getOperand(0);
5179 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5180 EVT VT = N->getValueType(0);
5181 EVT OpVT = N0.getValueType();
5183 // fold (sint_to_fp c1) -> c1fp
5184 if (N0C && OpVT != MVT::ppcf128 &&
5185 // ...but only if the target supports immediate floating-point values
5186 (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5187 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5189 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
5190 // but UINT_TO_FP is legal on this target, try to convert.
5191 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
5192 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
5193 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
5194 if (DAG.SignBitIsZero(N0))
5195 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5201 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
5202 SDValue N0 = N->getOperand(0);
5203 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5204 EVT VT = N->getValueType(0);
5205 EVT OpVT = N0.getValueType();
5207 // fold (uint_to_fp c1) -> c1fp
5208 if (N0C && OpVT != MVT::ppcf128 &&
5209 // ...but only if the target supports immediate floating-point values
5210 (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5211 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5213 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
5214 // but SINT_TO_FP is legal on this target, try to convert.
5215 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
5216 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
5217 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
5218 if (DAG.SignBitIsZero(N0))
5219 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5225 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
5226 SDValue N0 = N->getOperand(0);
5227 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5228 EVT VT = N->getValueType(0);
5230 // fold (fp_to_sint c1fp) -> c1
5232 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
5237 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
5238 SDValue N0 = N->getOperand(0);
5239 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5240 EVT VT = N->getValueType(0);
5242 // fold (fp_to_uint c1fp) -> c1
5243 if (N0CFP && VT != MVT::ppcf128)
5244 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
5249 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
5250 SDValue N0 = N->getOperand(0);
5251 SDValue N1 = N->getOperand(1);
5252 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5253 EVT VT = N->getValueType(0);
5255 // fold (fp_round c1fp) -> c1fp
5256 if (N0CFP && N0.getValueType() != MVT::ppcf128)
5257 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
5259 // fold (fp_round (fp_extend x)) -> x
5260 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
5261 return N0.getOperand(0);
5263 // fold (fp_round (fp_round x)) -> (fp_round x)
5264 if (N0.getOpcode() == ISD::FP_ROUND) {
5265 // This is a value preserving truncation if both round's are.
5266 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
5267 N0.getNode()->getConstantOperandVal(1) == 1;
5268 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
5269 DAG.getIntPtrConstant(IsTrunc));
5272 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
5273 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
5274 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
5275 N0.getOperand(0), N1);
5276 AddToWorkList(Tmp.getNode());
5277 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5278 Tmp, N0.getOperand(1));
5284 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
5285 SDValue N0 = N->getOperand(0);
5286 EVT VT = N->getValueType(0);
5287 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5288 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5290 // fold (fp_round_inreg c1fp) -> c1fp
5291 if (N0CFP && isTypeLegal(EVT)) {
5292 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
5293 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
5299 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
5300 SDValue N0 = N->getOperand(0);
5301 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5302 EVT VT = N->getValueType(0);
5304 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
5305 if (N->hasOneUse() &&
5306 N->use_begin()->getOpcode() == ISD::FP_ROUND)
5309 // fold (fp_extend c1fp) -> c1fp
5310 if (N0CFP && VT != MVT::ppcf128)
5311 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
5313 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
5315 if (N0.getOpcode() == ISD::FP_ROUND
5316 && N0.getNode()->getConstantOperandVal(1) == 1) {
5317 SDValue In = N0.getOperand(0);
5318 if (In.getValueType() == VT) return In;
5319 if (VT.bitsLT(In.getValueType()))
5320 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
5321 In, N0.getOperand(1));
5322 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
5325 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
5326 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
5327 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5328 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5329 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5330 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
5332 LN0->getBasePtr(), LN0->getPointerInfo(),
5334 LN0->isVolatile(), LN0->isNonTemporal(),
5335 LN0->getAlignment());
5336 CombineTo(N, ExtLoad);
5337 CombineTo(N0.getNode(),
5338 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
5339 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
5340 ExtLoad.getValue(1));
5341 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5347 SDValue DAGCombiner::visitFNEG(SDNode *N) {
5348 SDValue N0 = N->getOperand(0);
5349 EVT VT = N->getValueType(0);
5351 if (isNegatibleForFree(N0, LegalOperations))
5352 return GetNegatedExpression(N0, DAG, LegalOperations);
5354 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
5355 // constant pool values.
5356 if (N0.getOpcode() == ISD::BITCAST &&
5358 N0.getNode()->hasOneUse() &&
5359 N0.getOperand(0).getValueType().isInteger()) {
5360 SDValue Int = N0.getOperand(0);
5361 EVT IntVT = Int.getValueType();
5362 if (IntVT.isInteger() && !IntVT.isVector()) {
5363 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5364 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5365 AddToWorkList(Int.getNode());
5366 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5374 SDValue DAGCombiner::visitFABS(SDNode *N) {
5375 SDValue N0 = N->getOperand(0);
5376 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5377 EVT VT = N->getValueType(0);
5379 // fold (fabs c1) -> fabs(c1)
5380 if (N0CFP && VT != MVT::ppcf128)
5381 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5382 // fold (fabs (fabs x)) -> (fabs x)
5383 if (N0.getOpcode() == ISD::FABS)
5384 return N->getOperand(0);
5385 // fold (fabs (fneg x)) -> (fabs x)
5386 // fold (fabs (fcopysign x, y)) -> (fabs x)
5387 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5388 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5390 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5391 // constant pool values.
5392 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
5393 N0.getOperand(0).getValueType().isInteger() &&
5394 !N0.getOperand(0).getValueType().isVector()) {
5395 SDValue Int = N0.getOperand(0);
5396 EVT IntVT = Int.getValueType();
5397 if (IntVT.isInteger() && !IntVT.isVector()) {
5398 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5399 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5400 AddToWorkList(Int.getNode());
5401 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5402 N->getValueType(0), Int);
5409 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
5410 SDValue Chain = N->getOperand(0);
5411 SDValue N1 = N->getOperand(1);
5412 SDValue N2 = N->getOperand(2);
5414 // If N is a constant we could fold this into a fallthrough or unconditional
5415 // branch. However that doesn't happen very often in normal code, because
5416 // Instcombine/SimplifyCFG should have handled the available opportunities.
5417 // If we did this folding here, it would be necessary to update the
5418 // MachineBasicBlock CFG, which is awkward.
5420 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5422 if (N1.getOpcode() == ISD::SETCC &&
5423 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5424 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5425 Chain, N1.getOperand(2),
5426 N1.getOperand(0), N1.getOperand(1), N2);
5429 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
5430 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
5431 (N1.getOperand(0).hasOneUse() &&
5432 N1.getOperand(0).getOpcode() == ISD::SRL))) {
5434 if (N1.getOpcode() == ISD::TRUNCATE) {
5435 // Look pass the truncate.
5436 Trunc = N1.getNode();
5437 N1 = N1.getOperand(0);
5440 // Match this pattern so that we can generate simpler code:
5443 // %b = and i32 %a, 2
5444 // %c = srl i32 %b, 1
5445 // brcond i32 %c ...
5450 // %b = and i32 %a, 2
5451 // %c = setcc eq %b, 0
5454 // This applies only when the AND constant value has one bit set and the
5455 // SRL constant is equal to the log2 of the AND constant. The back-end is
5456 // smart enough to convert the result into a TEST/JMP sequence.
5457 SDValue Op0 = N1.getOperand(0);
5458 SDValue Op1 = N1.getOperand(1);
5460 if (Op0.getOpcode() == ISD::AND &&
5461 Op1.getOpcode() == ISD::Constant) {
5462 SDValue AndOp1 = Op0.getOperand(1);
5464 if (AndOp1.getOpcode() == ISD::Constant) {
5465 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
5467 if (AndConst.isPowerOf2() &&
5468 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
5470 DAG.getSetCC(N->getDebugLoc(),
5471 TLI.getSetCCResultType(Op0.getValueType()),
5472 Op0, DAG.getConstant(0, Op0.getValueType()),
5475 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5476 MVT::Other, Chain, SetCC, N2);
5477 // Don't add the new BRCond into the worklist or else SimplifySelectCC
5478 // will convert it back to (X & C1) >> C2.
5479 CombineTo(N, NewBRCond, false);
5480 // Truncate is dead.
5482 removeFromWorkList(Trunc);
5483 DAG.DeleteNode(Trunc);
5485 // Replace the uses of SRL with SETCC
5486 WorkListRemover DeadNodes(*this);
5487 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5488 removeFromWorkList(N1.getNode());
5489 DAG.DeleteNode(N1.getNode());
5490 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5496 // Restore N1 if the above transformation doesn't match.
5497 N1 = N->getOperand(1);
5500 // Transform br(xor(x, y)) -> br(x != y)
5501 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
5502 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
5503 SDNode *TheXor = N1.getNode();
5504 SDValue Op0 = TheXor->getOperand(0);
5505 SDValue Op1 = TheXor->getOperand(1);
5506 if (Op0.getOpcode() == Op1.getOpcode()) {
5507 // Avoid missing important xor optimizations.
5508 SDValue Tmp = visitXOR(TheXor);
5509 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
5510 DEBUG(dbgs() << "\nReplacing.8 ";
5512 dbgs() << "\nWith: ";
5513 Tmp.getNode()->dump(&DAG);
5515 WorkListRemover DeadNodes(*this);
5516 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
5517 removeFromWorkList(TheXor);
5518 DAG.DeleteNode(TheXor);
5519 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5520 MVT::Other, Chain, Tmp, N2);
5524 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
5526 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
5527 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
5528 Op0.getOpcode() == ISD::XOR) {
5529 TheXor = Op0.getNode();
5533 EVT SetCCVT = N1.getValueType();
5535 SetCCVT = TLI.getSetCCResultType(SetCCVT);
5536 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
5539 Equal ? ISD::SETEQ : ISD::SETNE);
5540 // Replace the uses of XOR with SETCC
5541 WorkListRemover DeadNodes(*this);
5542 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5543 removeFromWorkList(N1.getNode());
5544 DAG.DeleteNode(N1.getNode());
5545 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5546 MVT::Other, Chain, SetCC, N2);
5553 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
5555 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
5556 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
5557 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
5559 // If N is a constant we could fold this into a fallthrough or unconditional
5560 // branch. However that doesn't happen very often in normal code, because
5561 // Instcombine/SimplifyCFG should have handled the available opportunities.
5562 // If we did this folding here, it would be necessary to update the
5563 // MachineBasicBlock CFG, which is awkward.
5565 // Use SimplifySetCC to simplify SETCC's.
5566 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
5567 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
5569 if (Simp.getNode()) AddToWorkList(Simp.getNode());
5571 // fold to a simpler setcc
5572 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
5573 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5574 N->getOperand(0), Simp.getOperand(2),
5575 Simp.getOperand(0), Simp.getOperand(1),
5581 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
5582 /// pre-indexed load / store when the base pointer is an add or subtract
5583 /// and it has other uses besides the load / store. After the
5584 /// transformation, the new indexed load / store has effectively folded
5585 /// the add / subtract in and all of its other uses are redirected to the
5586 /// new load / store.
5587 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
5588 if (!LegalOperations)
5594 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5595 if (LD->isIndexed())
5597 VT = LD->getMemoryVT();
5598 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
5599 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
5601 Ptr = LD->getBasePtr();
5602 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5603 if (ST->isIndexed())
5605 VT = ST->getMemoryVT();
5606 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
5607 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
5609 Ptr = ST->getBasePtr();
5615 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
5616 // out. There is no reason to make this a preinc/predec.
5617 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
5618 Ptr.getNode()->hasOneUse())
5621 // Ask the target to do addressing mode selection.
5624 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5625 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
5627 // Don't create a indexed load / store with zero offset.
5628 if (isa<ConstantSDNode>(Offset) &&
5629 cast<ConstantSDNode>(Offset)->isNullValue())
5632 // Try turning it into a pre-indexed load / store except when:
5633 // 1) The new base ptr is a frame index.
5634 // 2) If N is a store and the new base ptr is either the same as or is a
5635 // predecessor of the value being stored.
5636 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
5637 // that would create a cycle.
5638 // 4) All uses are load / store ops that use it as old base ptr.
5640 // Check #1. Preinc'ing a frame index would require copying the stack pointer
5641 // (plus the implicit offset) to a register to preinc anyway.
5642 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5647 SDValue Val = cast<StoreSDNode>(N)->getValue();
5648 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
5652 // Now check for #3 and #4.
5653 bool RealUse = false;
5654 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5655 E = Ptr.getNode()->use_end(); I != E; ++I) {
5659 if (Use->isPredecessorOf(N))
5662 if (!((Use->getOpcode() == ISD::LOAD &&
5663 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
5664 (Use->getOpcode() == ISD::STORE &&
5665 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
5674 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5675 BasePtr, Offset, AM);
5677 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5678 BasePtr, Offset, AM);
5681 DEBUG(dbgs() << "\nReplacing.4 ";
5683 dbgs() << "\nWith: ";
5684 Result.getNode()->dump(&DAG);
5686 WorkListRemover DeadNodes(*this);
5688 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5690 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5693 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5697 // Finally, since the node is now dead, remove it from the graph.
5700 // Replace the uses of Ptr with uses of the updated base value.
5701 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
5703 removeFromWorkList(Ptr.getNode());
5704 DAG.DeleteNode(Ptr.getNode());
5709 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
5710 /// add / sub of the base pointer node into a post-indexed load / store.
5711 /// The transformation folded the add / subtract into the new indexed
5712 /// load / store effectively and all of its uses are redirected to the
5713 /// new load / store.
5714 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
5715 if (!LegalOperations)
5721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5722 if (LD->isIndexed())
5724 VT = LD->getMemoryVT();
5725 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
5726 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
5728 Ptr = LD->getBasePtr();
5729 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5730 if (ST->isIndexed())
5732 VT = ST->getMemoryVT();
5733 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
5734 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
5736 Ptr = ST->getBasePtr();
5742 if (Ptr.getNode()->hasOneUse())
5745 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5746 E = Ptr.getNode()->use_end(); I != E; ++I) {
5749 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
5754 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5755 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
5756 // Don't create a indexed load / store with zero offset.
5757 if (isa<ConstantSDNode>(Offset) &&
5758 cast<ConstantSDNode>(Offset)->isNullValue())
5761 // Try turning it into a post-indexed load / store except when
5762 // 1) All uses are load / store ops that use it as base ptr.
5763 // 2) Op must be independent of N, i.e. Op is neither a predecessor
5764 // nor a successor of N. Otherwise, if Op is folded that would
5767 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5771 bool TryNext = false;
5772 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
5773 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
5775 if (Use == Ptr.getNode())
5778 // If all the uses are load / store addresses, then don't do the
5780 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
5781 bool RealUse = false;
5782 for (SDNode::use_iterator III = Use->use_begin(),
5783 EEE = Use->use_end(); III != EEE; ++III) {
5784 SDNode *UseUse = *III;
5785 if (!((UseUse->getOpcode() == ISD::LOAD &&
5786 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
5787 (UseUse->getOpcode() == ISD::STORE &&
5788 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
5803 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
5804 SDValue Result = isLoad
5805 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5806 BasePtr, Offset, AM)
5807 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5808 BasePtr, Offset, AM);
5811 DEBUG(dbgs() << "\nReplacing.5 ";
5813 dbgs() << "\nWith: ";
5814 Result.getNode()->dump(&DAG);
5816 WorkListRemover DeadNodes(*this);
5818 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5820 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5823 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5827 // Finally, since the node is now dead, remove it from the graph.
5830 // Replace the uses of Use with uses of the updated base value.
5831 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
5832 Result.getValue(isLoad ? 1 : 0),
5834 removeFromWorkList(Op);
5844 SDValue DAGCombiner::visitLOAD(SDNode *N) {
5845 LoadSDNode *LD = cast<LoadSDNode>(N);
5846 SDValue Chain = LD->getChain();
5847 SDValue Ptr = LD->getBasePtr();
5849 // If load is not volatile and there are no uses of the loaded value (and
5850 // the updated indexed value in case of indexed loads), change uses of the
5851 // chain value into uses of the chain input (i.e. delete the dead load).
5852 if (!LD->isVolatile()) {
5853 if (N->getValueType(1) == MVT::Other) {
5855 if (N->hasNUsesOfValue(0, 0)) {
5856 // It's not safe to use the two value CombineTo variant here. e.g.
5857 // v1, chain2 = load chain1, loc
5858 // v2, chain3 = load chain2, loc
5860 // Now we replace use of chain2 with chain1. This makes the second load
5861 // isomorphic to the one we are deleting, and thus makes this load live.
5862 DEBUG(dbgs() << "\nReplacing.6 ";
5864 dbgs() << "\nWith chain: ";
5865 Chain.getNode()->dump(&DAG);
5867 WorkListRemover DeadNodes(*this);
5868 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
5870 if (N->use_empty()) {
5871 removeFromWorkList(N);
5875 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5879 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
5880 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
5881 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
5882 DEBUG(dbgs() << "\nReplacing.7 ";
5884 dbgs() << "\nWith: ";
5885 Undef.getNode()->dump(&DAG);
5886 dbgs() << " and 2 other values\n");
5887 WorkListRemover DeadNodes(*this);
5888 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
5889 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
5890 DAG.getUNDEF(N->getValueType(1)),
5892 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
5893 removeFromWorkList(N);
5895 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5900 // If this load is directly stored, replace the load value with the stored
5902 // TODO: Handle store large -> read small portion.
5903 // TODO: Handle TRUNCSTORE/LOADEXT
5904 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
5905 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
5906 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
5907 if (PrevST->getBasePtr() == Ptr &&
5908 PrevST->getValue().getValueType() == N->getValueType(0))
5909 return CombineTo(N, Chain.getOperand(1), Chain);
5913 // Try to infer better alignment information than the load already has.
5914 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
5915 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5916 if (Align > LD->getAlignment())
5917 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
5918 LD->getValueType(0),
5919 Chain, Ptr, LD->getPointerInfo(),
5921 LD->isVolatile(), LD->isNonTemporal(), Align);
5926 // Walk up chain skipping non-aliasing memory nodes.
5927 SDValue BetterChain = FindBetterChain(N, Chain);
5929 // If there is a better chain.
5930 if (Chain != BetterChain) {
5933 // Replace the chain to void dependency.
5934 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
5935 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
5936 BetterChain, Ptr, LD->getPointerInfo(),
5937 LD->isVolatile(), LD->isNonTemporal(),
5938 LD->getAlignment());
5940 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
5941 LD->getValueType(0),
5942 BetterChain, Ptr, LD->getPointerInfo(),
5945 LD->isNonTemporal(),
5946 LD->getAlignment());
5949 // Create token factor to keep old chain connected.
5950 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5951 MVT::Other, Chain, ReplLoad.getValue(1));
5953 // Make sure the new and old chains are cleaned up.
5954 AddToWorkList(Token.getNode());
5956 // Replace uses with load result and token factor. Don't add users
5958 return CombineTo(N, ReplLoad.getValue(0), Token, false);
5962 // Try transforming N to an indexed load.
5963 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5964 return SDValue(N, 0);
5969 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
5970 /// load is having specific bytes cleared out. If so, return the byte size
5971 /// being masked out and the shift amount.
5972 static std::pair<unsigned, unsigned>
5973 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
5974 std::pair<unsigned, unsigned> Result(0, 0);
5976 // Check for the structure we're looking for.
5977 if (V->getOpcode() != ISD::AND ||
5978 !isa<ConstantSDNode>(V->getOperand(1)) ||
5979 !ISD::isNormalLoad(V->getOperand(0).getNode()))
5982 // Check the chain and pointer.
5983 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
5984 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
5986 // The store should be chained directly to the load or be an operand of a
5988 if (LD == Chain.getNode())
5990 else if (Chain->getOpcode() != ISD::TokenFactor)
5991 return Result; // Fail.
5994 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
5995 if (Chain->getOperand(i).getNode() == LD) {
5999 if (!isOk) return Result;
6002 // This only handles simple types.
6003 if (V.getValueType() != MVT::i16 &&
6004 V.getValueType() != MVT::i32 &&
6005 V.getValueType() != MVT::i64)
6008 // Check the constant mask. Invert it so that the bits being masked out are
6009 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
6010 // follow the sign bit for uniformity.
6011 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
6012 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
6013 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
6014 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
6015 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
6016 if (NotMaskLZ == 64) return Result; // All zero mask.
6018 // See if we have a continuous run of bits. If so, we have 0*1+0*
6019 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
6022 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
6023 if (V.getValueType() != MVT::i64 && NotMaskLZ)
6024 NotMaskLZ -= 64-V.getValueSizeInBits();
6026 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
6027 switch (MaskedBytes) {
6031 default: return Result; // All one mask, or 5-byte mask.
6034 // Verify that the first bit starts at a multiple of mask so that the access
6035 // is aligned the same as the access width.
6036 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
6038 Result.first = MaskedBytes;
6039 Result.second = NotMaskTZ/8;
6044 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
6045 /// provides a value as specified by MaskInfo. If so, replace the specified
6046 /// store with a narrower store of truncated IVal.
6048 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
6049 SDValue IVal, StoreSDNode *St,
6051 unsigned NumBytes = MaskInfo.first;
6052 unsigned ByteShift = MaskInfo.second;
6053 SelectionDAG &DAG = DC->getDAG();
6055 // Check to see if IVal is all zeros in the part being masked in by the 'or'
6056 // that uses this. If not, this is not a replacement.
6057 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
6058 ByteShift*8, (ByteShift+NumBytes)*8);
6059 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
6061 // Check that it is legal on the target to do this. It is legal if the new
6062 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
6064 MVT VT = MVT::getIntegerVT(NumBytes*8);
6065 if (!DC->isTypeLegal(VT))
6068 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
6069 // shifted by ByteShift and truncated down to NumBytes.
6071 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
6072 DAG.getConstant(ByteShift*8,
6073 DC->getShiftAmountTy(IVal.getValueType())));
6075 // Figure out the offset for the store and the alignment of the access.
6077 unsigned NewAlign = St->getAlignment();
6079 if (DAG.getTargetLoweringInfo().isLittleEndian())
6080 StOffset = ByteShift;
6082 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
6084 SDValue Ptr = St->getBasePtr();
6086 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
6087 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
6088 NewAlign = MinAlign(NewAlign, StOffset);
6091 // Truncate down to the new size.
6092 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
6095 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
6096 St->getPointerInfo().getWithOffset(StOffset),
6097 false, false, NewAlign).getNode();
6101 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
6102 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
6103 /// of the loaded bits, try narrowing the load and store if it would end up
6104 /// being a win for performance or code size.
6105 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
6106 StoreSDNode *ST = cast<StoreSDNode>(N);
6107 if (ST->isVolatile())
6110 SDValue Chain = ST->getChain();
6111 SDValue Value = ST->getValue();
6112 SDValue Ptr = ST->getBasePtr();
6113 EVT VT = Value.getValueType();
6115 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
6118 unsigned Opc = Value.getOpcode();
6120 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
6121 // is a byte mask indicating a consecutive number of bytes, check to see if
6122 // Y is known to provide just those bytes. If so, we try to replace the
6123 // load + replace + store sequence with a single (narrower) store, which makes
6125 if (Opc == ISD::OR) {
6126 std::pair<unsigned, unsigned> MaskedLoad;
6127 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
6128 if (MaskedLoad.first)
6129 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6130 Value.getOperand(1), ST,this))
6131 return SDValue(NewST, 0);
6133 // Or is commutative, so try swapping X and Y.
6134 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
6135 if (MaskedLoad.first)
6136 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6137 Value.getOperand(0), ST,this))
6138 return SDValue(NewST, 0);
6141 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
6142 Value.getOperand(1).getOpcode() != ISD::Constant)
6145 SDValue N0 = Value.getOperand(0);
6146 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6147 Chain == SDValue(N0.getNode(), 1)) {
6148 LoadSDNode *LD = cast<LoadSDNode>(N0);
6149 if (LD->getBasePtr() != Ptr ||
6150 LD->getPointerInfo().getAddrSpace() !=
6151 ST->getPointerInfo().getAddrSpace())
6154 // Find the type to narrow it the load / op / store to.
6155 SDValue N1 = Value.getOperand(1);
6156 unsigned BitWidth = N1.getValueSizeInBits();
6157 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
6158 if (Opc == ISD::AND)
6159 Imm ^= APInt::getAllOnesValue(BitWidth);
6160 if (Imm == 0 || Imm.isAllOnesValue())
6162 unsigned ShAmt = Imm.countTrailingZeros();
6163 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
6164 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
6165 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6166 while (NewBW < BitWidth &&
6167 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
6168 TLI.isNarrowingProfitable(VT, NewVT))) {
6169 NewBW = NextPowerOf2(NewBW);
6170 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6172 if (NewBW >= BitWidth)
6175 // If the lsb changed does not start at the type bitwidth boundary,
6176 // start at the previous one.
6178 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
6179 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
6180 if ((Imm & Mask) == Imm) {
6181 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
6182 if (Opc == ISD::AND)
6183 NewImm ^= APInt::getAllOnesValue(NewBW);
6184 uint64_t PtrOff = ShAmt / 8;
6185 // For big endian targets, we need to adjust the offset to the pointer to
6186 // load the correct bytes.
6187 if (TLI.isBigEndian())
6188 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
6190 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
6191 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
6192 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
6195 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
6196 Ptr.getValueType(), Ptr,
6197 DAG.getConstant(PtrOff, Ptr.getValueType()));
6198 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
6199 LD->getChain(), NewPtr,
6200 LD->getPointerInfo().getWithOffset(PtrOff),
6201 LD->isVolatile(), LD->isNonTemporal(),
6203 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
6204 DAG.getConstant(NewImm, NewVT));
6205 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
6207 ST->getPointerInfo().getWithOffset(PtrOff),
6208 false, false, NewAlign);
6210 AddToWorkList(NewPtr.getNode());
6211 AddToWorkList(NewLD.getNode());
6212 AddToWorkList(NewVal.getNode());
6213 WorkListRemover DeadNodes(*this);
6214 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
6224 /// TransformFPLoadStorePair - For a given floating point load / store pair,
6225 /// if the load value isn't used by any other operations, then consider
6226 /// transforming the pair to integer load / store operations if the target
6227 /// deems the transformation profitable.
6228 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
6229 StoreSDNode *ST = cast<StoreSDNode>(N);
6230 SDValue Chain = ST->getChain();
6231 SDValue Value = ST->getValue();
6232 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
6233 Value.hasOneUse() &&
6234 Chain == SDValue(Value.getNode(), 1)) {
6235 LoadSDNode *LD = cast<LoadSDNode>(Value);
6236 EVT VT = LD->getMemoryVT();
6237 if (!VT.isFloatingPoint() ||
6238 VT != ST->getMemoryVT() ||
6239 LD->isNonTemporal() ||
6240 ST->isNonTemporal() ||
6241 LD->getPointerInfo().getAddrSpace() != 0 ||
6242 ST->getPointerInfo().getAddrSpace() != 0)
6245 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
6246 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
6247 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
6248 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
6249 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
6252 unsigned LDAlign = LD->getAlignment();
6253 unsigned STAlign = ST->getAlignment();
6254 const Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
6255 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy);
6256 if (LDAlign < ABIAlign || STAlign < ABIAlign)
6259 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
6260 LD->getChain(), LD->getBasePtr(),
6261 LD->getPointerInfo(),
6262 false, false, LDAlign);
6264 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
6265 NewLD, ST->getBasePtr(),
6266 ST->getPointerInfo(),
6267 false, false, STAlign);
6269 AddToWorkList(NewLD.getNode());
6270 AddToWorkList(NewST.getNode());
6271 WorkListRemover DeadNodes(*this);
6272 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1),
6281 SDValue DAGCombiner::visitSTORE(SDNode *N) {
6282 StoreSDNode *ST = cast<StoreSDNode>(N);
6283 SDValue Chain = ST->getChain();
6284 SDValue Value = ST->getValue();
6285 SDValue Ptr = ST->getBasePtr();
6287 // If this is a store of a bit convert, store the input value if the
6288 // resultant store does not need a higher alignment than the original.
6289 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
6290 ST->isUnindexed()) {
6291 unsigned OrigAlign = ST->getAlignment();
6292 EVT SVT = Value.getOperand(0).getValueType();
6293 unsigned Align = TLI.getTargetData()->
6294 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
6295 if (Align <= OrigAlign &&
6296 ((!LegalOperations && !ST->isVolatile()) ||
6297 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
6298 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6299 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6300 ST->isNonTemporal(), OrigAlign);
6303 // Turn 'store undef, Ptr' -> nothing.
6304 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
6307 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
6308 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
6309 // NOTE: If the original store is volatile, this transform must not increase
6310 // the number of stores. For example, on x86-32 an f64 can be stored in one
6311 // processor operation but an i64 (which is not legal) requires two. So the
6312 // transform should not be done in this case.
6313 if (Value.getOpcode() != ISD::TargetConstantFP) {
6315 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
6316 default: llvm_unreachable("Unknown FP type");
6317 case MVT::f80: // We don't do this for these yet.
6322 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
6323 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6324 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
6325 bitcastToAPInt().getZExtValue(), MVT::i32);
6326 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6327 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6328 ST->isNonTemporal(), ST->getAlignment());
6332 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
6333 !ST->isVolatile()) ||
6334 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
6335 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
6336 getZExtValue(), MVT::i64);
6337 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6338 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6339 ST->isNonTemporal(), ST->getAlignment());
6342 if (!ST->isVolatile() &&
6343 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6344 // Many FP stores are not made apparent until after legalize, e.g. for
6345 // argument passing. Since this is so common, custom legalize the
6346 // 64-bit integer store into two 32-bit stores.
6347 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
6348 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
6349 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
6350 if (TLI.isBigEndian()) std::swap(Lo, Hi);
6352 unsigned Alignment = ST->getAlignment();
6353 bool isVolatile = ST->isVolatile();
6354 bool isNonTemporal = ST->isNonTemporal();
6356 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
6357 Ptr, ST->getPointerInfo(),
6358 isVolatile, isNonTemporal,
6359 ST->getAlignment());
6360 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
6361 DAG.getConstant(4, Ptr.getValueType()));
6362 Alignment = MinAlign(Alignment, 4U);
6363 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
6364 Ptr, ST->getPointerInfo().getWithOffset(4),
6365 isVolatile, isNonTemporal,
6367 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6376 // Try to infer better alignment information than the store already has.
6377 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
6378 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6379 if (Align > ST->getAlignment())
6380 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
6381 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6382 ST->isVolatile(), ST->isNonTemporal(), Align);
6386 // Try transforming a pair floating point load / store ops to integer
6387 // load / store ops.
6388 SDValue NewST = TransformFPLoadStorePair(N);
6389 if (NewST.getNode())
6393 // Walk up chain skipping non-aliasing memory nodes.
6394 SDValue BetterChain = FindBetterChain(N, Chain);
6396 // If there is a better chain.
6397 if (Chain != BetterChain) {
6400 // Replace the chain to avoid dependency.
6401 if (ST->isTruncatingStore()) {
6402 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6403 ST->getPointerInfo(),
6404 ST->getMemoryVT(), ST->isVolatile(),
6405 ST->isNonTemporal(), ST->getAlignment());
6407 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6408 ST->getPointerInfo(),
6409 ST->isVolatile(), ST->isNonTemporal(),
6410 ST->getAlignment());
6413 // Create token to keep both nodes around.
6414 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6415 MVT::Other, Chain, ReplStore);
6417 // Make sure the new and old chains are cleaned up.
6418 AddToWorkList(Token.getNode());
6420 // Don't add users to work list.
6421 return CombineTo(N, Token, false);
6425 // Try transforming N to an indexed store.
6426 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6427 return SDValue(N, 0);
6429 // FIXME: is there such a thing as a truncating indexed store?
6430 if (ST->isTruncatingStore() && ST->isUnindexed() &&
6431 Value.getValueType().isInteger()) {
6432 // See if we can simplify the input to this truncstore with knowledge that
6433 // only the low bits are being used. For example:
6434 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
6436 GetDemandedBits(Value,
6437 APInt::getLowBitsSet(
6438 Value.getValueType().getScalarType().getSizeInBits(),
6439 ST->getMemoryVT().getScalarType().getSizeInBits()));
6440 AddToWorkList(Value.getNode());
6441 if (Shorter.getNode())
6442 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
6443 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6444 ST->isVolatile(), ST->isNonTemporal(),
6445 ST->getAlignment());
6447 // Otherwise, see if we can simplify the operation with
6448 // SimplifyDemandedBits, which only works if the value has a single use.
6449 if (SimplifyDemandedBits(Value,
6450 APInt::getLowBitsSet(
6451 Value.getValueType().getScalarType().getSizeInBits(),
6452 ST->getMemoryVT().getScalarType().getSizeInBits())))
6453 return SDValue(N, 0);
6456 // If this is a load followed by a store to the same location, then the store
6458 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
6459 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
6460 ST->isUnindexed() && !ST->isVolatile() &&
6461 // There can't be any side effects between the load and store, such as
6463 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
6464 // The store is dead, remove it.
6469 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
6470 // truncating store. We can do this even if this is already a truncstore.
6471 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
6472 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
6473 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
6474 ST->getMemoryVT())) {
6475 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6476 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6477 ST->isVolatile(), ST->isNonTemporal(),
6478 ST->getAlignment());
6481 return ReduceLoadOpStoreWidth(N);
6484 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
6485 SDValue InVec = N->getOperand(0);
6486 SDValue InVal = N->getOperand(1);
6487 SDValue EltNo = N->getOperand(2);
6489 // If the inserted element is an UNDEF, just use the input vector.
6490 if (InVal.getOpcode() == ISD::UNDEF)
6493 EVT VT = InVec.getValueType();
6495 // If we can't generate a legal BUILD_VECTOR, exit
6496 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
6499 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
6500 // vector with the inserted element.
6501 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
6502 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6503 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
6504 InVec.getNode()->op_end());
6505 if (Elt < Ops.size())
6507 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6508 VT, &Ops[0], Ops.size());
6510 // If the invec is an UNDEF and if EltNo is a constant, create a new
6511 // BUILD_VECTOR with undef elements and the inserted element.
6512 if (InVec.getOpcode() == ISD::UNDEF &&
6513 isa<ConstantSDNode>(EltNo)) {
6514 EVT EltVT = VT.getVectorElementType();
6515 unsigned NElts = VT.getVectorNumElements();
6516 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
6518 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6519 if (Elt < Ops.size())
6521 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6522 VT, &Ops[0], Ops.size());
6527 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
6528 // (vextract (scalar_to_vector val, 0) -> val
6529 SDValue InVec = N->getOperand(0);
6531 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
6532 // Check if the result type doesn't match the inserted element type. A
6533 // SCALAR_TO_VECTOR may truncate the inserted element and the
6534 // EXTRACT_VECTOR_ELT may widen the extracted vector.
6535 SDValue InOp = InVec.getOperand(0);
6536 EVT NVT = N->getValueType(0);
6537 if (InOp.getValueType() != NVT) {
6538 assert(InOp.getValueType().isInteger() && NVT.isInteger());
6539 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
6544 // Perform only after legalization to ensure build_vector / vector_shuffle
6545 // optimizations have already been done.
6546 if (!LegalOperations) return SDValue();
6548 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
6549 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
6550 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
6551 SDValue EltNo = N->getOperand(1);
6553 if (isa<ConstantSDNode>(EltNo)) {
6554 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6555 bool NewLoad = false;
6556 bool BCNumEltsChanged = false;
6557 EVT VT = InVec.getValueType();
6558 EVT ExtVT = VT.getVectorElementType();
6561 if (InVec.getOpcode() == ISD::BITCAST) {
6562 EVT BCVT = InVec.getOperand(0).getValueType();
6563 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
6565 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
6566 BCNumEltsChanged = true;
6567 InVec = InVec.getOperand(0);
6568 ExtVT = BCVT.getVectorElementType();
6572 LoadSDNode *LN0 = NULL;
6573 const ShuffleVectorSDNode *SVN = NULL;
6574 if (ISD::isNormalLoad(InVec.getNode())) {
6575 LN0 = cast<LoadSDNode>(InVec);
6576 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6577 InVec.getOperand(0).getValueType() == ExtVT &&
6578 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
6579 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
6580 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
6581 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
6583 // (load $addr+1*size)
6585 // If the bit convert changed the number of elements, it is unsafe
6586 // to examine the mask.
6587 if (BCNumEltsChanged)
6590 // Select the input vector, guarding against out of range extract vector.
6591 unsigned NumElems = VT.getVectorNumElements();
6592 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
6593 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
6595 if (InVec.getOpcode() == ISD::BITCAST)
6596 InVec = InVec.getOperand(0);
6597 if (ISD::isNormalLoad(InVec.getNode())) {
6598 LN0 = cast<LoadSDNode>(InVec);
6599 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
6603 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6606 // If Idx was -1 above, Elt is going to be -1, so just return undef.
6608 return DAG.getUNDEF(LN0->getBasePtr().getValueType());
6610 unsigned Align = LN0->getAlignment();
6612 // Check the resultant load doesn't need a higher alignment than the
6616 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
6618 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
6624 SDValue NewPtr = LN0->getBasePtr();
6625 unsigned PtrOff = 0;
6628 PtrOff = LVT.getSizeInBits() * Elt / 8;
6629 EVT PtrType = NewPtr.getValueType();
6630 if (TLI.isBigEndian())
6631 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
6632 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
6633 DAG.getConstant(PtrOff, PtrType));
6636 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
6637 LN0->getPointerInfo().getWithOffset(PtrOff),
6638 LN0->isVolatile(), LN0->isNonTemporal(), Align);
6644 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
6645 unsigned NumInScalars = N->getNumOperands();
6646 EVT VT = N->getValueType(0);
6648 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
6649 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
6650 // at most two distinct vectors, turn this into a shuffle node.
6651 SDValue VecIn1, VecIn2;
6652 for (unsigned i = 0; i != NumInScalars; ++i) {
6653 // Ignore undef inputs.
6654 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6656 // If this input is something other than a EXTRACT_VECTOR_ELT with a
6657 // constant index, bail out.
6658 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
6659 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
6660 VecIn1 = VecIn2 = SDValue(0, 0);
6664 // If the input vector type disagrees with the result of the build_vector,
6665 // we can't make a shuffle.
6666 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
6667 if (ExtractedFromVec.getValueType() != VT) {
6668 VecIn1 = VecIn2 = SDValue(0, 0);
6672 // Otherwise, remember this. We allow up to two distinct input vectors.
6673 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
6676 if (VecIn1.getNode() == 0) {
6677 VecIn1 = ExtractedFromVec;
6678 } else if (VecIn2.getNode() == 0) {
6679 VecIn2 = ExtractedFromVec;
6682 VecIn1 = VecIn2 = SDValue(0, 0);
6687 // If everything is good, we can make a shuffle operation.
6688 if (VecIn1.getNode()) {
6689 SmallVector<int, 8> Mask;
6690 for (unsigned i = 0; i != NumInScalars; ++i) {
6691 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
6696 // If extracting from the first vector, just use the index directly.
6697 SDValue Extract = N->getOperand(i);
6698 SDValue ExtVal = Extract.getOperand(1);
6699 if (Extract.getOperand(0) == VecIn1) {
6700 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6701 if (ExtIndex > VT.getVectorNumElements())
6704 Mask.push_back(ExtIndex);
6708 // Otherwise, use InIdx + VecSize
6709 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
6710 Mask.push_back(Idx+NumInScalars);
6713 // Add count and size info.
6714 if (!isTypeLegal(VT))
6717 // Return the new VECTOR_SHUFFLE node.
6720 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
6721 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
6727 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
6728 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
6729 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
6730 // inputs come from at most two distinct vectors, turn this into a shuffle
6733 // If we only have one input vector, we don't need to do any concatenation.
6734 if (N->getNumOperands() == 1)
6735 return N->getOperand(0);
6740 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
6741 EVT VT = N->getValueType(0);
6742 unsigned NumElts = VT.getVectorNumElements();
6744 SDValue N0 = N->getOperand(0);
6746 assert(N0.getValueType().getVectorNumElements() == NumElts &&
6747 "Vector shuffle must be normalized in DAG");
6749 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
6751 // If it is a splat, check if the argument vector is another splat or a
6752 // build_vector with all scalar elements the same.
6753 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
6754 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
6755 SDNode *V = N0.getNode();
6757 // If this is a bit convert that changes the element type of the vector but
6758 // not the number of vector elements, look through it. Be careful not to
6759 // look though conversions that change things like v4f32 to v2f64.
6760 if (V->getOpcode() == ISD::BITCAST) {
6761 SDValue ConvInput = V->getOperand(0);
6762 if (ConvInput.getValueType().isVector() &&
6763 ConvInput.getValueType().getVectorNumElements() == NumElts)
6764 V = ConvInput.getNode();
6767 if (V->getOpcode() == ISD::BUILD_VECTOR) {
6768 assert(V->getNumOperands() == NumElts &&
6769 "BUILD_VECTOR has wrong number of operands");
6771 bool AllSame = true;
6772 for (unsigned i = 0; i != NumElts; ++i) {
6773 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
6774 Base = V->getOperand(i);
6778 // Splat of <u, u, u, u>, return <u, u, u, u>
6779 if (!Base.getNode())
6781 for (unsigned i = 0; i != NumElts; ++i) {
6782 if (V->getOperand(i) != Base) {
6787 // Splat of <x, x, x, x>, return <x, x, x, x>
6795 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
6796 if (!TLI.getShouldFoldAtomicFences())
6799 SDValue atomic = N->getOperand(0);
6800 switch (atomic.getOpcode()) {
6801 case ISD::ATOMIC_CMP_SWAP:
6802 case ISD::ATOMIC_SWAP:
6803 case ISD::ATOMIC_LOAD_ADD:
6804 case ISD::ATOMIC_LOAD_SUB:
6805 case ISD::ATOMIC_LOAD_AND:
6806 case ISD::ATOMIC_LOAD_OR:
6807 case ISD::ATOMIC_LOAD_XOR:
6808 case ISD::ATOMIC_LOAD_NAND:
6809 case ISD::ATOMIC_LOAD_MIN:
6810 case ISD::ATOMIC_LOAD_MAX:
6811 case ISD::ATOMIC_LOAD_UMIN:
6812 case ISD::ATOMIC_LOAD_UMAX:
6818 SDValue fence = atomic.getOperand(0);
6819 if (fence.getOpcode() != ISD::MEMBARRIER)
6822 switch (atomic.getOpcode()) {
6823 case ISD::ATOMIC_CMP_SWAP:
6824 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
6825 fence.getOperand(0),
6826 atomic.getOperand(1), atomic.getOperand(2),
6827 atomic.getOperand(3)), atomic.getResNo());
6828 case ISD::ATOMIC_SWAP:
6829 case ISD::ATOMIC_LOAD_ADD:
6830 case ISD::ATOMIC_LOAD_SUB:
6831 case ISD::ATOMIC_LOAD_AND:
6832 case ISD::ATOMIC_LOAD_OR:
6833 case ISD::ATOMIC_LOAD_XOR:
6834 case ISD::ATOMIC_LOAD_NAND:
6835 case ISD::ATOMIC_LOAD_MIN:
6836 case ISD::ATOMIC_LOAD_MAX:
6837 case ISD::ATOMIC_LOAD_UMIN:
6838 case ISD::ATOMIC_LOAD_UMAX:
6839 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
6840 fence.getOperand(0),
6841 atomic.getOperand(1), atomic.getOperand(2)),
6848 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
6849 /// an AND to a vector_shuffle with the destination vector and a zero vector.
6850 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
6851 /// vector_shuffle V, Zero, <0, 4, 2, 4>
6852 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
6853 EVT VT = N->getValueType(0);
6854 DebugLoc dl = N->getDebugLoc();
6855 SDValue LHS = N->getOperand(0);
6856 SDValue RHS = N->getOperand(1);
6857 if (N->getOpcode() == ISD::AND) {
6858 if (RHS.getOpcode() == ISD::BITCAST)
6859 RHS = RHS.getOperand(0);
6860 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
6861 SmallVector<int, 8> Indices;
6862 unsigned NumElts = RHS.getNumOperands();
6863 for (unsigned i = 0; i != NumElts; ++i) {
6864 SDValue Elt = RHS.getOperand(i);
6865 if (!isa<ConstantSDNode>(Elt))
6867 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
6868 Indices.push_back(i);
6869 else if (cast<ConstantSDNode>(Elt)->isNullValue())
6870 Indices.push_back(NumElts);
6875 // Let's see if the target supports this vector_shuffle.
6876 EVT RVT = RHS.getValueType();
6877 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
6880 // Return the new VECTOR_SHUFFLE node.
6881 EVT EltVT = RVT.getVectorElementType();
6882 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
6883 DAG.getConstant(0, EltVT));
6884 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6885 RVT, &ZeroOps[0], ZeroOps.size());
6886 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
6887 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
6888 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
6895 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
6896 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
6897 // After legalize, the target may be depending on adds and other
6898 // binary ops to provide legal ways to construct constants or other
6899 // things. Simplifying them may result in a loss of legality.
6900 if (LegalOperations) return SDValue();
6902 assert(N->getValueType(0).isVector() &&
6903 "SimplifyVBinOp only works on vectors!");
6905 SDValue LHS = N->getOperand(0);
6906 SDValue RHS = N->getOperand(1);
6907 SDValue Shuffle = XformToShuffleWithZero(N);
6908 if (Shuffle.getNode()) return Shuffle;
6910 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
6912 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
6913 RHS.getOpcode() == ISD::BUILD_VECTOR) {
6914 SmallVector<SDValue, 8> Ops;
6915 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
6916 SDValue LHSOp = LHS.getOperand(i);
6917 SDValue RHSOp = RHS.getOperand(i);
6918 // If these two elements can't be folded, bail out.
6919 if ((LHSOp.getOpcode() != ISD::UNDEF &&
6920 LHSOp.getOpcode() != ISD::Constant &&
6921 LHSOp.getOpcode() != ISD::ConstantFP) ||
6922 (RHSOp.getOpcode() != ISD::UNDEF &&
6923 RHSOp.getOpcode() != ISD::Constant &&
6924 RHSOp.getOpcode() != ISD::ConstantFP))
6927 // Can't fold divide by zero.
6928 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
6929 N->getOpcode() == ISD::FDIV) {
6930 if ((RHSOp.getOpcode() == ISD::Constant &&
6931 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
6932 (RHSOp.getOpcode() == ISD::ConstantFP &&
6933 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
6937 EVT VT = LHSOp.getValueType();
6938 assert(RHSOp.getValueType() == VT &&
6939 "SimplifyVBinOp with different BUILD_VECTOR element types");
6940 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
6942 if (FoldOp.getOpcode() != ISD::UNDEF &&
6943 FoldOp.getOpcode() != ISD::Constant &&
6944 FoldOp.getOpcode() != ISD::ConstantFP)
6946 Ops.push_back(FoldOp);
6947 AddToWorkList(FoldOp.getNode());
6950 if (Ops.size() == LHS.getNumOperands())
6951 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6952 LHS.getValueType(), &Ops[0], Ops.size());
6958 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
6959 SDValue N1, SDValue N2){
6960 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
6962 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
6963 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6965 // If we got a simplified select_cc node back from SimplifySelectCC, then
6966 // break it down into a new SETCC node, and a new SELECT node, and then return
6967 // the SELECT node, since we were called with a SELECT node.
6968 if (SCC.getNode()) {
6969 // Check to see if we got a select_cc back (to turn into setcc/select).
6970 // Otherwise, just return whatever node we got back, like fabs.
6971 if (SCC.getOpcode() == ISD::SELECT_CC) {
6972 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
6974 SCC.getOperand(0), SCC.getOperand(1),
6976 AddToWorkList(SETCC.getNode());
6977 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
6978 SCC.getOperand(2), SCC.getOperand(3), SETCC);
6986 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
6987 /// are the two values being selected between, see if we can simplify the
6988 /// select. Callers of this should assume that TheSelect is deleted if this
6989 /// returns true. As such, they should return the appropriate thing (e.g. the
6990 /// node) back to the top-level of the DAG combiner loop to avoid it being
6992 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
6995 // Cannot simplify select with vector condition
6996 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
6998 // If this is a select from two identical things, try to pull the operation
6999 // through the select.
7000 if (LHS.getOpcode() != RHS.getOpcode() ||
7001 !LHS.hasOneUse() || !RHS.hasOneUse())
7004 // If this is a load and the token chain is identical, replace the select
7005 // of two loads with a load through a select of the address to load from.
7006 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
7007 // constants have been dropped into the constant pool.
7008 if (LHS.getOpcode() == ISD::LOAD) {
7009 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
7010 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
7012 // Token chains must be identical.
7013 if (LHS.getOperand(0) != RHS.getOperand(0) ||
7014 // Do not let this transformation reduce the number of volatile loads.
7015 LLD->isVolatile() || RLD->isVolatile() ||
7016 // If this is an EXTLOAD, the VT's must match.
7017 LLD->getMemoryVT() != RLD->getMemoryVT() ||
7018 // If this is an EXTLOAD, the kind of extension must match.
7019 (LLD->getExtensionType() != RLD->getExtensionType() &&
7020 // The only exception is if one of the extensions is anyext.
7021 LLD->getExtensionType() != ISD::EXTLOAD &&
7022 RLD->getExtensionType() != ISD::EXTLOAD) ||
7023 // FIXME: this discards src value information. This is
7024 // over-conservative. It would be beneficial to be able to remember
7025 // both potential memory locations. Since we are discarding
7026 // src value info, don't do the transformation if the memory
7027 // locations are not in the default address space.
7028 LLD->getPointerInfo().getAddrSpace() != 0 ||
7029 RLD->getPointerInfo().getAddrSpace() != 0)
7032 // Check that the select condition doesn't reach either load. If so,
7033 // folding this will induce a cycle into the DAG. If not, this is safe to
7034 // xform, so create a select of the addresses.
7036 if (TheSelect->getOpcode() == ISD::SELECT) {
7037 SDNode *CondNode = TheSelect->getOperand(0).getNode();
7038 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
7039 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
7041 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
7042 LLD->getBasePtr().getValueType(),
7043 TheSelect->getOperand(0), LLD->getBasePtr(),
7045 } else { // Otherwise SELECT_CC
7046 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
7047 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
7049 if ((LLD->hasAnyUseOfValue(1) &&
7050 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
7051 (LLD->hasAnyUseOfValue(1) &&
7052 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))))
7055 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
7056 LLD->getBasePtr().getValueType(),
7057 TheSelect->getOperand(0),
7058 TheSelect->getOperand(1),
7059 LLD->getBasePtr(), RLD->getBasePtr(),
7060 TheSelect->getOperand(4));
7064 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
7065 Load = DAG.getLoad(TheSelect->getValueType(0),
7066 TheSelect->getDebugLoc(),
7067 // FIXME: Discards pointer info.
7068 LLD->getChain(), Addr, MachinePointerInfo(),
7069 LLD->isVolatile(), LLD->isNonTemporal(),
7070 LLD->getAlignment());
7072 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
7073 RLD->getExtensionType() : LLD->getExtensionType(),
7074 TheSelect->getDebugLoc(),
7075 TheSelect->getValueType(0),
7076 // FIXME: Discards pointer info.
7077 LLD->getChain(), Addr, MachinePointerInfo(),
7078 LLD->getMemoryVT(), LLD->isVolatile(),
7079 LLD->isNonTemporal(), LLD->getAlignment());
7082 // Users of the select now use the result of the load.
7083 CombineTo(TheSelect, Load);
7085 // Users of the old loads now use the new load's chain. We know the
7086 // old-load value is dead now.
7087 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
7088 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
7095 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
7096 /// where 'cond' is the comparison specified by CC.
7097 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
7098 SDValue N2, SDValue N3,
7099 ISD::CondCode CC, bool NotExtCompare) {
7100 // (x ? y : y) -> y.
7101 if (N2 == N3) return N2;
7103 EVT VT = N2.getValueType();
7104 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
7105 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
7106 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
7108 // Determine if the condition we're dealing with is constant
7109 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
7110 N0, N1, CC, DL, false);
7111 if (SCC.getNode()) AddToWorkList(SCC.getNode());
7112 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
7114 // fold select_cc true, x, y -> x
7115 if (SCCC && !SCCC->isNullValue())
7117 // fold select_cc false, x, y -> y
7118 if (SCCC && SCCC->isNullValue())
7121 // Check to see if we can simplify the select into an fabs node
7122 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
7123 // Allow either -0.0 or 0.0
7124 if (CFP->getValueAPF().isZero()) {
7125 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
7126 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
7127 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
7128 N2 == N3.getOperand(0))
7129 return DAG.getNode(ISD::FABS, DL, VT, N0);
7131 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
7132 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
7133 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
7134 N2.getOperand(0) == N3)
7135 return DAG.getNode(ISD::FABS, DL, VT, N3);
7139 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
7140 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
7141 // in it. This is a win when the constant is not otherwise available because
7142 // it replaces two constant pool loads with one. We only do this if the FP
7143 // type is known to be legal, because if it isn't, then we are before legalize
7144 // types an we want the other legalization to happen first (e.g. to avoid
7145 // messing with soft float) and if the ConstantFP is not legal, because if
7146 // it is legal, we may not need to store the FP constant in a constant pool.
7147 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
7148 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
7149 if (TLI.isTypeLegal(N2.getValueType()) &&
7150 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
7151 TargetLowering::Legal) &&
7152 // If both constants have multiple uses, then we won't need to do an
7153 // extra load, they are likely around in registers for other users.
7154 (TV->hasOneUse() || FV->hasOneUse())) {
7155 Constant *Elts[] = {
7156 const_cast<ConstantFP*>(FV->getConstantFPValue()),
7157 const_cast<ConstantFP*>(TV->getConstantFPValue())
7159 const Type *FPTy = Elts[0]->getType();
7160 const TargetData &TD = *TLI.getTargetData();
7162 // Create a ConstantArray of the two constants.
7163 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
7164 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
7165 TD.getPrefTypeAlignment(FPTy));
7166 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
7168 // Get the offsets to the 0 and 1 element of the array so that we can
7169 // select between them.
7170 SDValue Zero = DAG.getIntPtrConstant(0);
7171 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
7172 SDValue One = DAG.getIntPtrConstant(EltSize);
7174 SDValue Cond = DAG.getSetCC(DL,
7175 TLI.getSetCCResultType(N0.getValueType()),
7177 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
7179 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
7181 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
7182 MachinePointerInfo::getConstantPool(), false,
7188 // Check to see if we can perform the "gzip trick", transforming
7189 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
7190 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
7191 N0.getValueType().isInteger() &&
7192 N2.getValueType().isInteger() &&
7193 (N1C->isNullValue() || // (a < 0) ? b : 0
7194 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
7195 EVT XType = N0.getValueType();
7196 EVT AType = N2.getValueType();
7197 if (XType.bitsGE(AType)) {
7198 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
7199 // single-bit constant.
7200 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
7201 unsigned ShCtV = N2C->getAPIntValue().logBase2();
7202 ShCtV = XType.getSizeInBits()-ShCtV-1;
7203 SDValue ShCt = DAG.getConstant(ShCtV,
7204 getShiftAmountTy(N0.getValueType()));
7205 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
7207 AddToWorkList(Shift.getNode());
7209 if (XType.bitsGT(AType)) {
7210 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7211 AddToWorkList(Shift.getNode());
7214 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7217 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
7219 DAG.getConstant(XType.getSizeInBits()-1,
7220 getShiftAmountTy(N0.getValueType())));
7221 AddToWorkList(Shift.getNode());
7223 if (XType.bitsGT(AType)) {
7224 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7225 AddToWorkList(Shift.getNode());
7228 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7232 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
7233 // where y is has a single bit set.
7234 // A plaintext description would be, we can turn the SELECT_CC into an AND
7235 // when the condition can be materialized as an all-ones register. Any
7236 // single bit-test can be materialized as an all-ones register with
7237 // shift-left and shift-right-arith.
7238 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
7239 N0->getValueType(0) == VT &&
7240 N1C && N1C->isNullValue() &&
7241 N2C && N2C->isNullValue()) {
7242 SDValue AndLHS = N0->getOperand(0);
7243 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
7244 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
7245 // Shift the tested bit over the sign bit.
7246 APInt AndMask = ConstAndRHS->getAPIntValue();
7248 DAG.getConstant(AndMask.countLeadingZeros(),
7249 getShiftAmountTy(AndLHS.getValueType()));
7250 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
7252 // Now arithmetic right shift it all the way over, so the result is either
7253 // all-ones, or zero.
7255 DAG.getConstant(AndMask.getBitWidth()-1,
7256 getShiftAmountTy(Shl.getValueType()));
7257 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
7259 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
7263 // fold select C, 16, 0 -> shl C, 4
7264 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
7265 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
7267 // If the caller doesn't want us to simplify this into a zext of a compare,
7269 if (NotExtCompare && N2C->getAPIntValue() == 1)
7272 // Get a SetCC of the condition
7273 // FIXME: Should probably make sure that setcc is legal if we ever have a
7274 // target where it isn't.
7276 // cast from setcc result type to select result type
7278 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
7280 if (N2.getValueType().bitsLT(SCC.getValueType()))
7281 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
7283 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7284 N2.getValueType(), SCC);
7286 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
7287 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7288 N2.getValueType(), SCC);
7291 AddToWorkList(SCC.getNode());
7292 AddToWorkList(Temp.getNode());
7294 if (N2C->getAPIntValue() == 1)
7297 // shl setcc result by log2 n2c
7298 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
7299 DAG.getConstant(N2C->getAPIntValue().logBase2(),
7300 getShiftAmountTy(Temp.getValueType())));
7303 // Check to see if this is the equivalent of setcc
7304 // FIXME: Turn all of these into setcc if setcc if setcc is legal
7305 // otherwise, go ahead with the folds.
7306 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
7307 EVT XType = N0.getValueType();
7308 if (!LegalOperations ||
7309 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
7310 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
7311 if (Res.getValueType() != VT)
7312 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
7316 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
7317 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
7318 (!LegalOperations ||
7319 TLI.isOperationLegal(ISD::CTLZ, XType))) {
7320 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
7321 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
7322 DAG.getConstant(Log2_32(XType.getSizeInBits()),
7323 getShiftAmountTy(Ctlz.getValueType())));
7325 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
7326 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
7327 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
7328 XType, DAG.getConstant(0, XType), N0);
7329 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
7330 return DAG.getNode(ISD::SRL, DL, XType,
7331 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
7332 DAG.getConstant(XType.getSizeInBits()-1,
7333 getShiftAmountTy(XType)));
7335 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
7336 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
7337 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
7338 DAG.getConstant(XType.getSizeInBits()-1,
7339 getShiftAmountTy(N0.getValueType())));
7340 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
7344 // Check to see if this is an integer abs.
7345 // select_cc setg[te] X, 0, X, -X ->
7346 // select_cc setgt X, -1, X, -X ->
7347 // select_cc setl[te] X, 0, -X, X ->
7348 // select_cc setlt X, 1, -X, X ->
7349 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
7351 ConstantSDNode *SubC = NULL;
7352 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
7353 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
7354 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
7355 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
7356 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
7357 (N1C->isOne() && CC == ISD::SETLT)) &&
7358 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
7359 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
7361 EVT XType = N0.getValueType();
7362 if (SubC && SubC->isNullValue() && XType.isInteger()) {
7363 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
7365 DAG.getConstant(XType.getSizeInBits()-1,
7366 getShiftAmountTy(N0.getValueType())));
7367 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
7369 AddToWorkList(Shift.getNode());
7370 AddToWorkList(Add.getNode());
7371 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
7378 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
7379 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
7380 SDValue N1, ISD::CondCode Cond,
7381 DebugLoc DL, bool foldBooleans) {
7382 TargetLowering::DAGCombinerInfo
7383 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
7384 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
7387 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
7388 /// return a DAG expression to select that will generate the same value by
7389 /// multiplying by a magic number. See:
7390 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7391 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
7392 std::vector<SDNode*> Built;
7393 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
7395 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7401 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
7402 /// return a DAG expression to select that will generate the same value by
7403 /// multiplying by a magic number. See:
7404 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7405 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
7406 std::vector<SDNode*> Built;
7407 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
7409 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7415 /// FindBaseOffset - Return true if base is a frame index, which is known not
7416 // to alias with anything but itself. Provides base object and offset as
7418 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
7419 const GlobalValue *&GV, void *&CV) {
7420 // Assume it is a primitive operation.
7421 Base = Ptr; Offset = 0; GV = 0; CV = 0;
7423 // If it's an adding a simple constant then integrate the offset.
7424 if (Base.getOpcode() == ISD::ADD) {
7425 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
7426 Base = Base.getOperand(0);
7427 Offset += C->getZExtValue();
7431 // Return the underlying GlobalValue, and update the Offset. Return false
7432 // for GlobalAddressSDNode since the same GlobalAddress may be represented
7433 // by multiple nodes with different offsets.
7434 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
7435 GV = G->getGlobal();
7436 Offset += G->getOffset();
7440 // Return the underlying Constant value, and update the Offset. Return false
7441 // for ConstantSDNodes since the same constant pool entry may be represented
7442 // by multiple nodes with different offsets.
7443 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
7444 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
7445 : (void *)C->getConstVal();
7446 Offset += C->getOffset();
7449 // If it's any of the following then it can't alias with anything but itself.
7450 return isa<FrameIndexSDNode>(Base);
7453 /// isAlias - Return true if there is any possibility that the two addresses
7455 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
7456 const Value *SrcValue1, int SrcValueOffset1,
7457 unsigned SrcValueAlign1,
7458 const MDNode *TBAAInfo1,
7459 SDValue Ptr2, int64_t Size2,
7460 const Value *SrcValue2, int SrcValueOffset2,
7461 unsigned SrcValueAlign2,
7462 const MDNode *TBAAInfo2) const {
7463 // If they are the same then they must be aliases.
7464 if (Ptr1 == Ptr2) return true;
7466 // Gather base node and offset information.
7467 SDValue Base1, Base2;
7468 int64_t Offset1, Offset2;
7469 const GlobalValue *GV1, *GV2;
7471 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
7472 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
7474 // If they have a same base address then check to see if they overlap.
7475 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
7476 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7478 // It is possible for different frame indices to alias each other, mostly
7479 // when tail call optimization reuses return address slots for arguments.
7480 // To catch this case, look up the actual index of frame indices to compute
7481 // the real alias relationship.
7482 if (isFrameIndex1 && isFrameIndex2) {
7483 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7484 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
7485 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
7486 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7489 // Otherwise, if we know what the bases are, and they aren't identical, then
7490 // we know they cannot alias.
7491 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
7494 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
7495 // compared to the size and offset of the access, we may be able to prove they
7496 // do not alias. This check is conservative for now to catch cases created by
7497 // splitting vector types.
7498 if ((SrcValueAlign1 == SrcValueAlign2) &&
7499 (SrcValueOffset1 != SrcValueOffset2) &&
7500 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
7501 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
7502 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
7504 // There is no overlap between these relatively aligned accesses of similar
7505 // size, return no alias.
7506 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
7510 if (CombinerGlobalAA) {
7511 // Use alias analysis information.
7512 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
7513 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
7514 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
7515 AliasAnalysis::AliasResult AAResult =
7516 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
7517 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
7518 if (AAResult == AliasAnalysis::NoAlias)
7522 // Otherwise we have to assume they alias.
7526 /// FindAliasInfo - Extracts the relevant alias information from the memory
7527 /// node. Returns true if the operand was a load.
7528 bool DAGCombiner::FindAliasInfo(SDNode *N,
7529 SDValue &Ptr, int64_t &Size,
7530 const Value *&SrcValue,
7531 int &SrcValueOffset,
7532 unsigned &SrcValueAlign,
7533 const MDNode *&TBAAInfo) const {
7534 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7535 Ptr = LD->getBasePtr();
7536 Size = LD->getMemoryVT().getSizeInBits() >> 3;
7537 SrcValue = LD->getSrcValue();
7538 SrcValueOffset = LD->getSrcValueOffset();
7539 SrcValueAlign = LD->getOriginalAlignment();
7540 TBAAInfo = LD->getTBAAInfo();
7543 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7544 Ptr = ST->getBasePtr();
7545 Size = ST->getMemoryVT().getSizeInBits() >> 3;
7546 SrcValue = ST->getSrcValue();
7547 SrcValueOffset = ST->getSrcValueOffset();
7548 SrcValueAlign = ST->getOriginalAlignment();
7549 TBAAInfo = ST->getTBAAInfo();
7552 llvm_unreachable("FindAliasInfo expected a memory operand");
7555 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
7556 /// looking for aliasing nodes and adding them to the Aliases vector.
7557 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
7558 SmallVector<SDValue, 8> &Aliases) {
7559 SmallVector<SDValue, 8> Chains; // List of chains to visit.
7560 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
7562 // Get alias information for node.
7565 const Value *SrcValue;
7567 unsigned SrcValueAlign;
7568 const MDNode *SrcTBAAInfo;
7569 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
7570 SrcValueAlign, SrcTBAAInfo);
7573 Chains.push_back(OriginalChain);
7576 // Look at each chain and determine if it is an alias. If so, add it to the
7577 // aliases list. If not, then continue up the chain looking for the next
7579 while (!Chains.empty()) {
7580 SDValue Chain = Chains.back();
7583 // For TokenFactor nodes, look at each operand and only continue up the
7584 // chain until we find two aliases. If we've seen two aliases, assume we'll
7585 // find more and revert to original chain since the xform is unlikely to be
7588 // FIXME: The depth check could be made to return the last non-aliasing
7589 // chain we found before we hit a tokenfactor rather than the original
7591 if (Depth > 6 || Aliases.size() == 2) {
7593 Aliases.push_back(OriginalChain);
7597 // Don't bother if we've been before.
7598 if (!Visited.insert(Chain.getNode()))
7601 switch (Chain.getOpcode()) {
7602 case ISD::EntryToken:
7603 // Entry token is ideal chain operand, but handled in FindBetterChain.
7608 // Get alias information for Chain.
7611 const Value *OpSrcValue;
7612 int OpSrcValueOffset;
7613 unsigned OpSrcValueAlign;
7614 const MDNode *OpSrcTBAAInfo;
7615 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
7616 OpSrcValue, OpSrcValueOffset,
7620 // If chain is alias then stop here.
7621 if (!(IsLoad && IsOpLoad) &&
7622 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
7624 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
7625 OpSrcValueAlign, OpSrcTBAAInfo)) {
7626 Aliases.push_back(Chain);
7628 // Look further up the chain.
7629 Chains.push_back(Chain.getOperand(0));
7635 case ISD::TokenFactor:
7636 // We have to check each of the operands of the token factor for "small"
7637 // token factors, so we queue them up. Adding the operands to the queue
7638 // (stack) in reverse order maintains the original order and increases the
7639 // likelihood that getNode will find a matching token factor (CSE.)
7640 if (Chain.getNumOperands() > 16) {
7641 Aliases.push_back(Chain);
7644 for (unsigned n = Chain.getNumOperands(); n;)
7645 Chains.push_back(Chain.getOperand(--n));
7650 // For all other instructions we will just have to take what we can get.
7651 Aliases.push_back(Chain);
7657 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
7658 /// for a better chain (aliasing node.)
7659 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
7660 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
7662 // Accumulate all the aliases to this node.
7663 GatherAllAliases(N, OldChain, Aliases);
7665 // If no operands then chain to entry token.
7666 if (Aliases.size() == 0)
7667 return DAG.getEntryNode();
7669 // If a single operand then chain to it. We don't need to revisit it.
7670 if (Aliases.size() == 1)
7673 // Construct a custom tailored token factor.
7674 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
7675 &Aliases[0], Aliases.size());
7678 // SelectionDAG::Combine - This is the entry point for the file.
7680 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
7681 CodeGenOpt::Level OptLevel) {
7682 /// run - This is the main entry point to this class.
7684 DAGCombiner(*this, AA, OptLevel).Run(Level);