1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: Should add a corresponding version of fold AND with
20 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
23 // FIXME: select C, pow2, pow2 -> something smart
24 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
25 // FIXME: Dead stores -> nuke
26 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
27 // FIXME: mul (x, const) -> shifts + adds
28 // FIXME: undef values
29 // FIXME: make truncate see through SIGN_EXTEND and AND
30 // FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
31 // FIXME: verify that getNode can't return extends with an operand whose type
32 // is >= to that of the extend.
33 // FIXME: divide by zero is currently left unfolded. do we want to turn this
35 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
37 //===----------------------------------------------------------------------===//
39 #define DEBUG_TYPE "dagcombine"
40 #include "llvm/ADT/Statistic.h"
41 #include "llvm/CodeGen/SelectionDAG.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Target/TargetLowering.h"
51 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
58 // Worklist of all of the nodes that need to be simplified.
59 std::vector<SDNode*> WorkList;
61 /// AddUsersToWorkList - When an instruction is simplified, add all users of
62 /// the instruction to the work lists because they might get more simplified
65 void AddUsersToWorkList(SDNode *N) {
66 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
68 WorkList.push_back(*UI);
71 /// removeFromWorkList - remove all instances of N from the worklist.
72 void removeFromWorkList(SDNode *N) {
73 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
77 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
79 DEBUG(std::cerr << "\nReplacing "; N->dump();
80 std::cerr << "\nWith: "; To[0].Val->dump();
81 std::cerr << " and " << To.size()-1 << " other values\n");
82 std::vector<SDNode*> NowDead;
83 DAG.ReplaceAllUsesWith(N, To, &NowDead);
85 // Push the new nodes and any users onto the worklist
86 for (unsigned i = 0, e = To.size(); i != e; ++i) {
87 WorkList.push_back(To[i].Val);
88 AddUsersToWorkList(To[i].Val);
91 // Nodes can end up on the worklist more than once. Make sure we do
92 // not process a node that has been replaced.
93 removeFromWorkList(N);
94 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
95 removeFromWorkList(NowDead[i]);
97 // Finally, since the node is now dead, remove it from the graph.
99 return SDOperand(N, 0);
102 SDOperand CombineTo(SDNode *N, SDOperand Res) {
103 std::vector<SDOperand> To;
105 return CombineTo(N, To);
108 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
109 std::vector<SDOperand> To;
112 return CombineTo(N, To);
115 /// visit - call the node-specific routine that knows how to fold each
116 /// particular type of node.
117 SDOperand visit(SDNode *N);
119 // Visitation implementation - Implement dag node combining for different
120 // node types. The semantics are as follows:
122 // SDOperand.Val == 0 - No change was made
123 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
124 // otherwise - N should be replaced by the returned Operand.
126 SDOperand visitTokenFactor(SDNode *N);
127 SDOperand visitADD(SDNode *N);
128 SDOperand visitSUB(SDNode *N);
129 SDOperand visitMUL(SDNode *N);
130 SDOperand visitSDIV(SDNode *N);
131 SDOperand visitUDIV(SDNode *N);
132 SDOperand visitSREM(SDNode *N);
133 SDOperand visitUREM(SDNode *N);
134 SDOperand visitMULHU(SDNode *N);
135 SDOperand visitMULHS(SDNode *N);
136 SDOperand visitAND(SDNode *N);
137 SDOperand visitOR(SDNode *N);
138 SDOperand visitXOR(SDNode *N);
139 SDOperand visitSHL(SDNode *N);
140 SDOperand visitSRA(SDNode *N);
141 SDOperand visitSRL(SDNode *N);
142 SDOperand visitCTLZ(SDNode *N);
143 SDOperand visitCTTZ(SDNode *N);
144 SDOperand visitCTPOP(SDNode *N);
145 SDOperand visitSELECT(SDNode *N);
146 SDOperand visitSELECT_CC(SDNode *N);
147 SDOperand visitSETCC(SDNode *N);
148 SDOperand visitADD_PARTS(SDNode *N);
149 SDOperand visitSUB_PARTS(SDNode *N);
150 SDOperand visitSIGN_EXTEND(SDNode *N);
151 SDOperand visitZERO_EXTEND(SDNode *N);
152 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
153 SDOperand visitTRUNCATE(SDNode *N);
154 SDOperand visitBIT_CONVERT(SDNode *N);
156 SDOperand visitFADD(SDNode *N);
157 SDOperand visitFSUB(SDNode *N);
158 SDOperand visitFMUL(SDNode *N);
159 SDOperand visitFDIV(SDNode *N);
160 SDOperand visitFREM(SDNode *N);
161 SDOperand visitSINT_TO_FP(SDNode *N);
162 SDOperand visitUINT_TO_FP(SDNode *N);
163 SDOperand visitFP_TO_SINT(SDNode *N);
164 SDOperand visitFP_TO_UINT(SDNode *N);
165 SDOperand visitFP_ROUND(SDNode *N);
166 SDOperand visitFP_ROUND_INREG(SDNode *N);
167 SDOperand visitFP_EXTEND(SDNode *N);
168 SDOperand visitFNEG(SDNode *N);
169 SDOperand visitFABS(SDNode *N);
170 SDOperand visitBRCOND(SDNode *N);
171 SDOperand visitBRCONDTWOWAY(SDNode *N);
172 SDOperand visitBR_CC(SDNode *N);
173 SDOperand visitBRTWOWAY_CC(SDNode *N);
175 SDOperand visitLOAD(SDNode *N);
176 SDOperand visitSTORE(SDNode *N);
178 SDOperand visitLOCATION(SDNode *N);
179 SDOperand visitDEBUGLOC(SDNode *N);
181 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
183 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
184 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
185 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
186 SDOperand N3, ISD::CondCode CC);
187 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
188 ISD::CondCode Cond, bool foldBooleans = true);
190 SDOperand BuildSDIV(SDNode *N);
191 SDOperand BuildUDIV(SDNode *N);
193 DAGCombiner(SelectionDAG &D)
194 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
196 /// Run - runs the dag combiner on all nodes in the work list
197 void Run(bool RunningAfterLegalize);
202 int64_t m; // magic number
203 int64_t s; // shift amount
207 uint64_t m; // magic number
208 int64_t a; // add indicator
209 int64_t s; // shift amount
212 /// magic - calculate the magic numbers required to codegen an integer sdiv as
213 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
215 static ms magic32(int32_t d) {
217 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
218 const uint32_t two31 = 0x80000000U;
222 t = two31 + ((uint32_t)d >> 31);
223 anc = t - 1 - t%ad; // absolute value of nc
224 p = 31; // initialize p
225 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
226 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
227 q2 = two31/ad; // initialize q2 = 2p/abs(d)
228 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
231 q1 = 2*q1; // update q1 = 2p/abs(nc)
232 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
233 if (r1 >= anc) { // must be unsigned comparison
237 q2 = 2*q2; // update q2 = 2p/abs(d)
238 r2 = 2*r2; // update r2 = rem(2p/abs(d))
239 if (r2 >= ad) { // must be unsigned comparison
244 } while (q1 < delta || (q1 == delta && r1 == 0));
246 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
247 if (d < 0) mag.m = -mag.m; // resulting magic number
248 mag.s = p - 32; // resulting shift
252 /// magicu - calculate the magic numbers required to codegen an integer udiv as
253 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
254 static mu magicu32(uint32_t d) {
256 uint32_t nc, delta, q1, r1, q2, r2;
258 magu.a = 0; // initialize "add" indicator
260 p = 31; // initialize p
261 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
262 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
263 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
264 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
267 if (r1 >= nc - r1 ) {
268 q1 = 2*q1 + 1; // update q1
269 r1 = 2*r1 - nc; // update r1
272 q1 = 2*q1; // update q1
273 r1 = 2*r1; // update r1
275 if (r2 + 1 >= d - r2) {
276 if (q2 >= 0x7FFFFFFF) magu.a = 1;
277 q2 = 2*q2 + 1; // update q2
278 r2 = 2*r2 + 1 - d; // update r2
281 if (q2 >= 0x80000000) magu.a = 1;
282 q2 = 2*q2; // update q2
283 r2 = 2*r2 + 1; // update r2
286 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
287 magu.m = q2 + 1; // resulting magic number
288 magu.s = p - 32; // resulting shift
292 /// magic - calculate the magic numbers required to codegen an integer sdiv as
293 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
295 static ms magic64(int64_t d) {
297 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
298 const uint64_t two63 = 9223372036854775808ULL; // 2^63
301 ad = d >= 0 ? d : -d;
302 t = two63 + ((uint64_t)d >> 63);
303 anc = t - 1 - t%ad; // absolute value of nc
304 p = 63; // initialize p
305 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
306 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
307 q2 = two63/ad; // initialize q2 = 2p/abs(d)
308 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
311 q1 = 2*q1; // update q1 = 2p/abs(nc)
312 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
313 if (r1 >= anc) { // must be unsigned comparison
317 q2 = 2*q2; // update q2 = 2p/abs(d)
318 r2 = 2*r2; // update r2 = rem(2p/abs(d))
319 if (r2 >= ad) { // must be unsigned comparison
324 } while (q1 < delta || (q1 == delta && r1 == 0));
327 if (d < 0) mag.m = -mag.m; // resulting magic number
328 mag.s = p - 64; // resulting shift
332 /// magicu - calculate the magic numbers required to codegen an integer udiv as
333 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
334 static mu magicu64(uint64_t d)
337 uint64_t nc, delta, q1, r1, q2, r2;
339 magu.a = 0; // initialize "add" indicator
341 p = 63; // initialize p
342 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
343 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
344 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
345 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
348 if (r1 >= nc - r1 ) {
349 q1 = 2*q1 + 1; // update q1
350 r1 = 2*r1 - nc; // update r1
353 q1 = 2*q1; // update q1
354 r1 = 2*r1; // update r1
356 if (r2 + 1 >= d - r2) {
357 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
358 q2 = 2*q2 + 1; // update q2
359 r2 = 2*r2 + 1 - d; // update r2
362 if (q2 >= 0x8000000000000000ull) magu.a = 1;
363 q2 = 2*q2; // update q2
364 r2 = 2*r2 + 1; // update r2
367 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
368 magu.m = q2 + 1; // resulting magic number
369 magu.s = p - 64; // resulting shift
373 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
374 // that selects between the values 1 and 0, making it equivalent to a setcc.
375 // Also, set the incoming LHS, RHS, and CC references to the appropriate
376 // nodes based on the type of node we are checking. This simplifies life a
377 // bit for the callers.
378 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
380 if (N.getOpcode() == ISD::SETCC) {
381 LHS = N.getOperand(0);
382 RHS = N.getOperand(1);
383 CC = N.getOperand(2);
386 if (N.getOpcode() == ISD::SELECT_CC &&
387 N.getOperand(2).getOpcode() == ISD::Constant &&
388 N.getOperand(3).getOpcode() == ISD::Constant &&
389 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
390 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
391 LHS = N.getOperand(0);
392 RHS = N.getOperand(1);
393 CC = N.getOperand(4);
399 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
400 // one use. If this is true, it allows the users to invert the operation for
401 // free when it is profitable to do so.
402 static bool isOneUseSetCC(SDOperand N) {
403 SDOperand N0, N1, N2;
404 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
409 // FIXME: This should probably go in the ISD class rather than being duplicated
411 static bool isCommutativeBinOp(unsigned Opcode) {
417 case ISD::XOR: return true;
418 default: return false; // FIXME: Need commutative info for user ops!
422 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
423 MVT::ValueType VT = N0.getValueType();
424 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
425 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
426 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
427 if (isa<ConstantSDNode>(N1)) {
428 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
429 WorkList.push_back(OpNode.Val);
430 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
431 } else if (N0.hasOneUse()) {
432 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
433 WorkList.push_back(OpNode.Val);
434 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
437 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
438 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
439 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
440 if (isa<ConstantSDNode>(N0)) {
441 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
442 WorkList.push_back(OpNode.Val);
443 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
444 } else if (N1.hasOneUse()) {
445 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
446 WorkList.push_back(OpNode.Val);
447 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
453 void DAGCombiner::Run(bool RunningAfterLegalize) {
454 // set the instance variable, so that the various visit routines may use it.
455 AfterLegalize = RunningAfterLegalize;
457 // Add all the dag nodes to the worklist.
458 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
459 E = DAG.allnodes_end(); I != E; ++I)
460 WorkList.push_back(I);
462 // Create a dummy node (which is not added to allnodes), that adds a reference
463 // to the root node, preventing it from being deleted, and tracking any
464 // changes of the root.
465 HandleSDNode Dummy(DAG.getRoot());
467 // while the worklist isn't empty, inspect the node on the end of it and
468 // try and combine it.
469 while (!WorkList.empty()) {
470 SDNode *N = WorkList.back();
473 // If N has no uses, it is dead. Make sure to revisit all N's operands once
474 // N is deleted from the DAG, since they too may now be dead or may have a
475 // reduced number of uses, allowing other xforms.
476 if (N->use_empty() && N != &Dummy) {
477 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
478 WorkList.push_back(N->getOperand(i).Val);
480 removeFromWorkList(N);
485 SDOperand RV = visit(N);
488 // If we get back the same node we passed in, rather than a new node or
489 // zero, we know that the node must have defined multiple values and
490 // CombineTo was used. Since CombineTo takes care of the worklist
491 // mechanics for us, we have no work to do in this case.
493 DEBUG(std::cerr << "\nReplacing "; N->dump();
494 std::cerr << "\nWith: "; RV.Val->dump();
496 std::vector<SDNode*> NowDead;
497 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
499 // Push the new node and any users onto the worklist
500 WorkList.push_back(RV.Val);
501 AddUsersToWorkList(RV.Val);
503 // Nodes can end up on the worklist more than once. Make sure we do
504 // not process a node that has been replaced.
505 removeFromWorkList(N);
506 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
507 removeFromWorkList(NowDead[i]);
509 // Finally, since the node is now dead, remove it from the graph.
515 // If the root changed (e.g. it was a dead load, update the root).
516 DAG.setRoot(Dummy.getValue());
519 SDOperand DAGCombiner::visit(SDNode *N) {
520 switch(N->getOpcode()) {
522 case ISD::TokenFactor: return visitTokenFactor(N);
523 case ISD::ADD: return visitADD(N);
524 case ISD::SUB: return visitSUB(N);
525 case ISD::MUL: return visitMUL(N);
526 case ISD::SDIV: return visitSDIV(N);
527 case ISD::UDIV: return visitUDIV(N);
528 case ISD::SREM: return visitSREM(N);
529 case ISD::UREM: return visitUREM(N);
530 case ISD::MULHU: return visitMULHU(N);
531 case ISD::MULHS: return visitMULHS(N);
532 case ISD::AND: return visitAND(N);
533 case ISD::OR: return visitOR(N);
534 case ISD::XOR: return visitXOR(N);
535 case ISD::SHL: return visitSHL(N);
536 case ISD::SRA: return visitSRA(N);
537 case ISD::SRL: return visitSRL(N);
538 case ISD::CTLZ: return visitCTLZ(N);
539 case ISD::CTTZ: return visitCTTZ(N);
540 case ISD::CTPOP: return visitCTPOP(N);
541 case ISD::SELECT: return visitSELECT(N);
542 case ISD::SELECT_CC: return visitSELECT_CC(N);
543 case ISD::SETCC: return visitSETCC(N);
544 case ISD::ADD_PARTS: return visitADD_PARTS(N);
545 case ISD::SUB_PARTS: return visitSUB_PARTS(N);
546 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
547 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
548 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
549 case ISD::TRUNCATE: return visitTRUNCATE(N);
550 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
551 case ISD::FADD: return visitFADD(N);
552 case ISD::FSUB: return visitFSUB(N);
553 case ISD::FMUL: return visitFMUL(N);
554 case ISD::FDIV: return visitFDIV(N);
555 case ISD::FREM: return visitFREM(N);
556 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
557 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
558 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
559 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
560 case ISD::FP_ROUND: return visitFP_ROUND(N);
561 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
562 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
563 case ISD::FNEG: return visitFNEG(N);
564 case ISD::FABS: return visitFABS(N);
565 case ISD::BRCOND: return visitBRCOND(N);
566 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
567 case ISD::BR_CC: return visitBR_CC(N);
568 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
569 case ISD::LOAD: return visitLOAD(N);
570 case ISD::STORE: return visitSTORE(N);
571 case ISD::LOCATION: return visitLOCATION(N);
572 case ISD::DEBUG_LOC: return visitDEBUGLOC(N);
577 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
578 std::vector<SDOperand> Ops;
579 bool Changed = false;
581 // If the token factor has two operands and one is the entry token, replace
582 // the token factor with the other operand.
583 if (N->getNumOperands() == 2) {
584 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
585 return N->getOperand(1);
586 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
587 return N->getOperand(0);
590 // fold (tokenfactor (tokenfactor)) -> tokenfactor
591 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
592 SDOperand Op = N->getOperand(i);
593 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
595 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
596 Ops.push_back(Op.getOperand(j));
602 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
606 SDOperand DAGCombiner::visitADD(SDNode *N) {
607 SDOperand N0 = N->getOperand(0);
608 SDOperand N1 = N->getOperand(1);
609 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
610 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
611 MVT::ValueType VT = N0.getValueType();
613 // fold (add c1, c2) -> c1+c2
615 return DAG.getNode(ISD::ADD, VT, N0, N1);
616 // canonicalize constant to RHS
618 return DAG.getNode(ISD::ADD, VT, N1, N0);
619 // fold (add x, 0) -> x
620 if (N1C && N1C->isNullValue())
622 // fold ((c1-A)+c2) -> (c1+c2)-A
623 if (N1C && N0.getOpcode() == ISD::SUB)
624 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
625 return DAG.getNode(ISD::SUB, VT,
626 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
629 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
632 // fold ((0-A) + B) -> B-A
633 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
634 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
635 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
636 // fold (A + (0-B)) -> A-B
637 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
638 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
639 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
640 // fold (A+(B-A)) -> B
641 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
642 return N1.getOperand(0);
646 SDOperand DAGCombiner::visitSUB(SDNode *N) {
647 SDOperand N0 = N->getOperand(0);
648 SDOperand N1 = N->getOperand(1);
649 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
650 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
651 MVT::ValueType VT = N0.getValueType();
653 // fold (sub x, x) -> 0
655 return DAG.getConstant(0, N->getValueType(0));
656 // fold (sub c1, c2) -> c1-c2
658 return DAG.getNode(ISD::SUB, VT, N0, N1);
659 // fold (sub x, c) -> (add x, -c)
661 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
663 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
664 return N0.getOperand(1);
666 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
667 return N0.getOperand(0);
671 SDOperand DAGCombiner::visitMUL(SDNode *N) {
672 SDOperand N0 = N->getOperand(0);
673 SDOperand N1 = N->getOperand(1);
674 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
675 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
676 MVT::ValueType VT = N0.getValueType();
678 // fold (mul c1, c2) -> c1*c2
680 return DAG.getNode(ISD::MUL, VT, N0, N1);
681 // canonicalize constant to RHS
683 return DAG.getNode(ISD::MUL, VT, N1, N0);
684 // fold (mul x, 0) -> 0
685 if (N1C && N1C->isNullValue())
687 // fold (mul x, -1) -> 0-x
688 if (N1C && N1C->isAllOnesValue())
689 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
690 // fold (mul x, (1 << c)) -> x << c
691 if (N1C && isPowerOf2_64(N1C->getValue()))
692 return DAG.getNode(ISD::SHL, VT, N0,
693 DAG.getConstant(Log2_64(N1C->getValue()),
694 TLI.getShiftAmountTy()));
695 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
696 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
697 // FIXME: If the input is something that is easily negated (e.g. a
698 // single-use add), we should put the negate there.
699 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
700 DAG.getNode(ISD::SHL, VT, N0,
701 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
702 TLI.getShiftAmountTy())));
705 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
711 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
712 SDOperand N0 = N->getOperand(0);
713 SDOperand N1 = N->getOperand(1);
714 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
715 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
716 MVT::ValueType VT = N->getValueType(0);
718 // fold (sdiv c1, c2) -> c1/c2
719 if (N0C && N1C && !N1C->isNullValue())
720 return DAG.getNode(ISD::SDIV, VT, N0, N1);
721 // fold (sdiv X, 1) -> X
722 if (N1C && N1C->getSignExtended() == 1LL)
724 // fold (sdiv X, -1) -> 0-X
725 if (N1C && N1C->isAllOnesValue())
726 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
727 // If we know the sign bits of both operands are zero, strength reduce to a
728 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
729 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
730 if (TLI.MaskedValueIsZero(N1, SignBit) &&
731 TLI.MaskedValueIsZero(N0, SignBit))
732 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
733 // fold (sdiv X, pow2) -> (add (sra X, log(pow2)), (srl X, sizeof(X)-1))
734 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
735 (isPowerOf2_64(N1C->getSignExtended()) ||
736 isPowerOf2_64(-N1C->getSignExtended()))) {
737 // If dividing by powers of two is cheap, then don't perform the following
739 if (TLI.isPow2DivCheap())
741 int64_t pow2 = N1C->getSignExtended();
742 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
743 SDOperand SRL = DAG.getNode(ISD::SRL, VT, N0,
744 DAG.getConstant(MVT::getSizeInBits(VT)-1,
745 TLI.getShiftAmountTy()));
746 WorkList.push_back(SRL.Val);
747 SDOperand SGN = DAG.getNode(ISD::ADD, VT, N0, SRL);
748 WorkList.push_back(SGN.Val);
749 SDOperand SRA = DAG.getNode(ISD::SRA, VT, SGN,
750 DAG.getConstant(Log2_64(abs2),
751 TLI.getShiftAmountTy()));
752 // If we're dividing by a positive value, we're done. Otherwise, we must
753 // negate the result.
756 WorkList.push_back(SRA.Val);
757 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
759 // if integer divide is expensive and we satisfy the requirements, emit an
760 // alternate sequence.
761 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
762 !TLI.isIntDivCheap()) {
763 SDOperand Op = BuildSDIV(N);
764 if (Op.Val) return Op;
769 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
770 SDOperand N0 = N->getOperand(0);
771 SDOperand N1 = N->getOperand(1);
772 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
773 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
774 MVT::ValueType VT = N->getValueType(0);
776 // fold (udiv c1, c2) -> c1/c2
777 if (N0C && N1C && !N1C->isNullValue())
778 return DAG.getNode(ISD::UDIV, VT, N0, N1);
779 // fold (udiv x, (1 << c)) -> x >>u c
780 if (N1C && isPowerOf2_64(N1C->getValue()))
781 return DAG.getNode(ISD::SRL, VT, N0,
782 DAG.getConstant(Log2_64(N1C->getValue()),
783 TLI.getShiftAmountTy()));
784 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
785 if (N1.getOpcode() == ISD::SHL) {
786 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
787 if (isPowerOf2_64(SHC->getValue())) {
788 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
789 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
790 DAG.getConstant(Log2_64(SHC->getValue()),
792 WorkList.push_back(Add.Val);
793 return DAG.getNode(ISD::SRL, VT, N0, Add);
797 // fold (udiv x, c) -> alternate
798 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
799 SDOperand Op = BuildUDIV(N);
800 if (Op.Val) return Op;
805 SDOperand DAGCombiner::visitSREM(SDNode *N) {
806 SDOperand N0 = N->getOperand(0);
807 SDOperand N1 = N->getOperand(1);
808 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
809 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
810 MVT::ValueType VT = N->getValueType(0);
812 // fold (srem c1, c2) -> c1%c2
813 if (N0C && N1C && !N1C->isNullValue())
814 return DAG.getNode(ISD::SREM, VT, N0, N1);
815 // If we know the sign bits of both operands are zero, strength reduce to a
816 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
817 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
818 if (TLI.MaskedValueIsZero(N1, SignBit) &&
819 TLI.MaskedValueIsZero(N0, SignBit))
820 return DAG.getNode(ISD::UREM, VT, N0, N1);
824 SDOperand DAGCombiner::visitUREM(SDNode *N) {
825 SDOperand N0 = N->getOperand(0);
826 SDOperand N1 = N->getOperand(1);
827 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
828 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
829 MVT::ValueType VT = N->getValueType(0);
831 // fold (urem c1, c2) -> c1%c2
832 if (N0C && N1C && !N1C->isNullValue())
833 return DAG.getNode(ISD::UREM, VT, N0, N1);
834 // fold (urem x, pow2) -> (and x, pow2-1)
835 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
836 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
837 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
838 if (N1.getOpcode() == ISD::SHL) {
839 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
840 if (isPowerOf2_64(SHC->getValue())) {
841 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1, DAG.getConstant(-1, VT));
842 WorkList.push_back(Add.Val);
843 return DAG.getNode(ISD::AND, VT, N0, Add);
850 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
851 SDOperand N0 = N->getOperand(0);
852 SDOperand N1 = N->getOperand(1);
853 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
855 // fold (mulhs x, 0) -> 0
856 if (N1C && N1C->isNullValue())
858 // fold (mulhs x, 1) -> (sra x, size(x)-1)
859 if (N1C && N1C->getValue() == 1)
860 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
861 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
862 TLI.getShiftAmountTy()));
866 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
867 SDOperand N0 = N->getOperand(0);
868 SDOperand N1 = N->getOperand(1);
869 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
871 // fold (mulhu x, 0) -> 0
872 if (N1C && N1C->isNullValue())
874 // fold (mulhu x, 1) -> 0
875 if (N1C && N1C->getValue() == 1)
876 return DAG.getConstant(0, N0.getValueType());
880 SDOperand DAGCombiner::visitAND(SDNode *N) {
881 SDOperand N0 = N->getOperand(0);
882 SDOperand N1 = N->getOperand(1);
883 SDOperand LL, LR, RL, RR, CC0, CC1, Old, New;
884 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
885 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
886 MVT::ValueType VT = N1.getValueType();
887 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
889 // fold (and c1, c2) -> c1&c2
891 return DAG.getNode(ISD::AND, VT, N0, N1);
892 // canonicalize constant to RHS
894 return DAG.getNode(ISD::AND, VT, N1, N0);
895 // fold (and x, -1) -> x
896 if (N1C && N1C->isAllOnesValue())
898 // if (and x, c) is known to be zero, return 0
899 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
900 return DAG.getConstant(0, VT);
901 // fold (and x, c) -> x iff (x & ~c) == 0
903 TLI.MaskedValueIsZero(N0, ~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
906 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
909 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
910 if (N1C && N0.getOpcode() == ISD::OR)
911 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
912 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
914 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
915 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
916 unsigned InBits = MVT::getSizeInBits(N0.getOperand(0).getValueType());
917 if (TLI.MaskedValueIsZero(N0.getOperand(0),
918 ~N1C->getValue() & ((1ULL << InBits)-1))) {
919 // We actually want to replace all uses of the any_extend with the
920 // zero_extend, to avoid duplicating things. This will later cause this
922 CombineTo(N0.Val, DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
927 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
928 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
929 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
930 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
932 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
933 MVT::isInteger(LL.getValueType())) {
934 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
935 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
936 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
937 WorkList.push_back(ORNode.Val);
938 return DAG.getSetCC(VT, ORNode, LR, Op1);
940 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
941 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
942 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
943 WorkList.push_back(ANDNode.Val);
944 return DAG.getSetCC(VT, ANDNode, LR, Op1);
946 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
947 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
948 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
949 WorkList.push_back(ORNode.Val);
950 return DAG.getSetCC(VT, ORNode, LR, Op1);
953 // canonicalize equivalent to ll == rl
954 if (LL == RR && LR == RL) {
955 Op1 = ISD::getSetCCSwappedOperands(Op1);
958 if (LL == RL && LR == RR) {
959 bool isInteger = MVT::isInteger(LL.getValueType());
960 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
961 if (Result != ISD::SETCC_INVALID)
962 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
965 // fold (and (zext x), (zext y)) -> (zext (and x, y))
966 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
967 N1.getOpcode() == ISD::ZERO_EXTEND &&
968 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
969 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
970 N0.getOperand(0), N1.getOperand(0));
971 WorkList.push_back(ANDNode.Val);
972 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
974 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y))
975 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
976 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
977 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
978 N0.getOperand(1) == N1.getOperand(1)) {
979 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
980 N0.getOperand(0), N1.getOperand(0));
981 WorkList.push_back(ANDNode.Val);
982 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
984 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
985 // fold (and (sra)) -> (and (srl)) when possible.
986 if (TLI.DemandedBitsAreZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits), Old,
988 WorkList.push_back(N);
989 CombineTo(Old.Val, New);
992 // FIXME: DemandedBitsAreZero cannot currently handle AND with non-constant
993 // RHS and propagate known cleared bits to LHS. For this reason, we must keep
994 // this fold, for now, for the following testcase:
996 //int %test2(uint %mode.0.i.0) {
997 // %tmp.79 = cast uint %mode.0.i.0 to int
998 // %tmp.80 = shr int %tmp.79, ubyte 15
999 // %tmp.81 = shr uint %mode.0.i.0, ubyte 16
1000 // %tmp.82 = cast uint %tmp.81 to int
1001 // %tmp.83 = and int %tmp.80, %tmp.82
1004 // fold (and (sra)) -> (and (srl)) when possible.
1005 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) {
1006 if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1007 // If the RHS of the AND has zeros where the sign bits of the SRA will
1008 // land, turn the SRA into an SRL.
1009 if (TLI.MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) &
1010 (~0ULL>>(64-OpSizeInBits)))) {
1011 WorkList.push_back(N);
1012 CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1018 // fold (zext_inreg (extload x)) -> (zextload x)
1019 if (N0.getOpcode() == ISD::EXTLOAD) {
1020 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1021 // If we zero all the possible extended bits, then we can turn this into
1022 // a zextload if we are running before legalize or the operation is legal.
1023 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1024 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1025 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1026 N0.getOperand(1), N0.getOperand(2),
1028 WorkList.push_back(N);
1029 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1033 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1034 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
1035 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1036 // If we zero all the possible extended bits, then we can turn this into
1037 // a zextload if we are running before legalize or the operation is legal.
1038 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1039 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1040 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1041 N0.getOperand(1), N0.getOperand(2),
1043 WorkList.push_back(N);
1044 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1051 SDOperand DAGCombiner::visitOR(SDNode *N) {
1052 SDOperand N0 = N->getOperand(0);
1053 SDOperand N1 = N->getOperand(1);
1054 SDOperand LL, LR, RL, RR, CC0, CC1;
1055 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1056 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1057 MVT::ValueType VT = N1.getValueType();
1058 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1060 // fold (or c1, c2) -> c1|c2
1062 return DAG.getNode(ISD::OR, VT, N0, N1);
1063 // canonicalize constant to RHS
1065 return DAG.getNode(ISD::OR, VT, N1, N0);
1066 // fold (or x, 0) -> x
1067 if (N1C && N1C->isNullValue())
1069 // fold (or x, -1) -> -1
1070 if (N1C && N1C->isAllOnesValue())
1072 // fold (or x, c) -> c iff (x & ~c) == 0
1074 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1077 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1080 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1081 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1082 isa<ConstantSDNode>(N0.getOperand(1))) {
1083 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1084 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1086 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1088 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1089 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1090 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1091 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1093 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1094 MVT::isInteger(LL.getValueType())) {
1095 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1096 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1097 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1098 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1099 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1100 WorkList.push_back(ORNode.Val);
1101 return DAG.getSetCC(VT, ORNode, LR, Op1);
1103 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1104 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1105 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1106 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1107 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1108 WorkList.push_back(ANDNode.Val);
1109 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1112 // canonicalize equivalent to ll == rl
1113 if (LL == RR && LR == RL) {
1114 Op1 = ISD::getSetCCSwappedOperands(Op1);
1117 if (LL == RL && LR == RR) {
1118 bool isInteger = MVT::isInteger(LL.getValueType());
1119 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1120 if (Result != ISD::SETCC_INVALID)
1121 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1124 // fold (or (zext x), (zext y)) -> (zext (or x, y))
1125 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1126 N1.getOpcode() == ISD::ZERO_EXTEND &&
1127 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1128 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1129 N0.getOperand(0), N1.getOperand(0));
1130 WorkList.push_back(ORNode.Val);
1131 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
1133 // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y))
1134 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1135 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1136 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1137 N0.getOperand(1) == N1.getOperand(1)) {
1138 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1139 N0.getOperand(0), N1.getOperand(0));
1140 WorkList.push_back(ORNode.Val);
1141 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1143 // canonicalize shl to left side in a shl/srl pair, to match rotate
1144 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
1146 // check for rotl, rotr
1147 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
1148 N0.getOperand(0) == N1.getOperand(0) &&
1149 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
1150 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1151 if (N0.getOperand(1).getOpcode() == ISD::Constant &&
1152 N1.getOperand(1).getOpcode() == ISD::Constant) {
1153 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1154 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1155 if ((c1val + c2val) == OpSizeInBits)
1156 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1158 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1159 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
1160 N0.getOperand(1) == N1.getOperand(1).getOperand(1))
1161 if (ConstantSDNode *SUBC =
1162 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
1163 if (SUBC->getValue() == OpSizeInBits)
1164 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1165 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1166 if (N0.getOperand(1).getOpcode() == ISD::SUB &&
1167 N1.getOperand(1) == N0.getOperand(1).getOperand(1))
1168 if (ConstantSDNode *SUBC =
1169 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
1170 if (SUBC->getValue() == OpSizeInBits) {
1171 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
1172 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
1175 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
1182 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1183 SDOperand N0 = N->getOperand(0);
1184 SDOperand N1 = N->getOperand(1);
1185 SDOperand LHS, RHS, CC;
1186 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1187 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1188 MVT::ValueType VT = N0.getValueType();
1190 // fold (xor c1, c2) -> c1^c2
1192 return DAG.getNode(ISD::XOR, VT, N0, N1);
1193 // canonicalize constant to RHS
1195 return DAG.getNode(ISD::XOR, VT, N1, N0);
1196 // fold (xor x, 0) -> x
1197 if (N1C && N1C->isNullValue())
1200 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1203 // fold !(x cc y) -> (x !cc y)
1204 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1205 bool isInt = MVT::isInteger(LHS.getValueType());
1206 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1208 if (N0.getOpcode() == ISD::SETCC)
1209 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1210 if (N0.getOpcode() == ISD::SELECT_CC)
1211 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1212 assert(0 && "Unhandled SetCC Equivalent!");
1215 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1216 if (N1C && N1C->getValue() == 1 &&
1217 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1218 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1219 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1220 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1221 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1222 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1223 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1224 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1227 // fold !(x or y) -> (!x and !y) iff x or y are constants
1228 if (N1C && N1C->isAllOnesValue() &&
1229 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1230 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1231 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1232 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1233 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1234 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1235 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1236 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1239 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1240 if (N1C && N0.getOpcode() == ISD::XOR) {
1241 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1242 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1244 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1245 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1247 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1248 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1250 // fold (xor x, x) -> 0
1252 return DAG.getConstant(0, VT);
1253 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
1254 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1255 N1.getOpcode() == ISD::ZERO_EXTEND &&
1256 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1257 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1258 N0.getOperand(0), N1.getOperand(0));
1259 WorkList.push_back(XORNode.Val);
1260 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
1262 // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y))
1263 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1264 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1265 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1266 N0.getOperand(1) == N1.getOperand(1)) {
1267 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1268 N0.getOperand(0), N1.getOperand(0));
1269 WorkList.push_back(XORNode.Val);
1270 return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1));
1275 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1276 SDOperand N0 = N->getOperand(0);
1277 SDOperand N1 = N->getOperand(1);
1278 SDOperand Old = SDOperand();
1279 SDOperand New = SDOperand();
1280 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1281 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1282 MVT::ValueType VT = N0.getValueType();
1283 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1285 // fold (shl c1, c2) -> c1<<c2
1287 return DAG.getNode(ISD::SHL, VT, N0, N1);
1288 // fold (shl 0, x) -> 0
1289 if (N0C && N0C->isNullValue())
1291 // fold (shl x, c >= size(x)) -> undef
1292 if (N1C && N1C->getValue() >= OpSizeInBits)
1293 return DAG.getNode(ISD::UNDEF, VT);
1294 // fold (shl x, 0) -> x
1295 if (N1C && N1C->isNullValue())
1297 // if (shl x, c) is known to be zero, return 0
1298 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1299 return DAG.getConstant(0, VT);
1300 if (N1C && TLI.DemandedBitsAreZero(SDOperand(N,0), ~0ULL >> (64-OpSizeInBits),
1302 WorkList.push_back(N);
1303 CombineTo(Old.Val, New);
1306 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1307 if (N1C && N0.getOpcode() == ISD::SHL &&
1308 N0.getOperand(1).getOpcode() == ISD::Constant) {
1309 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1310 uint64_t c2 = N1C->getValue();
1311 if (c1 + c2 > OpSizeInBits)
1312 return DAG.getConstant(0, VT);
1313 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1314 DAG.getConstant(c1 + c2, N1.getValueType()));
1316 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1317 // (srl (and x, -1 << c1), c1-c2)
1318 if (N1C && N0.getOpcode() == ISD::SRL &&
1319 N0.getOperand(1).getOpcode() == ISD::Constant) {
1320 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1321 uint64_t c2 = N1C->getValue();
1322 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1323 DAG.getConstant(~0ULL << c1, VT));
1325 return DAG.getNode(ISD::SHL, VT, Mask,
1326 DAG.getConstant(c2-c1, N1.getValueType()));
1328 return DAG.getNode(ISD::SRL, VT, Mask,
1329 DAG.getConstant(c1-c2, N1.getValueType()));
1331 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1332 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1333 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1334 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1338 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1339 SDOperand N0 = N->getOperand(0);
1340 SDOperand N1 = N->getOperand(1);
1341 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1342 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1343 MVT::ValueType VT = N0.getValueType();
1344 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1346 // fold (sra c1, c2) -> c1>>c2
1348 return DAG.getNode(ISD::SRA, VT, N0, N1);
1349 // fold (sra 0, x) -> 0
1350 if (N0C && N0C->isNullValue())
1352 // fold (sra -1, x) -> -1
1353 if (N0C && N0C->isAllOnesValue())
1355 // fold (sra x, c >= size(x)) -> undef
1356 if (N1C && N1C->getValue() >= OpSizeInBits)
1357 return DAG.getNode(ISD::UNDEF, VT);
1358 // fold (sra x, 0) -> x
1359 if (N1C && N1C->isNullValue())
1361 // If the sign bit is known to be zero, switch this to a SRL.
1362 if (TLI.MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1))))
1363 return DAG.getNode(ISD::SRL, VT, N0, N1);
1367 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1368 SDOperand N0 = N->getOperand(0);
1369 SDOperand N1 = N->getOperand(1);
1370 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1371 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1372 MVT::ValueType VT = N0.getValueType();
1373 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1375 // fold (srl c1, c2) -> c1 >>u c2
1377 return DAG.getNode(ISD::SRL, VT, N0, N1);
1378 // fold (srl 0, x) -> 0
1379 if (N0C && N0C->isNullValue())
1381 // fold (srl x, c >= size(x)) -> undef
1382 if (N1C && N1C->getValue() >= OpSizeInBits)
1383 return DAG.getNode(ISD::UNDEF, VT);
1384 // fold (srl x, 0) -> x
1385 if (N1C && N1C->isNullValue())
1387 // if (srl x, c) is known to be zero, return 0
1388 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1389 return DAG.getConstant(0, VT);
1390 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1391 if (N1C && N0.getOpcode() == ISD::SRL &&
1392 N0.getOperand(1).getOpcode() == ISD::Constant) {
1393 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1394 uint64_t c2 = N1C->getValue();
1395 if (c1 + c2 > OpSizeInBits)
1396 return DAG.getConstant(0, VT);
1397 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1398 DAG.getConstant(c1 + c2, N1.getValueType()));
1403 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1404 SDOperand N0 = N->getOperand(0);
1405 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1406 MVT::ValueType VT = N->getValueType(0);
1408 // fold (ctlz c1) -> c2
1410 return DAG.getNode(ISD::CTLZ, VT, N0);
1414 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1415 SDOperand N0 = N->getOperand(0);
1416 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1417 MVT::ValueType VT = N->getValueType(0);
1419 // fold (cttz c1) -> c2
1421 return DAG.getNode(ISD::CTTZ, VT, N0);
1425 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1426 SDOperand N0 = N->getOperand(0);
1427 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1428 MVT::ValueType VT = N->getValueType(0);
1430 // fold (ctpop c1) -> c2
1432 return DAG.getNode(ISD::CTPOP, VT, N0);
1436 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1437 SDOperand N0 = N->getOperand(0);
1438 SDOperand N1 = N->getOperand(1);
1439 SDOperand N2 = N->getOperand(2);
1440 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1441 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1442 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1443 MVT::ValueType VT = N->getValueType(0);
1445 // fold select C, X, X -> X
1448 // fold select true, X, Y -> X
1449 if (N0C && !N0C->isNullValue())
1451 // fold select false, X, Y -> Y
1452 if (N0C && N0C->isNullValue())
1454 // fold select C, 1, X -> C | X
1455 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1456 return DAG.getNode(ISD::OR, VT, N0, N2);
1457 // fold select C, 0, X -> ~C & X
1458 // FIXME: this should check for C type == X type, not i1?
1459 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1460 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1461 WorkList.push_back(XORNode.Val);
1462 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1464 // fold select C, X, 1 -> ~C | X
1465 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1466 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1467 WorkList.push_back(XORNode.Val);
1468 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1470 // fold select C, X, 0 -> C & X
1471 // FIXME: this should check for C type == X type, not i1?
1472 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1473 return DAG.getNode(ISD::AND, VT, N0, N1);
1474 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1475 if (MVT::i1 == VT && N0 == N1)
1476 return DAG.getNode(ISD::OR, VT, N0, N2);
1477 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1478 if (MVT::i1 == VT && N0 == N2)
1479 return DAG.getNode(ISD::AND, VT, N0, N1);
1480 // If we can fold this based on the true/false value, do so.
1481 if (SimplifySelectOps(N, N1, N2))
1483 // fold selects based on a setcc into other things, such as min/max/abs
1484 if (N0.getOpcode() == ISD::SETCC)
1486 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1487 // having to say they don't support SELECT_CC on every type the DAG knows
1488 // about, since there is no way to mark an opcode illegal at all value types
1489 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1490 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1491 N1, N2, N0.getOperand(2));
1493 return SimplifySelect(N0, N1, N2);
1497 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1498 SDOperand N0 = N->getOperand(0);
1499 SDOperand N1 = N->getOperand(1);
1500 SDOperand N2 = N->getOperand(2);
1501 SDOperand N3 = N->getOperand(3);
1502 SDOperand N4 = N->getOperand(4);
1503 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1504 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1505 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1506 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1508 // Determine if the condition we're dealing with is constant
1509 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1510 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1512 // fold select_cc lhs, rhs, x, x, cc -> x
1516 // If we can fold this based on the true/false value, do so.
1517 if (SimplifySelectOps(N, N2, N3))
1520 // fold select_cc into other things, such as min/max/abs
1521 return SimplifySelectCC(N0, N1, N2, N3, CC);
1524 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1525 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1526 cast<CondCodeSDNode>(N->getOperand(2))->get());
1529 SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
1530 SDOperand LHSLo = N->getOperand(0);
1531 SDOperand RHSLo = N->getOperand(2);
1532 MVT::ValueType VT = LHSLo.getValueType();
1534 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo)
1535 if (TLI.MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) {
1536 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1538 WorkList.push_back(Hi.Val);
1539 CombineTo(N, RHSLo, Hi);
1542 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo)
1543 if (TLI.MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) {
1544 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1),
1546 WorkList.push_back(Hi.Val);
1547 CombineTo(N, LHSLo, Hi);
1553 SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) {
1554 SDOperand LHSLo = N->getOperand(0);
1555 SDOperand RHSLo = N->getOperand(2);
1556 MVT::ValueType VT = LHSLo.getValueType();
1558 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo)
1559 if (TLI.MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) {
1560 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1),
1562 WorkList.push_back(Hi.Val);
1563 CombineTo(N, LHSLo, Hi);
1569 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1570 SDOperand N0 = N->getOperand(0);
1571 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1572 MVT::ValueType VT = N->getValueType(0);
1574 // fold (sext c1) -> c1
1576 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1577 // fold (sext (sext x)) -> (sext x)
1578 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1579 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1580 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
1581 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1583 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
1584 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1585 DAG.getValueType(N0.getValueType()));
1586 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1587 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1588 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
1589 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1590 N0.getOperand(1), N0.getOperand(2),
1592 CombineTo(N, ExtLoad);
1593 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1594 ExtLoad.getValue(1));
1598 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1599 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1600 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1602 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0),
1603 N0.getOperand(1), N0.getOperand(2),
1605 CombineTo(N, ExtLoad);
1606 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1607 ExtLoad.getValue(1));
1614 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1615 SDOperand N0 = N->getOperand(0);
1616 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1617 MVT::ValueType VT = N->getValueType(0);
1619 // fold (zext c1) -> c1
1621 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1622 // fold (zext (zext x)) -> (zext x)
1623 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1624 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1625 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
1626 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1627 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType())))
1628 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
1629 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1630 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1631 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
1632 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1633 N0.getOperand(1), N0.getOperand(2),
1635 CombineTo(N, ExtLoad);
1636 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1637 ExtLoad.getValue(1));
1641 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1642 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1643 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1645 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1646 N0.getOperand(1), N0.getOperand(2),
1648 CombineTo(N, ExtLoad);
1649 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1650 ExtLoad.getValue(1));
1656 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1657 SDOperand N0 = N->getOperand(0);
1658 SDOperand N1 = N->getOperand(1);
1659 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1660 MVT::ValueType VT = N->getValueType(0);
1661 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1662 unsigned EVTBits = MVT::getSizeInBits(EVT);
1664 // fold (sext_in_reg c1) -> c1
1666 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1667 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1669 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1670 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1671 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1674 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1675 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1676 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1677 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1679 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1680 if (N0.getOpcode() == ISD::AssertSext &&
1681 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1684 // fold (sext_in_reg (sextload x)) -> (sextload x)
1685 if (N0.getOpcode() == ISD::SEXTLOAD &&
1686 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1689 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1690 if (N0.getOpcode() == ISD::SETCC &&
1691 TLI.getSetCCResultContents() ==
1692 TargetLowering::ZeroOrNegativeOneSetCCResult)
1694 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1695 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
1696 return DAG.getZeroExtendInReg(N0, EVT);
1697 // fold (sext_in_reg (srl x)) -> sra x
1698 if (N0.getOpcode() == ISD::SRL &&
1699 N0.getOperand(1).getOpcode() == ISD::Constant &&
1700 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1701 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1704 // fold (sext_inreg (extload x)) -> (sextload x)
1705 if (N0.getOpcode() == ISD::EXTLOAD &&
1706 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1707 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1708 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1709 N0.getOperand(1), N0.getOperand(2),
1711 CombineTo(N, ExtLoad);
1712 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1715 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1716 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
1717 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1718 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1719 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1720 N0.getOperand(1), N0.getOperand(2),
1722 CombineTo(N, ExtLoad);
1723 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1729 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1730 SDOperand N0 = N->getOperand(0);
1731 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1732 MVT::ValueType VT = N->getValueType(0);
1735 if (N0.getValueType() == N->getValueType(0))
1737 // fold (truncate c1) -> c1
1739 return DAG.getNode(ISD::TRUNCATE, VT, N0);
1740 // fold (truncate (truncate x)) -> (truncate x)
1741 if (N0.getOpcode() == ISD::TRUNCATE)
1742 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1743 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1744 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1745 if (N0.getValueType() < VT)
1746 // if the source is smaller than the dest, we still need an extend
1747 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1748 else if (N0.getValueType() > VT)
1749 // if the source is larger than the dest, than we just need the truncate
1750 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1752 // if the source and dest are the same type, we can drop both the extend
1754 return N0.getOperand(0);
1756 // fold (truncate (load x)) -> (smaller load x)
1757 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1758 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1759 "Cannot truncate to larger type!");
1760 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1761 // For big endian targets, we need to add an offset to the pointer to load
1762 // the correct bytes. For little endian systems, we merely need to read
1763 // fewer bytes from the same pointer.
1765 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1766 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1767 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1768 DAG.getConstant(PtrOff, PtrType));
1769 WorkList.push_back(NewPtr.Val);
1770 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1771 WorkList.push_back(N);
1772 CombineTo(N0.Val, Load, Load.getValue(1));
1778 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
1779 SDOperand N0 = N->getOperand(0);
1780 MVT::ValueType VT = N->getValueType(0);
1782 // If the input is a constant, let getNode() fold it.
1783 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
1784 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
1785 if (Res.Val != N) return Res;
1788 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
1789 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
1791 // fold (conv (load x)) -> (load (conv*)x)
1792 // FIXME: These xforms need to know that the resultant load doesn't need a
1793 // higher alignment than the original!
1794 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1795 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
1797 WorkList.push_back(N);
1798 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
1806 SDOperand DAGCombiner::visitFADD(SDNode *N) {
1807 SDOperand N0 = N->getOperand(0);
1808 SDOperand N1 = N->getOperand(1);
1809 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1810 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1811 MVT::ValueType VT = N->getValueType(0);
1813 // fold (fadd c1, c2) -> c1+c2
1815 return DAG.getNode(ISD::FADD, VT, N0, N1);
1816 // canonicalize constant to RHS
1817 if (N0CFP && !N1CFP)
1818 return DAG.getNode(ISD::FADD, VT, N1, N0);
1819 // fold (A + (-B)) -> A-B
1820 if (N1.getOpcode() == ISD::FNEG)
1821 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1822 // fold ((-A) + B) -> B-A
1823 if (N0.getOpcode() == ISD::FNEG)
1824 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1828 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1829 SDOperand N0 = N->getOperand(0);
1830 SDOperand N1 = N->getOperand(1);
1831 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1832 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1833 MVT::ValueType VT = N->getValueType(0);
1835 // fold (fsub c1, c2) -> c1-c2
1837 return DAG.getNode(ISD::FSUB, VT, N0, N1);
1838 // fold (A-(-B)) -> A+B
1839 if (N1.getOpcode() == ISD::FNEG)
1840 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
1844 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1845 SDOperand N0 = N->getOperand(0);
1846 SDOperand N1 = N->getOperand(1);
1847 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1848 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1849 MVT::ValueType VT = N->getValueType(0);
1851 // fold (fmul c1, c2) -> c1*c2
1853 return DAG.getNode(ISD::FMUL, VT, N0, N1);
1854 // canonicalize constant to RHS
1855 if (N0CFP && !N1CFP)
1856 return DAG.getNode(ISD::FMUL, VT, N1, N0);
1857 // fold (fmul X, 2.0) -> (fadd X, X)
1858 if (N1CFP && N1CFP->isExactlyValue(+2.0))
1859 return DAG.getNode(ISD::FADD, VT, N0, N0);
1863 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1864 SDOperand N0 = N->getOperand(0);
1865 SDOperand N1 = N->getOperand(1);
1866 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1867 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1868 MVT::ValueType VT = N->getValueType(0);
1870 // fold (fdiv c1, c2) -> c1/c2
1872 return DAG.getNode(ISD::FDIV, VT, N0, N1);
1876 SDOperand DAGCombiner::visitFREM(SDNode *N) {
1877 SDOperand N0 = N->getOperand(0);
1878 SDOperand N1 = N->getOperand(1);
1879 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1880 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1881 MVT::ValueType VT = N->getValueType(0);
1883 // fold (frem c1, c2) -> fmod(c1,c2)
1885 return DAG.getNode(ISD::FREM, VT, N0, N1);
1890 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1891 SDOperand N0 = N->getOperand(0);
1892 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1893 MVT::ValueType VT = N->getValueType(0);
1895 // fold (sint_to_fp c1) -> c1fp
1897 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
1901 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1902 SDOperand N0 = N->getOperand(0);
1903 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1904 MVT::ValueType VT = N->getValueType(0);
1906 // fold (uint_to_fp c1) -> c1fp
1908 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
1912 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1913 SDOperand N0 = N->getOperand(0);
1914 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1915 MVT::ValueType VT = N->getValueType(0);
1917 // fold (fp_to_sint c1fp) -> c1
1919 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
1923 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1924 SDOperand N0 = N->getOperand(0);
1925 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1926 MVT::ValueType VT = N->getValueType(0);
1928 // fold (fp_to_uint c1fp) -> c1
1930 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
1934 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1935 SDOperand N0 = N->getOperand(0);
1936 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1937 MVT::ValueType VT = N->getValueType(0);
1939 // fold (fp_round c1fp) -> c1fp
1941 return DAG.getNode(ISD::FP_ROUND, VT, N0);
1945 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1946 SDOperand N0 = N->getOperand(0);
1947 MVT::ValueType VT = N->getValueType(0);
1948 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1949 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1951 // fold (fp_round_inreg c1fp) -> c1fp
1953 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1954 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1959 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1960 SDOperand N0 = N->getOperand(0);
1961 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1962 MVT::ValueType VT = N->getValueType(0);
1964 // fold (fp_extend c1fp) -> c1fp
1966 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
1970 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1971 SDOperand N0 = N->getOperand(0);
1972 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1973 MVT::ValueType VT = N->getValueType(0);
1975 // fold (fneg c1) -> -c1
1977 return DAG.getNode(ISD::FNEG, VT, N0);
1978 // fold (fneg (sub x, y)) -> (sub y, x)
1979 if (N->getOperand(0).getOpcode() == ISD::SUB)
1980 return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0));
1981 // fold (fneg (fneg x)) -> x
1982 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1983 return N->getOperand(0).getOperand(0);
1987 SDOperand DAGCombiner::visitFABS(SDNode *N) {
1988 SDOperand N0 = N->getOperand(0);
1989 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1990 MVT::ValueType VT = N->getValueType(0);
1992 // fold (fabs c1) -> fabs(c1)
1994 return DAG.getNode(ISD::FABS, VT, N0);
1995 // fold (fabs (fabs x)) -> (fabs x)
1996 if (N->getOperand(0).getOpcode() == ISD::FABS)
1997 return N->getOperand(0);
1998 // fold (fabs (fneg x)) -> (fabs x)
1999 if (N->getOperand(0).getOpcode() == ISD::FNEG)
2000 return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0));
2004 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2005 SDOperand Chain = N->getOperand(0);
2006 SDOperand N1 = N->getOperand(1);
2007 SDOperand N2 = N->getOperand(2);
2008 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2010 // never taken branch, fold to chain
2011 if (N1C && N1C->isNullValue())
2013 // unconditional branch
2014 if (N1C && N1C->getValue() == 1)
2015 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2016 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2018 if (N1.getOpcode() == ISD::SETCC &&
2019 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2020 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2021 N1.getOperand(0), N1.getOperand(1), N2);
2026 SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
2027 SDOperand Chain = N->getOperand(0);
2028 SDOperand N1 = N->getOperand(1);
2029 SDOperand N2 = N->getOperand(2);
2030 SDOperand N3 = N->getOperand(3);
2031 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2033 // unconditional branch to true mbb
2034 if (N1C && N1C->getValue() == 1)
2035 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2036 // unconditional branch to false mbb
2037 if (N1C && N1C->isNullValue())
2038 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
2039 // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if
2040 // BRTWOWAY_CC is legal on the target.
2041 if (N1.getOpcode() == ISD::SETCC &&
2042 TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
2043 std::vector<SDOperand> Ops;
2044 Ops.push_back(Chain);
2045 Ops.push_back(N1.getOperand(2));
2046 Ops.push_back(N1.getOperand(0));
2047 Ops.push_back(N1.getOperand(1));
2050 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
2055 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2057 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2058 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2059 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2061 // Use SimplifySetCC to simplify SETCC's.
2062 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2063 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2065 // fold br_cc true, dest -> br dest (unconditional branch)
2066 if (SCCC && SCCC->getValue())
2067 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2069 // fold br_cc false, dest -> unconditional fall through
2070 if (SCCC && SCCC->isNullValue())
2071 return N->getOperand(0);
2072 // fold to a simpler setcc
2073 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2074 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2075 Simp.getOperand(2), Simp.getOperand(0),
2076 Simp.getOperand(1), N->getOperand(4));
2080 SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
2081 SDOperand Chain = N->getOperand(0);
2082 SDOperand CCN = N->getOperand(1);
2083 SDOperand LHS = N->getOperand(2);
2084 SDOperand RHS = N->getOperand(3);
2085 SDOperand N4 = N->getOperand(4);
2086 SDOperand N5 = N->getOperand(5);
2088 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
2089 cast<CondCodeSDNode>(CCN)->get(), false);
2090 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2092 // fold select_cc lhs, rhs, x, x, cc -> x
2094 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2095 // fold select_cc true, x, y -> x
2096 if (SCCC && SCCC->getValue())
2097 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2098 // fold select_cc false, x, y -> y
2099 if (SCCC && SCCC->isNullValue())
2100 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
2101 // fold to a simpler setcc
2102 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) {
2103 std::vector<SDOperand> Ops;
2104 Ops.push_back(Chain);
2105 Ops.push_back(SCC.getOperand(2));
2106 Ops.push_back(SCC.getOperand(0));
2107 Ops.push_back(SCC.getOperand(1));
2110 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
2115 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2116 SDOperand Chain = N->getOperand(0);
2117 SDOperand Ptr = N->getOperand(1);
2118 SDOperand SrcValue = N->getOperand(2);
2120 // If this load is directly stored, replace the load value with the stored
2122 // TODO: Handle store large -> read small portion.
2123 // TODO: Handle TRUNCSTORE/EXTLOAD
2124 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2125 Chain.getOperand(1).getValueType() == N->getValueType(0))
2126 return CombineTo(N, Chain.getOperand(1), Chain);
2131 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2132 SDOperand Chain = N->getOperand(0);
2133 SDOperand Value = N->getOperand(1);
2134 SDOperand Ptr = N->getOperand(2);
2135 SDOperand SrcValue = N->getOperand(3);
2137 // If this is a store that kills a previous store, remove the previous store.
2138 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2139 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2140 // Make sure that these stores are the same value type:
2141 // FIXME: we really care that the second store is >= size of the first.
2142 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2143 // Create a new store of Value that replaces both stores.
2144 SDNode *PrevStore = Chain.Val;
2145 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2147 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
2148 PrevStore->getOperand(0), Value, Ptr,
2150 CombineTo(N, NewStore); // Nuke this store.
2151 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2152 return SDOperand(N, 0);
2155 // If this is a store of a bit convert, store the input value.
2156 // FIXME: This needs to know that the resultant store does not need a
2157 // higher alignment than the original.
2158 if (0 && Value.getOpcode() == ISD::BIT_CONVERT)
2159 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
2165 SDOperand DAGCombiner::visitLOCATION(SDNode *N) {
2166 SDOperand Chain = N->getOperand(0);
2168 // Remove redundant locations (last one holds)
2169 if (Chain.getOpcode() == ISD::LOCATION && Chain.hasOneUse()) {
2170 return DAG.getNode(ISD::LOCATION, MVT::Other, Chain.getOperand(0),
2180 SDOperand DAGCombiner::visitDEBUGLOC(SDNode *N) {
2181 SDOperand Chain = N->getOperand(0);
2183 // Remove redundant debug locations (last one holds)
2184 if (Chain.getOpcode() == ISD::DEBUG_LOC && Chain.hasOneUse()) {
2185 return DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Chain.getOperand(0),
2194 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
2195 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
2197 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
2198 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2199 // If we got a simplified select_cc node back from SimplifySelectCC, then
2200 // break it down into a new SETCC node, and a new SELECT node, and then return
2201 // the SELECT node, since we were called with a SELECT node.
2203 // Check to see if we got a select_cc back (to turn into setcc/select).
2204 // Otherwise, just return whatever node we got back, like fabs.
2205 if (SCC.getOpcode() == ISD::SELECT_CC) {
2206 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
2207 SCC.getOperand(0), SCC.getOperand(1),
2209 WorkList.push_back(SETCC.Val);
2210 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
2211 SCC.getOperand(3), SETCC);
2218 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
2219 /// are the two values being selected between, see if we can simplify the
2222 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
2225 // If this is a select from two identical things, try to pull the operation
2226 // through the select.
2227 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
2229 std::cerr << "SELECT: ["; LHS.Val->dump();
2230 std::cerr << "] ["; RHS.Val->dump();
2234 // If this is a load and the token chain is identical, replace the select
2235 // of two loads with a load through a select of the address to load from.
2236 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
2237 // constants have been dropped into the constant pool.
2238 if ((LHS.getOpcode() == ISD::LOAD ||
2239 LHS.getOpcode() == ISD::EXTLOAD ||
2240 LHS.getOpcode() == ISD::ZEXTLOAD ||
2241 LHS.getOpcode() == ISD::SEXTLOAD) &&
2242 // Token chains must be identical.
2243 LHS.getOperand(0) == RHS.getOperand(0) &&
2244 // If this is an EXTLOAD, the VT's must match.
2245 (LHS.getOpcode() == ISD::LOAD ||
2246 LHS.getOperand(3) == RHS.getOperand(3))) {
2247 // FIXME: this conflates two src values, discarding one. This is not
2248 // the right thing to do, but nothing uses srcvalues now. When they do,
2249 // turn SrcValue into a list of locations.
2251 if (TheSelect->getOpcode() == ISD::SELECT)
2252 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
2253 TheSelect->getOperand(0), LHS.getOperand(1),
2256 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
2257 TheSelect->getOperand(0),
2258 TheSelect->getOperand(1),
2259 LHS.getOperand(1), RHS.getOperand(1),
2260 TheSelect->getOperand(4));
2263 if (LHS.getOpcode() == ISD::LOAD)
2264 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
2265 Addr, LHS.getOperand(2));
2267 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
2268 LHS.getOperand(0), Addr, LHS.getOperand(2),
2269 cast<VTSDNode>(LHS.getOperand(3))->getVT());
2270 // Users of the select now use the result of the load.
2271 CombineTo(TheSelect, Load);
2273 // Users of the old loads now use the new load's chain. We know the
2274 // old-load value is dead now.
2275 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
2276 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
2284 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
2285 SDOperand N2, SDOperand N3,
2288 MVT::ValueType VT = N2.getValueType();
2289 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
2290 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
2291 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
2292 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
2294 // Determine if the condition we're dealing with is constant
2295 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2296 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2298 // fold select_cc true, x, y -> x
2299 if (SCCC && SCCC->getValue())
2301 // fold select_cc false, x, y -> y
2302 if (SCCC && SCCC->getValue() == 0)
2305 // Check to see if we can simplify the select into an fabs node
2306 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
2307 // Allow either -0.0 or 0.0
2308 if (CFP->getValue() == 0.0) {
2309 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
2310 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
2311 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
2312 N2 == N3.getOperand(0))
2313 return DAG.getNode(ISD::FABS, VT, N0);
2315 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
2316 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
2317 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
2318 N2.getOperand(0) == N3)
2319 return DAG.getNode(ISD::FABS, VT, N3);
2323 // Check to see if we can perform the "gzip trick", transforming
2324 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
2325 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
2326 MVT::isInteger(N0.getValueType()) &&
2327 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
2328 MVT::ValueType XType = N0.getValueType();
2329 MVT::ValueType AType = N2.getValueType();
2330 if (XType >= AType) {
2331 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
2332 // single-bit constant.
2333 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
2334 unsigned ShCtV = Log2_64(N2C->getValue());
2335 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
2336 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
2337 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
2338 WorkList.push_back(Shift.Val);
2339 if (XType > AType) {
2340 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2341 WorkList.push_back(Shift.Val);
2343 return DAG.getNode(ISD::AND, AType, Shift, N2);
2345 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2346 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2347 TLI.getShiftAmountTy()));
2348 WorkList.push_back(Shift.Val);
2349 if (XType > AType) {
2350 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2351 WorkList.push_back(Shift.Val);
2353 return DAG.getNode(ISD::AND, AType, Shift, N2);
2357 // fold select C, 16, 0 -> shl C, 4
2358 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
2359 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
2360 // Get a SetCC of the condition
2361 // FIXME: Should probably make sure that setcc is legal if we ever have a
2362 // target where it isn't.
2363 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2364 WorkList.push_back(SCC.Val);
2365 // cast from setcc result type to select result type
2367 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
2369 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
2370 WorkList.push_back(Temp.Val);
2371 // shl setcc result by log2 n2c
2372 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
2373 DAG.getConstant(Log2_64(N2C->getValue()),
2374 TLI.getShiftAmountTy()));
2377 // Check to see if this is the equivalent of setcc
2378 // FIXME: Turn all of these into setcc if setcc if setcc is legal
2379 // otherwise, go ahead with the folds.
2380 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
2381 MVT::ValueType XType = N0.getValueType();
2382 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
2383 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2384 if (Res.getValueType() != VT)
2385 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
2389 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
2390 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
2391 TLI.isOperationLegal(ISD::CTLZ, XType)) {
2392 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
2393 return DAG.getNode(ISD::SRL, XType, Ctlz,
2394 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
2395 TLI.getShiftAmountTy()));
2397 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
2398 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
2399 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
2401 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
2402 DAG.getConstant(~0ULL, XType));
2403 return DAG.getNode(ISD::SRL, XType,
2404 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
2405 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2406 TLI.getShiftAmountTy()));
2408 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
2409 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
2410 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
2411 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2412 TLI.getShiftAmountTy()));
2413 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
2417 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
2418 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2419 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
2420 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
2421 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
2422 MVT::ValueType XType = N0.getValueType();
2423 if (SubC->isNullValue() && MVT::isInteger(XType)) {
2424 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2425 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2426 TLI.getShiftAmountTy()));
2427 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
2428 WorkList.push_back(Shift.Val);
2429 WorkList.push_back(Add.Val);
2430 return DAG.getNode(ISD::XOR, XType, Add, Shift);
2438 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
2439 SDOperand N1, ISD::CondCode Cond,
2440 bool foldBooleans) {
2441 // These setcc operations always fold.
2445 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
2447 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
2450 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
2451 uint64_t C1 = N1C->getValue();
2452 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
2453 uint64_t C0 = N0C->getValue();
2455 // Sign extend the operands if required
2456 if (ISD::isSignedIntSetCC(Cond)) {
2457 C0 = N0C->getSignExtended();
2458 C1 = N1C->getSignExtended();
2462 default: assert(0 && "Unknown integer setcc!");
2463 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2464 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2465 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
2466 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
2467 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
2468 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
2469 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
2470 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
2471 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
2472 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
2475 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2476 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2477 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
2479 // If the comparison constant has bits in the upper part, the
2480 // zero-extended value could never match.
2481 if (C1 & (~0ULL << InSize)) {
2482 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
2486 case ISD::SETEQ: return DAG.getConstant(0, VT);
2489 case ISD::SETNE: return DAG.getConstant(1, VT);
2492 // True if the sign bit of C1 is set.
2493 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
2496 // True if the sign bit of C1 isn't set.
2497 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
2503 // Otherwise, we can perform the comparison with the low bits.
2511 return DAG.getSetCC(VT, N0.getOperand(0),
2512 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
2515 break; // todo, be more careful with signed comparisons
2517 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2518 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2519 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2520 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
2521 MVT::ValueType ExtDstTy = N0.getValueType();
2522 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
2524 // If the extended part has any inconsistent bits, it cannot ever
2525 // compare equal. In other words, they have to be all ones or all
2528 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
2529 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
2530 return DAG.getConstant(Cond == ISD::SETNE, VT);
2533 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
2534 if (Op0Ty == ExtSrcTy) {
2535 ZextOp = N0.getOperand(0);
2537 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
2538 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
2539 DAG.getConstant(Imm, Op0Ty));
2541 WorkList.push_back(ZextOp.Val);
2542 // Otherwise, make this a use of a zext.
2543 return DAG.getSetCC(VT, ZextOp,
2544 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
2549 uint64_t MinVal, MaxVal;
2550 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
2551 if (ISD::isSignedIntSetCC(Cond)) {
2552 MinVal = 1ULL << (OperandBitSize-1);
2553 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
2554 MaxVal = ~0ULL >> (65-OperandBitSize);
2559 MaxVal = ~0ULL >> (64-OperandBitSize);
2562 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2563 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2564 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2565 --C1; // X >= C0 --> X > (C0-1)
2566 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2567 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2570 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2571 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2572 ++C1; // X <= C0 --> X < (C0+1)
2573 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2574 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2577 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2578 return DAG.getConstant(0, VT); // X < MIN --> false
2580 // Canonicalize setgt X, Min --> setne X, Min
2581 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2582 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2583 // Canonicalize setlt X, Max --> setne X, Max
2584 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2585 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2587 // If we have setult X, 1, turn it into seteq X, 0
2588 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2589 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
2591 // If we have setugt X, Max-1, turn it into seteq X, Max
2592 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2593 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
2596 // If we have "setcc X, C0", check to see if we can shrink the immediate
2599 // SETUGT X, SINTMAX -> SETLT X, 0
2600 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
2601 C1 == (~0ULL >> (65-OperandBitSize)))
2602 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
2605 // FIXME: Implement the rest of these.
2607 // Fold bit comparisons when we can.
2608 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2609 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
2610 if (ConstantSDNode *AndRHS =
2611 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2612 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2613 // Perform the xform if the AND RHS is a single bit.
2614 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
2615 return DAG.getNode(ISD::SRL, VT, N0,
2616 DAG.getConstant(Log2_64(AndRHS->getValue()),
2617 TLI.getShiftAmountTy()));
2619 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
2620 // (X & 8) == 8 --> (X & 8) >> 3
2621 // Perform the xform if C1 is a single bit.
2622 if ((C1 & (C1-1)) == 0) {
2623 return DAG.getNode(ISD::SRL, VT, N0,
2624 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
2629 } else if (isa<ConstantSDNode>(N0.Val)) {
2630 // Ensure that the constant occurs on the RHS.
2631 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2634 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
2635 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
2636 double C0 = N0C->getValue(), C1 = N1C->getValue();
2639 default: break; // FIXME: Implement the rest of these!
2640 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2641 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2642 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
2643 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
2644 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
2645 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
2648 // Ensure that the constant occurs on the RHS.
2649 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2653 // We can always fold X == Y for integer setcc's.
2654 if (MVT::isInteger(N0.getValueType()))
2655 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2656 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2657 if (UOF == 2) // FP operators that are undefined on NaNs.
2658 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2659 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2660 return DAG.getConstant(UOF, VT);
2661 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2662 // if it is not already.
2663 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2664 if (NewCond != Cond)
2665 return DAG.getSetCC(VT, N0, N1, NewCond);
2668 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2669 MVT::isInteger(N0.getValueType())) {
2670 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2671 N0.getOpcode() == ISD::XOR) {
2672 // Simplify (X+Y) == (X+Z) --> Y == Z
2673 if (N0.getOpcode() == N1.getOpcode()) {
2674 if (N0.getOperand(0) == N1.getOperand(0))
2675 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2676 if (N0.getOperand(1) == N1.getOperand(1))
2677 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2678 if (isCommutativeBinOp(N0.getOpcode())) {
2679 // If X op Y == Y op X, try other combinations.
2680 if (N0.getOperand(0) == N1.getOperand(1))
2681 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2682 if (N0.getOperand(1) == N1.getOperand(0))
2683 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
2687 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2688 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2689 // Turn (X+C1) == C2 --> X == C2-C1
2690 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
2691 return DAG.getSetCC(VT, N0.getOperand(0),
2692 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
2693 N0.getValueType()), Cond);
2696 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2697 if (N0.getOpcode() == ISD::XOR)
2698 // If we know that all of the inverted bits are zero, don't bother
2699 // performing the inversion.
2700 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
2701 return DAG.getSetCC(VT, N0.getOperand(0),
2702 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
2703 N0.getValueType()), Cond);
2706 // Turn (C1-X) == C2 --> X == C1-C2
2707 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2708 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
2709 return DAG.getSetCC(VT, N0.getOperand(1),
2710 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
2711 N0.getValueType()), Cond);
2716 // Simplify (X+Z) == X --> Z == 0
2717 if (N0.getOperand(0) == N1)
2718 return DAG.getSetCC(VT, N0.getOperand(1),
2719 DAG.getConstant(0, N0.getValueType()), Cond);
2720 if (N0.getOperand(1) == N1) {
2721 if (isCommutativeBinOp(N0.getOpcode()))
2722 return DAG.getSetCC(VT, N0.getOperand(0),
2723 DAG.getConstant(0, N0.getValueType()), Cond);
2725 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2726 // (Z-X) == X --> Z == X<<1
2727 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2729 DAG.getConstant(1,TLI.getShiftAmountTy()));
2730 WorkList.push_back(SH.Val);
2731 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2736 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2737 N1.getOpcode() == ISD::XOR) {
2738 // Simplify X == (X+Z) --> Z == 0
2739 if (N1.getOperand(0) == N0) {
2740 return DAG.getSetCC(VT, N1.getOperand(1),
2741 DAG.getConstant(0, N1.getValueType()), Cond);
2742 } else if (N1.getOperand(1) == N0) {
2743 if (isCommutativeBinOp(N1.getOpcode())) {
2744 return DAG.getSetCC(VT, N1.getOperand(0),
2745 DAG.getConstant(0, N1.getValueType()), Cond);
2747 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2748 // X == (Z-X) --> X<<1 == Z
2749 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2750 DAG.getConstant(1,TLI.getShiftAmountTy()));
2751 WorkList.push_back(SH.Val);
2752 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2758 // Fold away ALL boolean setcc's.
2760 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2762 default: assert(0 && "Unknown integer setcc!");
2763 case ISD::SETEQ: // X == Y -> (X^Y)^1
2764 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2765 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2766 WorkList.push_back(Temp.Val);
2768 case ISD::SETNE: // X != Y --> (X^Y)
2769 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2771 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
2772 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
2773 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2774 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2775 WorkList.push_back(Temp.Val);
2777 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
2778 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
2779 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2780 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2781 WorkList.push_back(Temp.Val);
2783 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
2784 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
2785 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2786 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2787 WorkList.push_back(Temp.Val);
2789 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
2790 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
2791 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2792 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2795 if (VT != MVT::i1) {
2796 WorkList.push_back(N0.Val);
2797 // FIXME: If running after legalize, we probably can't do this.
2798 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2803 // Could not fold it.
2807 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2808 /// return a DAG expression to select that will generate the same value by
2809 /// multiplying by a magic number. See:
2810 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2811 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
2812 MVT::ValueType VT = N->getValueType(0);
2814 // Check to see if we can do this.
2815 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2816 return SDOperand(); // BuildSDIV only operates on i32 or i64
2817 if (!TLI.isOperationLegal(ISD::MULHS, VT))
2818 return SDOperand(); // Make sure the target supports MULHS.
2820 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
2821 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
2823 // Multiply the numerator (operand 0) by the magic value
2824 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
2825 DAG.getConstant(magics.m, VT));
2826 // If d > 0 and m < 0, add the numerator
2827 if (d > 0 && magics.m < 0) {
2828 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
2829 WorkList.push_back(Q.Val);
2831 // If d < 0 and m > 0, subtract the numerator.
2832 if (d < 0 && magics.m > 0) {
2833 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
2834 WorkList.push_back(Q.Val);
2836 // Shift right algebraic if shift value is nonzero
2838 Q = DAG.getNode(ISD::SRA, VT, Q,
2839 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2840 WorkList.push_back(Q.Val);
2842 // Extract the sign bit and add it to the quotient
2844 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
2845 TLI.getShiftAmountTy()));
2846 WorkList.push_back(T.Val);
2847 return DAG.getNode(ISD::ADD, VT, Q, T);
2850 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2851 /// return a DAG expression to select that will generate the same value by
2852 /// multiplying by a magic number. See:
2853 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2854 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
2855 MVT::ValueType VT = N->getValueType(0);
2857 // Check to see if we can do this.
2858 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2859 return SDOperand(); // BuildUDIV only operates on i32 or i64
2860 if (!TLI.isOperationLegal(ISD::MULHU, VT))
2861 return SDOperand(); // Make sure the target supports MULHU.
2863 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
2864 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
2866 // Multiply the numerator (operand 0) by the magic value
2867 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
2868 DAG.getConstant(magics.m, VT));
2869 WorkList.push_back(Q.Val);
2871 if (magics.a == 0) {
2872 return DAG.getNode(ISD::SRL, VT, Q,
2873 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2875 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
2876 WorkList.push_back(NPQ.Val);
2877 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
2878 DAG.getConstant(1, TLI.getShiftAmountTy()));
2879 WorkList.push_back(NPQ.Val);
2880 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
2881 WorkList.push_back(NPQ.Val);
2882 return DAG.getNode(ISD::SRL, VT, NPQ,
2883 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
2887 // SelectionDAG::Combine - This is the entry point for the file.
2889 void SelectionDAG::Combine(bool RunningAfterLegalize) {
2890 /// run - This is the main entry point to this class.
2892 DAGCombiner(*this).Run(RunningAfterLegalize);