1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "dagcombine"
16 #include "llvm/CodeGen/SelectionDAG.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/Analysis/AliasAnalysis.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetFrameInfo.h"
24 #include "llvm/Target/TargetLowering.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/ADT/SmallPtrSet.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
37 STATISTIC(NodesCombined , "Number of dag nodes combined");
38 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
39 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
43 CombinerAA("combiner-alias-analysis", cl::Hidden,
44 cl::desc("Turn on alias analysis during testing"));
47 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
48 cl::desc("Include global information in alias analysis"));
50 //------------------------------ DAGCombiner ---------------------------------//
52 class VISIBILITY_HIDDEN DAGCombiner {
54 const TargetLowering &TLI;
60 // Worklist of all of the nodes that need to be simplified.
61 std::vector<SDNode*> WorkList;
63 // AA - Used for DAG load/store alias analysis.
66 /// AddUsersToWorkList - When an instruction is simplified, add all users of
67 /// the instruction to the work lists because they might get more simplified
70 void AddUsersToWorkList(SDNode *N) {
71 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
76 /// visit - call the node-specific routine that knows how to fold each
77 /// particular type of node.
78 SDValue visit(SDNode *N);
81 /// AddToWorkList - Add to the work list making sure it's instance is at the
82 /// the back (next to be processed.)
83 void AddToWorkList(SDNode *N) {
84 removeFromWorkList(N);
85 WorkList.push_back(N);
88 /// removeFromWorkList - remove all instances of N from the worklist.
90 void removeFromWorkList(SDNode *N) {
91 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
95 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
98 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
99 return CombineTo(N, &Res, 1, AddTo);
102 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
104 SDValue To[] = { Res0, Res1 };
105 return CombineTo(N, To, 2, AddTo);
108 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
112 /// SimplifyDemandedBits - Check the specified integer node value to see if
113 /// it can be simplified or if things it uses can be simplified by bit
114 /// propagation. If so, return true.
115 bool SimplifyDemandedBits(SDValue Op) {
116 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits());
117 return SimplifyDemandedBits(Op, Demanded);
120 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
122 bool CombineToPreIndexedLoadStore(SDNode *N);
123 bool CombineToPostIndexedLoadStore(SDNode *N);
126 /// combine - call the node-specific routine that knows how to fold each
127 /// particular type of node. If that doesn't do anything, try the
128 /// target-specific DAG combines.
129 SDValue combine(SDNode *N);
131 // Visitation implementation - Implement dag node combining for different
132 // node types. The semantics are as follows:
134 // SDValue.getNode() == 0 - No change was made
135 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
136 // otherwise - N should be replaced by the returned Operand.
138 SDValue visitTokenFactor(SDNode *N);
139 SDValue visitMERGE_VALUES(SDNode *N);
140 SDValue visitADD(SDNode *N);
141 SDValue visitSUB(SDNode *N);
142 SDValue visitADDC(SDNode *N);
143 SDValue visitADDE(SDNode *N);
144 SDValue visitMUL(SDNode *N);
145 SDValue visitSDIV(SDNode *N);
146 SDValue visitUDIV(SDNode *N);
147 SDValue visitSREM(SDNode *N);
148 SDValue visitUREM(SDNode *N);
149 SDValue visitMULHU(SDNode *N);
150 SDValue visitMULHS(SDNode *N);
151 SDValue visitSMUL_LOHI(SDNode *N);
152 SDValue visitUMUL_LOHI(SDNode *N);
153 SDValue visitSDIVREM(SDNode *N);
154 SDValue visitUDIVREM(SDNode *N);
155 SDValue visitAND(SDNode *N);
156 SDValue visitOR(SDNode *N);
157 SDValue visitXOR(SDNode *N);
158 SDValue SimplifyVBinOp(SDNode *N);
159 SDValue visitSHL(SDNode *N);
160 SDValue visitSRA(SDNode *N);
161 SDValue visitSRL(SDNode *N);
162 SDValue visitCTLZ(SDNode *N);
163 SDValue visitCTTZ(SDNode *N);
164 SDValue visitCTPOP(SDNode *N);
165 SDValue visitSELECT(SDNode *N);
166 SDValue visitSELECT_CC(SDNode *N);
167 SDValue visitSETCC(SDNode *N);
168 SDValue visitSIGN_EXTEND(SDNode *N);
169 SDValue visitZERO_EXTEND(SDNode *N);
170 SDValue visitANY_EXTEND(SDNode *N);
171 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
172 SDValue visitTRUNCATE(SDNode *N);
173 SDValue visitBIT_CONVERT(SDNode *N);
174 SDValue visitBUILD_PAIR(SDNode *N);
175 SDValue visitFADD(SDNode *N);
176 SDValue visitFSUB(SDNode *N);
177 SDValue visitFMUL(SDNode *N);
178 SDValue visitFDIV(SDNode *N);
179 SDValue visitFREM(SDNode *N);
180 SDValue visitFCOPYSIGN(SDNode *N);
181 SDValue visitSINT_TO_FP(SDNode *N);
182 SDValue visitUINT_TO_FP(SDNode *N);
183 SDValue visitFP_TO_SINT(SDNode *N);
184 SDValue visitFP_TO_UINT(SDNode *N);
185 SDValue visitFP_ROUND(SDNode *N);
186 SDValue visitFP_ROUND_INREG(SDNode *N);
187 SDValue visitFP_EXTEND(SDNode *N);
188 SDValue visitFNEG(SDNode *N);
189 SDValue visitFABS(SDNode *N);
190 SDValue visitBRCOND(SDNode *N);
191 SDValue visitBR_CC(SDNode *N);
192 SDValue visitLOAD(SDNode *N);
193 SDValue visitSTORE(SDNode *N);
194 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
195 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
196 SDValue visitBUILD_VECTOR(SDNode *N);
197 SDValue visitCONCAT_VECTORS(SDNode *N);
198 SDValue visitVECTOR_SHUFFLE(SDNode *N);
200 SDValue XformToShuffleWithZero(SDNode *N);
201 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
203 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
205 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
206 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
207 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
208 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
209 SDValue N3, ISD::CondCode CC,
210 bool NotExtCompare = false);
211 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
212 DebugLoc DL, bool foldBooleans = true);
213 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
215 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
216 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
217 SDValue BuildSDIV(SDNode *N);
218 SDValue BuildUDIV(SDNode *N);
219 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
220 SDValue ReduceLoadWidth(SDNode *N);
222 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
224 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
225 /// looking for aliasing nodes and adding them to the Aliases vector.
226 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
227 SmallVector<SDValue, 8> &Aliases);
229 /// isAlias - Return true if there is any possibility that the two addresses
231 bool isAlias(SDValue Ptr1, int64_t Size1,
232 const Value *SrcValue1, int SrcValueOffset1,
233 SDValue Ptr2, int64_t Size2,
234 const Value *SrcValue2, int SrcValueOffset2) const;
236 /// FindAliasInfo - Extracts the relevant alias information from the memory
237 /// node. Returns true if the operand was a load.
238 bool FindAliasInfo(SDNode *N,
239 SDValue &Ptr, int64_t &Size,
240 const Value *&SrcValue, int &SrcValueOffset) const;
242 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
243 /// looking for a better chain (aliasing node.)
244 SDValue FindBetterChain(SDNode *N, SDValue Chain);
246 /// getShiftAmountTy - Returns a type large enough to hold any valid
247 /// shift amount - before type legalization these can be huge.
248 MVT getShiftAmountTy() {
249 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
253 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast)
255 TLI(D.getTargetLoweringInfo()),
257 LegalOperations(false),
262 /// Run - runs the dag combiner on all nodes in the work list
263 void Run(CombineLevel AtLevel);
269 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
270 /// nodes from the worklist.
271 class VISIBILITY_HIDDEN WorkListRemover :
272 public SelectionDAG::DAGUpdateListener {
275 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
277 virtual void NodeDeleted(SDNode *N, SDNode *E) {
278 DC.removeFromWorkList(N);
281 virtual void NodeUpdated(SDNode *N) {
287 //===----------------------------------------------------------------------===//
288 // TargetLowering::DAGCombinerInfo implementation
289 //===----------------------------------------------------------------------===//
291 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
292 ((DAGCombiner*)DC)->AddToWorkList(N);
295 SDValue TargetLowering::DAGCombinerInfo::
296 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
297 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
300 SDValue TargetLowering::DAGCombinerInfo::
301 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
302 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
306 SDValue TargetLowering::DAGCombinerInfo::
307 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
308 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
311 void TargetLowering::DAGCombinerInfo::
312 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
313 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
316 //===----------------------------------------------------------------------===//
318 //===----------------------------------------------------------------------===//
320 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
321 /// specified expression for the same cost as the expression itself, or 2 if we
322 /// can compute the negated form more cheaply than the expression itself.
323 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
324 unsigned Depth = 0) {
325 // No compile time optimizations on this type.
326 if (Op.getValueType() == MVT::ppcf128)
329 // fneg is removable even if it has multiple uses.
330 if (Op.getOpcode() == ISD::FNEG) return 2;
332 // Don't allow anything with multiple uses.
333 if (!Op.hasOneUse()) return 0;
335 // Don't recurse exponentially.
336 if (Depth > 6) return 0;
338 switch (Op.getOpcode()) {
339 default: return false;
340 case ISD::ConstantFP:
341 // Don't invert constant FP values after legalize. The negated constant
342 // isn't necessarily legal.
343 return LegalOperations ? 0 : 1;
345 // FIXME: determine better conditions for this xform.
346 if (!UnsafeFPMath) return 0;
348 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
349 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
351 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
352 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
354 // We can't turn -(A-B) into B-A when we honor signed zeros.
355 if (!UnsafeFPMath) return 0;
357 // fold (fneg (fsub A, B)) -> (fsub B, A)
362 if (HonorSignDependentRoundingFPMath()) return 0;
364 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
365 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
368 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
373 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
377 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
378 /// returns the newly negated expression.
379 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
380 bool LegalOperations, unsigned Depth = 0) {
381 // fneg is removable even if it has multiple uses.
382 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
384 // Don't allow anything with multiple uses.
385 assert(Op.hasOneUse() && "Unknown reuse!");
387 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
388 switch (Op.getOpcode()) {
389 default: assert(0 && "Unknown code");
390 case ISD::ConstantFP: {
391 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
393 return DAG.getConstantFP(V, Op.getValueType());
396 // FIXME: determine better conditions for this xform.
397 assert(UnsafeFPMath);
399 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
400 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
401 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
402 GetNegatedExpression(Op.getOperand(0), DAG,
403 LegalOperations, Depth+1),
405 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
406 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
407 GetNegatedExpression(Op.getOperand(1), DAG,
408 LegalOperations, Depth+1),
411 // We can't turn -(A-B) into B-A when we honor signed zeros.
412 assert(UnsafeFPMath);
414 // fold (fneg (fsub 0, B)) -> B
415 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
416 if (N0CFP->getValueAPF().isZero())
417 return Op.getOperand(1);
419 // fold (fneg (fsub A, B)) -> (fsub B, A)
420 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
421 Op.getOperand(1), Op.getOperand(0));
425 assert(!HonorSignDependentRoundingFPMath());
427 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
428 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
429 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
430 GetNegatedExpression(Op.getOperand(0), DAG,
431 LegalOperations, Depth+1),
434 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
435 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
437 GetNegatedExpression(Op.getOperand(1), DAG,
438 LegalOperations, Depth+1));
442 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
443 GetNegatedExpression(Op.getOperand(0), DAG,
444 LegalOperations, Depth+1));
446 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
447 GetNegatedExpression(Op.getOperand(0), DAG,
448 LegalOperations, Depth+1),
454 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
455 // that selects between the values 1 and 0, making it equivalent to a setcc.
456 // Also, set the incoming LHS, RHS, and CC references to the appropriate
457 // nodes based on the type of node we are checking. This simplifies life a
458 // bit for the callers.
459 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
461 if (N.getOpcode() == ISD::SETCC) {
462 LHS = N.getOperand(0);
463 RHS = N.getOperand(1);
464 CC = N.getOperand(2);
467 if (N.getOpcode() == ISD::SELECT_CC &&
468 N.getOperand(2).getOpcode() == ISD::Constant &&
469 N.getOperand(3).getOpcode() == ISD::Constant &&
470 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
471 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
472 LHS = N.getOperand(0);
473 RHS = N.getOperand(1);
474 CC = N.getOperand(4);
480 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
481 // one use. If this is true, it allows the users to invert the operation for
482 // free when it is profitable to do so.
483 static bool isOneUseSetCC(SDValue N) {
485 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
490 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
491 SDValue N0, SDValue N1) {
492 MVT VT = N0.getValueType();
493 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
494 if (isa<ConstantSDNode>(N1)) {
495 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
497 DAG.FoldConstantArithmetic(Opc, VT,
498 cast<ConstantSDNode>(N0.getOperand(1)),
499 cast<ConstantSDNode>(N1));
500 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
501 } else if (N0.hasOneUse()) {
502 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
503 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
504 N0.getOperand(0), N1);
505 AddToWorkList(OpNode.getNode());
506 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
510 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
511 if (isa<ConstantSDNode>(N0)) {
512 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
514 DAG.FoldConstantArithmetic(Opc, VT,
515 cast<ConstantSDNode>(N1.getOperand(1)),
516 cast<ConstantSDNode>(N0));
517 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
518 } else if (N1.hasOneUse()) {
519 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
520 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
521 N1.getOperand(0), N0);
522 AddToWorkList(OpNode.getNode());
523 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
530 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
532 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
534 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
535 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG));
536 DOUT << " and " << NumTo-1 << " other values\n";
537 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i)
538 assert(N->getValueType(i) == To[i].getValueType() &&
539 "Cannot combine value to value of different type!"));
540 WorkListRemover DeadNodes(*this);
541 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
544 // Push the new nodes and any users onto the worklist
545 for (unsigned i = 0, e = NumTo; i != e; ++i) {
546 if (To[i].getNode()) {
547 AddToWorkList(To[i].getNode());
548 AddUsersToWorkList(To[i].getNode());
553 // Finally, if the node is now dead, remove it from the graph. The node
554 // may not be dead if the replacement process recursively simplified to
555 // something else needing this node.
556 if (N->use_empty()) {
557 // Nodes can be reintroduced into the worklist. Make sure we do not
558 // process a node that has been replaced.
559 removeFromWorkList(N);
561 // Finally, since the node is now dead, remove it from the graph.
564 return SDValue(N, 0);
568 DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &
570 // Replace all uses. If any nodes become isomorphic to other nodes and
571 // are deleted, make sure to remove them from our worklist.
572 WorkListRemover DeadNodes(*this);
573 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
575 // Push the new node and any (possibly new) users onto the worklist.
576 AddToWorkList(TLO.New.getNode());
577 AddUsersToWorkList(TLO.New.getNode());
579 // Finally, if the node is now dead, remove it from the graph. The node
580 // may not be dead if the replacement process recursively simplified to
581 // something else needing this node.
582 if (TLO.Old.getNode()->use_empty()) {
583 removeFromWorkList(TLO.Old.getNode());
585 // If the operands of this node are only used by the node, they will now
586 // be dead. Make sure to visit them first to delete dead nodes early.
587 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
588 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
589 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
591 DAG.DeleteNode(TLO.Old.getNode());
595 /// SimplifyDemandedBits - Check the specified integer node value to see if
596 /// it can be simplified or if things it uses can be simplified by bit
597 /// propagation. If so, return true.
598 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
599 TargetLowering::TargetLoweringOpt TLO(DAG);
600 APInt KnownZero, KnownOne;
601 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
605 AddToWorkList(Op.getNode());
607 // Replace the old value with the new one.
609 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG));
610 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG));
613 CommitTargetLoweringOpt(TLO);
617 //===----------------------------------------------------------------------===//
618 // Main DAG Combiner implementation
619 //===----------------------------------------------------------------------===//
621 void DAGCombiner::Run(CombineLevel AtLevel) {
622 // set the instance variables, so that the various visit routines may use it.
624 LegalOperations = Level >= NoIllegalOperations;
625 LegalTypes = Level >= NoIllegalTypes;
627 // Add all the dag nodes to the worklist.
628 WorkList.reserve(DAG.allnodes_size());
629 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
630 E = DAG.allnodes_end(); I != E; ++I)
631 WorkList.push_back(I);
633 // Create a dummy node (which is not added to allnodes), that adds a reference
634 // to the root node, preventing it from being deleted, and tracking any
635 // changes of the root.
636 HandleSDNode Dummy(DAG.getRoot());
638 // The root of the dag may dangle to deleted nodes until the dag combiner is
639 // done. Set it to null to avoid confusion.
640 DAG.setRoot(SDValue());
642 // while the worklist isn't empty, inspect the node on the end of it and
643 // try and combine it.
644 while (!WorkList.empty()) {
645 SDNode *N = WorkList.back();
648 // If N has no uses, it is dead. Make sure to revisit all N's operands once
649 // N is deleted from the DAG, since they too may now be dead or may have a
650 // reduced number of uses, allowing other xforms.
651 if (N->use_empty() && N != &Dummy) {
652 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
653 AddToWorkList(N->getOperand(i).getNode());
659 SDValue RV = combine(N);
661 if (RV.getNode() == 0)
666 // If we get back the same node we passed in, rather than a new node or
667 // zero, we know that the node must have defined multiple values and
668 // CombineTo was used. Since CombineTo takes care of the worklist
669 // mechanics for us, we have no work to do in this case.
670 if (RV.getNode() == N)
673 assert(N->getOpcode() != ISD::DELETED_NODE &&
674 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
675 "Node was deleted but visit returned new node!");
677 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
678 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG));
680 WorkListRemover DeadNodes(*this);
681 if (N->getNumValues() == RV.getNode()->getNumValues())
682 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
684 assert(N->getValueType(0) == RV.getValueType() &&
685 N->getNumValues() == 1 && "Type mismatch");
687 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
690 // Push the new node and any users onto the worklist
691 AddToWorkList(RV.getNode());
692 AddUsersToWorkList(RV.getNode());
694 // Add any uses of the old node to the worklist in case this node is the
695 // last one that uses them. They may become dead after this node is
697 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
698 AddToWorkList(N->getOperand(i).getNode());
700 // Finally, if the node is now dead, remove it from the graph. The node
701 // may not be dead if the replacement process recursively simplified to
702 // something else needing this node.
703 if (N->use_empty()) {
704 // Nodes can be reintroduced into the worklist. Make sure we do not
705 // process a node that has been replaced.
706 removeFromWorkList(N);
708 // Finally, since the node is now dead, remove it from the graph.
713 // If the root changed (e.g. it was a dead load, update the root).
714 DAG.setRoot(Dummy.getValue());
717 SDValue DAGCombiner::visit(SDNode *N) {
718 switch(N->getOpcode()) {
720 case ISD::TokenFactor: return visitTokenFactor(N);
721 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
722 case ISD::ADD: return visitADD(N);
723 case ISD::SUB: return visitSUB(N);
724 case ISD::ADDC: return visitADDC(N);
725 case ISD::ADDE: return visitADDE(N);
726 case ISD::MUL: return visitMUL(N);
727 case ISD::SDIV: return visitSDIV(N);
728 case ISD::UDIV: return visitUDIV(N);
729 case ISD::SREM: return visitSREM(N);
730 case ISD::UREM: return visitUREM(N);
731 case ISD::MULHU: return visitMULHU(N);
732 case ISD::MULHS: return visitMULHS(N);
733 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
734 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
735 case ISD::SDIVREM: return visitSDIVREM(N);
736 case ISD::UDIVREM: return visitUDIVREM(N);
737 case ISD::AND: return visitAND(N);
738 case ISD::OR: return visitOR(N);
739 case ISD::XOR: return visitXOR(N);
740 case ISD::SHL: return visitSHL(N);
741 case ISD::SRA: return visitSRA(N);
742 case ISD::SRL: return visitSRL(N);
743 case ISD::CTLZ: return visitCTLZ(N);
744 case ISD::CTTZ: return visitCTTZ(N);
745 case ISD::CTPOP: return visitCTPOP(N);
746 case ISD::SELECT: return visitSELECT(N);
747 case ISD::SELECT_CC: return visitSELECT_CC(N);
748 case ISD::SETCC: return visitSETCC(N);
749 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
750 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
751 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
752 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
753 case ISD::TRUNCATE: return visitTRUNCATE(N);
754 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
755 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
756 case ISD::FADD: return visitFADD(N);
757 case ISD::FSUB: return visitFSUB(N);
758 case ISD::FMUL: return visitFMUL(N);
759 case ISD::FDIV: return visitFDIV(N);
760 case ISD::FREM: return visitFREM(N);
761 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
762 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
763 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
764 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
765 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
766 case ISD::FP_ROUND: return visitFP_ROUND(N);
767 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
768 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
769 case ISD::FNEG: return visitFNEG(N);
770 case ISD::FABS: return visitFABS(N);
771 case ISD::BRCOND: return visitBRCOND(N);
772 case ISD::BR_CC: return visitBR_CC(N);
773 case ISD::LOAD: return visitLOAD(N);
774 case ISD::STORE: return visitSTORE(N);
775 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
776 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
777 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
778 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
779 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
784 SDValue DAGCombiner::combine(SDNode *N) {
785 SDValue RV = visit(N);
787 // If nothing happened, try a target-specific DAG combine.
788 if (RV.getNode() == 0) {
789 assert(N->getOpcode() != ISD::DELETED_NODE &&
790 "Node was deleted but visit returned NULL!");
792 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
793 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
795 // Expose the DAG combiner to the target combiner impls.
796 TargetLowering::DAGCombinerInfo
797 DagCombineInfo(DAG, Level == Unrestricted, false, this);
799 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
803 // If N is a commutative binary node, try commuting it to enable more
805 if (RV.getNode() == 0 &&
806 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
807 N->getNumValues() == 1) {
808 SDValue N0 = N->getOperand(0);
809 SDValue N1 = N->getOperand(1);
811 // Constant operands are canonicalized to RHS.
812 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
813 SDValue Ops[] = { N1, N0 };
814 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
817 return SDValue(CSENode, 0);
824 /// getInputChainForNode - Given a node, return its input chain if it has one,
825 /// otherwise return a null sd operand.
826 static SDValue getInputChainForNode(SDNode *N) {
827 if (unsigned NumOps = N->getNumOperands()) {
828 if (N->getOperand(0).getValueType() == MVT::Other)
829 return N->getOperand(0);
830 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
831 return N->getOperand(NumOps-1);
832 for (unsigned i = 1; i < NumOps-1; ++i)
833 if (N->getOperand(i).getValueType() == MVT::Other)
834 return N->getOperand(i);
839 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
840 // If N has two operands, where one has an input chain equal to the other,
841 // the 'other' chain is redundant.
842 if (N->getNumOperands() == 2) {
843 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
844 return N->getOperand(0);
845 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
846 return N->getOperand(1);
849 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
850 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
851 SmallPtrSet<SDNode*, 16> SeenOps;
852 bool Changed = false; // If we should replace this token factor.
854 // Start out with this token factor.
857 // Iterate through token factors. The TFs grows when new token factors are
859 for (unsigned i = 0; i < TFs.size(); ++i) {
862 // Check each of the operands.
863 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
864 SDValue Op = TF->getOperand(i);
866 switch (Op.getOpcode()) {
867 case ISD::EntryToken:
868 // Entry tokens don't need to be added to the list. They are
873 case ISD::TokenFactor:
874 if ((CombinerAA || Op.hasOneUse()) &&
875 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
876 // Queue up for processing.
877 TFs.push_back(Op.getNode());
878 // Clean up in case the token factor is removed.
879 AddToWorkList(Op.getNode());
886 // Only add if it isn't already in the list.
887 if (SeenOps.insert(Op.getNode()))
898 // If we've change things around then replace token factor.
901 // The entry token is the only possible outcome.
902 Result = DAG.getEntryNode();
904 // New and improved token factor.
905 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
906 MVT::Other, &Ops[0], Ops.size());
909 // Don't add users to work list.
910 return CombineTo(N, Result, false);
916 /// MERGE_VALUES can always be eliminated.
917 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
918 WorkListRemover DeadNodes(*this);
919 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
920 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
922 removeFromWorkList(N);
924 return SDValue(N, 0); // Return N so it doesn't get rechecked!
928 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
930 MVT VT = N0.getValueType();
931 SDValue N00 = N0.getOperand(0);
932 SDValue N01 = N0.getOperand(1);
933 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
935 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
936 isa<ConstantSDNode>(N00.getOperand(1))) {
937 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
938 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
939 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
940 N00.getOperand(0), N01),
941 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
942 N00.getOperand(1), N01));
943 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
949 SDValue DAGCombiner::visitADD(SDNode *N) {
950 SDValue N0 = N->getOperand(0);
951 SDValue N1 = N->getOperand(1);
952 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
953 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
954 MVT VT = N0.getValueType();
958 SDValue FoldedVOp = SimplifyVBinOp(N);
959 if (FoldedVOp.getNode()) return FoldedVOp;
962 // fold (add x, undef) -> undef
963 if (N0.getOpcode() == ISD::UNDEF)
965 if (N1.getOpcode() == ISD::UNDEF)
967 // fold (add c1, c2) -> c1+c2
969 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
970 // canonicalize constant to RHS
972 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
973 // fold (add x, 0) -> x
974 if (N1C && N1C->isNullValue())
976 // fold (add Sym, c) -> Sym+c
977 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
978 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
979 GA->getOpcode() == ISD::GlobalAddress)
980 return DAG.getGlobalAddress(GA->getGlobal(), VT,
982 (uint64_t)N1C->getSExtValue());
983 // fold ((c1-A)+c2) -> (c1+c2)-A
984 if (N1C && N0.getOpcode() == ISD::SUB)
985 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
986 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
987 DAG.getConstant(N1C->getAPIntValue()+
988 N0C->getAPIntValue(), VT),
991 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
992 if (RADD.getNode() != 0)
994 // fold ((0-A) + B) -> B-A
995 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
996 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
997 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
998 // fold (A + (0-B)) -> A-B
999 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1000 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1001 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1002 // fold (A+(B-A)) -> B
1003 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1004 return N1.getOperand(0);
1005 // fold ((B-A)+A) -> B
1006 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1007 return N0.getOperand(0);
1008 // fold (A+(B-(A+C))) to (B-C)
1009 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1010 N0 == N1.getOperand(1).getOperand(0))
1011 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1012 N1.getOperand(1).getOperand(1));
1013 // fold (A+(B-(C+A))) to (B-C)
1014 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1015 N0 == N1.getOperand(1).getOperand(1))
1016 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1017 N1.getOperand(1).getOperand(0));
1018 // fold (A+((B-A)+or-C)) to (B+or-C)
1019 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1020 N1.getOperand(0).getOpcode() == ISD::SUB &&
1021 N0 == N1.getOperand(0).getOperand(1))
1022 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1023 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1025 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1026 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1027 SDValue N00 = N0.getOperand(0);
1028 SDValue N01 = N0.getOperand(1);
1029 SDValue N10 = N1.getOperand(0);
1030 SDValue N11 = N1.getOperand(1);
1032 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1033 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1034 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1035 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1038 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1039 return SDValue(N, 0);
1041 // fold (a+b) -> (a|b) iff a and b share no bits.
1042 if (VT.isInteger() && !VT.isVector()) {
1043 APInt LHSZero, LHSOne;
1044 APInt RHSZero, RHSOne;
1045 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1046 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1048 if (LHSZero.getBoolValue()) {
1049 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1051 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1052 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1053 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1054 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1055 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1059 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1060 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1061 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1062 if (Result.getNode()) return Result;
1064 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1065 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1066 if (Result.getNode()) return Result;
1072 SDValue DAGCombiner::visitADDC(SDNode *N) {
1073 SDValue N0 = N->getOperand(0);
1074 SDValue N1 = N->getOperand(1);
1075 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1076 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1077 MVT VT = N0.getValueType();
1079 // If the flag result is dead, turn this into an ADD.
1080 if (N->hasNUsesOfValue(0, 1))
1081 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1082 DAG.getNode(ISD::CARRY_FALSE,
1083 N->getDebugLoc(), MVT::Flag));
1085 // canonicalize constant to RHS.
1087 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1089 // fold (addc x, 0) -> x + no carry out
1090 if (N1C && N1C->isNullValue())
1091 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1092 N->getDebugLoc(), MVT::Flag));
1094 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1095 APInt LHSZero, LHSOne;
1096 APInt RHSZero, RHSOne;
1097 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
1098 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1100 if (LHSZero.getBoolValue()) {
1101 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1103 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1104 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1105 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1106 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1107 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1108 DAG.getNode(ISD::CARRY_FALSE,
1109 N->getDebugLoc(), MVT::Flag));
1115 SDValue DAGCombiner::visitADDE(SDNode *N) {
1116 SDValue N0 = N->getOperand(0);
1117 SDValue N1 = N->getOperand(1);
1118 SDValue CarryIn = N->getOperand(2);
1119 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1120 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1122 // canonicalize constant to RHS
1124 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1127 // fold (adde x, y, false) -> (addc x, y)
1128 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1129 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1134 SDValue DAGCombiner::visitSUB(SDNode *N) {
1135 SDValue N0 = N->getOperand(0);
1136 SDValue N1 = N->getOperand(1);
1137 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1138 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1139 MVT VT = N0.getValueType();
1142 if (VT.isVector()) {
1143 SDValue FoldedVOp = SimplifyVBinOp(N);
1144 if (FoldedVOp.getNode()) return FoldedVOp;
1147 // fold (sub x, x) -> 0
1149 return DAG.getConstant(0, N->getValueType(0));
1150 // fold (sub c1, c2) -> c1-c2
1152 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1153 // fold (sub x, c) -> (add x, -c)
1155 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1156 DAG.getConstant(-N1C->getAPIntValue(), VT));
1157 // fold (A+B)-A -> B
1158 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1159 return N0.getOperand(1);
1160 // fold (A+B)-B -> A
1161 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1162 return N0.getOperand(0);
1163 // fold ((A+(B+or-C))-B) -> A+or-C
1164 if (N0.getOpcode() == ISD::ADD &&
1165 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1166 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1167 N0.getOperand(1).getOperand(0) == N1)
1168 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1169 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1170 // fold ((A+(C+B))-B) -> A+C
1171 if (N0.getOpcode() == ISD::ADD &&
1172 N0.getOperand(1).getOpcode() == ISD::ADD &&
1173 N0.getOperand(1).getOperand(1) == N1)
1174 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1175 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1176 // fold ((A-(B-C))-C) -> A-B
1177 if (N0.getOpcode() == ISD::SUB &&
1178 N0.getOperand(1).getOpcode() == ISD::SUB &&
1179 N0.getOperand(1).getOperand(1) == N1)
1180 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1181 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1183 // If either operand of a sub is undef, the result is undef
1184 if (N0.getOpcode() == ISD::UNDEF)
1186 if (N1.getOpcode() == ISD::UNDEF)
1189 // If the relocation model supports it, consider symbol offsets.
1190 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1191 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1192 // fold (sub Sym, c) -> Sym-c
1193 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1194 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1196 (uint64_t)N1C->getSExtValue());
1197 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1198 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1199 if (GA->getGlobal() == GB->getGlobal())
1200 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1207 SDValue DAGCombiner::visitMUL(SDNode *N) {
1208 SDValue N0 = N->getOperand(0);
1209 SDValue N1 = N->getOperand(1);
1210 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1211 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1212 MVT VT = N0.getValueType();
1215 if (VT.isVector()) {
1216 SDValue FoldedVOp = SimplifyVBinOp(N);
1217 if (FoldedVOp.getNode()) return FoldedVOp;
1220 // fold (mul x, undef) -> 0
1221 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1222 return DAG.getConstant(0, VT);
1223 // fold (mul c1, c2) -> c1*c2
1225 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1226 // canonicalize constant to RHS
1228 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1229 // fold (mul x, 0) -> 0
1230 if (N1C && N1C->isNullValue())
1232 // fold (mul x, -1) -> 0-x
1233 if (N1C && N1C->isAllOnesValue())
1234 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1235 DAG.getConstant(0, VT), N0);
1236 // fold (mul x, (1 << c)) -> x << c
1237 if (N1C && N1C->getAPIntValue().isPowerOf2())
1238 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1239 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1240 getShiftAmountTy()));
1241 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1242 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1243 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1244 // FIXME: If the input is something that is easily negated (e.g. a
1245 // single-use add), we should put the negate there.
1246 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1247 DAG.getConstant(0, VT),
1248 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1249 DAG.getConstant(Log2Val, getShiftAmountTy())));
1251 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1252 if (N1C && N0.getOpcode() == ISD::SHL &&
1253 isa<ConstantSDNode>(N0.getOperand(1))) {
1254 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1255 N1, N0.getOperand(1));
1256 AddToWorkList(C3.getNode());
1257 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1258 N0.getOperand(0), C3);
1261 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1264 SDValue Sh(0,0), Y(0,0);
1265 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1266 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1267 N0.getNode()->hasOneUse()) {
1269 } else if (N1.getOpcode() == ISD::SHL &&
1270 isa<ConstantSDNode>(N1.getOperand(1)) &&
1271 N1.getNode()->hasOneUse()) {
1276 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1277 Sh.getOperand(0), Y);
1278 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1279 Mul, Sh.getOperand(1));
1283 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1284 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1285 isa<ConstantSDNode>(N0.getOperand(1)))
1286 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1287 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1288 N0.getOperand(0), N1),
1289 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1290 N0.getOperand(1), N1));
1293 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1294 if (RMUL.getNode() != 0)
1300 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1301 SDValue N0 = N->getOperand(0);
1302 SDValue N1 = N->getOperand(1);
1303 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1304 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1305 MVT VT = N->getValueType(0);
1308 if (VT.isVector()) {
1309 SDValue FoldedVOp = SimplifyVBinOp(N);
1310 if (FoldedVOp.getNode()) return FoldedVOp;
1313 // fold (sdiv c1, c2) -> c1/c2
1314 if (N0C && N1C && !N1C->isNullValue())
1315 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1316 // fold (sdiv X, 1) -> X
1317 if (N1C && N1C->getSExtValue() == 1LL)
1319 // fold (sdiv X, -1) -> 0-X
1320 if (N1C && N1C->isAllOnesValue())
1321 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1322 DAG.getConstant(0, VT), N0);
1323 // If we know the sign bits of both operands are zero, strength reduce to a
1324 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1325 if (!VT.isVector()) {
1326 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1327 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1330 // fold (sdiv X, pow2) -> simple ops after legalize
1331 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1332 (isPowerOf2_64(N1C->getSExtValue()) ||
1333 isPowerOf2_64(-N1C->getSExtValue()))) {
1334 // If dividing by powers of two is cheap, then don't perform the following
1336 if (TLI.isPow2DivCheap())
1339 int64_t pow2 = N1C->getSExtValue();
1340 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1341 unsigned lg2 = Log2_64(abs2);
1343 // Splat the sign bit into the register
1344 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1345 DAG.getConstant(VT.getSizeInBits()-1,
1346 getShiftAmountTy()));
1347 AddToWorkList(SGN.getNode());
1349 // Add (N0 < 0) ? abs2 - 1 : 0;
1350 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1351 DAG.getConstant(VT.getSizeInBits() - lg2,
1352 getShiftAmountTy()));
1353 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1354 AddToWorkList(SRL.getNode());
1355 AddToWorkList(ADD.getNode()); // Divide by pow2
1356 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1357 DAG.getConstant(lg2, getShiftAmountTy()));
1359 // If we're dividing by a positive value, we're done. Otherwise, we must
1360 // negate the result.
1364 AddToWorkList(SRA.getNode());
1365 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1366 DAG.getConstant(0, VT), SRA);
1369 // if integer divide is expensive and we satisfy the requirements, emit an
1370 // alternate sequence.
1371 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1372 !TLI.isIntDivCheap()) {
1373 SDValue Op = BuildSDIV(N);
1374 if (Op.getNode()) return Op;
1378 if (N0.getOpcode() == ISD::UNDEF)
1379 return DAG.getConstant(0, VT);
1380 // X / undef -> undef
1381 if (N1.getOpcode() == ISD::UNDEF)
1387 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1388 SDValue N0 = N->getOperand(0);
1389 SDValue N1 = N->getOperand(1);
1390 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1391 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1392 MVT VT = N->getValueType(0);
1395 if (VT.isVector()) {
1396 SDValue FoldedVOp = SimplifyVBinOp(N);
1397 if (FoldedVOp.getNode()) return FoldedVOp;
1400 // fold (udiv c1, c2) -> c1/c2
1401 if (N0C && N1C && !N1C->isNullValue())
1402 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1403 // fold (udiv x, (1 << c)) -> x >>u c
1404 if (N1C && N1C->getAPIntValue().isPowerOf2())
1405 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1406 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1407 getShiftAmountTy()));
1408 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1409 if (N1.getOpcode() == ISD::SHL) {
1410 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1411 if (SHC->getAPIntValue().isPowerOf2()) {
1412 MVT ADDVT = N1.getOperand(1).getValueType();
1413 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1415 DAG.getConstant(SHC->getAPIntValue()
1418 AddToWorkList(Add.getNode());
1419 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1423 // fold (udiv x, c) -> alternate
1424 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1425 SDValue Op = BuildUDIV(N);
1426 if (Op.getNode()) return Op;
1430 if (N0.getOpcode() == ISD::UNDEF)
1431 return DAG.getConstant(0, VT);
1432 // X / undef -> undef
1433 if (N1.getOpcode() == ISD::UNDEF)
1439 SDValue DAGCombiner::visitSREM(SDNode *N) {
1440 SDValue N0 = N->getOperand(0);
1441 SDValue N1 = N->getOperand(1);
1442 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1443 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1444 MVT VT = N->getValueType(0);
1446 // fold (srem c1, c2) -> c1%c2
1447 if (N0C && N1C && !N1C->isNullValue())
1448 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1449 // If we know the sign bits of both operands are zero, strength reduce to a
1450 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1451 if (!VT.isVector()) {
1452 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1453 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1456 // If X/C can be simplified by the division-by-constant logic, lower
1457 // X%C to the equivalent of X-X/C*C.
1458 if (N1C && !N1C->isNullValue()) {
1459 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1460 AddToWorkList(Div.getNode());
1461 SDValue OptimizedDiv = combine(Div.getNode());
1462 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1463 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1465 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1466 AddToWorkList(Mul.getNode());
1472 if (N0.getOpcode() == ISD::UNDEF)
1473 return DAG.getConstant(0, VT);
1474 // X % undef -> undef
1475 if (N1.getOpcode() == ISD::UNDEF)
1481 SDValue DAGCombiner::visitUREM(SDNode *N) {
1482 SDValue N0 = N->getOperand(0);
1483 SDValue N1 = N->getOperand(1);
1484 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1485 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1486 MVT VT = N->getValueType(0);
1488 // fold (urem c1, c2) -> c1%c2
1489 if (N0C && N1C && !N1C->isNullValue())
1490 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1491 // fold (urem x, pow2) -> (and x, pow2-1)
1492 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1493 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1494 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1495 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1496 if (N1.getOpcode() == ISD::SHL) {
1497 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1498 if (SHC->getAPIntValue().isPowerOf2()) {
1500 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1501 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1503 AddToWorkList(Add.getNode());
1504 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1509 // If X/C can be simplified by the division-by-constant logic, lower
1510 // X%C to the equivalent of X-X/C*C.
1511 if (N1C && !N1C->isNullValue()) {
1512 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1513 AddToWorkList(Div.getNode());
1514 SDValue OptimizedDiv = combine(Div.getNode());
1515 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1516 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1518 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1519 AddToWorkList(Mul.getNode());
1525 if (N0.getOpcode() == ISD::UNDEF)
1526 return DAG.getConstant(0, VT);
1527 // X % undef -> undef
1528 if (N1.getOpcode() == ISD::UNDEF)
1534 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1535 SDValue N0 = N->getOperand(0);
1536 SDValue N1 = N->getOperand(1);
1537 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1538 MVT VT = N->getValueType(0);
1540 // fold (mulhs x, 0) -> 0
1541 if (N1C && N1C->isNullValue())
1543 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1544 if (N1C && N1C->getAPIntValue() == 1)
1545 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1546 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1547 getShiftAmountTy()));
1548 // fold (mulhs x, undef) -> 0
1549 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1550 return DAG.getConstant(0, VT);
1555 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1556 SDValue N0 = N->getOperand(0);
1557 SDValue N1 = N->getOperand(1);
1558 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1559 MVT VT = N->getValueType(0);
1561 // fold (mulhu x, 0) -> 0
1562 if (N1C && N1C->isNullValue())
1564 // fold (mulhu x, 1) -> 0
1565 if (N1C && N1C->getAPIntValue() == 1)
1566 return DAG.getConstant(0, N0.getValueType());
1567 // fold (mulhu x, undef) -> 0
1568 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1569 return DAG.getConstant(0, VT);
1574 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1575 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1576 /// that are being performed. Return true if a simplification was made.
1578 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1580 // If the high half is not needed, just compute the low half.
1581 bool HiExists = N->hasAnyUseOfValue(1);
1583 (!LegalOperations ||
1584 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1585 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1586 N->op_begin(), N->getNumOperands());
1587 return CombineTo(N, Res, Res);
1590 // If the low half is not needed, just compute the high half.
1591 bool LoExists = N->hasAnyUseOfValue(0);
1593 (!LegalOperations ||
1594 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1595 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1596 N->op_begin(), N->getNumOperands());
1597 return CombineTo(N, Res, Res);
1600 // If both halves are used, return as it is.
1601 if (LoExists && HiExists)
1604 // If the two computed results can be simplified separately, separate them.
1606 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1607 N->op_begin(), N->getNumOperands());
1608 AddToWorkList(Lo.getNode());
1609 SDValue LoOpt = combine(Lo.getNode());
1610 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1611 (!LegalOperations ||
1612 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1613 return CombineTo(N, LoOpt, LoOpt);
1617 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1618 N->op_begin(), N->getNumOperands());
1619 AddToWorkList(Hi.getNode());
1620 SDValue HiOpt = combine(Hi.getNode());
1621 if (HiOpt.getNode() && HiOpt != Hi &&
1622 (!LegalOperations ||
1623 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1624 return CombineTo(N, HiOpt, HiOpt);
1630 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1631 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1632 if (Res.getNode()) return Res;
1637 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1638 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1639 if (Res.getNode()) return Res;
1644 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
1645 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1646 if (Res.getNode()) return Res;
1651 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
1652 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1653 if (Res.getNode()) return Res;
1658 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1659 /// two operands of the same opcode, try to simplify it.
1660 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1661 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1662 MVT VT = N0.getValueType();
1663 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1665 // For each of OP in AND/OR/XOR:
1666 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1667 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1668 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1669 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
1670 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1671 N0.getOpcode() == ISD::SIGN_EXTEND ||
1672 (N0.getOpcode() == ISD::TRUNCATE &&
1673 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) &&
1674 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1675 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1676 N0.getOperand(0).getValueType(),
1677 N0.getOperand(0), N1.getOperand(0));
1678 AddToWorkList(ORNode.getNode());
1679 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
1682 // For each of OP in SHL/SRL/SRA/AND...
1683 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1684 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1685 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1686 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1687 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1688 N0.getOperand(1) == N1.getOperand(1)) {
1689 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1690 N0.getOperand(0).getValueType(),
1691 N0.getOperand(0), N1.getOperand(0));
1692 AddToWorkList(ORNode.getNode());
1693 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
1694 ORNode, N0.getOperand(1));
1700 SDValue DAGCombiner::visitAND(SDNode *N) {
1701 SDValue N0 = N->getOperand(0);
1702 SDValue N1 = N->getOperand(1);
1703 SDValue LL, LR, RL, RR, CC0, CC1;
1704 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1705 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1706 MVT VT = N1.getValueType();
1707 unsigned BitWidth = VT.getSizeInBits();
1710 if (VT.isVector()) {
1711 SDValue FoldedVOp = SimplifyVBinOp(N);
1712 if (FoldedVOp.getNode()) return FoldedVOp;
1715 // fold (and x, undef) -> 0
1716 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1717 return DAG.getConstant(0, VT);
1718 // fold (and c1, c2) -> c1&c2
1720 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
1721 // canonicalize constant to RHS
1723 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
1724 // fold (and x, -1) -> x
1725 if (N1C && N1C->isAllOnesValue())
1727 // if (and x, c) is known to be zero, return 0
1728 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
1729 APInt::getAllOnesValue(BitWidth)))
1730 return DAG.getConstant(0, VT);
1732 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
1733 if (RAND.getNode() != 0)
1735 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1736 if (N1C && N0.getOpcode() == ISD::OR)
1737 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1738 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
1740 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1741 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1742 SDValue N0Op0 = N0.getOperand(0);
1743 APInt Mask = ~N1C->getAPIntValue();
1744 Mask.trunc(N0Op0.getValueSizeInBits());
1745 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
1746 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
1747 N0.getValueType(), N0Op0);
1749 // Replace uses of the AND with uses of the Zero extend node.
1752 // We actually want to replace all uses of the any_extend with the
1753 // zero_extend, to avoid duplicating things. This will later cause this
1754 // AND to be folded.
1755 CombineTo(N0.getNode(), Zext);
1756 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1759 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1760 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1761 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1762 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1764 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1765 LL.getValueType().isInteger()) {
1766 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
1767 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
1768 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1769 LR.getValueType(), LL, RL);
1770 AddToWorkList(ORNode.getNode());
1771 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1773 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
1774 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1775 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
1776 LR.getValueType(), LL, RL);
1777 AddToWorkList(ANDNode.getNode());
1778 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1780 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
1781 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1782 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1783 LR.getValueType(), LL, RL);
1784 AddToWorkList(ORNode.getNode());
1785 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1788 // canonicalize equivalent to ll == rl
1789 if (LL == RR && LR == RL) {
1790 Op1 = ISD::getSetCCSwappedOperands(Op1);
1793 if (LL == RL && LR == RR) {
1794 bool isInteger = LL.getValueType().isInteger();
1795 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1796 if (Result != ISD::SETCC_INVALID &&
1797 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
1798 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
1803 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
1804 if (N0.getOpcode() == N1.getOpcode()) {
1805 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1806 if (Tmp.getNode()) return Tmp;
1809 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1810 // fold (and (sra)) -> (and (srl)) when possible.
1811 if (!VT.isVector() &&
1812 SimplifyDemandedBits(SDValue(N, 0)))
1813 return SDValue(N, 0);
1814 // fold (zext_inreg (extload x)) -> (zextload x)
1815 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
1816 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1817 MVT EVT = LN0->getMemoryVT();
1818 // If we zero all the possible extended bits, then we can turn this into
1819 // a zextload if we are running before legalize or the operation is legal.
1820 unsigned BitWidth = N1.getValueSizeInBits();
1821 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1822 BitWidth - EVT.getSizeInBits())) &&
1823 ((!LegalOperations && !LN0->isVolatile()) ||
1824 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1825 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1826 LN0->getChain(), LN0->getBasePtr(),
1828 LN0->getSrcValueOffset(), EVT,
1829 LN0->isVolatile(), LN0->getAlignment());
1831 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1832 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1835 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1836 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
1838 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1839 MVT EVT = LN0->getMemoryVT();
1840 // If we zero all the possible extended bits, then we can turn this into
1841 // a zextload if we are running before legalize or the operation is legal.
1842 unsigned BitWidth = N1.getValueSizeInBits();
1843 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1844 BitWidth - EVT.getSizeInBits())) &&
1845 ((!LegalOperations && !LN0->isVolatile()) ||
1846 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1847 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1849 LN0->getBasePtr(), LN0->getSrcValue(),
1850 LN0->getSrcValueOffset(), EVT,
1851 LN0->isVolatile(), LN0->getAlignment());
1853 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1854 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1858 // fold (and (load x), 255) -> (zextload x, i8)
1859 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1860 if (N1C && N0.getOpcode() == ISD::LOAD) {
1861 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1862 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1863 LN0->isUnindexed() && N0.hasOneUse() &&
1864 // Do not change the width of a volatile load.
1865 !LN0->isVolatile()) {
1866 MVT EVT = MVT::Other;
1867 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
1868 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
1869 EVT = MVT::getIntegerVT(ActiveBits);
1871 MVT LoadedVT = LN0->getMemoryVT();
1873 // Do not generate loads of non-round integer types since these can
1874 // be expensive (and would be wrong if the type is not byte sized).
1875 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() &&
1876 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
1877 MVT PtrType = N0.getOperand(1).getValueType();
1879 // For big endian targets, we need to add an offset to the pointer to
1880 // load the correct bytes. For little endian systems, we merely need to
1881 // read fewer bytes from the same pointer.
1882 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
1883 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
1884 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
1885 unsigned Alignment = LN0->getAlignment();
1886 SDValue NewPtr = LN0->getBasePtr();
1888 if (TLI.isBigEndian()) {
1889 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
1890 NewPtr, DAG.getConstant(PtrOff, PtrType));
1891 Alignment = MinAlign(Alignment, PtrOff);
1894 AddToWorkList(NewPtr.getNode());
1896 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(),
1897 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(),
1898 EVT, LN0->isVolatile(), Alignment);
1900 CombineTo(N0.getNode(), Load, Load.getValue(1));
1901 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1909 SDValue DAGCombiner::visitOR(SDNode *N) {
1910 SDValue N0 = N->getOperand(0);
1911 SDValue N1 = N->getOperand(1);
1912 SDValue LL, LR, RL, RR, CC0, CC1;
1913 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1914 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1915 MVT VT = N1.getValueType();
1918 if (VT.isVector()) {
1919 SDValue FoldedVOp = SimplifyVBinOp(N);
1920 if (FoldedVOp.getNode()) return FoldedVOp;
1923 // fold (or x, undef) -> -1
1924 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1925 return DAG.getConstant(~0ULL, VT);
1926 // fold (or c1, c2) -> c1|c2
1928 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
1929 // canonicalize constant to RHS
1931 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
1932 // fold (or x, 0) -> x
1933 if (N1C && N1C->isNullValue())
1935 // fold (or x, -1) -> -1
1936 if (N1C && N1C->isAllOnesValue())
1938 // fold (or x, c) -> c iff (x & ~c) == 0
1939 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
1942 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
1943 if (ROR.getNode() != 0)
1945 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1946 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
1947 isa<ConstantSDNode>(N0.getOperand(1))) {
1948 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1949 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
1950 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
1951 N0.getOperand(0), N1),
1952 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
1954 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1955 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1956 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1957 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1959 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1960 LL.getValueType().isInteger()) {
1961 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
1962 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
1963 if (cast<ConstantSDNode>(LR)->isNullValue() &&
1964 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1965 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
1966 LR.getValueType(), LL, RL);
1967 AddToWorkList(ORNode.getNode());
1968 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1970 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
1971 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
1972 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1973 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1974 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
1975 LR.getValueType(), LL, RL);
1976 AddToWorkList(ANDNode.getNode());
1977 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1980 // canonicalize equivalent to ll == rl
1981 if (LL == RR && LR == RL) {
1982 Op1 = ISD::getSetCCSwappedOperands(Op1);
1985 if (LL == RL && LR == RR) {
1986 bool isInteger = LL.getValueType().isInteger();
1987 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1988 if (Result != ISD::SETCC_INVALID &&
1989 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
1990 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
1995 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
1996 if (N0.getOpcode() == N1.getOpcode()) {
1997 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1998 if (Tmp.getNode()) return Tmp;
2001 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2002 if (N0.getOpcode() == ISD::AND &&
2003 N1.getOpcode() == ISD::AND &&
2004 N0.getOperand(1).getOpcode() == ISD::Constant &&
2005 N1.getOperand(1).getOpcode() == ISD::Constant &&
2006 // Don't increase # computations.
2007 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2008 // We can only do this xform if we know that bits from X that are set in C2
2009 // but not in C1 are already zero. Likewise for Y.
2010 const APInt &LHSMask =
2011 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2012 const APInt &RHSMask =
2013 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2015 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2016 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2017 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2018 N0.getOperand(0), N1.getOperand(0));
2019 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2020 DAG.getConstant(LHSMask | RHSMask, VT));
2024 // See if this is some rotate idiom.
2025 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2026 return SDValue(Rot, 0);
2031 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2032 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2033 if (Op.getOpcode() == ISD::AND) {
2034 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2035 Mask = Op.getOperand(1);
2036 Op = Op.getOperand(0);
2042 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2050 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2051 // idioms for rotate, and if the target supports rotation instructions, generate
2053 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2054 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2055 MVT VT = LHS.getValueType();
2056 if (!TLI.isTypeLegal(VT)) return 0;
2058 // The target must have at least one rotate flavor.
2059 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2060 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2061 if (!HasROTL && !HasROTR) return 0;
2063 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2064 SDValue LHSShift; // The shift.
2065 SDValue LHSMask; // AND value if any.
2066 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2067 return 0; // Not part of a rotate.
2069 SDValue RHSShift; // The shift.
2070 SDValue RHSMask; // AND value if any.
2071 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2072 return 0; // Not part of a rotate.
2074 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2075 return 0; // Not shifting the same value.
2077 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2078 return 0; // Shifts must disagree.
2080 // Canonicalize shl to left side in a shl/srl pair.
2081 if (RHSShift.getOpcode() == ISD::SHL) {
2082 std::swap(LHS, RHS);
2083 std::swap(LHSShift, RHSShift);
2084 std::swap(LHSMask , RHSMask );
2087 unsigned OpSizeInBits = VT.getSizeInBits();
2088 SDValue LHSShiftArg = LHSShift.getOperand(0);
2089 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2090 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2092 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2093 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2094 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2095 RHSShiftAmt.getOpcode() == ISD::Constant) {
2096 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2097 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2098 if ((LShVal + RShVal) != OpSizeInBits)
2103 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2105 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2107 // If there is an AND of either shifted operand, apply it to the result.
2108 if (LHSMask.getNode() || RHSMask.getNode()) {
2109 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2111 if (LHSMask.getNode()) {
2112 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2113 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2115 if (RHSMask.getNode()) {
2116 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2117 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2120 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2123 return Rot.getNode();
2126 // If there is a mask here, and we have a variable shift, we can't be sure
2127 // that we're masking out the right stuff.
2128 if (LHSMask.getNode() || RHSMask.getNode())
2131 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2132 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2133 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2134 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2135 if (ConstantSDNode *SUBC =
2136 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2137 if (SUBC->getAPIntValue() == OpSizeInBits) {
2139 return DAG.getNode(ISD::ROTL, DL, VT,
2140 LHSShiftArg, LHSShiftAmt).getNode();
2142 return DAG.getNode(ISD::ROTR, DL, VT,
2143 LHSShiftArg, RHSShiftAmt).getNode();
2148 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2149 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2150 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2151 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2152 if (ConstantSDNode *SUBC =
2153 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2154 if (SUBC->getAPIntValue() == OpSizeInBits) {
2156 return DAG.getNode(ISD::ROTR, DL, VT,
2157 LHSShiftArg, RHSShiftAmt).getNode();
2159 return DAG.getNode(ISD::ROTL, DL, VT,
2160 LHSShiftArg, LHSShiftAmt).getNode();
2165 // Look for sign/zext/any-extended or truncate cases:
2166 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2167 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2168 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2169 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2170 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2171 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2172 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2173 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2174 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2175 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2176 if (RExtOp0.getOpcode() == ISD::SUB &&
2177 RExtOp0.getOperand(1) == LExtOp0) {
2178 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2180 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2181 // (rotr x, (sub 32, y))
2182 if (ConstantSDNode *SUBC =
2183 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2184 if (SUBC->getAPIntValue() == OpSizeInBits) {
2185 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2187 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2190 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2191 RExtOp0 == LExtOp0.getOperand(1)) {
2192 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2194 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2195 // (rotl x, (sub 32, y))
2196 if (ConstantSDNode *SUBC =
2197 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2198 if (SUBC->getAPIntValue() == OpSizeInBits) {
2199 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2201 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2210 SDValue DAGCombiner::visitXOR(SDNode *N) {
2211 SDValue N0 = N->getOperand(0);
2212 SDValue N1 = N->getOperand(1);
2213 SDValue LHS, RHS, CC;
2214 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2215 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2216 MVT VT = N0.getValueType();
2219 if (VT.isVector()) {
2220 SDValue FoldedVOp = SimplifyVBinOp(N);
2221 if (FoldedVOp.getNode()) return FoldedVOp;
2224 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2225 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2226 return DAG.getConstant(0, VT);
2227 // fold (xor x, undef) -> undef
2228 if (N0.getOpcode() == ISD::UNDEF)
2230 if (N1.getOpcode() == ISD::UNDEF)
2232 // fold (xor c1, c2) -> c1^c2
2234 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2235 // canonicalize constant to RHS
2237 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2238 // fold (xor x, 0) -> x
2239 if (N1C && N1C->isNullValue())
2242 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2243 if (RXOR.getNode() != 0)
2246 // fold !(x cc y) -> (x !cc y)
2247 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2248 bool isInt = LHS.getValueType().isInteger();
2249 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2252 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2253 switch (N0.getOpcode()) {
2255 assert(0 && "Unhandled SetCC Equivalent!");
2258 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2259 case ISD::SELECT_CC:
2260 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2261 N0.getOperand(3), NotCC);
2266 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2267 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2268 N0.getNode()->hasOneUse() &&
2269 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2270 SDValue V = N0.getOperand(0);
2271 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2272 DAG.getConstant(1, V.getValueType()));
2273 AddToWorkList(V.getNode());
2274 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2277 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2278 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2279 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2280 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2281 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2282 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2283 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2284 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2285 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2286 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2289 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2290 if (N1C && N1C->isAllOnesValue() &&
2291 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2292 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2293 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2294 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2295 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2296 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2297 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2298 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2301 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2302 if (N1C && N0.getOpcode() == ISD::XOR) {
2303 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2304 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2306 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2307 DAG.getConstant(N1C->getAPIntValue() ^
2308 N00C->getAPIntValue(), VT));
2310 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2311 DAG.getConstant(N1C->getAPIntValue() ^
2312 N01C->getAPIntValue(), VT));
2314 // fold (xor x, x) -> 0
2316 if (!VT.isVector()) {
2317 return DAG.getConstant(0, VT);
2318 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2319 // Produce a vector of zeros.
2320 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2321 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2322 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2323 &Ops[0], Ops.size());
2327 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2328 if (N0.getOpcode() == N1.getOpcode()) {
2329 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2330 if (Tmp.getNode()) return Tmp;
2333 // Simplify the expression using non-local knowledge.
2334 if (!VT.isVector() &&
2335 SimplifyDemandedBits(SDValue(N, 0)))
2336 return SDValue(N, 0);
2341 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2342 /// the shift amount is a constant.
2343 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2344 SDNode *LHS = N->getOperand(0).getNode();
2345 if (!LHS->hasOneUse()) return SDValue();
2347 // We want to pull some binops through shifts, so that we have (and (shift))
2348 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2349 // thing happens with address calculations, so it's important to canonicalize
2351 bool HighBitSet = false; // Can we transform this if the high bit is set?
2353 switch (LHS->getOpcode()) {
2354 default: return SDValue();
2357 HighBitSet = false; // We can only transform sra if the high bit is clear.
2360 HighBitSet = true; // We can only transform sra if the high bit is set.
2363 if (N->getOpcode() != ISD::SHL)
2364 return SDValue(); // only shl(add) not sr[al](add).
2365 HighBitSet = false; // We can only transform sra if the high bit is clear.
2369 // We require the RHS of the binop to be a constant as well.
2370 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2371 if (!BinOpCst) return SDValue();
2373 // FIXME: disable this unless the input to the binop is a shift by a constant.
2374 // If it is not a shift, it pessimizes some common cases like:
2376 // void foo(int *X, int i) { X[i & 1235] = 1; }
2377 // int bar(int *X, int i) { return X[i & 255]; }
2378 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2379 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2380 BinOpLHSVal->getOpcode() != ISD::SRA &&
2381 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2382 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2385 MVT VT = N->getValueType(0);
2387 // If this is a signed shift right, and the high bit is modified by the
2388 // logical operation, do not perform the transformation. The highBitSet
2389 // boolean indicates the value of the high bit of the constant which would
2390 // cause it to be modified for this operation.
2391 if (N->getOpcode() == ISD::SRA) {
2392 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2393 if (BinOpRHSSignSet != HighBitSet)
2397 // Fold the constants, shifting the binop RHS by the shift amount.
2398 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2400 LHS->getOperand(1), N->getOperand(1));
2402 // Create the new shift.
2403 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2404 VT, LHS->getOperand(0), N->getOperand(1));
2406 // Create the new binop.
2407 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2410 SDValue DAGCombiner::visitSHL(SDNode *N) {
2411 SDValue N0 = N->getOperand(0);
2412 SDValue N1 = N->getOperand(1);
2413 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2414 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2415 MVT VT = N0.getValueType();
2416 unsigned OpSizeInBits = VT.getSizeInBits();
2418 // fold (shl c1, c2) -> c1<<c2
2420 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2421 // fold (shl 0, x) -> 0
2422 if (N0C && N0C->isNullValue())
2424 // fold (shl x, c >= size(x)) -> undef
2425 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2426 return DAG.getUNDEF(VT);
2427 // fold (shl x, 0) -> x
2428 if (N1C && N1C->isNullValue())
2430 // if (shl x, c) is known to be zero, return 0
2431 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2432 APInt::getAllOnesValue(VT.getSizeInBits())))
2433 return DAG.getConstant(0, VT);
2434 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2435 if (N1.getOpcode() == ISD::TRUNCATE &&
2436 N1.getOperand(0).getOpcode() == ISD::AND &&
2437 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2438 SDValue N101 = N1.getOperand(0).getOperand(1);
2439 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2440 MVT TruncVT = N1.getValueType();
2441 SDValue N100 = N1.getOperand(0).getOperand(0);
2442 APInt TruncC = N101C->getAPIntValue();
2443 TruncC.trunc(TruncVT.getSizeInBits());
2444 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2445 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2446 DAG.getNode(ISD::TRUNCATE,
2449 DAG.getConstant(TruncC, TruncVT)));
2453 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2454 return SDValue(N, 0);
2456 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2457 if (N1C && N0.getOpcode() == ISD::SHL &&
2458 N0.getOperand(1).getOpcode() == ISD::Constant) {
2459 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2460 uint64_t c2 = N1C->getZExtValue();
2461 if (c1 + c2 > OpSizeInBits)
2462 return DAG.getConstant(0, VT);
2463 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2464 DAG.getConstant(c1 + c2, N1.getValueType()));
2466 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2467 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2468 if (N1C && N0.getOpcode() == ISD::SRL &&
2469 N0.getOperand(1).getOpcode() == ISD::Constant) {
2470 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2471 uint64_t c2 = N1C->getZExtValue();
2472 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, N0.getOperand(0),
2473 DAG.getConstant(~0ULL << c1, VT));
2475 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2476 DAG.getConstant(c2-c1, N1.getValueType()));
2478 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2479 DAG.getConstant(c1-c2, N1.getValueType()));
2481 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2482 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2483 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2484 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT));
2486 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2489 SDValue DAGCombiner::visitSRA(SDNode *N) {
2490 SDValue N0 = N->getOperand(0);
2491 SDValue N1 = N->getOperand(1);
2492 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2493 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2494 MVT VT = N0.getValueType();
2496 // fold (sra c1, c2) -> (sra c1, c2)
2498 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2499 // fold (sra 0, x) -> 0
2500 if (N0C && N0C->isNullValue())
2502 // fold (sra -1, x) -> -1
2503 if (N0C && N0C->isAllOnesValue())
2505 // fold (sra x, (setge c, size(x))) -> undef
2506 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits())
2507 return DAG.getUNDEF(VT);
2508 // fold (sra x, 0) -> x
2509 if (N1C && N1C->isNullValue())
2511 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2513 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2514 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
2515 MVT EVT = MVT::getIntegerVT(LowBits);
2516 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
2517 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2518 N0.getOperand(0), DAG.getValueType(EVT));
2521 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2522 if (N1C && N0.getOpcode() == ISD::SRA) {
2523 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2524 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2525 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
2526 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2527 DAG.getConstant(Sum, N1C->getValueType(0)));
2531 // fold (sra (shl X, m), (sub result_size, n))
2532 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2533 // result_size - n != m.
2534 // If truncate is free for the target sext(shl) is likely to result in better
2536 if (N0.getOpcode() == ISD::SHL) {
2537 // Get the two constanst of the shifts, CN0 = m, CN = n.
2538 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2540 // Determine what the truncate's result bitsize and type would be.
2541 unsigned VTValSize = VT.getSizeInBits();
2543 MVT::getIntegerVT(VTValSize - N1C->getZExtValue());
2544 // Determine the residual right-shift amount.
2545 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2547 // If the shift is not a no-op (in which case this should be just a sign
2548 // extend already), the truncated to type is legal, sign_extend is legal
2549 // on that type, and the the truncate to that type is both legal and free,
2550 // perform the transform.
2552 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2553 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
2554 TLI.isTruncateFree(VT, TruncVT)) {
2556 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
2557 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
2558 N0.getOperand(0), Amt);
2559 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
2561 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
2562 N->getValueType(0), Trunc);
2567 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
2568 if (N1.getOpcode() == ISD::TRUNCATE &&
2569 N1.getOperand(0).getOpcode() == ISD::AND &&
2570 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2571 SDValue N101 = N1.getOperand(0).getOperand(1);
2572 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2573 MVT TruncVT = N1.getValueType();
2574 SDValue N100 = N1.getOperand(0).getOperand(0);
2575 APInt TruncC = N101C->getAPIntValue();
2576 TruncC.trunc(TruncVT.getSizeInBits());
2577 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
2578 DAG.getNode(ISD::AND, N->getDebugLoc(),
2580 DAG.getNode(ISD::TRUNCATE,
2583 DAG.getConstant(TruncC, TruncVT)));
2587 // Simplify, based on bits shifted out of the LHS.
2588 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2589 return SDValue(N, 0);
2592 // If the sign bit is known to be zero, switch this to a SRL.
2593 if (DAG.SignBitIsZero(N0))
2594 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
2596 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2599 SDValue DAGCombiner::visitSRL(SDNode *N) {
2600 SDValue N0 = N->getOperand(0);
2601 SDValue N1 = N->getOperand(1);
2602 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2603 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2604 MVT VT = N0.getValueType();
2605 unsigned OpSizeInBits = VT.getSizeInBits();
2607 // fold (srl c1, c2) -> c1 >>u c2
2609 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
2610 // fold (srl 0, x) -> 0
2611 if (N0C && N0C->isNullValue())
2613 // fold (srl x, c >= size(x)) -> undef
2614 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2615 return DAG.getUNDEF(VT);
2616 // fold (srl x, 0) -> x
2617 if (N1C && N1C->isNullValue())
2619 // if (srl x, c) is known to be zero, return 0
2620 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2621 APInt::getAllOnesValue(OpSizeInBits)))
2622 return DAG.getConstant(0, VT);
2624 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
2625 if (N1C && N0.getOpcode() == ISD::SRL &&
2626 N0.getOperand(1).getOpcode() == ISD::Constant) {
2627 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2628 uint64_t c2 = N1C->getZExtValue();
2629 if (c1 + c2 > OpSizeInBits)
2630 return DAG.getConstant(0, VT);
2631 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
2632 DAG.getConstant(c1 + c2, N1.getValueType()));
2635 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2636 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2637 // Shifting in all undef bits?
2638 MVT SmallVT = N0.getOperand(0).getValueType();
2639 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
2640 return DAG.getUNDEF(VT);
2642 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
2643 N0.getOperand(0), N1);
2644 AddToWorkList(SmallShift.getNode());
2645 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
2648 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2649 // bit, which is unmodified by sra.
2650 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
2651 if (N0.getOpcode() == ISD::SRA)
2652 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
2655 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2656 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2657 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
2658 APInt KnownZero, KnownOne;
2659 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
2660 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2662 // If any of the input bits are KnownOne, then the input couldn't be all
2663 // zeros, thus the result of the srl will always be zero.
2664 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
2666 // If all of the bits input the to ctlz node are known to be zero, then
2667 // the result of the ctlz is "32" and the result of the shift is one.
2668 APInt UnknownBits = ~KnownZero & Mask;
2669 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2671 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2672 if ((UnknownBits & (UnknownBits - 1)) == 0) {
2673 // Okay, we know that only that the single bit specified by UnknownBits
2674 // could be set on input to the CTLZ node. If this bit is set, the SRL
2675 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2676 // to an SRL/XOR pair, which is likely to simplify more.
2677 unsigned ShAmt = UnknownBits.countTrailingZeros();
2678 SDValue Op = N0.getOperand(0);
2681 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
2682 DAG.getConstant(ShAmt, getShiftAmountTy()));
2683 AddToWorkList(Op.getNode());
2686 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
2687 Op, DAG.getConstant(1, VT));
2691 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
2692 if (N1.getOpcode() == ISD::TRUNCATE &&
2693 N1.getOperand(0).getOpcode() == ISD::AND &&
2694 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2695 SDValue N101 = N1.getOperand(0).getOperand(1);
2696 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2697 MVT TruncVT = N1.getValueType();
2698 SDValue N100 = N1.getOperand(0).getOperand(0);
2699 APInt TruncC = N101C->getAPIntValue();
2700 TruncC.trunc(TruncVT.getSizeInBits());
2701 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
2702 DAG.getNode(ISD::AND, N->getDebugLoc(),
2704 DAG.getNode(ISD::TRUNCATE,
2707 DAG.getConstant(TruncC, TruncVT)));
2711 // fold operands of srl based on knowledge that the low bits are not
2713 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2714 return SDValue(N, 0);
2716 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue();
2719 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
2720 SDValue N0 = N->getOperand(0);
2721 MVT VT = N->getValueType(0);
2723 // fold (ctlz c1) -> c2
2724 if (isa<ConstantSDNode>(N0))
2725 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
2729 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
2730 SDValue N0 = N->getOperand(0);
2731 MVT VT = N->getValueType(0);
2733 // fold (cttz c1) -> c2
2734 if (isa<ConstantSDNode>(N0))
2735 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
2739 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
2740 SDValue N0 = N->getOperand(0);
2741 MVT VT = N->getValueType(0);
2743 // fold (ctpop c1) -> c2
2744 if (isa<ConstantSDNode>(N0))
2745 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
2749 SDValue DAGCombiner::visitSELECT(SDNode *N) {
2750 SDValue N0 = N->getOperand(0);
2751 SDValue N1 = N->getOperand(1);
2752 SDValue N2 = N->getOperand(2);
2753 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2754 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2755 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2756 MVT VT = N->getValueType(0);
2757 MVT VT0 = N0.getValueType();
2759 // fold (select C, X, X) -> X
2762 // fold (select true, X, Y) -> X
2763 if (N0C && !N0C->isNullValue())
2765 // fold (select false, X, Y) -> Y
2766 if (N0C && N0C->isNullValue())
2768 // fold (select C, 1, X) -> (or C, X)
2769 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
2770 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2771 // fold (select C, 0, 1) -> (xor C, 1)
2772 if (VT.isInteger() &&
2775 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
2776 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
2779 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
2780 N0, DAG.getConstant(1, VT0));
2781 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
2782 N0, DAG.getConstant(1, VT0));
2783 AddToWorkList(XORNode.getNode());
2785 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
2786 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
2788 // fold (select C, 0, X) -> (and (not C), X)
2789 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
2790 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2791 AddToWorkList(NOTNode.getNode());
2792 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
2794 // fold (select C, X, 1) -> (or (not C), X)
2795 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
2796 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
2797 AddToWorkList(NOTNode.getNode());
2798 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
2800 // fold (select C, X, 0) -> (and C, X)
2801 if (VT == MVT::i1 && N2C && N2C->isNullValue())
2802 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2803 // fold (select X, X, Y) -> (or X, Y)
2804 // fold (select X, 1, Y) -> (or X, Y)
2805 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
2806 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
2807 // fold (select X, Y, X) -> (and X, Y)
2808 // fold (select X, Y, 0) -> (and X, Y)
2809 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
2810 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
2812 // If we can fold this based on the true/false value, do so.
2813 if (SimplifySelectOps(N, N1, N2))
2814 return SDValue(N, 0); // Don't revisit N.
2816 // fold selects based on a setcc into other things, such as min/max/abs
2817 if (N0.getOpcode() == ISD::SETCC) {
2819 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2820 // having to say they don't support SELECT_CC on every type the DAG knows
2821 // about, since there is no way to mark an opcode illegal at all value types
2822 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other))
2823 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
2824 N0.getOperand(0), N0.getOperand(1),
2825 N1, N2, N0.getOperand(2));
2826 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
2832 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
2833 SDValue N0 = N->getOperand(0);
2834 SDValue N1 = N->getOperand(1);
2835 SDValue N2 = N->getOperand(2);
2836 SDValue N3 = N->getOperand(3);
2837 SDValue N4 = N->getOperand(4);
2838 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2840 // fold select_cc lhs, rhs, x, x, cc -> x
2844 // Determine if the condition we're dealing with is constant
2845 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
2846 N0, N1, CC, N->getDebugLoc(), false);
2847 if (SCC.getNode()) AddToWorkList(SCC.getNode());
2849 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
2850 if (!SCCC->isNullValue())
2851 return N2; // cond always true -> true val
2853 return N3; // cond always false -> false val
2856 // Fold to a simpler select_cc
2857 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
2858 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
2859 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2862 // If we can fold this based on the true/false value, do so.
2863 if (SimplifySelectOps(N, N2, N3))
2864 return SDValue(N, 0); // Don't revisit N.
2866 // fold select_cc into other things, such as min/max/abs
2867 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
2870 SDValue DAGCombiner::visitSETCC(SDNode *N) {
2871 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2872 cast<CondCodeSDNode>(N->getOperand(2))->get(),
2876 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
2877 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
2878 // transformation. Returns true if extension are possible and the above
2879 // mentioned transformation is profitable.
2880 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
2882 SmallVector<SDNode*, 4> &ExtendNodes,
2883 const TargetLowering &TLI) {
2884 bool HasCopyToRegUses = false;
2885 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
2886 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
2887 UE = N0.getNode()->use_end();
2892 if (UI.getUse().getResNo() != N0.getResNo())
2894 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
2895 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
2896 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
2897 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
2898 // Sign bits will be lost after a zext.
2901 for (unsigned i = 0; i != 2; ++i) {
2902 SDValue UseOp = User->getOperand(i);
2905 if (!isa<ConstantSDNode>(UseOp))
2910 ExtendNodes.push_back(User);
2913 // If truncates aren't free and there are users we can't
2914 // extend, it isn't worthwhile.
2917 // Remember if this value is live-out.
2918 if (User->getOpcode() == ISD::CopyToReg)
2919 HasCopyToRegUses = true;
2922 if (HasCopyToRegUses) {
2923 bool BothLiveOut = false;
2924 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
2926 SDUse &Use = UI.getUse();
2927 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
2933 // Both unextended and extended values are live out. There had better be
2934 // good a reason for the transformation.
2935 return ExtendNodes.size();
2940 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2941 SDValue N0 = N->getOperand(0);
2942 MVT VT = N->getValueType(0);
2944 // fold (sext c1) -> c1
2945 if (isa<ConstantSDNode>(N0))
2946 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
2948 // fold (sext (sext x)) -> (sext x)
2949 // fold (sext (aext x)) -> (sext x)
2950 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2951 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
2954 if (N0.getOpcode() == ISD::TRUNCATE) {
2955 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2956 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2957 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
2958 if (NarrowLoad.getNode()) {
2959 if (NarrowLoad.getNode() != N0.getNode())
2960 CombineTo(N0.getNode(), NarrowLoad);
2961 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
2964 // See if the value being truncated is already sign extended. If so, just
2965 // eliminate the trunc/sext pair.
2966 SDValue Op = N0.getOperand(0);
2967 unsigned OpBits = Op.getValueType().getSizeInBits();
2968 unsigned MidBits = N0.getValueType().getSizeInBits();
2969 unsigned DestBits = VT.getSizeInBits();
2970 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2972 if (OpBits == DestBits) {
2973 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2974 // bits, it is already ready.
2975 if (NumSignBits > DestBits-MidBits)
2977 } else if (OpBits < DestBits) {
2978 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2979 // bits, just sext from i32.
2980 if (NumSignBits > OpBits-MidBits)
2981 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
2983 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2984 // bits, just truncate to i32.
2985 if (NumSignBits > OpBits-MidBits)
2986 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
2989 // fold (sext (truncate x)) -> (sextinreg x).
2990 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2991 N0.getValueType())) {
2992 if (Op.getValueType().bitsLT(VT))
2993 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
2994 else if (Op.getValueType().bitsGT(VT))
2995 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
2996 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
2997 DAG.getValueType(N0.getValueType()));
3001 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3002 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3003 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3004 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3005 bool DoXform = true;
3006 SmallVector<SDNode*, 4> SetCCs;
3007 if (!N0.hasOneUse())
3008 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3010 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3011 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3013 LN0->getBasePtr(), LN0->getSrcValue(),
3014 LN0->getSrcValueOffset(),
3016 LN0->isVolatile(), LN0->getAlignment());
3017 CombineTo(N, ExtLoad);
3018 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3019 N0.getValueType(), ExtLoad);
3020 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3022 // Extend SetCC uses if necessary.
3023 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3024 SDNode *SetCC = SetCCs[i];
3025 SmallVector<SDValue, 4> Ops;
3027 for (unsigned j = 0; j != 2; ++j) {
3028 SDValue SOp = SetCC->getOperand(j);
3030 Ops.push_back(ExtLoad);
3032 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3033 N->getDebugLoc(), VT, SOp));
3036 Ops.push_back(SetCC->getOperand(2));
3037 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3038 SetCC->getValueType(0),
3039 &Ops[0], Ops.size()));
3042 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3046 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3047 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3048 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3049 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3050 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3051 MVT EVT = LN0->getMemoryVT();
3052 if ((!LegalOperations && !LN0->isVolatile()) ||
3053 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) {
3054 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3056 LN0->getBasePtr(), LN0->getSrcValue(),
3057 LN0->getSrcValueOffset(), EVT,
3058 LN0->isVolatile(), LN0->getAlignment());
3059 CombineTo(N, ExtLoad);
3060 CombineTo(N0.getNode(),
3061 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3062 N0.getValueType(), ExtLoad),
3063 ExtLoad.getValue(1));
3064 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3068 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3069 if (N0.getOpcode() == ISD::SETCC) {
3071 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3072 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
3073 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3074 if (SCC.getNode()) return SCC;
3077 // fold (sext x) -> (zext x) if the sign bit is known zero.
3078 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3079 DAG.SignBitIsZero(N0))
3080 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3085 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3086 SDValue N0 = N->getOperand(0);
3087 MVT VT = N->getValueType(0);
3089 // fold (zext c1) -> c1
3090 if (isa<ConstantSDNode>(N0))
3091 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3092 // fold (zext (zext x)) -> (zext x)
3093 // fold (zext (aext x)) -> (zext x)
3094 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3095 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3098 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3099 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3100 if (N0.getOpcode() == ISD::TRUNCATE) {
3101 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3102 if (NarrowLoad.getNode()) {
3103 if (NarrowLoad.getNode() != N0.getNode())
3104 CombineTo(N0.getNode(), NarrowLoad);
3105 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3109 // fold (zext (truncate x)) -> (and x, mask)
3110 if (N0.getOpcode() == ISD::TRUNCATE &&
3111 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
3112 SDValue Op = N0.getOperand(0);
3113 if (Op.getValueType().bitsLT(VT)) {
3114 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3115 } else if (Op.getValueType().bitsGT(VT)) {
3116 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3118 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType());
3121 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
3122 // if either of the casts is not free.
3123 if (N0.getOpcode() == ISD::AND &&
3124 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3125 N0.getOperand(1).getOpcode() == ISD::Constant &&
3126 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3127 N0.getValueType()) ||
3128 !TLI.isZExtFree(N0.getValueType(), VT))) {
3129 SDValue X = N0.getOperand(0).getOperand(0);
3130 if (X.getValueType().bitsLT(VT)) {
3131 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3132 } else if (X.getValueType().bitsGT(VT)) {
3133 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3135 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3136 Mask.zext(VT.getSizeInBits());
3137 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3138 X, DAG.getConstant(Mask, VT));
3141 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3142 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3143 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3144 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3145 bool DoXform = true;
3146 SmallVector<SDNode*, 4> SetCCs;
3147 if (!N0.hasOneUse())
3148 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3150 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3151 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3153 LN0->getBasePtr(), LN0->getSrcValue(),
3154 LN0->getSrcValueOffset(),
3156 LN0->isVolatile(), LN0->getAlignment());
3157 CombineTo(N, ExtLoad);
3158 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3159 N0.getValueType(), ExtLoad);
3160 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3162 // Extend SetCC uses if necessary.
3163 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3164 SDNode *SetCC = SetCCs[i];
3165 SmallVector<SDValue, 4> Ops;
3167 for (unsigned j = 0; j != 2; ++j) {
3168 SDValue SOp = SetCC->getOperand(j);
3170 Ops.push_back(ExtLoad);
3172 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3173 N->getDebugLoc(), VT, SOp));
3176 Ops.push_back(SetCC->getOperand(2));
3177 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3178 SetCC->getValueType(0),
3179 &Ops[0], Ops.size()));
3182 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3186 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3187 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3188 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3189 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3190 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3191 MVT EVT = LN0->getMemoryVT();
3192 if ((!LegalOperations && !LN0->isVolatile()) ||
3193 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) {
3194 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3196 LN0->getBasePtr(), LN0->getSrcValue(),
3197 LN0->getSrcValueOffset(), EVT,
3198 LN0->isVolatile(), LN0->getAlignment());
3199 CombineTo(N, ExtLoad);
3200 CombineTo(N0.getNode(),
3201 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3203 ExtLoad.getValue(1));
3204 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3208 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3209 if (N0.getOpcode() == ISD::SETCC) {
3211 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3212 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3213 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3214 if (SCC.getNode()) return SCC;
3220 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3221 SDValue N0 = N->getOperand(0);
3222 MVT VT = N->getValueType(0);
3224 // fold (aext c1) -> c1
3225 if (isa<ConstantSDNode>(N0))
3226 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3227 // fold (aext (aext x)) -> (aext x)
3228 // fold (aext (zext x)) -> (zext x)
3229 // fold (aext (sext x)) -> (sext x)
3230 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3231 N0.getOpcode() == ISD::ZERO_EXTEND ||
3232 N0.getOpcode() == ISD::SIGN_EXTEND)
3233 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3235 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3236 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3237 if (N0.getOpcode() == ISD::TRUNCATE) {
3238 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3239 if (NarrowLoad.getNode()) {
3240 if (NarrowLoad.getNode() != N0.getNode())
3241 CombineTo(N0.getNode(), NarrowLoad);
3242 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3246 // fold (aext (truncate x))
3247 if (N0.getOpcode() == ISD::TRUNCATE) {
3248 SDValue TruncOp = N0.getOperand(0);
3249 if (TruncOp.getValueType() == VT)
3250 return TruncOp; // x iff x size == zext size.
3251 if (TruncOp.getValueType().bitsGT(VT))
3252 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3253 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3256 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
3257 // if the trunc is not free.
3258 if (N0.getOpcode() == ISD::AND &&
3259 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3260 N0.getOperand(1).getOpcode() == ISD::Constant &&
3261 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3262 N0.getValueType())) {
3263 SDValue X = N0.getOperand(0).getOperand(0);
3264 if (X.getValueType().bitsLT(VT)) {
3265 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3266 } else if (X.getValueType().bitsGT(VT)) {
3267 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3269 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3270 Mask.zext(VT.getSizeInBits());
3271 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3272 X, DAG.getConstant(Mask, VT));
3275 // fold (aext (load x)) -> (aext (truncate (extload x)))
3276 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3277 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3278 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3279 bool DoXform = true;
3280 SmallVector<SDNode*, 4> SetCCs;
3281 if (!N0.hasOneUse())
3282 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
3284 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3285 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
3287 LN0->getBasePtr(), LN0->getSrcValue(),
3288 LN0->getSrcValueOffset(),
3290 LN0->isVolatile(), LN0->getAlignment());
3291 CombineTo(N, ExtLoad);
3292 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3293 N0.getValueType(), ExtLoad);
3294 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3296 // Extend SetCC uses if necessary.
3297 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3298 SDNode *SetCC = SetCCs[i];
3299 SmallVector<SDValue, 4> Ops;
3301 for (unsigned j = 0; j != 2; ++j) {
3302 SDValue SOp = SetCC->getOperand(j);
3304 Ops.push_back(ExtLoad);
3306 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
3307 N->getDebugLoc(), VT, SOp));
3310 Ops.push_back(SetCC->getOperand(2));
3311 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3312 SetCC->getValueType(0),
3313 &Ops[0], Ops.size()));
3316 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3320 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3321 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3322 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3323 if (N0.getOpcode() == ISD::LOAD &&
3324 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3326 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3327 MVT EVT = LN0->getMemoryVT();
3328 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
3329 VT, LN0->getChain(), LN0->getBasePtr(),
3331 LN0->getSrcValueOffset(), EVT,
3332 LN0->isVolatile(), LN0->getAlignment());
3333 CombineTo(N, ExtLoad);
3334 CombineTo(N0.getNode(),
3335 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3336 N0.getValueType(), ExtLoad),
3337 ExtLoad.getValue(1));
3338 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3341 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3342 if (N0.getOpcode() == ISD::SETCC) {
3344 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3345 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3346 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3354 /// GetDemandedBits - See if the specified operand can be simplified with the
3355 /// knowledge that only the bits specified by Mask are used. If so, return the
3356 /// simpler operand, otherwise return a null SDValue.
3357 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
3358 switch (V.getOpcode()) {
3362 // If the LHS or RHS don't contribute bits to the or, drop them.
3363 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3364 return V.getOperand(1);
3365 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3366 return V.getOperand(0);
3369 // Only look at single-use SRLs.
3370 if (!V.getNode()->hasOneUse())
3372 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3373 // See if we can recursively simplify the LHS.
3374 unsigned Amt = RHSC->getZExtValue();
3376 // Watch out for shift count overflow though.
3377 if (Amt >= Mask.getBitWidth()) break;
3378 APInt NewMask = Mask << Amt;
3379 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
3380 if (SimplifyLHS.getNode())
3381 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
3382 SimplifyLHS, V.getOperand(1));
3388 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3389 /// bits and then truncated to a narrower type and where N is a multiple
3390 /// of number of bits of the narrower type, transform it to a narrower load
3391 /// from address + N / num of bits of new type. If the result is to be
3392 /// extended, also fold the extension to form a extending load.
3393 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
3394 unsigned Opc = N->getOpcode();
3395 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3396 SDValue N0 = N->getOperand(0);
3397 MVT VT = N->getValueType(0);
3400 // This transformation isn't valid for vector loads.
3404 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
3406 if (Opc == ISD::SIGN_EXTEND_INREG) {
3407 ExtType = ISD::SEXTLOAD;
3408 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3409 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))
3413 unsigned EVTBits = EVT.getSizeInBits();
3415 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
3416 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3417 ShAmt = N01->getZExtValue();
3418 // Is the shift amount a multiple of size of VT?
3419 if ((ShAmt & (EVTBits-1)) == 0) {
3420 N0 = N0.getOperand(0);
3421 if (N0.getValueType().getSizeInBits() <= EVTBits)
3427 // Do not generate loads of non-round integer types since these can
3428 // be expensive (and would be wrong if the type is not byte sized).
3429 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() &&
3430 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
3431 // Do not change the width of a volatile load.
3432 !cast<LoadSDNode>(N0)->isVolatile()) {
3433 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3434 MVT PtrType = N0.getOperand(1).getValueType();
3436 // For big endian targets, we need to adjust the offset to the pointer to
3437 // load the correct bytes.
3438 if (TLI.isBigEndian()) {
3439 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
3440 unsigned EVTStoreBits = EVT.getStoreSizeInBits();
3441 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3444 uint64_t PtrOff = ShAmt / 8;
3445 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3446 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
3447 PtrType, LN0->getBasePtr(),
3448 DAG.getConstant(PtrOff, PtrType));
3449 AddToWorkList(NewPtr.getNode());
3451 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
3452 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
3453 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3454 LN0->isVolatile(), NewAlign)
3455 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
3456 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3457 EVT, LN0->isVolatile(), NewAlign);
3459 // Replace the old load's chain with the new load's chain.
3460 WorkListRemover DeadNodes(*this);
3461 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
3464 // Return the new loaded value.
3471 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3472 SDValue N0 = N->getOperand(0);
3473 SDValue N1 = N->getOperand(1);
3474 MVT VT = N->getValueType(0);
3475 MVT EVT = cast<VTSDNode>(N1)->getVT();
3476 unsigned VTBits = VT.getSizeInBits();
3477 unsigned EVTBits = EVT.getSizeInBits();
3479 // fold (sext_in_reg c1) -> c1
3480 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3481 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
3483 // If the input is already sign extended, just drop the extension.
3484 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
3487 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3488 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3489 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
3490 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3491 N0.getOperand(0), N1);
3494 // fold (sext_in_reg (sext x)) -> (sext x)
3495 // fold (sext_in_reg (aext x)) -> (sext x)
3496 // if x is small enough.
3497 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
3498 SDValue N00 = N0.getOperand(0);
3499 if (N00.getValueType().getSizeInBits() < EVTBits)
3500 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
3503 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3504 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
3505 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
3507 // fold operands of sext_in_reg based on knowledge that the top bits are not
3509 if (SimplifyDemandedBits(SDValue(N, 0)))
3510 return SDValue(N, 0);
3512 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3513 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3514 SDValue NarrowLoad = ReduceLoadWidth(N);
3515 if (NarrowLoad.getNode())
3518 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
3519 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
3520 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3521 if (N0.getOpcode() == ISD::SRL) {
3522 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3523 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) {
3524 // We can turn this into an SRA iff the input to the SRL is already sign
3526 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3527 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
3528 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
3529 N0.getOperand(0), N0.getOperand(1));
3533 // fold (sext_inreg (extload x)) -> (sextload x)
3534 if (ISD::isEXTLoad(N0.getNode()) &&
3535 ISD::isUNINDEXEDLoad(N0.getNode()) &&
3536 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3537 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3538 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3539 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3540 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3542 LN0->getBasePtr(), LN0->getSrcValue(),
3543 LN0->getSrcValueOffset(), EVT,
3544 LN0->isVolatile(), LN0->getAlignment());
3545 CombineTo(N, ExtLoad);
3546 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3547 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3549 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3550 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3552 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3553 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3554 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3555 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3556 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3558 LN0->getBasePtr(), LN0->getSrcValue(),
3559 LN0->getSrcValueOffset(), EVT,
3560 LN0->isVolatile(), LN0->getAlignment());
3561 CombineTo(N, ExtLoad);
3562 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3563 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3568 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
3569 SDValue N0 = N->getOperand(0);
3570 MVT VT = N->getValueType(0);
3573 if (N0.getValueType() == N->getValueType(0))
3575 // fold (truncate c1) -> c1
3576 if (isa<ConstantSDNode>(N0))
3577 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
3578 // fold (truncate (truncate x)) -> (truncate x)
3579 if (N0.getOpcode() == ISD::TRUNCATE)
3580 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3581 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3582 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
3583 N0.getOpcode() == ISD::ANY_EXTEND) {
3584 if (N0.getOperand(0).getValueType().bitsLT(VT))
3585 // if the source is smaller than the dest, we still need an extend
3586 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
3588 else if (N0.getOperand(0).getValueType().bitsGT(VT))
3589 // if the source is larger than the dest, than we just need the truncate
3590 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3592 // if the source and dest are the same type, we can drop both the extend
3594 return N0.getOperand(0);
3597 // See if we can simplify the input to this truncate through knowledge that
3598 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3601 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3602 VT.getSizeInBits()));
3603 if (Shorter.getNode())
3604 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
3606 // fold (truncate (load x)) -> (smaller load x)
3607 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3608 return ReduceLoadWidth(N);
3611 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
3612 SDValue Elt = N->getOperand(i);
3613 if (Elt.getOpcode() != ISD::MERGE_VALUES)
3614 return Elt.getNode();
3615 return Elt.getOperand(Elt.getResNo()).getNode();
3618 /// CombineConsecutiveLoads - build_pair (load, load) -> load
3619 /// if load locations are consecutive.
3620 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
3621 assert(N->getOpcode() == ISD::BUILD_PAIR);
3623 SDNode *LD1 = getBuildPairElt(N, 0);
3624 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
3626 MVT LD1VT = LD1->getValueType(0);
3627 SDNode *LD2 = getBuildPairElt(N, 1);
3628 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3630 if (ISD::isNON_EXTLoad(LD2) &&
3632 // If both are volatile this would reduce the number of volatile loads.
3633 // If one is volatile it might be ok, but play conservative and bail out.
3634 !cast<LoadSDNode>(LD1)->isVolatile() &&
3635 !cast<LoadSDNode>(LD2)->isVolatile() &&
3636 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
3637 LoadSDNode *LD = cast<LoadSDNode>(LD1);
3638 unsigned Align = LD->getAlignment();
3639 unsigned NewAlign = TLI.getTargetData()->
3640 getABITypeAlignment(VT.getTypeForMVT());
3642 if (NewAlign <= Align &&
3643 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
3644 return DAG.getLoad(VT, N->getDebugLoc(), LD->getChain(), LD->getBasePtr(),
3645 LD->getSrcValue(), LD->getSrcValueOffset(),
3652 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3653 SDValue N0 = N->getOperand(0);
3654 MVT VT = N->getValueType(0);
3656 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3657 // Only do this before legalize, since afterward the target may be depending
3658 // on the bitconvert.
3659 // First check to see if this is all constant.
3661 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
3663 bool isSimple = true;
3664 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3665 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3666 N0.getOperand(i).getOpcode() != ISD::Constant &&
3667 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3672 MVT DestEltVT = N->getValueType(0).getVectorElementType();
3673 assert(!DestEltVT.isVector() &&
3674 "Element type of vector ValueType must not be vector!");
3676 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
3679 // If the input is a constant, let getNode fold it.
3680 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
3681 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
3682 if (Res.getNode() != N) return Res;
3685 // (conv (conv x, t1), t2) -> (conv x, t2)
3686 if (N0.getOpcode() == ISD::BIT_CONVERT)
3687 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
3690 // fold (conv (load x)) -> (load (conv*)x)
3691 // If the resultant load doesn't need a higher alignment than the original!
3692 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
3693 // Do not change the width of a volatile load.
3694 !cast<LoadSDNode>(N0)->isVolatile() &&
3695 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
3696 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3697 unsigned Align = TLI.getTargetData()->
3698 getABITypeAlignment(VT.getTypeForMVT());
3699 unsigned OrigAlign = LN0->getAlignment();
3701 if (Align <= OrigAlign) {
3702 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
3704 LN0->getSrcValue(), LN0->getSrcValueOffset(),
3705 LN0->isVolatile(), OrigAlign);
3707 CombineTo(N0.getNode(),
3708 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3709 N0.getValueType(), Load),
3715 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
3716 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
3717 // This often reduces constant pool loads.
3718 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3719 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
3720 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
3722 AddToWorkList(NewConv.getNode());
3724 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3725 if (N0.getOpcode() == ISD::FNEG)
3726 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3727 NewConv, DAG.getConstant(SignBit, VT));
3728 assert(N0.getOpcode() == ISD::FABS);
3729 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3730 NewConv, DAG.getConstant(~SignBit, VT));
3733 // fold (bitconvert (fcopysign cst, x)) ->
3734 // (or (and (bitconvert x), sign), (and cst, (not sign)))
3735 // Note that we don't handle (copysign x, cst) because this can always be
3736 // folded to an fneg or fabs.
3737 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
3738 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
3739 VT.isInteger() && !VT.isVector()) {
3740 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
3741 MVT IntXVT = MVT::getIntegerVT(OrigXWidth);
3742 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) {
3743 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3744 IntXVT, N0.getOperand(1));
3745 AddToWorkList(X.getNode());
3747 // If X has a different width than the result/lhs, sext it or truncate it.
3748 unsigned VTWidth = VT.getSizeInBits();
3749 if (OrigXWidth < VTWidth) {
3750 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
3751 AddToWorkList(X.getNode());
3752 } else if (OrigXWidth > VTWidth) {
3753 // To get the sign bit in the right place, we have to shift it right
3754 // before truncating.
3755 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
3756 X.getValueType(), X,
3757 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
3758 AddToWorkList(X.getNode());
3759 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3760 AddToWorkList(X.getNode());
3763 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
3764 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
3765 X, DAG.getConstant(SignBit, VT));
3766 AddToWorkList(X.getNode());
3768 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
3769 VT, N0.getOperand(0));
3770 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
3771 Cst, DAG.getConstant(~SignBit, VT));
3772 AddToWorkList(Cst.getNode());
3774 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
3778 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
3779 if (N0.getOpcode() == ISD::BUILD_PAIR) {
3780 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
3781 if (CombineLD.getNode())
3788 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
3789 MVT VT = N->getValueType(0);
3790 return CombineConsecutiveLoads(N, VT);
3793 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
3794 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
3795 /// destination element value type.
3796 SDValue DAGCombiner::
3797 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
3798 MVT SrcEltVT = BV->getValueType(0).getVectorElementType();
3800 // If this is already the right type, we're done.
3801 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
3803 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
3804 unsigned DstBitSize = DstEltVT.getSizeInBits();
3806 // If this is a conversion of N elements of one type to N elements of another
3807 // type, convert each element. This handles FP<->INT cases.
3808 if (SrcBitSize == DstBitSize) {
3809 SmallVector<SDValue, 8> Ops;
3810 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3811 SDValue Op = BV->getOperand(i);
3812 // If the vector element type is not legal, the BUILD_VECTOR operands
3813 // are promoted and implicitly truncated. Make that explicit here.
3814 if (Op.getValueType() != SrcEltVT)
3815 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
3816 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
3818 AddToWorkList(Ops.back().getNode());
3820 MVT VT = MVT::getVectorVT(DstEltVT,
3821 BV->getValueType(0).getVectorNumElements());
3822 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3823 &Ops[0], Ops.size());
3826 // Otherwise, we're growing or shrinking the elements. To avoid having to
3827 // handle annoying details of growing/shrinking FP values, we convert them to
3829 if (SrcEltVT.isFloatingPoint()) {
3830 // Convert the input float vector to a int vector where the elements are the
3832 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
3833 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
3834 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
3838 // Now we know the input is an integer vector. If the output is a FP type,
3839 // convert to integer first, then to FP of the right size.
3840 if (DstEltVT.isFloatingPoint()) {
3841 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
3842 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
3843 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
3845 // Next, convert to FP elements of the same size.
3846 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
3849 // Okay, we know the src/dst types are both integers of differing types.
3850 // Handling growing first.
3851 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
3852 if (SrcBitSize < DstBitSize) {
3853 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
3855 SmallVector<SDValue, 8> Ops;
3856 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
3857 i += NumInputsPerOutput) {
3858 bool isLE = TLI.isLittleEndian();
3859 APInt NewBits = APInt(DstBitSize, 0);
3860 bool EltIsUndef = true;
3861 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
3862 // Shift the previously computed bits over.
3863 NewBits <<= SrcBitSize;
3864 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
3865 if (Op.getOpcode() == ISD::UNDEF) continue;
3868 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).
3869 zextOrTrunc(SrcBitSize).zext(DstBitSize));
3873 Ops.push_back(DAG.getUNDEF(DstEltVT));
3875 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
3878 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size());
3879 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3880 &Ops[0], Ops.size());
3883 // Finally, this must be the case where we are shrinking elements: each input
3884 // turns into multiple outputs.
3885 bool isS2V = ISD::isScalarToVector(BV);
3886 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3887 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
3888 SmallVector<SDValue, 8> Ops;
3890 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3891 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3892 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3893 Ops.push_back(DAG.getUNDEF(DstEltVT));
3897 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))->
3898 getAPIntValue()).zextOrTrunc(SrcBitSize);
3900 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3901 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
3902 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3903 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
3904 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
3905 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
3907 OpVal = OpVal.lshr(DstBitSize);
3910 // For big endian targets, swap the order of the pieces of each element.
3911 if (TLI.isBigEndian())
3912 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3915 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
3916 &Ops[0], Ops.size());
3919 SDValue DAGCombiner::visitFADD(SDNode *N) {
3920 SDValue N0 = N->getOperand(0);
3921 SDValue N1 = N->getOperand(1);
3922 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3923 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3924 MVT VT = N->getValueType(0);
3927 if (VT.isVector()) {
3928 SDValue FoldedVOp = SimplifyVBinOp(N);
3929 if (FoldedVOp.getNode()) return FoldedVOp;
3932 // fold (fadd c1, c2) -> (fadd c1, c2)
3933 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3934 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
3935 // canonicalize constant to RHS
3936 if (N0CFP && !N1CFP)
3937 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
3938 // fold (fadd A, 0) -> A
3939 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
3941 // fold (fadd A, (fneg B)) -> (fsub A, B)
3942 if (isNegatibleForFree(N1, LegalOperations) == 2)
3943 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
3944 GetNegatedExpression(N1, DAG, LegalOperations));
3945 // fold (fadd (fneg A), B) -> (fsub B, A)
3946 if (isNegatibleForFree(N0, LegalOperations) == 2)
3947 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
3948 GetNegatedExpression(N0, DAG, LegalOperations));
3950 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3951 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3952 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3953 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
3954 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
3955 N0.getOperand(1), N1));
3960 SDValue DAGCombiner::visitFSUB(SDNode *N) {
3961 SDValue N0 = N->getOperand(0);
3962 SDValue N1 = N->getOperand(1);
3963 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3964 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3965 MVT VT = N->getValueType(0);
3968 if (VT.isVector()) {
3969 SDValue FoldedVOp = SimplifyVBinOp(N);
3970 if (FoldedVOp.getNode()) return FoldedVOp;
3973 // fold (fsub c1, c2) -> c1-c2
3974 if (N0CFP && N1CFP && VT != MVT::ppcf128)
3975 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
3976 // fold (fsub A, 0) -> A
3977 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
3979 // fold (fsub 0, B) -> -B
3980 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
3981 if (isNegatibleForFree(N1, LegalOperations))
3982 return GetNegatedExpression(N1, DAG, LegalOperations);
3983 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
3984 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
3986 // fold (fsub A, (fneg B)) -> (fadd A, B)
3987 if (isNegatibleForFree(N1, LegalOperations))
3988 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
3989 GetNegatedExpression(N1, DAG, LegalOperations));
3994 SDValue DAGCombiner::visitFMUL(SDNode *N) {
3995 SDValue N0 = N->getOperand(0);
3996 SDValue N1 = N->getOperand(1);
3997 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3998 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3999 MVT VT = N->getValueType(0);
4002 if (VT.isVector()) {
4003 SDValue FoldedVOp = SimplifyVBinOp(N);
4004 if (FoldedVOp.getNode()) return FoldedVOp;
4007 // fold (fmul c1, c2) -> c1*c2
4008 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4009 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4010 // canonicalize constant to RHS
4011 if (N0CFP && !N1CFP)
4012 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4013 // fold (fmul A, 0) -> 0
4014 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4016 // fold (fmul X, 2.0) -> (fadd X, X)
4017 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4018 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4019 // fold (fmul X, (fneg 1.0)) -> (fneg X)
4020 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4021 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4022 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4024 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4025 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4026 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4027 // Both can be negated for free, check to see if at least one is cheaper
4029 if (LHSNeg == 2 || RHSNeg == 2)
4030 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4031 GetNegatedExpression(N0, DAG, LegalOperations),
4032 GetNegatedExpression(N1, DAG, LegalOperations));
4036 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4037 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4038 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4039 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4040 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4041 N0.getOperand(1), N1));
4046 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4047 SDValue N0 = N->getOperand(0);
4048 SDValue N1 = N->getOperand(1);
4049 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4050 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4051 MVT VT = N->getValueType(0);
4054 if (VT.isVector()) {
4055 SDValue FoldedVOp = SimplifyVBinOp(N);
4056 if (FoldedVOp.getNode()) return FoldedVOp;
4059 // fold (fdiv c1, c2) -> c1/c2
4060 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4061 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4064 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4065 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4066 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4067 // Both can be negated for free, check to see if at least one is cheaper
4069 if (LHSNeg == 2 || RHSNeg == 2)
4070 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4071 GetNegatedExpression(N0, DAG, LegalOperations),
4072 GetNegatedExpression(N1, DAG, LegalOperations));
4079 SDValue DAGCombiner::visitFREM(SDNode *N) {
4080 SDValue N0 = N->getOperand(0);
4081 SDValue N1 = N->getOperand(1);
4082 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4083 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4084 MVT VT = N->getValueType(0);
4086 // fold (frem c1, c2) -> fmod(c1,c2)
4087 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4088 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4093 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4094 SDValue N0 = N->getOperand(0);
4095 SDValue N1 = N->getOperand(1);
4096 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4097 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4098 MVT VT = N->getValueType(0);
4100 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4101 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4104 const APFloat& V = N1CFP->getValueAPF();
4105 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4106 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4107 if (!V.isNegative()) {
4108 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4109 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4111 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4112 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4113 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4117 // copysign(fabs(x), y) -> copysign(x, y)
4118 // copysign(fneg(x), y) -> copysign(x, y)
4119 // copysign(copysign(x,z), y) -> copysign(x, y)
4120 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4121 N0.getOpcode() == ISD::FCOPYSIGN)
4122 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4123 N0.getOperand(0), N1);
4125 // copysign(x, abs(y)) -> abs(x)
4126 if (N1.getOpcode() == ISD::FABS)
4127 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4129 // copysign(x, copysign(y,z)) -> copysign(x, z)
4130 if (N1.getOpcode() == ISD::FCOPYSIGN)
4131 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4132 N0, N1.getOperand(1));
4134 // copysign(x, fp_extend(y)) -> copysign(x, y)
4135 // copysign(x, fp_round(y)) -> copysign(x, y)
4136 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4137 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4138 N0, N1.getOperand(0));
4143 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4144 SDValue N0 = N->getOperand(0);
4145 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4146 MVT VT = N->getValueType(0);
4147 MVT OpVT = N0.getValueType();
4149 // fold (sint_to_fp c1) -> c1fp
4150 if (N0C && OpVT != MVT::ppcf128)
4151 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4153 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4154 // but UINT_TO_FP is legal on this target, try to convert.
4155 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4156 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4157 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4158 if (DAG.SignBitIsZero(N0))
4159 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4165 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4166 SDValue N0 = N->getOperand(0);
4167 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4168 MVT VT = N->getValueType(0);
4169 MVT OpVT = N0.getValueType();
4171 // fold (uint_to_fp c1) -> c1fp
4172 if (N0C && OpVT != MVT::ppcf128)
4173 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4175 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
4176 // but SINT_TO_FP is legal on this target, try to convert.
4177 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4178 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4179 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4180 if (DAG.SignBitIsZero(N0))
4181 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4187 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4188 SDValue N0 = N->getOperand(0);
4189 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4190 MVT VT = N->getValueType(0);
4192 // fold (fp_to_sint c1fp) -> c1
4194 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
4199 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4200 SDValue N0 = N->getOperand(0);
4201 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4202 MVT VT = N->getValueType(0);
4204 // fold (fp_to_uint c1fp) -> c1
4205 if (N0CFP && VT != MVT::ppcf128)
4206 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
4211 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4212 SDValue N0 = N->getOperand(0);
4213 SDValue N1 = N->getOperand(1);
4214 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4215 MVT VT = N->getValueType(0);
4217 // fold (fp_round c1fp) -> c1fp
4218 if (N0CFP && N0.getValueType() != MVT::ppcf128)
4219 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
4221 // fold (fp_round (fp_extend x)) -> x
4222 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4223 return N0.getOperand(0);
4225 // fold (fp_round (fp_round x)) -> (fp_round x)
4226 if (N0.getOpcode() == ISD::FP_ROUND) {
4227 // This is a value preserving truncation if both round's are.
4228 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4229 N0.getNode()->getConstantOperandVal(1) == 1;
4230 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
4231 DAG.getIntPtrConstant(IsTrunc));
4234 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4235 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4236 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
4237 N0.getOperand(0), N1);
4238 AddToWorkList(Tmp.getNode());
4239 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4240 Tmp, N0.getOperand(1));
4246 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4247 SDValue N0 = N->getOperand(0);
4248 MVT VT = N->getValueType(0);
4249 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4250 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4252 // fold (fp_round_inreg c1fp) -> c1fp
4253 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) {
4254 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4255 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
4261 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4262 SDValue N0 = N->getOperand(0);
4263 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4264 MVT VT = N->getValueType(0);
4266 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4267 if (N->hasOneUse() &&
4268 N->use_begin()->getOpcode() == ISD::FP_ROUND)
4271 // fold (fp_extend c1fp) -> c1fp
4272 if (N0CFP && VT != MVT::ppcf128)
4273 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
4275 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4277 if (N0.getOpcode() == ISD::FP_ROUND
4278 && N0.getNode()->getConstantOperandVal(1) == 1) {
4279 SDValue In = N0.getOperand(0);
4280 if (In.getValueType() == VT) return In;
4281 if (VT.bitsLT(In.getValueType()))
4282 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
4283 In, N0.getOperand(1));
4284 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
4287 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
4288 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
4289 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4290 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4291 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4292 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4294 LN0->getBasePtr(), LN0->getSrcValue(),
4295 LN0->getSrcValueOffset(),
4297 LN0->isVolatile(), LN0->getAlignment());
4298 CombineTo(N, ExtLoad);
4299 CombineTo(N0.getNode(),
4300 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
4301 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
4302 ExtLoad.getValue(1));
4303 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4309 SDValue DAGCombiner::visitFNEG(SDNode *N) {
4310 SDValue N0 = N->getOperand(0);
4312 if (isNegatibleForFree(N0, LegalOperations))
4313 return GetNegatedExpression(N0, DAG, LegalOperations);
4315 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
4316 // constant pool values.
4317 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4318 N0.getOperand(0).getValueType().isInteger() &&
4319 !N0.getOperand(0).getValueType().isVector()) {
4320 SDValue Int = N0.getOperand(0);
4321 MVT IntVT = Int.getValueType();
4322 if (IntVT.isInteger() && !IntVT.isVector()) {
4323 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
4324 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4325 AddToWorkList(Int.getNode());
4326 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4327 N->getValueType(0), Int);
4334 SDValue DAGCombiner::visitFABS(SDNode *N) {
4335 SDValue N0 = N->getOperand(0);
4336 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4337 MVT VT = N->getValueType(0);
4339 // fold (fabs c1) -> fabs(c1)
4340 if (N0CFP && VT != MVT::ppcf128)
4341 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4342 // fold (fabs (fabs x)) -> (fabs x)
4343 if (N0.getOpcode() == ISD::FABS)
4344 return N->getOperand(0);
4345 // fold (fabs (fneg x)) -> (fabs x)
4346 // fold (fabs (fcopysign x, y)) -> (fabs x)
4347 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
4348 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
4350 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
4351 // constant pool values.
4352 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4353 N0.getOperand(0).getValueType().isInteger() &&
4354 !N0.getOperand(0).getValueType().isVector()) {
4355 SDValue Int = N0.getOperand(0);
4356 MVT IntVT = Int.getValueType();
4357 if (IntVT.isInteger() && !IntVT.isVector()) {
4358 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
4359 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4360 AddToWorkList(Int.getNode());
4361 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4362 N->getValueType(0), Int);
4369 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
4370 SDValue Chain = N->getOperand(0);
4371 SDValue N1 = N->getOperand(1);
4372 SDValue N2 = N->getOperand(2);
4373 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4375 // never taken branch, fold to chain
4376 if (N1C && N1C->isNullValue())
4378 // unconditional branch
4379 if (N1C && N1C->getAPIntValue() == 1)
4380 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2);
4381 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
4383 if (N1.getOpcode() == ISD::SETCC &&
4384 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
4385 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4386 Chain, N1.getOperand(2),
4387 N1.getOperand(0), N1.getOperand(1), N2);
4390 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) {
4391 // Match this pattern so that we can generate simpler code:
4394 // %b = and i32 %a, 2
4395 // %c = srl i32 %b, 1
4396 // brcond i32 %c ...
4402 // %c = setcc eq %b, 0
4405 // This applies only when the AND constant value has one bit set and the
4406 // SRL constant is equal to the log2 of the AND constant. The back-end is
4407 // smart enough to convert the result into a TEST/JMP sequence.
4408 SDValue Op0 = N1.getOperand(0);
4409 SDValue Op1 = N1.getOperand(1);
4411 if (Op0.getOpcode() == ISD::AND &&
4413 Op1.getOpcode() == ISD::Constant) {
4414 SDValue AndOp0 = Op0.getOperand(0);
4415 SDValue AndOp1 = Op0.getOperand(1);
4417 if (AndOp1.getOpcode() == ISD::Constant) {
4418 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
4420 if (AndConst.isPowerOf2() &&
4421 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
4423 DAG.getSetCC(N->getDebugLoc(),
4424 TLI.getSetCCResultType(Op0.getValueType()),
4425 Op0, DAG.getConstant(0, Op0.getValueType()),
4428 // Replace the uses of SRL with SETCC
4429 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
4430 removeFromWorkList(N1.getNode());
4431 DAG.DeleteNode(N1.getNode());
4432 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4433 MVT::Other, Chain, SetCC, N2);
4442 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
4444 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
4445 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
4446 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
4448 // Use SimplifySetCC to simplify SETCC's.
4449 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
4450 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
4452 if (Simp.getNode()) AddToWorkList(Simp.getNode());
4454 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode());
4456 // fold br_cc true, dest -> br dest (unconditional branch)
4457 if (SCCC && !SCCC->isNullValue())
4458 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other,
4459 N->getOperand(0), N->getOperand(4));
4460 // fold br_cc false, dest -> unconditional fall through
4461 if (SCCC && SCCC->isNullValue())
4462 return N->getOperand(0);
4464 // fold to a simpler setcc
4465 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
4466 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4467 N->getOperand(0), Simp.getOperand(2),
4468 Simp.getOperand(0), Simp.getOperand(1),
4474 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
4475 /// pre-indexed load / store when the base pointer is an add or subtract
4476 /// and it has other uses besides the load / store. After the
4477 /// transformation, the new indexed load / store has effectively folded
4478 /// the add / subtract in and all of its other uses are redirected to the
4479 /// new load / store.
4480 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
4481 if (!LegalOperations)
4487 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4488 if (LD->isIndexed())
4490 VT = LD->getMemoryVT();
4491 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
4492 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
4494 Ptr = LD->getBasePtr();
4495 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4496 if (ST->isIndexed())
4498 VT = ST->getMemoryVT();
4499 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
4500 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
4502 Ptr = ST->getBasePtr();
4508 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
4509 // out. There is no reason to make this a preinc/predec.
4510 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
4511 Ptr.getNode()->hasOneUse())
4514 // Ask the target to do addressing mode selection.
4517 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4518 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
4520 // Don't create a indexed load / store with zero offset.
4521 if (isa<ConstantSDNode>(Offset) &&
4522 cast<ConstantSDNode>(Offset)->isNullValue())
4525 // Try turning it into a pre-indexed load / store except when:
4526 // 1) The new base ptr is a frame index.
4527 // 2) If N is a store and the new base ptr is either the same as or is a
4528 // predecessor of the value being stored.
4529 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
4530 // that would create a cycle.
4531 // 4) All uses are load / store ops that use it as old base ptr.
4533 // Check #1. Preinc'ing a frame index would require copying the stack pointer
4534 // (plus the implicit offset) to a register to preinc anyway.
4535 if (isa<FrameIndexSDNode>(BasePtr))
4540 SDValue Val = cast<StoreSDNode>(N)->getValue();
4541 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
4545 // Now check for #3 and #4.
4546 bool RealUse = false;
4547 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4548 E = Ptr.getNode()->use_end(); I != E; ++I) {
4552 if (Use->isPredecessorOf(N))
4555 if (!((Use->getOpcode() == ISD::LOAD &&
4556 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
4557 (Use->getOpcode() == ISD::STORE &&
4558 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
4567 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4568 BasePtr, Offset, AM);
4570 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4571 BasePtr, Offset, AM);
4574 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
4575 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4577 WorkListRemover DeadNodes(*this);
4579 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4581 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4584 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4588 // Finally, since the node is now dead, remove it from the graph.
4591 // Replace the uses of Ptr with uses of the updated base value.
4592 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
4594 removeFromWorkList(Ptr.getNode());
4595 DAG.DeleteNode(Ptr.getNode());
4600 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
4601 /// add / sub of the base pointer node into a post-indexed load / store.
4602 /// The transformation folded the add / subtract into the new indexed
4603 /// load / store effectively and all of its uses are redirected to the
4604 /// new load / store.
4605 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
4606 if (!LegalOperations)
4612 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4613 if (LD->isIndexed())
4615 VT = LD->getMemoryVT();
4616 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
4617 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
4619 Ptr = LD->getBasePtr();
4620 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4621 if (ST->isIndexed())
4623 VT = ST->getMemoryVT();
4624 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
4625 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
4627 Ptr = ST->getBasePtr();
4633 if (Ptr.getNode()->hasOneUse())
4636 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4637 E = Ptr.getNode()->use_end(); I != E; ++I) {
4640 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
4645 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4646 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
4648 std::swap(BasePtr, Offset);
4651 // Don't create a indexed load / store with zero offset.
4652 if (isa<ConstantSDNode>(Offset) &&
4653 cast<ConstantSDNode>(Offset)->isNullValue())
4656 // Try turning it into a post-indexed load / store except when
4657 // 1) All uses are load / store ops that use it as base ptr.
4658 // 2) Op must be independent of N, i.e. Op is neither a predecessor
4659 // nor a successor of N. Otherwise, if Op is folded that would
4663 bool TryNext = false;
4664 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
4665 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
4667 if (Use == Ptr.getNode())
4670 // If all the uses are load / store addresses, then don't do the
4672 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
4673 bool RealUse = false;
4674 for (SDNode::use_iterator III = Use->use_begin(),
4675 EEE = Use->use_end(); III != EEE; ++III) {
4676 SDNode *UseUse = *III;
4677 if (!((UseUse->getOpcode() == ISD::LOAD &&
4678 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
4679 (UseUse->getOpcode() == ISD::STORE &&
4680 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
4695 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
4696 SDValue Result = isLoad
4697 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4698 BasePtr, Offset, AM)
4699 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4700 BasePtr, Offset, AM);
4703 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
4704 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG));
4706 WorkListRemover DeadNodes(*this);
4708 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4710 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4713 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4717 // Finally, since the node is now dead, remove it from the graph.
4720 // Replace the uses of Use with uses of the updated base value.
4721 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
4722 Result.getValue(isLoad ? 1 : 0),
4724 removeFromWorkList(Op);
4734 /// InferAlignment - If we can infer some alignment information from this
4735 /// pointer, return it.
4736 static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) {
4737 // If this is a direct reference to a stack slot, use information about the
4738 // stack slot's alignment.
4739 int FrameIdx = 1 << 31;
4740 int64_t FrameOffset = 0;
4741 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) {
4742 FrameIdx = FI->getIndex();
4743 } else if (Ptr.getOpcode() == ISD::ADD &&
4744 isa<ConstantSDNode>(Ptr.getOperand(1)) &&
4745 isa<FrameIndexSDNode>(Ptr.getOperand(0))) {
4746 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
4747 FrameOffset = Ptr.getConstantOperandVal(1);
4750 if (FrameIdx != (1 << 31)) {
4751 // FIXME: Handle FI+CST.
4752 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo();
4753 if (MFI.isFixedObjectIndex(FrameIdx)) {
4754 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset;
4756 // The alignment of the frame index can be determined from its offset from
4757 // the incoming frame position. If the frame object is at offset 32 and
4758 // the stack is guaranteed to be 16-byte aligned, then we know that the
4759 // object is 16-byte aligned.
4760 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment();
4761 unsigned Align = MinAlign(ObjectOffset, StackAlign);
4763 // Finally, the frame object itself may have a known alignment. Factor
4764 // the alignment + offset into a new alignment. For example, if we know
4765 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a
4766 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte
4767 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc.
4768 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx),
4770 return std::max(Align, FIInfoAlign);
4777 SDValue DAGCombiner::visitLOAD(SDNode *N) {
4778 LoadSDNode *LD = cast<LoadSDNode>(N);
4779 SDValue Chain = LD->getChain();
4780 SDValue Ptr = LD->getBasePtr();
4782 // Try to infer better alignment information than the load already has.
4783 if (!Fast && LD->isUnindexed()) {
4784 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4785 if (Align > LD->getAlignment())
4786 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
4787 LD->getValueType(0),
4788 Chain, Ptr, LD->getSrcValue(),
4789 LD->getSrcValueOffset(), LD->getMemoryVT(),
4790 LD->isVolatile(), Align);
4794 // If load is not volatile and there are no uses of the loaded value (and
4795 // the updated indexed value in case of indexed loads), change uses of the
4796 // chain value into uses of the chain input (i.e. delete the dead load).
4797 if (!LD->isVolatile()) {
4798 if (N->getValueType(1) == MVT::Other) {
4800 if (N->hasNUsesOfValue(0, 0)) {
4801 // It's not safe to use the two value CombineTo variant here. e.g.
4802 // v1, chain2 = load chain1, loc
4803 // v2, chain3 = load chain2, loc
4805 // Now we replace use of chain2 with chain1. This makes the second load
4806 // isomorphic to the one we are deleting, and thus makes this load live.
4807 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4808 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG));
4810 WorkListRemover DeadNodes(*this);
4811 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
4813 if (N->use_empty()) {
4814 removeFromWorkList(N);
4818 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4822 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
4823 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
4824 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
4825 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
4826 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG));
4827 DOUT << " and 2 other values\n";
4828 WorkListRemover DeadNodes(*this);
4829 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
4830 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
4831 DAG.getUNDEF(N->getValueType(1)),
4833 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
4834 removeFromWorkList(N);
4836 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4841 // If this load is directly stored, replace the load value with the stored
4843 // TODO: Handle store large -> read small portion.
4844 // TODO: Handle TRUNCSTORE/LOADEXT
4845 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
4846 !LD->isVolatile()) {
4847 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
4848 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
4849 if (PrevST->getBasePtr() == Ptr &&
4850 PrevST->getValue().getValueType() == N->getValueType(0))
4851 return CombineTo(N, Chain.getOperand(1), Chain);
4856 // Walk up chain skipping non-aliasing memory nodes.
4857 SDValue BetterChain = FindBetterChain(N, Chain);
4859 // If there is a better chain.
4860 if (Chain != BetterChain) {
4863 // Replace the chain to void dependency.
4864 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
4865 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
4867 LD->getSrcValue(), LD->getSrcValueOffset(),
4868 LD->isVolatile(), LD->getAlignment());
4870 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
4871 LD->getValueType(0),
4872 BetterChain, Ptr, LD->getSrcValue(),
4873 LD->getSrcValueOffset(),
4876 LD->getAlignment());
4879 // Create token factor to keep old chain connected.
4880 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
4881 MVT::Other, Chain, ReplLoad.getValue(1));
4883 // Replace uses with load result and token factor. Don't add users
4885 return CombineTo(N, ReplLoad.getValue(0), Token, false);
4889 // Try transforming N to an indexed load.
4890 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
4891 return SDValue(N, 0);
4896 SDValue DAGCombiner::visitSTORE(SDNode *N) {
4897 StoreSDNode *ST = cast<StoreSDNode>(N);
4898 SDValue Chain = ST->getChain();
4899 SDValue Value = ST->getValue();
4900 SDValue Ptr = ST->getBasePtr();
4902 // Try to infer better alignment information than the store already has.
4903 if (!Fast && ST->isUnindexed()) {
4904 if (unsigned Align = InferAlignment(Ptr, DAG)) {
4905 if (Align > ST->getAlignment())
4906 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
4907 Ptr, ST->getSrcValue(),
4908 ST->getSrcValueOffset(), ST->getMemoryVT(),
4909 ST->isVolatile(), Align);
4913 // If this is a store of a bit convert, store the input value if the
4914 // resultant store does not need a higher alignment than the original.
4915 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
4916 ST->isUnindexed()) {
4917 unsigned OrigAlign = ST->getAlignment();
4918 MVT SVT = Value.getOperand(0).getValueType();
4919 unsigned Align = TLI.getTargetData()->
4920 getABITypeAlignment(SVT.getTypeForMVT());
4921 if (Align <= OrigAlign &&
4922 ((!LegalOperations && !ST->isVolatile()) ||
4923 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
4924 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
4925 Ptr, ST->getSrcValue(),
4926 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign);
4929 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
4930 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
4931 // NOTE: If the original store is volatile, this transform must not increase
4932 // the number of stores. For example, on x86-32 an f64 can be stored in one
4933 // processor operation but an i64 (which is not legal) requires two. So the
4934 // transform should not be done in this case.
4935 if (Value.getOpcode() != ISD::TargetConstantFP) {
4937 switch (CFP->getValueType(0).getSimpleVT()) {
4938 default: assert(0 && "Unknown FP type");
4939 case MVT::f80: // We don't do this for these yet.
4944 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
4945 !ST->isVolatile()) ||
4946 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
4947 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
4948 bitcastToAPInt().getZExtValue(), MVT::i32);
4949 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
4950 Ptr, ST->getSrcValue(),
4951 ST->getSrcValueOffset(), ST->isVolatile(),
4952 ST->getAlignment());
4956 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
4957 !ST->isVolatile()) ||
4958 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
4959 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
4960 getZExtValue(), MVT::i64);
4961 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
4962 Ptr, ST->getSrcValue(),
4963 ST->getSrcValueOffset(), ST->isVolatile(),
4964 ST->getAlignment());
4965 } else if (!ST->isVolatile() &&
4966 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
4967 // Many FP stores are not made apparent until after legalize, e.g. for
4968 // argument passing. Since this is so common, custom legalize the
4969 // 64-bit integer store into two 32-bit stores.
4970 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
4971 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
4972 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
4973 if (TLI.isBigEndian()) std::swap(Lo, Hi);
4975 int SVOffset = ST->getSrcValueOffset();
4976 unsigned Alignment = ST->getAlignment();
4977 bool isVolatile = ST->isVolatile();
4979 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
4980 Ptr, ST->getSrcValue(),
4981 ST->getSrcValueOffset(),
4982 isVolatile, ST->getAlignment());
4983 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
4984 DAG.getConstant(4, Ptr.getValueType()));
4986 Alignment = MinAlign(Alignment, 4U);
4987 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
4988 Ptr, ST->getSrcValue(),
4989 SVOffset, isVolatile, Alignment);
4990 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
5000 // Walk up chain skipping non-aliasing memory nodes.
5001 SDValue BetterChain = FindBetterChain(N, Chain);
5003 // If there is a better chain.
5004 if (Chain != BetterChain) {
5005 // Replace the chain to avoid dependency.
5007 if (ST->isTruncatingStore()) {
5008 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5009 ST->getSrcValue(),ST->getSrcValueOffset(),
5011 ST->isVolatile(), ST->getAlignment());
5013 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5014 ST->getSrcValue(), ST->getSrcValueOffset(),
5015 ST->isVolatile(), ST->getAlignment());
5018 // Create token to keep both nodes around.
5019 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5020 MVT::Other, Chain, ReplStore);
5022 // Don't add users to work list.
5023 return CombineTo(N, Token, false);
5027 // Try transforming N to an indexed store.
5028 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5029 return SDValue(N, 0);
5031 // FIXME: is there such a thing as a truncating indexed store?
5032 if (ST->isTruncatingStore() && ST->isUnindexed() &&
5033 Value.getValueType().isInteger()) {
5034 // See if we can simplify the input to this truncstore with knowledge that
5035 // only the low bits are being used. For example:
5036 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
5038 GetDemandedBits(Value,
5039 APInt::getLowBitsSet(Value.getValueSizeInBits(),
5040 ST->getMemoryVT().getSizeInBits()));
5041 AddToWorkList(Value.getNode());
5042 if (Shorter.getNode())
5043 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
5044 Ptr, ST->getSrcValue(),
5045 ST->getSrcValueOffset(), ST->getMemoryVT(),
5046 ST->isVolatile(), ST->getAlignment());
5048 // Otherwise, see if we can simplify the operation with
5049 // SimplifyDemandedBits, which only works if the value has a single use.
5050 if (SimplifyDemandedBits(Value,
5051 APInt::getLowBitsSet(
5052 Value.getValueSizeInBits(),
5053 ST->getMemoryVT().getSizeInBits())))
5054 return SDValue(N, 0);
5057 // If this is a load followed by a store to the same location, then the store
5059 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
5060 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
5061 ST->isUnindexed() && !ST->isVolatile() &&
5062 // There can't be any side effects between the load and store, such as
5064 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
5065 // The store is dead, remove it.
5070 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
5071 // truncating store. We can do this even if this is already a truncstore.
5072 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
5073 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
5074 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
5075 ST->getMemoryVT())) {
5076 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5077 Ptr, ST->getSrcValue(),
5078 ST->getSrcValueOffset(), ST->getMemoryVT(),
5079 ST->isVolatile(), ST->getAlignment());
5085 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
5086 SDValue InVec = N->getOperand(0);
5087 SDValue InVal = N->getOperand(1);
5088 SDValue EltNo = N->getOperand(2);
5090 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
5091 // vector with the inserted element.
5092 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
5093 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5094 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
5095 InVec.getNode()->op_end());
5096 if (Elt < Ops.size())
5098 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5099 InVec.getValueType(), &Ops[0], Ops.size());
5105 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
5106 // (vextract (scalar_to_vector val, 0) -> val
5107 SDValue InVec = N->getOperand(0);
5109 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5110 // If the operand is wider than the vector element type then it is implicitly
5111 // truncated. Make that explicit here.
5112 MVT EltVT = InVec.getValueType().getVectorElementType();
5113 SDValue InOp = InVec.getOperand(0);
5114 if (InOp.getValueType() != EltVT)
5115 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp);
5119 // Perform only after legalization to ensure build_vector / vector_shuffle
5120 // optimizations have already been done.
5121 if (!LegalOperations) return SDValue();
5123 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
5124 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
5125 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
5126 SDValue EltNo = N->getOperand(1);
5128 if (isa<ConstantSDNode>(EltNo)) {
5129 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5130 bool NewLoad = false;
5131 bool BCNumEltsChanged = false;
5132 MVT VT = InVec.getValueType();
5133 MVT EVT = VT.getVectorElementType();
5136 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
5137 MVT BCVT = InVec.getOperand(0).getValueType();
5138 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
5140 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
5141 BCNumEltsChanged = true;
5142 InVec = InVec.getOperand(0);
5143 EVT = BCVT.getVectorElementType();
5147 LoadSDNode *LN0 = NULL;
5148 if (ISD::isNormalLoad(InVec.getNode())) {
5149 LN0 = cast<LoadSDNode>(InVec);
5150 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5151 InVec.getOperand(0).getValueType() == EVT &&
5152 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
5153 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
5154 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) {
5155 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
5157 // (load $addr+1*size)
5159 // If the bit convert changed the number of elements, it is unsafe
5160 // to examine the mask.
5161 if (BCNumEltsChanged)
5163 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2).
5164 getOperand(Elt))->getZExtValue();
5165 unsigned NumElems = InVec.getOperand(2).getNumOperands();
5166 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
5167 if (InVec.getOpcode() == ISD::BIT_CONVERT)
5168 InVec = InVec.getOperand(0);
5169 if (ISD::isNormalLoad(InVec.getNode())) {
5170 LN0 = cast<LoadSDNode>(InVec);
5171 Elt = (Idx < NumElems) ? Idx : Idx - NumElems;
5175 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
5178 unsigned Align = LN0->getAlignment();
5180 // Check the resultant load doesn't need a higher alignment than the
5183 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT());
5185 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
5191 SDValue NewPtr = LN0->getBasePtr();
5193 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
5194 MVT PtrType = NewPtr.getValueType();
5195 if (TLI.isBigEndian())
5196 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
5197 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
5198 DAG.getConstant(PtrOff, PtrType));
5201 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
5202 LN0->getSrcValue(), LN0->getSrcValueOffset(),
5203 LN0->isVolatile(), Align);
5209 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
5210 unsigned NumInScalars = N->getNumOperands();
5211 MVT VT = N->getValueType(0);
5212 unsigned NumElts = VT.getVectorNumElements();
5213 MVT EltType = VT.getVectorElementType();
5215 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
5216 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
5217 // at most two distinct vectors, turn this into a shuffle node.
5218 SDValue VecIn1, VecIn2;
5219 for (unsigned i = 0; i != NumInScalars; ++i) {
5220 // Ignore undef inputs.
5221 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5223 // If this input is something other than a EXTRACT_VECTOR_ELT with a
5224 // constant index, bail out.
5225 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5226 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
5227 VecIn1 = VecIn2 = SDValue(0, 0);
5231 // If the input vector type disagrees with the result of the build_vector,
5232 // we can't make a shuffle.
5233 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
5234 if (ExtractedFromVec.getValueType() != VT) {
5235 VecIn1 = VecIn2 = SDValue(0, 0);
5239 // Otherwise, remember this. We allow up to two distinct input vectors.
5240 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
5243 if (VecIn1.getNode() == 0) {
5244 VecIn1 = ExtractedFromVec;
5245 } else if (VecIn2.getNode() == 0) {
5246 VecIn2 = ExtractedFromVec;
5249 VecIn1 = VecIn2 = SDValue(0, 0);
5254 // If everything is good, we can make a shuffle operation.
5255 MVT IndexVT = MVT::i32;
5256 if (VecIn1.getNode()) {
5257 SmallVector<SDValue, 8> BuildVecIndices;
5258 for (unsigned i = 0; i != NumInScalars; ++i) {
5259 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
5260 BuildVecIndices.push_back(DAG.getUNDEF(IndexVT));
5264 SDValue Extract = N->getOperand(i);
5266 // If extracting from the first vector, just use the index directly.
5267 SDValue ExtVal = Extract.getOperand(1);
5268 if (Extract.getOperand(0) == VecIn1) {
5269 if (ExtVal.getValueType() == IndexVT)
5270 BuildVecIndices.push_back(ExtVal);
5272 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5273 BuildVecIndices.push_back(DAG.getConstant(Idx, IndexVT));
5278 // Otherwise, use InIdx + VecSize
5279 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5280 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, IndexVT));
5283 // Add count and size info.
5284 MVT BuildVecVT = MVT::getVectorVT(IndexVT, NumElts);
5285 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes)
5288 // Return the new VECTOR_SHUFFLE node.
5291 if (VecIn2.getNode()) {
5294 // Use an undef build_vector as input for the second operand.
5295 std::vector<SDValue> UnOps(NumInScalars,
5296 DAG.getUNDEF(EltType));
5297 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
5298 &UnOps[0], UnOps.size());
5299 AddToWorkList(Ops[1].getNode());
5302 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), BuildVecVT,
5303 &BuildVecIndices[0], BuildVecIndices.size());
5304 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(), VT, Ops, 3);
5310 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
5311 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
5312 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
5313 // inputs come from at most two distinct vectors, turn this into a shuffle
5316 // If we only have one input vector, we don't need to do any concatenation.
5317 if (N->getNumOperands() == 1)
5318 return N->getOperand(0);
5323 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
5324 SDValue ShufMask = N->getOperand(2);
5325 unsigned NumElts = ShufMask.getNumOperands();
5327 SDValue N0 = N->getOperand(0);
5328 SDValue N1 = N->getOperand(1);
5330 assert(N0.getValueType().getVectorNumElements() == NumElts &&
5331 "Vector shuffle must be normalized in DAG");
5333 // If the shuffle mask is an identity operation on the LHS, return the LHS.
5334 bool isIdentity = true;
5335 for (unsigned i = 0; i != NumElts; ++i) {
5336 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
5337 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) {
5342 if (isIdentity) return N->getOperand(0);
5344 // If the shuffle mask is an identity operation on the RHS, return the RHS.
5346 for (unsigned i = 0; i != NumElts; ++i) {
5347 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
5348 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() !=
5354 if (isIdentity) return N->getOperand(1);
5356 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
5358 bool isUnary = true;
5359 bool isSplat = true;
5361 unsigned BaseIdx = 0;
5362 for (unsigned i = 0; i != NumElts; ++i)
5363 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
5364 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue();
5365 int V = (Idx < NumElts) ? 0 : 1;
5379 // Normalize unary shuffle so the RHS is undef.
5380 if (isUnary && VecNum == 1)
5383 // If it is a splat, check if the argument vector is a build_vector with
5384 // all scalar elements the same.
5386 SDNode *V = N0.getNode();
5388 // If this is a bit convert that changes the element type of the vector but
5389 // not the number of vector elements, look through it. Be careful not to
5390 // look though conversions that change things like v4f32 to v2f64.
5391 if (V->getOpcode() == ISD::BIT_CONVERT) {
5392 SDValue ConvInput = V->getOperand(0);
5393 if (ConvInput.getValueType().isVector() &&
5394 ConvInput.getValueType().getVectorNumElements() == NumElts)
5395 V = ConvInput.getNode();
5398 if (V->getOpcode() == ISD::BUILD_VECTOR) {
5399 unsigned NumElems = V->getNumOperands();
5400 if (NumElems > BaseIdx) {
5402 bool AllSame = true;
5403 for (unsigned i = 0; i != NumElems; ++i) {
5404 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
5405 Base = V->getOperand(i);
5409 // Splat of <u, u, u, u>, return <u, u, u, u>
5410 if (!Base.getNode())
5412 for (unsigned i = 0; i != NumElems; ++i) {
5413 if (V->getOperand(i) != Base) {
5418 // Splat of <x, x, x, x>, return <x, x, x, x>
5425 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
5427 if (isUnary || N0 == N1) {
5428 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
5430 SmallVector<SDValue, 8> MappedOps;
5432 for (unsigned i = 0; i != NumElts; ++i) {
5433 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
5434 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() <
5436 MappedOps.push_back(ShufMask.getOperand(i));
5439 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() -
5441 MappedOps.push_back(DAG.getConstant(NewIdx,
5442 ShufMask.getOperand(i).getValueType()));
5446 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5447 ShufMask.getValueType(),
5448 &MappedOps[0], MappedOps.size());
5449 AddToWorkList(ShufMask.getNode());
5450 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
5451 N->getValueType(0), N0,
5452 DAG.getUNDEF(N->getValueType(0)),
5459 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
5460 /// an AND to a vector_shuffle with the destination vector and a zero vector.
5461 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
5462 /// vector_shuffle V, Zero, <0, 4, 2, 4>
5463 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
5464 SDValue LHS = N->getOperand(0);
5465 SDValue RHS = N->getOperand(1);
5466 if (N->getOpcode() == ISD::AND) {
5467 if (RHS.getOpcode() == ISD::BIT_CONVERT)
5468 RHS = RHS.getOperand(0);
5469 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
5470 std::vector<SDValue> IdxOps;
5471 unsigned NumOps = RHS.getNumOperands();
5472 unsigned NumElts = NumOps;
5473 for (unsigned i = 0; i != NumElts; ++i) {
5474 SDValue Elt = RHS.getOperand(i);
5475 if (!isa<ConstantSDNode>(Elt))
5477 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
5478 IdxOps.push_back(DAG.getIntPtrConstant(i));
5479 else if (cast<ConstantSDNode>(Elt)->isNullValue())
5480 IdxOps.push_back(DAG.getIntPtrConstant(NumElts));
5485 // Let's see if the target supports this vector_shuffle.
5486 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG))
5489 // Return the new VECTOR_SHUFFLE node.
5490 MVT EVT = RHS.getValueType().getVectorElementType();
5491 MVT VT = MVT::getVectorVT(EVT, NumElts);
5492 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
5493 std::vector<SDValue> Ops;
5494 LHS = DAG.getNode(ISD::BIT_CONVERT, LHS.getDebugLoc(), VT, LHS);
5496 AddToWorkList(LHS.getNode());
5497 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT));
5498 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5499 VT, &ZeroOps[0], ZeroOps.size()));
5500 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5501 MaskVT, &IdxOps[0], IdxOps.size()));
5502 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, N->getDebugLoc(),
5503 VT, &Ops[0], Ops.size());
5505 if (VT != N->getValueType(0))
5506 Result = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
5507 N->getValueType(0), Result);
5516 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
5517 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
5518 // After legalize, the target may be depending on adds and other
5519 // binary ops to provide legal ways to construct constants or other
5520 // things. Simplifying them may result in a loss of legality.
5521 if (LegalOperations) return SDValue();
5523 MVT VT = N->getValueType(0);
5524 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
5526 MVT EltType = VT.getVectorElementType();
5527 SDValue LHS = N->getOperand(0);
5528 SDValue RHS = N->getOperand(1);
5529 SDValue Shuffle = XformToShuffleWithZero(N);
5530 if (Shuffle.getNode()) return Shuffle;
5532 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
5534 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
5535 RHS.getOpcode() == ISD::BUILD_VECTOR) {
5536 SmallVector<SDValue, 8> Ops;
5537 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
5538 SDValue LHSOp = LHS.getOperand(i);
5539 SDValue RHSOp = RHS.getOperand(i);
5540 // If these two elements can't be folded, bail out.
5541 if ((LHSOp.getOpcode() != ISD::UNDEF &&
5542 LHSOp.getOpcode() != ISD::Constant &&
5543 LHSOp.getOpcode() != ISD::ConstantFP) ||
5544 (RHSOp.getOpcode() != ISD::UNDEF &&
5545 RHSOp.getOpcode() != ISD::Constant &&
5546 RHSOp.getOpcode() != ISD::ConstantFP))
5549 // Can't fold divide by zero.
5550 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
5551 N->getOpcode() == ISD::FDIV) {
5552 if ((RHSOp.getOpcode() == ISD::Constant &&
5553 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
5554 (RHSOp.getOpcode() == ISD::ConstantFP &&
5555 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
5559 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(),
5560 EltType, LHSOp, RHSOp));
5561 AddToWorkList(Ops.back().getNode());
5562 assert((Ops.back().getOpcode() == ISD::UNDEF ||
5563 Ops.back().getOpcode() == ISD::Constant ||
5564 Ops.back().getOpcode() == ISD::ConstantFP) &&
5565 "Scalar binop didn't fold!");
5568 if (Ops.size() == LHS.getNumOperands()) {
5569 MVT VT = LHS.getValueType();
5570 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
5571 &Ops[0], Ops.size());
5578 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
5579 SDValue N1, SDValue N2){
5580 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
5582 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
5583 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5585 // If we got a simplified select_cc node back from SimplifySelectCC, then
5586 // break it down into a new SETCC node, and a new SELECT node, and then return
5587 // the SELECT node, since we were called with a SELECT node.
5588 if (SCC.getNode()) {
5589 // Check to see if we got a select_cc back (to turn into setcc/select).
5590 // Otherwise, just return whatever node we got back, like fabs.
5591 if (SCC.getOpcode() == ISD::SELECT_CC) {
5592 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
5594 SCC.getOperand(0), SCC.getOperand(1),
5596 AddToWorkList(SETCC.getNode());
5597 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
5598 SCC.getOperand(2), SCC.getOperand(3), SETCC);
5606 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
5607 /// are the two values being selected between, see if we can simplify the
5608 /// select. Callers of this should assume that TheSelect is deleted if this
5609 /// returns true. As such, they should return the appropriate thing (e.g. the
5610 /// node) back to the top-level of the DAG combiner loop to avoid it being
5612 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
5615 // If this is a select from two identical things, try to pull the operation
5616 // through the select.
5617 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
5618 // If this is a load and the token chain is identical, replace the select
5619 // of two loads with a load through a select of the address to load from.
5620 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
5621 // constants have been dropped into the constant pool.
5622 if (LHS.getOpcode() == ISD::LOAD &&
5623 // Do not let this transformation reduce the number of volatile loads.
5624 !cast<LoadSDNode>(LHS)->isVolatile() &&
5625 !cast<LoadSDNode>(RHS)->isVolatile() &&
5626 // Token chains must be identical.
5627 LHS.getOperand(0) == RHS.getOperand(0)) {
5628 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
5629 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
5631 // If this is an EXTLOAD, the VT's must match.
5632 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
5633 // FIXME: this conflates two src values, discarding one. This is not
5634 // the right thing to do, but nothing uses srcvalues now. When they do,
5635 // turn SrcValue into a list of locations.
5637 if (TheSelect->getOpcode() == ISD::SELECT) {
5638 // Check that the condition doesn't reach either load. If so, folding
5639 // this will induce a cycle into the DAG.
5640 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5641 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) {
5642 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
5643 LLD->getBasePtr().getValueType(),
5644 TheSelect->getOperand(0), LLD->getBasePtr(),
5648 // Check that the condition doesn't reach either load. If so, folding
5649 // this will induce a cycle into the DAG.
5650 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5651 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
5652 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) &&
5653 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) {
5654 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
5655 LLD->getBasePtr().getValueType(),
5656 TheSelect->getOperand(0),
5657 TheSelect->getOperand(1),
5658 LLD->getBasePtr(), RLD->getBasePtr(),
5659 TheSelect->getOperand(4));
5663 if (Addr.getNode()) {
5665 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
5666 Load = DAG.getLoad(TheSelect->getValueType(0),
5667 TheSelect->getDebugLoc(),
5669 Addr,LLD->getSrcValue(),
5670 LLD->getSrcValueOffset(),
5672 LLD->getAlignment());
5674 Load = DAG.getExtLoad(LLD->getExtensionType(),
5675 TheSelect->getDebugLoc(),
5676 TheSelect->getValueType(0),
5677 LLD->getChain(), Addr, LLD->getSrcValue(),
5678 LLD->getSrcValueOffset(),
5681 LLD->getAlignment());
5684 // Users of the select now use the result of the load.
5685 CombineTo(TheSelect, Load);
5687 // Users of the old loads now use the new load's chain. We know the
5688 // old-load value is dead now.
5689 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
5690 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
5700 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
5701 /// where 'cond' is the comparison specified by CC.
5702 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
5703 SDValue N2, SDValue N3,
5704 ISD::CondCode CC, bool NotExtCompare) {
5705 // (x ? y : y) -> y.
5706 if (N2 == N3) return N2;
5708 MVT VT = N2.getValueType();
5709 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
5710 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
5711 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
5713 // Determine if the condition we're dealing with is constant
5714 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
5715 N0, N1, CC, DL, false);
5716 if (SCC.getNode()) AddToWorkList(SCC.getNode());
5717 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
5719 // fold select_cc true, x, y -> x
5720 if (SCCC && !SCCC->isNullValue())
5722 // fold select_cc false, x, y -> y
5723 if (SCCC && SCCC->isNullValue())
5726 // Check to see if we can simplify the select into an fabs node
5727 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
5728 // Allow either -0.0 or 0.0
5729 if (CFP->getValueAPF().isZero()) {
5730 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
5731 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
5732 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
5733 N2 == N3.getOperand(0))
5734 return DAG.getNode(ISD::FABS, DL, VT, N0);
5736 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
5737 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
5738 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
5739 N2.getOperand(0) == N3)
5740 return DAG.getNode(ISD::FABS, DL, VT, N3);
5744 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
5745 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
5746 // in it. This is a win when the constant is not otherwise available because
5747 // it replaces two constant pool loads with one. We only do this if the FP
5748 // type is known to be legal, because if it isn't, then we are before legalize
5749 // types an we want the other legalization to happen first (e.g. to avoid
5750 // messing with soft float) and if the ConstantFP is not legal, because if
5751 // it is legal, we may not need to store the FP constant in a constant pool.
5752 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
5753 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
5754 if (TLI.isTypeLegal(N2.getValueType()) &&
5755 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
5756 TargetLowering::Legal) &&
5757 // If both constants have multiple uses, then we won't need to do an
5758 // extra load, they are likely around in registers for other users.
5759 (TV->hasOneUse() || FV->hasOneUse())) {
5760 Constant *Elts[] = {
5761 const_cast<ConstantFP*>(FV->getConstantFPValue()),
5762 const_cast<ConstantFP*>(TV->getConstantFPValue())
5764 const Type *FPTy = Elts[0]->getType();
5765 const TargetData &TD = *TLI.getTargetData();
5767 // Create a ConstantArray of the two constants.
5768 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
5769 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
5770 TD.getPrefTypeAlignment(FPTy));
5771 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5773 // Get the offsets to the 0 and 1 element of the array so that we can
5774 // select between them.
5775 SDValue Zero = DAG.getIntPtrConstant(0);
5776 unsigned EltSize = (unsigned)TD.getTypePaddedSize(Elts[0]->getType());
5777 SDValue One = DAG.getIntPtrConstant(EltSize);
5779 SDValue Cond = DAG.getSetCC(DL,
5780 TLI.getSetCCResultType(N0.getValueType()),
5782 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
5784 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
5786 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
5787 PseudoSourceValue::getConstantPool(), 0, false,
5793 // Check to see if we can perform the "gzip trick", transforming
5794 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
5795 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
5796 N0.getValueType().isInteger() &&
5797 N2.getValueType().isInteger() &&
5798 (N1C->isNullValue() || // (a < 0) ? b : 0
5799 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
5800 MVT XType = N0.getValueType();
5801 MVT AType = N2.getValueType();
5802 if (XType.bitsGE(AType)) {
5803 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
5804 // single-bit constant.
5805 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
5806 unsigned ShCtV = N2C->getAPIntValue().logBase2();
5807 ShCtV = XType.getSizeInBits()-ShCtV-1;
5808 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
5809 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
5811 AddToWorkList(Shift.getNode());
5813 if (XType.bitsGT(AType)) {
5814 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
5815 AddToWorkList(Shift.getNode());
5818 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
5821 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
5823 DAG.getConstant(XType.getSizeInBits()-1,
5824 getShiftAmountTy()));
5825 AddToWorkList(Shift.getNode());
5827 if (XType.bitsGT(AType)) {
5828 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
5829 AddToWorkList(Shift.getNode());
5832 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
5836 // fold select C, 16, 0 -> shl C, 4
5837 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
5838 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
5840 // If the caller doesn't want us to simplify this into a zext of a compare,
5842 if (NotExtCompare && N2C->getAPIntValue() == 1)
5845 // Get a SetCC of the condition
5846 // FIXME: Should probably make sure that setcc is legal if we ever have a
5847 // target where it isn't.
5849 // cast from setcc result type to select result type
5851 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
5853 if (N2.getValueType().bitsLT(SCC.getValueType()))
5854 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
5856 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
5857 N2.getValueType(), SCC);
5859 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
5860 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
5861 N2.getValueType(), SCC);
5864 AddToWorkList(SCC.getNode());
5865 AddToWorkList(Temp.getNode());
5867 if (N2C->getAPIntValue() == 1)
5870 // shl setcc result by log2 n2c
5871 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
5872 DAG.getConstant(N2C->getAPIntValue().logBase2(),
5873 getShiftAmountTy()));
5876 // Check to see if this is the equivalent of setcc
5877 // FIXME: Turn all of these into setcc if setcc if setcc is legal
5878 // otherwise, go ahead with the folds.
5879 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
5880 MVT XType = N0.getValueType();
5881 if (!LegalOperations ||
5882 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
5883 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
5884 if (Res.getValueType() != VT)
5885 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
5889 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
5890 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
5891 (!LegalOperations ||
5892 TLI.isOperationLegal(ISD::CTLZ, XType))) {
5893 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
5894 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
5895 DAG.getConstant(Log2_32(XType.getSizeInBits()),
5896 getShiftAmountTy()));
5898 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
5899 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
5900 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
5901 XType, DAG.getConstant(0, XType), N0);
5902 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
5903 return DAG.getNode(ISD::SRL, DL, XType,
5904 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
5905 DAG.getConstant(XType.getSizeInBits()-1,
5906 getShiftAmountTy()));
5908 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
5909 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
5910 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
5911 DAG.getConstant(XType.getSizeInBits()-1,
5912 getShiftAmountTy()));
5913 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
5917 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
5918 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5919 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
5920 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
5921 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
5922 MVT XType = N0.getValueType();
5923 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
5924 DAG.getConstant(XType.getSizeInBits()-1,
5925 getShiftAmountTy()));
5926 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
5928 AddToWorkList(Shift.getNode());
5929 AddToWorkList(Add.getNode());
5930 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
5932 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
5933 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5934 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
5935 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
5936 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
5937 MVT XType = N0.getValueType();
5938 if (SubC->isNullValue() && XType.isInteger()) {
5939 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
5941 DAG.getConstant(XType.getSizeInBits()-1,
5942 getShiftAmountTy()));
5943 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
5945 AddToWorkList(Shift.getNode());
5946 AddToWorkList(Add.getNode());
5947 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
5955 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
5956 SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0,
5957 SDValue N1, ISD::CondCode Cond,
5958 DebugLoc DL, bool foldBooleans) {
5959 TargetLowering::DAGCombinerInfo
5960 DagCombineInfo(DAG, Level == Unrestricted, false, this);
5961 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
5964 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
5965 /// return a DAG expression to select that will generate the same value by
5966 /// multiplying by a magic number. See:
5967 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5968 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
5969 std::vector<SDNode*> Built;
5970 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
5972 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5978 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
5979 /// return a DAG expression to select that will generate the same value by
5980 /// multiplying by a magic number. See:
5981 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
5982 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
5983 std::vector<SDNode*> Built;
5984 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
5986 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
5992 /// FindBaseOffset - Return true if base is known not to alias with anything
5993 /// but itself. Provides base object and offset as results.
5994 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) {
5995 // Assume it is a primitive operation.
5996 Base = Ptr; Offset = 0;
5998 // If it's an adding a simple constant then integrate the offset.
5999 if (Base.getOpcode() == ISD::ADD) {
6000 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
6001 Base = Base.getOperand(0);
6002 Offset += C->getZExtValue();
6006 // If it's any of the following then it can't alias with anything but itself.
6007 return isa<FrameIndexSDNode>(Base) ||
6008 isa<ConstantPoolSDNode>(Base) ||
6009 isa<GlobalAddressSDNode>(Base);
6012 /// isAlias - Return true if there is any possibility that the two addresses
6014 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
6015 const Value *SrcValue1, int SrcValueOffset1,
6016 SDValue Ptr2, int64_t Size2,
6017 const Value *SrcValue2, int SrcValueOffset2) const {
6018 // If they are the same then they must be aliases.
6019 if (Ptr1 == Ptr2) return true;
6021 // Gather base node and offset information.
6022 SDValue Base1, Base2;
6023 int64_t Offset1, Offset2;
6024 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
6025 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
6027 // If they have a same base address then...
6029 // Check to see if the addresses overlap.
6030 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
6032 // If we know both bases then they can't alias.
6033 if (KnownBase1 && KnownBase2) return false;
6035 if (CombinerGlobalAA) {
6036 // Use alias analysis information.
6037 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
6038 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
6039 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
6040 AliasAnalysis::AliasResult AAResult =
6041 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
6042 if (AAResult == AliasAnalysis::NoAlias)
6046 // Otherwise we have to assume they alias.
6050 /// FindAliasInfo - Extracts the relevant alias information from the memory
6051 /// node. Returns true if the operand was a load.
6052 bool DAGCombiner::FindAliasInfo(SDNode *N,
6053 SDValue &Ptr, int64_t &Size,
6054 const Value *&SrcValue, int &SrcValueOffset) const {
6055 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6056 Ptr = LD->getBasePtr();
6057 Size = LD->getMemoryVT().getSizeInBits() >> 3;
6058 SrcValue = LD->getSrcValue();
6059 SrcValueOffset = LD->getSrcValueOffset();
6061 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6062 Ptr = ST->getBasePtr();
6063 Size = ST->getMemoryVT().getSizeInBits() >> 3;
6064 SrcValue = ST->getSrcValue();
6065 SrcValueOffset = ST->getSrcValueOffset();
6067 assert(0 && "FindAliasInfo expected a memory operand");
6073 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
6074 /// looking for aliasing nodes and adding them to the Aliases vector.
6075 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
6076 SmallVector<SDValue, 8> &Aliases) {
6077 SmallVector<SDValue, 8> Chains; // List of chains to visit.
6078 std::set<SDNode *> Visited; // Visited node set.
6080 // Get alias information for node.
6083 const Value *SrcValue;
6085 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
6088 Chains.push_back(OriginalChain);
6090 // Look at each chain and determine if it is an alias. If so, add it to the
6091 // aliases list. If not, then continue up the chain looking for the next
6093 while (!Chains.empty()) {
6094 SDValue Chain = Chains.back();
6097 // Don't bother if we've been before.
6098 if (Visited.find(Chain.getNode()) != Visited.end()) continue;
6099 Visited.insert(Chain.getNode());
6101 switch (Chain.getOpcode()) {
6102 case ISD::EntryToken:
6103 // Entry token is ideal chain operand, but handled in FindBetterChain.
6108 // Get alias information for Chain.
6111 const Value *OpSrcValue;
6112 int OpSrcValueOffset;
6113 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
6114 OpSrcValue, OpSrcValueOffset);
6116 // If chain is alias then stop here.
6117 if (!(IsLoad && IsOpLoad) &&
6118 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
6119 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
6120 Aliases.push_back(Chain);
6122 // Look further up the chain.
6123 Chains.push_back(Chain.getOperand(0));
6124 // Clean up old chain.
6125 AddToWorkList(Chain.getNode());
6130 case ISD::TokenFactor:
6131 // We have to check each of the operands of the token factor, so we queue
6132 // then up. Adding the operands to the queue (stack) in reverse order
6133 // maintains the original order and increases the likelihood that getNode
6134 // will find a matching token factor (CSE.)
6135 for (unsigned n = Chain.getNumOperands(); n;)
6136 Chains.push_back(Chain.getOperand(--n));
6137 // Eliminate the token factor if we can.
6138 AddToWorkList(Chain.getNode());
6142 // For all other instructions we will just have to take what we can get.
6143 Aliases.push_back(Chain);
6149 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
6150 /// for a better chain (aliasing node.)
6151 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
6152 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
6154 // Accumulate all the aliases to this node.
6155 GatherAllAliases(N, OldChain, Aliases);
6157 if (Aliases.size() == 0) {
6158 // If no operands then chain to entry token.
6159 return DAG.getEntryNode();
6160 } else if (Aliases.size() == 1) {
6161 // If a single operand then chain to it. We don't need to revisit it.
6165 // Construct a custom tailored token factor.
6166 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6167 &Aliases[0], Aliases.size());
6169 // Make sure the old chain gets cleaned up.
6170 if (NewChain != OldChain) AddToWorkList(OldChain.getNode());
6175 // SelectionDAG::Combine - This is the entry point for the file.
6177 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) {
6178 /// run - This is the main entry point to this class.
6180 DAGCombiner(*this, AA, Fast).Run(Level);