1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: make truncate see through SIGN_EXTEND and AND
26 // FIXME: divide by zero is currently left unfolded. do we want to turn this
28 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
30 //===----------------------------------------------------------------------===//
32 #define DEBUG_TYPE "dagcombine"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
44 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
51 // Worklist of all of the nodes that need to be simplified.
52 std::vector<SDNode*> WorkList;
54 /// AddUsersToWorkList - When an instruction is simplified, add all users of
55 /// the instruction to the work lists because they might get more simplified
58 void AddUsersToWorkList(SDNode *N) {
59 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
61 WorkList.push_back(*UI);
64 /// removeFromWorkList - remove all instances of N from the worklist.
66 void removeFromWorkList(SDNode *N) {
67 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
72 void AddToWorkList(SDNode *N) {
73 WorkList.push_back(N);
76 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
78 DEBUG(std::cerr << "\nReplacing "; N->dump();
79 std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
80 std::cerr << " and " << To.size()-1 << " other values\n");
81 std::vector<SDNode*> NowDead;
82 DAG.ReplaceAllUsesWith(N, To, &NowDead);
84 // Push the new nodes and any users onto the worklist
85 for (unsigned i = 0, e = To.size(); i != e; ++i) {
86 WorkList.push_back(To[i].Val);
87 AddUsersToWorkList(To[i].Val);
90 // Nodes can end up on the worklist more than once. Make sure we do
91 // not process a node that has been replaced.
92 removeFromWorkList(N);
93 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
94 removeFromWorkList(NowDead[i]);
96 // Finally, since the node is now dead, remove it from the graph.
98 return SDOperand(N, 0);
101 SDOperand CombineTo(SDNode *N, SDOperand Res) {
102 std::vector<SDOperand> To;
104 return CombineTo(N, To);
107 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
108 std::vector<SDOperand> To;
111 return CombineTo(N, To);
115 /// SimplifyDemandedBits - Check the specified integer node value to see if
116 /// it can be simplified or if things it uses can be simplified by bit
117 /// propagation. If so, return true.
118 bool SimplifyDemandedBits(SDOperand Op) {
119 TargetLowering::TargetLoweringOpt TLO(DAG);
120 uint64_t KnownZero, KnownOne;
121 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
122 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
126 WorkList.push_back(Op.Val);
128 // Replace the old value with the new one.
130 DEBUG(std::cerr << "\nReplacing "; TLO.Old.Val->dump();
131 std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG));
133 std::vector<SDNode*> NowDead;
134 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
136 // Push the new node and any (possibly new) users onto the worklist.
137 WorkList.push_back(TLO.New.Val);
138 AddUsersToWorkList(TLO.New.Val);
140 // Nodes can end up on the worklist more than once. Make sure we do
141 // not process a node that has been replaced.
142 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
143 removeFromWorkList(NowDead[i]);
145 // Finally, if the node is now dead, remove it from the graph. The node
146 // may not be dead if the replacement process recursively simplified to
147 // something else needing this node.
148 if (TLO.Old.Val->use_empty()) {
149 removeFromWorkList(TLO.Old.Val);
150 DAG.DeleteNode(TLO.Old.Val);
155 /// visit - call the node-specific routine that knows how to fold each
156 /// particular type of node.
157 SDOperand visit(SDNode *N);
159 // Visitation implementation - Implement dag node combining for different
160 // node types. The semantics are as follows:
162 // SDOperand.Val == 0 - No change was made
163 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
164 // otherwise - N should be replaced by the returned Operand.
166 SDOperand visitTokenFactor(SDNode *N);
167 SDOperand visitADD(SDNode *N);
168 SDOperand visitSUB(SDNode *N);
169 SDOperand visitMUL(SDNode *N);
170 SDOperand visitSDIV(SDNode *N);
171 SDOperand visitUDIV(SDNode *N);
172 SDOperand visitSREM(SDNode *N);
173 SDOperand visitUREM(SDNode *N);
174 SDOperand visitMULHU(SDNode *N);
175 SDOperand visitMULHS(SDNode *N);
176 SDOperand visitAND(SDNode *N);
177 SDOperand visitOR(SDNode *N);
178 SDOperand visitXOR(SDNode *N);
179 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
180 SDOperand visitSHL(SDNode *N);
181 SDOperand visitSRA(SDNode *N);
182 SDOperand visitSRL(SDNode *N);
183 SDOperand visitCTLZ(SDNode *N);
184 SDOperand visitCTTZ(SDNode *N);
185 SDOperand visitCTPOP(SDNode *N);
186 SDOperand visitSELECT(SDNode *N);
187 SDOperand visitSELECT_CC(SDNode *N);
188 SDOperand visitSETCC(SDNode *N);
189 SDOperand visitSIGN_EXTEND(SDNode *N);
190 SDOperand visitZERO_EXTEND(SDNode *N);
191 SDOperand visitANY_EXTEND(SDNode *N);
192 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
193 SDOperand visitTRUNCATE(SDNode *N);
194 SDOperand visitBIT_CONVERT(SDNode *N);
195 SDOperand visitVBIT_CONVERT(SDNode *N);
196 SDOperand visitFADD(SDNode *N);
197 SDOperand visitFSUB(SDNode *N);
198 SDOperand visitFMUL(SDNode *N);
199 SDOperand visitFDIV(SDNode *N);
200 SDOperand visitFREM(SDNode *N);
201 SDOperand visitFCOPYSIGN(SDNode *N);
202 SDOperand visitSINT_TO_FP(SDNode *N);
203 SDOperand visitUINT_TO_FP(SDNode *N);
204 SDOperand visitFP_TO_SINT(SDNode *N);
205 SDOperand visitFP_TO_UINT(SDNode *N);
206 SDOperand visitFP_ROUND(SDNode *N);
207 SDOperand visitFP_ROUND_INREG(SDNode *N);
208 SDOperand visitFP_EXTEND(SDNode *N);
209 SDOperand visitFNEG(SDNode *N);
210 SDOperand visitFABS(SDNode *N);
211 SDOperand visitBRCOND(SDNode *N);
212 SDOperand visitBR_CC(SDNode *N);
213 SDOperand visitLOAD(SDNode *N);
214 SDOperand visitXEXTLOAD(SDNode *N);
215 SDOperand visitSTORE(SDNode *N);
216 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
217 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
218 SDOperand visitVBUILD_VECTOR(SDNode *N);
219 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
220 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
222 SDOperand XformToShuffleWithZero(SDNode *N);
223 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
225 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
226 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
227 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
228 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
229 SDOperand N3, ISD::CondCode CC);
230 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
231 ISD::CondCode Cond, bool foldBooleans = true);
232 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
233 SDOperand BuildSDIV(SDNode *N);
234 SDOperand BuildUDIV(SDNode *N);
236 DAGCombiner(SelectionDAG &D)
237 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
239 /// Run - runs the dag combiner on all nodes in the work list
240 void Run(bool RunningAfterLegalize);
244 //===----------------------------------------------------------------------===//
245 // TargetLowering::DAGCombinerInfo implementation
246 //===----------------------------------------------------------------------===//
248 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
249 ((DAGCombiner*)DC)->AddToWorkList(N);
252 SDOperand TargetLowering::DAGCombinerInfo::
253 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
254 return ((DAGCombiner*)DC)->CombineTo(N, To);
257 SDOperand TargetLowering::DAGCombinerInfo::
258 CombineTo(SDNode *N, SDOperand Res) {
259 return ((DAGCombiner*)DC)->CombineTo(N, Res);
263 SDOperand TargetLowering::DAGCombinerInfo::
264 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
265 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
271 //===----------------------------------------------------------------------===//
274 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
275 // that selects between the values 1 and 0, making it equivalent to a setcc.
276 // Also, set the incoming LHS, RHS, and CC references to the appropriate
277 // nodes based on the type of node we are checking. This simplifies life a
278 // bit for the callers.
279 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
281 if (N.getOpcode() == ISD::SETCC) {
282 LHS = N.getOperand(0);
283 RHS = N.getOperand(1);
284 CC = N.getOperand(2);
287 if (N.getOpcode() == ISD::SELECT_CC &&
288 N.getOperand(2).getOpcode() == ISD::Constant &&
289 N.getOperand(3).getOpcode() == ISD::Constant &&
290 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
291 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
292 LHS = N.getOperand(0);
293 RHS = N.getOperand(1);
294 CC = N.getOperand(4);
300 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
301 // one use. If this is true, it allows the users to invert the operation for
302 // free when it is profitable to do so.
303 static bool isOneUseSetCC(SDOperand N) {
304 SDOperand N0, N1, N2;
305 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
310 // FIXME: This should probably go in the ISD class rather than being duplicated
312 static bool isCommutativeBinOp(unsigned Opcode) {
318 case ISD::XOR: return true;
319 default: return false; // FIXME: Need commutative info for user ops!
323 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
324 MVT::ValueType VT = N0.getValueType();
325 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
326 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
327 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
328 if (isa<ConstantSDNode>(N1)) {
329 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
330 AddToWorkList(OpNode.Val);
331 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
332 } else if (N0.hasOneUse()) {
333 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
334 AddToWorkList(OpNode.Val);
335 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
338 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
339 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
340 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
341 if (isa<ConstantSDNode>(N0)) {
342 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
343 AddToWorkList(OpNode.Val);
344 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
345 } else if (N1.hasOneUse()) {
346 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
347 AddToWorkList(OpNode.Val);
348 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
354 void DAGCombiner::Run(bool RunningAfterLegalize) {
355 // set the instance variable, so that the various visit routines may use it.
356 AfterLegalize = RunningAfterLegalize;
358 // Add all the dag nodes to the worklist.
359 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
360 E = DAG.allnodes_end(); I != E; ++I)
361 WorkList.push_back(I);
363 // Create a dummy node (which is not added to allnodes), that adds a reference
364 // to the root node, preventing it from being deleted, and tracking any
365 // changes of the root.
366 HandleSDNode Dummy(DAG.getRoot());
369 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
370 TargetLowering::DAGCombinerInfo
371 DagCombineInfo(DAG, !RunningAfterLegalize, this);
373 // while the worklist isn't empty, inspect the node on the end of it and
374 // try and combine it.
375 while (!WorkList.empty()) {
376 SDNode *N = WorkList.back();
379 // If N has no uses, it is dead. Make sure to revisit all N's operands once
380 // N is deleted from the DAG, since they too may now be dead or may have a
381 // reduced number of uses, allowing other xforms.
382 if (N->use_empty() && N != &Dummy) {
383 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
384 WorkList.push_back(N->getOperand(i).Val);
386 removeFromWorkList(N);
391 SDOperand RV = visit(N);
393 // If nothing happened, try a target-specific DAG combine.
395 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
396 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
397 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
402 // If we get back the same node we passed in, rather than a new node or
403 // zero, we know that the node must have defined multiple values and
404 // CombineTo was used. Since CombineTo takes care of the worklist
405 // mechanics for us, we have no work to do in this case.
407 DEBUG(std::cerr << "\nReplacing "; N->dump();
408 std::cerr << "\nWith: "; RV.Val->dump(&DAG);
410 std::vector<SDNode*> NowDead;
411 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
413 // Push the new node and any users onto the worklist
414 WorkList.push_back(RV.Val);
415 AddUsersToWorkList(RV.Val);
417 // Nodes can end up on the worklist more than once. Make sure we do
418 // not process a node that has been replaced.
419 removeFromWorkList(N);
420 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
421 removeFromWorkList(NowDead[i]);
423 // Finally, since the node is now dead, remove it from the graph.
429 // If the root changed (e.g. it was a dead load, update the root).
430 DAG.setRoot(Dummy.getValue());
433 SDOperand DAGCombiner::visit(SDNode *N) {
434 switch(N->getOpcode()) {
436 case ISD::TokenFactor: return visitTokenFactor(N);
437 case ISD::ADD: return visitADD(N);
438 case ISD::SUB: return visitSUB(N);
439 case ISD::MUL: return visitMUL(N);
440 case ISD::SDIV: return visitSDIV(N);
441 case ISD::UDIV: return visitUDIV(N);
442 case ISD::SREM: return visitSREM(N);
443 case ISD::UREM: return visitUREM(N);
444 case ISD::MULHU: return visitMULHU(N);
445 case ISD::MULHS: return visitMULHS(N);
446 case ISD::AND: return visitAND(N);
447 case ISD::OR: return visitOR(N);
448 case ISD::XOR: return visitXOR(N);
449 case ISD::SHL: return visitSHL(N);
450 case ISD::SRA: return visitSRA(N);
451 case ISD::SRL: return visitSRL(N);
452 case ISD::CTLZ: return visitCTLZ(N);
453 case ISD::CTTZ: return visitCTTZ(N);
454 case ISD::CTPOP: return visitCTPOP(N);
455 case ISD::SELECT: return visitSELECT(N);
456 case ISD::SELECT_CC: return visitSELECT_CC(N);
457 case ISD::SETCC: return visitSETCC(N);
458 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
459 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
460 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
461 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
462 case ISD::TRUNCATE: return visitTRUNCATE(N);
463 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
464 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
465 case ISD::FADD: return visitFADD(N);
466 case ISD::FSUB: return visitFSUB(N);
467 case ISD::FMUL: return visitFMUL(N);
468 case ISD::FDIV: return visitFDIV(N);
469 case ISD::FREM: return visitFREM(N);
470 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
471 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
472 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
473 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
474 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
475 case ISD::FP_ROUND: return visitFP_ROUND(N);
476 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
477 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
478 case ISD::FNEG: return visitFNEG(N);
479 case ISD::FABS: return visitFABS(N);
480 case ISD::BRCOND: return visitBRCOND(N);
481 case ISD::BR_CC: return visitBR_CC(N);
482 case ISD::LOAD: return visitLOAD(N);
485 case ISD::ZEXTLOAD: return visitXEXTLOAD(N);
486 case ISD::STORE: return visitSTORE(N);
487 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
488 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
489 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
490 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
491 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
492 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
493 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
494 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
495 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
496 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
497 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
498 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
499 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
504 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
505 std::vector<SDOperand> Ops;
506 bool Changed = false;
508 // If the token factor has two operands and one is the entry token, replace
509 // the token factor with the other operand.
510 if (N->getNumOperands() == 2) {
511 if (N->getOperand(0).getOpcode() == ISD::EntryToken ||
512 N->getOperand(0) == N->getOperand(1))
513 return N->getOperand(1);
514 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
515 return N->getOperand(0);
518 // fold (tokenfactor (tokenfactor)) -> tokenfactor
519 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
520 SDOperand Op = N->getOperand(i);
521 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
522 AddToWorkList(Op.Val); // Remove dead node.
524 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
525 Ops.push_back(Op.getOperand(j));
526 } else if (i == 0 || N->getOperand(i) != N->getOperand(i-1)) {
529 // Deleted an operand that was the same as the last one.
534 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
538 SDOperand DAGCombiner::visitADD(SDNode *N) {
539 SDOperand N0 = N->getOperand(0);
540 SDOperand N1 = N->getOperand(1);
541 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
542 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
543 MVT::ValueType VT = N0.getValueType();
545 // fold (add c1, c2) -> c1+c2
547 return DAG.getNode(ISD::ADD, VT, N0, N1);
548 // canonicalize constant to RHS
550 return DAG.getNode(ISD::ADD, VT, N1, N0);
551 // fold (add x, 0) -> x
552 if (N1C && N1C->isNullValue())
554 // fold ((c1-A)+c2) -> (c1+c2)-A
555 if (N1C && N0.getOpcode() == ISD::SUB)
556 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
557 return DAG.getNode(ISD::SUB, VT,
558 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
561 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
564 // fold ((0-A) + B) -> B-A
565 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
566 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
567 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
568 // fold (A + (0-B)) -> A-B
569 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
570 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
571 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
572 // fold (A+(B-A)) -> B
573 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
574 return N1.getOperand(0);
576 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
577 return SDOperand(N, 0);
579 // fold (a+b) -> (a|b) iff a and b share no bits.
580 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
581 uint64_t LHSZero, LHSOne;
582 uint64_t RHSZero, RHSOne;
583 uint64_t Mask = MVT::getIntVTBitMask(VT);
584 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
586 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
588 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
589 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
590 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
591 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
592 return DAG.getNode(ISD::OR, VT, N0, N1);
599 SDOperand DAGCombiner::visitSUB(SDNode *N) {
600 SDOperand N0 = N->getOperand(0);
601 SDOperand N1 = N->getOperand(1);
602 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
603 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
604 MVT::ValueType VT = N0.getValueType();
606 // fold (sub x, x) -> 0
608 return DAG.getConstant(0, N->getValueType(0));
609 // fold (sub c1, c2) -> c1-c2
611 return DAG.getNode(ISD::SUB, VT, N0, N1);
612 // fold (sub x, c) -> (add x, -c)
614 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
616 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
617 return N0.getOperand(1);
619 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
620 return N0.getOperand(0);
624 SDOperand DAGCombiner::visitMUL(SDNode *N) {
625 SDOperand N0 = N->getOperand(0);
626 SDOperand N1 = N->getOperand(1);
627 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
628 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
629 MVT::ValueType VT = N0.getValueType();
631 // fold (mul c1, c2) -> c1*c2
633 return DAG.getNode(ISD::MUL, VT, N0, N1);
634 // canonicalize constant to RHS
636 return DAG.getNode(ISD::MUL, VT, N1, N0);
637 // fold (mul x, 0) -> 0
638 if (N1C && N1C->isNullValue())
640 // fold (mul x, -1) -> 0-x
641 if (N1C && N1C->isAllOnesValue())
642 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
643 // fold (mul x, (1 << c)) -> x << c
644 if (N1C && isPowerOf2_64(N1C->getValue()))
645 return DAG.getNode(ISD::SHL, VT, N0,
646 DAG.getConstant(Log2_64(N1C->getValue()),
647 TLI.getShiftAmountTy()));
648 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
649 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
650 // FIXME: If the input is something that is easily negated (e.g. a
651 // single-use add), we should put the negate there.
652 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
653 DAG.getNode(ISD::SHL, VT, N0,
654 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
655 TLI.getShiftAmountTy())));
658 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
659 if (N1C && N0.getOpcode() == ISD::SHL &&
660 isa<ConstantSDNode>(N0.getOperand(1))) {
661 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
662 AddToWorkList(C3.Val);
663 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
666 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
669 SDOperand Sh(0,0), Y(0,0);
670 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
671 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
672 N0.Val->hasOneUse()) {
674 } else if (N1.getOpcode() == ISD::SHL &&
675 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
679 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
680 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
683 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
684 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
685 isa<ConstantSDNode>(N0.getOperand(1))) {
686 return DAG.getNode(ISD::ADD, VT,
687 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
688 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
692 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
698 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
699 SDOperand N0 = N->getOperand(0);
700 SDOperand N1 = N->getOperand(1);
701 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
702 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
703 MVT::ValueType VT = N->getValueType(0);
705 // fold (sdiv c1, c2) -> c1/c2
706 if (N0C && N1C && !N1C->isNullValue())
707 return DAG.getNode(ISD::SDIV, VT, N0, N1);
708 // fold (sdiv X, 1) -> X
709 if (N1C && N1C->getSignExtended() == 1LL)
711 // fold (sdiv X, -1) -> 0-X
712 if (N1C && N1C->isAllOnesValue())
713 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
714 // If we know the sign bits of both operands are zero, strength reduce to a
715 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
716 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
717 if (TLI.MaskedValueIsZero(N1, SignBit) &&
718 TLI.MaskedValueIsZero(N0, SignBit))
719 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
720 // fold (sdiv X, pow2) -> simple ops after legalize
721 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
722 (isPowerOf2_64(N1C->getSignExtended()) ||
723 isPowerOf2_64(-N1C->getSignExtended()))) {
724 // If dividing by powers of two is cheap, then don't perform the following
726 if (TLI.isPow2DivCheap())
728 int64_t pow2 = N1C->getSignExtended();
729 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
730 unsigned lg2 = Log2_64(abs2);
731 // Splat the sign bit into the register
732 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
733 DAG.getConstant(MVT::getSizeInBits(VT)-1,
734 TLI.getShiftAmountTy()));
735 AddToWorkList(SGN.Val);
736 // Add (N0 < 0) ? abs2 - 1 : 0;
737 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
738 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
739 TLI.getShiftAmountTy()));
740 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
741 AddToWorkList(SRL.Val);
742 AddToWorkList(ADD.Val); // Divide by pow2
743 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
744 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
745 // If we're dividing by a positive value, we're done. Otherwise, we must
746 // negate the result.
749 AddToWorkList(SRA.Val);
750 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
752 // if integer divide is expensive and we satisfy the requirements, emit an
753 // alternate sequence.
754 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
755 !TLI.isIntDivCheap()) {
756 SDOperand Op = BuildSDIV(N);
757 if (Op.Val) return Op;
762 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
763 SDOperand N0 = N->getOperand(0);
764 SDOperand N1 = N->getOperand(1);
765 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
766 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
767 MVT::ValueType VT = N->getValueType(0);
769 // fold (udiv c1, c2) -> c1/c2
770 if (N0C && N1C && !N1C->isNullValue())
771 return DAG.getNode(ISD::UDIV, VT, N0, N1);
772 // fold (udiv x, (1 << c)) -> x >>u c
773 if (N1C && isPowerOf2_64(N1C->getValue()))
774 return DAG.getNode(ISD::SRL, VT, N0,
775 DAG.getConstant(Log2_64(N1C->getValue()),
776 TLI.getShiftAmountTy()));
777 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
778 if (N1.getOpcode() == ISD::SHL) {
779 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
780 if (isPowerOf2_64(SHC->getValue())) {
781 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
782 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
783 DAG.getConstant(Log2_64(SHC->getValue()),
785 AddToWorkList(Add.Val);
786 return DAG.getNode(ISD::SRL, VT, N0, Add);
790 // fold (udiv x, c) -> alternate
791 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
792 SDOperand Op = BuildUDIV(N);
793 if (Op.Val) return Op;
798 SDOperand DAGCombiner::visitSREM(SDNode *N) {
799 SDOperand N0 = N->getOperand(0);
800 SDOperand N1 = N->getOperand(1);
801 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
802 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
803 MVT::ValueType VT = N->getValueType(0);
805 // fold (srem c1, c2) -> c1%c2
806 if (N0C && N1C && !N1C->isNullValue())
807 return DAG.getNode(ISD::SREM, VT, N0, N1);
808 // If we know the sign bits of both operands are zero, strength reduce to a
809 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
810 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
811 if (TLI.MaskedValueIsZero(N1, SignBit) &&
812 TLI.MaskedValueIsZero(N0, SignBit))
813 return DAG.getNode(ISD::UREM, VT, N0, N1);
817 SDOperand DAGCombiner::visitUREM(SDNode *N) {
818 SDOperand N0 = N->getOperand(0);
819 SDOperand N1 = N->getOperand(1);
820 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
821 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
822 MVT::ValueType VT = N->getValueType(0);
824 // fold (urem c1, c2) -> c1%c2
825 if (N0C && N1C && !N1C->isNullValue())
826 return DAG.getNode(ISD::UREM, VT, N0, N1);
827 // fold (urem x, pow2) -> (and x, pow2-1)
828 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
829 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
830 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
831 if (N1.getOpcode() == ISD::SHL) {
832 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
833 if (isPowerOf2_64(SHC->getValue())) {
834 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
835 AddToWorkList(Add.Val);
836 return DAG.getNode(ISD::AND, VT, N0, Add);
843 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
844 SDOperand N0 = N->getOperand(0);
845 SDOperand N1 = N->getOperand(1);
846 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
848 // fold (mulhs x, 0) -> 0
849 if (N1C && N1C->isNullValue())
851 // fold (mulhs x, 1) -> (sra x, size(x)-1)
852 if (N1C && N1C->getValue() == 1)
853 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
854 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
855 TLI.getShiftAmountTy()));
859 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
860 SDOperand N0 = N->getOperand(0);
861 SDOperand N1 = N->getOperand(1);
862 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
864 // fold (mulhu x, 0) -> 0
865 if (N1C && N1C->isNullValue())
867 // fold (mulhu x, 1) -> 0
868 if (N1C && N1C->getValue() == 1)
869 return DAG.getConstant(0, N0.getValueType());
873 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
874 /// two operands of the same opcode, try to simplify it.
875 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
876 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
877 MVT::ValueType VT = N0.getValueType();
878 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
880 // For each of OP in AND/OR/XOR:
881 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
882 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
883 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
884 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
885 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
886 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
887 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
888 SDOperand ORNode = DAG.getNode(N->getOpcode(),
889 N0.getOperand(0).getValueType(),
890 N0.getOperand(0), N1.getOperand(0));
891 AddToWorkList(ORNode.Val);
892 return DAG.getNode(N0.getOpcode(), VT, ORNode);
895 // For each of OP in SHL/SRL/SRA/AND...
896 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
897 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
898 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
899 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
900 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
901 N0.getOperand(1) == N1.getOperand(1)) {
902 SDOperand ORNode = DAG.getNode(N->getOpcode(),
903 N0.getOperand(0).getValueType(),
904 N0.getOperand(0), N1.getOperand(0));
905 AddToWorkList(ORNode.Val);
906 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
912 SDOperand DAGCombiner::visitAND(SDNode *N) {
913 SDOperand N0 = N->getOperand(0);
914 SDOperand N1 = N->getOperand(1);
915 SDOperand LL, LR, RL, RR, CC0, CC1;
916 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
917 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
918 MVT::ValueType VT = N1.getValueType();
919 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
921 // fold (and c1, c2) -> c1&c2
923 return DAG.getNode(ISD::AND, VT, N0, N1);
924 // canonicalize constant to RHS
926 return DAG.getNode(ISD::AND, VT, N1, N0);
927 // fold (and x, -1) -> x
928 if (N1C && N1C->isAllOnesValue())
930 // if (and x, c) is known to be zero, return 0
931 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
932 return DAG.getConstant(0, VT);
934 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
937 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
938 if (N1C && N0.getOpcode() == ISD::OR)
939 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
940 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
942 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
943 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
944 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
945 if (TLI.MaskedValueIsZero(N0.getOperand(0),
946 ~N1C->getValue() & InMask)) {
947 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
950 // Replace uses of the AND with uses of the Zero extend node.
953 // We actually want to replace all uses of the any_extend with the
954 // zero_extend, to avoid duplicating things. This will later cause this
956 CombineTo(N0.Val, Zext);
957 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
960 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
961 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
962 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
963 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
965 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
966 MVT::isInteger(LL.getValueType())) {
967 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
968 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
969 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
970 AddToWorkList(ORNode.Val);
971 return DAG.getSetCC(VT, ORNode, LR, Op1);
973 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
974 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
975 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
976 AddToWorkList(ANDNode.Val);
977 return DAG.getSetCC(VT, ANDNode, LR, Op1);
979 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
980 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
981 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
982 AddToWorkList(ORNode.Val);
983 return DAG.getSetCC(VT, ORNode, LR, Op1);
986 // canonicalize equivalent to ll == rl
987 if (LL == RR && LR == RL) {
988 Op1 = ISD::getSetCCSwappedOperands(Op1);
991 if (LL == RL && LR == RR) {
992 bool isInteger = MVT::isInteger(LL.getValueType());
993 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
994 if (Result != ISD::SETCC_INVALID)
995 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
999 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1000 if (N0.getOpcode() == N1.getOpcode()) {
1001 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1002 if (Tmp.Val) return Tmp;
1005 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1006 // fold (and (sra)) -> (and (srl)) when possible.
1007 if (!MVT::isVector(VT) &&
1008 SimplifyDemandedBits(SDOperand(N, 0)))
1009 return SDOperand(N, 0);
1010 // fold (zext_inreg (extload x)) -> (zextload x)
1011 if (N0.getOpcode() == ISD::EXTLOAD) {
1012 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1013 // If we zero all the possible extended bits, then we can turn this into
1014 // a zextload if we are running before legalize or the operation is legal.
1015 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1016 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1017 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1018 N0.getOperand(1), N0.getOperand(2),
1021 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1022 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1025 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1026 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
1027 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1028 // If we zero all the possible extended bits, then we can turn this into
1029 // a zextload if we are running before legalize or the operation is legal.
1030 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1031 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1032 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1033 N0.getOperand(1), N0.getOperand(2),
1036 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1037 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1041 // fold (and (load x), 255) -> (zextload x, i8)
1042 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1044 (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD ||
1045 N0.getOpcode() == ISD::ZEXTLOAD) &&
1047 MVT::ValueType EVT, LoadedVT;
1048 if (N1C->getValue() == 255)
1050 else if (N1C->getValue() == 65535)
1052 else if (N1C->getValue() == ~0U)
1057 LoadedVT = N0.getOpcode() == ISD::LOAD ? VT :
1058 cast<VTSDNode>(N0.getOperand(3))->getVT();
1059 if (EVT != MVT::Other && LoadedVT > EVT &&
1060 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1061 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1062 // For big endian targets, we need to add an offset to the pointer to load
1063 // the correct bytes. For little endian systems, we merely need to read
1064 // fewer bytes from the same pointer.
1066 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1067 SDOperand NewPtr = N0.getOperand(1);
1068 if (!TLI.isLittleEndian())
1069 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1070 DAG.getConstant(PtrOff, PtrType));
1071 AddToWorkList(NewPtr.Val);
1073 DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), NewPtr,
1074 N0.getOperand(2), EVT);
1076 CombineTo(N0.Val, Load, Load.getValue(1));
1077 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1084 SDOperand DAGCombiner::visitOR(SDNode *N) {
1085 SDOperand N0 = N->getOperand(0);
1086 SDOperand N1 = N->getOperand(1);
1087 SDOperand LL, LR, RL, RR, CC0, CC1;
1088 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1089 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1090 MVT::ValueType VT = N1.getValueType();
1091 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1093 // fold (or c1, c2) -> c1|c2
1095 return DAG.getNode(ISD::OR, VT, N0, N1);
1096 // canonicalize constant to RHS
1098 return DAG.getNode(ISD::OR, VT, N1, N0);
1099 // fold (or x, 0) -> x
1100 if (N1C && N1C->isNullValue())
1102 // fold (or x, -1) -> -1
1103 if (N1C && N1C->isAllOnesValue())
1105 // fold (or x, c) -> c iff (x & ~c) == 0
1107 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1110 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1113 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1114 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1115 isa<ConstantSDNode>(N0.getOperand(1))) {
1116 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1117 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1119 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1121 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1122 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1123 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1124 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1126 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1127 MVT::isInteger(LL.getValueType())) {
1128 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1129 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1130 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1131 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1132 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1133 AddToWorkList(ORNode.Val);
1134 return DAG.getSetCC(VT, ORNode, LR, Op1);
1136 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1137 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1138 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1139 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1140 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1141 AddToWorkList(ANDNode.Val);
1142 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1145 // canonicalize equivalent to ll == rl
1146 if (LL == RR && LR == RL) {
1147 Op1 = ISD::getSetCCSwappedOperands(Op1);
1150 if (LL == RL && LR == RR) {
1151 bool isInteger = MVT::isInteger(LL.getValueType());
1152 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1153 if (Result != ISD::SETCC_INVALID)
1154 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1158 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1159 if (N0.getOpcode() == N1.getOpcode()) {
1160 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1161 if (Tmp.Val) return Tmp;
1164 // canonicalize shl to left side in a shl/srl pair, to match rotate
1165 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
1167 // check for rotl, rotr
1168 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
1169 N0.getOperand(0) == N1.getOperand(0) &&
1170 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
1171 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1172 if (N0.getOperand(1).getOpcode() == ISD::Constant &&
1173 N1.getOperand(1).getOpcode() == ISD::Constant) {
1174 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1175 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1176 if ((c1val + c2val) == OpSizeInBits)
1177 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1179 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1180 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
1181 N0.getOperand(1) == N1.getOperand(1).getOperand(1))
1182 if (ConstantSDNode *SUBC =
1183 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
1184 if (SUBC->getValue() == OpSizeInBits)
1185 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1186 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1187 if (N0.getOperand(1).getOpcode() == ISD::SUB &&
1188 N1.getOperand(1) == N0.getOperand(1).getOperand(1))
1189 if (ConstantSDNode *SUBC =
1190 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
1191 if (SUBC->getValue() == OpSizeInBits) {
1192 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
1193 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
1196 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
1203 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1204 SDOperand N0 = N->getOperand(0);
1205 SDOperand N1 = N->getOperand(1);
1206 SDOperand LHS, RHS, CC;
1207 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1208 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1209 MVT::ValueType VT = N0.getValueType();
1211 // fold (xor c1, c2) -> c1^c2
1213 return DAG.getNode(ISD::XOR, VT, N0, N1);
1214 // canonicalize constant to RHS
1216 return DAG.getNode(ISD::XOR, VT, N1, N0);
1217 // fold (xor x, 0) -> x
1218 if (N1C && N1C->isNullValue())
1221 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1224 // fold !(x cc y) -> (x !cc y)
1225 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1226 bool isInt = MVT::isInteger(LHS.getValueType());
1227 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1229 if (N0.getOpcode() == ISD::SETCC)
1230 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1231 if (N0.getOpcode() == ISD::SELECT_CC)
1232 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1233 assert(0 && "Unhandled SetCC Equivalent!");
1236 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1237 if (N1C && N1C->getValue() == 1 &&
1238 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1239 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1240 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1241 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1242 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1243 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1244 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1245 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1248 // fold !(x or y) -> (!x and !y) iff x or y are constants
1249 if (N1C && N1C->isAllOnesValue() &&
1250 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1251 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1252 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1253 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1254 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1255 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1256 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1257 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1260 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1261 if (N1C && N0.getOpcode() == ISD::XOR) {
1262 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1263 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1265 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1266 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1268 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1269 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1271 // fold (xor x, x) -> 0
1273 if (!MVT::isVector(VT)) {
1274 return DAG.getConstant(0, VT);
1275 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1276 // Produce a vector of zeros.
1277 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1278 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1279 return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
1283 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1284 if (N0.getOpcode() == N1.getOpcode()) {
1285 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1286 if (Tmp.Val) return Tmp;
1289 // Simplify the expression using non-local knowledge.
1290 if (!MVT::isVector(VT) &&
1291 SimplifyDemandedBits(SDOperand(N, 0)))
1292 return SDOperand(N, 0);
1297 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1298 SDOperand N0 = N->getOperand(0);
1299 SDOperand N1 = N->getOperand(1);
1300 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1301 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1302 MVT::ValueType VT = N0.getValueType();
1303 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1305 // fold (shl c1, c2) -> c1<<c2
1307 return DAG.getNode(ISD::SHL, VT, N0, N1);
1308 // fold (shl 0, x) -> 0
1309 if (N0C && N0C->isNullValue())
1311 // fold (shl x, c >= size(x)) -> undef
1312 if (N1C && N1C->getValue() >= OpSizeInBits)
1313 return DAG.getNode(ISD::UNDEF, VT);
1314 // fold (shl x, 0) -> x
1315 if (N1C && N1C->isNullValue())
1317 // if (shl x, c) is known to be zero, return 0
1318 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1319 return DAG.getConstant(0, VT);
1320 if (SimplifyDemandedBits(SDOperand(N, 0)))
1321 return SDOperand(N, 0);
1322 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1323 if (N1C && N0.getOpcode() == ISD::SHL &&
1324 N0.getOperand(1).getOpcode() == ISD::Constant) {
1325 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1326 uint64_t c2 = N1C->getValue();
1327 if (c1 + c2 > OpSizeInBits)
1328 return DAG.getConstant(0, VT);
1329 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1330 DAG.getConstant(c1 + c2, N1.getValueType()));
1332 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1333 // (srl (and x, -1 << c1), c1-c2)
1334 if (N1C && N0.getOpcode() == ISD::SRL &&
1335 N0.getOperand(1).getOpcode() == ISD::Constant) {
1336 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1337 uint64_t c2 = N1C->getValue();
1338 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1339 DAG.getConstant(~0ULL << c1, VT));
1341 return DAG.getNode(ISD::SHL, VT, Mask,
1342 DAG.getConstant(c2-c1, N1.getValueType()));
1344 return DAG.getNode(ISD::SRL, VT, Mask,
1345 DAG.getConstant(c1-c2, N1.getValueType()));
1347 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1348 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1349 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1350 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1351 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1352 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1353 isa<ConstantSDNode>(N0.getOperand(1))) {
1354 return DAG.getNode(ISD::ADD, VT,
1355 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1356 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1361 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1362 SDOperand N0 = N->getOperand(0);
1363 SDOperand N1 = N->getOperand(1);
1364 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1365 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1366 MVT::ValueType VT = N0.getValueType();
1368 // fold (sra c1, c2) -> c1>>c2
1370 return DAG.getNode(ISD::SRA, VT, N0, N1);
1371 // fold (sra 0, x) -> 0
1372 if (N0C && N0C->isNullValue())
1374 // fold (sra -1, x) -> -1
1375 if (N0C && N0C->isAllOnesValue())
1377 // fold (sra x, c >= size(x)) -> undef
1378 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1379 return DAG.getNode(ISD::UNDEF, VT);
1380 // fold (sra x, 0) -> x
1381 if (N1C && N1C->isNullValue())
1383 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1385 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1386 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1389 default: EVT = MVT::Other; break;
1390 case 1: EVT = MVT::i1; break;
1391 case 8: EVT = MVT::i8; break;
1392 case 16: EVT = MVT::i16; break;
1393 case 32: EVT = MVT::i32; break;
1395 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1396 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1397 DAG.getValueType(EVT));
1400 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1401 if (N1C && N0.getOpcode() == ISD::SRA) {
1402 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1403 unsigned Sum = N1C->getValue() + C1->getValue();
1404 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1405 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1406 DAG.getConstant(Sum, N1C->getValueType(0)));
1410 // Simplify, based on bits shifted out of the LHS.
1411 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1412 return SDOperand(N, 0);
1415 // If the sign bit is known to be zero, switch this to a SRL.
1416 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1417 return DAG.getNode(ISD::SRL, VT, N0, N1);
1421 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1422 SDOperand N0 = N->getOperand(0);
1423 SDOperand N1 = N->getOperand(1);
1424 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1425 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1426 MVT::ValueType VT = N0.getValueType();
1427 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1429 // fold (srl c1, c2) -> c1 >>u c2
1431 return DAG.getNode(ISD::SRL, VT, N0, N1);
1432 // fold (srl 0, x) -> 0
1433 if (N0C && N0C->isNullValue())
1435 // fold (srl x, c >= size(x)) -> undef
1436 if (N1C && N1C->getValue() >= OpSizeInBits)
1437 return DAG.getNode(ISD::UNDEF, VT);
1438 // fold (srl x, 0) -> x
1439 if (N1C && N1C->isNullValue())
1441 // if (srl x, c) is known to be zero, return 0
1442 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1443 return DAG.getConstant(0, VT);
1444 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1445 if (N1C && N0.getOpcode() == ISD::SRL &&
1446 N0.getOperand(1).getOpcode() == ISD::Constant) {
1447 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1448 uint64_t c2 = N1C->getValue();
1449 if (c1 + c2 > OpSizeInBits)
1450 return DAG.getConstant(0, VT);
1451 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1452 DAG.getConstant(c1 + c2, N1.getValueType()));
1455 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1456 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1457 // Shifting in all undef bits?
1458 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1459 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1460 return DAG.getNode(ISD::UNDEF, VT);
1462 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1463 AddToWorkList(SmallShift.Val);
1464 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1467 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1468 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1469 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1470 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1471 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1473 // If any of the input bits are KnownOne, then the input couldn't be all
1474 // zeros, thus the result of the srl will always be zero.
1475 if (KnownOne) return DAG.getConstant(0, VT);
1477 // If all of the bits input the to ctlz node are known to be zero, then
1478 // the result of the ctlz is "32" and the result of the shift is one.
1479 uint64_t UnknownBits = ~KnownZero & Mask;
1480 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1482 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1483 if ((UnknownBits & (UnknownBits-1)) == 0) {
1484 // Okay, we know that only that the single bit specified by UnknownBits
1485 // could be set on input to the CTLZ node. If this bit is set, the SRL
1486 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1487 // to an SRL,XOR pair, which is likely to simplify more.
1488 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1489 SDOperand Op = N0.getOperand(0);
1491 Op = DAG.getNode(ISD::SRL, VT, Op,
1492 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1493 AddToWorkList(Op.Val);
1495 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1502 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1503 SDOperand N0 = N->getOperand(0);
1504 MVT::ValueType VT = N->getValueType(0);
1506 // fold (ctlz c1) -> c2
1507 if (isa<ConstantSDNode>(N0))
1508 return DAG.getNode(ISD::CTLZ, VT, N0);
1512 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1513 SDOperand N0 = N->getOperand(0);
1514 MVT::ValueType VT = N->getValueType(0);
1516 // fold (cttz c1) -> c2
1517 if (isa<ConstantSDNode>(N0))
1518 return DAG.getNode(ISD::CTTZ, VT, N0);
1522 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1523 SDOperand N0 = N->getOperand(0);
1524 MVT::ValueType VT = N->getValueType(0);
1526 // fold (ctpop c1) -> c2
1527 if (isa<ConstantSDNode>(N0))
1528 return DAG.getNode(ISD::CTPOP, VT, N0);
1532 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1533 SDOperand N0 = N->getOperand(0);
1534 SDOperand N1 = N->getOperand(1);
1535 SDOperand N2 = N->getOperand(2);
1536 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1537 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1538 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1539 MVT::ValueType VT = N->getValueType(0);
1541 // fold select C, X, X -> X
1544 // fold select true, X, Y -> X
1545 if (N0C && !N0C->isNullValue())
1547 // fold select false, X, Y -> Y
1548 if (N0C && N0C->isNullValue())
1550 // fold select C, 1, X -> C | X
1551 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1552 return DAG.getNode(ISD::OR, VT, N0, N2);
1553 // fold select C, 0, X -> ~C & X
1554 // FIXME: this should check for C type == X type, not i1?
1555 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1556 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1557 AddToWorkList(XORNode.Val);
1558 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1560 // fold select C, X, 1 -> ~C | X
1561 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1562 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1563 AddToWorkList(XORNode.Val);
1564 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1566 // fold select C, X, 0 -> C & X
1567 // FIXME: this should check for C type == X type, not i1?
1568 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1569 return DAG.getNode(ISD::AND, VT, N0, N1);
1570 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1571 if (MVT::i1 == VT && N0 == N1)
1572 return DAG.getNode(ISD::OR, VT, N0, N2);
1573 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1574 if (MVT::i1 == VT && N0 == N2)
1575 return DAG.getNode(ISD::AND, VT, N0, N1);
1576 // If we can fold this based on the true/false value, do so.
1577 if (SimplifySelectOps(N, N1, N2))
1579 // fold selects based on a setcc into other things, such as min/max/abs
1580 if (N0.getOpcode() == ISD::SETCC)
1582 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1583 // having to say they don't support SELECT_CC on every type the DAG knows
1584 // about, since there is no way to mark an opcode illegal at all value types
1585 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1586 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1587 N1, N2, N0.getOperand(2));
1589 return SimplifySelect(N0, N1, N2);
1593 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1594 SDOperand N0 = N->getOperand(0);
1595 SDOperand N1 = N->getOperand(1);
1596 SDOperand N2 = N->getOperand(2);
1597 SDOperand N3 = N->getOperand(3);
1598 SDOperand N4 = N->getOperand(4);
1599 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1600 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1601 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1602 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1604 // Determine if the condition we're dealing with is constant
1605 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1606 //ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1608 // fold select_cc lhs, rhs, x, x, cc -> x
1612 // If we can fold this based on the true/false value, do so.
1613 if (SimplifySelectOps(N, N2, N3))
1616 // fold select_cc into other things, such as min/max/abs
1617 return SimplifySelectCC(N0, N1, N2, N3, CC);
1620 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1621 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1622 cast<CondCodeSDNode>(N->getOperand(2))->get());
1625 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1626 SDOperand N0 = N->getOperand(0);
1627 MVT::ValueType VT = N->getValueType(0);
1629 // fold (sext c1) -> c1
1630 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1631 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1633 // fold (sext (sext x)) -> (sext x)
1634 // fold (sext (aext x)) -> (sext x)
1635 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1636 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1638 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
1639 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1641 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
1642 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1643 DAG.getValueType(N0.getValueType()));
1645 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1646 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1647 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
1648 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1649 N0.getOperand(1), N0.getOperand(2),
1651 CombineTo(N, ExtLoad);
1652 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1653 ExtLoad.getValue(1));
1654 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1657 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1658 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1659 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1661 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1662 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1663 N0.getOperand(1), N0.getOperand(2), EVT);
1664 CombineTo(N, ExtLoad);
1665 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1666 ExtLoad.getValue(1));
1667 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1673 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1674 SDOperand N0 = N->getOperand(0);
1675 MVT::ValueType VT = N->getValueType(0);
1677 // fold (zext c1) -> c1
1678 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0))
1679 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1680 // fold (zext (zext x)) -> (zext x)
1681 // fold (zext (aext x)) -> (zext x)
1682 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1683 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1684 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
1685 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1686 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType())))
1687 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
1688 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1689 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1690 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
1691 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1692 N0.getOperand(1), N0.getOperand(2),
1694 CombineTo(N, ExtLoad);
1695 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1696 ExtLoad.getValue(1));
1697 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1700 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1701 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1702 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1704 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1705 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1706 N0.getOperand(1), N0.getOperand(2), EVT);
1707 CombineTo(N, ExtLoad);
1708 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1709 ExtLoad.getValue(1));
1710 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1715 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
1716 SDOperand N0 = N->getOperand(0);
1717 MVT::ValueType VT = N->getValueType(0);
1719 // fold (aext c1) -> c1
1720 if (isa<ConstantSDNode>(N0))
1721 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
1722 // fold (aext (aext x)) -> (aext x)
1723 // fold (aext (zext x)) -> (zext x)
1724 // fold (aext (sext x)) -> (sext x)
1725 if (N0.getOpcode() == ISD::ANY_EXTEND ||
1726 N0.getOpcode() == ISD::ZERO_EXTEND ||
1727 N0.getOpcode() == ISD::SIGN_EXTEND)
1728 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1730 // fold (aext (truncate x)) -> x iff x size == zext size.
1731 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT)
1732 return N0.getOperand(0);
1733 // fold (aext (load x)) -> (aext (truncate (extload x)))
1734 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1735 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) {
1736 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0),
1737 N0.getOperand(1), N0.getOperand(2),
1739 CombineTo(N, ExtLoad);
1740 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1741 ExtLoad.getValue(1));
1742 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1745 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
1746 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
1747 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
1748 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD ||
1749 N0.getOpcode() == ISD::SEXTLOAD) &&
1751 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1752 SDOperand ExtLoad = DAG.getExtLoad(N0.getOpcode(), VT, N0.getOperand(0),
1753 N0.getOperand(1), N0.getOperand(2), EVT);
1754 CombineTo(N, ExtLoad);
1755 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1756 ExtLoad.getValue(1));
1757 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1763 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1764 SDOperand N0 = N->getOperand(0);
1765 SDOperand N1 = N->getOperand(1);
1766 MVT::ValueType VT = N->getValueType(0);
1767 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1768 unsigned EVTBits = MVT::getSizeInBits(EVT);
1770 // fold (sext_in_reg c1) -> c1
1771 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
1772 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
1774 // If the input is already sign extended, just drop the extension.
1775 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
1778 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1779 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1780 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1781 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1784 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1785 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
1786 return DAG.getZeroExtendInReg(N0, EVT);
1788 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
1789 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
1790 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
1791 if (N0.getOpcode() == ISD::SRL) {
1792 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1793 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
1794 // We can turn this into an SRA iff the input to the SRL is already sign
1796 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
1797 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
1798 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
1802 // fold (sext_inreg (extload x)) -> (sextload x)
1803 if (N0.getOpcode() == ISD::EXTLOAD &&
1804 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1805 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1806 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1807 N0.getOperand(1), N0.getOperand(2),
1809 CombineTo(N, ExtLoad);
1810 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1811 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1813 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1814 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
1815 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1816 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1817 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1818 N0.getOperand(1), N0.getOperand(2),
1820 CombineTo(N, ExtLoad);
1821 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1822 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1827 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1828 SDOperand N0 = N->getOperand(0);
1829 MVT::ValueType VT = N->getValueType(0);
1832 if (N0.getValueType() == N->getValueType(0))
1834 // fold (truncate c1) -> c1
1835 if (isa<ConstantSDNode>(N0))
1836 return DAG.getNode(ISD::TRUNCATE, VT, N0);
1837 // fold (truncate (truncate x)) -> (truncate x)
1838 if (N0.getOpcode() == ISD::TRUNCATE)
1839 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1840 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1841 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
1842 N0.getOpcode() == ISD::ANY_EXTEND) {
1843 if (N0.getValueType() < VT)
1844 // if the source is smaller than the dest, we still need an extend
1845 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1846 else if (N0.getValueType() > VT)
1847 // if the source is larger than the dest, than we just need the truncate
1848 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1850 // if the source and dest are the same type, we can drop both the extend
1852 return N0.getOperand(0);
1854 // fold (truncate (load x)) -> (smaller load x)
1855 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1856 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1857 "Cannot truncate to larger type!");
1858 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1859 // For big endian targets, we need to add an offset to the pointer to load
1860 // the correct bytes. For little endian systems, we merely need to read
1861 // fewer bytes from the same pointer.
1863 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1864 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1865 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1866 DAG.getConstant(PtrOff, PtrType));
1867 AddToWorkList(NewPtr.Val);
1868 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1870 CombineTo(N0.Val, Load, Load.getValue(1));
1871 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1876 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
1877 SDOperand N0 = N->getOperand(0);
1878 MVT::ValueType VT = N->getValueType(0);
1880 // If the input is a constant, let getNode() fold it.
1881 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
1882 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
1883 if (Res.Val != N) return Res;
1886 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
1887 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
1889 // fold (conv (load x)) -> (load (conv*)x)
1890 // FIXME: These xforms need to know that the resultant load doesn't need a
1891 // higher alignment than the original!
1892 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1893 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
1896 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
1904 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
1905 SDOperand N0 = N->getOperand(0);
1906 MVT::ValueType VT = N->getValueType(0);
1908 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
1909 // First check to see if this is all constant.
1910 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
1911 VT == MVT::Vector) {
1912 bool isSimple = true;
1913 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
1914 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
1915 N0.getOperand(i).getOpcode() != ISD::Constant &&
1916 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
1921 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
1922 if (isSimple && !MVT::isVector(DestEltVT)) {
1923 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
1930 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
1931 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
1932 /// destination element value type.
1933 SDOperand DAGCombiner::
1934 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
1935 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
1937 // If this is already the right type, we're done.
1938 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
1940 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
1941 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
1943 // If this is a conversion of N elements of one type to N elements of another
1944 // type, convert each element. This handles FP<->INT cases.
1945 if (SrcBitSize == DstBitSize) {
1946 std::vector<SDOperand> Ops;
1947 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
1948 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
1949 AddToWorkList(Ops.back().Val);
1951 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
1952 Ops.push_back(DAG.getValueType(DstEltVT));
1953 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
1956 // Otherwise, we're growing or shrinking the elements. To avoid having to
1957 // handle annoying details of growing/shrinking FP values, we convert them to
1959 if (MVT::isFloatingPoint(SrcEltVT)) {
1960 // Convert the input float vector to a int vector where the elements are the
1962 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
1963 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
1964 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
1968 // Now we know the input is an integer vector. If the output is a FP type,
1969 // convert to integer first, then to FP of the right size.
1970 if (MVT::isFloatingPoint(DstEltVT)) {
1971 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
1972 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
1973 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
1975 // Next, convert to FP elements of the same size.
1976 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
1979 // Okay, we know the src/dst types are both integers of differing types.
1980 // Handling growing first.
1981 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
1982 if (SrcBitSize < DstBitSize) {
1983 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
1985 std::vector<SDOperand> Ops;
1986 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
1987 i += NumInputsPerOutput) {
1988 bool isLE = TLI.isLittleEndian();
1989 uint64_t NewBits = 0;
1990 bool EltIsUndef = true;
1991 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
1992 // Shift the previously computed bits over.
1993 NewBits <<= SrcBitSize;
1994 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
1995 if (Op.getOpcode() == ISD::UNDEF) continue;
1998 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2002 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2004 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2007 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2008 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2009 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
2012 // Finally, this must be the case where we are shrinking elements: each input
2013 // turns into multiple outputs.
2014 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2015 std::vector<SDOperand> Ops;
2016 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2017 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2018 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2019 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2022 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2024 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2025 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2026 OpVal >>= DstBitSize;
2027 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2030 // For big endian targets, swap the order of the pieces of each element.
2031 if (!TLI.isLittleEndian())
2032 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2034 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2035 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2036 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
2041 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2042 SDOperand N0 = N->getOperand(0);
2043 SDOperand N1 = N->getOperand(1);
2044 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2045 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2046 MVT::ValueType VT = N->getValueType(0);
2048 // fold (fadd c1, c2) -> c1+c2
2050 return DAG.getNode(ISD::FADD, VT, N0, N1);
2051 // canonicalize constant to RHS
2052 if (N0CFP && !N1CFP)
2053 return DAG.getNode(ISD::FADD, VT, N1, N0);
2054 // fold (A + (-B)) -> A-B
2055 if (N1.getOpcode() == ISD::FNEG)
2056 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2057 // fold ((-A) + B) -> B-A
2058 if (N0.getOpcode() == ISD::FNEG)
2059 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2063 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2064 SDOperand N0 = N->getOperand(0);
2065 SDOperand N1 = N->getOperand(1);
2066 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2067 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2068 MVT::ValueType VT = N->getValueType(0);
2070 // fold (fsub c1, c2) -> c1-c2
2072 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2073 // fold (A-(-B)) -> A+B
2074 if (N1.getOpcode() == ISD::FNEG)
2075 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2079 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2080 SDOperand N0 = N->getOperand(0);
2081 SDOperand N1 = N->getOperand(1);
2082 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2083 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2084 MVT::ValueType VT = N->getValueType(0);
2086 // fold (fmul c1, c2) -> c1*c2
2088 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2089 // canonicalize constant to RHS
2090 if (N0CFP && !N1CFP)
2091 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2092 // fold (fmul X, 2.0) -> (fadd X, X)
2093 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2094 return DAG.getNode(ISD::FADD, VT, N0, N0);
2098 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2099 SDOperand N0 = N->getOperand(0);
2100 SDOperand N1 = N->getOperand(1);
2101 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2102 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2103 MVT::ValueType VT = N->getValueType(0);
2105 // fold (fdiv c1, c2) -> c1/c2
2107 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2111 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2112 SDOperand N0 = N->getOperand(0);
2113 SDOperand N1 = N->getOperand(1);
2114 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2115 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2116 MVT::ValueType VT = N->getValueType(0);
2118 // fold (frem c1, c2) -> fmod(c1,c2)
2120 return DAG.getNode(ISD::FREM, VT, N0, N1);
2124 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2125 SDOperand N0 = N->getOperand(0);
2126 SDOperand N1 = N->getOperand(1);
2127 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2128 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2129 MVT::ValueType VT = N->getValueType(0);
2131 if (N0CFP && N1CFP) // Constant fold
2132 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2135 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2136 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2141 u.d = N1CFP->getValue();
2143 return DAG.getNode(ISD::FABS, VT, N0);
2145 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2148 // copysign(fabs(x), y) -> copysign(x, y)
2149 // copysign(fneg(x), y) -> copysign(x, y)
2150 // copysign(copysign(x,z), y) -> copysign(x, y)
2151 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2152 N0.getOpcode() == ISD::FCOPYSIGN)
2153 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2155 // copysign(x, abs(y)) -> abs(x)
2156 if (N1.getOpcode() == ISD::FABS)
2157 return DAG.getNode(ISD::FABS, VT, N0);
2159 // copysign(x, copysign(y,z)) -> copysign(x, z)
2160 if (N1.getOpcode() == ISD::FCOPYSIGN)
2161 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2163 // copysign(x, fp_extend(y)) -> copysign(x, y)
2164 // copysign(x, fp_round(y)) -> copysign(x, y)
2165 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2166 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2173 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2174 SDOperand N0 = N->getOperand(0);
2175 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2176 MVT::ValueType VT = N->getValueType(0);
2178 // fold (sint_to_fp c1) -> c1fp
2180 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2184 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2185 SDOperand N0 = N->getOperand(0);
2186 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2187 MVT::ValueType VT = N->getValueType(0);
2189 // fold (uint_to_fp c1) -> c1fp
2191 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2195 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2196 SDOperand N0 = N->getOperand(0);
2197 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2198 MVT::ValueType VT = N->getValueType(0);
2200 // fold (fp_to_sint c1fp) -> c1
2202 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2206 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2207 SDOperand N0 = N->getOperand(0);
2208 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2209 MVT::ValueType VT = N->getValueType(0);
2211 // fold (fp_to_uint c1fp) -> c1
2213 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2217 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2218 SDOperand N0 = N->getOperand(0);
2219 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2220 MVT::ValueType VT = N->getValueType(0);
2222 // fold (fp_round c1fp) -> c1fp
2224 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2226 // fold (fp_round (fp_extend x)) -> x
2227 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2228 return N0.getOperand(0);
2230 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2231 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2232 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2233 AddToWorkList(Tmp.Val);
2234 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2240 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2241 SDOperand N0 = N->getOperand(0);
2242 MVT::ValueType VT = N->getValueType(0);
2243 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2244 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2246 // fold (fp_round_inreg c1fp) -> c1fp
2248 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2249 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2254 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2255 SDOperand N0 = N->getOperand(0);
2256 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2257 MVT::ValueType VT = N->getValueType(0);
2259 // fold (fp_extend c1fp) -> c1fp
2261 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2263 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2264 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
2265 (!AfterLegalize||TLI.isOperationLegal(ISD::EXTLOAD, N0.getValueType()))) {
2266 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, N0.getOperand(0),
2267 N0.getOperand(1), N0.getOperand(2),
2269 CombineTo(N, ExtLoad);
2270 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2271 ExtLoad.getValue(1));
2272 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2279 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2280 SDOperand N0 = N->getOperand(0);
2281 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2282 MVT::ValueType VT = N->getValueType(0);
2284 // fold (fneg c1) -> -c1
2286 return DAG.getNode(ISD::FNEG, VT, N0);
2287 // fold (fneg (sub x, y)) -> (sub y, x)
2288 if (N0.getOpcode() == ISD::SUB)
2289 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2290 // fold (fneg (fneg x)) -> x
2291 if (N0.getOpcode() == ISD::FNEG)
2292 return N0.getOperand(0);
2296 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2297 SDOperand N0 = N->getOperand(0);
2298 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2299 MVT::ValueType VT = N->getValueType(0);
2301 // fold (fabs c1) -> fabs(c1)
2303 return DAG.getNode(ISD::FABS, VT, N0);
2304 // fold (fabs (fabs x)) -> (fabs x)
2305 if (N0.getOpcode() == ISD::FABS)
2306 return N->getOperand(0);
2307 // fold (fabs (fneg x)) -> (fabs x)
2308 // fold (fabs (fcopysign x, y)) -> (fabs x)
2309 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2310 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2315 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2316 SDOperand Chain = N->getOperand(0);
2317 SDOperand N1 = N->getOperand(1);
2318 SDOperand N2 = N->getOperand(2);
2319 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2321 // never taken branch, fold to chain
2322 if (N1C && N1C->isNullValue())
2324 // unconditional branch
2325 if (N1C && N1C->getValue() == 1)
2326 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2327 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2329 if (N1.getOpcode() == ISD::SETCC &&
2330 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2331 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2332 N1.getOperand(0), N1.getOperand(1), N2);
2337 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2339 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2340 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2341 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2343 // Use SimplifySetCC to simplify SETCC's.
2344 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2345 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2347 // fold br_cc true, dest -> br dest (unconditional branch)
2348 if (SCCC && SCCC->getValue())
2349 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2351 // fold br_cc false, dest -> unconditional fall through
2352 if (SCCC && SCCC->isNullValue())
2353 return N->getOperand(0);
2354 // fold to a simpler setcc
2355 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2356 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2357 Simp.getOperand(2), Simp.getOperand(0),
2358 Simp.getOperand(1), N->getOperand(4));
2362 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2363 SDOperand Chain = N->getOperand(0);
2364 SDOperand Ptr = N->getOperand(1);
2365 SDOperand SrcValue = N->getOperand(2);
2367 // If there are no uses of the loaded value, change uses of the chain value
2368 // into uses of the chain input (i.e. delete the dead load).
2369 if (N->hasNUsesOfValue(0, 0))
2370 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2372 // If this load is directly stored, replace the load value with the stored
2374 // TODO: Handle store large -> read small portion.
2375 // TODO: Handle TRUNCSTORE/EXTLOAD
2376 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2377 Chain.getOperand(1).getValueType() == N->getValueType(0))
2378 return CombineTo(N, Chain.getOperand(1), Chain);
2383 /// visitXEXTLOAD - Handle EXTLOAD/ZEXTLOAD/SEXTLOAD.
2384 SDOperand DAGCombiner::visitXEXTLOAD(SDNode *N) {
2385 SDOperand Chain = N->getOperand(0);
2386 SDOperand Ptr = N->getOperand(1);
2387 SDOperand SrcValue = N->getOperand(2);
2388 SDOperand EVT = N->getOperand(3);
2390 // If there are no uses of the loaded value, change uses of the chain value
2391 // into uses of the chain input (i.e. delete the dead load).
2392 if (N->hasNUsesOfValue(0, 0))
2393 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2398 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2399 SDOperand Chain = N->getOperand(0);
2400 SDOperand Value = N->getOperand(1);
2401 SDOperand Ptr = N->getOperand(2);
2402 SDOperand SrcValue = N->getOperand(3);
2404 // If this is a store that kills a previous store, remove the previous store.
2405 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2406 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2407 // Make sure that these stores are the same value type:
2408 // FIXME: we really care that the second store is >= size of the first.
2409 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2410 // Create a new store of Value that replaces both stores.
2411 SDNode *PrevStore = Chain.Val;
2412 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2414 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
2415 PrevStore->getOperand(0), Value, Ptr,
2417 CombineTo(N, NewStore); // Nuke this store.
2418 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2419 return SDOperand(N, 0);
2422 // If this is a store of a bit convert, store the input value.
2423 // FIXME: This needs to know that the resultant store does not need a
2424 // higher alignment than the original.
2425 if (0 && Value.getOpcode() == ISD::BIT_CONVERT)
2426 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
2432 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
2433 SDOperand InVec = N->getOperand(0);
2434 SDOperand InVal = N->getOperand(1);
2435 SDOperand EltNo = N->getOperand(2);
2437 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
2438 // vector with the inserted element.
2439 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2440 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2441 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2442 if (Elt < Ops.size())
2444 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), Ops);
2450 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
2451 SDOperand InVec = N->getOperand(0);
2452 SDOperand InVal = N->getOperand(1);
2453 SDOperand EltNo = N->getOperand(2);
2454 SDOperand NumElts = N->getOperand(3);
2455 SDOperand EltType = N->getOperand(4);
2457 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
2458 // vector with the inserted element.
2459 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
2460 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
2461 std::vector<SDOperand> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
2462 if (Elt < Ops.size()-2)
2464 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), Ops);
2470 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
2471 unsigned NumInScalars = N->getNumOperands()-2;
2472 SDOperand NumElts = N->getOperand(NumInScalars);
2473 SDOperand EltType = N->getOperand(NumInScalars+1);
2475 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
2476 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
2477 // two distinct vectors, turn this into a shuffle node.
2478 SDOperand VecIn1, VecIn2;
2479 for (unsigned i = 0; i != NumInScalars; ++i) {
2480 // Ignore undef inputs.
2481 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2483 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
2484 // constant index, bail out.
2485 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
2486 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
2487 VecIn1 = VecIn2 = SDOperand(0, 0);
2491 // If the input vector type disagrees with the result of the vbuild_vector,
2492 // we can't make a shuffle.
2493 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
2494 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
2495 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
2496 VecIn1 = VecIn2 = SDOperand(0, 0);
2500 // Otherwise, remember this. We allow up to two distinct input vectors.
2501 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
2504 if (VecIn1.Val == 0) {
2505 VecIn1 = ExtractedFromVec;
2506 } else if (VecIn2.Val == 0) {
2507 VecIn2 = ExtractedFromVec;
2510 VecIn1 = VecIn2 = SDOperand(0, 0);
2515 // If everything is good, we can make a shuffle operation.
2517 std::vector<SDOperand> BuildVecIndices;
2518 for (unsigned i = 0; i != NumInScalars; ++i) {
2519 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
2520 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2524 SDOperand Extract = N->getOperand(i);
2526 // If extracting from the first vector, just use the index directly.
2527 if (Extract.getOperand(0) == VecIn1) {
2528 BuildVecIndices.push_back(Extract.getOperand(1));
2532 // Otherwise, use InIdx + VecSize
2533 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
2534 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
2537 // Add count and size info.
2538 BuildVecIndices.push_back(NumElts);
2539 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
2541 // Return the new VVECTOR_SHUFFLE node.
2542 std::vector<SDOperand> Ops;
2543 Ops.push_back(VecIn1);
2545 Ops.push_back(VecIn2);
2547 // Use an undef vbuild_vector as input for the second operand.
2548 std::vector<SDOperand> UnOps(NumInScalars,
2549 DAG.getNode(ISD::UNDEF,
2550 cast<VTSDNode>(EltType)->getVT()));
2551 UnOps.push_back(NumElts);
2552 UnOps.push_back(EltType);
2553 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, UnOps));
2554 AddToWorkList(Ops.back().Val);
2556 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR,MVT::Vector, BuildVecIndices));
2557 Ops.push_back(NumElts);
2558 Ops.push_back(EltType);
2559 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
2565 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
2566 SDOperand ShufMask = N->getOperand(2);
2567 unsigned NumElts = ShufMask.getNumOperands();
2569 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2570 bool isIdentity = true;
2571 for (unsigned i = 0; i != NumElts; ++i) {
2572 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2573 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2578 if (isIdentity) return N->getOperand(0);
2580 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2582 for (unsigned i = 0; i != NumElts; ++i) {
2583 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2584 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2589 if (isIdentity) return N->getOperand(1);
2591 // If the LHS and the RHS are the same node, turn the RHS into an undef.
2592 if (N->getOperand(0) == N->getOperand(1)) {
2593 if (N->getOperand(0).getOpcode() == ISD::UNDEF)
2594 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
2595 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
2597 std::vector<SDOperand> MappedOps;
2598 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
2599 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
2600 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
2601 MappedOps.push_back(ShufMask.getOperand(i));
2604 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
2605 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
2608 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
2610 AddToWorkList(ShufMask.Val);
2611 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
2613 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
2620 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
2621 SDOperand ShufMask = N->getOperand(2);
2622 unsigned NumElts = ShufMask.getNumOperands()-2;
2624 // If the shuffle mask is an identity operation on the LHS, return the LHS.
2625 bool isIdentity = true;
2626 for (unsigned i = 0; i != NumElts; ++i) {
2627 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2628 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
2633 if (isIdentity) return N->getOperand(0);
2635 // If the shuffle mask is an identity operation on the RHS, return the RHS.
2637 for (unsigned i = 0; i != NumElts; ++i) {
2638 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
2639 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
2644 if (isIdentity) return N->getOperand(1);
2646 // If the LHS and the RHS are the same node, turn the RHS into an undef.
2647 if (N->getOperand(0) == N->getOperand(1)) {
2648 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
2650 std::vector<SDOperand> MappedOps;
2651 for (unsigned i = 0; i != NumElts; ++i) {
2652 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
2653 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
2654 MappedOps.push_back(ShufMask.getOperand(i));
2657 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
2658 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
2661 // Add the type/#elts values.
2662 MappedOps.push_back(ShufMask.getOperand(NumElts));
2663 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
2665 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
2667 AddToWorkList(ShufMask.Val);
2669 // Build the undef vector.
2670 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
2671 for (unsigned i = 0; i != NumElts; ++i)
2672 MappedOps[i] = UDVal;
2673 MappedOps[NumElts ] = *(N->getOperand(0).Val->op_end()-2);
2674 MappedOps[NumElts+1] = *(N->getOperand(0).Val->op_end()-1);
2675 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, MappedOps);
2677 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
2678 N->getOperand(0), UDVal, ShufMask,
2679 MappedOps[NumElts], MappedOps[NumElts+1]);
2685 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
2686 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
2687 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
2688 /// vector_shuffle V, Zero, <0, 4, 2, 4>
2689 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
2690 SDOperand LHS = N->getOperand(0);
2691 SDOperand RHS = N->getOperand(1);
2692 if (N->getOpcode() == ISD::VAND) {
2693 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
2694 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
2695 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
2696 RHS = RHS.getOperand(0);
2697 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
2698 std::vector<SDOperand> IdxOps;
2699 unsigned NumOps = RHS.getNumOperands();
2700 unsigned NumElts = NumOps-2;
2701 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
2702 for (unsigned i = 0; i != NumElts; ++i) {
2703 SDOperand Elt = RHS.getOperand(i);
2704 if (!isa<ConstantSDNode>(Elt))
2706 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
2707 IdxOps.push_back(DAG.getConstant(i, EVT));
2708 else if (cast<ConstantSDNode>(Elt)->isNullValue())
2709 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
2714 // Let's see if the target supports this vector_shuffle.
2715 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
2718 // Return the new VVECTOR_SHUFFLE node.
2719 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
2720 SDOperand EVTNode = DAG.getValueType(EVT);
2721 std::vector<SDOperand> Ops;
2722 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, EVTNode);
2724 AddToWorkList(LHS.Val);
2725 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
2726 ZeroOps.push_back(NumEltsNode);
2727 ZeroOps.push_back(EVTNode);
2728 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, ZeroOps));
2729 IdxOps.push_back(NumEltsNode);
2730 IdxOps.push_back(EVTNode);
2731 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, IdxOps));
2732 Ops.push_back(NumEltsNode);
2733 Ops.push_back(EVTNode);
2734 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops);
2735 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
2736 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
2737 DstVecSize, DstVecEVT);
2745 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
2746 /// the scalar operation of the vop if it is operating on an integer vector
2747 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
2748 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
2749 ISD::NodeType FPOp) {
2750 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
2751 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
2752 SDOperand LHS = N->getOperand(0);
2753 SDOperand RHS = N->getOperand(1);
2754 SDOperand Shuffle = XformToShuffleWithZero(N);
2755 if (Shuffle.Val) return Shuffle;
2757 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
2759 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
2760 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
2761 std::vector<SDOperand> Ops;
2762 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
2763 SDOperand LHSOp = LHS.getOperand(i);
2764 SDOperand RHSOp = RHS.getOperand(i);
2765 // If these two elements can't be folded, bail out.
2766 if ((LHSOp.getOpcode() != ISD::UNDEF &&
2767 LHSOp.getOpcode() != ISD::Constant &&
2768 LHSOp.getOpcode() != ISD::ConstantFP) ||
2769 (RHSOp.getOpcode() != ISD::UNDEF &&
2770 RHSOp.getOpcode() != ISD::Constant &&
2771 RHSOp.getOpcode() != ISD::ConstantFP))
2773 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
2774 AddToWorkList(Ops.back().Val);
2775 assert((Ops.back().getOpcode() == ISD::UNDEF ||
2776 Ops.back().getOpcode() == ISD::Constant ||
2777 Ops.back().getOpcode() == ISD::ConstantFP) &&
2778 "Scalar binop didn't fold!");
2781 if (Ops.size() == LHS.getNumOperands()-2) {
2782 Ops.push_back(*(LHS.Val->op_end()-2));
2783 Ops.push_back(*(LHS.Val->op_end()-1));
2784 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
2791 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
2792 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
2794 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
2795 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2796 // If we got a simplified select_cc node back from SimplifySelectCC, then
2797 // break it down into a new SETCC node, and a new SELECT node, and then return
2798 // the SELECT node, since we were called with a SELECT node.
2800 // Check to see if we got a select_cc back (to turn into setcc/select).
2801 // Otherwise, just return whatever node we got back, like fabs.
2802 if (SCC.getOpcode() == ISD::SELECT_CC) {
2803 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
2804 SCC.getOperand(0), SCC.getOperand(1),
2806 AddToWorkList(SETCC.Val);
2807 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
2808 SCC.getOperand(3), SETCC);
2815 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
2816 /// are the two values being selected between, see if we can simplify the
2819 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
2822 // If this is a select from two identical things, try to pull the operation
2823 // through the select.
2824 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
2826 std::cerr << "SELECT: ["; LHS.Val->dump();
2827 std::cerr << "] ["; RHS.Val->dump();
2831 // If this is a load and the token chain is identical, replace the select
2832 // of two loads with a load through a select of the address to load from.
2833 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
2834 // constants have been dropped into the constant pool.
2835 if ((LHS.getOpcode() == ISD::LOAD ||
2836 LHS.getOpcode() == ISD::EXTLOAD ||
2837 LHS.getOpcode() == ISD::ZEXTLOAD ||
2838 LHS.getOpcode() == ISD::SEXTLOAD) &&
2839 // Token chains must be identical.
2840 LHS.getOperand(0) == RHS.getOperand(0) &&
2841 // If this is an EXTLOAD, the VT's must match.
2842 (LHS.getOpcode() == ISD::LOAD ||
2843 LHS.getOperand(3) == RHS.getOperand(3))) {
2844 // FIXME: this conflates two src values, discarding one. This is not
2845 // the right thing to do, but nothing uses srcvalues now. When they do,
2846 // turn SrcValue into a list of locations.
2848 if (TheSelect->getOpcode() == ISD::SELECT)
2849 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
2850 TheSelect->getOperand(0), LHS.getOperand(1),
2853 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
2854 TheSelect->getOperand(0),
2855 TheSelect->getOperand(1),
2856 LHS.getOperand(1), RHS.getOperand(1),
2857 TheSelect->getOperand(4));
2860 if (LHS.getOpcode() == ISD::LOAD)
2861 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
2862 Addr, LHS.getOperand(2));
2864 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
2865 LHS.getOperand(0), Addr, LHS.getOperand(2),
2866 cast<VTSDNode>(LHS.getOperand(3))->getVT());
2867 // Users of the select now use the result of the load.
2868 CombineTo(TheSelect, Load);
2870 // Users of the old loads now use the new load's chain. We know the
2871 // old-load value is dead now.
2872 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
2873 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
2881 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
2882 SDOperand N2, SDOperand N3,
2885 MVT::ValueType VT = N2.getValueType();
2886 //ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
2887 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
2888 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
2889 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
2891 // Determine if the condition we're dealing with is constant
2892 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2893 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2895 // fold select_cc true, x, y -> x
2896 if (SCCC && SCCC->getValue())
2898 // fold select_cc false, x, y -> y
2899 if (SCCC && SCCC->getValue() == 0)
2902 // Check to see if we can simplify the select into an fabs node
2903 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
2904 // Allow either -0.0 or 0.0
2905 if (CFP->getValue() == 0.0) {
2906 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
2907 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
2908 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
2909 N2 == N3.getOperand(0))
2910 return DAG.getNode(ISD::FABS, VT, N0);
2912 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
2913 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
2914 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
2915 N2.getOperand(0) == N3)
2916 return DAG.getNode(ISD::FABS, VT, N3);
2920 // Check to see if we can perform the "gzip trick", transforming
2921 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
2922 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
2923 MVT::isInteger(N0.getValueType()) &&
2924 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
2925 MVT::ValueType XType = N0.getValueType();
2926 MVT::ValueType AType = N2.getValueType();
2927 if (XType >= AType) {
2928 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
2929 // single-bit constant.
2930 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
2931 unsigned ShCtV = Log2_64(N2C->getValue());
2932 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
2933 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
2934 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
2935 AddToWorkList(Shift.Val);
2936 if (XType > AType) {
2937 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2938 AddToWorkList(Shift.Val);
2940 return DAG.getNode(ISD::AND, AType, Shift, N2);
2942 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2943 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2944 TLI.getShiftAmountTy()));
2945 AddToWorkList(Shift.Val);
2946 if (XType > AType) {
2947 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2948 AddToWorkList(Shift.Val);
2950 return DAG.getNode(ISD::AND, AType, Shift, N2);
2954 // fold select C, 16, 0 -> shl C, 4
2955 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
2956 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
2957 // Get a SetCC of the condition
2958 // FIXME: Should probably make sure that setcc is legal if we ever have a
2959 // target where it isn't.
2960 SDOperand Temp, SCC;
2961 // cast from setcc result type to select result type
2962 if (AfterLegalize) {
2963 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2964 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
2966 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
2967 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
2969 AddToWorkList(SCC.Val);
2970 AddToWorkList(Temp.Val);
2971 // shl setcc result by log2 n2c
2972 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
2973 DAG.getConstant(Log2_64(N2C->getValue()),
2974 TLI.getShiftAmountTy()));
2977 // Check to see if this is the equivalent of setcc
2978 // FIXME: Turn all of these into setcc if setcc if setcc is legal
2979 // otherwise, go ahead with the folds.
2980 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
2981 MVT::ValueType XType = N0.getValueType();
2982 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
2983 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2984 if (Res.getValueType() != VT)
2985 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
2989 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
2990 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
2991 TLI.isOperationLegal(ISD::CTLZ, XType)) {
2992 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
2993 return DAG.getNode(ISD::SRL, XType, Ctlz,
2994 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
2995 TLI.getShiftAmountTy()));
2997 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
2998 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
2999 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3001 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3002 DAG.getConstant(~0ULL, XType));
3003 return DAG.getNode(ISD::SRL, XType,
3004 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3005 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3006 TLI.getShiftAmountTy()));
3008 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3009 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3010 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3011 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3012 TLI.getShiftAmountTy()));
3013 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3017 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3018 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3019 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3020 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3021 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3022 MVT::ValueType XType = N0.getValueType();
3023 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3024 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3025 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3026 TLI.getShiftAmountTy()));
3027 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3028 AddToWorkList(Shift.Val);
3029 AddToWorkList(Add.Val);
3030 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3038 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3039 SDOperand N1, ISD::CondCode Cond,
3040 bool foldBooleans) {
3041 // These setcc operations always fold.
3045 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3047 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3050 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3051 uint64_t C1 = N1C->getValue();
3052 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
3053 uint64_t C0 = N0C->getValue();
3055 // Sign extend the operands if required
3056 if (ISD::isSignedIntSetCC(Cond)) {
3057 C0 = N0C->getSignExtended();
3058 C1 = N1C->getSignExtended();
3062 default: assert(0 && "Unknown integer setcc!");
3063 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3064 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3065 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
3066 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
3067 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
3068 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
3069 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
3070 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
3071 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
3072 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
3075 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3076 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3077 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3079 // If the comparison constant has bits in the upper part, the
3080 // zero-extended value could never match.
3081 if (C1 & (~0ULL << InSize)) {
3082 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3086 case ISD::SETEQ: return DAG.getConstant(0, VT);
3089 case ISD::SETNE: return DAG.getConstant(1, VT);
3092 // True if the sign bit of C1 is set.
3093 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3096 // True if the sign bit of C1 isn't set.
3097 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3103 // Otherwise, we can perform the comparison with the low bits.
3111 return DAG.getSetCC(VT, N0.getOperand(0),
3112 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3115 break; // todo, be more careful with signed comparisons
3117 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3118 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3119 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3120 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3121 MVT::ValueType ExtDstTy = N0.getValueType();
3122 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3124 // If the extended part has any inconsistent bits, it cannot ever
3125 // compare equal. In other words, they have to be all ones or all
3128 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3129 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3130 return DAG.getConstant(Cond == ISD::SETNE, VT);
3133 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3134 if (Op0Ty == ExtSrcTy) {
3135 ZextOp = N0.getOperand(0);
3137 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3138 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3139 DAG.getConstant(Imm, Op0Ty));
3141 AddToWorkList(ZextOp.Val);
3142 // Otherwise, make this a use of a zext.
3143 return DAG.getSetCC(VT, ZextOp,
3144 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3147 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3148 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3149 (N0.getOpcode() == ISD::XOR ||
3150 (N0.getOpcode() == ISD::AND &&
3151 N0.getOperand(0).getOpcode() == ISD::XOR &&
3152 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
3153 isa<ConstantSDNode>(N0.getOperand(1)) &&
3154 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
3155 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
3156 // only do this if the top bits are known zero.
3157 if (TLI.MaskedValueIsZero(N1,
3158 MVT::getIntVTBitMask(N0.getValueType())-1)) {
3159 // Okay, get the un-inverted input value.
3161 if (N0.getOpcode() == ISD::XOR)
3162 Val = N0.getOperand(0);
3164 assert(N0.getOpcode() == ISD::AND &&
3165 N0.getOperand(0).getOpcode() == ISD::XOR);
3166 // ((X^1)&1)^1 -> X & 1
3167 Val = DAG.getNode(ISD::AND, N0.getValueType(),
3168 N0.getOperand(0).getOperand(0), N0.getOperand(1));
3170 return DAG.getSetCC(VT, Val, N1,
3171 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
3175 uint64_t MinVal, MaxVal;
3176 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
3177 if (ISD::isSignedIntSetCC(Cond)) {
3178 MinVal = 1ULL << (OperandBitSize-1);
3179 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
3180 MaxVal = ~0ULL >> (65-OperandBitSize);
3185 MaxVal = ~0ULL >> (64-OperandBitSize);
3188 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
3189 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
3190 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
3191 --C1; // X >= C0 --> X > (C0-1)
3192 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3193 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
3196 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
3197 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
3198 ++C1; // X <= C0 --> X < (C0+1)
3199 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
3200 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
3203 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
3204 return DAG.getConstant(0, VT); // X < MIN --> false
3206 // Canonicalize setgt X, Min --> setne X, Min
3207 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
3208 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3209 // Canonicalize setlt X, Max --> setne X, Max
3210 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
3211 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
3213 // If we have setult X, 1, turn it into seteq X, 0
3214 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
3215 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
3217 // If we have setugt X, Max-1, turn it into seteq X, Max
3218 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
3219 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
3222 // If we have "setcc X, C0", check to see if we can shrink the immediate
3225 // SETUGT X, SINTMAX -> SETLT X, 0
3226 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
3227 C1 == (~0ULL >> (65-OperandBitSize)))
3228 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
3231 // FIXME: Implement the rest of these.
3233 // Fold bit comparisons when we can.
3234 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3235 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
3236 if (ConstantSDNode *AndRHS =
3237 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3238 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
3239 // Perform the xform if the AND RHS is a single bit.
3240 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
3241 return DAG.getNode(ISD::SRL, VT, N0,
3242 DAG.getConstant(Log2_64(AndRHS->getValue()),
3243 TLI.getShiftAmountTy()));
3245 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
3246 // (X & 8) == 8 --> (X & 8) >> 3
3247 // Perform the xform if C1 is a single bit.
3248 if ((C1 & (C1-1)) == 0) {
3249 return DAG.getNode(ISD::SRL, VT, N0,
3250 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
3255 } else if (isa<ConstantSDNode>(N0.Val)) {
3256 // Ensure that the constant occurs on the RHS.
3257 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3260 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
3261 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
3262 double C0 = N0C->getValue(), C1 = N1C->getValue();
3265 default: break; // FIXME: Implement the rest of these!
3266 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
3267 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
3268 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
3269 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
3270 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
3271 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
3274 // Ensure that the constant occurs on the RHS.
3275 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
3279 // We can always fold X == Y for integer setcc's.
3280 if (MVT::isInteger(N0.getValueType()))
3281 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3282 unsigned UOF = ISD::getUnorderedFlavor(Cond);
3283 if (UOF == 2) // FP operators that are undefined on NaNs.
3284 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
3285 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
3286 return DAG.getConstant(UOF, VT);
3287 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
3288 // if it is not already.
3289 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
3290 if (NewCond != Cond)
3291 return DAG.getSetCC(VT, N0, N1, NewCond);
3294 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3295 MVT::isInteger(N0.getValueType())) {
3296 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
3297 N0.getOpcode() == ISD::XOR) {
3298 // Simplify (X+Y) == (X+Z) --> Y == Z
3299 if (N0.getOpcode() == N1.getOpcode()) {
3300 if (N0.getOperand(0) == N1.getOperand(0))
3301 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
3302 if (N0.getOperand(1) == N1.getOperand(1))
3303 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
3304 if (isCommutativeBinOp(N0.getOpcode())) {
3305 // If X op Y == Y op X, try other combinations.
3306 if (N0.getOperand(0) == N1.getOperand(1))
3307 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
3308 if (N0.getOperand(1) == N1.getOperand(0))
3309 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
3313 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
3314 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3315 // Turn (X+C1) == C2 --> X == C2-C1
3316 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
3317 return DAG.getSetCC(VT, N0.getOperand(0),
3318 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
3319 N0.getValueType()), Cond);
3322 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
3323 if (N0.getOpcode() == ISD::XOR)
3324 // If we know that all of the inverted bits are zero, don't bother
3325 // performing the inversion.
3326 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
3327 return DAG.getSetCC(VT, N0.getOperand(0),
3328 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
3329 N0.getValueType()), Cond);
3332 // Turn (C1-X) == C2 --> X == C1-C2
3333 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
3334 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
3335 return DAG.getSetCC(VT, N0.getOperand(1),
3336 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
3337 N0.getValueType()), Cond);
3342 // Simplify (X+Z) == X --> Z == 0
3343 if (N0.getOperand(0) == N1)
3344 return DAG.getSetCC(VT, N0.getOperand(1),
3345 DAG.getConstant(0, N0.getValueType()), Cond);
3346 if (N0.getOperand(1) == N1) {
3347 if (isCommutativeBinOp(N0.getOpcode()))
3348 return DAG.getSetCC(VT, N0.getOperand(0),
3349 DAG.getConstant(0, N0.getValueType()), Cond);
3351 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
3352 // (Z-X) == X --> Z == X<<1
3353 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
3355 DAG.getConstant(1,TLI.getShiftAmountTy()));
3356 AddToWorkList(SH.Val);
3357 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
3362 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
3363 N1.getOpcode() == ISD::XOR) {
3364 // Simplify X == (X+Z) --> Z == 0
3365 if (N1.getOperand(0) == N0) {
3366 return DAG.getSetCC(VT, N1.getOperand(1),
3367 DAG.getConstant(0, N1.getValueType()), Cond);
3368 } else if (N1.getOperand(1) == N0) {
3369 if (isCommutativeBinOp(N1.getOpcode())) {
3370 return DAG.getSetCC(VT, N1.getOperand(0),
3371 DAG.getConstant(0, N1.getValueType()), Cond);
3373 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
3374 // X == (Z-X) --> X<<1 == Z
3375 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
3376 DAG.getConstant(1,TLI.getShiftAmountTy()));
3377 AddToWorkList(SH.Val);
3378 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
3384 // Fold away ALL boolean setcc's.
3386 if (N0.getValueType() == MVT::i1 && foldBooleans) {
3388 default: assert(0 && "Unknown integer setcc!");
3389 case ISD::SETEQ: // X == Y -> (X^Y)^1
3390 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3391 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
3392 AddToWorkList(Temp.Val);
3394 case ISD::SETNE: // X != Y --> (X^Y)
3395 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
3397 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
3398 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
3399 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3400 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
3401 AddToWorkList(Temp.Val);
3403 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
3404 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
3405 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3406 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
3407 AddToWorkList(Temp.Val);
3409 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
3410 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
3411 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
3412 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
3413 AddToWorkList(Temp.Val);
3415 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
3416 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
3417 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
3418 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
3421 if (VT != MVT::i1) {
3422 AddToWorkList(N0.Val);
3423 // FIXME: If running after legalize, we probably can't do this.
3424 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
3429 // Could not fold it.
3433 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
3434 /// return a DAG expression to select that will generate the same value by
3435 /// multiplying by a magic number. See:
3436 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3437 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
3438 std::list<SDNode*> Built;
3439 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
3441 for (std::list<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3447 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
3448 /// return a DAG expression to select that will generate the same value by
3449 /// multiplying by a magic number. See:
3450 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
3451 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
3452 std::list<SDNode*> Built;
3453 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
3455 for (std::list<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
3461 // SelectionDAG::Combine - This is the entry point for the file.
3463 void SelectionDAG::Combine(bool RunningAfterLegalize) {
3464 /// run - This is the main entry point to this class.
3466 DAGCombiner(*this).Run(RunningAfterLegalize);