1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetFrameInfo.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/ADT/SmallPtrSet.h"
33 #include "llvm/ADT/Statistic.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
42 STATISTIC(NodesCombined , "Number of dag nodes combined");
43 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
44 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
45 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
67 std::vector<SDNode*> WorkList;
69 // AA - Used for DAG load/store alias analysis.
72 /// AddUsersToWorkList - When an instruction is simplified, add all users of
73 /// the instruction to the work lists because they might get more simplified
76 void AddUsersToWorkList(SDNode *N) {
77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
82 /// visit - call the node-specific routine that knows how to fold each
83 /// particular type of node.
84 SDValue visit(SDNode *N);
87 /// AddToWorkList - Add to the work list making sure it's instance is at the
88 /// the back (next to be processed.)
89 void AddToWorkList(SDNode *N) {
90 removeFromWorkList(N);
91 WorkList.push_back(N);
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
105 return CombineTo(N, &Res, 1, AddTo);
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
110 SDValue To[] = { Res0, Res1 };
111 return CombineTo(N, To, 2, AddTo);
114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
118 /// SimplifyDemandedBits - Check the specified integer node value to see if
119 /// it can be simplified or if things it uses can be simplified by bit
120 /// propagation. If so, return true.
121 bool SimplifyDemandedBits(SDValue Op) {
122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
123 APInt Demanded = APInt::getAllOnesValue(BitWidth);
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
132 SDValue PromoteIntBinOp(SDValue Op);
134 /// combine - call the node-specific routine that knows how to fold each
135 /// particular type of node. If that doesn't do anything, try the
136 /// target-specific DAG combines.
137 SDValue combine(SDNode *N);
139 // Visitation implementation - Implement dag node combining for different
140 // node types. The semantics are as follows:
142 // SDValue.getNode() == 0 - No change was made
143 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
144 // otherwise - N should be replaced by the returned Operand.
146 SDValue visitTokenFactor(SDNode *N);
147 SDValue visitMERGE_VALUES(SDNode *N);
148 SDValue visitADD(SDNode *N);
149 SDValue visitSUB(SDNode *N);
150 SDValue visitADDC(SDNode *N);
151 SDValue visitADDE(SDNode *N);
152 SDValue visitMUL(SDNode *N);
153 SDValue visitSDIV(SDNode *N);
154 SDValue visitUDIV(SDNode *N);
155 SDValue visitSREM(SDNode *N);
156 SDValue visitUREM(SDNode *N);
157 SDValue visitMULHU(SDNode *N);
158 SDValue visitMULHS(SDNode *N);
159 SDValue visitSMUL_LOHI(SDNode *N);
160 SDValue visitUMUL_LOHI(SDNode *N);
161 SDValue visitSDIVREM(SDNode *N);
162 SDValue visitUDIVREM(SDNode *N);
163 SDValue visitAND(SDNode *N);
164 SDValue visitOR(SDNode *N);
165 SDValue visitXOR(SDNode *N);
166 SDValue SimplifyVBinOp(SDNode *N);
167 SDValue visitSHL(SDNode *N);
168 SDValue visitSRA(SDNode *N);
169 SDValue visitSRL(SDNode *N);
170 SDValue visitCTLZ(SDNode *N);
171 SDValue visitCTTZ(SDNode *N);
172 SDValue visitCTPOP(SDNode *N);
173 SDValue visitSELECT(SDNode *N);
174 SDValue visitSELECT_CC(SDNode *N);
175 SDValue visitSETCC(SDNode *N);
176 SDValue visitSIGN_EXTEND(SDNode *N);
177 SDValue visitZERO_EXTEND(SDNode *N);
178 SDValue visitANY_EXTEND(SDNode *N);
179 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
180 SDValue visitTRUNCATE(SDNode *N);
181 SDValue visitBIT_CONVERT(SDNode *N);
182 SDValue visitBUILD_PAIR(SDNode *N);
183 SDValue visitFADD(SDNode *N);
184 SDValue visitFSUB(SDNode *N);
185 SDValue visitFMUL(SDNode *N);
186 SDValue visitFDIV(SDNode *N);
187 SDValue visitFREM(SDNode *N);
188 SDValue visitFCOPYSIGN(SDNode *N);
189 SDValue visitSINT_TO_FP(SDNode *N);
190 SDValue visitUINT_TO_FP(SDNode *N);
191 SDValue visitFP_TO_SINT(SDNode *N);
192 SDValue visitFP_TO_UINT(SDNode *N);
193 SDValue visitFP_ROUND(SDNode *N);
194 SDValue visitFP_ROUND_INREG(SDNode *N);
195 SDValue visitFP_EXTEND(SDNode *N);
196 SDValue visitFNEG(SDNode *N);
197 SDValue visitFABS(SDNode *N);
198 SDValue visitBRCOND(SDNode *N);
199 SDValue visitBR_CC(SDNode *N);
200 SDValue visitLOAD(SDNode *N);
201 SDValue visitSTORE(SDNode *N);
202 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
203 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
204 SDValue visitBUILD_VECTOR(SDNode *N);
205 SDValue visitCONCAT_VECTORS(SDNode *N);
206 SDValue visitVECTOR_SHUFFLE(SDNode *N);
208 SDValue XformToShuffleWithZero(SDNode *N);
209 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
211 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
213 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
214 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
215 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
216 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
217 SDValue N3, ISD::CondCode CC,
218 bool NotExtCompare = false);
219 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
220 DebugLoc DL, bool foldBooleans = true);
221 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
223 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
224 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT);
225 SDValue BuildSDIV(SDNode *N);
226 SDValue BuildUDIV(SDNode *N);
227 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
228 SDValue ReduceLoadWidth(SDNode *N);
229 SDValue ReduceLoadOpStoreWidth(SDNode *N);
231 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
233 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
234 /// looking for aliasing nodes and adding them to the Aliases vector.
235 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
236 SmallVector<SDValue, 8> &Aliases);
238 /// isAlias - Return true if there is any possibility that the two addresses
240 bool isAlias(SDValue Ptr1, int64_t Size1,
241 const Value *SrcValue1, int SrcValueOffset1,
242 unsigned SrcValueAlign1,
243 SDValue Ptr2, int64_t Size2,
244 const Value *SrcValue2, int SrcValueOffset2,
245 unsigned SrcValueAlign2) const;
247 /// FindAliasInfo - Extracts the relevant alias information from the memory
248 /// node. Returns true if the operand was a load.
249 bool FindAliasInfo(SDNode *N,
250 SDValue &Ptr, int64_t &Size,
251 const Value *&SrcValue, int &SrcValueOffset,
252 unsigned &SrcValueAlignment) const;
254 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
255 /// looking for a better chain (aliasing node.)
256 SDValue FindBetterChain(SDNode *N, SDValue Chain);
259 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
260 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted),
261 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
263 /// Run - runs the dag combiner on all nodes in the work list
264 void Run(CombineLevel AtLevel);
266 SelectionDAG &getDAG() const { return DAG; }
268 /// getShiftAmountTy - Returns a type large enough to hold any valid
269 /// shift amount - before type legalization these can be huge.
270 EVT getShiftAmountTy() {
271 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
274 /// isTypeLegal - This method returns true if we are running before type
275 /// legalization or if the specified VT is legal.
276 bool isTypeLegal(const EVT &VT) {
277 if (!LegalTypes) return true;
278 return TLI.isTypeLegal(VT);
285 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
286 /// nodes from the worklist.
287 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
290 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
292 virtual void NodeDeleted(SDNode *N, SDNode *E) {
293 DC.removeFromWorkList(N);
296 virtual void NodeUpdated(SDNode *N) {
302 //===----------------------------------------------------------------------===//
303 // TargetLowering::DAGCombinerInfo implementation
304 //===----------------------------------------------------------------------===//
306 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
307 ((DAGCombiner*)DC)->AddToWorkList(N);
310 SDValue TargetLowering::DAGCombinerInfo::
311 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
312 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
315 SDValue TargetLowering::DAGCombinerInfo::
316 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
317 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
321 SDValue TargetLowering::DAGCombinerInfo::
322 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
323 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
326 void TargetLowering::DAGCombinerInfo::
327 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
328 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
331 //===----------------------------------------------------------------------===//
333 //===----------------------------------------------------------------------===//
335 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
336 /// specified expression for the same cost as the expression itself, or 2 if we
337 /// can compute the negated form more cheaply than the expression itself.
338 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
339 unsigned Depth = 0) {
340 // No compile time optimizations on this type.
341 if (Op.getValueType() == MVT::ppcf128)
344 // fneg is removable even if it has multiple uses.
345 if (Op.getOpcode() == ISD::FNEG) return 2;
347 // Don't allow anything with multiple uses.
348 if (!Op.hasOneUse()) return 0;
350 // Don't recurse exponentially.
351 if (Depth > 6) return 0;
353 switch (Op.getOpcode()) {
354 default: return false;
355 case ISD::ConstantFP:
356 // Don't invert constant FP values after legalize. The negated constant
357 // isn't necessarily legal.
358 return LegalOperations ? 0 : 1;
360 // FIXME: determine better conditions for this xform.
361 if (!UnsafeFPMath) return 0;
363 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
364 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
366 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
367 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
369 // We can't turn -(A-B) into B-A when we honor signed zeros.
370 if (!UnsafeFPMath) return 0;
372 // fold (fneg (fsub A, B)) -> (fsub B, A)
377 if (HonorSignDependentRoundingFPMath()) return 0;
379 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
380 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
383 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
388 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
392 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
393 /// returns the newly negated expression.
394 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
395 bool LegalOperations, unsigned Depth = 0) {
396 // fneg is removable even if it has multiple uses.
397 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
399 // Don't allow anything with multiple uses.
400 assert(Op.hasOneUse() && "Unknown reuse!");
402 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
403 switch (Op.getOpcode()) {
404 default: llvm_unreachable("Unknown code");
405 case ISD::ConstantFP: {
406 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
408 return DAG.getConstantFP(V, Op.getValueType());
411 // FIXME: determine better conditions for this xform.
412 assert(UnsafeFPMath);
414 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
415 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
416 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
417 GetNegatedExpression(Op.getOperand(0), DAG,
418 LegalOperations, Depth+1),
420 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
421 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
422 GetNegatedExpression(Op.getOperand(1), DAG,
423 LegalOperations, Depth+1),
426 // We can't turn -(A-B) into B-A when we honor signed zeros.
427 assert(UnsafeFPMath);
429 // fold (fneg (fsub 0, B)) -> B
430 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
431 if (N0CFP->getValueAPF().isZero())
432 return Op.getOperand(1);
434 // fold (fneg (fsub A, B)) -> (fsub B, A)
435 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
436 Op.getOperand(1), Op.getOperand(0));
440 assert(!HonorSignDependentRoundingFPMath());
442 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
443 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
444 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
445 GetNegatedExpression(Op.getOperand(0), DAG,
446 LegalOperations, Depth+1),
449 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
450 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
452 GetNegatedExpression(Op.getOperand(1), DAG,
453 LegalOperations, Depth+1));
457 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
458 GetNegatedExpression(Op.getOperand(0), DAG,
459 LegalOperations, Depth+1));
461 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
462 GetNegatedExpression(Op.getOperand(0), DAG,
463 LegalOperations, Depth+1),
469 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
470 // that selects between the values 1 and 0, making it equivalent to a setcc.
471 // Also, set the incoming LHS, RHS, and CC references to the appropriate
472 // nodes based on the type of node we are checking. This simplifies life a
473 // bit for the callers.
474 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
476 if (N.getOpcode() == ISD::SETCC) {
477 LHS = N.getOperand(0);
478 RHS = N.getOperand(1);
479 CC = N.getOperand(2);
482 if (N.getOpcode() == ISD::SELECT_CC &&
483 N.getOperand(2).getOpcode() == ISD::Constant &&
484 N.getOperand(3).getOpcode() == ISD::Constant &&
485 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
486 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
487 LHS = N.getOperand(0);
488 RHS = N.getOperand(1);
489 CC = N.getOperand(4);
495 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
496 // one use. If this is true, it allows the users to invert the operation for
497 // free when it is profitable to do so.
498 static bool isOneUseSetCC(SDValue N) {
500 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
505 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
506 SDValue N0, SDValue N1) {
507 EVT VT = N0.getValueType();
508 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
509 if (isa<ConstantSDNode>(N1)) {
510 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
512 DAG.FoldConstantArithmetic(Opc, VT,
513 cast<ConstantSDNode>(N0.getOperand(1)),
514 cast<ConstantSDNode>(N1));
515 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
516 } else if (N0.hasOneUse()) {
517 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
518 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
519 N0.getOperand(0), N1);
520 AddToWorkList(OpNode.getNode());
521 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
525 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
526 if (isa<ConstantSDNode>(N0)) {
527 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
529 DAG.FoldConstantArithmetic(Opc, VT,
530 cast<ConstantSDNode>(N1.getOperand(1)),
531 cast<ConstantSDNode>(N0));
532 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
533 } else if (N1.hasOneUse()) {
534 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
535 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
536 N1.getOperand(0), N0);
537 AddToWorkList(OpNode.getNode());
538 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
545 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
547 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
549 DEBUG(dbgs() << "\nReplacing.1 ";
551 dbgs() << "\nWith: ";
552 To[0].getNode()->dump(&DAG);
553 dbgs() << " and " << NumTo-1 << " other values\n";
554 for (unsigned i = 0, e = NumTo; i != e; ++i)
555 assert((!To[i].getNode() ||
556 N->getValueType(i) == To[i].getValueType()) &&
557 "Cannot combine value to value of different type!"));
558 WorkListRemover DeadNodes(*this);
559 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
562 // Push the new nodes and any users onto the worklist
563 for (unsigned i = 0, e = NumTo; i != e; ++i) {
564 if (To[i].getNode()) {
565 AddToWorkList(To[i].getNode());
566 AddUsersToWorkList(To[i].getNode());
571 // Finally, if the node is now dead, remove it from the graph. The node
572 // may not be dead if the replacement process recursively simplified to
573 // something else needing this node.
574 if (N->use_empty()) {
575 // Nodes can be reintroduced into the worklist. Make sure we do not
576 // process a node that has been replaced.
577 removeFromWorkList(N);
579 // Finally, since the node is now dead, remove it from the graph.
582 return SDValue(N, 0);
586 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
587 // Replace all uses. If any nodes become isomorphic to other nodes and
588 // are deleted, make sure to remove them from our worklist.
589 WorkListRemover DeadNodes(*this);
590 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
592 // Push the new node and any (possibly new) users onto the worklist.
593 AddToWorkList(TLO.New.getNode());
594 AddUsersToWorkList(TLO.New.getNode());
596 // Finally, if the node is now dead, remove it from the graph. The node
597 // may not be dead if the replacement process recursively simplified to
598 // something else needing this node.
599 if (TLO.Old.getNode()->use_empty()) {
600 removeFromWorkList(TLO.Old.getNode());
602 // If the operands of this node are only used by the node, they will now
603 // be dead. Make sure to visit them first to delete dead nodes early.
604 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
605 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
606 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
608 DAG.DeleteNode(TLO.Old.getNode());
612 /// SimplifyDemandedBits - Check the specified integer node value to see if
613 /// it can be simplified or if things it uses can be simplified by bit
614 /// propagation. If so, return true.
615 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
616 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
617 APInt KnownZero, KnownOne;
618 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
622 AddToWorkList(Op.getNode());
624 // Replace the old value with the new one.
626 DEBUG(dbgs() << "\nReplacing.2 ";
627 TLO.Old.getNode()->dump(&DAG);
628 dbgs() << "\nWith: ";
629 TLO.New.getNode()->dump(&DAG);
632 CommitTargetLoweringOpt(TLO);
636 static SDValue PromoteOperand(SDValue Op, EVT PVT, SelectionDAG &DAG,
637 const TargetLowering &TLI) {
638 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
639 return DAG.getExtLoad(ISD::EXTLOAD, Op.getDebugLoc(), PVT,
640 LD->getChain(), LD->getBasePtr(),
641 LD->getSrcValue(), LD->getSrcValueOffset(),
642 LD->getMemoryVT(), LD->isVolatile(),
643 LD->isNonTemporal(), LD->getAlignment());
646 unsigned Opc = ISD::ANY_EXTEND;
647 if (Op.getOpcode() == ISD::Constant)
648 // Zero extend things like i1, sign extend everything else. It shouldn't
649 // matter in theory which one we pick, but this tends to give better code?
650 // See DAGTypeLegalizer::PromoteIntRes_Constant.
651 Opc = Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
652 if (!TLI.isOperationLegal(Opc, PVT))
654 return DAG.getNode(Opc, Op.getDebugLoc(), PVT, Op);
657 static SDValue SExtPromoteOperand(SDValue Op, EVT PVT, SelectionDAG &DAG,
658 const TargetLowering &TLI) {
659 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
661 EVT OldVT = Op.getValueType();
662 DebugLoc dl = Op.getDebugLoc();
663 Op = PromoteOperand(Op, PVT, DAG, TLI);
664 if (Op.getNode() == 0)
666 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
667 DAG.getValueType(OldVT));
670 static SDValue ZExtPromoteOperand(SDValue Op, EVT PVT, SelectionDAG &DAG,
671 const TargetLowering &TLI) {
672 EVT OldVT = Op.getValueType();
673 DebugLoc dl = Op.getDebugLoc();
674 Op = PromoteOperand(Op, PVT, DAG, TLI);
675 if (Op.getNode() == 0)
677 return DAG.getZeroExtendInReg(Op, dl, OldVT);
680 /// PromoteIntBinOp - Promote the specified integer binary operation if the
681 /// target indicates it is beneficial. e.g. On x86, it's usually better to
682 /// promote i16 operations to i32 since i16 instructions are longer.
683 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
684 if (!LegalOperations)
687 EVT VT = Op.getValueType();
688 if (VT.isVector() || !VT.isInteger())
691 // If operation type is 'undesirable', e.g. i16 on x86, consider
693 unsigned Opc = Op.getOpcode();
694 if (TLI.isTypeDesirableForOp(Opc, VT))
698 // Consult target whether it is a good idea to promote this operation and
699 // what's the right type to promote it to.
700 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
701 assert(PVT != VT && "Don't know what type to promote to!");
703 bool isShift = (Opc == ISD::SHL) || (Opc == ISD::SRA) || (Opc == ISD::SRL);
704 SDValue N0 = Op.getOperand(0);
706 N0 = SExtPromoteOperand(Op.getOperand(0), PVT, DAG, TLI);
707 else if (Opc == ISD::SRL)
708 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT, DAG, TLI);
710 N0 = PromoteOperand(N0, PVT, DAG, TLI);
711 if (N0.getNode() == 0)
714 SDValue N1 = Op.getOperand(1);
716 N1 = PromoteOperand(N1, PVT, DAG, TLI);
717 if (N1.getNode() == 0)
719 AddToWorkList(N1.getNode());
721 AddToWorkList(N0.getNode());
723 DebugLoc dl = Op.getDebugLoc();
724 return DAG.getNode(ISD::TRUNCATE, dl, VT,
725 DAG.getNode(Op.getOpcode(), dl, PVT, N0, N1));
731 //===----------------------------------------------------------------------===//
732 // Main DAG Combiner implementation
733 //===----------------------------------------------------------------------===//
735 void DAGCombiner::Run(CombineLevel AtLevel) {
736 // set the instance variables, so that the various visit routines may use it.
738 LegalOperations = Level >= NoIllegalOperations;
739 LegalTypes = Level >= NoIllegalTypes;
741 // Add all the dag nodes to the worklist.
742 WorkList.reserve(DAG.allnodes_size());
743 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
744 E = DAG.allnodes_end(); I != E; ++I)
745 WorkList.push_back(I);
747 // Create a dummy node (which is not added to allnodes), that adds a reference
748 // to the root node, preventing it from being deleted, and tracking any
749 // changes of the root.
750 HandleSDNode Dummy(DAG.getRoot());
752 // The root of the dag may dangle to deleted nodes until the dag combiner is
753 // done. Set it to null to avoid confusion.
754 DAG.setRoot(SDValue());
756 // while the worklist isn't empty, inspect the node on the end of it and
757 // try and combine it.
758 while (!WorkList.empty()) {
759 SDNode *N = WorkList.back();
762 // If N has no uses, it is dead. Make sure to revisit all N's operands once
763 // N is deleted from the DAG, since they too may now be dead or may have a
764 // reduced number of uses, allowing other xforms.
765 if (N->use_empty() && N != &Dummy) {
766 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
767 AddToWorkList(N->getOperand(i).getNode());
773 SDValue RV = combine(N);
775 if (RV.getNode() == 0)
780 // If we get back the same node we passed in, rather than a new node or
781 // zero, we know that the node must have defined multiple values and
782 // CombineTo was used. Since CombineTo takes care of the worklist
783 // mechanics for us, we have no work to do in this case.
784 if (RV.getNode() == N)
787 assert(N->getOpcode() != ISD::DELETED_NODE &&
788 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
789 "Node was deleted but visit returned new node!");
791 DEBUG(dbgs() << "\nReplacing.3 ";
793 dbgs() << "\nWith: ";
794 RV.getNode()->dump(&DAG);
796 WorkListRemover DeadNodes(*this);
797 if (N->getNumValues() == RV.getNode()->getNumValues())
798 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
800 assert(N->getValueType(0) == RV.getValueType() &&
801 N->getNumValues() == 1 && "Type mismatch");
803 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
806 // Push the new node and any users onto the worklist
807 AddToWorkList(RV.getNode());
808 AddUsersToWorkList(RV.getNode());
810 // Add any uses of the old node to the worklist in case this node is the
811 // last one that uses them. They may become dead after this node is
813 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
814 AddToWorkList(N->getOperand(i).getNode());
816 // Finally, if the node is now dead, remove it from the graph. The node
817 // may not be dead if the replacement process recursively simplified to
818 // something else needing this node.
819 if (N->use_empty()) {
820 // Nodes can be reintroduced into the worklist. Make sure we do not
821 // process a node that has been replaced.
822 removeFromWorkList(N);
824 // Finally, since the node is now dead, remove it from the graph.
829 // If the root changed (e.g. it was a dead load, update the root).
830 DAG.setRoot(Dummy.getValue());
833 SDValue DAGCombiner::visit(SDNode *N) {
834 switch(N->getOpcode()) {
836 case ISD::TokenFactor: return visitTokenFactor(N);
837 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
838 case ISD::ADD: return visitADD(N);
839 case ISD::SUB: return visitSUB(N);
840 case ISD::ADDC: return visitADDC(N);
841 case ISD::ADDE: return visitADDE(N);
842 case ISD::MUL: return visitMUL(N);
843 case ISD::SDIV: return visitSDIV(N);
844 case ISD::UDIV: return visitUDIV(N);
845 case ISD::SREM: return visitSREM(N);
846 case ISD::UREM: return visitUREM(N);
847 case ISD::MULHU: return visitMULHU(N);
848 case ISD::MULHS: return visitMULHS(N);
849 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
850 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
851 case ISD::SDIVREM: return visitSDIVREM(N);
852 case ISD::UDIVREM: return visitUDIVREM(N);
853 case ISD::AND: return visitAND(N);
854 case ISD::OR: return visitOR(N);
855 case ISD::XOR: return visitXOR(N);
856 case ISD::SHL: return visitSHL(N);
857 case ISD::SRA: return visitSRA(N);
858 case ISD::SRL: return visitSRL(N);
859 case ISD::CTLZ: return visitCTLZ(N);
860 case ISD::CTTZ: return visitCTTZ(N);
861 case ISD::CTPOP: return visitCTPOP(N);
862 case ISD::SELECT: return visitSELECT(N);
863 case ISD::SELECT_CC: return visitSELECT_CC(N);
864 case ISD::SETCC: return visitSETCC(N);
865 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
866 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
867 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
868 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
869 case ISD::TRUNCATE: return visitTRUNCATE(N);
870 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
871 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
872 case ISD::FADD: return visitFADD(N);
873 case ISD::FSUB: return visitFSUB(N);
874 case ISD::FMUL: return visitFMUL(N);
875 case ISD::FDIV: return visitFDIV(N);
876 case ISD::FREM: return visitFREM(N);
877 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
878 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
879 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
880 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
881 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
882 case ISD::FP_ROUND: return visitFP_ROUND(N);
883 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
884 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
885 case ISD::FNEG: return visitFNEG(N);
886 case ISD::FABS: return visitFABS(N);
887 case ISD::BRCOND: return visitBRCOND(N);
888 case ISD::BR_CC: return visitBR_CC(N);
889 case ISD::LOAD: return visitLOAD(N);
890 case ISD::STORE: return visitSTORE(N);
891 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
892 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
893 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
894 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
895 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
900 SDValue DAGCombiner::combine(SDNode *N) {
901 SDValue RV = visit(N);
903 // If nothing happened, try a target-specific DAG combine.
904 if (RV.getNode() == 0) {
905 assert(N->getOpcode() != ISD::DELETED_NODE &&
906 "Node was deleted but visit returned NULL!");
908 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
909 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
911 // Expose the DAG combiner to the target combiner impls.
912 TargetLowering::DAGCombinerInfo
913 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
915 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
919 // If N is a commutative binary node, try commuting it to enable more
921 if (RV.getNode() == 0 &&
922 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
923 N->getNumValues() == 1) {
924 SDValue N0 = N->getOperand(0);
925 SDValue N1 = N->getOperand(1);
927 // Constant operands are canonicalized to RHS.
928 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
929 SDValue Ops[] = { N1, N0 };
930 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
933 return SDValue(CSENode, 0);
940 /// getInputChainForNode - Given a node, return its input chain if it has one,
941 /// otherwise return a null sd operand.
942 static SDValue getInputChainForNode(SDNode *N) {
943 if (unsigned NumOps = N->getNumOperands()) {
944 if (N->getOperand(0).getValueType() == MVT::Other)
945 return N->getOperand(0);
946 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
947 return N->getOperand(NumOps-1);
948 for (unsigned i = 1; i < NumOps-1; ++i)
949 if (N->getOperand(i).getValueType() == MVT::Other)
950 return N->getOperand(i);
955 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
956 // If N has two operands, where one has an input chain equal to the other,
957 // the 'other' chain is redundant.
958 if (N->getNumOperands() == 2) {
959 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
960 return N->getOperand(0);
961 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
962 return N->getOperand(1);
965 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
966 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
967 SmallPtrSet<SDNode*, 16> SeenOps;
968 bool Changed = false; // If we should replace this token factor.
970 // Start out with this token factor.
973 // Iterate through token factors. The TFs grows when new token factors are
975 for (unsigned i = 0; i < TFs.size(); ++i) {
978 // Check each of the operands.
979 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
980 SDValue Op = TF->getOperand(i);
982 switch (Op.getOpcode()) {
983 case ISD::EntryToken:
984 // Entry tokens don't need to be added to the list. They are
989 case ISD::TokenFactor:
990 if (Op.hasOneUse() &&
991 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
992 // Queue up for processing.
993 TFs.push_back(Op.getNode());
994 // Clean up in case the token factor is removed.
995 AddToWorkList(Op.getNode());
1002 // Only add if it isn't already in the list.
1003 if (SeenOps.insert(Op.getNode()))
1014 // If we've change things around then replace token factor.
1017 // The entry token is the only possible outcome.
1018 Result = DAG.getEntryNode();
1020 // New and improved token factor.
1021 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1022 MVT::Other, &Ops[0], Ops.size());
1025 // Don't add users to work list.
1026 return CombineTo(N, Result, false);
1032 /// MERGE_VALUES can always be eliminated.
1033 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1034 WorkListRemover DeadNodes(*this);
1035 // Replacing results may cause a different MERGE_VALUES to suddenly
1036 // be CSE'd with N, and carry its uses with it. Iterate until no
1037 // uses remain, to ensure that the node can be safely deleted.
1039 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1040 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1042 } while (!N->use_empty());
1043 removeFromWorkList(N);
1045 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1049 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1050 SelectionDAG &DAG) {
1051 EVT VT = N0.getValueType();
1052 SDValue N00 = N0.getOperand(0);
1053 SDValue N01 = N0.getOperand(1);
1054 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1056 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1057 isa<ConstantSDNode>(N00.getOperand(1))) {
1058 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1059 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1060 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1061 N00.getOperand(0), N01),
1062 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1063 N00.getOperand(1), N01));
1064 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1070 SDValue DAGCombiner::visitADD(SDNode *N) {
1071 SDValue N0 = N->getOperand(0);
1072 SDValue N1 = N->getOperand(1);
1073 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1074 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1075 EVT VT = N0.getValueType();
1078 if (VT.isVector()) {
1079 SDValue FoldedVOp = SimplifyVBinOp(N);
1080 if (FoldedVOp.getNode()) return FoldedVOp;
1083 // fold (add x, undef) -> undef
1084 if (N0.getOpcode() == ISD::UNDEF)
1086 if (N1.getOpcode() == ISD::UNDEF)
1088 // fold (add c1, c2) -> c1+c2
1090 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1091 // canonicalize constant to RHS
1093 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1094 // fold (add x, 0) -> x
1095 if (N1C && N1C->isNullValue())
1097 // fold (add Sym, c) -> Sym+c
1098 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1099 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1100 GA->getOpcode() == ISD::GlobalAddress)
1101 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1103 (uint64_t)N1C->getSExtValue());
1104 // fold ((c1-A)+c2) -> (c1+c2)-A
1105 if (N1C && N0.getOpcode() == ISD::SUB)
1106 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1107 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1108 DAG.getConstant(N1C->getAPIntValue()+
1109 N0C->getAPIntValue(), VT),
1112 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1113 if (RADD.getNode() != 0)
1115 // fold ((0-A) + B) -> B-A
1116 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1117 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1118 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1119 // fold (A + (0-B)) -> A-B
1120 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1121 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1122 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1123 // fold (A+(B-A)) -> B
1124 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1125 return N1.getOperand(0);
1126 // fold ((B-A)+A) -> B
1127 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1128 return N0.getOperand(0);
1129 // fold (A+(B-(A+C))) to (B-C)
1130 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1131 N0 == N1.getOperand(1).getOperand(0))
1132 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1133 N1.getOperand(1).getOperand(1));
1134 // fold (A+(B-(C+A))) to (B-C)
1135 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1136 N0 == N1.getOperand(1).getOperand(1))
1137 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1138 N1.getOperand(1).getOperand(0));
1139 // fold (A+((B-A)+or-C)) to (B+or-C)
1140 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1141 N1.getOperand(0).getOpcode() == ISD::SUB &&
1142 N0 == N1.getOperand(0).getOperand(1))
1143 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1144 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1146 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1147 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1148 SDValue N00 = N0.getOperand(0);
1149 SDValue N01 = N0.getOperand(1);
1150 SDValue N10 = N1.getOperand(0);
1151 SDValue N11 = N1.getOperand(1);
1153 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1154 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1155 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1156 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1159 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1160 return SDValue(N, 0);
1162 // fold (a+b) -> (a|b) iff a and b share no bits.
1163 if (VT.isInteger() && !VT.isVector()) {
1164 APInt LHSZero, LHSOne;
1165 APInt RHSZero, RHSOne;
1166 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1167 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1169 if (LHSZero.getBoolValue()) {
1170 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1172 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1173 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1174 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1175 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1176 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1180 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1181 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1182 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1183 if (Result.getNode()) return Result;
1185 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1186 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1187 if (Result.getNode()) return Result;
1190 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1191 if (N1.getOpcode() == ISD::SHL &&
1192 N1.getOperand(0).getOpcode() == ISD::SUB)
1193 if (ConstantSDNode *C =
1194 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1195 if (C->getAPIntValue() == 0)
1196 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1197 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1198 N1.getOperand(0).getOperand(1),
1200 if (N0.getOpcode() == ISD::SHL &&
1201 N0.getOperand(0).getOpcode() == ISD::SUB)
1202 if (ConstantSDNode *C =
1203 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1204 if (C->getAPIntValue() == 0)
1205 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1206 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1207 N0.getOperand(0).getOperand(1),
1210 return PromoteIntBinOp(SDValue(N, 0));
1213 SDValue DAGCombiner::visitADDC(SDNode *N) {
1214 SDValue N0 = N->getOperand(0);
1215 SDValue N1 = N->getOperand(1);
1216 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1217 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1218 EVT VT = N0.getValueType();
1220 // If the flag result is dead, turn this into an ADD.
1221 if (N->hasNUsesOfValue(0, 1))
1222 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1223 DAG.getNode(ISD::CARRY_FALSE,
1224 N->getDebugLoc(), MVT::Flag));
1226 // canonicalize constant to RHS.
1228 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1230 // fold (addc x, 0) -> x + no carry out
1231 if (N1C && N1C->isNullValue())
1232 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1233 N->getDebugLoc(), MVT::Flag));
1235 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1236 APInt LHSZero, LHSOne;
1237 APInt RHSZero, RHSOne;
1238 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1239 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1241 if (LHSZero.getBoolValue()) {
1242 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1244 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1245 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1246 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1247 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1248 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1249 DAG.getNode(ISD::CARRY_FALSE,
1250 N->getDebugLoc(), MVT::Flag));
1256 SDValue DAGCombiner::visitADDE(SDNode *N) {
1257 SDValue N0 = N->getOperand(0);
1258 SDValue N1 = N->getOperand(1);
1259 SDValue CarryIn = N->getOperand(2);
1260 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1261 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1263 // canonicalize constant to RHS
1265 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1268 // fold (adde x, y, false) -> (addc x, y)
1269 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1270 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1275 SDValue DAGCombiner::visitSUB(SDNode *N) {
1276 SDValue N0 = N->getOperand(0);
1277 SDValue N1 = N->getOperand(1);
1278 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1279 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1280 EVT VT = N0.getValueType();
1283 if (VT.isVector()) {
1284 SDValue FoldedVOp = SimplifyVBinOp(N);
1285 if (FoldedVOp.getNode()) return FoldedVOp;
1288 // fold (sub x, x) -> 0
1290 return DAG.getConstant(0, N->getValueType(0));
1291 // fold (sub c1, c2) -> c1-c2
1293 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1294 // fold (sub x, c) -> (add x, -c)
1296 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1297 DAG.getConstant(-N1C->getAPIntValue(), VT));
1298 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1299 if (N0C && N0C->isAllOnesValue())
1300 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1301 // fold (A+B)-A -> B
1302 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1303 return N0.getOperand(1);
1304 // fold (A+B)-B -> A
1305 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1306 return N0.getOperand(0);
1307 // fold ((A+(B+or-C))-B) -> A+or-C
1308 if (N0.getOpcode() == ISD::ADD &&
1309 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1310 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1311 N0.getOperand(1).getOperand(0) == N1)
1312 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1313 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1314 // fold ((A+(C+B))-B) -> A+C
1315 if (N0.getOpcode() == ISD::ADD &&
1316 N0.getOperand(1).getOpcode() == ISD::ADD &&
1317 N0.getOperand(1).getOperand(1) == N1)
1318 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1319 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1320 // fold ((A-(B-C))-C) -> A-B
1321 if (N0.getOpcode() == ISD::SUB &&
1322 N0.getOperand(1).getOpcode() == ISD::SUB &&
1323 N0.getOperand(1).getOperand(1) == N1)
1324 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1325 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1327 // If either operand of a sub is undef, the result is undef
1328 if (N0.getOpcode() == ISD::UNDEF)
1330 if (N1.getOpcode() == ISD::UNDEF)
1333 // If the relocation model supports it, consider symbol offsets.
1334 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1335 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1336 // fold (sub Sym, c) -> Sym-c
1337 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1338 return DAG.getGlobalAddress(GA->getGlobal(), VT,
1340 (uint64_t)N1C->getSExtValue());
1341 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1342 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1343 if (GA->getGlobal() == GB->getGlobal())
1344 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1348 return PromoteIntBinOp(SDValue(N, 0));
1351 SDValue DAGCombiner::visitMUL(SDNode *N) {
1352 SDValue N0 = N->getOperand(0);
1353 SDValue N1 = N->getOperand(1);
1354 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1355 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1356 EVT VT = N0.getValueType();
1359 if (VT.isVector()) {
1360 SDValue FoldedVOp = SimplifyVBinOp(N);
1361 if (FoldedVOp.getNode()) return FoldedVOp;
1364 // fold (mul x, undef) -> 0
1365 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1366 return DAG.getConstant(0, VT);
1367 // fold (mul c1, c2) -> c1*c2
1369 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1370 // canonicalize constant to RHS
1372 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1373 // fold (mul x, 0) -> 0
1374 if (N1C && N1C->isNullValue())
1376 // fold (mul x, -1) -> 0-x
1377 if (N1C && N1C->isAllOnesValue())
1378 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1379 DAG.getConstant(0, VT), N0);
1380 // fold (mul x, (1 << c)) -> x << c
1381 if (N1C && N1C->getAPIntValue().isPowerOf2())
1382 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1383 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1384 getShiftAmountTy()));
1385 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1386 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1387 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1388 // FIXME: If the input is something that is easily negated (e.g. a
1389 // single-use add), we should put the negate there.
1390 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1391 DAG.getConstant(0, VT),
1392 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1393 DAG.getConstant(Log2Val, getShiftAmountTy())));
1395 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1396 if (N1C && N0.getOpcode() == ISD::SHL &&
1397 isa<ConstantSDNode>(N0.getOperand(1))) {
1398 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1399 N1, N0.getOperand(1));
1400 AddToWorkList(C3.getNode());
1401 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1402 N0.getOperand(0), C3);
1405 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1408 SDValue Sh(0,0), Y(0,0);
1409 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1410 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1411 N0.getNode()->hasOneUse()) {
1413 } else if (N1.getOpcode() == ISD::SHL &&
1414 isa<ConstantSDNode>(N1.getOperand(1)) &&
1415 N1.getNode()->hasOneUse()) {
1420 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1421 Sh.getOperand(0), Y);
1422 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1423 Mul, Sh.getOperand(1));
1427 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1428 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1429 isa<ConstantSDNode>(N0.getOperand(1)))
1430 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1431 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1432 N0.getOperand(0), N1),
1433 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1434 N0.getOperand(1), N1));
1437 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1438 if (RMUL.getNode() != 0)
1441 return PromoteIntBinOp(SDValue(N, 0));
1444 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1445 SDValue N0 = N->getOperand(0);
1446 SDValue N1 = N->getOperand(1);
1447 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1448 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1449 EVT VT = N->getValueType(0);
1452 if (VT.isVector()) {
1453 SDValue FoldedVOp = SimplifyVBinOp(N);
1454 if (FoldedVOp.getNode()) return FoldedVOp;
1457 // fold (sdiv c1, c2) -> c1/c2
1458 if (N0C && N1C && !N1C->isNullValue())
1459 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1460 // fold (sdiv X, 1) -> X
1461 if (N1C && N1C->getSExtValue() == 1LL)
1463 // fold (sdiv X, -1) -> 0-X
1464 if (N1C && N1C->isAllOnesValue())
1465 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1466 DAG.getConstant(0, VT), N0);
1467 // If we know the sign bits of both operands are zero, strength reduce to a
1468 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1469 if (!VT.isVector()) {
1470 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1471 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1474 // fold (sdiv X, pow2) -> simple ops after legalize
1475 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1476 (isPowerOf2_64(N1C->getSExtValue()) ||
1477 isPowerOf2_64(-N1C->getSExtValue()))) {
1478 // If dividing by powers of two is cheap, then don't perform the following
1480 if (TLI.isPow2DivCheap())
1483 int64_t pow2 = N1C->getSExtValue();
1484 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1485 unsigned lg2 = Log2_64(abs2);
1487 // Splat the sign bit into the register
1488 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1489 DAG.getConstant(VT.getSizeInBits()-1,
1490 getShiftAmountTy()));
1491 AddToWorkList(SGN.getNode());
1493 // Add (N0 < 0) ? abs2 - 1 : 0;
1494 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1495 DAG.getConstant(VT.getSizeInBits() - lg2,
1496 getShiftAmountTy()));
1497 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1498 AddToWorkList(SRL.getNode());
1499 AddToWorkList(ADD.getNode()); // Divide by pow2
1500 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1501 DAG.getConstant(lg2, getShiftAmountTy()));
1503 // If we're dividing by a positive value, we're done. Otherwise, we must
1504 // negate the result.
1508 AddToWorkList(SRA.getNode());
1509 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1510 DAG.getConstant(0, VT), SRA);
1513 // if integer divide is expensive and we satisfy the requirements, emit an
1514 // alternate sequence.
1515 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) &&
1516 !TLI.isIntDivCheap()) {
1517 SDValue Op = BuildSDIV(N);
1518 if (Op.getNode()) return Op;
1522 if (N0.getOpcode() == ISD::UNDEF)
1523 return DAG.getConstant(0, VT);
1524 // X / undef -> undef
1525 if (N1.getOpcode() == ISD::UNDEF)
1531 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1532 SDValue N0 = N->getOperand(0);
1533 SDValue N1 = N->getOperand(1);
1534 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1535 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1536 EVT VT = N->getValueType(0);
1539 if (VT.isVector()) {
1540 SDValue FoldedVOp = SimplifyVBinOp(N);
1541 if (FoldedVOp.getNode()) return FoldedVOp;
1544 // fold (udiv c1, c2) -> c1/c2
1545 if (N0C && N1C && !N1C->isNullValue())
1546 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1547 // fold (udiv x, (1 << c)) -> x >>u c
1548 if (N1C && N1C->getAPIntValue().isPowerOf2())
1549 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1550 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1551 getShiftAmountTy()));
1552 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1553 if (N1.getOpcode() == ISD::SHL) {
1554 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1555 if (SHC->getAPIntValue().isPowerOf2()) {
1556 EVT ADDVT = N1.getOperand(1).getValueType();
1557 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1559 DAG.getConstant(SHC->getAPIntValue()
1562 AddToWorkList(Add.getNode());
1563 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1567 // fold (udiv x, c) -> alternate
1568 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1569 SDValue Op = BuildUDIV(N);
1570 if (Op.getNode()) return Op;
1574 if (N0.getOpcode() == ISD::UNDEF)
1575 return DAG.getConstant(0, VT);
1576 // X / undef -> undef
1577 if (N1.getOpcode() == ISD::UNDEF)
1583 SDValue DAGCombiner::visitSREM(SDNode *N) {
1584 SDValue N0 = N->getOperand(0);
1585 SDValue N1 = N->getOperand(1);
1586 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1587 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1588 EVT VT = N->getValueType(0);
1590 // fold (srem c1, c2) -> c1%c2
1591 if (N0C && N1C && !N1C->isNullValue())
1592 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1593 // If we know the sign bits of both operands are zero, strength reduce to a
1594 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1595 if (!VT.isVector()) {
1596 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1597 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1600 // If X/C can be simplified by the division-by-constant logic, lower
1601 // X%C to the equivalent of X-X/C*C.
1602 if (N1C && !N1C->isNullValue()) {
1603 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1604 AddToWorkList(Div.getNode());
1605 SDValue OptimizedDiv = combine(Div.getNode());
1606 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1607 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1609 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1610 AddToWorkList(Mul.getNode());
1616 if (N0.getOpcode() == ISD::UNDEF)
1617 return DAG.getConstant(0, VT);
1618 // X % undef -> undef
1619 if (N1.getOpcode() == ISD::UNDEF)
1625 SDValue DAGCombiner::visitUREM(SDNode *N) {
1626 SDValue N0 = N->getOperand(0);
1627 SDValue N1 = N->getOperand(1);
1628 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1629 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1630 EVT VT = N->getValueType(0);
1632 // fold (urem c1, c2) -> c1%c2
1633 if (N0C && N1C && !N1C->isNullValue())
1634 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1635 // fold (urem x, pow2) -> (and x, pow2-1)
1636 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1637 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1638 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1639 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1640 if (N1.getOpcode() == ISD::SHL) {
1641 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1642 if (SHC->getAPIntValue().isPowerOf2()) {
1644 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1645 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1647 AddToWorkList(Add.getNode());
1648 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1653 // If X/C can be simplified by the division-by-constant logic, lower
1654 // X%C to the equivalent of X-X/C*C.
1655 if (N1C && !N1C->isNullValue()) {
1656 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1657 AddToWorkList(Div.getNode());
1658 SDValue OptimizedDiv = combine(Div.getNode());
1659 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1660 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1662 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1663 AddToWorkList(Mul.getNode());
1669 if (N0.getOpcode() == ISD::UNDEF)
1670 return DAG.getConstant(0, VT);
1671 // X % undef -> undef
1672 if (N1.getOpcode() == ISD::UNDEF)
1678 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1679 SDValue N0 = N->getOperand(0);
1680 SDValue N1 = N->getOperand(1);
1681 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1682 EVT VT = N->getValueType(0);
1684 // fold (mulhs x, 0) -> 0
1685 if (N1C && N1C->isNullValue())
1687 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1688 if (N1C && N1C->getAPIntValue() == 1)
1689 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1690 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1691 getShiftAmountTy()));
1692 // fold (mulhs x, undef) -> 0
1693 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1694 return DAG.getConstant(0, VT);
1699 SDValue DAGCombiner::visitMULHU(SDNode *N) {
1700 SDValue N0 = N->getOperand(0);
1701 SDValue N1 = N->getOperand(1);
1702 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1703 EVT VT = N->getValueType(0);
1705 // fold (mulhu x, 0) -> 0
1706 if (N1C && N1C->isNullValue())
1708 // fold (mulhu x, 1) -> 0
1709 if (N1C && N1C->getAPIntValue() == 1)
1710 return DAG.getConstant(0, N0.getValueType());
1711 // fold (mulhu x, undef) -> 0
1712 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1713 return DAG.getConstant(0, VT);
1718 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
1719 /// compute two values. LoOp and HiOp give the opcodes for the two computations
1720 /// that are being performed. Return true if a simplification was made.
1722 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
1724 // If the high half is not needed, just compute the low half.
1725 bool HiExists = N->hasAnyUseOfValue(1);
1727 (!LegalOperations ||
1728 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
1729 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1730 N->op_begin(), N->getNumOperands());
1731 return CombineTo(N, Res, Res);
1734 // If the low half is not needed, just compute the high half.
1735 bool LoExists = N->hasAnyUseOfValue(0);
1737 (!LegalOperations ||
1738 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
1739 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1740 N->op_begin(), N->getNumOperands());
1741 return CombineTo(N, Res, Res);
1744 // If both halves are used, return as it is.
1745 if (LoExists && HiExists)
1748 // If the two computed results can be simplified separately, separate them.
1750 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
1751 N->op_begin(), N->getNumOperands());
1752 AddToWorkList(Lo.getNode());
1753 SDValue LoOpt = combine(Lo.getNode());
1754 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
1755 (!LegalOperations ||
1756 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
1757 return CombineTo(N, LoOpt, LoOpt);
1761 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
1762 N->op_begin(), N->getNumOperands());
1763 AddToWorkList(Hi.getNode());
1764 SDValue HiOpt = combine(Hi.getNode());
1765 if (HiOpt.getNode() && HiOpt != Hi &&
1766 (!LegalOperations ||
1767 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
1768 return CombineTo(N, HiOpt, HiOpt);
1774 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
1775 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
1776 if (Res.getNode()) return Res;
1781 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
1782 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
1783 if (Res.getNode()) return Res;
1788 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
1789 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
1790 if (Res.getNode()) return Res;
1795 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
1796 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
1797 if (Res.getNode()) return Res;
1802 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1803 /// two operands of the same opcode, try to simplify it.
1804 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1805 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1806 EVT VT = N0.getValueType();
1807 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1809 // Bail early if none of these transforms apply.
1810 if (N0.getNode()->getNumOperands() == 0) return SDValue();
1812 // For each of OP in AND/OR/XOR:
1813 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1814 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1815 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1816 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1818 // do not sink logical op inside of a vector extend, since it may combine
1820 EVT Op0VT = N0.getOperand(0).getValueType();
1821 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
1822 N0.getOpcode() == ISD::SIGN_EXTEND ||
1823 // Avoid infinite looping with PromoteIntBinOp.
1824 (N0.getOpcode() == ISD::ANY_EXTEND &&
1825 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
1826 (N0.getOpcode() == ISD::TRUNCATE && TLI.isTypeLegal(Op0VT))) &&
1828 Op0VT == N1.getOperand(0).getValueType() &&
1829 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
1830 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1831 N0.getOperand(0).getValueType(),
1832 N0.getOperand(0), N1.getOperand(0));
1833 AddToWorkList(ORNode.getNode());
1834 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
1837 // For each of OP in SHL/SRL/SRA/AND...
1838 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1839 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1840 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1841 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1842 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1843 N0.getOperand(1) == N1.getOperand(1)) {
1844 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
1845 N0.getOperand(0).getValueType(),
1846 N0.getOperand(0), N1.getOperand(0));
1847 AddToWorkList(ORNode.getNode());
1848 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
1849 ORNode, N0.getOperand(1));
1855 SDValue DAGCombiner::visitAND(SDNode *N) {
1856 SDValue N0 = N->getOperand(0);
1857 SDValue N1 = N->getOperand(1);
1858 SDValue LL, LR, RL, RR, CC0, CC1;
1859 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1860 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1861 EVT VT = N1.getValueType();
1862 unsigned BitWidth = VT.getScalarType().getSizeInBits();
1865 if (VT.isVector()) {
1866 SDValue FoldedVOp = SimplifyVBinOp(N);
1867 if (FoldedVOp.getNode()) return FoldedVOp;
1870 // fold (and x, undef) -> 0
1871 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1872 return DAG.getConstant(0, VT);
1873 // fold (and c1, c2) -> c1&c2
1875 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
1876 // canonicalize constant to RHS
1878 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
1879 // fold (and x, -1) -> x
1880 if (N1C && N1C->isAllOnesValue())
1882 // if (and x, c) is known to be zero, return 0
1883 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
1884 APInt::getAllOnesValue(BitWidth)))
1885 return DAG.getConstant(0, VT);
1887 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
1888 if (RAND.getNode() != 0)
1890 // fold (and (or x, C), D) -> D if (C & D) == D
1891 if (N1C && N0.getOpcode() == ISD::OR)
1892 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1893 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
1895 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1896 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1897 SDValue N0Op0 = N0.getOperand(0);
1898 APInt Mask = ~N1C->getAPIntValue();
1899 Mask.trunc(N0Op0.getValueSizeInBits());
1900 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
1901 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
1902 N0.getValueType(), N0Op0);
1904 // Replace uses of the AND with uses of the Zero extend node.
1907 // We actually want to replace all uses of the any_extend with the
1908 // zero_extend, to avoid duplicating things. This will later cause this
1909 // AND to be folded.
1910 CombineTo(N0.getNode(), Zext);
1911 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1914 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1915 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1916 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1917 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1919 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1920 LL.getValueType().isInteger()) {
1921 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
1922 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
1923 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1924 LR.getValueType(), LL, RL);
1925 AddToWorkList(ORNode.getNode());
1926 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1928 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
1929 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1930 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
1931 LR.getValueType(), LL, RL);
1932 AddToWorkList(ANDNode.getNode());
1933 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
1935 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
1936 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1937 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
1938 LR.getValueType(), LL, RL);
1939 AddToWorkList(ORNode.getNode());
1940 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
1943 // canonicalize equivalent to ll == rl
1944 if (LL == RR && LR == RL) {
1945 Op1 = ISD::getSetCCSwappedOperands(Op1);
1948 if (LL == RL && LR == RR) {
1949 bool isInteger = LL.getValueType().isInteger();
1950 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1951 if (Result != ISD::SETCC_INVALID &&
1952 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
1953 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
1958 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
1959 if (N0.getOpcode() == N1.getOpcode()) {
1960 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1961 if (Tmp.getNode()) return Tmp;
1964 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1965 // fold (and (sra)) -> (and (srl)) when possible.
1966 if (!VT.isVector() &&
1967 SimplifyDemandedBits(SDValue(N, 0)))
1968 return SDValue(N, 0);
1970 // fold (zext_inreg (extload x)) -> (zextload x)
1971 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
1972 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1973 EVT MemVT = LN0->getMemoryVT();
1974 // If we zero all the possible extended bits, then we can turn this into
1975 // a zextload if we are running before legalize or the operation is legal.
1976 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
1977 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1978 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
1979 ((!LegalOperations && !LN0->isVolatile()) ||
1980 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
1981 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
1982 LN0->getChain(), LN0->getBasePtr(),
1984 LN0->getSrcValueOffset(), MemVT,
1985 LN0->isVolatile(), LN0->isNonTemporal(),
1986 LN0->getAlignment());
1988 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
1989 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1992 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1993 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
1995 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1996 EVT MemVT = LN0->getMemoryVT();
1997 // If we zero all the possible extended bits, then we can turn this into
1998 // a zextload if we are running before legalize or the operation is legal.
1999 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2000 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2001 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2002 ((!LegalOperations && !LN0->isVolatile()) ||
2003 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2004 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2006 LN0->getBasePtr(), LN0->getSrcValue(),
2007 LN0->getSrcValueOffset(), MemVT,
2008 LN0->isVolatile(), LN0->isNonTemporal(),
2009 LN0->getAlignment());
2011 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2012 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2016 // fold (and (load x), 255) -> (zextload x, i8)
2017 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2018 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2019 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2020 (N0.getOpcode() == ISD::ANY_EXTEND &&
2021 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2022 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2023 LoadSDNode *LN0 = HasAnyExt
2024 ? cast<LoadSDNode>(N0.getOperand(0))
2025 : cast<LoadSDNode>(N0);
2026 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2027 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2028 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2029 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2030 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2031 EVT LoadedVT = LN0->getMemoryVT();
2033 if (ExtVT == LoadedVT &&
2034 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2035 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2038 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2039 LN0->getChain(), LN0->getBasePtr(),
2040 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2041 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2042 LN0->getAlignment());
2044 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2045 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2048 // Do not change the width of a volatile load.
2049 // Do not generate loads of non-round integer types since these can
2050 // be expensive (and would be wrong if the type is not byte sized).
2051 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2052 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2053 EVT PtrType = LN0->getOperand(1).getValueType();
2055 unsigned Alignment = LN0->getAlignment();
2056 SDValue NewPtr = LN0->getBasePtr();
2058 // For big endian targets, we need to add an offset to the pointer
2059 // to load the correct bytes. For little endian systems, we merely
2060 // need to read fewer bytes from the same pointer.
2061 if (TLI.isBigEndian()) {
2062 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2063 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2064 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2065 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2066 NewPtr, DAG.getConstant(PtrOff, PtrType));
2067 Alignment = MinAlign(Alignment, PtrOff);
2070 AddToWorkList(NewPtr.getNode());
2072 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2074 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2075 LN0->getChain(), NewPtr,
2076 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2077 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2080 CombineTo(LN0, Load, Load.getValue(1));
2081 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2087 return PromoteIntBinOp(SDValue(N, 0));
2090 SDValue DAGCombiner::visitOR(SDNode *N) {
2091 SDValue N0 = N->getOperand(0);
2092 SDValue N1 = N->getOperand(1);
2093 SDValue LL, LR, RL, RR, CC0, CC1;
2094 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2095 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2096 EVT VT = N1.getValueType();
2099 if (VT.isVector()) {
2100 SDValue FoldedVOp = SimplifyVBinOp(N);
2101 if (FoldedVOp.getNode()) return FoldedVOp;
2104 // fold (or x, undef) -> -1
2105 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) {
2106 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2107 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2109 // fold (or c1, c2) -> c1|c2
2111 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2112 // canonicalize constant to RHS
2114 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2115 // fold (or x, 0) -> x
2116 if (N1C && N1C->isNullValue())
2118 // fold (or x, -1) -> -1
2119 if (N1C && N1C->isAllOnesValue())
2121 // fold (or x, c) -> c iff (x & ~c) == 0
2122 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2125 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2126 if (ROR.getNode() != 0)
2128 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2129 // iff (c1 & c2) == 0.
2130 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2131 isa<ConstantSDNode>(N0.getOperand(1))) {
2132 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2133 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2134 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2135 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2136 N0.getOperand(0), N1),
2137 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2139 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2140 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2141 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2142 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2144 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2145 LL.getValueType().isInteger()) {
2146 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2147 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2148 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2149 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2150 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2151 LR.getValueType(), LL, RL);
2152 AddToWorkList(ORNode.getNode());
2153 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2155 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2156 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2157 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2158 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2159 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2160 LR.getValueType(), LL, RL);
2161 AddToWorkList(ANDNode.getNode());
2162 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2165 // canonicalize equivalent to ll == rl
2166 if (LL == RR && LR == RL) {
2167 Op1 = ISD::getSetCCSwappedOperands(Op1);
2170 if (LL == RL && LR == RR) {
2171 bool isInteger = LL.getValueType().isInteger();
2172 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2173 if (Result != ISD::SETCC_INVALID &&
2174 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2175 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2180 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2181 if (N0.getOpcode() == N1.getOpcode()) {
2182 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2183 if (Tmp.getNode()) return Tmp;
2186 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2187 if (N0.getOpcode() == ISD::AND &&
2188 N1.getOpcode() == ISD::AND &&
2189 N0.getOperand(1).getOpcode() == ISD::Constant &&
2190 N1.getOperand(1).getOpcode() == ISD::Constant &&
2191 // Don't increase # computations.
2192 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2193 // We can only do this xform if we know that bits from X that are set in C2
2194 // but not in C1 are already zero. Likewise for Y.
2195 const APInt &LHSMask =
2196 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2197 const APInt &RHSMask =
2198 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2200 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2201 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2202 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2203 N0.getOperand(0), N1.getOperand(0));
2204 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2205 DAG.getConstant(LHSMask | RHSMask, VT));
2209 // See if this is some rotate idiom.
2210 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2211 return SDValue(Rot, 0);
2213 return PromoteIntBinOp(SDValue(N, 0));
2216 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2217 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2218 if (Op.getOpcode() == ISD::AND) {
2219 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2220 Mask = Op.getOperand(1);
2221 Op = Op.getOperand(0);
2227 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2235 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2236 // idioms for rotate, and if the target supports rotation instructions, generate
2238 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2239 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2240 EVT VT = LHS.getValueType();
2241 if (!TLI.isTypeLegal(VT)) return 0;
2243 // The target must have at least one rotate flavor.
2244 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2245 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2246 if (!HasROTL && !HasROTR) return 0;
2248 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2249 SDValue LHSShift; // The shift.
2250 SDValue LHSMask; // AND value if any.
2251 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2252 return 0; // Not part of a rotate.
2254 SDValue RHSShift; // The shift.
2255 SDValue RHSMask; // AND value if any.
2256 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2257 return 0; // Not part of a rotate.
2259 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2260 return 0; // Not shifting the same value.
2262 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2263 return 0; // Shifts must disagree.
2265 // Canonicalize shl to left side in a shl/srl pair.
2266 if (RHSShift.getOpcode() == ISD::SHL) {
2267 std::swap(LHS, RHS);
2268 std::swap(LHSShift, RHSShift);
2269 std::swap(LHSMask , RHSMask );
2272 unsigned OpSizeInBits = VT.getSizeInBits();
2273 SDValue LHSShiftArg = LHSShift.getOperand(0);
2274 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2275 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2277 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2278 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2279 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2280 RHSShiftAmt.getOpcode() == ISD::Constant) {
2281 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2282 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2283 if ((LShVal + RShVal) != OpSizeInBits)
2288 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2290 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2292 // If there is an AND of either shifted operand, apply it to the result.
2293 if (LHSMask.getNode() || RHSMask.getNode()) {
2294 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2296 if (LHSMask.getNode()) {
2297 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2298 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2300 if (RHSMask.getNode()) {
2301 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2302 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2305 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2308 return Rot.getNode();
2311 // If there is a mask here, and we have a variable shift, we can't be sure
2312 // that we're masking out the right stuff.
2313 if (LHSMask.getNode() || RHSMask.getNode())
2316 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2317 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2318 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2319 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2320 if (ConstantSDNode *SUBC =
2321 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2322 if (SUBC->getAPIntValue() == OpSizeInBits) {
2324 return DAG.getNode(ISD::ROTL, DL, VT,
2325 LHSShiftArg, LHSShiftAmt).getNode();
2327 return DAG.getNode(ISD::ROTR, DL, VT,
2328 LHSShiftArg, RHSShiftAmt).getNode();
2333 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2334 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2335 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2336 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2337 if (ConstantSDNode *SUBC =
2338 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2339 if (SUBC->getAPIntValue() == OpSizeInBits) {
2341 return DAG.getNode(ISD::ROTR, DL, VT,
2342 LHSShiftArg, RHSShiftAmt).getNode();
2344 return DAG.getNode(ISD::ROTL, DL, VT,
2345 LHSShiftArg, LHSShiftAmt).getNode();
2350 // Look for sign/zext/any-extended or truncate cases:
2351 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2352 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2353 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2354 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
2355 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
2356 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
2357 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
2358 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
2359 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
2360 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
2361 if (RExtOp0.getOpcode() == ISD::SUB &&
2362 RExtOp0.getOperand(1) == LExtOp0) {
2363 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2365 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
2366 // (rotr x, (sub 32, y))
2367 if (ConstantSDNode *SUBC =
2368 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
2369 if (SUBC->getAPIntValue() == OpSizeInBits) {
2370 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
2372 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
2375 } else if (LExtOp0.getOpcode() == ISD::SUB &&
2376 RExtOp0 == LExtOp0.getOperand(1)) {
2377 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2379 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
2380 // (rotl x, (sub 32, y))
2381 if (ConstantSDNode *SUBC =
2382 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
2383 if (SUBC->getAPIntValue() == OpSizeInBits) {
2384 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
2386 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
2395 SDValue DAGCombiner::visitXOR(SDNode *N) {
2396 SDValue N0 = N->getOperand(0);
2397 SDValue N1 = N->getOperand(1);
2398 SDValue LHS, RHS, CC;
2399 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2400 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2401 EVT VT = N0.getValueType();
2404 if (VT.isVector()) {
2405 SDValue FoldedVOp = SimplifyVBinOp(N);
2406 if (FoldedVOp.getNode()) return FoldedVOp;
2409 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
2410 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
2411 return DAG.getConstant(0, VT);
2412 // fold (xor x, undef) -> undef
2413 if (N0.getOpcode() == ISD::UNDEF)
2415 if (N1.getOpcode() == ISD::UNDEF)
2417 // fold (xor c1, c2) -> c1^c2
2419 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
2420 // canonicalize constant to RHS
2422 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
2423 // fold (xor x, 0) -> x
2424 if (N1C && N1C->isNullValue())
2427 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
2428 if (RXOR.getNode() != 0)
2431 // fold !(x cc y) -> (x !cc y)
2432 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2433 bool isInt = LHS.getValueType().isInteger();
2434 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
2437 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
2438 switch (N0.getOpcode()) {
2440 llvm_unreachable("Unhandled SetCC Equivalent!");
2442 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
2443 case ISD::SELECT_CC:
2444 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
2445 N0.getOperand(3), NotCC);
2450 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
2451 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
2452 N0.getNode()->hasOneUse() &&
2453 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
2454 SDValue V = N0.getOperand(0);
2455 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
2456 DAG.getConstant(1, V.getValueType()));
2457 AddToWorkList(V.getNode());
2458 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
2461 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2462 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
2463 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2464 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2465 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
2466 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2467 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2468 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2469 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2470 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2473 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
2474 if (N1C && N1C->isAllOnesValue() &&
2475 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
2476 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
2477 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
2478 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
2479 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
2480 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
2481 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
2482 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
2485 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
2486 if (N1C && N0.getOpcode() == ISD::XOR) {
2487 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
2488 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2490 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
2491 DAG.getConstant(N1C->getAPIntValue() ^
2492 N00C->getAPIntValue(), VT));
2494 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
2495 DAG.getConstant(N1C->getAPIntValue() ^
2496 N01C->getAPIntValue(), VT));
2498 // fold (xor x, x) -> 0
2500 if (!VT.isVector()) {
2501 return DAG.getConstant(0, VT);
2502 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){
2503 // Produce a vector of zeros.
2504 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
2505 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
2506 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
2507 &Ops[0], Ops.size());
2511 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
2512 if (N0.getOpcode() == N1.getOpcode()) {
2513 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2514 if (Tmp.getNode()) return Tmp;
2517 // Simplify the expression using non-local knowledge.
2518 if (!VT.isVector() &&
2519 SimplifyDemandedBits(SDValue(N, 0)))
2520 return SDValue(N, 0);
2522 return PromoteIntBinOp(SDValue(N, 0));
2525 /// visitShiftByConstant - Handle transforms common to the three shifts, when
2526 /// the shift amount is a constant.
2527 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
2528 SDNode *LHS = N->getOperand(0).getNode();
2529 if (!LHS->hasOneUse()) return SDValue();
2531 // We want to pull some binops through shifts, so that we have (and (shift))
2532 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
2533 // thing happens with address calculations, so it's important to canonicalize
2535 bool HighBitSet = false; // Can we transform this if the high bit is set?
2537 switch (LHS->getOpcode()) {
2538 default: return SDValue();
2541 HighBitSet = false; // We can only transform sra if the high bit is clear.
2544 HighBitSet = true; // We can only transform sra if the high bit is set.
2547 if (N->getOpcode() != ISD::SHL)
2548 return SDValue(); // only shl(add) not sr[al](add).
2549 HighBitSet = false; // We can only transform sra if the high bit is clear.
2553 // We require the RHS of the binop to be a constant as well.
2554 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
2555 if (!BinOpCst) return SDValue();
2557 // FIXME: disable this unless the input to the binop is a shift by a constant.
2558 // If it is not a shift, it pessimizes some common cases like:
2560 // void foo(int *X, int i) { X[i & 1235] = 1; }
2561 // int bar(int *X, int i) { return X[i & 255]; }
2562 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
2563 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
2564 BinOpLHSVal->getOpcode() != ISD::SRA &&
2565 BinOpLHSVal->getOpcode() != ISD::SRL) ||
2566 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
2569 EVT VT = N->getValueType(0);
2571 // If this is a signed shift right, and the high bit is modified by the
2572 // logical operation, do not perform the transformation. The highBitSet
2573 // boolean indicates the value of the high bit of the constant which would
2574 // cause it to be modified for this operation.
2575 if (N->getOpcode() == ISD::SRA) {
2576 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
2577 if (BinOpRHSSignSet != HighBitSet)
2581 // Fold the constants, shifting the binop RHS by the shift amount.
2582 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
2584 LHS->getOperand(1), N->getOperand(1));
2586 // Create the new shift.
2587 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(),
2588 VT, LHS->getOperand(0), N->getOperand(1));
2590 // Create the new binop.
2591 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
2594 SDValue DAGCombiner::visitSHL(SDNode *N) {
2595 SDValue N0 = N->getOperand(0);
2596 SDValue N1 = N->getOperand(1);
2597 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2598 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2599 EVT VT = N0.getValueType();
2600 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2602 // fold (shl c1, c2) -> c1<<c2
2604 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
2605 // fold (shl 0, x) -> 0
2606 if (N0C && N0C->isNullValue())
2608 // fold (shl x, c >= size(x)) -> undef
2609 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2610 return DAG.getUNDEF(VT);
2611 // fold (shl x, 0) -> x
2612 if (N1C && N1C->isNullValue())
2614 // if (shl x, c) is known to be zero, return 0
2615 if (DAG.MaskedValueIsZero(SDValue(N, 0),
2616 APInt::getAllOnesValue(OpSizeInBits)))
2617 return DAG.getConstant(0, VT);
2618 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
2619 if (N1.getOpcode() == ISD::TRUNCATE &&
2620 N1.getOperand(0).getOpcode() == ISD::AND &&
2621 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2622 SDValue N101 = N1.getOperand(0).getOperand(1);
2623 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2624 EVT TruncVT = N1.getValueType();
2625 SDValue N100 = N1.getOperand(0).getOperand(0);
2626 APInt TruncC = N101C->getAPIntValue();
2627 TruncC.trunc(TruncVT.getSizeInBits());
2628 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
2629 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
2630 DAG.getNode(ISD::TRUNCATE,
2633 DAG.getConstant(TruncC, TruncVT)));
2637 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2638 return SDValue(N, 0);
2640 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
2641 if (N1C && N0.getOpcode() == ISD::SHL &&
2642 N0.getOperand(1).getOpcode() == ISD::Constant) {
2643 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2644 uint64_t c2 = N1C->getZExtValue();
2645 if (c1 + c2 > OpSizeInBits)
2646 return DAG.getConstant(0, VT);
2647 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
2648 DAG.getConstant(c1 + c2, N1.getValueType()));
2650 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or
2651 // (srl (and x, (shl -1, c1)), (sub c1, c2))
2652 if (N1C && N0.getOpcode() == ISD::SRL &&
2653 N0.getOperand(1).getOpcode() == ISD::Constant) {
2654 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2655 if (c1 < VT.getSizeInBits()) {
2656 uint64_t c2 = N1C->getZExtValue();
2657 SDValue HiBitsMask =
2658 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2659 VT.getSizeInBits() - c1),
2661 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT,
2665 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask,
2666 DAG.getConstant(c2-c1, N1.getValueType()));
2668 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask,
2669 DAG.getConstant(c1-c2, N1.getValueType()));
2672 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
2673 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
2674 SDValue HiBitsMask =
2675 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
2676 VT.getSizeInBits() -
2677 N1C->getZExtValue()),
2679 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2684 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
2685 if (NewSHL.getNode())
2689 return PromoteIntBinOp(SDValue(N, 0));
2692 SDValue DAGCombiner::visitSRA(SDNode *N) {
2693 SDValue N0 = N->getOperand(0);
2694 SDValue N1 = N->getOperand(1);
2695 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2696 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2697 EVT VT = N0.getValueType();
2698 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2700 // fold (sra c1, c2) -> (sra c1, c2)
2702 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
2703 // fold (sra 0, x) -> 0
2704 if (N0C && N0C->isNullValue())
2706 // fold (sra -1, x) -> -1
2707 if (N0C && N0C->isAllOnesValue())
2709 // fold (sra x, (setge c, size(x))) -> undef
2710 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2711 return DAG.getUNDEF(VT);
2712 // fold (sra x, 0) -> x
2713 if (N1C && N1C->isNullValue())
2715 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2717 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2718 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
2719 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
2721 ExtVT = EVT::getVectorVT(*DAG.getContext(),
2722 ExtVT, VT.getVectorNumElements());
2723 if ((!LegalOperations ||
2724 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
2725 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
2726 N0.getOperand(0), DAG.getValueType(ExtVT));
2729 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
2730 if (N1C && N0.getOpcode() == ISD::SRA) {
2731 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2732 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
2733 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
2734 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
2735 DAG.getConstant(Sum, N1C->getValueType(0)));
2739 // fold (sra (shl X, m), (sub result_size, n))
2740 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
2741 // result_size - n != m.
2742 // If truncate is free for the target sext(shl) is likely to result in better
2744 if (N0.getOpcode() == ISD::SHL) {
2745 // Get the two constanst of the shifts, CN0 = m, CN = n.
2746 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2748 // Determine what the truncate's result bitsize and type would be.
2750 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue());
2751 // Determine the residual right-shift amount.
2752 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
2754 // If the shift is not a no-op (in which case this should be just a sign
2755 // extend already), the truncated to type is legal, sign_extend is legal
2756 // on that type, and the truncate to that type is both legal and free,
2757 // perform the transform.
2758 if ((ShiftAmt > 0) &&
2759 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
2760 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
2761 TLI.isTruncateFree(VT, TruncVT)) {
2763 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy());
2764 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
2765 N0.getOperand(0), Amt);
2766 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
2768 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
2769 N->getValueType(0), Trunc);
2774 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
2775 if (N1.getOpcode() == ISD::TRUNCATE &&
2776 N1.getOperand(0).getOpcode() == ISD::AND &&
2777 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2778 SDValue N101 = N1.getOperand(0).getOperand(1);
2779 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2780 EVT TruncVT = N1.getValueType();
2781 SDValue N100 = N1.getOperand(0).getOperand(0);
2782 APInt TruncC = N101C->getAPIntValue();
2783 TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
2784 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
2785 DAG.getNode(ISD::AND, N->getDebugLoc(),
2787 DAG.getNode(ISD::TRUNCATE,
2790 DAG.getConstant(TruncC, TruncVT)));
2794 // Simplify, based on bits shifted out of the LHS.
2795 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2796 return SDValue(N, 0);
2799 // If the sign bit is known to be zero, switch this to a SRL.
2800 if (DAG.SignBitIsZero(N0))
2801 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
2804 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
2805 if (NewSRA.getNode())
2809 return PromoteIntBinOp(SDValue(N, 0));
2812 SDValue DAGCombiner::visitSRL(SDNode *N) {
2813 SDValue N0 = N->getOperand(0);
2814 SDValue N1 = N->getOperand(1);
2815 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2816 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2817 EVT VT = N0.getValueType();
2818 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
2820 // fold (srl c1, c2) -> c1 >>u c2
2822 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
2823 // fold (srl 0, x) -> 0
2824 if (N0C && N0C->isNullValue())
2826 // fold (srl x, c >= size(x)) -> undef
2827 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
2828 return DAG.getUNDEF(VT);
2829 // fold (srl x, 0) -> x
2830 if (N1C && N1C->isNullValue())
2832 // if (srl x, c) is known to be zero, return 0
2833 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2834 APInt::getAllOnesValue(OpSizeInBits)))
2835 return DAG.getConstant(0, VT);
2837 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
2838 if (N1C && N0.getOpcode() == ISD::SRL &&
2839 N0.getOperand(1).getOpcode() == ISD::Constant) {
2840 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
2841 uint64_t c2 = N1C->getZExtValue();
2842 if (c1 + c2 > OpSizeInBits)
2843 return DAG.getConstant(0, VT);
2844 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
2845 DAG.getConstant(c1 + c2, N1.getValueType()));
2848 // fold (srl (shl x, c), c) -> (and x, cst2)
2849 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
2850 N0.getValueSizeInBits() <= 64) {
2851 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
2852 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
2853 DAG.getConstant(~0ULL >> ShAmt, VT));
2857 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2858 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2859 // Shifting in all undef bits?
2860 EVT SmallVT = N0.getOperand(0).getValueType();
2861 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
2862 return DAG.getUNDEF(VT);
2864 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
2865 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
2866 N0.getOperand(0), N1);
2867 AddToWorkList(SmallShift.getNode());
2868 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
2872 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2873 // bit, which is unmodified by sra.
2874 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
2875 if (N0.getOpcode() == ISD::SRA)
2876 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
2879 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2880 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2881 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
2882 APInt KnownZero, KnownOne;
2883 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
2884 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2886 // If any of the input bits are KnownOne, then the input couldn't be all
2887 // zeros, thus the result of the srl will always be zero.
2888 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
2890 // If all of the bits input the to ctlz node are known to be zero, then
2891 // the result of the ctlz is "32" and the result of the shift is one.
2892 APInt UnknownBits = ~KnownZero & Mask;
2893 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2895 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2896 if ((UnknownBits & (UnknownBits - 1)) == 0) {
2897 // Okay, we know that only that the single bit specified by UnknownBits
2898 // could be set on input to the CTLZ node. If this bit is set, the SRL
2899 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2900 // to an SRL/XOR pair, which is likely to simplify more.
2901 unsigned ShAmt = UnknownBits.countTrailingZeros();
2902 SDValue Op = N0.getOperand(0);
2905 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
2906 DAG.getConstant(ShAmt, getShiftAmountTy()));
2907 AddToWorkList(Op.getNode());
2910 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
2911 Op, DAG.getConstant(1, VT));
2915 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
2916 if (N1.getOpcode() == ISD::TRUNCATE &&
2917 N1.getOperand(0).getOpcode() == ISD::AND &&
2918 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
2919 SDValue N101 = N1.getOperand(0).getOperand(1);
2920 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
2921 EVT TruncVT = N1.getValueType();
2922 SDValue N100 = N1.getOperand(0).getOperand(0);
2923 APInt TruncC = N101C->getAPIntValue();
2924 TruncC.trunc(TruncVT.getSizeInBits());
2925 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
2926 DAG.getNode(ISD::AND, N->getDebugLoc(),
2928 DAG.getNode(ISD::TRUNCATE,
2931 DAG.getConstant(TruncC, TruncVT)));
2935 // fold operands of srl based on knowledge that the low bits are not
2937 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
2938 return SDValue(N, 0);
2941 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
2942 if (NewSRL.getNode())
2946 // Here is a common situation. We want to optimize:
2949 // %b = and i32 %a, 2
2950 // %c = srl i32 %b, 1
2951 // brcond i32 %c ...
2957 // %c = setcc eq %b, 0
2960 // However when after the source operand of SRL is optimized into AND, the SRL
2961 // itself may not be optimized further. Look for it and add the BRCOND into
2963 if (N->hasOneUse()) {
2964 SDNode *Use = *N->use_begin();
2965 if (Use->getOpcode() == ISD::BRCOND)
2967 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
2968 // Also look pass the truncate.
2969 Use = *Use->use_begin();
2970 if (Use->getOpcode() == ISD::BRCOND)
2975 return PromoteIntBinOp(SDValue(N, 0));
2978 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
2979 SDValue N0 = N->getOperand(0);
2980 EVT VT = N->getValueType(0);
2982 // fold (ctlz c1) -> c2
2983 if (isa<ConstantSDNode>(N0))
2984 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
2988 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
2989 SDValue N0 = N->getOperand(0);
2990 EVT VT = N->getValueType(0);
2992 // fold (cttz c1) -> c2
2993 if (isa<ConstantSDNode>(N0))
2994 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
2998 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
2999 SDValue N0 = N->getOperand(0);
3000 EVT VT = N->getValueType(0);
3002 // fold (ctpop c1) -> c2
3003 if (isa<ConstantSDNode>(N0))
3004 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3008 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3009 SDValue N0 = N->getOperand(0);
3010 SDValue N1 = N->getOperand(1);
3011 SDValue N2 = N->getOperand(2);
3012 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3013 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3014 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3015 EVT VT = N->getValueType(0);
3016 EVT VT0 = N0.getValueType();
3018 // fold (select C, X, X) -> X
3021 // fold (select true, X, Y) -> X
3022 if (N0C && !N0C->isNullValue())
3024 // fold (select false, X, Y) -> Y
3025 if (N0C && N0C->isNullValue())
3027 // fold (select C, 1, X) -> (or C, X)
3028 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3029 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3030 // fold (select C, 0, 1) -> (xor C, 1)
3031 if (VT.isInteger() &&
3034 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
3035 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3038 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3039 N0, DAG.getConstant(1, VT0));
3040 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3041 N0, DAG.getConstant(1, VT0));
3042 AddToWorkList(XORNode.getNode());
3044 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3045 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3047 // fold (select C, 0, X) -> (and (not C), X)
3048 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3049 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3050 AddToWorkList(NOTNode.getNode());
3051 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3053 // fold (select C, X, 1) -> (or (not C), X)
3054 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3055 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3056 AddToWorkList(NOTNode.getNode());
3057 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3059 // fold (select C, X, 0) -> (and C, X)
3060 if (VT == MVT::i1 && N2C && N2C->isNullValue())
3061 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3062 // fold (select X, X, Y) -> (or X, Y)
3063 // fold (select X, 1, Y) -> (or X, Y)
3064 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3065 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3066 // fold (select X, Y, X) -> (and X, Y)
3067 // fold (select X, Y, 0) -> (and X, Y)
3068 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3069 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3071 // If we can fold this based on the true/false value, do so.
3072 if (SimplifySelectOps(N, N1, N2))
3073 return SDValue(N, 0); // Don't revisit N.
3075 // fold selects based on a setcc into other things, such as min/max/abs
3076 if (N0.getOpcode() == ISD::SETCC) {
3078 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3079 // having to say they don't support SELECT_CC on every type the DAG knows
3080 // about, since there is no way to mark an opcode illegal at all value types
3081 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3082 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3083 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3084 N0.getOperand(0), N0.getOperand(1),
3085 N1, N2, N0.getOperand(2));
3086 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3092 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3093 SDValue N0 = N->getOperand(0);
3094 SDValue N1 = N->getOperand(1);
3095 SDValue N2 = N->getOperand(2);
3096 SDValue N3 = N->getOperand(3);
3097 SDValue N4 = N->getOperand(4);
3098 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3100 // fold select_cc lhs, rhs, x, x, cc -> x
3104 // Determine if the condition we're dealing with is constant
3105 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3106 N0, N1, CC, N->getDebugLoc(), false);
3107 if (SCC.getNode()) AddToWorkList(SCC.getNode());
3109 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3110 if (!SCCC->isNullValue())
3111 return N2; // cond always true -> true val
3113 return N3; // cond always false -> false val
3116 // Fold to a simpler select_cc
3117 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3118 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3119 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3122 // If we can fold this based on the true/false value, do so.
3123 if (SimplifySelectOps(N, N2, N3))
3124 return SDValue(N, 0); // Don't revisit N.
3126 // fold select_cc into other things, such as min/max/abs
3127 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3130 SDValue DAGCombiner::visitSETCC(SDNode *N) {
3131 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3132 cast<CondCodeSDNode>(N->getOperand(2))->get(),
3136 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3137 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3138 // transformation. Returns true if extension are possible and the above
3139 // mentioned transformation is profitable.
3140 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3142 SmallVector<SDNode*, 4> &ExtendNodes,
3143 const TargetLowering &TLI) {
3144 bool HasCopyToRegUses = false;
3145 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3146 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3147 UE = N0.getNode()->use_end();
3152 if (UI.getUse().getResNo() != N0.getResNo())
3154 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3155 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3156 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3157 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3158 // Sign bits will be lost after a zext.
3161 for (unsigned i = 0; i != 2; ++i) {
3162 SDValue UseOp = User->getOperand(i);
3165 if (!isa<ConstantSDNode>(UseOp))
3170 ExtendNodes.push_back(User);
3173 // If truncates aren't free and there are users we can't
3174 // extend, it isn't worthwhile.
3177 // Remember if this value is live-out.
3178 if (User->getOpcode() == ISD::CopyToReg)
3179 HasCopyToRegUses = true;
3182 if (HasCopyToRegUses) {
3183 bool BothLiveOut = false;
3184 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3186 SDUse &Use = UI.getUse();
3187 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3193 // Both unextended and extended values are live out. There had better be
3194 // good a reason for the transformation.
3195 return ExtendNodes.size();
3200 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3201 SDValue N0 = N->getOperand(0);
3202 EVT VT = N->getValueType(0);
3204 // fold (sext c1) -> c1
3205 if (isa<ConstantSDNode>(N0))
3206 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3208 // fold (sext (sext x)) -> (sext x)
3209 // fold (sext (aext x)) -> (sext x)
3210 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3211 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3214 if (N0.getOpcode() == ISD::TRUNCATE) {
3215 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3216 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3217 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3218 if (NarrowLoad.getNode()) {
3219 if (NarrowLoad.getNode() != N0.getNode())
3220 CombineTo(N0.getNode(), NarrowLoad);
3221 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3224 // See if the value being truncated is already sign extended. If so, just
3225 // eliminate the trunc/sext pair.
3226 SDValue Op = N0.getOperand(0);
3227 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
3228 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
3229 unsigned DestBits = VT.getScalarType().getSizeInBits();
3230 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3232 if (OpBits == DestBits) {
3233 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3234 // bits, it is already ready.
3235 if (NumSignBits > DestBits-MidBits)
3237 } else if (OpBits < DestBits) {
3238 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3239 // bits, just sext from i32.
3240 if (NumSignBits > OpBits-MidBits)
3241 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3243 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3244 // bits, just truncate to i32.
3245 if (NumSignBits > OpBits-MidBits)
3246 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3249 // fold (sext (truncate x)) -> (sextinreg x).
3250 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
3251 N0.getValueType())) {
3252 if (OpBits < DestBits)
3253 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
3254 else if (OpBits > DestBits)
3255 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
3256 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
3257 DAG.getValueType(N0.getValueType()));
3261 // fold (sext (load x)) -> (sext (truncate (sextload x)))
3262 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3263 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3264 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
3265 bool DoXform = true;
3266 SmallVector<SDNode*, 4> SetCCs;
3267 if (!N0.hasOneUse())
3268 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
3270 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3271 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3273 LN0->getBasePtr(), LN0->getSrcValue(),
3274 LN0->getSrcValueOffset(),
3276 LN0->isVolatile(), LN0->isNonTemporal(),
3277 LN0->getAlignment());
3278 CombineTo(N, ExtLoad);
3279 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3280 N0.getValueType(), ExtLoad);
3281 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3283 // Extend SetCC uses if necessary.
3284 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3285 SDNode *SetCC = SetCCs[i];
3286 SmallVector<SDValue, 4> Ops;
3288 for (unsigned j = 0; j != 2; ++j) {
3289 SDValue SOp = SetCC->getOperand(j);
3291 Ops.push_back(ExtLoad);
3293 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND,
3294 N->getDebugLoc(), VT, SOp));
3297 Ops.push_back(SetCC->getOperand(2));
3298 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3299 SetCC->getValueType(0),
3300 &Ops[0], Ops.size()));
3303 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3307 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
3308 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
3309 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3310 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3311 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3312 EVT MemVT = LN0->getMemoryVT();
3313 if ((!LegalOperations && !LN0->isVolatile()) ||
3314 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
3315 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3317 LN0->getBasePtr(), LN0->getSrcValue(),
3318 LN0->getSrcValueOffset(), MemVT,
3319 LN0->isVolatile(), LN0->isNonTemporal(),
3320 LN0->getAlignment());
3321 CombineTo(N, ExtLoad);
3322 CombineTo(N0.getNode(),
3323 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3324 N0.getValueType(), ExtLoad),
3325 ExtLoad.getValue(1));
3326 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3330 if (N0.getOpcode() == ISD::SETCC) {
3331 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
3332 if (VT.isVector() &&
3333 // We know that the # elements of the results is the same as the
3334 // # elements of the compare (and the # elements of the compare result
3335 // for that matter). Check to see that they are the same size. If so,
3336 // we know that the element size of the sext'd result matches the
3337 // element size of the compare operands.
3338 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() &&
3340 // Only do this before legalize for now.
3342 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
3344 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3347 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
3349 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
3351 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3352 NegOne, DAG.getConstant(0, VT),
3353 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3354 if (SCC.getNode()) return SCC;
3355 if (!LegalOperations ||
3356 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
3357 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3358 DAG.getSetCC(N->getDebugLoc(),
3359 TLI.getSetCCResultType(VT),
3360 N0.getOperand(0), N0.getOperand(1),
3361 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
3362 NegOne, DAG.getConstant(0, VT));
3367 // fold (sext x) -> (zext x) if the sign bit is known zero.
3368 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
3369 DAG.SignBitIsZero(N0))
3370 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3375 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
3376 SDValue N0 = N->getOperand(0);
3377 EVT VT = N->getValueType(0);
3379 // fold (zext c1) -> c1
3380 if (isa<ConstantSDNode>(N0))
3381 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
3382 // fold (zext (zext x)) -> (zext x)
3383 // fold (zext (aext x)) -> (zext x)
3384 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3385 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
3388 // fold (zext (truncate (load x))) -> (zext (smaller load x))
3389 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
3390 if (N0.getOpcode() == ISD::TRUNCATE) {
3391 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3392 if (NarrowLoad.getNode()) {
3393 if (NarrowLoad.getNode() != N0.getNode())
3394 CombineTo(N0.getNode(), NarrowLoad);
3395 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3399 // fold (zext (truncate x)) -> (and x, mask)
3400 if (N0.getOpcode() == ISD::TRUNCATE &&
3401 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) &&
3402 (!TLI.isTruncateFree(N0.getOperand(0).getValueType(),
3403 N0.getValueType()) ||
3404 !TLI.isZExtFree(N0.getValueType(), VT))) {
3405 SDValue Op = N0.getOperand(0);
3406 if (Op.getValueType().bitsLT(VT)) {
3407 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
3408 } else if (Op.getValueType().bitsGT(VT)) {
3409 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
3411 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
3412 N0.getValueType().getScalarType());
3415 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
3416 // if either of the casts is not free.
3417 if (N0.getOpcode() == ISD::AND &&
3418 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3419 N0.getOperand(1).getOpcode() == ISD::Constant &&
3420 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3421 N0.getValueType()) ||
3422 !TLI.isZExtFree(N0.getValueType(), VT))) {
3423 SDValue X = N0.getOperand(0).getOperand(0);
3424 if (X.getValueType().bitsLT(VT)) {
3425 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
3426 } else if (X.getValueType().bitsGT(VT)) {
3427 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
3429 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3430 Mask.zext(VT.getSizeInBits());
3431 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3432 X, DAG.getConstant(Mask, VT));
3435 // fold (zext (load x)) -> (zext (truncate (zextload x)))
3436 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3437 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3438 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
3439 bool DoXform = true;
3440 SmallVector<SDNode*, 4> SetCCs;
3441 if (!N0.hasOneUse())
3442 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
3444 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3445 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3447 LN0->getBasePtr(), LN0->getSrcValue(),
3448 LN0->getSrcValueOffset(),
3450 LN0->isVolatile(), LN0->isNonTemporal(),
3451 LN0->getAlignment());
3452 CombineTo(N, ExtLoad);
3453 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3454 N0.getValueType(), ExtLoad);
3455 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3457 // Extend SetCC uses if necessary.
3458 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3459 SDNode *SetCC = SetCCs[i];
3460 SmallVector<SDValue, 4> Ops;
3462 for (unsigned j = 0; j != 2; ++j) {
3463 SDValue SOp = SetCC->getOperand(j);
3465 Ops.push_back(ExtLoad);
3467 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND,
3468 N->getDebugLoc(), VT, SOp));
3471 Ops.push_back(SetCC->getOperand(2));
3472 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3473 SetCC->getValueType(0),
3474 &Ops[0], Ops.size()));
3477 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3481 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
3482 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
3483 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
3484 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
3485 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3486 EVT MemVT = LN0->getMemoryVT();
3487 if ((!LegalOperations && !LN0->isVolatile()) ||
3488 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
3489 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
3491 LN0->getBasePtr(), LN0->getSrcValue(),
3492 LN0->getSrcValueOffset(), MemVT,
3493 LN0->isVolatile(), LN0->isNonTemporal(),
3494 LN0->getAlignment());
3495 CombineTo(N, ExtLoad);
3496 CombineTo(N0.getNode(),
3497 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
3499 ExtLoad.getValue(1));
3500 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3504 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3505 if (N0.getOpcode() == ISD::SETCC) {
3507 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3508 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3509 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3510 if (SCC.getNode()) return SCC;
3513 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
3514 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
3515 isa<ConstantSDNode>(N0.getOperand(1)) &&
3516 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
3518 if (N0.getOpcode() == ISD::SHL) {
3519 // If the original shl may be shifting out bits, do not perform this
3521 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3522 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() -
3523 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits();
3524 if (ShAmt > KnownZeroBits)
3527 DebugLoc dl = N->getDebugLoc();
3528 return DAG.getNode(N0.getOpcode(), dl, VT,
3529 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)),
3530 DAG.getNode(ISD::ZERO_EXTEND, dl,
3531 N0.getOperand(1).getValueType(),
3538 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
3539 SDValue N0 = N->getOperand(0);
3540 EVT VT = N->getValueType(0);
3542 // fold (aext c1) -> c1
3543 if (isa<ConstantSDNode>(N0))
3544 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
3545 // fold (aext (aext x)) -> (aext x)
3546 // fold (aext (zext x)) -> (zext x)
3547 // fold (aext (sext x)) -> (sext x)
3548 if (N0.getOpcode() == ISD::ANY_EXTEND ||
3549 N0.getOpcode() == ISD::ZERO_EXTEND ||
3550 N0.getOpcode() == ISD::SIGN_EXTEND)
3551 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
3553 // fold (aext (truncate (load x))) -> (aext (smaller load x))
3554 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
3555 if (N0.getOpcode() == ISD::TRUNCATE) {
3556 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3557 if (NarrowLoad.getNode()) {
3558 if (NarrowLoad.getNode() != N0.getNode())
3559 CombineTo(N0.getNode(), NarrowLoad);
3560 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad);
3564 // fold (aext (truncate x))
3565 if (N0.getOpcode() == ISD::TRUNCATE) {
3566 SDValue TruncOp = N0.getOperand(0);
3567 if (TruncOp.getValueType() == VT)
3568 return TruncOp; // x iff x size == zext size.
3569 if (TruncOp.getValueType().bitsGT(VT))
3570 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
3571 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
3574 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
3575 // if the trunc is not free.
3576 if (N0.getOpcode() == ISD::AND &&
3577 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
3578 N0.getOperand(1).getOpcode() == ISD::Constant &&
3579 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
3580 N0.getValueType())) {
3581 SDValue X = N0.getOperand(0).getOperand(0);
3582 if (X.getValueType().bitsLT(VT)) {
3583 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
3584 } else if (X.getValueType().bitsGT(VT)) {
3585 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
3587 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
3588 Mask.zext(VT.getSizeInBits());
3589 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
3590 X, DAG.getConstant(Mask, VT));
3593 // fold (aext (load x)) -> (aext (truncate (extload x)))
3594 if (ISD::isNON_EXTLoad(N0.getNode()) &&
3595 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3596 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
3597 bool DoXform = true;
3598 SmallVector<SDNode*, 4> SetCCs;
3599 if (!N0.hasOneUse())
3600 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
3602 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3603 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
3605 LN0->getBasePtr(), LN0->getSrcValue(),
3606 LN0->getSrcValueOffset(),
3608 LN0->isVolatile(), LN0->isNonTemporal(),
3609 LN0->getAlignment());
3610 CombineTo(N, ExtLoad);
3611 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3612 N0.getValueType(), ExtLoad);
3613 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
3615 // Extend SetCC uses if necessary.
3616 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3617 SDNode *SetCC = SetCCs[i];
3618 SmallVector<SDValue, 4> Ops;
3620 for (unsigned j = 0; j != 2; ++j) {
3621 SDValue SOp = SetCC->getOperand(j);
3623 Ops.push_back(ExtLoad);
3625 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND,
3626 N->getDebugLoc(), VT, SOp));
3629 Ops.push_back(SetCC->getOperand(2));
3630 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(),
3631 SetCC->getValueType(0),
3632 &Ops[0], Ops.size()));
3635 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3639 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
3640 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
3641 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
3642 if (N0.getOpcode() == ISD::LOAD &&
3643 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3645 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3646 EVT MemVT = LN0->getMemoryVT();
3647 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
3648 VT, LN0->getChain(), LN0->getBasePtr(),
3650 LN0->getSrcValueOffset(), MemVT,
3651 LN0->isVolatile(), LN0->isNonTemporal(),
3652 LN0->getAlignment());
3653 CombineTo(N, ExtLoad);
3654 CombineTo(N0.getNode(),
3655 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
3656 N0.getValueType(), ExtLoad),
3657 ExtLoad.getValue(1));
3658 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3661 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
3662 if (N0.getOpcode() == ISD::SETCC) {
3664 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
3665 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3666 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
3674 /// GetDemandedBits - See if the specified operand can be simplified with the
3675 /// knowledge that only the bits specified by Mask are used. If so, return the
3676 /// simpler operand, otherwise return a null SDValue.
3677 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
3678 switch (V.getOpcode()) {
3682 // If the LHS or RHS don't contribute bits to the or, drop them.
3683 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
3684 return V.getOperand(1);
3685 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
3686 return V.getOperand(0);
3689 // Only look at single-use SRLs.
3690 if (!V.getNode()->hasOneUse())
3692 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
3693 // See if we can recursively simplify the LHS.
3694 unsigned Amt = RHSC->getZExtValue();
3696 // Watch out for shift count overflow though.
3697 if (Amt >= Mask.getBitWidth()) break;
3698 APInt NewMask = Mask << Amt;
3699 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
3700 if (SimplifyLHS.getNode())
3701 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
3702 SimplifyLHS, V.getOperand(1));
3708 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
3709 /// bits and then truncated to a narrower type and where N is a multiple
3710 /// of number of bits of the narrower type, transform it to a narrower load
3711 /// from address + N / num of bits of new type. If the result is to be
3712 /// extended, also fold the extension to form a extending load.
3713 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
3714 unsigned Opc = N->getOpcode();
3715 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
3716 SDValue N0 = N->getOperand(0);
3717 EVT VT = N->getValueType(0);
3720 // This transformation isn't valid for vector loads.
3724 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
3726 if (Opc == ISD::SIGN_EXTEND_INREG) {
3727 ExtType = ISD::SEXTLOAD;
3728 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3729 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
3733 unsigned EVTBits = ExtVT.getSizeInBits();
3735 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) {
3736 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3737 ShAmt = N01->getZExtValue();
3738 // Is the shift amount a multiple of size of VT?
3739 if ((ShAmt & (EVTBits-1)) == 0) {
3740 N0 = N0.getOperand(0);
3741 // Is the load width a multiple of size of VT?
3742 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
3748 // Do not generate loads of non-round integer types since these can
3749 // be expensive (and would be wrong if the type is not byte sized).
3750 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() &&
3751 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() >= EVTBits &&
3752 // Do not change the width of a volatile load.
3753 !cast<LoadSDNode>(N0)->isVolatile()) {
3754 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3755 EVT PtrType = N0.getOperand(1).getValueType();
3757 // For big endian targets, we need to adjust the offset to the pointer to
3758 // load the correct bytes.
3759 if (TLI.isBigEndian()) {
3760 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
3761 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
3762 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
3765 uint64_t PtrOff = ShAmt / 8;
3766 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
3767 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
3768 PtrType, LN0->getBasePtr(),
3769 DAG.getConstant(PtrOff, PtrType));
3770 AddToWorkList(NewPtr.getNode());
3772 SDValue Load = (ExtType == ISD::NON_EXTLOAD)
3773 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
3774 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3775 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign)
3776 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
3777 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
3778 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
3781 // Replace the old load's chain with the new load's chain.
3782 WorkListRemover DeadNodes(*this);
3783 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
3786 // Return the new loaded value.
3793 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
3794 SDValue N0 = N->getOperand(0);
3795 SDValue N1 = N->getOperand(1);
3796 EVT VT = N->getValueType(0);
3797 EVT EVT = cast<VTSDNode>(N1)->getVT();
3798 unsigned VTBits = VT.getScalarType().getSizeInBits();
3799 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
3801 // fold (sext_in_reg c1) -> c1
3802 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
3803 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
3805 // If the input is already sign extended, just drop the extension.
3806 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
3809 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
3810 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3811 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
3812 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3813 N0.getOperand(0), N1);
3816 // fold (sext_in_reg (sext x)) -> (sext x)
3817 // fold (sext_in_reg (aext x)) -> (sext x)
3818 // if x is small enough.
3819 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
3820 SDValue N00 = N0.getOperand(0);
3821 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
3822 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
3823 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
3826 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
3827 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
3828 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
3830 // fold operands of sext_in_reg based on knowledge that the top bits are not
3832 if (SimplifyDemandedBits(SDValue(N, 0)))
3833 return SDValue(N, 0);
3835 // fold (sext_in_reg (load x)) -> (smaller sextload x)
3836 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
3837 SDValue NarrowLoad = ReduceLoadWidth(N);
3838 if (NarrowLoad.getNode())
3841 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
3842 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
3843 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
3844 if (N0.getOpcode() == ISD::SRL) {
3845 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
3846 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
3847 // We can turn this into an SRA iff the input to the SRL is already sign
3849 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3850 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
3851 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
3852 N0.getOperand(0), N0.getOperand(1));
3856 // fold (sext_inreg (extload x)) -> (sextload x)
3857 if (ISD::isEXTLoad(N0.getNode()) &&
3858 ISD::isUNINDEXEDLoad(N0.getNode()) &&
3859 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3860 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3861 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3862 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3863 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3865 LN0->getBasePtr(), LN0->getSrcValue(),
3866 LN0->getSrcValueOffset(), EVT,
3867 LN0->isVolatile(), LN0->isNonTemporal(),
3868 LN0->getAlignment());
3869 CombineTo(N, ExtLoad);
3870 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3871 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3873 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
3874 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3876 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
3877 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
3878 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
3879 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3880 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
3882 LN0->getBasePtr(), LN0->getSrcValue(),
3883 LN0->getSrcValueOffset(), EVT,
3884 LN0->isVolatile(), LN0->isNonTemporal(),
3885 LN0->getAlignment());
3886 CombineTo(N, ExtLoad);
3887 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3888 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3893 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
3894 SDValue N0 = N->getOperand(0);
3895 EVT VT = N->getValueType(0);
3898 if (N0.getValueType() == N->getValueType(0))
3900 // fold (truncate c1) -> c1
3901 if (isa<ConstantSDNode>(N0))
3902 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
3903 // fold (truncate (truncate x)) -> (truncate x)
3904 if (N0.getOpcode() == ISD::TRUNCATE)
3905 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3906 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
3907 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
3908 N0.getOpcode() == ISD::SIGN_EXTEND ||
3909 N0.getOpcode() == ISD::ANY_EXTEND) {
3910 if (N0.getOperand(0).getValueType().bitsLT(VT))
3911 // if the source is smaller than the dest, we still need an extend
3912 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
3914 else if (N0.getOperand(0).getValueType().bitsGT(VT))
3915 // if the source is larger than the dest, than we just need the truncate
3916 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
3918 // if the source and dest are the same type, we can drop both the extend
3919 // and the truncate.
3920 return N0.getOperand(0);
3923 // See if we can simplify the input to this truncate through knowledge that
3924 // only the low bits are being used. For example "trunc (or (shl x, 8), y)"
3927 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3928 VT.getSizeInBits()));
3929 if (Shorter.getNode())
3930 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
3932 // fold (truncate (load x)) -> (smaller load x)
3933 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
3934 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT))
3935 return ReduceLoadWidth(N);
3939 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
3940 SDValue Elt = N->getOperand(i);
3941 if (Elt.getOpcode() != ISD::MERGE_VALUES)
3942 return Elt.getNode();
3943 return Elt.getOperand(Elt.getResNo()).getNode();
3946 /// CombineConsecutiveLoads - build_pair (load, load) -> load
3947 /// if load locations are consecutive.
3948 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
3949 assert(N->getOpcode() == ISD::BUILD_PAIR);
3951 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
3952 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
3953 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
3955 EVT LD1VT = LD1->getValueType(0);
3957 if (ISD::isNON_EXTLoad(LD2) &&
3959 // If both are volatile this would reduce the number of volatile loads.
3960 // If one is volatile it might be ok, but play conservative and bail out.
3961 !LD1->isVolatile() &&
3962 !LD2->isVolatile() &&
3963 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
3964 unsigned Align = LD1->getAlignment();
3965 unsigned NewAlign = TLI.getTargetData()->
3966 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
3968 if (NewAlign <= Align &&
3969 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
3970 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
3971 LD1->getBasePtr(), LD1->getSrcValue(),
3972 LD1->getSrcValueOffset(), false, false, Align);
3978 SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
3979 SDValue N0 = N->getOperand(0);
3980 EVT VT = N->getValueType(0);
3982 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
3983 // Only do this before legalize, since afterward the target may be depending
3984 // on the bitconvert.
3985 // First check to see if this is all constant.
3987 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
3989 bool isSimple = true;
3990 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
3991 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
3992 N0.getOperand(i).getOpcode() != ISD::Constant &&
3993 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
3998 EVT DestEltVT = N->getValueType(0).getVectorElementType();
3999 assert(!DestEltVT.isVector() &&
4000 "Element type of vector ValueType must not be vector!");
4002 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT);
4005 // If the input is a constant, let getNode fold it.
4006 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
4007 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0);
4008 if (Res.getNode() != N) {
4009 if (!LegalOperations ||
4010 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
4013 // Folding it resulted in an illegal node, and it's too late to
4014 // do that. Clean up the old node and forego the transformation.
4015 // Ideally this won't happen very often, because instcombine
4016 // and the earlier dagcombine runs (where illegal nodes are
4017 // permitted) should have folded most of them already.
4018 DAG.DeleteNode(Res.getNode());
4022 // (conv (conv x, t1), t2) -> (conv x, t2)
4023 if (N0.getOpcode() == ISD::BIT_CONVERT)
4024 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT,
4027 // fold (conv (load x)) -> (load (conv*)x)
4028 // If the resultant load doesn't need a higher alignment than the original!
4029 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
4030 // Do not change the width of a volatile load.
4031 !cast<LoadSDNode>(N0)->isVolatile() &&
4032 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
4033 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4034 unsigned Align = TLI.getTargetData()->
4035 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4036 unsigned OrigAlign = LN0->getAlignment();
4038 if (Align <= OrigAlign) {
4039 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
4041 LN0->getSrcValue(), LN0->getSrcValueOffset(),
4042 LN0->isVolatile(), LN0->isNonTemporal(),
4045 CombineTo(N0.getNode(),
4046 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4047 N0.getValueType(), Load),
4053 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
4054 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
4055 // This often reduces constant pool loads.
4056 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
4057 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
4058 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT,
4060 AddToWorkList(NewConv.getNode());
4062 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4063 if (N0.getOpcode() == ISD::FNEG)
4064 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
4065 NewConv, DAG.getConstant(SignBit, VT));
4066 assert(N0.getOpcode() == ISD::FABS);
4067 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4068 NewConv, DAG.getConstant(~SignBit, VT));
4071 // fold (bitconvert (fcopysign cst, x)) ->
4072 // (or (and (bitconvert x), sign), (and cst, (not sign)))
4073 // Note that we don't handle (copysign x, cst) because this can always be
4074 // folded to an fneg or fabs.
4075 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
4076 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
4077 VT.isInteger() && !VT.isVector()) {
4078 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
4079 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
4080 if (isTypeLegal(IntXVT)) {
4081 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4082 IntXVT, N0.getOperand(1));
4083 AddToWorkList(X.getNode());
4085 // If X has a different width than the result/lhs, sext it or truncate it.
4086 unsigned VTWidth = VT.getSizeInBits();
4087 if (OrigXWidth < VTWidth) {
4088 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
4089 AddToWorkList(X.getNode());
4090 } else if (OrigXWidth > VTWidth) {
4091 // To get the sign bit in the right place, we have to shift it right
4092 // before truncating.
4093 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
4094 X.getValueType(), X,
4095 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
4096 AddToWorkList(X.getNode());
4097 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4098 AddToWorkList(X.getNode());
4101 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
4102 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
4103 X, DAG.getConstant(SignBit, VT));
4104 AddToWorkList(X.getNode());
4106 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
4107 VT, N0.getOperand(0));
4108 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
4109 Cst, DAG.getConstant(~SignBit, VT));
4110 AddToWorkList(Cst.getNode());
4112 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
4116 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
4117 if (N0.getOpcode() == ISD::BUILD_PAIR) {
4118 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
4119 if (CombineLD.getNode())
4126 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
4127 EVT VT = N->getValueType(0);
4128 return CombineConsecutiveLoads(N, VT);
4131 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
4132 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
4133 /// destination element value type.
4134 SDValue DAGCombiner::
4135 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
4136 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
4138 // If this is already the right type, we're done.
4139 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
4141 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
4142 unsigned DstBitSize = DstEltVT.getSizeInBits();
4144 // If this is a conversion of N elements of one type to N elements of another
4145 // type, convert each element. This handles FP<->INT cases.
4146 if (SrcBitSize == DstBitSize) {
4147 SmallVector<SDValue, 8> Ops;
4148 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4149 SDValue Op = BV->getOperand(i);
4150 // If the vector element type is not legal, the BUILD_VECTOR operands
4151 // are promoted and implicitly truncated. Make that explicit here.
4152 if (Op.getValueType() != SrcEltVT)
4153 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
4154 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(),
4156 AddToWorkList(Ops.back().getNode());
4158 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4159 BV->getValueType(0).getVectorNumElements());
4160 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4161 &Ops[0], Ops.size());
4164 // Otherwise, we're growing or shrinking the elements. To avoid having to
4165 // handle annoying details of growing/shrinking FP values, we convert them to
4167 if (SrcEltVT.isFloatingPoint()) {
4168 // Convert the input float vector to a int vector where the elements are the
4170 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
4171 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
4172 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
4176 // Now we know the input is an integer vector. If the output is a FP type,
4177 // convert to integer first, then to FP of the right size.
4178 if (DstEltVT.isFloatingPoint()) {
4179 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
4180 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
4181 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
4183 // Next, convert to FP elements of the same size.
4184 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
4187 // Okay, we know the src/dst types are both integers of differing types.
4188 // Handling growing first.
4189 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
4190 if (SrcBitSize < DstBitSize) {
4191 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
4193 SmallVector<SDValue, 8> Ops;
4194 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
4195 i += NumInputsPerOutput) {
4196 bool isLE = TLI.isLittleEndian();
4197 APInt NewBits = APInt(DstBitSize, 0);
4198 bool EltIsUndef = true;
4199 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
4200 // Shift the previously computed bits over.
4201 NewBits <<= SrcBitSize;
4202 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
4203 if (Op.getOpcode() == ISD::UNDEF) continue;
4206 NewBits |= APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).
4207 zextOrTrunc(SrcBitSize).zext(DstBitSize);
4211 Ops.push_back(DAG.getUNDEF(DstEltVT));
4213 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
4216 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
4217 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4218 &Ops[0], Ops.size());
4221 // Finally, this must be the case where we are shrinking elements: each input
4222 // turns into multiple outputs.
4223 bool isS2V = ISD::isScalarToVector(BV);
4224 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
4225 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
4226 NumOutputsPerInput*BV->getNumOperands());
4227 SmallVector<SDValue, 8> Ops;
4229 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
4230 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
4231 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
4232 Ops.push_back(DAG.getUNDEF(DstEltVT));
4236 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))->
4237 getAPIntValue()).zextOrTrunc(SrcBitSize);
4239 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
4240 APInt ThisVal = APInt(OpVal).trunc(DstBitSize);
4241 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
4242 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal)
4243 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
4244 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
4246 OpVal = OpVal.lshr(DstBitSize);
4249 // For big endian targets, swap the order of the pieces of each element.
4250 if (TLI.isBigEndian())
4251 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
4254 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
4255 &Ops[0], Ops.size());
4258 SDValue DAGCombiner::visitFADD(SDNode *N) {
4259 SDValue N0 = N->getOperand(0);
4260 SDValue N1 = N->getOperand(1);
4261 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4262 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4263 EVT VT = N->getValueType(0);
4266 if (VT.isVector()) {
4267 SDValue FoldedVOp = SimplifyVBinOp(N);
4268 if (FoldedVOp.getNode()) return FoldedVOp;
4271 // fold (fadd c1, c2) -> (fadd c1, c2)
4272 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4273 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
4274 // canonicalize constant to RHS
4275 if (N0CFP && !N1CFP)
4276 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
4277 // fold (fadd A, 0) -> A
4278 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4280 // fold (fadd A, (fneg B)) -> (fsub A, B)
4281 if (isNegatibleForFree(N1, LegalOperations) == 2)
4282 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
4283 GetNegatedExpression(N1, DAG, LegalOperations));
4284 // fold (fadd (fneg A), B) -> (fsub B, A)
4285 if (isNegatibleForFree(N0, LegalOperations) == 2)
4286 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
4287 GetNegatedExpression(N0, DAG, LegalOperations));
4289 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
4290 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
4291 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4292 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
4293 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
4294 N0.getOperand(1), N1));
4299 SDValue DAGCombiner::visitFSUB(SDNode *N) {
4300 SDValue N0 = N->getOperand(0);
4301 SDValue N1 = N->getOperand(1);
4302 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4303 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4304 EVT VT = N->getValueType(0);
4307 if (VT.isVector()) {
4308 SDValue FoldedVOp = SimplifyVBinOp(N);
4309 if (FoldedVOp.getNode()) return FoldedVOp;
4312 // fold (fsub c1, c2) -> c1-c2
4313 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4314 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
4315 // fold (fsub A, 0) -> A
4316 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4318 // fold (fsub 0, B) -> -B
4319 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
4320 if (isNegatibleForFree(N1, LegalOperations))
4321 return GetNegatedExpression(N1, DAG, LegalOperations);
4322 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4323 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
4325 // fold (fsub A, (fneg B)) -> (fadd A, B)
4326 if (isNegatibleForFree(N1, LegalOperations))
4327 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
4328 GetNegatedExpression(N1, DAG, LegalOperations));
4333 SDValue DAGCombiner::visitFMUL(SDNode *N) {
4334 SDValue N0 = N->getOperand(0);
4335 SDValue N1 = N->getOperand(1);
4336 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4337 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4338 EVT VT = N->getValueType(0);
4341 if (VT.isVector()) {
4342 SDValue FoldedVOp = SimplifyVBinOp(N);
4343 if (FoldedVOp.getNode()) return FoldedVOp;
4346 // fold (fmul c1, c2) -> c1*c2
4347 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4348 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
4349 // canonicalize constant to RHS
4350 if (N0CFP && !N1CFP)
4351 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
4352 // fold (fmul A, 0) -> 0
4353 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
4355 // fold (fmul A, 0) -> 0, vector edition.
4356 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
4358 // fold (fmul X, 2.0) -> (fadd X, X)
4359 if (N1CFP && N1CFP->isExactlyValue(+2.0))
4360 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
4361 // fold (fmul X, -1.0) -> (fneg X)
4362 if (N1CFP && N1CFP->isExactlyValue(-1.0))
4363 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4364 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
4366 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
4367 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4368 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4369 // Both can be negated for free, check to see if at least one is cheaper
4371 if (LHSNeg == 2 || RHSNeg == 2)
4372 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4373 GetNegatedExpression(N0, DAG, LegalOperations),
4374 GetNegatedExpression(N1, DAG, LegalOperations));
4378 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
4379 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
4380 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
4381 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
4382 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
4383 N0.getOperand(1), N1));
4388 SDValue DAGCombiner::visitFDIV(SDNode *N) {
4389 SDValue N0 = N->getOperand(0);
4390 SDValue N1 = N->getOperand(1);
4391 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4392 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4393 EVT VT = N->getValueType(0);
4396 if (VT.isVector()) {
4397 SDValue FoldedVOp = SimplifyVBinOp(N);
4398 if (FoldedVOp.getNode()) return FoldedVOp;
4401 // fold (fdiv c1, c2) -> c1/c2
4402 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4403 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
4406 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
4407 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
4408 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
4409 // Both can be negated for free, check to see if at least one is cheaper
4411 if (LHSNeg == 2 || RHSNeg == 2)
4412 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
4413 GetNegatedExpression(N0, DAG, LegalOperations),
4414 GetNegatedExpression(N1, DAG, LegalOperations));
4421 SDValue DAGCombiner::visitFREM(SDNode *N) {
4422 SDValue N0 = N->getOperand(0);
4423 SDValue N1 = N->getOperand(1);
4424 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4425 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4426 EVT VT = N->getValueType(0);
4428 // fold (frem c1, c2) -> fmod(c1,c2)
4429 if (N0CFP && N1CFP && VT != MVT::ppcf128)
4430 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
4435 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
4436 SDValue N0 = N->getOperand(0);
4437 SDValue N1 = N->getOperand(1);
4438 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4439 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
4440 EVT VT = N->getValueType(0);
4442 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
4443 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
4446 const APFloat& V = N1CFP->getValueAPF();
4447 // copysign(x, c1) -> fabs(x) iff ispos(c1)
4448 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
4449 if (!V.isNegative()) {
4450 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
4451 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4453 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
4454 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
4455 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
4459 // copysign(fabs(x), y) -> copysign(x, y)
4460 // copysign(fneg(x), y) -> copysign(x, y)
4461 // copysign(copysign(x,z), y) -> copysign(x, y)
4462 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
4463 N0.getOpcode() == ISD::FCOPYSIGN)
4464 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4465 N0.getOperand(0), N1);
4467 // copysign(x, abs(y)) -> abs(x)
4468 if (N1.getOpcode() == ISD::FABS)
4469 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4471 // copysign(x, copysign(y,z)) -> copysign(x, z)
4472 if (N1.getOpcode() == ISD::FCOPYSIGN)
4473 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4474 N0, N1.getOperand(1));
4476 // copysign(x, fp_extend(y)) -> copysign(x, y)
4477 // copysign(x, fp_round(y)) -> copysign(x, y)
4478 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
4479 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4480 N0, N1.getOperand(0));
4485 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
4486 SDValue N0 = N->getOperand(0);
4487 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4488 EVT VT = N->getValueType(0);
4489 EVT OpVT = N0.getValueType();
4491 // fold (sint_to_fp c1) -> c1fp
4492 if (N0C && OpVT != MVT::ppcf128)
4493 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4495 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
4496 // but UINT_TO_FP is legal on this target, try to convert.
4497 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
4498 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
4499 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
4500 if (DAG.SignBitIsZero(N0))
4501 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4507 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
4508 SDValue N0 = N->getOperand(0);
4509 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
4510 EVT VT = N->getValueType(0);
4511 EVT OpVT = N0.getValueType();
4513 // fold (uint_to_fp c1) -> c1fp
4514 if (N0C && OpVT != MVT::ppcf128)
4515 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
4517 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
4518 // but SINT_TO_FP is legal on this target, try to convert.
4519 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
4520 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
4521 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
4522 if (DAG.SignBitIsZero(N0))
4523 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
4529 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
4530 SDValue N0 = N->getOperand(0);
4531 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4532 EVT VT = N->getValueType(0);
4534 // fold (fp_to_sint c1fp) -> c1
4536 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
4541 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
4542 SDValue N0 = N->getOperand(0);
4543 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4544 EVT VT = N->getValueType(0);
4546 // fold (fp_to_uint c1fp) -> c1
4547 if (N0CFP && VT != MVT::ppcf128)
4548 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
4553 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
4554 SDValue N0 = N->getOperand(0);
4555 SDValue N1 = N->getOperand(1);
4556 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4557 EVT VT = N->getValueType(0);
4559 // fold (fp_round c1fp) -> c1fp
4560 if (N0CFP && N0.getValueType() != MVT::ppcf128)
4561 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
4563 // fold (fp_round (fp_extend x)) -> x
4564 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
4565 return N0.getOperand(0);
4567 // fold (fp_round (fp_round x)) -> (fp_round x)
4568 if (N0.getOpcode() == ISD::FP_ROUND) {
4569 // This is a value preserving truncation if both round's are.
4570 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
4571 N0.getNode()->getConstantOperandVal(1) == 1;
4572 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
4573 DAG.getIntPtrConstant(IsTrunc));
4576 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
4577 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
4578 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
4579 N0.getOperand(0), N1);
4580 AddToWorkList(Tmp.getNode());
4581 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
4582 Tmp, N0.getOperand(1));
4588 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
4589 SDValue N0 = N->getOperand(0);
4590 EVT VT = N->getValueType(0);
4591 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4592 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4594 // fold (fp_round_inreg c1fp) -> c1fp
4595 if (N0CFP && isTypeLegal(EVT)) {
4596 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
4597 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
4603 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
4604 SDValue N0 = N->getOperand(0);
4605 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4606 EVT VT = N->getValueType(0);
4608 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
4609 if (N->hasOneUse() &&
4610 N->use_begin()->getOpcode() == ISD::FP_ROUND)
4613 // fold (fp_extend c1fp) -> c1fp
4614 if (N0CFP && VT != MVT::ppcf128)
4615 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
4617 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
4619 if (N0.getOpcode() == ISD::FP_ROUND
4620 && N0.getNode()->getConstantOperandVal(1) == 1) {
4621 SDValue In = N0.getOperand(0);
4622 if (In.getValueType() == VT) return In;
4623 if (VT.bitsLT(In.getValueType()))
4624 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
4625 In, N0.getOperand(1));
4626 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
4629 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
4630 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
4631 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4632 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4633 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4634 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4636 LN0->getBasePtr(), LN0->getSrcValue(),
4637 LN0->getSrcValueOffset(),
4639 LN0->isVolatile(), LN0->isNonTemporal(),
4640 LN0->getAlignment());
4641 CombineTo(N, ExtLoad);
4642 CombineTo(N0.getNode(),
4643 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
4644 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
4645 ExtLoad.getValue(1));
4646 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4652 SDValue DAGCombiner::visitFNEG(SDNode *N) {
4653 SDValue N0 = N->getOperand(0);
4654 EVT VT = N->getValueType(0);
4656 if (isNegatibleForFree(N0, LegalOperations))
4657 return GetNegatedExpression(N0, DAG, LegalOperations);
4659 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
4660 // constant pool values.
4661 if (N0.getOpcode() == ISD::BIT_CONVERT &&
4663 N0.getNode()->hasOneUse() &&
4664 N0.getOperand(0).getValueType().isInteger()) {
4665 SDValue Int = N0.getOperand(0);
4666 EVT IntVT = Int.getValueType();
4667 if (IntVT.isInteger() && !IntVT.isVector()) {
4668 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
4669 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4670 AddToWorkList(Int.getNode());
4671 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4679 SDValue DAGCombiner::visitFABS(SDNode *N) {
4680 SDValue N0 = N->getOperand(0);
4681 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
4682 EVT VT = N->getValueType(0);
4684 // fold (fabs c1) -> fabs(c1)
4685 if (N0CFP && VT != MVT::ppcf128)
4686 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
4687 // fold (fabs (fabs x)) -> (fabs x)
4688 if (N0.getOpcode() == ISD::FABS)
4689 return N->getOperand(0);
4690 // fold (fabs (fneg x)) -> (fabs x)
4691 // fold (fabs (fcopysign x, y)) -> (fabs x)
4692 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
4693 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
4695 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
4696 // constant pool values.
4697 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() &&
4698 N0.getOperand(0).getValueType().isInteger() &&
4699 !N0.getOperand(0).getValueType().isVector()) {
4700 SDValue Int = N0.getOperand(0);
4701 EVT IntVT = Int.getValueType();
4702 if (IntVT.isInteger() && !IntVT.isVector()) {
4703 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
4704 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
4705 AddToWorkList(Int.getNode());
4706 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4707 N->getValueType(0), Int);
4714 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
4715 SDValue Chain = N->getOperand(0);
4716 SDValue N1 = N->getOperand(1);
4717 SDValue N2 = N->getOperand(2);
4719 // If N is a constant we could fold this into a fallthrough or unconditional
4720 // branch. However that doesn't happen very often in normal code, because
4721 // Instcombine/SimplifyCFG should have handled the available opportunities.
4722 // If we did this folding here, it would be necessary to update the
4723 // MachineBasicBlock CFG, which is awkward.
4725 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
4727 if (N1.getOpcode() == ISD::SETCC &&
4728 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
4729 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4730 Chain, N1.getOperand(2),
4731 N1.getOperand(0), N1.getOperand(1), N2);
4735 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) {
4736 // Look past truncate.
4737 Trunc = N1.getNode();
4738 N1 = N1.getOperand(0);
4741 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) {
4742 // Match this pattern so that we can generate simpler code:
4745 // %b = and i32 %a, 2
4746 // %c = srl i32 %b, 1
4747 // brcond i32 %c ...
4752 // %b = and i32 %a, 2
4753 // %c = setcc eq %b, 0
4756 // This applies only when the AND constant value has one bit set and the
4757 // SRL constant is equal to the log2 of the AND constant. The back-end is
4758 // smart enough to convert the result into a TEST/JMP sequence.
4759 SDValue Op0 = N1.getOperand(0);
4760 SDValue Op1 = N1.getOperand(1);
4762 if (Op0.getOpcode() == ISD::AND &&
4763 Op1.getOpcode() == ISD::Constant) {
4764 SDValue AndOp1 = Op0.getOperand(1);
4766 if (AndOp1.getOpcode() == ISD::Constant) {
4767 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
4769 if (AndConst.isPowerOf2() &&
4770 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
4772 DAG.getSetCC(N->getDebugLoc(),
4773 TLI.getSetCCResultType(Op0.getValueType()),
4774 Op0, DAG.getConstant(0, Op0.getValueType()),
4777 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4778 MVT::Other, Chain, SetCC, N2);
4779 // Don't add the new BRCond into the worklist or else SimplifySelectCC
4780 // will convert it back to (X & C1) >> C2.
4781 CombineTo(N, NewBRCond, false);
4782 // Truncate is dead.
4784 removeFromWorkList(Trunc);
4785 DAG.DeleteNode(Trunc);
4787 // Replace the uses of SRL with SETCC
4788 WorkListRemover DeadNodes(*this);
4789 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
4790 removeFromWorkList(N1.getNode());
4791 DAG.DeleteNode(N1.getNode());
4792 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4798 // Transform br(xor(x, y)) -> br(x != y)
4799 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
4800 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
4801 SDNode *TheXor = N1.getNode();
4802 SDValue Op0 = TheXor->getOperand(0);
4803 SDValue Op1 = TheXor->getOperand(1);
4804 if (Op0.getOpcode() == Op1.getOpcode()) {
4805 // Avoid missing important xor optimizations.
4806 SDValue Tmp = visitXOR(TheXor);
4807 if (Tmp.getNode()) {
4808 DEBUG(dbgs() << "\nReplacing.8 ";
4810 dbgs() << "\nWith: ";
4811 Tmp.getNode()->dump(&DAG);
4813 WorkListRemover DeadNodes(*this);
4814 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
4815 removeFromWorkList(TheXor);
4816 DAG.DeleteNode(TheXor);
4817 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4818 MVT::Other, Chain, Tmp, N2);
4822 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
4824 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
4825 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
4826 Op0.getOpcode() == ISD::XOR) {
4827 TheXor = Op0.getNode();
4831 SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1;
4833 EVT SetCCVT = NodeToReplace.getValueType();
4835 SetCCVT = TLI.getSetCCResultType(SetCCVT);
4836 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
4839 Equal ? ISD::SETEQ : ISD::SETNE);
4840 // Replace the uses of XOR with SETCC
4841 WorkListRemover DeadNodes(*this);
4842 DAG.ReplaceAllUsesOfValueWith(NodeToReplace, SetCC, &DeadNodes);
4843 removeFromWorkList(NodeToReplace.getNode());
4844 DAG.DeleteNode(NodeToReplace.getNode());
4845 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4846 MVT::Other, Chain, SetCC, N2);
4853 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
4855 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
4856 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
4857 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
4859 // If N is a constant we could fold this into a fallthrough or unconditional
4860 // branch. However that doesn't happen very often in normal code, because
4861 // Instcombine/SimplifyCFG should have handled the available opportunities.
4862 // If we did this folding here, it would be necessary to update the
4863 // MachineBasicBlock CFG, which is awkward.
4865 // Use SimplifySetCC to simplify SETCC's.
4866 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
4867 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
4869 if (Simp.getNode()) AddToWorkList(Simp.getNode());
4871 // fold to a simpler setcc
4872 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
4873 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
4874 N->getOperand(0), Simp.getOperand(2),
4875 Simp.getOperand(0), Simp.getOperand(1),
4881 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
4882 /// pre-indexed load / store when the base pointer is an add or subtract
4883 /// and it has other uses besides the load / store. After the
4884 /// transformation, the new indexed load / store has effectively folded
4885 /// the add / subtract in and all of its other uses are redirected to the
4886 /// new load / store.
4887 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
4888 if (!LegalOperations)
4894 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4895 if (LD->isIndexed())
4897 VT = LD->getMemoryVT();
4898 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
4899 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
4901 Ptr = LD->getBasePtr();
4902 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4903 if (ST->isIndexed())
4905 VT = ST->getMemoryVT();
4906 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
4907 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
4909 Ptr = ST->getBasePtr();
4915 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
4916 // out. There is no reason to make this a preinc/predec.
4917 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
4918 Ptr.getNode()->hasOneUse())
4921 // Ask the target to do addressing mode selection.
4924 ISD::MemIndexedMode AM = ISD::UNINDEXED;
4925 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
4927 // Don't create a indexed load / store with zero offset.
4928 if (isa<ConstantSDNode>(Offset) &&
4929 cast<ConstantSDNode>(Offset)->isNullValue())
4932 // Try turning it into a pre-indexed load / store except when:
4933 // 1) The new base ptr is a frame index.
4934 // 2) If N is a store and the new base ptr is either the same as or is a
4935 // predecessor of the value being stored.
4936 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
4937 // that would create a cycle.
4938 // 4) All uses are load / store ops that use it as old base ptr.
4940 // Check #1. Preinc'ing a frame index would require copying the stack pointer
4941 // (plus the implicit offset) to a register to preinc anyway.
4942 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
4947 SDValue Val = cast<StoreSDNode>(N)->getValue();
4948 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
4952 // Now check for #3 and #4.
4953 bool RealUse = false;
4954 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
4955 E = Ptr.getNode()->use_end(); I != E; ++I) {
4959 if (Use->isPredecessorOf(N))
4962 if (!((Use->getOpcode() == ISD::LOAD &&
4963 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
4964 (Use->getOpcode() == ISD::STORE &&
4965 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
4974 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
4975 BasePtr, Offset, AM);
4977 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
4978 BasePtr, Offset, AM);
4981 DEBUG(dbgs() << "\nReplacing.4 ";
4983 dbgs() << "\nWith: ";
4984 Result.getNode()->dump(&DAG);
4986 WorkListRemover DeadNodes(*this);
4988 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
4990 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
4993 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
4997 // Finally, since the node is now dead, remove it from the graph.
5000 // Replace the uses of Ptr with uses of the updated base value.
5001 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
5003 removeFromWorkList(Ptr.getNode());
5004 DAG.DeleteNode(Ptr.getNode());
5009 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
5010 /// add / sub of the base pointer node into a post-indexed load / store.
5011 /// The transformation folded the add / subtract into the new indexed
5012 /// load / store effectively and all of its uses are redirected to the
5013 /// new load / store.
5014 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
5015 if (!LegalOperations)
5021 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5022 if (LD->isIndexed())
5024 VT = LD->getMemoryVT();
5025 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
5026 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
5028 Ptr = LD->getBasePtr();
5029 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5030 if (ST->isIndexed())
5032 VT = ST->getMemoryVT();
5033 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
5034 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
5036 Ptr = ST->getBasePtr();
5042 if (Ptr.getNode()->hasOneUse())
5045 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5046 E = Ptr.getNode()->use_end(); I != E; ++I) {
5049 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
5054 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5055 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
5056 if (Ptr == Offset && Op->getOpcode() == ISD::ADD)
5057 std::swap(BasePtr, Offset);
5060 // Don't create a indexed load / store with zero offset.
5061 if (isa<ConstantSDNode>(Offset) &&
5062 cast<ConstantSDNode>(Offset)->isNullValue())
5065 // Try turning it into a post-indexed load / store except when
5066 // 1) All uses are load / store ops that use it as base ptr.
5067 // 2) Op must be independent of N, i.e. Op is neither a predecessor
5068 // nor a successor of N. Otherwise, if Op is folded that would
5071 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5075 bool TryNext = false;
5076 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
5077 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
5079 if (Use == Ptr.getNode())
5082 // If all the uses are load / store addresses, then don't do the
5084 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
5085 bool RealUse = false;
5086 for (SDNode::use_iterator III = Use->use_begin(),
5087 EEE = Use->use_end(); III != EEE; ++III) {
5088 SDNode *UseUse = *III;
5089 if (!((UseUse->getOpcode() == ISD::LOAD &&
5090 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
5091 (UseUse->getOpcode() == ISD::STORE &&
5092 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
5107 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
5108 SDValue Result = isLoad
5109 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5110 BasePtr, Offset, AM)
5111 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5112 BasePtr, Offset, AM);
5115 DEBUG(dbgs() << "\nReplacing.5 ";
5117 dbgs() << "\nWith: ";
5118 Result.getNode()->dump(&DAG);
5120 WorkListRemover DeadNodes(*this);
5122 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5124 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5127 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5131 // Finally, since the node is now dead, remove it from the graph.
5134 // Replace the uses of Use with uses of the updated base value.
5135 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
5136 Result.getValue(isLoad ? 1 : 0),
5138 removeFromWorkList(Op);
5148 SDValue DAGCombiner::visitLOAD(SDNode *N) {
5149 LoadSDNode *LD = cast<LoadSDNode>(N);
5150 SDValue Chain = LD->getChain();
5151 SDValue Ptr = LD->getBasePtr();
5153 // If load is not volatile and there are no uses of the loaded value (and
5154 // the updated indexed value in case of indexed loads), change uses of the
5155 // chain value into uses of the chain input (i.e. delete the dead load).
5156 if (!LD->isVolatile()) {
5157 if (N->getValueType(1) == MVT::Other) {
5159 if (N->hasNUsesOfValue(0, 0)) {
5160 // It's not safe to use the two value CombineTo variant here. e.g.
5161 // v1, chain2 = load chain1, loc
5162 // v2, chain3 = load chain2, loc
5164 // Now we replace use of chain2 with chain1. This makes the second load
5165 // isomorphic to the one we are deleting, and thus makes this load live.
5166 DEBUG(dbgs() << "\nReplacing.6 ";
5168 dbgs() << "\nWith chain: ";
5169 Chain.getNode()->dump(&DAG);
5171 WorkListRemover DeadNodes(*this);
5172 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
5174 if (N->use_empty()) {
5175 removeFromWorkList(N);
5179 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5183 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
5184 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
5185 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
5186 DEBUG(dbgs() << "\nReplacing.7 ";
5188 dbgs() << "\nWith: ";
5189 Undef.getNode()->dump(&DAG);
5190 dbgs() << " and 2 other values\n");
5191 WorkListRemover DeadNodes(*this);
5192 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
5193 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
5194 DAG.getUNDEF(N->getValueType(1)),
5196 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
5197 removeFromWorkList(N);
5199 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5204 // If this load is directly stored, replace the load value with the stored
5206 // TODO: Handle store large -> read small portion.
5207 // TODO: Handle TRUNCSTORE/LOADEXT
5208 if (LD->getExtensionType() == ISD::NON_EXTLOAD &&
5209 !LD->isVolatile()) {
5210 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
5211 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
5212 if (PrevST->getBasePtr() == Ptr &&
5213 PrevST->getValue().getValueType() == N->getValueType(0))
5214 return CombineTo(N, Chain.getOperand(1), Chain);
5218 // Try to infer better alignment information than the load already has.
5219 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
5220 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5221 if (Align > LD->getAlignment())
5222 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
5223 LD->getValueType(0),
5224 Chain, Ptr, LD->getSrcValue(),
5225 LD->getSrcValueOffset(), LD->getMemoryVT(),
5226 LD->isVolatile(), LD->isNonTemporal(), Align);
5231 // Walk up chain skipping non-aliasing memory nodes.
5232 SDValue BetterChain = FindBetterChain(N, Chain);
5234 // If there is a better chain.
5235 if (Chain != BetterChain) {
5238 // Replace the chain to void dependency.
5239 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
5240 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
5242 LD->getSrcValue(), LD->getSrcValueOffset(),
5243 LD->isVolatile(), LD->isNonTemporal(),
5244 LD->getAlignment());
5246 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
5247 LD->getValueType(0),
5248 BetterChain, Ptr, LD->getSrcValue(),
5249 LD->getSrcValueOffset(),
5252 LD->isNonTemporal(),
5253 LD->getAlignment());
5256 // Create token factor to keep old chain connected.
5257 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5258 MVT::Other, Chain, ReplLoad.getValue(1));
5260 // Make sure the new and old chains are cleaned up.
5261 AddToWorkList(Token.getNode());
5263 // Replace uses with load result and token factor. Don't add users
5265 return CombineTo(N, ReplLoad.getValue(0), Token, false);
5269 // Try transforming N to an indexed load.
5270 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5271 return SDValue(N, 0);
5276 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
5277 /// load is having specific bytes cleared out. If so, return the byte size
5278 /// being masked out and the shift amount.
5279 static std::pair<unsigned, unsigned>
5280 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
5281 std::pair<unsigned, unsigned> Result(0, 0);
5283 // Check for the structure we're looking for.
5284 if (V->getOpcode() != ISD::AND ||
5285 !isa<ConstantSDNode>(V->getOperand(1)) ||
5286 !ISD::isNormalLoad(V->getOperand(0).getNode()))
5289 // Check the chain and pointer.
5290 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
5291 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
5293 // The store should be chained directly to the load or be an operand of a
5295 if (LD == Chain.getNode())
5297 else if (Chain->getOpcode() != ISD::TokenFactor)
5298 return Result; // Fail.
5301 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
5302 if (Chain->getOperand(i).getNode() == LD) {
5306 if (!isOk) return Result;
5309 // This only handles simple types.
5310 if (V.getValueType() != MVT::i16 &&
5311 V.getValueType() != MVT::i32 &&
5312 V.getValueType() != MVT::i64)
5315 // Check the constant mask. Invert it so that the bits being masked out are
5316 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
5317 // follow the sign bit for uniformity.
5318 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
5319 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
5320 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
5321 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
5322 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
5323 if (NotMaskLZ == 64) return Result; // All zero mask.
5325 // See if we have a continuous run of bits. If so, we have 0*1+0*
5326 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
5329 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
5330 if (V.getValueType() != MVT::i64 && NotMaskLZ)
5331 NotMaskLZ -= 64-V.getValueSizeInBits();
5333 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
5334 switch (MaskedBytes) {
5338 default: return Result; // All one mask, or 5-byte mask.
5341 // Verify that the first bit starts at a multiple of mask so that the access
5342 // is aligned the same as the access width.
5343 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
5345 Result.first = MaskedBytes;
5346 Result.second = NotMaskTZ/8;
5351 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
5352 /// provides a value as specified by MaskInfo. If so, replace the specified
5353 /// store with a narrower store of truncated IVal.
5355 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
5356 SDValue IVal, StoreSDNode *St,
5358 unsigned NumBytes = MaskInfo.first;
5359 unsigned ByteShift = MaskInfo.second;
5360 SelectionDAG &DAG = DC->getDAG();
5362 // Check to see if IVal is all zeros in the part being masked in by the 'or'
5363 // that uses this. If not, this is not a replacement.
5364 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
5365 ByteShift*8, (ByteShift+NumBytes)*8);
5366 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
5368 // Check that it is legal on the target to do this. It is legal if the new
5369 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
5371 MVT VT = MVT::getIntegerVT(NumBytes*8);
5372 if (!DC->isTypeLegal(VT))
5375 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
5376 // shifted by ByteShift and truncated down to NumBytes.
5378 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
5379 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy()));
5381 // Figure out the offset for the store and the alignment of the access.
5383 unsigned NewAlign = St->getAlignment();
5385 if (DAG.getTargetLoweringInfo().isLittleEndian())
5386 StOffset = ByteShift;
5388 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
5390 SDValue Ptr = St->getBasePtr();
5392 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
5393 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
5394 NewAlign = MinAlign(NewAlign, StOffset);
5397 // Truncate down to the new size.
5398 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
5401 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
5402 St->getSrcValue(), St->getSrcValueOffset()+StOffset,
5403 false, false, NewAlign).getNode();
5407 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
5408 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
5409 /// of the loaded bits, try narrowing the load and store if it would end up
5410 /// being a win for performance or code size.
5411 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
5412 StoreSDNode *ST = cast<StoreSDNode>(N);
5413 if (ST->isVolatile())
5416 SDValue Chain = ST->getChain();
5417 SDValue Value = ST->getValue();
5418 SDValue Ptr = ST->getBasePtr();
5419 EVT VT = Value.getValueType();
5421 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
5424 unsigned Opc = Value.getOpcode();
5426 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
5427 // is a byte mask indicating a consecutive number of bytes, check to see if
5428 // Y is known to provide just those bytes. If so, we try to replace the
5429 // load + replace + store sequence with a single (narrower) store, which makes
5431 if (Opc == ISD::OR) {
5432 std::pair<unsigned, unsigned> MaskedLoad;
5433 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
5434 if (MaskedLoad.first)
5435 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5436 Value.getOperand(1), ST,this))
5437 return SDValue(NewST, 0);
5439 // Or is commutative, so try swapping X and Y.
5440 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
5441 if (MaskedLoad.first)
5442 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
5443 Value.getOperand(0), ST,this))
5444 return SDValue(NewST, 0);
5447 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
5448 Value.getOperand(1).getOpcode() != ISD::Constant)
5451 SDValue N0 = Value.getOperand(0);
5452 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) {
5453 LoadSDNode *LD = cast<LoadSDNode>(N0);
5454 if (LD->getBasePtr() != Ptr)
5457 // Find the type to narrow it the load / op / store to.
5458 SDValue N1 = Value.getOperand(1);
5459 unsigned BitWidth = N1.getValueSizeInBits();
5460 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
5461 if (Opc == ISD::AND)
5462 Imm ^= APInt::getAllOnesValue(BitWidth);
5463 if (Imm == 0 || Imm.isAllOnesValue())
5465 unsigned ShAmt = Imm.countTrailingZeros();
5466 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
5467 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
5468 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5469 while (NewBW < BitWidth &&
5470 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
5471 TLI.isNarrowingProfitable(VT, NewVT))) {
5472 NewBW = NextPowerOf2(NewBW);
5473 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
5475 if (NewBW >= BitWidth)
5478 // If the lsb changed does not start at the type bitwidth boundary,
5479 // start at the previous one.
5481 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
5482 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
5483 if ((Imm & Mask) == Imm) {
5484 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
5485 if (Opc == ISD::AND)
5486 NewImm ^= APInt::getAllOnesValue(NewBW);
5487 uint64_t PtrOff = ShAmt / 8;
5488 // For big endian targets, we need to adjust the offset to the pointer to
5489 // load the correct bytes.
5490 if (TLI.isBigEndian())
5491 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
5493 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
5494 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
5495 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
5498 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
5499 Ptr.getValueType(), Ptr,
5500 DAG.getConstant(PtrOff, Ptr.getValueType()));
5501 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
5502 LD->getChain(), NewPtr,
5503 LD->getSrcValue(), LD->getSrcValueOffset(),
5504 LD->isVolatile(), LD->isNonTemporal(),
5506 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
5507 DAG.getConstant(NewImm, NewVT));
5508 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
5510 ST->getSrcValue(), ST->getSrcValueOffset(),
5511 false, false, NewAlign);
5513 AddToWorkList(NewPtr.getNode());
5514 AddToWorkList(NewLD.getNode());
5515 AddToWorkList(NewVal.getNode());
5516 WorkListRemover DeadNodes(*this);
5517 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
5527 SDValue DAGCombiner::visitSTORE(SDNode *N) {
5528 StoreSDNode *ST = cast<StoreSDNode>(N);
5529 SDValue Chain = ST->getChain();
5530 SDValue Value = ST->getValue();
5531 SDValue Ptr = ST->getBasePtr();
5533 // If this is a store of a bit convert, store the input value if the
5534 // resultant store does not need a higher alignment than the original.
5535 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
5536 ST->isUnindexed()) {
5537 unsigned OrigAlign = ST->getAlignment();
5538 EVT SVT = Value.getOperand(0).getValueType();
5539 unsigned Align = TLI.getTargetData()->
5540 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
5541 if (Align <= OrigAlign &&
5542 ((!LegalOperations && !ST->isVolatile()) ||
5543 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
5544 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5545 Ptr, ST->getSrcValue(),
5546 ST->getSrcValueOffset(), ST->isVolatile(),
5547 ST->isNonTemporal(), OrigAlign);
5550 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
5551 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
5552 // NOTE: If the original store is volatile, this transform must not increase
5553 // the number of stores. For example, on x86-32 an f64 can be stored in one
5554 // processor operation but an i64 (which is not legal) requires two. So the
5555 // transform should not be done in this case.
5556 if (Value.getOpcode() != ISD::TargetConstantFP) {
5558 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
5559 default: llvm_unreachable("Unknown FP type");
5560 case MVT::f80: // We don't do this for these yet.
5565 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
5566 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5567 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
5568 bitcastToAPInt().getZExtValue(), MVT::i32);
5569 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5570 Ptr, ST->getSrcValue(),
5571 ST->getSrcValueOffset(), ST->isVolatile(),
5572 ST->isNonTemporal(), ST->getAlignment());
5576 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
5577 !ST->isVolatile()) ||
5578 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
5579 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
5580 getZExtValue(), MVT::i64);
5581 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
5582 Ptr, ST->getSrcValue(),
5583 ST->getSrcValueOffset(), ST->isVolatile(),
5584 ST->isNonTemporal(), ST->getAlignment());
5585 } else if (!ST->isVolatile() &&
5586 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
5587 // Many FP stores are not made apparent until after legalize, e.g. for
5588 // argument passing. Since this is so common, custom legalize the
5589 // 64-bit integer store into two 32-bit stores.
5590 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
5591 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
5592 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
5593 if (TLI.isBigEndian()) std::swap(Lo, Hi);
5595 int SVOffset = ST->getSrcValueOffset();
5596 unsigned Alignment = ST->getAlignment();
5597 bool isVolatile = ST->isVolatile();
5598 bool isNonTemporal = ST->isNonTemporal();
5600 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
5601 Ptr, ST->getSrcValue(),
5602 ST->getSrcValueOffset(),
5603 isVolatile, isNonTemporal,
5604 ST->getAlignment());
5605 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
5606 DAG.getConstant(4, Ptr.getValueType()));
5608 Alignment = MinAlign(Alignment, 4U);
5609 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
5610 Ptr, ST->getSrcValue(),
5611 SVOffset, isVolatile, isNonTemporal,
5613 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
5622 // Try to infer better alignment information than the store already has.
5623 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
5624 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
5625 if (Align > ST->getAlignment())
5626 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
5627 Ptr, ST->getSrcValue(),
5628 ST->getSrcValueOffset(), ST->getMemoryVT(),
5629 ST->isVolatile(), ST->isNonTemporal(), Align);
5634 // Walk up chain skipping non-aliasing memory nodes.
5635 SDValue BetterChain = FindBetterChain(N, Chain);
5637 // If there is a better chain.
5638 if (Chain != BetterChain) {
5641 // Replace the chain to avoid dependency.
5642 if (ST->isTruncatingStore()) {
5643 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5644 ST->getSrcValue(),ST->getSrcValueOffset(),
5645 ST->getMemoryVT(), ST->isVolatile(),
5646 ST->isNonTemporal(), ST->getAlignment());
5648 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
5649 ST->getSrcValue(), ST->getSrcValueOffset(),
5650 ST->isVolatile(), ST->isNonTemporal(),
5651 ST->getAlignment());
5654 // Create token to keep both nodes around.
5655 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5656 MVT::Other, Chain, ReplStore);
5658 // Make sure the new and old chains are cleaned up.
5659 AddToWorkList(Token.getNode());
5661 // Don't add users to work list.
5662 return CombineTo(N, Token, false);
5666 // Try transforming N to an indexed store.
5667 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
5668 return SDValue(N, 0);
5670 // FIXME: is there such a thing as a truncating indexed store?
5671 if (ST->isTruncatingStore() && ST->isUnindexed() &&
5672 Value.getValueType().isInteger()) {
5673 // See if we can simplify the input to this truncstore with knowledge that
5674 // only the low bits are being used. For example:
5675 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
5677 GetDemandedBits(Value,
5678 APInt::getLowBitsSet(Value.getValueSizeInBits(),
5679 ST->getMemoryVT().getSizeInBits()));
5680 AddToWorkList(Value.getNode());
5681 if (Shorter.getNode())
5682 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
5683 Ptr, ST->getSrcValue(),
5684 ST->getSrcValueOffset(), ST->getMemoryVT(),
5685 ST->isVolatile(), ST->isNonTemporal(),
5686 ST->getAlignment());
5688 // Otherwise, see if we can simplify the operation with
5689 // SimplifyDemandedBits, which only works if the value has a single use.
5690 if (SimplifyDemandedBits(Value,
5691 APInt::getLowBitsSet(
5692 Value.getValueType().getScalarType().getSizeInBits(),
5693 ST->getMemoryVT().getScalarType().getSizeInBits())))
5694 return SDValue(N, 0);
5697 // If this is a load followed by a store to the same location, then the store
5699 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
5700 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
5701 ST->isUnindexed() && !ST->isVolatile() &&
5702 // There can't be any side effects between the load and store, such as
5704 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
5705 // The store is dead, remove it.
5710 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
5711 // truncating store. We can do this even if this is already a truncstore.
5712 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
5713 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
5714 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
5715 ST->getMemoryVT())) {
5716 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
5717 Ptr, ST->getSrcValue(),
5718 ST->getSrcValueOffset(), ST->getMemoryVT(),
5719 ST->isVolatile(), ST->isNonTemporal(),
5720 ST->getAlignment());
5723 return ReduceLoadOpStoreWidth(N);
5726 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
5727 SDValue InVec = N->getOperand(0);
5728 SDValue InVal = N->getOperand(1);
5729 SDValue EltNo = N->getOperand(2);
5731 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
5732 // vector with the inserted element.
5733 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
5734 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5735 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(),
5736 InVec.getNode()->op_end());
5737 if (Elt < Ops.size())
5739 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5740 InVec.getValueType(), &Ops[0], Ops.size());
5742 // If the invec is an UNDEF and if EltNo is a constant, create a new
5743 // BUILD_VECTOR with undef elements and the inserted element.
5744 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
5745 isa<ConstantSDNode>(EltNo)) {
5746 EVT VT = InVec.getValueType();
5747 EVT EltVT = VT.getVectorElementType();
5748 unsigned NElts = VT.getVectorNumElements();
5749 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT));
5751 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5752 if (Elt < Ops.size())
5754 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
5755 InVec.getValueType(), &Ops[0], Ops.size());
5760 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
5761 // (vextract (scalar_to_vector val, 0) -> val
5762 SDValue InVec = N->getOperand(0);
5764 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5765 // Check if the result type doesn't match the inserted element type. A
5766 // SCALAR_TO_VECTOR may truncate the inserted element and the
5767 // EXTRACT_VECTOR_ELT may widen the extracted vector.
5768 EVT EltVT = InVec.getValueType().getVectorElementType();
5769 SDValue InOp = InVec.getOperand(0);
5770 EVT NVT = N->getValueType(0);
5771 if (InOp.getValueType() != NVT) {
5772 assert(InOp.getValueType().isInteger() && NVT.isInteger());
5773 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
5778 // Perform only after legalization to ensure build_vector / vector_shuffle
5779 // optimizations have already been done.
5780 if (!LegalOperations) return SDValue();
5782 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
5783 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
5784 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
5785 SDValue EltNo = N->getOperand(1);
5787 if (isa<ConstantSDNode>(EltNo)) {
5788 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
5789 bool NewLoad = false;
5790 bool BCNumEltsChanged = false;
5791 EVT VT = InVec.getValueType();
5792 EVT ExtVT = VT.getVectorElementType();
5795 if (InVec.getOpcode() == ISD::BIT_CONVERT) {
5796 EVT BCVT = InVec.getOperand(0).getValueType();
5797 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
5799 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
5800 BCNumEltsChanged = true;
5801 InVec = InVec.getOperand(0);
5802 ExtVT = BCVT.getVectorElementType();
5806 LoadSDNode *LN0 = NULL;
5807 const ShuffleVectorSDNode *SVN = NULL;
5808 if (ISD::isNormalLoad(InVec.getNode())) {
5809 LN0 = cast<LoadSDNode>(InVec);
5810 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
5811 InVec.getOperand(0).getValueType() == ExtVT &&
5812 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
5813 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
5814 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
5815 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
5817 // (load $addr+1*size)
5819 // If the bit convert changed the number of elements, it is unsafe
5820 // to examine the mask.
5821 if (BCNumEltsChanged)
5824 // Select the input vector, guarding against out of range extract vector.
5825 unsigned NumElems = VT.getVectorNumElements();
5826 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt);
5827 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
5829 if (InVec.getOpcode() == ISD::BIT_CONVERT)
5830 InVec = InVec.getOperand(0);
5831 if (ISD::isNormalLoad(InVec.getNode())) {
5832 LN0 = cast<LoadSDNode>(InVec);
5833 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
5837 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile())
5840 unsigned Align = LN0->getAlignment();
5842 // Check the resultant load doesn't need a higher alignment than the
5845 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
5847 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
5853 SDValue NewPtr = LN0->getBasePtr();
5855 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
5856 EVT PtrType = NewPtr.getValueType();
5857 if (TLI.isBigEndian())
5858 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
5859 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
5860 DAG.getConstant(PtrOff, PtrType));
5863 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
5864 LN0->getSrcValue(), LN0->getSrcValueOffset(),
5865 LN0->isVolatile(), LN0->isNonTemporal(), Align);
5871 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
5872 unsigned NumInScalars = N->getNumOperands();
5873 EVT VT = N->getValueType(0);
5875 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
5876 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
5877 // at most two distinct vectors, turn this into a shuffle node.
5878 SDValue VecIn1, VecIn2;
5879 for (unsigned i = 0; i != NumInScalars; ++i) {
5880 // Ignore undef inputs.
5881 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5883 // If this input is something other than a EXTRACT_VECTOR_ELT with a
5884 // constant index, bail out.
5885 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
5886 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
5887 VecIn1 = VecIn2 = SDValue(0, 0);
5891 // If the input vector type disagrees with the result of the build_vector,
5892 // we can't make a shuffle.
5893 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
5894 if (ExtractedFromVec.getValueType() != VT) {
5895 VecIn1 = VecIn2 = SDValue(0, 0);
5899 // Otherwise, remember this. We allow up to two distinct input vectors.
5900 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
5903 if (VecIn1.getNode() == 0) {
5904 VecIn1 = ExtractedFromVec;
5905 } else if (VecIn2.getNode() == 0) {
5906 VecIn2 = ExtractedFromVec;
5909 VecIn1 = VecIn2 = SDValue(0, 0);
5914 // If everything is good, we can make a shuffle operation.
5915 if (VecIn1.getNode()) {
5916 SmallVector<int, 8> Mask;
5917 for (unsigned i = 0; i != NumInScalars; ++i) {
5918 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
5923 // If extracting from the first vector, just use the index directly.
5924 SDValue Extract = N->getOperand(i);
5925 SDValue ExtVal = Extract.getOperand(1);
5926 if (Extract.getOperand(0) == VecIn1) {
5927 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5928 if (ExtIndex > VT.getVectorNumElements())
5931 Mask.push_back(ExtIndex);
5935 // Otherwise, use InIdx + VecSize
5936 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
5937 Mask.push_back(Idx+NumInScalars);
5940 // Add count and size info.
5941 if (!isTypeLegal(VT))
5944 // Return the new VECTOR_SHUFFLE node.
5947 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
5948 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
5954 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
5955 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
5956 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
5957 // inputs come from at most two distinct vectors, turn this into a shuffle
5960 // If we only have one input vector, we don't need to do any concatenation.
5961 if (N->getNumOperands() == 1)
5962 return N->getOperand(0);
5967 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
5970 EVT VT = N->getValueType(0);
5971 unsigned NumElts = VT.getVectorNumElements();
5973 SDValue N0 = N->getOperand(0);
5975 assert(N0.getValueType().getVectorNumElements() == NumElts &&
5976 "Vector shuffle must be normalized in DAG");
5978 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
5980 // If it is a splat, check if the argument vector is a build_vector with
5981 // all scalar elements the same.
5982 if (cast<ShuffleVectorSDNode>(N)->isSplat()) {
5983 SDNode *V = N0.getNode();
5986 // If this is a bit convert that changes the element type of the vector but
5987 // not the number of vector elements, look through it. Be careful not to
5988 // look though conversions that change things like v4f32 to v2f64.
5989 if (V->getOpcode() == ISD::BIT_CONVERT) {
5990 SDValue ConvInput = V->getOperand(0);
5991 if (ConvInput.getValueType().isVector() &&
5992 ConvInput.getValueType().getVectorNumElements() == NumElts)
5993 V = ConvInput.getNode();
5996 if (V->getOpcode() == ISD::BUILD_VECTOR) {
5997 unsigned NumElems = V->getNumOperands();
5998 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex();
5999 if (NumElems > BaseIdx) {
6001 bool AllSame = true;
6002 for (unsigned i = 0; i != NumElems; ++i) {
6003 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
6004 Base = V->getOperand(i);
6008 // Splat of <u, u, u, u>, return <u, u, u, u>
6009 if (!Base.getNode())
6011 for (unsigned i = 0; i != NumElems; ++i) {
6012 if (V->getOperand(i) != Base) {
6017 // Splat of <x, x, x, x>, return <x, x, x, x>
6026 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
6027 /// an AND to a vector_shuffle with the destination vector and a zero vector.
6028 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
6029 /// vector_shuffle V, Zero, <0, 4, 2, 4>
6030 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
6031 EVT VT = N->getValueType(0);
6032 DebugLoc dl = N->getDebugLoc();
6033 SDValue LHS = N->getOperand(0);
6034 SDValue RHS = N->getOperand(1);
6035 if (N->getOpcode() == ISD::AND) {
6036 if (RHS.getOpcode() == ISD::BIT_CONVERT)
6037 RHS = RHS.getOperand(0);
6038 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
6039 SmallVector<int, 8> Indices;
6040 unsigned NumElts = RHS.getNumOperands();
6041 for (unsigned i = 0; i != NumElts; ++i) {
6042 SDValue Elt = RHS.getOperand(i);
6043 if (!isa<ConstantSDNode>(Elt))
6045 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
6046 Indices.push_back(i);
6047 else if (cast<ConstantSDNode>(Elt)->isNullValue())
6048 Indices.push_back(NumElts);
6053 // Let's see if the target supports this vector_shuffle.
6054 EVT RVT = RHS.getValueType();
6055 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
6058 // Return the new VECTOR_SHUFFLE node.
6059 EVT EltVT = RVT.getVectorElementType();
6060 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
6061 DAG.getConstant(0, EltVT));
6062 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
6063 RVT, &ZeroOps[0], ZeroOps.size());
6064 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS);
6065 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
6066 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf);
6073 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
6074 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
6075 // After legalize, the target may be depending on adds and other
6076 // binary ops to provide legal ways to construct constants or other
6077 // things. Simplifying them may result in a loss of legality.
6078 if (LegalOperations) return SDValue();
6080 EVT VT = N->getValueType(0);
6081 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
6083 EVT EltType = VT.getVectorElementType();
6084 SDValue LHS = N->getOperand(0);
6085 SDValue RHS = N->getOperand(1);
6086 SDValue Shuffle = XformToShuffleWithZero(N);
6087 if (Shuffle.getNode()) return Shuffle;
6089 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
6091 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
6092 RHS.getOpcode() == ISD::BUILD_VECTOR) {
6093 SmallVector<SDValue, 8> Ops;
6094 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
6095 SDValue LHSOp = LHS.getOperand(i);
6096 SDValue RHSOp = RHS.getOperand(i);
6097 // If these two elements can't be folded, bail out.
6098 if ((LHSOp.getOpcode() != ISD::UNDEF &&
6099 LHSOp.getOpcode() != ISD::Constant &&
6100 LHSOp.getOpcode() != ISD::ConstantFP) ||
6101 (RHSOp.getOpcode() != ISD::UNDEF &&
6102 RHSOp.getOpcode() != ISD::Constant &&
6103 RHSOp.getOpcode() != ISD::ConstantFP))
6106 // Can't fold divide by zero.
6107 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
6108 N->getOpcode() == ISD::FDIV) {
6109 if ((RHSOp.getOpcode() == ISD::Constant &&
6110 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
6111 (RHSOp.getOpcode() == ISD::ConstantFP &&
6112 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
6116 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(),
6117 EltType, LHSOp, RHSOp));
6118 AddToWorkList(Ops.back().getNode());
6119 assert((Ops.back().getOpcode() == ISD::UNDEF ||
6120 Ops.back().getOpcode() == ISD::Constant ||
6121 Ops.back().getOpcode() == ISD::ConstantFP) &&
6122 "Scalar binop didn't fold!");
6125 if (Ops.size() == LHS.getNumOperands()) {
6126 EVT VT = LHS.getValueType();
6127 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
6128 &Ops[0], Ops.size());
6135 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
6136 SDValue N1, SDValue N2){
6137 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
6139 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
6140 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6142 // If we got a simplified select_cc node back from SimplifySelectCC, then
6143 // break it down into a new SETCC node, and a new SELECT node, and then return
6144 // the SELECT node, since we were called with a SELECT node.
6145 if (SCC.getNode()) {
6146 // Check to see if we got a select_cc back (to turn into setcc/select).
6147 // Otherwise, just return whatever node we got back, like fabs.
6148 if (SCC.getOpcode() == ISD::SELECT_CC) {
6149 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
6151 SCC.getOperand(0), SCC.getOperand(1),
6153 AddToWorkList(SETCC.getNode());
6154 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
6155 SCC.getOperand(2), SCC.getOperand(3), SETCC);
6163 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
6164 /// are the two values being selected between, see if we can simplify the
6165 /// select. Callers of this should assume that TheSelect is deleted if this
6166 /// returns true. As such, they should return the appropriate thing (e.g. the
6167 /// node) back to the top-level of the DAG combiner loop to avoid it being
6169 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
6172 // If this is a select from two identical things, try to pull the operation
6173 // through the select.
6174 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
6175 // If this is a load and the token chain is identical, replace the select
6176 // of two loads with a load through a select of the address to load from.
6177 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
6178 // constants have been dropped into the constant pool.
6179 if (LHS.getOpcode() == ISD::LOAD &&
6180 // Do not let this transformation reduce the number of volatile loads.
6181 !cast<LoadSDNode>(LHS)->isVolatile() &&
6182 !cast<LoadSDNode>(RHS)->isVolatile() &&
6183 // Token chains must be identical.
6184 LHS.getOperand(0) == RHS.getOperand(0)) {
6185 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
6186 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
6188 // If this is an EXTLOAD, the VT's must match.
6189 if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
6190 // FIXME: this discards src value information. This is
6191 // over-conservative. It would be beneficial to be able to remember
6192 // both potential memory locations. Since we are discarding
6193 // src value info, don't do the transformation if the memory
6194 // locations are not in the default address space.
6195 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0;
6196 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) {
6197 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType()))
6198 LLDAddrSpace = PT->getAddressSpace();
6200 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) {
6201 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType()))
6202 RLDAddrSpace = PT->getAddressSpace();
6205 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) {
6206 if (TheSelect->getOpcode() == ISD::SELECT) {
6207 // Check that the condition doesn't reach either load. If so, folding
6208 // this will induce a cycle into the DAG.
6209 if ((!LLD->hasAnyUseOfValue(1) ||
6210 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) &&
6211 (!RLD->hasAnyUseOfValue(1) ||
6212 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) {
6213 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
6214 LLD->getBasePtr().getValueType(),
6215 TheSelect->getOperand(0), LLD->getBasePtr(),
6219 // Check that the condition doesn't reach either load. If so, folding
6220 // this will induce a cycle into the DAG.
6221 if ((!LLD->hasAnyUseOfValue(1) ||
6222 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
6223 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) &&
6224 (!RLD->hasAnyUseOfValue(1) ||
6225 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
6226 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) {
6227 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
6228 LLD->getBasePtr().getValueType(),
6229 TheSelect->getOperand(0),
6230 TheSelect->getOperand(1),
6231 LLD->getBasePtr(), RLD->getBasePtr(),
6232 TheSelect->getOperand(4));
6237 if (Addr.getNode()) {
6239 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
6240 Load = DAG.getLoad(TheSelect->getValueType(0),
6241 TheSelect->getDebugLoc(),
6245 LLD->isNonTemporal(),
6246 LLD->getAlignment());
6248 Load = DAG.getExtLoad(LLD->getExtensionType(),
6249 TheSelect->getDebugLoc(),
6250 TheSelect->getValueType(0),
6251 LLD->getChain(), Addr, 0, 0,
6254 LLD->isNonTemporal(),
6255 LLD->getAlignment());
6258 // Users of the select now use the result of the load.
6259 CombineTo(TheSelect, Load);
6261 // Users of the old loads now use the new load's chain. We know the
6262 // old-load value is dead now.
6263 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
6264 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
6274 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
6275 /// where 'cond' is the comparison specified by CC.
6276 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
6277 SDValue N2, SDValue N3,
6278 ISD::CondCode CC, bool NotExtCompare) {
6279 // (x ? y : y) -> y.
6280 if (N2 == N3) return N2;
6282 EVT VT = N2.getValueType();
6283 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
6284 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
6285 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
6287 // Determine if the condition we're dealing with is constant
6288 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
6289 N0, N1, CC, DL, false);
6290 if (SCC.getNode()) AddToWorkList(SCC.getNode());
6291 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
6293 // fold select_cc true, x, y -> x
6294 if (SCCC && !SCCC->isNullValue())
6296 // fold select_cc false, x, y -> y
6297 if (SCCC && SCCC->isNullValue())
6300 // Check to see if we can simplify the select into an fabs node
6301 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
6302 // Allow either -0.0 or 0.0
6303 if (CFP->getValueAPF().isZero()) {
6304 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
6305 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
6306 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
6307 N2 == N3.getOperand(0))
6308 return DAG.getNode(ISD::FABS, DL, VT, N0);
6310 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
6311 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
6312 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
6313 N2.getOperand(0) == N3)
6314 return DAG.getNode(ISD::FABS, DL, VT, N3);
6318 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
6319 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
6320 // in it. This is a win when the constant is not otherwise available because
6321 // it replaces two constant pool loads with one. We only do this if the FP
6322 // type is known to be legal, because if it isn't, then we are before legalize
6323 // types an we want the other legalization to happen first (e.g. to avoid
6324 // messing with soft float) and if the ConstantFP is not legal, because if
6325 // it is legal, we may not need to store the FP constant in a constant pool.
6326 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
6327 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
6328 if (TLI.isTypeLegal(N2.getValueType()) &&
6329 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
6330 TargetLowering::Legal) &&
6331 // If both constants have multiple uses, then we won't need to do an
6332 // extra load, they are likely around in registers for other users.
6333 (TV->hasOneUse() || FV->hasOneUse())) {
6334 Constant *Elts[] = {
6335 const_cast<ConstantFP*>(FV->getConstantFPValue()),
6336 const_cast<ConstantFP*>(TV->getConstantFPValue())
6338 const Type *FPTy = Elts[0]->getType();
6339 const TargetData &TD = *TLI.getTargetData();
6341 // Create a ConstantArray of the two constants.
6342 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
6343 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
6344 TD.getPrefTypeAlignment(FPTy));
6345 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6347 // Get the offsets to the 0 and 1 element of the array so that we can
6348 // select between them.
6349 SDValue Zero = DAG.getIntPtrConstant(0);
6350 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
6351 SDValue One = DAG.getIntPtrConstant(EltSize);
6353 SDValue Cond = DAG.getSetCC(DL,
6354 TLI.getSetCCResultType(N0.getValueType()),
6356 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
6358 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
6360 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
6361 PseudoSourceValue::getConstantPool(), 0, false,
6367 // Check to see if we can perform the "gzip trick", transforming
6368 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
6369 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
6370 N0.getValueType().isInteger() &&
6371 N2.getValueType().isInteger() &&
6372 (N1C->isNullValue() || // (a < 0) ? b : 0
6373 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
6374 EVT XType = N0.getValueType();
6375 EVT AType = N2.getValueType();
6376 if (XType.bitsGE(AType)) {
6377 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
6378 // single-bit constant.
6379 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
6380 unsigned ShCtV = N2C->getAPIntValue().logBase2();
6381 ShCtV = XType.getSizeInBits()-ShCtV-1;
6382 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy());
6383 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
6385 AddToWorkList(Shift.getNode());
6387 if (XType.bitsGT(AType)) {
6388 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6389 AddToWorkList(Shift.getNode());
6392 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6395 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
6397 DAG.getConstant(XType.getSizeInBits()-1,
6398 getShiftAmountTy()));
6399 AddToWorkList(Shift.getNode());
6401 if (XType.bitsGT(AType)) {
6402 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
6403 AddToWorkList(Shift.getNode());
6406 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
6410 // fold select C, 16, 0 -> shl C, 4
6411 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
6412 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) {
6414 // If the caller doesn't want us to simplify this into a zext of a compare,
6416 if (NotExtCompare && N2C->getAPIntValue() == 1)
6419 // Get a SetCC of the condition
6420 // FIXME: Should probably make sure that setcc is legal if we ever have a
6421 // target where it isn't.
6423 // cast from setcc result type to select result type
6425 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
6427 if (N2.getValueType().bitsLT(SCC.getValueType()))
6428 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
6430 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6431 N2.getValueType(), SCC);
6433 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
6434 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
6435 N2.getValueType(), SCC);
6438 AddToWorkList(SCC.getNode());
6439 AddToWorkList(Temp.getNode());
6441 if (N2C->getAPIntValue() == 1)
6444 // shl setcc result by log2 n2c
6445 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
6446 DAG.getConstant(N2C->getAPIntValue().logBase2(),
6447 getShiftAmountTy()));
6450 // Check to see if this is the equivalent of setcc
6451 // FIXME: Turn all of these into setcc if setcc if setcc is legal
6452 // otherwise, go ahead with the folds.
6453 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
6454 EVT XType = N0.getValueType();
6455 if (!LegalOperations ||
6456 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
6457 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
6458 if (Res.getValueType() != VT)
6459 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
6463 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
6464 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
6465 (!LegalOperations ||
6466 TLI.isOperationLegal(ISD::CTLZ, XType))) {
6467 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
6468 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
6469 DAG.getConstant(Log2_32(XType.getSizeInBits()),
6470 getShiftAmountTy()));
6472 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
6473 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
6474 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
6475 XType, DAG.getConstant(0, XType), N0);
6476 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
6477 return DAG.getNode(ISD::SRL, DL, XType,
6478 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
6479 DAG.getConstant(XType.getSizeInBits()-1,
6480 getShiftAmountTy()));
6482 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
6483 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
6484 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
6485 DAG.getConstant(XType.getSizeInBits()-1,
6486 getShiftAmountTy()));
6487 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
6491 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
6492 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6493 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
6494 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
6495 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
6496 EVT XType = N0.getValueType();
6497 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
6498 DAG.getConstant(XType.getSizeInBits()-1,
6499 getShiftAmountTy()));
6500 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
6502 AddToWorkList(Shift.getNode());
6503 AddToWorkList(Add.getNode());
6504 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6506 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
6507 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
6508 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
6509 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
6510 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
6511 EVT XType = N0.getValueType();
6512 if (SubC->isNullValue() && XType.isInteger()) {
6513 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
6515 DAG.getConstant(XType.getSizeInBits()-1,
6516 getShiftAmountTy()));
6517 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
6519 AddToWorkList(Shift.getNode());
6520 AddToWorkList(Add.getNode());
6521 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
6529 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
6530 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
6531 SDValue N1, ISD::CondCode Cond,
6532 DebugLoc DL, bool foldBooleans) {
6533 TargetLowering::DAGCombinerInfo
6534 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
6535 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
6538 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
6539 /// return a DAG expression to select that will generate the same value by
6540 /// multiplying by a magic number. See:
6541 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6542 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
6543 std::vector<SDNode*> Built;
6544 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
6546 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6552 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
6553 /// return a DAG expression to select that will generate the same value by
6554 /// multiplying by a magic number. See:
6555 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
6556 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
6557 std::vector<SDNode*> Built;
6558 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
6560 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
6566 /// FindBaseOffset - Return true if base is a frame index, which is known not
6567 // to alias with anything but itself. Provides base object and offset as results.
6568 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
6569 const GlobalValue *&GV, void *&CV) {
6570 // Assume it is a primitive operation.
6571 Base = Ptr; Offset = 0; GV = 0; CV = 0;
6573 // If it's an adding a simple constant then integrate the offset.
6574 if (Base.getOpcode() == ISD::ADD) {
6575 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
6576 Base = Base.getOperand(0);
6577 Offset += C->getZExtValue();
6581 // Return the underlying GlobalValue, and update the Offset. Return false
6582 // for GlobalAddressSDNode since the same GlobalAddress may be represented
6583 // by multiple nodes with different offsets.
6584 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
6585 GV = G->getGlobal();
6586 Offset += G->getOffset();
6590 // Return the underlying Constant value, and update the Offset. Return false
6591 // for ConstantSDNodes since the same constant pool entry may be represented
6592 // by multiple nodes with different offsets.
6593 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
6594 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
6595 : (void *)C->getConstVal();
6596 Offset += C->getOffset();
6599 // If it's any of the following then it can't alias with anything but itself.
6600 return isa<FrameIndexSDNode>(Base);
6603 /// isAlias - Return true if there is any possibility that the two addresses
6605 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
6606 const Value *SrcValue1, int SrcValueOffset1,
6607 unsigned SrcValueAlign1,
6608 SDValue Ptr2, int64_t Size2,
6609 const Value *SrcValue2, int SrcValueOffset2,
6610 unsigned SrcValueAlign2) const {
6611 // If they are the same then they must be aliases.
6612 if (Ptr1 == Ptr2) return true;
6614 // Gather base node and offset information.
6615 SDValue Base1, Base2;
6616 int64_t Offset1, Offset2;
6617 const GlobalValue *GV1, *GV2;
6619 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
6620 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
6622 // If they have a same base address then check to see if they overlap.
6623 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
6624 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
6626 // If we know what the bases are, and they aren't identical, then we know they
6628 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
6631 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
6632 // compared to the size and offset of the access, we may be able to prove they
6633 // do not alias. This check is conservative for now to catch cases created by
6634 // splitting vector types.
6635 if ((SrcValueAlign1 == SrcValueAlign2) &&
6636 (SrcValueOffset1 != SrcValueOffset2) &&
6637 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
6638 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
6639 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
6641 // There is no overlap between these relatively aligned accesses of similar
6642 // size, return no alias.
6643 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
6647 if (CombinerGlobalAA) {
6648 // Use alias analysis information.
6649 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
6650 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
6651 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
6652 AliasAnalysis::AliasResult AAResult =
6653 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
6654 if (AAResult == AliasAnalysis::NoAlias)
6658 // Otherwise we have to assume they alias.
6662 /// FindAliasInfo - Extracts the relevant alias information from the memory
6663 /// node. Returns true if the operand was a load.
6664 bool DAGCombiner::FindAliasInfo(SDNode *N,
6665 SDValue &Ptr, int64_t &Size,
6666 const Value *&SrcValue,
6667 int &SrcValueOffset,
6668 unsigned &SrcValueAlign) const {
6669 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6670 Ptr = LD->getBasePtr();
6671 Size = LD->getMemoryVT().getSizeInBits() >> 3;
6672 SrcValue = LD->getSrcValue();
6673 SrcValueOffset = LD->getSrcValueOffset();
6674 SrcValueAlign = LD->getOriginalAlignment();
6676 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6677 Ptr = ST->getBasePtr();
6678 Size = ST->getMemoryVT().getSizeInBits() >> 3;
6679 SrcValue = ST->getSrcValue();
6680 SrcValueOffset = ST->getSrcValueOffset();
6681 SrcValueAlign = ST->getOriginalAlignment();
6683 llvm_unreachable("FindAliasInfo expected a memory operand");
6689 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
6690 /// looking for aliasing nodes and adding them to the Aliases vector.
6691 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
6692 SmallVector<SDValue, 8> &Aliases) {
6693 SmallVector<SDValue, 8> Chains; // List of chains to visit.
6694 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
6696 // Get alias information for node.
6699 const Value *SrcValue;
6701 unsigned SrcValueAlign;
6702 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
6706 Chains.push_back(OriginalChain);
6709 // Look at each chain and determine if it is an alias. If so, add it to the
6710 // aliases list. If not, then continue up the chain looking for the next
6712 while (!Chains.empty()) {
6713 SDValue Chain = Chains.back();
6716 // For TokenFactor nodes, look at each operand and only continue up the
6717 // chain until we find two aliases. If we've seen two aliases, assume we'll
6718 // find more and revert to original chain since the xform is unlikely to be
6721 // FIXME: The depth check could be made to return the last non-aliasing
6722 // chain we found before we hit a tokenfactor rather than the original
6724 if (Depth > 6 || Aliases.size() == 2) {
6726 Aliases.push_back(OriginalChain);
6730 // Don't bother if we've been before.
6731 if (!Visited.insert(Chain.getNode()))
6734 switch (Chain.getOpcode()) {
6735 case ISD::EntryToken:
6736 // Entry token is ideal chain operand, but handled in FindBetterChain.
6741 // Get alias information for Chain.
6744 const Value *OpSrcValue;
6745 int OpSrcValueOffset;
6746 unsigned OpSrcValueAlign;
6747 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
6748 OpSrcValue, OpSrcValueOffset,
6751 // If chain is alias then stop here.
6752 if (!(IsLoad && IsOpLoad) &&
6753 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
6754 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
6756 Aliases.push_back(Chain);
6758 // Look further up the chain.
6759 Chains.push_back(Chain.getOperand(0));
6765 case ISD::TokenFactor:
6766 // We have to check each of the operands of the token factor for "small"
6767 // token factors, so we queue them up. Adding the operands to the queue
6768 // (stack) in reverse order maintains the original order and increases the
6769 // likelihood that getNode will find a matching token factor (CSE.)
6770 if (Chain.getNumOperands() > 16) {
6771 Aliases.push_back(Chain);
6774 for (unsigned n = Chain.getNumOperands(); n;)
6775 Chains.push_back(Chain.getOperand(--n));
6780 // For all other instructions we will just have to take what we can get.
6781 Aliases.push_back(Chain);
6787 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
6788 /// for a better chain (aliasing node.)
6789 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
6790 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
6792 // Accumulate all the aliases to this node.
6793 GatherAllAliases(N, OldChain, Aliases);
6795 if (Aliases.size() == 0) {
6796 // If no operands then chain to entry token.
6797 return DAG.getEntryNode();
6798 } else if (Aliases.size() == 1) {
6799 // If a single operand then chain to it. We don't need to revisit it.
6803 // Construct a custom tailored token factor.
6804 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6805 &Aliases[0], Aliases.size());
6808 // SelectionDAG::Combine - This is the entry point for the file.
6810 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
6811 CodeGenOpt::Level OptLevel) {
6812 /// run - This is the main entry point to this class.
6814 DAGCombiner(*this, AA, OptLevel).Run(Level);