1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/Target/TargetData.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/SmallPtrSet.h"
39 #include "llvm/ADT/Statistic.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/CommandLine.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/MathExtras.h"
47 STATISTIC(NodesCombined , "Number of dag nodes combined");
48 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
49 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
54 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
55 cl::desc("Pop up a window to show dags before the first "
58 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
59 cl::desc("Pop up a window to show dags before the second "
62 static const bool ViewDAGCombine1 = false;
63 static const bool ViewDAGCombine2 = false;
67 CombinerAA("combiner-alias-analysis", cl::Hidden,
68 cl::desc("Turn on alias analysis during testing"));
71 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
72 cl::desc("Include global information in alias analysis"));
74 //------------------------------ DAGCombiner ---------------------------------//
76 class VISIBILITY_HIDDEN DAGCombiner {
81 // Worklist of all of the nodes that need to be simplified.
82 std::vector<SDNode*> WorkList;
84 // AA - Used for DAG load/store alias analysis.
87 /// AddUsersToWorkList - When an instruction is simplified, add all users of
88 /// the instruction to the work lists because they might get more simplified
91 void AddUsersToWorkList(SDNode *N) {
92 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
97 /// removeFromWorkList - remove all instances of N from the worklist.
99 void removeFromWorkList(SDNode *N) {
100 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
105 /// AddToWorkList - Add to the work list making sure it's instance is at the
106 /// the back (next to be processed.)
107 void AddToWorkList(SDNode *N) {
108 removeFromWorkList(N);
109 WorkList.push_back(N);
112 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
114 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
116 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
117 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
118 DOUT << " and " << NumTo-1 << " other values\n";
119 std::vector<SDNode*> NowDead;
120 DAG.ReplaceAllUsesWith(N, To, &NowDead);
123 // Push the new nodes and any users onto the worklist
124 for (unsigned i = 0, e = NumTo; i != e; ++i) {
125 AddToWorkList(To[i].Val);
126 AddUsersToWorkList(To[i].Val);
130 // Nodes can be reintroduced into the worklist. Make sure we do not
131 // process a node that has been replaced.
132 removeFromWorkList(N);
133 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
134 removeFromWorkList(NowDead[i]);
136 // Finally, since the node is now dead, remove it from the graph.
138 return SDOperand(N, 0);
141 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
142 return CombineTo(N, &Res, 1, AddTo);
145 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
147 SDOperand To[] = { Res0, Res1 };
148 return CombineTo(N, To, 2, AddTo);
152 /// SimplifyDemandedBits - Check the specified integer node value to see if
153 /// it can be simplified or if things it uses can be simplified by bit
154 /// propagation. If so, return true.
155 bool SimplifyDemandedBits(SDOperand Op) {
156 TargetLowering::TargetLoweringOpt TLO(DAG);
157 uint64_t KnownZero, KnownOne;
158 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
159 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
163 AddToWorkList(Op.Val);
165 // Replace the old value with the new one.
167 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
168 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
171 std::vector<SDNode*> NowDead;
172 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
174 // Push the new node and any (possibly new) users onto the worklist.
175 AddToWorkList(TLO.New.Val);
176 AddUsersToWorkList(TLO.New.Val);
178 // Nodes can end up on the worklist more than once. Make sure we do
179 // not process a node that has been replaced.
180 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
181 removeFromWorkList(NowDead[i]);
183 // Finally, if the node is now dead, remove it from the graph. The node
184 // may not be dead if the replacement process recursively simplified to
185 // something else needing this node.
186 if (TLO.Old.Val->use_empty()) {
187 removeFromWorkList(TLO.Old.Val);
189 // If the operands of this node are only used by the node, they will now
190 // be dead. Make sure to visit them first to delete dead nodes early.
191 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
192 if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
193 AddToWorkList(TLO.Old.Val->getOperand(i).Val);
195 DAG.DeleteNode(TLO.Old.Val);
200 bool CombineToPreIndexedLoadStore(SDNode *N);
201 bool CombineToPostIndexedLoadStore(SDNode *N);
204 /// visit - call the node-specific routine that knows how to fold each
205 /// particular type of node.
206 SDOperand visit(SDNode *N);
208 // Visitation implementation - Implement dag node combining for different
209 // node types. The semantics are as follows:
211 // SDOperand.Val == 0 - No change was made
212 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
213 // otherwise - N should be replaced by the returned Operand.
215 SDOperand visitTokenFactor(SDNode *N);
216 SDOperand visitADD(SDNode *N);
217 SDOperand visitSUB(SDNode *N);
218 SDOperand visitADDC(SDNode *N);
219 SDOperand visitADDE(SDNode *N);
220 SDOperand visitMUL(SDNode *N);
221 SDOperand visitSDIV(SDNode *N);
222 SDOperand visitUDIV(SDNode *N);
223 SDOperand visitSREM(SDNode *N);
224 SDOperand visitUREM(SDNode *N);
225 SDOperand visitMULHU(SDNode *N);
226 SDOperand visitMULHS(SDNode *N);
227 SDOperand visitAND(SDNode *N);
228 SDOperand visitOR(SDNode *N);
229 SDOperand visitXOR(SDNode *N);
230 SDOperand SimplifyVBinOp(SDNode *N);
231 SDOperand visitSHL(SDNode *N);
232 SDOperand visitSRA(SDNode *N);
233 SDOperand visitSRL(SDNode *N);
234 SDOperand visitCTLZ(SDNode *N);
235 SDOperand visitCTTZ(SDNode *N);
236 SDOperand visitCTPOP(SDNode *N);
237 SDOperand visitSELECT(SDNode *N);
238 SDOperand visitSELECT_CC(SDNode *N);
239 SDOperand visitSETCC(SDNode *N);
240 SDOperand visitSIGN_EXTEND(SDNode *N);
241 SDOperand visitZERO_EXTEND(SDNode *N);
242 SDOperand visitANY_EXTEND(SDNode *N);
243 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
244 SDOperand visitTRUNCATE(SDNode *N);
245 SDOperand visitBIT_CONVERT(SDNode *N);
246 SDOperand visitFADD(SDNode *N);
247 SDOperand visitFSUB(SDNode *N);
248 SDOperand visitFMUL(SDNode *N);
249 SDOperand visitFDIV(SDNode *N);
250 SDOperand visitFREM(SDNode *N);
251 SDOperand visitFCOPYSIGN(SDNode *N);
252 SDOperand visitSINT_TO_FP(SDNode *N);
253 SDOperand visitUINT_TO_FP(SDNode *N);
254 SDOperand visitFP_TO_SINT(SDNode *N);
255 SDOperand visitFP_TO_UINT(SDNode *N);
256 SDOperand visitFP_ROUND(SDNode *N);
257 SDOperand visitFP_ROUND_INREG(SDNode *N);
258 SDOperand visitFP_EXTEND(SDNode *N);
259 SDOperand visitFNEG(SDNode *N);
260 SDOperand visitFABS(SDNode *N);
261 SDOperand visitBRCOND(SDNode *N);
262 SDOperand visitBR_CC(SDNode *N);
263 SDOperand visitLOAD(SDNode *N);
264 SDOperand visitSTORE(SDNode *N);
265 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
266 SDOperand visitBUILD_VECTOR(SDNode *N);
267 SDOperand visitCONCAT_VECTORS(SDNode *N);
268 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
270 SDOperand XformToShuffleWithZero(SDNode *N);
271 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
273 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
274 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
275 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
276 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
277 SDOperand N3, ISD::CondCode CC,
278 bool NotExtCompare = false);
279 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
280 ISD::CondCode Cond, bool foldBooleans = true);
281 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
282 SDOperand BuildSDIV(SDNode *N);
283 SDOperand BuildUDIV(SDNode *N);
284 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
285 SDOperand ReduceLoadWidth(SDNode *N);
287 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
288 /// looking for aliasing nodes and adding them to the Aliases vector.
289 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
290 SmallVector<SDOperand, 8> &Aliases);
292 /// isAlias - Return true if there is any possibility that the two addresses
294 bool isAlias(SDOperand Ptr1, int64_t Size1,
295 const Value *SrcValue1, int SrcValueOffset1,
296 SDOperand Ptr2, int64_t Size2,
297 const Value *SrcValue2, int SrcValueOffset2);
299 /// FindAliasInfo - Extracts the relevant alias information from the memory
300 /// node. Returns true if the operand was a load.
301 bool FindAliasInfo(SDNode *N,
302 SDOperand &Ptr, int64_t &Size,
303 const Value *&SrcValue, int &SrcValueOffset);
305 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
306 /// looking for a better chain (aliasing node.)
307 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
310 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
312 TLI(D.getTargetLoweringInfo()),
313 AfterLegalize(false),
316 /// Run - runs the dag combiner on all nodes in the work list
317 void Run(bool RunningAfterLegalize);
321 //===----------------------------------------------------------------------===//
322 // TargetLowering::DAGCombinerInfo implementation
323 //===----------------------------------------------------------------------===//
325 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
326 ((DAGCombiner*)DC)->AddToWorkList(N);
329 SDOperand TargetLowering::DAGCombinerInfo::
330 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
331 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
334 SDOperand TargetLowering::DAGCombinerInfo::
335 CombineTo(SDNode *N, SDOperand Res) {
336 return ((DAGCombiner*)DC)->CombineTo(N, Res);
340 SDOperand TargetLowering::DAGCombinerInfo::
341 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
342 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
346 //===----------------------------------------------------------------------===//
348 //===----------------------------------------------------------------------===//
350 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
351 /// specified expression for the same cost as the expression itself, or 2 if we
352 /// can compute the negated form more cheaply than the expression itself.
353 static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
354 // fneg is removable even if it has multiple uses.
355 if (Op.getOpcode() == ISD::FNEG) return 2;
357 // Don't allow anything with multiple uses.
358 if (!Op.hasOneUse()) return 0;
360 // Don't recurse exponentially.
361 if (Depth > 6) return 0;
363 switch (Op.getOpcode()) {
364 default: return false;
365 case ISD::ConstantFP:
368 // FIXME: determine better conditions for this xform.
369 if (!UnsafeFPMath) return 0;
372 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
375 return isNegatibleForFree(Op.getOperand(1), Depth+1);
377 // We can't turn -(A-B) into B-A when we honor signed zeros.
378 if (!UnsafeFPMath) return 0;
385 if (HonorSignDependentRoundingFPMath()) return 0;
387 // -(X*Y) -> (-X * Y) or (X*-Y)
388 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
391 return isNegatibleForFree(Op.getOperand(1), Depth+1);
396 return isNegatibleForFree(Op.getOperand(0), Depth+1);
400 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
401 /// returns the newly negated expression.
402 static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
403 unsigned Depth = 0) {
404 // fneg is removable even if it has multiple uses.
405 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
407 // Don't allow anything with multiple uses.
408 assert(Op.hasOneUse() && "Unknown reuse!");
410 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
411 switch (Op.getOpcode()) {
412 default: assert(0 && "Unknown code");
413 case ISD::ConstantFP:
414 return DAG.getConstantFP(-cast<ConstantFPSDNode>(Op)->getValue(),
417 // FIXME: determine better conditions for this xform.
418 assert(UnsafeFPMath);
421 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
422 return DAG.getNode(ISD::FSUB, Op.getValueType(),
423 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
426 return DAG.getNode(ISD::FSUB, Op.getValueType(),
427 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1),
430 // We can't turn -(A-B) into B-A when we honor signed zeros.
431 assert(UnsafeFPMath);
434 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
435 if (N0CFP->getValue() == 0.0)
436 return Op.getOperand(1);
439 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
444 assert(!HonorSignDependentRoundingFPMath());
447 if (isNegatibleForFree(Op.getOperand(0), Depth+1))
448 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
449 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
453 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
455 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
460 return DAG.getNode(Op.getOpcode(), Op.getValueType(),
461 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
466 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
467 // that selects between the values 1 and 0, making it equivalent to a setcc.
468 // Also, set the incoming LHS, RHS, and CC references to the appropriate
469 // nodes based on the type of node we are checking. This simplifies life a
470 // bit for the callers.
471 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
473 if (N.getOpcode() == ISD::SETCC) {
474 LHS = N.getOperand(0);
475 RHS = N.getOperand(1);
476 CC = N.getOperand(2);
479 if (N.getOpcode() == ISD::SELECT_CC &&
480 N.getOperand(2).getOpcode() == ISD::Constant &&
481 N.getOperand(3).getOpcode() == ISD::Constant &&
482 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
483 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
484 LHS = N.getOperand(0);
485 RHS = N.getOperand(1);
486 CC = N.getOperand(4);
492 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
493 // one use. If this is true, it allows the users to invert the operation for
494 // free when it is profitable to do so.
495 static bool isOneUseSetCC(SDOperand N) {
496 SDOperand N0, N1, N2;
497 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
502 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
503 MVT::ValueType VT = N0.getValueType();
504 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
505 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
506 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
507 if (isa<ConstantSDNode>(N1)) {
508 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
509 AddToWorkList(OpNode.Val);
510 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
511 } else if (N0.hasOneUse()) {
512 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
513 AddToWorkList(OpNode.Val);
514 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
517 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
518 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
519 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
520 if (isa<ConstantSDNode>(N0)) {
521 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
522 AddToWorkList(OpNode.Val);
523 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
524 } else if (N1.hasOneUse()) {
525 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
526 AddToWorkList(OpNode.Val);
527 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
533 //===----------------------------------------------------------------------===//
534 // Main DAG Combiner implementation
535 //===----------------------------------------------------------------------===//
537 void DAGCombiner::Run(bool RunningAfterLegalize) {
538 // set the instance variable, so that the various visit routines may use it.
539 AfterLegalize = RunningAfterLegalize;
541 // Add all the dag nodes to the worklist.
542 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
543 E = DAG.allnodes_end(); I != E; ++I)
544 WorkList.push_back(I);
546 // Create a dummy node (which is not added to allnodes), that adds a reference
547 // to the root node, preventing it from being deleted, and tracking any
548 // changes of the root.
549 HandleSDNode Dummy(DAG.getRoot());
551 // The root of the dag may dangle to deleted nodes until the dag combiner is
552 // done. Set it to null to avoid confusion.
553 DAG.setRoot(SDOperand());
555 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
556 TargetLowering::DAGCombinerInfo
557 DagCombineInfo(DAG, !RunningAfterLegalize, false, this);
559 // while the worklist isn't empty, inspect the node on the end of it and
560 // try and combine it.
561 while (!WorkList.empty()) {
562 SDNode *N = WorkList.back();
565 // If N has no uses, it is dead. Make sure to revisit all N's operands once
566 // N is deleted from the DAG, since they too may now be dead or may have a
567 // reduced number of uses, allowing other xforms.
568 if (N->use_empty() && N != &Dummy) {
569 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
570 AddToWorkList(N->getOperand(i).Val);
576 SDOperand RV = visit(N);
578 // If nothing happened, try a target-specific DAG combine.
580 assert(N->getOpcode() != ISD::DELETED_NODE &&
581 "Node was deleted but visit returned NULL!");
582 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
583 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
584 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
589 // If we get back the same node we passed in, rather than a new node or
590 // zero, we know that the node must have defined multiple values and
591 // CombineTo was used. Since CombineTo takes care of the worklist
592 // mechanics for us, we have no work to do in this case.
594 assert(N->getOpcode() != ISD::DELETED_NODE &&
595 RV.Val->getOpcode() != ISD::DELETED_NODE &&
596 "Node was deleted but visit returned new node!");
598 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
599 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
601 std::vector<SDNode*> NowDead;
602 if (N->getNumValues() == RV.Val->getNumValues())
603 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
605 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
607 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
610 // Push the new node and any users onto the worklist
611 AddToWorkList(RV.Val);
612 AddUsersToWorkList(RV.Val);
614 // Nodes can be reintroduced into the worklist. Make sure we do not
615 // process a node that has been replaced.
616 removeFromWorkList(N);
617 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
618 removeFromWorkList(NowDead[i]);
620 // Finally, since the node is now dead, remove it from the graph.
626 // If the root changed (e.g. it was a dead load, update the root).
627 DAG.setRoot(Dummy.getValue());
630 SDOperand DAGCombiner::visit(SDNode *N) {
631 switch(N->getOpcode()) {
633 case ISD::TokenFactor: return visitTokenFactor(N);
634 case ISD::ADD: return visitADD(N);
635 case ISD::SUB: return visitSUB(N);
636 case ISD::ADDC: return visitADDC(N);
637 case ISD::ADDE: return visitADDE(N);
638 case ISD::MUL: return visitMUL(N);
639 case ISD::SDIV: return visitSDIV(N);
640 case ISD::UDIV: return visitUDIV(N);
641 case ISD::SREM: return visitSREM(N);
642 case ISD::UREM: return visitUREM(N);
643 case ISD::MULHU: return visitMULHU(N);
644 case ISD::MULHS: return visitMULHS(N);
645 case ISD::AND: return visitAND(N);
646 case ISD::OR: return visitOR(N);
647 case ISD::XOR: return visitXOR(N);
648 case ISD::SHL: return visitSHL(N);
649 case ISD::SRA: return visitSRA(N);
650 case ISD::SRL: return visitSRL(N);
651 case ISD::CTLZ: return visitCTLZ(N);
652 case ISD::CTTZ: return visitCTTZ(N);
653 case ISD::CTPOP: return visitCTPOP(N);
654 case ISD::SELECT: return visitSELECT(N);
655 case ISD::SELECT_CC: return visitSELECT_CC(N);
656 case ISD::SETCC: return visitSETCC(N);
657 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
658 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
659 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
660 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
661 case ISD::TRUNCATE: return visitTRUNCATE(N);
662 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
663 case ISD::FADD: return visitFADD(N);
664 case ISD::FSUB: return visitFSUB(N);
665 case ISD::FMUL: return visitFMUL(N);
666 case ISD::FDIV: return visitFDIV(N);
667 case ISD::FREM: return visitFREM(N);
668 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
669 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
670 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
671 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
672 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
673 case ISD::FP_ROUND: return visitFP_ROUND(N);
674 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
675 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
676 case ISD::FNEG: return visitFNEG(N);
677 case ISD::FABS: return visitFABS(N);
678 case ISD::BRCOND: return visitBRCOND(N);
679 case ISD::BR_CC: return visitBR_CC(N);
680 case ISD::LOAD: return visitLOAD(N);
681 case ISD::STORE: return visitSTORE(N);
682 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
683 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
684 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
685 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
690 /// getInputChainForNode - Given a node, return its input chain if it has one,
691 /// otherwise return a null sd operand.
692 static SDOperand getInputChainForNode(SDNode *N) {
693 if (unsigned NumOps = N->getNumOperands()) {
694 if (N->getOperand(0).getValueType() == MVT::Other)
695 return N->getOperand(0);
696 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
697 return N->getOperand(NumOps-1);
698 for (unsigned i = 1; i < NumOps-1; ++i)
699 if (N->getOperand(i).getValueType() == MVT::Other)
700 return N->getOperand(i);
702 return SDOperand(0, 0);
705 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
706 // If N has two operands, where one has an input chain equal to the other,
707 // the 'other' chain is redundant.
708 if (N->getNumOperands() == 2) {
709 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
710 return N->getOperand(0);
711 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
712 return N->getOperand(1);
715 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
716 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
717 SmallPtrSet<SDNode*, 16> SeenOps;
718 bool Changed = false; // If we should replace this token factor.
720 // Start out with this token factor.
723 // Iterate through token factors. The TFs grows when new token factors are
725 for (unsigned i = 0; i < TFs.size(); ++i) {
728 // Check each of the operands.
729 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
730 SDOperand Op = TF->getOperand(i);
732 switch (Op.getOpcode()) {
733 case ISD::EntryToken:
734 // Entry tokens don't need to be added to the list. They are
739 case ISD::TokenFactor:
740 if ((CombinerAA || Op.hasOneUse()) &&
741 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
742 // Queue up for processing.
743 TFs.push_back(Op.Val);
744 // Clean up in case the token factor is removed.
745 AddToWorkList(Op.Val);
752 // Only add if it isn't already in the list.
753 if (SeenOps.insert(Op.Val))
764 // If we've change things around then replace token factor.
766 if (Ops.size() == 0) {
767 // The entry token is the only possible outcome.
768 Result = DAG.getEntryNode();
770 // New and improved token factor.
771 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
774 // Don't add users to work list.
775 return CombineTo(N, Result, false);
782 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
783 MVT::ValueType VT = N0.getValueType();
784 SDOperand N00 = N0.getOperand(0);
785 SDOperand N01 = N0.getOperand(1);
786 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
787 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
788 isa<ConstantSDNode>(N00.getOperand(1))) {
789 N0 = DAG.getNode(ISD::ADD, VT,
790 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
791 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
792 return DAG.getNode(ISD::ADD, VT, N0, N1);
798 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
800 MVT::ValueType VT = N->getValueType(0);
801 unsigned Opc = N->getOpcode();
802 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
803 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
804 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
805 ISD::CondCode CC = ISD::SETCC_INVALID;
807 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
809 SDOperand CCOp = Slct.getOperand(0);
810 if (CCOp.getOpcode() == ISD::SETCC)
811 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
814 bool DoXform = false;
816 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
818 if (LHS.getOpcode() == ISD::Constant &&
819 cast<ConstantSDNode>(LHS)->isNullValue())
821 else if (CC != ISD::SETCC_INVALID &&
822 RHS.getOpcode() == ISD::Constant &&
823 cast<ConstantSDNode>(RHS)->isNullValue()) {
825 bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType()
826 : Slct.getOperand(0).getOperand(0).getValueType());
827 CC = ISD::getSetCCInverse(CC, isInt);
833 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
835 return DAG.getSelectCC(OtherOp, Result,
836 Slct.getOperand(0), Slct.getOperand(1), CC);
837 SDOperand CCOp = Slct.getOperand(0);
839 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
840 CCOp.getOperand(1), CC);
841 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
846 SDOperand DAGCombiner::visitADD(SDNode *N) {
847 SDOperand N0 = N->getOperand(0);
848 SDOperand N1 = N->getOperand(1);
849 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
850 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
851 MVT::ValueType VT = N0.getValueType();
854 if (MVT::isVector(VT)) {
855 SDOperand FoldedVOp = SimplifyVBinOp(N);
856 if (FoldedVOp.Val) return FoldedVOp;
859 // fold (add x, undef) -> undef
860 if (N0.getOpcode() == ISD::UNDEF)
862 if (N1.getOpcode() == ISD::UNDEF)
864 // fold (add c1, c2) -> c1+c2
866 return DAG.getNode(ISD::ADD, VT, N0, N1);
867 // canonicalize constant to RHS
869 return DAG.getNode(ISD::ADD, VT, N1, N0);
870 // fold (add x, 0) -> x
871 if (N1C && N1C->isNullValue())
873 // fold ((c1-A)+c2) -> (c1+c2)-A
874 if (N1C && N0.getOpcode() == ISD::SUB)
875 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
876 return DAG.getNode(ISD::SUB, VT,
877 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
880 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
883 // fold ((0-A) + B) -> B-A
884 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
885 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
886 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
887 // fold (A + (0-B)) -> A-B
888 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
889 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
890 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
891 // fold (A+(B-A)) -> B
892 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
893 return N1.getOperand(0);
895 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
896 return SDOperand(N, 0);
898 // fold (a+b) -> (a|b) iff a and b share no bits.
899 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
900 uint64_t LHSZero, LHSOne;
901 uint64_t RHSZero, RHSOne;
902 uint64_t Mask = MVT::getIntVTBitMask(VT);
903 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
905 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
907 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
908 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
909 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
910 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
911 return DAG.getNode(ISD::OR, VT, N0, N1);
915 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
916 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) {
917 SDOperand Result = combineShlAddConstant(N0, N1, DAG);
918 if (Result.Val) return Result;
920 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) {
921 SDOperand Result = combineShlAddConstant(N1, N0, DAG);
922 if (Result.Val) return Result;
925 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
926 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
927 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
928 if (Result.Val) return Result;
930 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
931 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
932 if (Result.Val) return Result;
938 SDOperand DAGCombiner::visitADDC(SDNode *N) {
939 SDOperand N0 = N->getOperand(0);
940 SDOperand N1 = N->getOperand(1);
941 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
942 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
943 MVT::ValueType VT = N0.getValueType();
945 // If the flag result is dead, turn this into an ADD.
946 if (N->hasNUsesOfValue(0, 1))
947 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
948 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
950 // canonicalize constant to RHS.
952 SDOperand Ops[] = { N1, N0 };
953 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
956 // fold (addc x, 0) -> x + no carry out
957 if (N1C && N1C->isNullValue())
958 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
960 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
961 uint64_t LHSZero, LHSOne;
962 uint64_t RHSZero, RHSOne;
963 uint64_t Mask = MVT::getIntVTBitMask(VT);
964 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
966 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
968 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
969 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
970 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
971 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
972 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
973 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
979 SDOperand DAGCombiner::visitADDE(SDNode *N) {
980 SDOperand N0 = N->getOperand(0);
981 SDOperand N1 = N->getOperand(1);
982 SDOperand CarryIn = N->getOperand(2);
983 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
984 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
985 //MVT::ValueType VT = N0.getValueType();
987 // canonicalize constant to RHS
989 SDOperand Ops[] = { N1, N0, CarryIn };
990 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
993 // fold (adde x, y, false) -> (addc x, y)
994 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
995 SDOperand Ops[] = { N1, N0 };
996 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
1004 SDOperand DAGCombiner::visitSUB(SDNode *N) {
1005 SDOperand N0 = N->getOperand(0);
1006 SDOperand N1 = N->getOperand(1);
1007 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1008 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1009 MVT::ValueType VT = N0.getValueType();
1012 if (MVT::isVector(VT)) {
1013 SDOperand FoldedVOp = SimplifyVBinOp(N);
1014 if (FoldedVOp.Val) return FoldedVOp;
1017 // fold (sub x, x) -> 0
1019 return DAG.getConstant(0, N->getValueType(0));
1020 // fold (sub c1, c2) -> c1-c2
1022 return DAG.getNode(ISD::SUB, VT, N0, N1);
1023 // fold (sub x, c) -> (add x, -c)
1025 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
1026 // fold (A+B)-A -> B
1027 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1028 return N0.getOperand(1);
1029 // fold (A+B)-B -> A
1030 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1031 return N0.getOperand(0);
1032 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
1033 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
1034 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
1035 if (Result.Val) return Result;
1037 // If either operand of a sub is undef, the result is undef
1038 if (N0.getOpcode() == ISD::UNDEF)
1040 if (N1.getOpcode() == ISD::UNDEF)
1046 SDOperand DAGCombiner::visitMUL(SDNode *N) {
1047 SDOperand N0 = N->getOperand(0);
1048 SDOperand N1 = N->getOperand(1);
1049 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1050 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1051 MVT::ValueType VT = N0.getValueType();
1054 if (MVT::isVector(VT)) {
1055 SDOperand FoldedVOp = SimplifyVBinOp(N);
1056 if (FoldedVOp.Val) return FoldedVOp;
1059 // fold (mul x, undef) -> 0
1060 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1061 return DAG.getConstant(0, VT);
1062 // fold (mul c1, c2) -> c1*c2
1064 return DAG.getNode(ISD::MUL, VT, N0, N1);
1065 // canonicalize constant to RHS
1067 return DAG.getNode(ISD::MUL, VT, N1, N0);
1068 // fold (mul x, 0) -> 0
1069 if (N1C && N1C->isNullValue())
1071 // fold (mul x, -1) -> 0-x
1072 if (N1C && N1C->isAllOnesValue())
1073 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1074 // fold (mul x, (1 << c)) -> x << c
1075 if (N1C && isPowerOf2_64(N1C->getValue()))
1076 return DAG.getNode(ISD::SHL, VT, N0,
1077 DAG.getConstant(Log2_64(N1C->getValue()),
1078 TLI.getShiftAmountTy()));
1079 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1080 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
1081 // FIXME: If the input is something that is easily negated (e.g. a
1082 // single-use add), we should put the negate there.
1083 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
1084 DAG.getNode(ISD::SHL, VT, N0,
1085 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
1086 TLI.getShiftAmountTy())));
1089 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1090 if (N1C && N0.getOpcode() == ISD::SHL &&
1091 isa<ConstantSDNode>(N0.getOperand(1))) {
1092 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
1093 AddToWorkList(C3.Val);
1094 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
1097 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1100 SDOperand Sh(0,0), Y(0,0);
1101 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1102 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1103 N0.Val->hasOneUse()) {
1105 } else if (N1.getOpcode() == ISD::SHL &&
1106 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
1110 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
1111 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
1114 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1115 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1116 isa<ConstantSDNode>(N0.getOperand(1))) {
1117 return DAG.getNode(ISD::ADD, VT,
1118 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
1119 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
1123 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
1130 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
1131 SDOperand N0 = N->getOperand(0);
1132 SDOperand N1 = N->getOperand(1);
1133 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1134 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1135 MVT::ValueType VT = N->getValueType(0);
1138 if (MVT::isVector(VT)) {
1139 SDOperand FoldedVOp = SimplifyVBinOp(N);
1140 if (FoldedVOp.Val) return FoldedVOp;
1143 // fold (sdiv c1, c2) -> c1/c2
1144 if (N0C && N1C && !N1C->isNullValue())
1145 return DAG.getNode(ISD::SDIV, VT, N0, N1);
1146 // fold (sdiv X, 1) -> X
1147 if (N1C && N1C->getSignExtended() == 1LL)
1149 // fold (sdiv X, -1) -> 0-X
1150 if (N1C && N1C->isAllOnesValue())
1151 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
1152 // If we know the sign bits of both operands are zero, strength reduce to a
1153 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1154 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1155 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1156 DAG.MaskedValueIsZero(N0, SignBit))
1157 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
1158 // fold (sdiv X, pow2) -> simple ops after legalize
1159 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
1160 (isPowerOf2_64(N1C->getSignExtended()) ||
1161 isPowerOf2_64(-N1C->getSignExtended()))) {
1162 // If dividing by powers of two is cheap, then don't perform the following
1164 if (TLI.isPow2DivCheap())
1166 int64_t pow2 = N1C->getSignExtended();
1167 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
1168 unsigned lg2 = Log2_64(abs2);
1169 // Splat the sign bit into the register
1170 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1171 DAG.getConstant(MVT::getSizeInBits(VT)-1,
1172 TLI.getShiftAmountTy()));
1173 AddToWorkList(SGN.Val);
1174 // Add (N0 < 0) ? abs2 - 1 : 0;
1175 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1176 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
1177 TLI.getShiftAmountTy()));
1178 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
1179 AddToWorkList(SRL.Val);
1180 AddToWorkList(ADD.Val); // Divide by pow2
1181 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
1182 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
1183 // If we're dividing by a positive value, we're done. Otherwise, we must
1184 // negate the result.
1187 AddToWorkList(SRA.Val);
1188 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
1190 // if integer divide is expensive and we satisfy the requirements, emit an
1191 // alternate sequence.
1192 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
1193 !TLI.isIntDivCheap()) {
1194 SDOperand Op = BuildSDIV(N);
1195 if (Op.Val) return Op;
1199 if (N0.getOpcode() == ISD::UNDEF)
1200 return DAG.getConstant(0, VT);
1201 // X / undef -> undef
1202 if (N1.getOpcode() == ISD::UNDEF)
1208 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
1209 SDOperand N0 = N->getOperand(0);
1210 SDOperand N1 = N->getOperand(1);
1211 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1212 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1213 MVT::ValueType VT = N->getValueType(0);
1216 if (MVT::isVector(VT)) {
1217 SDOperand FoldedVOp = SimplifyVBinOp(N);
1218 if (FoldedVOp.Val) return FoldedVOp;
1221 // fold (udiv c1, c2) -> c1/c2
1222 if (N0C && N1C && !N1C->isNullValue())
1223 return DAG.getNode(ISD::UDIV, VT, N0, N1);
1224 // fold (udiv x, (1 << c)) -> x >>u c
1225 if (N1C && isPowerOf2_64(N1C->getValue()))
1226 return DAG.getNode(ISD::SRL, VT, N0,
1227 DAG.getConstant(Log2_64(N1C->getValue()),
1228 TLI.getShiftAmountTy()));
1229 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1230 if (N1.getOpcode() == ISD::SHL) {
1231 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1232 if (isPowerOf2_64(SHC->getValue())) {
1233 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1234 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
1235 DAG.getConstant(Log2_64(SHC->getValue()),
1237 AddToWorkList(Add.Val);
1238 return DAG.getNode(ISD::SRL, VT, N0, Add);
1242 // fold (udiv x, c) -> alternate
1243 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
1244 SDOperand Op = BuildUDIV(N);
1245 if (Op.Val) return Op;
1249 if (N0.getOpcode() == ISD::UNDEF)
1250 return DAG.getConstant(0, VT);
1251 // X / undef -> undef
1252 if (N1.getOpcode() == ISD::UNDEF)
1258 SDOperand DAGCombiner::visitSREM(SDNode *N) {
1259 SDOperand N0 = N->getOperand(0);
1260 SDOperand N1 = N->getOperand(1);
1261 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1262 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1263 MVT::ValueType VT = N->getValueType(0);
1265 // fold (srem c1, c2) -> c1%c2
1266 if (N0C && N1C && !N1C->isNullValue())
1267 return DAG.getNode(ISD::SREM, VT, N0, N1);
1268 // If we know the sign bits of both operands are zero, strength reduce to a
1269 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1270 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
1271 if (DAG.MaskedValueIsZero(N1, SignBit) &&
1272 DAG.MaskedValueIsZero(N0, SignBit))
1273 return DAG.getNode(ISD::UREM, VT, N0, N1);
1275 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1276 // the remainder operation.
1277 if (N1C && !N1C->isNullValue()) {
1278 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
1279 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1280 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1281 AddToWorkList(Div.Val);
1282 AddToWorkList(Mul.Val);
1287 if (N0.getOpcode() == ISD::UNDEF)
1288 return DAG.getConstant(0, VT);
1289 // X % undef -> undef
1290 if (N1.getOpcode() == ISD::UNDEF)
1296 SDOperand DAGCombiner::visitUREM(SDNode *N) {
1297 SDOperand N0 = N->getOperand(0);
1298 SDOperand N1 = N->getOperand(1);
1299 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1300 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1301 MVT::ValueType VT = N->getValueType(0);
1303 // fold (urem c1, c2) -> c1%c2
1304 if (N0C && N1C && !N1C->isNullValue())
1305 return DAG.getNode(ISD::UREM, VT, N0, N1);
1306 // fold (urem x, pow2) -> (and x, pow2-1)
1307 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
1308 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
1309 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1310 if (N1.getOpcode() == ISD::SHL) {
1311 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1312 if (isPowerOf2_64(SHC->getValue())) {
1313 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
1314 AddToWorkList(Add.Val);
1315 return DAG.getNode(ISD::AND, VT, N0, Add);
1320 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
1321 // the remainder operation.
1322 if (N1C && !N1C->isNullValue()) {
1323 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
1324 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
1325 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
1326 AddToWorkList(Div.Val);
1327 AddToWorkList(Mul.Val);
1332 if (N0.getOpcode() == ISD::UNDEF)
1333 return DAG.getConstant(0, VT);
1334 // X % undef -> undef
1335 if (N1.getOpcode() == ISD::UNDEF)
1341 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
1342 SDOperand N0 = N->getOperand(0);
1343 SDOperand N1 = N->getOperand(1);
1344 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1345 MVT::ValueType VT = N->getValueType(0);
1347 // fold (mulhs x, 0) -> 0
1348 if (N1C && N1C->isNullValue())
1350 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1351 if (N1C && N1C->getValue() == 1)
1352 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1353 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1354 TLI.getShiftAmountTy()));
1355 // fold (mulhs x, undef) -> 0
1356 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1357 return DAG.getConstant(0, VT);
1362 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
1363 SDOperand N0 = N->getOperand(0);
1364 SDOperand N1 = N->getOperand(1);
1365 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1366 MVT::ValueType VT = N->getValueType(0);
1368 // fold (mulhu x, 0) -> 0
1369 if (N1C && N1C->isNullValue())
1371 // fold (mulhu x, 1) -> 0
1372 if (N1C && N1C->getValue() == 1)
1373 return DAG.getConstant(0, N0.getValueType());
1374 // fold (mulhu x, undef) -> 0
1375 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1376 return DAG.getConstant(0, VT);
1381 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1382 /// two operands of the same opcode, try to simplify it.
1383 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1384 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1385 MVT::ValueType VT = N0.getValueType();
1386 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1388 // For each of OP in AND/OR/XOR:
1389 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1390 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1391 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1392 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1393 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1394 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1395 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1396 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1397 N0.getOperand(0).getValueType(),
1398 N0.getOperand(0), N1.getOperand(0));
1399 AddToWorkList(ORNode.Val);
1400 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1403 // For each of OP in SHL/SRL/SRA/AND...
1404 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1405 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1406 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1407 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1408 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1409 N0.getOperand(1) == N1.getOperand(1)) {
1410 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1411 N0.getOperand(0).getValueType(),
1412 N0.getOperand(0), N1.getOperand(0));
1413 AddToWorkList(ORNode.Val);
1414 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1420 SDOperand DAGCombiner::visitAND(SDNode *N) {
1421 SDOperand N0 = N->getOperand(0);
1422 SDOperand N1 = N->getOperand(1);
1423 SDOperand LL, LR, RL, RR, CC0, CC1;
1424 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1425 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1426 MVT::ValueType VT = N1.getValueType();
1429 if (MVT::isVector(VT)) {
1430 SDOperand FoldedVOp = SimplifyVBinOp(N);
1431 if (FoldedVOp.Val) return FoldedVOp;
1434 // fold (and x, undef) -> 0
1435 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1436 return DAG.getConstant(0, VT);
1437 // fold (and c1, c2) -> c1&c2
1439 return DAG.getNode(ISD::AND, VT, N0, N1);
1440 // canonicalize constant to RHS
1442 return DAG.getNode(ISD::AND, VT, N1, N0);
1443 // fold (and x, -1) -> x
1444 if (N1C && N1C->isAllOnesValue())
1446 // if (and x, c) is known to be zero, return 0
1447 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1448 return DAG.getConstant(0, VT);
1450 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1453 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1454 if (N1C && N0.getOpcode() == ISD::OR)
1455 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1456 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1458 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1459 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1460 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1461 if (DAG.MaskedValueIsZero(N0.getOperand(0),
1462 ~N1C->getValue() & InMask)) {
1463 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1466 // Replace uses of the AND with uses of the Zero extend node.
1469 // We actually want to replace all uses of the any_extend with the
1470 // zero_extend, to avoid duplicating things. This will later cause this
1471 // AND to be folded.
1472 CombineTo(N0.Val, Zext);
1473 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1476 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1477 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1478 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1479 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1481 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1482 MVT::isInteger(LL.getValueType())) {
1483 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1484 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1485 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1486 AddToWorkList(ORNode.Val);
1487 return DAG.getSetCC(VT, ORNode, LR, Op1);
1489 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1490 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1491 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1492 AddToWorkList(ANDNode.Val);
1493 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1495 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1496 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1497 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1498 AddToWorkList(ORNode.Val);
1499 return DAG.getSetCC(VT, ORNode, LR, Op1);
1502 // canonicalize equivalent to ll == rl
1503 if (LL == RR && LR == RL) {
1504 Op1 = ISD::getSetCCSwappedOperands(Op1);
1507 if (LL == RL && LR == RR) {
1508 bool isInteger = MVT::isInteger(LL.getValueType());
1509 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1510 if (Result != ISD::SETCC_INVALID)
1511 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1515 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1516 if (N0.getOpcode() == N1.getOpcode()) {
1517 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1518 if (Tmp.Val) return Tmp;
1521 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1522 // fold (and (sra)) -> (and (srl)) when possible.
1523 if (!MVT::isVector(VT) &&
1524 SimplifyDemandedBits(SDOperand(N, 0)))
1525 return SDOperand(N, 0);
1526 // fold (zext_inreg (extload x)) -> (zextload x)
1527 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
1528 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1529 MVT::ValueType EVT = LN0->getLoadedVT();
1530 // If we zero all the possible extended bits, then we can turn this into
1531 // a zextload if we are running before legalize or the operation is legal.
1532 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1533 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1534 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1535 LN0->getBasePtr(), LN0->getSrcValue(),
1536 LN0->getSrcValueOffset(), EVT,
1538 LN0->getAlignment());
1540 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1541 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1544 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1545 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
1547 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1548 MVT::ValueType EVT = LN0->getLoadedVT();
1549 // If we zero all the possible extended bits, then we can turn this into
1550 // a zextload if we are running before legalize or the operation is legal.
1551 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1552 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1553 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1554 LN0->getBasePtr(), LN0->getSrcValue(),
1555 LN0->getSrcValueOffset(), EVT,
1557 LN0->getAlignment());
1559 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1560 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1564 // fold (and (load x), 255) -> (zextload x, i8)
1565 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1566 if (N1C && N0.getOpcode() == ISD::LOAD) {
1567 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1568 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1569 LN0->getAddressingMode() == ISD::UNINDEXED &&
1571 MVT::ValueType EVT, LoadedVT;
1572 if (N1C->getValue() == 255)
1574 else if (N1C->getValue() == 65535)
1576 else if (N1C->getValue() == ~0U)
1581 LoadedVT = LN0->getLoadedVT();
1582 if (EVT != MVT::Other && LoadedVT > EVT &&
1583 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1584 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1585 // For big endian targets, we need to add an offset to the pointer to
1586 // load the correct bytes. For little endian systems, we merely need to
1587 // read fewer bytes from the same pointer.
1589 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1590 SDOperand NewPtr = LN0->getBasePtr();
1591 if (!TLI.isLittleEndian())
1592 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1593 DAG.getConstant(PtrOff, PtrType));
1594 AddToWorkList(NewPtr.Val);
1596 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1597 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
1598 LN0->isVolatile(), LN0->getAlignment());
1600 CombineTo(N0.Val, Load, Load.getValue(1));
1601 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1609 SDOperand DAGCombiner::visitOR(SDNode *N) {
1610 SDOperand N0 = N->getOperand(0);
1611 SDOperand N1 = N->getOperand(1);
1612 SDOperand LL, LR, RL, RR, CC0, CC1;
1613 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1614 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1615 MVT::ValueType VT = N1.getValueType();
1616 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1619 if (MVT::isVector(VT)) {
1620 SDOperand FoldedVOp = SimplifyVBinOp(N);
1621 if (FoldedVOp.Val) return FoldedVOp;
1624 // fold (or x, undef) -> -1
1625 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1626 return DAG.getConstant(~0ULL, VT);
1627 // fold (or c1, c2) -> c1|c2
1629 return DAG.getNode(ISD::OR, VT, N0, N1);
1630 // canonicalize constant to RHS
1632 return DAG.getNode(ISD::OR, VT, N1, N0);
1633 // fold (or x, 0) -> x
1634 if (N1C && N1C->isNullValue())
1636 // fold (or x, -1) -> -1
1637 if (N1C && N1C->isAllOnesValue())
1639 // fold (or x, c) -> c iff (x & ~c) == 0
1641 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1644 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1647 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1648 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1649 isa<ConstantSDNode>(N0.getOperand(1))) {
1650 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1651 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1653 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1655 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1656 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1657 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1658 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1660 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1661 MVT::isInteger(LL.getValueType())) {
1662 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1663 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1664 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1665 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1666 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1667 AddToWorkList(ORNode.Val);
1668 return DAG.getSetCC(VT, ORNode, LR, Op1);
1670 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1671 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1672 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1673 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1674 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1675 AddToWorkList(ANDNode.Val);
1676 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1679 // canonicalize equivalent to ll == rl
1680 if (LL == RR && LR == RL) {
1681 Op1 = ISD::getSetCCSwappedOperands(Op1);
1684 if (LL == RL && LR == RR) {
1685 bool isInteger = MVT::isInteger(LL.getValueType());
1686 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1687 if (Result != ISD::SETCC_INVALID)
1688 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1692 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1693 if (N0.getOpcode() == N1.getOpcode()) {
1694 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1695 if (Tmp.Val) return Tmp;
1698 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1699 if (N0.getOpcode() == ISD::AND &&
1700 N1.getOpcode() == ISD::AND &&
1701 N0.getOperand(1).getOpcode() == ISD::Constant &&
1702 N1.getOperand(1).getOpcode() == ISD::Constant &&
1703 // Don't increase # computations.
1704 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1705 // We can only do this xform if we know that bits from X that are set in C2
1706 // but not in C1 are already zero. Likewise for Y.
1707 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1708 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1710 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1711 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1712 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1713 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1718 // See if this is some rotate idiom.
1719 if (SDNode *Rot = MatchRotate(N0, N1))
1720 return SDOperand(Rot, 0);
1726 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1727 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1728 if (Op.getOpcode() == ISD::AND) {
1729 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1730 Mask = Op.getOperand(1);
1731 Op = Op.getOperand(0);
1737 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1745 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1746 // idioms for rotate, and if the target supports rotation instructions, generate
1748 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1749 // Must be a legal type. Expanded an promoted things won't work with rotates.
1750 MVT::ValueType VT = LHS.getValueType();
1751 if (!TLI.isTypeLegal(VT)) return 0;
1753 // The target must have at least one rotate flavor.
1754 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1755 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1756 if (!HasROTL && !HasROTR) return 0;
1758 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1759 SDOperand LHSShift; // The shift.
1760 SDOperand LHSMask; // AND value if any.
1761 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1762 return 0; // Not part of a rotate.
1764 SDOperand RHSShift; // The shift.
1765 SDOperand RHSMask; // AND value if any.
1766 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1767 return 0; // Not part of a rotate.
1769 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1770 return 0; // Not shifting the same value.
1772 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1773 return 0; // Shifts must disagree.
1775 // Canonicalize shl to left side in a shl/srl pair.
1776 if (RHSShift.getOpcode() == ISD::SHL) {
1777 std::swap(LHS, RHS);
1778 std::swap(LHSShift, RHSShift);
1779 std::swap(LHSMask , RHSMask );
1782 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1783 SDOperand LHSShiftArg = LHSShift.getOperand(0);
1784 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
1785 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
1787 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1788 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1789 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
1790 RHSShiftAmt.getOpcode() == ISD::Constant) {
1791 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue();
1792 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue();
1793 if ((LShVal + RShVal) != OpSizeInBits)
1798 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
1800 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
1802 // If there is an AND of either shifted operand, apply it to the result.
1803 if (LHSMask.Val || RHSMask.Val) {
1804 uint64_t Mask = MVT::getIntVTBitMask(VT);
1807 uint64_t RHSBits = (1ULL << LShVal)-1;
1808 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1811 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1812 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1815 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1821 // If there is a mask here, and we have a variable shift, we can't be sure
1822 // that we're masking out the right stuff.
1823 if (LHSMask.Val || RHSMask.Val)
1826 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1827 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1828 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
1829 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
1830 if (ConstantSDNode *SUBC =
1831 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
1832 if (SUBC->getValue() == OpSizeInBits)
1834 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1836 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1840 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1841 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1842 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
1843 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
1844 if (ConstantSDNode *SUBC =
1845 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
1846 if (SUBC->getValue() == OpSizeInBits)
1848 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1850 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1854 // Look for sign/zext/any-extended cases:
1855 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1856 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1857 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
1858 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
1859 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
1860 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
1861 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
1862 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
1863 if (RExtOp0.getOpcode() == ISD::SUB &&
1864 RExtOp0.getOperand(1) == LExtOp0) {
1865 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1867 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
1868 // (rotl x, (sub 32, y))
1869 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
1870 if (SUBC->getValue() == OpSizeInBits) {
1872 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1874 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
1877 } else if (LExtOp0.getOpcode() == ISD::SUB &&
1878 RExtOp0 == LExtOp0.getOperand(1)) {
1879 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
1881 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) ->
1882 // (rotr x, (sub 32, y))
1883 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
1884 if (SUBC->getValue() == OpSizeInBits) {
1886 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val;
1888 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
1898 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1899 SDOperand N0 = N->getOperand(0);
1900 SDOperand N1 = N->getOperand(1);
1901 SDOperand LHS, RHS, CC;
1902 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1903 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1904 MVT::ValueType VT = N0.getValueType();
1907 if (MVT::isVector(VT)) {
1908 SDOperand FoldedVOp = SimplifyVBinOp(N);
1909 if (FoldedVOp.Val) return FoldedVOp;
1912 // fold (xor x, undef) -> undef
1913 if (N0.getOpcode() == ISD::UNDEF)
1915 if (N1.getOpcode() == ISD::UNDEF)
1917 // fold (xor c1, c2) -> c1^c2
1919 return DAG.getNode(ISD::XOR, VT, N0, N1);
1920 // canonicalize constant to RHS
1922 return DAG.getNode(ISD::XOR, VT, N1, N0);
1923 // fold (xor x, 0) -> x
1924 if (N1C && N1C->isNullValue())
1927 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1930 // fold !(x cc y) -> (x !cc y)
1931 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1932 bool isInt = MVT::isInteger(LHS.getValueType());
1933 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1935 if (N0.getOpcode() == ISD::SETCC)
1936 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1937 if (N0.getOpcode() == ISD::SELECT_CC)
1938 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1939 assert(0 && "Unhandled SetCC Equivalent!");
1942 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1943 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
1944 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1945 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1946 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1947 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1948 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1949 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1950 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1951 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1954 // fold !(x or y) -> (!x and !y) iff x or y are constants
1955 if (N1C && N1C->isAllOnesValue() &&
1956 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1957 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1958 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1959 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1960 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1961 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1962 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1963 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1966 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1967 if (N1C && N0.getOpcode() == ISD::XOR) {
1968 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1969 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1971 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1972 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1974 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1975 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1977 // fold (xor x, x) -> 0
1979 if (!MVT::isVector(VT)) {
1980 return DAG.getConstant(0, VT);
1981 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1982 // Produce a vector of zeros.
1983 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
1984 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1985 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1989 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1990 if (N0.getOpcode() == N1.getOpcode()) {
1991 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1992 if (Tmp.Val) return Tmp;
1995 // Simplify the expression using non-local knowledge.
1996 if (!MVT::isVector(VT) &&
1997 SimplifyDemandedBits(SDOperand(N, 0)))
1998 return SDOperand(N, 0);
2003 SDOperand DAGCombiner::visitSHL(SDNode *N) {
2004 SDOperand N0 = N->getOperand(0);
2005 SDOperand N1 = N->getOperand(1);
2006 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2007 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2008 MVT::ValueType VT = N0.getValueType();
2009 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2011 // fold (shl c1, c2) -> c1<<c2
2013 return DAG.getNode(ISD::SHL, VT, N0, N1);
2014 // fold (shl 0, x) -> 0
2015 if (N0C && N0C->isNullValue())
2017 // fold (shl x, c >= size(x)) -> undef
2018 if (N1C && N1C->getValue() >= OpSizeInBits)
2019 return DAG.getNode(ISD::UNDEF, VT);
2020 // fold (shl x, 0) -> x
2021 if (N1C && N1C->isNullValue())
2023 // if (shl x, c) is known to be zero, return 0
2024 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
2025 return DAG.getConstant(0, VT);
2026 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2027 return SDOperand(N, 0);
2028 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
2029 if (N1C && N0.getOpcode() == ISD::SHL &&
2030 N0.getOperand(1).getOpcode() == ISD::Constant) {
2031 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2032 uint64_t c2 = N1C->getValue();
2033 if (c1 + c2 > OpSizeInBits)
2034 return DAG.getConstant(0, VT);
2035 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
2036 DAG.getConstant(c1 + c2, N1.getValueType()));
2038 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
2039 // (srl (and x, -1 << c1), c1-c2)
2040 if (N1C && N0.getOpcode() == ISD::SRL &&
2041 N0.getOperand(1).getOpcode() == ISD::Constant) {
2042 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2043 uint64_t c2 = N1C->getValue();
2044 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2045 DAG.getConstant(~0ULL << c1, VT));
2047 return DAG.getNode(ISD::SHL, VT, Mask,
2048 DAG.getConstant(c2-c1, N1.getValueType()));
2050 return DAG.getNode(ISD::SRL, VT, Mask,
2051 DAG.getConstant(c1-c2, N1.getValueType()));
2053 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
2054 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
2055 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
2056 DAG.getConstant(~0ULL << N1C->getValue(), VT));
2060 SDOperand DAGCombiner::visitSRA(SDNode *N) {
2061 SDOperand N0 = N->getOperand(0);
2062 SDOperand N1 = N->getOperand(1);
2063 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2064 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2065 MVT::ValueType VT = N0.getValueType();
2067 // fold (sra c1, c2) -> c1>>c2
2069 return DAG.getNode(ISD::SRA, VT, N0, N1);
2070 // fold (sra 0, x) -> 0
2071 if (N0C && N0C->isNullValue())
2073 // fold (sra -1, x) -> -1
2074 if (N0C && N0C->isAllOnesValue())
2076 // fold (sra x, c >= size(x)) -> undef
2077 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
2078 return DAG.getNode(ISD::UNDEF, VT);
2079 // fold (sra x, 0) -> x
2080 if (N1C && N1C->isNullValue())
2082 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
2084 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2085 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
2088 default: EVT = MVT::Other; break;
2089 case 1: EVT = MVT::i1; break;
2090 case 8: EVT = MVT::i8; break;
2091 case 16: EVT = MVT::i16; break;
2092 case 32: EVT = MVT::i32; break;
2094 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
2095 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
2096 DAG.getValueType(EVT));
2099 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
2100 if (N1C && N0.getOpcode() == ISD::SRA) {
2101 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2102 unsigned Sum = N1C->getValue() + C1->getValue();
2103 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
2104 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
2105 DAG.getConstant(Sum, N1C->getValueType(0)));
2109 // Simplify, based on bits shifted out of the LHS.
2110 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2111 return SDOperand(N, 0);
2114 // If the sign bit is known to be zero, switch this to a SRL.
2115 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
2116 return DAG.getNode(ISD::SRL, VT, N0, N1);
2120 SDOperand DAGCombiner::visitSRL(SDNode *N) {
2121 SDOperand N0 = N->getOperand(0);
2122 SDOperand N1 = N->getOperand(1);
2123 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2124 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2125 MVT::ValueType VT = N0.getValueType();
2126 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2128 // fold (srl c1, c2) -> c1 >>u c2
2130 return DAG.getNode(ISD::SRL, VT, N0, N1);
2131 // fold (srl 0, x) -> 0
2132 if (N0C && N0C->isNullValue())
2134 // fold (srl x, c >= size(x)) -> undef
2135 if (N1C && N1C->getValue() >= OpSizeInBits)
2136 return DAG.getNode(ISD::UNDEF, VT);
2137 // fold (srl x, 0) -> x
2138 if (N1C && N1C->isNullValue())
2140 // if (srl x, c) is known to be zero, return 0
2141 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
2142 return DAG.getConstant(0, VT);
2144 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
2145 if (N1C && N0.getOpcode() == ISD::SRL &&
2146 N0.getOperand(1).getOpcode() == ISD::Constant) {
2147 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2148 uint64_t c2 = N1C->getValue();
2149 if (c1 + c2 > OpSizeInBits)
2150 return DAG.getConstant(0, VT);
2151 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
2152 DAG.getConstant(c1 + c2, N1.getValueType()));
2155 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
2156 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2157 // Shifting in all undef bits?
2158 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
2159 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
2160 return DAG.getNode(ISD::UNDEF, VT);
2162 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
2163 AddToWorkList(SmallShift.Val);
2164 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
2167 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
2168 // bit, which is unmodified by sra.
2169 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
2170 if (N0.getOpcode() == ISD::SRA)
2171 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
2174 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
2175 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2176 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
2177 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
2178 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
2180 // If any of the input bits are KnownOne, then the input couldn't be all
2181 // zeros, thus the result of the srl will always be zero.
2182 if (KnownOne) return DAG.getConstant(0, VT);
2184 // If all of the bits input the to ctlz node are known to be zero, then
2185 // the result of the ctlz is "32" and the result of the shift is one.
2186 uint64_t UnknownBits = ~KnownZero & Mask;
2187 if (UnknownBits == 0) return DAG.getConstant(1, VT);
2189 // Otherwise, check to see if there is exactly one bit input to the ctlz.
2190 if ((UnknownBits & (UnknownBits-1)) == 0) {
2191 // Okay, we know that only that the single bit specified by UnknownBits
2192 // could be set on input to the CTLZ node. If this bit is set, the SRL
2193 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
2194 // to an SRL,XOR pair, which is likely to simplify more.
2195 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
2196 SDOperand Op = N0.getOperand(0);
2198 Op = DAG.getNode(ISD::SRL, VT, Op,
2199 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
2200 AddToWorkList(Op.Val);
2202 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
2206 // fold operands of srl based on knowledge that the low bits are not
2208 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
2209 return SDOperand(N, 0);
2214 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
2215 SDOperand N0 = N->getOperand(0);
2216 MVT::ValueType VT = N->getValueType(0);
2218 // fold (ctlz c1) -> c2
2219 if (isa<ConstantSDNode>(N0))
2220 return DAG.getNode(ISD::CTLZ, VT, N0);
2224 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
2225 SDOperand N0 = N->getOperand(0);
2226 MVT::ValueType VT = N->getValueType(0);
2228 // fold (cttz c1) -> c2
2229 if (isa<ConstantSDNode>(N0))
2230 return DAG.getNode(ISD::CTTZ, VT, N0);
2234 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
2235 SDOperand N0 = N->getOperand(0);
2236 MVT::ValueType VT = N->getValueType(0);
2238 // fold (ctpop c1) -> c2
2239 if (isa<ConstantSDNode>(N0))
2240 return DAG.getNode(ISD::CTPOP, VT, N0);
2244 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
2245 SDOperand N0 = N->getOperand(0);
2246 SDOperand N1 = N->getOperand(1);
2247 SDOperand N2 = N->getOperand(2);
2248 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2249 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2250 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2251 MVT::ValueType VT = N->getValueType(0);
2252 MVT::ValueType VT0 = N0.getValueType();
2254 // fold select C, X, X -> X
2257 // fold select true, X, Y -> X
2258 if (N0C && !N0C->isNullValue())
2260 // fold select false, X, Y -> Y
2261 if (N0C && N0C->isNullValue())
2263 // fold select C, 1, X -> C | X
2264 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
2265 return DAG.getNode(ISD::OR, VT, N0, N2);
2266 // fold select C, 0, 1 -> ~C
2267 if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
2268 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) {
2269 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
2272 AddToWorkList(XORNode.Val);
2273 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0))
2274 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
2275 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
2277 // fold select C, 0, X -> ~C & X
2278 if (VT == VT0 && N1C && N1C->isNullValue()) {
2279 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2280 AddToWorkList(XORNode.Val);
2281 return DAG.getNode(ISD::AND, VT, XORNode, N2);
2283 // fold select C, X, 1 -> ~C | X
2284 if (VT == VT0 && N2C && N2C->getValue() == 1) {
2285 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
2286 AddToWorkList(XORNode.Val);
2287 return DAG.getNode(ISD::OR, VT, XORNode, N1);
2289 // fold select C, X, 0 -> C & X
2290 // FIXME: this should check for C type == X type, not i1?
2291 if (MVT::i1 == VT && N2C && N2C->isNullValue())
2292 return DAG.getNode(ISD::AND, VT, N0, N1);
2293 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2294 if (MVT::i1 == VT && N0 == N1)
2295 return DAG.getNode(ISD::OR, VT, N0, N2);
2296 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2297 if (MVT::i1 == VT && N0 == N2)
2298 return DAG.getNode(ISD::AND, VT, N0, N1);
2300 // If we can fold this based on the true/false value, do so.
2301 if (SimplifySelectOps(N, N1, N2))
2302 return SDOperand(N, 0); // Don't revisit N.
2304 // fold selects based on a setcc into other things, such as min/max/abs
2305 if (N0.getOpcode() == ISD::SETCC)
2307 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
2308 // having to say they don't support SELECT_CC on every type the DAG knows
2309 // about, since there is no way to mark an opcode illegal at all value types
2310 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
2311 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
2312 N1, N2, N0.getOperand(2));
2314 return SimplifySelect(N0, N1, N2);
2318 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
2319 SDOperand N0 = N->getOperand(0);
2320 SDOperand N1 = N->getOperand(1);
2321 SDOperand N2 = N->getOperand(2);
2322 SDOperand N3 = N->getOperand(3);
2323 SDOperand N4 = N->getOperand(4);
2324 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
2326 // fold select_cc lhs, rhs, x, x, cc -> x
2330 // Determine if the condition we're dealing with is constant
2331 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2332 if (SCC.Val) AddToWorkList(SCC.Val);
2334 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
2335 if (SCCC->getValue())
2336 return N2; // cond always true -> true val
2338 return N3; // cond always false -> false val
2341 // Fold to a simpler select_cc
2342 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
2343 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
2344 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
2347 // If we can fold this based on the true/false value, do so.
2348 if (SimplifySelectOps(N, N2, N3))
2349 return SDOperand(N, 0); // Don't revisit N.
2351 // fold select_cc into other things, such as min/max/abs
2352 return SimplifySelectCC(N0, N1, N2, N3, CC);
2355 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
2356 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
2357 cast<CondCodeSDNode>(N->getOperand(2))->get());
2360 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
2361 SDOperand N0 = N->getOperand(0);
2362 MVT::ValueType VT = N->getValueType(0);
2364 // fold (sext c1) -> c1
2365 if (isa<ConstantSDNode>(N0))
2366 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
2368 // fold (sext (sext x)) -> (sext x)
2369 // fold (sext (aext x)) -> (sext x)
2370 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2371 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
2373 // fold (sext (truncate (load x))) -> (sext (smaller load x))
2374 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
2375 if (N0.getOpcode() == ISD::TRUNCATE) {
2376 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2377 if (NarrowLoad.Val) {
2378 if (NarrowLoad.Val != N0.Val)
2379 CombineTo(N0.Val, NarrowLoad);
2380 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
2384 // See if the value being truncated is already sign extended. If so, just
2385 // eliminate the trunc/sext pair.
2386 if (N0.getOpcode() == ISD::TRUNCATE) {
2387 SDOperand Op = N0.getOperand(0);
2388 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2389 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2390 unsigned DestBits = MVT::getSizeInBits(VT);
2391 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
2393 if (OpBits == DestBits) {
2394 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
2395 // bits, it is already ready.
2396 if (NumSignBits > DestBits-MidBits)
2398 } else if (OpBits < DestBits) {
2399 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
2400 // bits, just sext from i32.
2401 if (NumSignBits > OpBits-MidBits)
2402 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
2404 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
2405 // bits, just truncate to i32.
2406 if (NumSignBits > OpBits-MidBits)
2407 return DAG.getNode(ISD::TRUNCATE, VT, Op);
2410 // fold (sext (truncate x)) -> (sextinreg x).
2411 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
2412 N0.getValueType())) {
2413 if (Op.getValueType() < VT)
2414 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2415 else if (Op.getValueType() > VT)
2416 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2417 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
2418 DAG.getValueType(N0.getValueType()));
2422 // fold (sext (load x)) -> (sext (truncate (sextload x)))
2423 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2424 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
2425 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2426 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2427 LN0->getBasePtr(), LN0->getSrcValue(),
2428 LN0->getSrcValueOffset(),
2431 LN0->getAlignment());
2432 CombineTo(N, ExtLoad);
2433 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2434 ExtLoad.getValue(1));
2435 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2438 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
2439 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
2440 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2441 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2442 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2443 MVT::ValueType EVT = LN0->getLoadedVT();
2444 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
2445 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2446 LN0->getBasePtr(), LN0->getSrcValue(),
2447 LN0->getSrcValueOffset(), EVT,
2449 LN0->getAlignment());
2450 CombineTo(N, ExtLoad);
2451 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2452 ExtLoad.getValue(1));
2453 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2457 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
2458 if (N0.getOpcode() == ISD::SETCC) {
2460 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2461 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
2462 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2463 if (SCC.Val) return SCC;
2469 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
2470 SDOperand N0 = N->getOperand(0);
2471 MVT::ValueType VT = N->getValueType(0);
2473 // fold (zext c1) -> c1
2474 if (isa<ConstantSDNode>(N0))
2475 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2476 // fold (zext (zext x)) -> (zext x)
2477 // fold (zext (aext x)) -> (zext x)
2478 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
2479 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
2481 // fold (zext (truncate (load x))) -> (zext (smaller load x))
2482 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
2483 if (N0.getOpcode() == ISD::TRUNCATE) {
2484 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2485 if (NarrowLoad.Val) {
2486 if (NarrowLoad.Val != N0.Val)
2487 CombineTo(N0.Val, NarrowLoad);
2488 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
2492 // fold (zext (truncate x)) -> (and x, mask)
2493 if (N0.getOpcode() == ISD::TRUNCATE &&
2494 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
2495 SDOperand Op = N0.getOperand(0);
2496 if (Op.getValueType() < VT) {
2497 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
2498 } else if (Op.getValueType() > VT) {
2499 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
2501 return DAG.getZeroExtendInReg(Op, N0.getValueType());
2504 // fold (zext (and (trunc x), cst)) -> (and x, cst).
2505 if (N0.getOpcode() == ISD::AND &&
2506 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2507 N0.getOperand(1).getOpcode() == ISD::Constant) {
2508 SDOperand X = N0.getOperand(0).getOperand(0);
2509 if (X.getValueType() < VT) {
2510 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2511 } else if (X.getValueType() > VT) {
2512 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2514 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2515 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2518 // fold (zext (load x)) -> (zext (truncate (zextload x)))
2519 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2520 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2521 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2522 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2523 LN0->getBasePtr(), LN0->getSrcValue(),
2524 LN0->getSrcValueOffset(),
2527 LN0->getAlignment());
2528 CombineTo(N, ExtLoad);
2529 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2530 ExtLoad.getValue(1));
2531 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2534 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2535 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2536 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
2537 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
2538 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2539 MVT::ValueType EVT = LN0->getLoadedVT();
2540 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2541 LN0->getBasePtr(), LN0->getSrcValue(),
2542 LN0->getSrcValueOffset(), EVT,
2544 LN0->getAlignment());
2545 CombineTo(N, ExtLoad);
2546 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2547 ExtLoad.getValue(1));
2548 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2551 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2552 if (N0.getOpcode() == ISD::SETCC) {
2554 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2555 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2556 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2557 if (SCC.Val) return SCC;
2563 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2564 SDOperand N0 = N->getOperand(0);
2565 MVT::ValueType VT = N->getValueType(0);
2567 // fold (aext c1) -> c1
2568 if (isa<ConstantSDNode>(N0))
2569 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2570 // fold (aext (aext x)) -> (aext x)
2571 // fold (aext (zext x)) -> (zext x)
2572 // fold (aext (sext x)) -> (sext x)
2573 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2574 N0.getOpcode() == ISD::ZERO_EXTEND ||
2575 N0.getOpcode() == ISD::SIGN_EXTEND)
2576 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2578 // fold (aext (truncate (load x))) -> (aext (smaller load x))
2579 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
2580 if (N0.getOpcode() == ISD::TRUNCATE) {
2581 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
2582 if (NarrowLoad.Val) {
2583 if (NarrowLoad.Val != N0.Val)
2584 CombineTo(N0.Val, NarrowLoad);
2585 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
2589 // fold (aext (truncate x))
2590 if (N0.getOpcode() == ISD::TRUNCATE) {
2591 SDOperand TruncOp = N0.getOperand(0);
2592 if (TruncOp.getValueType() == VT)
2593 return TruncOp; // x iff x size == zext size.
2594 if (TruncOp.getValueType() > VT)
2595 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2596 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2599 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2600 if (N0.getOpcode() == ISD::AND &&
2601 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2602 N0.getOperand(1).getOpcode() == ISD::Constant) {
2603 SDOperand X = N0.getOperand(0).getOperand(0);
2604 if (X.getValueType() < VT) {
2605 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2606 } else if (X.getValueType() > VT) {
2607 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2609 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2610 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2613 // fold (aext (load x)) -> (aext (truncate (extload x)))
2614 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2615 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2616 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2617 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2618 LN0->getBasePtr(), LN0->getSrcValue(),
2619 LN0->getSrcValueOffset(),
2622 LN0->getAlignment());
2623 CombineTo(N, ExtLoad);
2624 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2625 ExtLoad.getValue(1));
2626 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2629 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2630 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2631 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2632 if (N0.getOpcode() == ISD::LOAD &&
2633 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2635 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2636 MVT::ValueType EVT = LN0->getLoadedVT();
2637 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2638 LN0->getChain(), LN0->getBasePtr(),
2640 LN0->getSrcValueOffset(), EVT,
2642 LN0->getAlignment());
2643 CombineTo(N, ExtLoad);
2644 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2645 ExtLoad.getValue(1));
2646 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2649 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
2650 if (N0.getOpcode() == ISD::SETCC) {
2652 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
2653 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2654 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
2662 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
2663 /// bits and then truncated to a narrower type and where N is a multiple
2664 /// of number of bits of the narrower type, transform it to a narrower load
2665 /// from address + N / num of bits of new type. If the result is to be
2666 /// extended, also fold the extension to form a extending load.
2667 SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
2668 unsigned Opc = N->getOpcode();
2669 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
2670 SDOperand N0 = N->getOperand(0);
2671 MVT::ValueType VT = N->getValueType(0);
2672 MVT::ValueType EVT = N->getValueType(0);
2674 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
2676 if (Opc == ISD::SIGN_EXTEND_INREG) {
2677 ExtType = ISD::SEXTLOAD;
2678 EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2679 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
2683 unsigned EVTBits = MVT::getSizeInBits(EVT);
2685 bool CombineSRL = false;
2686 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
2687 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2688 ShAmt = N01->getValue();
2689 // Is the shift amount a multiple of size of VT?
2690 if ((ShAmt & (EVTBits-1)) == 0) {
2691 N0 = N0.getOperand(0);
2692 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
2699 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2700 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
2701 // zero extended form: by shrinking the load, we lose track of the fact
2702 // that it is already zero extended.
2703 // FIXME: This should be reevaluated.
2705 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
2706 "Cannot truncate to larger type!");
2707 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2708 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2709 // For big endian targets, we need to adjust the offset to the pointer to
2710 // load the correct bytes.
2711 if (!TLI.isLittleEndian())
2712 ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits;
2713 uint64_t PtrOff = ShAmt / 8;
2714 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2715 DAG.getConstant(PtrOff, PtrType));
2716 AddToWorkList(NewPtr.Val);
2717 SDOperand Load = (ExtType == ISD::NON_EXTLOAD)
2718 ? DAG.getLoad(VT, LN0->getChain(), NewPtr,
2719 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2720 LN0->isVolatile(), LN0->getAlignment())
2721 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
2722 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
2723 LN0->isVolatile(), LN0->getAlignment());
2726 std::vector<SDNode*> NowDead;
2727 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead);
2728 CombineTo(N->getOperand(0).Val, Load);
2730 CombineTo(N0.Val, Load, Load.getValue(1));
2732 if (Opc == ISD::SIGN_EXTEND_INREG)
2733 return DAG.getNode(Opc, VT, Load, N->getOperand(1));
2735 return DAG.getNode(Opc, VT, Load);
2737 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2744 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2745 SDOperand N0 = N->getOperand(0);
2746 SDOperand N1 = N->getOperand(1);
2747 MVT::ValueType VT = N->getValueType(0);
2748 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2749 unsigned EVTBits = MVT::getSizeInBits(EVT);
2751 // fold (sext_in_reg c1) -> c1
2752 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2753 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2755 // If the input is already sign extended, just drop the extension.
2756 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2759 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2760 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2761 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2762 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2765 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
2766 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2767 return DAG.getZeroExtendInReg(N0, EVT);
2769 // fold operands of sext_in_reg based on knowledge that the top bits are not
2771 if (SimplifyDemandedBits(SDOperand(N, 0)))
2772 return SDOperand(N, 0);
2774 // fold (sext_in_reg (load x)) -> (smaller sextload x)
2775 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
2776 SDOperand NarrowLoad = ReduceLoadWidth(N);
2780 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2781 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2782 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2783 if (N0.getOpcode() == ISD::SRL) {
2784 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2785 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2786 // We can turn this into an SRA iff the input to the SRL is already sign
2788 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
2789 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2790 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2794 // fold (sext_inreg (extload x)) -> (sextload x)
2795 if (ISD::isEXTLoad(N0.Val) &&
2796 ISD::isUNINDEXEDLoad(N0.Val) &&
2797 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2798 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2799 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2800 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2801 LN0->getBasePtr(), LN0->getSrcValue(),
2802 LN0->getSrcValueOffset(), EVT,
2804 LN0->getAlignment());
2805 CombineTo(N, ExtLoad);
2806 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2807 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2809 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2810 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
2812 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2813 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2814 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2815 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2816 LN0->getBasePtr(), LN0->getSrcValue(),
2817 LN0->getSrcValueOffset(), EVT,
2819 LN0->getAlignment());
2820 CombineTo(N, ExtLoad);
2821 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2822 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2827 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2828 SDOperand N0 = N->getOperand(0);
2829 MVT::ValueType VT = N->getValueType(0);
2832 if (N0.getValueType() == N->getValueType(0))
2834 // fold (truncate c1) -> c1
2835 if (isa<ConstantSDNode>(N0))
2836 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2837 // fold (truncate (truncate x)) -> (truncate x)
2838 if (N0.getOpcode() == ISD::TRUNCATE)
2839 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2840 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2841 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2842 N0.getOpcode() == ISD::ANY_EXTEND) {
2843 if (N0.getOperand(0).getValueType() < VT)
2844 // if the source is smaller than the dest, we still need an extend
2845 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2846 else if (N0.getOperand(0).getValueType() > VT)
2847 // if the source is larger than the dest, than we just need the truncate
2848 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2850 // if the source and dest are the same type, we can drop both the extend
2852 return N0.getOperand(0);
2855 // fold (truncate (load x)) -> (smaller load x)
2856 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
2857 return ReduceLoadWidth(N);
2860 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2861 SDOperand N0 = N->getOperand(0);
2862 MVT::ValueType VT = N->getValueType(0);
2864 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
2865 // Only do this before legalize, since afterward the target may be depending
2866 // on the bitconvert.
2867 // First check to see if this is all constant.
2868 if (!AfterLegalize &&
2869 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
2870 MVT::isVector(VT)) {
2871 bool isSimple = true;
2872 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
2873 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2874 N0.getOperand(i).getOpcode() != ISD::Constant &&
2875 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2880 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
2881 assert(!MVT::isVector(DestEltVT) &&
2882 "Element type of vector ValueType must not be vector!");
2884 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
2888 // If the input is a constant, let getNode() fold it.
2889 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2890 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2891 if (Res.Val != N) return Res;
2894 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2895 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2897 // fold (conv (load x)) -> (load (conv*)x)
2898 // If the resultant load doesn't need a higher alignment than the original!
2899 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2900 ISD::isUNINDEXEDLoad(N0.Val) &&
2901 TLI.isOperationLegal(ISD::LOAD, VT)) {
2902 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2903 unsigned Align = TLI.getTargetMachine().getTargetData()->
2904 getABITypeAlignment(MVT::getTypeForValueType(VT));
2905 unsigned OrigAlign = LN0->getAlignment();
2906 if (Align <= OrigAlign) {
2907 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2908 LN0->getSrcValue(), LN0->getSrcValueOffset(),
2909 LN0->isVolatile(), Align);
2911 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2920 /// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector
2921 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2922 /// destination element value type.
2923 SDOperand DAGCombiner::
2924 ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2925 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2927 // If this is already the right type, we're done.
2928 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2930 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2931 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2933 // If this is a conversion of N elements of one type to N elements of another
2934 // type, convert each element. This handles FP<->INT cases.
2935 if (SrcBitSize == DstBitSize) {
2936 SmallVector<SDOperand, 8> Ops;
2937 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2938 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2939 AddToWorkList(Ops.back().Val);
2942 MVT::getVectorType(DstEltVT,
2943 MVT::getVectorNumElements(BV->getValueType(0)));
2944 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
2947 // Otherwise, we're growing or shrinking the elements. To avoid having to
2948 // handle annoying details of growing/shrinking FP values, we convert them to
2950 if (MVT::isFloatingPoint(SrcEltVT)) {
2951 // Convert the input float vector to a int vector where the elements are the
2953 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2954 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2955 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
2959 // Now we know the input is an integer vector. If the output is a FP type,
2960 // convert to integer first, then to FP of the right size.
2961 if (MVT::isFloatingPoint(DstEltVT)) {
2962 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2963 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2964 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
2966 // Next, convert to FP elements of the same size.
2967 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT);
2970 // Okay, we know the src/dst types are both integers of differing types.
2971 // Handling growing first.
2972 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2973 if (SrcBitSize < DstBitSize) {
2974 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2976 SmallVector<SDOperand, 8> Ops;
2977 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
2978 i += NumInputsPerOutput) {
2979 bool isLE = TLI.isLittleEndian();
2980 uint64_t NewBits = 0;
2981 bool EltIsUndef = true;
2982 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2983 // Shift the previously computed bits over.
2984 NewBits <<= SrcBitSize;
2985 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2986 if (Op.getOpcode() == ISD::UNDEF) continue;
2989 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2993 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2995 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2998 MVT::ValueType VT = MVT::getVectorType(DstEltVT,
3000 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3003 // Finally, this must be the case where we are shrinking elements: each input
3004 // turns into multiple outputs.
3005 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
3006 SmallVector<SDOperand, 8> Ops;
3007 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3008 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
3009 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
3010 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
3013 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
3015 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
3016 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
3017 OpVal >>= DstBitSize;
3018 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
3021 // For big endian targets, swap the order of the pieces of each element.
3022 if (!TLI.isLittleEndian())
3023 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
3025 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
3026 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
3031 SDOperand DAGCombiner::visitFADD(SDNode *N) {
3032 SDOperand N0 = N->getOperand(0);
3033 SDOperand N1 = N->getOperand(1);
3034 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3035 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3036 MVT::ValueType VT = N->getValueType(0);
3039 if (MVT::isVector(VT)) {
3040 SDOperand FoldedVOp = SimplifyVBinOp(N);
3041 if (FoldedVOp.Val) return FoldedVOp;
3044 // fold (fadd c1, c2) -> c1+c2
3046 return DAG.getNode(ISD::FADD, VT, N0, N1);
3047 // canonicalize constant to RHS
3048 if (N0CFP && !N1CFP)
3049 return DAG.getNode(ISD::FADD, VT, N1, N0);
3050 // fold (A + (-B)) -> A-B
3051 if (isNegatibleForFree(N1) == 2)
3052 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG));
3053 // fold ((-A) + B) -> B-A
3054 if (isNegatibleForFree(N0) == 2)
3055 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG));
3057 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
3058 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
3059 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3060 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0),
3061 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1));
3066 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
3067 SDOperand N0 = N->getOperand(0);
3068 SDOperand N1 = N->getOperand(1);
3069 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3070 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3071 MVT::ValueType VT = N->getValueType(0);
3074 if (MVT::isVector(VT)) {
3075 SDOperand FoldedVOp = SimplifyVBinOp(N);
3076 if (FoldedVOp.Val) return FoldedVOp;
3079 // fold (fsub c1, c2) -> c1-c2
3081 return DAG.getNode(ISD::FSUB, VT, N0, N1);
3083 if (UnsafeFPMath && N0CFP && N0CFP->getValue() == 0.0) {
3084 if (isNegatibleForFree(N1))
3085 return GetNegatedExpression(N1, DAG);
3086 return DAG.getNode(ISD::FNEG, VT, N1);
3088 // fold (A-(-B)) -> A+B
3089 if (isNegatibleForFree(N1))
3090 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG));
3095 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
3096 SDOperand N0 = N->getOperand(0);
3097 SDOperand N1 = N->getOperand(1);
3098 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3099 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3100 MVT::ValueType VT = N->getValueType(0);
3103 if (MVT::isVector(VT)) {
3104 SDOperand FoldedVOp = SimplifyVBinOp(N);
3105 if (FoldedVOp.Val) return FoldedVOp;
3108 // fold (fmul c1, c2) -> c1*c2
3110 return DAG.getNode(ISD::FMUL, VT, N0, N1);
3111 // canonicalize constant to RHS
3112 if (N0CFP && !N1CFP)
3113 return DAG.getNode(ISD::FMUL, VT, N1, N0);
3114 // fold (fmul X, 2.0) -> (fadd X, X)
3115 if (N1CFP && N1CFP->isExactlyValue(+2.0))
3116 return DAG.getNode(ISD::FADD, VT, N0, N0);
3117 // fold (fmul X, -1.0) -> (fneg X)
3118 if (N1CFP && N1CFP->isExactlyValue(-1.0))
3119 return DAG.getNode(ISD::FNEG, VT, N0);
3122 if (char LHSNeg = isNegatibleForFree(N0)) {
3123 if (char RHSNeg = isNegatibleForFree(N1)) {
3124 // Both can be negated for free, check to see if at least one is cheaper
3126 if (LHSNeg == 2 || RHSNeg == 2)
3127 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG),
3128 GetNegatedExpression(N1, DAG));
3132 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
3133 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
3134 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
3135 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0),
3136 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
3141 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
3142 SDOperand N0 = N->getOperand(0);
3143 SDOperand N1 = N->getOperand(1);
3144 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3145 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3146 MVT::ValueType VT = N->getValueType(0);
3149 if (MVT::isVector(VT)) {
3150 SDOperand FoldedVOp = SimplifyVBinOp(N);
3151 if (FoldedVOp.Val) return FoldedVOp;
3154 // fold (fdiv c1, c2) -> c1/c2
3156 return DAG.getNode(ISD::FDIV, VT, N0, N1);
3160 if (char LHSNeg = isNegatibleForFree(N0)) {
3161 if (char RHSNeg = isNegatibleForFree(N1)) {
3162 // Both can be negated for free, check to see if at least one is cheaper
3164 if (LHSNeg == 2 || RHSNeg == 2)
3165 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG),
3166 GetNegatedExpression(N1, DAG));
3173 SDOperand DAGCombiner::visitFREM(SDNode *N) {
3174 SDOperand N0 = N->getOperand(0);
3175 SDOperand N1 = N->getOperand(1);
3176 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3177 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3178 MVT::ValueType VT = N->getValueType(0);
3180 // fold (frem c1, c2) -> fmod(c1,c2)
3182 return DAG.getNode(ISD::FREM, VT, N0, N1);
3187 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
3188 SDOperand N0 = N->getOperand(0);
3189 SDOperand N1 = N->getOperand(1);
3190 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3191 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
3192 MVT::ValueType VT = N->getValueType(0);
3194 if (N0CFP && N1CFP) // Constant fold
3195 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
3198 const APFloat& V = N1CFP->getValueAPF();
3199 // copysign(x, c1) -> fabs(x) iff ispos(c1)
3200 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
3201 if (!V.isNegative())
3202 return DAG.getNode(ISD::FABS, VT, N0);
3204 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
3207 // copysign(fabs(x), y) -> copysign(x, y)
3208 // copysign(fneg(x), y) -> copysign(x, y)
3209 // copysign(copysign(x,z), y) -> copysign(x, y)
3210 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
3211 N0.getOpcode() == ISD::FCOPYSIGN)
3212 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
3214 // copysign(x, abs(y)) -> abs(x)
3215 if (N1.getOpcode() == ISD::FABS)
3216 return DAG.getNode(ISD::FABS, VT, N0);
3218 // copysign(x, copysign(y,z)) -> copysign(x, z)
3219 if (N1.getOpcode() == ISD::FCOPYSIGN)
3220 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
3222 // copysign(x, fp_extend(y)) -> copysign(x, y)
3223 // copysign(x, fp_round(y)) -> copysign(x, y)
3224 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
3225 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
3232 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
3233 SDOperand N0 = N->getOperand(0);
3234 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3235 MVT::ValueType VT = N->getValueType(0);
3237 // fold (sint_to_fp c1) -> c1fp
3239 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
3243 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
3244 SDOperand N0 = N->getOperand(0);
3245 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3246 MVT::ValueType VT = N->getValueType(0);
3248 // fold (uint_to_fp c1) -> c1fp
3250 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
3254 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
3255 SDOperand N0 = N->getOperand(0);
3256 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3257 MVT::ValueType VT = N->getValueType(0);
3259 // fold (fp_to_sint c1fp) -> c1
3261 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
3265 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
3266 SDOperand N0 = N->getOperand(0);
3267 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3268 MVT::ValueType VT = N->getValueType(0);
3270 // fold (fp_to_uint c1fp) -> c1
3272 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
3276 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
3277 SDOperand N0 = N->getOperand(0);
3278 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3279 MVT::ValueType VT = N->getValueType(0);
3281 // fold (fp_round c1fp) -> c1fp
3283 return DAG.getNode(ISD::FP_ROUND, VT, N0);
3285 // fold (fp_round (fp_extend x)) -> x
3286 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
3287 return N0.getOperand(0);
3289 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
3290 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
3291 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
3292 AddToWorkList(Tmp.Val);
3293 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
3299 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
3300 SDOperand N0 = N->getOperand(0);
3301 MVT::ValueType VT = N->getValueType(0);
3302 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
3303 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3305 // fold (fp_round_inreg c1fp) -> c1fp
3307 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
3308 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
3313 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
3314 SDOperand N0 = N->getOperand(0);
3315 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3316 MVT::ValueType VT = N->getValueType(0);
3318 // fold (fp_extend c1fp) -> c1fp
3320 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
3322 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
3323 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
3324 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
3325 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3326 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
3327 LN0->getBasePtr(), LN0->getSrcValue(),
3328 LN0->getSrcValueOffset(),
3331 LN0->getAlignment());
3332 CombineTo(N, ExtLoad);
3333 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
3334 ExtLoad.getValue(1));
3335 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
3342 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
3343 SDOperand N0 = N->getOperand(0);
3345 if (isNegatibleForFree(N0))
3346 return GetNegatedExpression(N0, DAG);
3351 SDOperand DAGCombiner::visitFABS(SDNode *N) {
3352 SDOperand N0 = N->getOperand(0);
3353 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
3354 MVT::ValueType VT = N->getValueType(0);
3356 // fold (fabs c1) -> fabs(c1)
3358 return DAG.getNode(ISD::FABS, VT, N0);
3359 // fold (fabs (fabs x)) -> (fabs x)
3360 if (N0.getOpcode() == ISD::FABS)
3361 return N->getOperand(0);
3362 // fold (fabs (fneg x)) -> (fabs x)
3363 // fold (fabs (fcopysign x, y)) -> (fabs x)
3364 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
3365 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
3370 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
3371 SDOperand Chain = N->getOperand(0);
3372 SDOperand N1 = N->getOperand(1);
3373 SDOperand N2 = N->getOperand(2);
3374 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3376 // never taken branch, fold to chain
3377 if (N1C && N1C->isNullValue())
3379 // unconditional branch
3380 if (N1C && N1C->getValue() == 1)
3381 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
3382 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
3384 if (N1.getOpcode() == ISD::SETCC &&
3385 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
3386 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
3387 N1.getOperand(0), N1.getOperand(1), N2);
3392 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
3394 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
3395 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
3396 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
3398 // Use SimplifySetCC to simplify SETCC's.
3399 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
3400 if (Simp.Val) AddToWorkList(Simp.Val);
3402 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
3404 // fold br_cc true, dest -> br dest (unconditional branch)
3405 if (SCCC && SCCC->getValue())
3406 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
3408 // fold br_cc false, dest -> unconditional fall through
3409 if (SCCC && SCCC->isNullValue())
3410 return N->getOperand(0);
3412 // fold to a simpler setcc
3413 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
3414 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
3415 Simp.getOperand(2), Simp.getOperand(0),
3416 Simp.getOperand(1), N->getOperand(4));
3421 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
3422 /// pre-indexed load / store when the base pointer is a add or subtract
3423 /// and it has other uses besides the load / store. After the
3424 /// transformation, the new indexed load / store has effectively folded
3425 /// the add / subtract in and all of its other uses are redirected to the
3426 /// new load / store.
3427 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
3434 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3435 if (LD->getAddressingMode() != ISD::UNINDEXED)
3437 VT = LD->getLoadedVT();
3438 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
3439 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
3441 Ptr = LD->getBasePtr();
3442 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3443 if (ST->getAddressingMode() != ISD::UNINDEXED)
3445 VT = ST->getStoredVT();
3446 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
3447 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
3449 Ptr = ST->getBasePtr();
3454 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
3455 // out. There is no reason to make this a preinc/predec.
3456 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
3457 Ptr.Val->hasOneUse())
3460 // Ask the target to do addressing mode selection.
3463 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3464 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
3466 // Don't create a indexed load / store with zero offset.
3467 if (isa<ConstantSDNode>(Offset) &&
3468 cast<ConstantSDNode>(Offset)->getValue() == 0)
3471 // Try turning it into a pre-indexed load / store except when:
3472 // 1) The new base ptr is a frame index.
3473 // 2) If N is a store and the new base ptr is either the same as or is a
3474 // predecessor of the value being stored.
3475 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
3476 // that would create a cycle.
3477 // 4) All uses are load / store ops that use it as old base ptr.
3479 // Check #1. Preinc'ing a frame index would require copying the stack pointer
3480 // (plus the implicit offset) to a register to preinc anyway.
3481 if (isa<FrameIndexSDNode>(BasePtr))
3486 SDOperand Val = cast<StoreSDNode>(N)->getValue();
3487 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val))
3491 // Now check for #3 and #4.
3492 bool RealUse = false;
3493 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3494 E = Ptr.Val->use_end(); I != E; ++I) {
3498 if (Use->isPredecessor(N))
3501 if (!((Use->getOpcode() == ISD::LOAD &&
3502 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
3503 (Use->getOpcode() == ISD::STORE) &&
3504 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
3512 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
3514 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3517 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
3518 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3520 std::vector<SDNode*> NowDead;
3522 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3524 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3527 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3531 // Nodes can end up on the worklist more than once. Make sure we do
3532 // not process a node that has been replaced.
3533 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3534 removeFromWorkList(NowDead[i]);
3535 // Finally, since the node is now dead, remove it from the graph.
3538 // Replace the uses of Ptr with uses of the updated base value.
3539 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
3541 removeFromWorkList(Ptr.Val);
3542 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3543 removeFromWorkList(NowDead[i]);
3544 DAG.DeleteNode(Ptr.Val);
3549 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
3550 /// add / sub of the base pointer node into a post-indexed load / store.
3551 /// The transformation folded the add / subtract into the new indexed
3552 /// load / store effectively and all of its uses are redirected to the
3553 /// new load / store.
3554 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
3561 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3562 if (LD->getAddressingMode() != ISD::UNINDEXED)
3564 VT = LD->getLoadedVT();
3565 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
3566 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
3568 Ptr = LD->getBasePtr();
3569 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3570 if (ST->getAddressingMode() != ISD::UNINDEXED)
3572 VT = ST->getStoredVT();
3573 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
3574 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
3576 Ptr = ST->getBasePtr();
3581 if (Ptr.Val->hasOneUse())
3584 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
3585 E = Ptr.Val->use_end(); I != E; ++I) {
3588 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
3593 ISD::MemIndexedMode AM = ISD::UNINDEXED;
3594 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
3596 std::swap(BasePtr, Offset);
3599 // Don't create a indexed load / store with zero offset.
3600 if (isa<ConstantSDNode>(Offset) &&
3601 cast<ConstantSDNode>(Offset)->getValue() == 0)
3604 // Try turning it into a post-indexed load / store except when
3605 // 1) All uses are load / store ops that use it as base ptr.
3606 // 2) Op must be independent of N, i.e. Op is neither a predecessor
3607 // nor a successor of N. Otherwise, if Op is folded that would
3611 bool TryNext = false;
3612 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
3613 EE = BasePtr.Val->use_end(); II != EE; ++II) {
3618 // If all the uses are load / store addresses, then don't do the
3620 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
3621 bool RealUse = false;
3622 for (SDNode::use_iterator III = Use->use_begin(),
3623 EEE = Use->use_end(); III != EEE; ++III) {
3624 SDNode *UseUse = *III;
3625 if (!((UseUse->getOpcode() == ISD::LOAD &&
3626 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
3627 (UseUse->getOpcode() == ISD::STORE) &&
3628 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
3642 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
3643 SDOperand Result = isLoad
3644 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
3645 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
3648 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
3649 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
3651 std::vector<SDNode*> NowDead;
3653 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
3655 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
3658 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
3662 // Nodes can end up on the worklist more than once. Make sure we do
3663 // not process a node that has been replaced.
3664 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3665 removeFromWorkList(NowDead[i]);
3666 // Finally, since the node is now dead, remove it from the graph.
3669 // Replace the uses of Use with uses of the updated base value.
3670 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
3671 Result.getValue(isLoad ? 1 : 0),
3673 removeFromWorkList(Op);
3674 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
3675 removeFromWorkList(NowDead[i]);
3686 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
3687 LoadSDNode *LD = cast<LoadSDNode>(N);
3688 SDOperand Chain = LD->getChain();
3689 SDOperand Ptr = LD->getBasePtr();
3691 // If load is not volatile and there are no uses of the loaded value (and
3692 // the updated indexed value in case of indexed loads), change uses of the
3693 // chain value into uses of the chain input (i.e. delete the dead load).
3694 if (!LD->isVolatile()) {
3695 if (N->getValueType(1) == MVT::Other) {
3697 if (N->hasNUsesOfValue(0, 0))
3698 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
3701 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
3702 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
3703 SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0));
3704 SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1));
3705 SDOperand To[] = { Undef0, Undef1, Chain };
3706 return CombineTo(N, To, 3);
3711 // If this load is directly stored, replace the load value with the stored
3713 // TODO: Handle store large -> read small portion.
3714 // TODO: Handle TRUNCSTORE/LOADEXT
3715 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3716 if (ISD::isNON_TRUNCStore(Chain.Val)) {
3717 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
3718 if (PrevST->getBasePtr() == Ptr &&
3719 PrevST->getValue().getValueType() == N->getValueType(0))
3720 return CombineTo(N, Chain.getOperand(1), Chain);
3725 // Walk up chain skipping non-aliasing memory nodes.
3726 SDOperand BetterChain = FindBetterChain(N, Chain);
3728 // If there is a better chain.
3729 if (Chain != BetterChain) {
3732 // Replace the chain to void dependency.
3733 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
3734 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
3735 LD->getSrcValue(), LD->getSrcValueOffset(),
3736 LD->isVolatile(), LD->getAlignment());
3738 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
3739 LD->getValueType(0),
3740 BetterChain, Ptr, LD->getSrcValue(),
3741 LD->getSrcValueOffset(),
3744 LD->getAlignment());
3747 // Create token factor to keep old chain connected.
3748 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
3749 Chain, ReplLoad.getValue(1));
3751 // Replace uses with load result and token factor. Don't add users
3753 return CombineTo(N, ReplLoad.getValue(0), Token, false);
3757 // Try transforming N to an indexed load.
3758 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3759 return SDOperand(N, 0);
3764 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
3765 StoreSDNode *ST = cast<StoreSDNode>(N);
3766 SDOperand Chain = ST->getChain();
3767 SDOperand Value = ST->getValue();
3768 SDOperand Ptr = ST->getBasePtr();
3770 // If this is a store of a bit convert, store the input value if the
3771 // resultant store does not need a higher alignment than the original.
3772 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
3773 ST->getAddressingMode() == ISD::UNINDEXED) {
3774 unsigned Align = ST->getAlignment();
3775 MVT::ValueType SVT = Value.getOperand(0).getValueType();
3776 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
3777 getABITypeAlignment(MVT::getTypeForValueType(SVT));
3778 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
3779 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
3780 ST->getSrcValueOffset(), ST->isVolatile(), Align);
3783 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
3784 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
3785 if (Value.getOpcode() != ISD::TargetConstantFP) {
3787 switch (CFP->getValueType(0)) {
3788 default: assert(0 && "Unknown FP type");
3790 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
3791 Tmp = DAG.getConstant(FloatToBits(CFP->getValueAPF().convertToFloat()), MVT::i32);
3792 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3793 ST->getSrcValueOffset(), ST->isVolatile(),
3794 ST->getAlignment());
3798 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
3799 Tmp = DAG.getConstant(DoubleToBits(CFP->getValueAPF().convertToDouble()), MVT::i64);
3800 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3801 ST->getSrcValueOffset(), ST->isVolatile(),
3802 ST->getAlignment());
3803 } else if (TLI.isTypeLegal(MVT::i32)) {
3804 // Many FP stores are not make apparent until after legalize, e.g. for
3805 // argument passing. Since this is so common, custom legalize the
3806 // 64-bit integer store into two 32-bit stores.
3807 uint64_t Val = DoubleToBits(CFP->getValueAPF().convertToDouble());
3808 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
3809 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
3810 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
3812 int SVOffset = ST->getSrcValueOffset();
3813 unsigned Alignment = ST->getAlignment();
3814 bool isVolatile = ST->isVolatile();
3816 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
3817 ST->getSrcValueOffset(),
3818 isVolatile, ST->getAlignment());
3819 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3820 DAG.getConstant(4, Ptr.getValueType()));
3824 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
3825 SVOffset, isVolatile, Alignment);
3826 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
3834 // Walk up chain skipping non-aliasing memory nodes.
3835 SDOperand BetterChain = FindBetterChain(N, Chain);
3837 // If there is a better chain.
3838 if (Chain != BetterChain) {
3839 // Replace the chain to avoid dependency.
3840 SDOperand ReplStore;
3841 if (ST->isTruncatingStore()) {
3842 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
3843 ST->getSrcValue(), ST->getSrcValueOffset(), ST->getStoredVT(),
3844 ST->isVolatile(), ST->getAlignment());
3846 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
3847 ST->getSrcValue(), ST->getSrcValueOffset(),
3848 ST->isVolatile(), ST->getAlignment());
3851 // Create token to keep both nodes around.
3853 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
3855 // Don't add users to work list.
3856 return CombineTo(N, Token, false);
3860 // Try transforming N to an indexed store.
3861 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3862 return SDOperand(N, 0);
3867 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
3868 SDOperand InVec = N->getOperand(0);
3869 SDOperand InVal = N->getOperand(1);
3870 SDOperand EltNo = N->getOperand(2);
3872 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
3873 // vector with the inserted element.
3874 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3875 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3876 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3877 if (Elt < Ops.size())
3879 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
3880 &Ops[0], Ops.size());
3886 SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
3887 unsigned NumInScalars = N->getNumOperands();
3888 MVT::ValueType VT = N->getValueType(0);
3889 unsigned NumElts = MVT::getVectorNumElements(VT);
3890 MVT::ValueType EltType = MVT::getVectorElementType(VT);
3892 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
3893 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
3894 // at most two distinct vectors, turn this into a shuffle node.
3895 SDOperand VecIn1, VecIn2;
3896 for (unsigned i = 0; i != NumInScalars; ++i) {
3897 // Ignore undef inputs.
3898 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3900 // If this input is something other than a EXTRACT_VECTOR_ELT with a
3901 // constant index, bail out.
3902 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
3903 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
3904 VecIn1 = VecIn2 = SDOperand(0, 0);
3908 // If the input vector type disagrees with the result of the build_vector,
3909 // we can't make a shuffle.
3910 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
3911 if (ExtractedFromVec.getValueType() != VT) {
3912 VecIn1 = VecIn2 = SDOperand(0, 0);
3916 // Otherwise, remember this. We allow up to two distinct input vectors.
3917 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
3920 if (VecIn1.Val == 0) {
3921 VecIn1 = ExtractedFromVec;
3922 } else if (VecIn2.Val == 0) {
3923 VecIn2 = ExtractedFromVec;
3926 VecIn1 = VecIn2 = SDOperand(0, 0);
3931 // If everything is good, we can make a shuffle operation.
3933 SmallVector<SDOperand, 8> BuildVecIndices;
3934 for (unsigned i = 0; i != NumInScalars; ++i) {
3935 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
3936 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
3940 SDOperand Extract = N->getOperand(i);
3942 // If extracting from the first vector, just use the index directly.
3943 if (Extract.getOperand(0) == VecIn1) {
3944 BuildVecIndices.push_back(Extract.getOperand(1));
3948 // Otherwise, use InIdx + VecSize
3949 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
3950 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
3951 TLI.getPointerTy()));
3954 // Add count and size info.
3955 MVT::ValueType BuildVecVT =
3956 MVT::getVectorType(TLI.getPointerTy(), NumElts);
3958 // Return the new VECTOR_SHUFFLE node.
3964 // Use an undef build_vector as input for the second operand.
3965 std::vector<SDOperand> UnOps(NumInScalars,
3966 DAG.getNode(ISD::UNDEF,
3968 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT,
3969 &UnOps[0], UnOps.size());
3970 AddToWorkList(Ops[1].Val);
3972 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT,
3973 &BuildVecIndices[0], BuildVecIndices.size());
3974 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3);
3980 SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
3981 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
3982 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
3983 // inputs come from at most two distinct vectors, turn this into a shuffle
3986 // If we only have one input vector, we don't need to do any concatenation.
3987 if (N->getNumOperands() == 1) {
3988 return N->getOperand(0);
3994 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
3995 SDOperand ShufMask = N->getOperand(2);
3996 unsigned NumElts = ShufMask.getNumOperands();
3998 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3999 bool isIdentity = true;
4000 for (unsigned i = 0; i != NumElts; ++i) {
4001 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4002 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
4007 if (isIdentity) return N->getOperand(0);
4009 // If the shuffle mask is an identity operation on the RHS, return the RHS.
4011 for (unsigned i = 0; i != NumElts; ++i) {
4012 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
4013 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
4018 if (isIdentity) return N->getOperand(1);
4020 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
4022 bool isUnary = true;
4023 bool isSplat = true;
4025 unsigned BaseIdx = 0;
4026 for (unsigned i = 0; i != NumElts; ++i)
4027 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
4028 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
4029 int V = (Idx < NumElts) ? 0 : 1;
4043 SDOperand N0 = N->getOperand(0);
4044 SDOperand N1 = N->getOperand(1);
4045 // Normalize unary shuffle so the RHS is undef.
4046 if (isUnary && VecNum == 1)
4049 // If it is a splat, check if the argument vector is a build_vector with
4050 // all scalar elements the same.
4054 // If this is a bit convert that changes the element type of the vector but
4055 // not the number of vector elements, look through it. Be careful not to
4056 // look though conversions that change things like v4f32 to v2f64.
4057 if (V->getOpcode() == ISD::BIT_CONVERT) {
4058 SDOperand ConvInput = V->getOperand(0);
4059 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts)
4063 if (V->getOpcode() == ISD::BUILD_VECTOR) {
4064 unsigned NumElems = V->getNumOperands();
4065 if (NumElems > BaseIdx) {
4067 bool AllSame = true;
4068 for (unsigned i = 0; i != NumElems; ++i) {
4069 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
4070 Base = V->getOperand(i);
4074 // Splat of <u, u, u, u>, return <u, u, u, u>
4077 for (unsigned i = 0; i != NumElems; ++i) {
4078 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
4079 V->getOperand(i) != Base) {
4084 // Splat of <x, x, x, x>, return <x, x, x, x>
4091 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
4093 if (isUnary || N0 == N1) {
4094 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
4096 SmallVector<SDOperand, 8> MappedOps;
4097 for (unsigned i = 0; i != NumElts; ++i) {
4098 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
4099 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
4100 MappedOps.push_back(ShufMask.getOperand(i));
4103 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
4104 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
4107 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
4108 &MappedOps[0], MappedOps.size());
4109 AddToWorkList(ShufMask.Val);
4110 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
4112 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
4119 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
4120 /// an AND to a vector_shuffle with the destination vector and a zero vector.
4121 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
4122 /// vector_shuffle V, Zero, <0, 4, 2, 4>
4123 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
4124 SDOperand LHS = N->getOperand(0);
4125 SDOperand RHS = N->getOperand(1);
4126 if (N->getOpcode() == ISD::AND) {
4127 if (RHS.getOpcode() == ISD::BIT_CONVERT)
4128 RHS = RHS.getOperand(0);
4129 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
4130 std::vector<SDOperand> IdxOps;
4131 unsigned NumOps = RHS.getNumOperands();
4132 unsigned NumElts = NumOps;
4133 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType());
4134 for (unsigned i = 0; i != NumElts; ++i) {
4135 SDOperand Elt = RHS.getOperand(i);
4136 if (!isa<ConstantSDNode>(Elt))
4138 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
4139 IdxOps.push_back(DAG.getConstant(i, EVT));
4140 else if (cast<ConstantSDNode>(Elt)->isNullValue())
4141 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
4146 // Let's see if the target supports this vector_shuffle.
4147 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
4150 // Return the new VECTOR_SHUFFLE node.
4151 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts);
4152 std::vector<SDOperand> Ops;
4153 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
4155 AddToWorkList(LHS.Val);
4156 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
4157 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4158 &ZeroOps[0], ZeroOps.size()));
4159 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT,
4160 &IdxOps[0], IdxOps.size()));
4161 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT,
4162 &Ops[0], Ops.size());
4163 if (VT != LHS.getValueType()) {
4164 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result);
4172 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
4173 SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
4174 // After legalize, the target may be depending on adds and other
4175 // binary ops to provide legal ways to construct constants or other
4176 // things. Simplifying them may result in a loss of legality.
4177 if (AfterLegalize) return SDOperand();
4179 MVT::ValueType VT = N->getValueType(0);
4180 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!");
4182 MVT::ValueType EltType = MVT::getVectorElementType(VT);
4183 SDOperand LHS = N->getOperand(0);
4184 SDOperand RHS = N->getOperand(1);
4185 SDOperand Shuffle = XformToShuffleWithZero(N);
4186 if (Shuffle.Val) return Shuffle;
4188 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
4190 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
4191 RHS.getOpcode() == ISD::BUILD_VECTOR) {
4192 SmallVector<SDOperand, 8> Ops;
4193 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
4194 SDOperand LHSOp = LHS.getOperand(i);
4195 SDOperand RHSOp = RHS.getOperand(i);
4196 // If these two elements can't be folded, bail out.
4197 if ((LHSOp.getOpcode() != ISD::UNDEF &&
4198 LHSOp.getOpcode() != ISD::Constant &&
4199 LHSOp.getOpcode() != ISD::ConstantFP) ||
4200 (RHSOp.getOpcode() != ISD::UNDEF &&
4201 RHSOp.getOpcode() != ISD::Constant &&
4202 RHSOp.getOpcode() != ISD::ConstantFP))
4204 // Can't fold divide by zero.
4205 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
4206 N->getOpcode() == ISD::FDIV) {
4207 if ((RHSOp.getOpcode() == ISD::Constant &&
4208 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
4209 (RHSOp.getOpcode() == ISD::ConstantFP &&
4210 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
4213 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp));
4214 AddToWorkList(Ops.back().Val);
4215 assert((Ops.back().getOpcode() == ISD::UNDEF ||
4216 Ops.back().getOpcode() == ISD::Constant ||
4217 Ops.back().getOpcode() == ISD::ConstantFP) &&
4218 "Scalar binop didn't fold!");
4221 if (Ops.size() == LHS.getNumOperands()) {
4222 MVT::ValueType VT = LHS.getValueType();
4223 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
4230 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
4231 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
4233 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
4234 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4235 // If we got a simplified select_cc node back from SimplifySelectCC, then
4236 // break it down into a new SETCC node, and a new SELECT node, and then return
4237 // the SELECT node, since we were called with a SELECT node.
4239 // Check to see if we got a select_cc back (to turn into setcc/select).
4240 // Otherwise, just return whatever node we got back, like fabs.
4241 if (SCC.getOpcode() == ISD::SELECT_CC) {
4242 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
4243 SCC.getOperand(0), SCC.getOperand(1),
4245 AddToWorkList(SETCC.Val);
4246 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
4247 SCC.getOperand(3), SETCC);
4254 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
4255 /// are the two values being selected between, see if we can simplify the
4256 /// select. Callers of this should assume that TheSelect is deleted if this
4257 /// returns true. As such, they should return the appropriate thing (e.g. the
4258 /// node) back to the top-level of the DAG combiner loop to avoid it being
4261 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
4264 // If this is a select from two identical things, try to pull the operation
4265 // through the select.
4266 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
4267 // If this is a load and the token chain is identical, replace the select
4268 // of two loads with a load through a select of the address to load from.
4269 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
4270 // constants have been dropped into the constant pool.
4271 if (LHS.getOpcode() == ISD::LOAD &&
4272 // Token chains must be identical.
4273 LHS.getOperand(0) == RHS.getOperand(0)) {
4274 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
4275 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
4277 // If this is an EXTLOAD, the VT's must match.
4278 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
4279 // FIXME: this conflates two src values, discarding one. This is not
4280 // the right thing to do, but nothing uses srcvalues now. When they do,
4281 // turn SrcValue into a list of locations.
4283 if (TheSelect->getOpcode() == ISD::SELECT) {
4284 // Check that the condition doesn't reach either load. If so, folding
4285 // this will induce a cycle into the DAG.
4286 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4287 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
4288 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
4289 TheSelect->getOperand(0), LLD->getBasePtr(),
4293 // Check that the condition doesn't reach either load. If so, folding
4294 // this will induce a cycle into the DAG.
4295 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4296 !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
4297 !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
4298 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
4299 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
4300 TheSelect->getOperand(0),
4301 TheSelect->getOperand(1),
4302 LLD->getBasePtr(), RLD->getBasePtr(),
4303 TheSelect->getOperand(4));
4309 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
4310 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
4311 Addr,LLD->getSrcValue(),
4312 LLD->getSrcValueOffset(),
4314 LLD->getAlignment());
4316 Load = DAG.getExtLoad(LLD->getExtensionType(),
4317 TheSelect->getValueType(0),
4318 LLD->getChain(), Addr, LLD->getSrcValue(),
4319 LLD->getSrcValueOffset(),
4322 LLD->getAlignment());
4324 // Users of the select now use the result of the load.
4325 CombineTo(TheSelect, Load);
4327 // Users of the old loads now use the new load's chain. We know the
4328 // old-load value is dead now.
4329 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
4330 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
4340 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
4341 SDOperand N2, SDOperand N3,
4342 ISD::CondCode CC, bool NotExtCompare) {
4344 MVT::ValueType VT = N2.getValueType();
4345 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
4346 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
4347 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
4349 // Determine if the condition we're dealing with is constant
4350 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
4351 if (SCC.Val) AddToWorkList(SCC.Val);
4352 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
4354 // fold select_cc true, x, y -> x
4355 if (SCCC && SCCC->getValue())
4357 // fold select_cc false, x, y -> y
4358 if (SCCC && SCCC->getValue() == 0)
4361 // Check to see if we can simplify the select into an fabs node
4362 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
4363 // Allow either -0.0 or 0.0
4364 if (CFP->getValueAPF().isZero()) {
4365 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
4366 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
4367 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
4368 N2 == N3.getOperand(0))
4369 return DAG.getNode(ISD::FABS, VT, N0);
4371 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
4372 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
4373 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
4374 N2.getOperand(0) == N3)
4375 return DAG.getNode(ISD::FABS, VT, N3);
4379 // Check to see if we can perform the "gzip trick", transforming
4380 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
4381 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
4382 MVT::isInteger(N0.getValueType()) &&
4383 MVT::isInteger(N2.getValueType()) &&
4384 (N1C->isNullValue() || // (a < 0) ? b : 0
4385 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
4386 MVT::ValueType XType = N0.getValueType();
4387 MVT::ValueType AType = N2.getValueType();
4388 if (XType >= AType) {
4389 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
4390 // single-bit constant.
4391 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
4392 unsigned ShCtV = Log2_64(N2C->getValue());
4393 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
4394 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
4395 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
4396 AddToWorkList(Shift.Val);
4397 if (XType > AType) {
4398 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4399 AddToWorkList(Shift.Val);
4401 return DAG.getNode(ISD::AND, AType, Shift, N2);
4403 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4404 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4405 TLI.getShiftAmountTy()));
4406 AddToWorkList(Shift.Val);
4407 if (XType > AType) {
4408 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
4409 AddToWorkList(Shift.Val);
4411 return DAG.getNode(ISD::AND, AType, Shift, N2);
4415 // fold select C, 16, 0 -> shl C, 4
4416 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
4417 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
4419 // If the caller doesn't want us to simplify this into a zext of a compare,
4421 if (NotExtCompare && N2C->getValue() == 1)
4424 // Get a SetCC of the condition
4425 // FIXME: Should probably make sure that setcc is legal if we ever have a
4426 // target where it isn't.
4427 SDOperand Temp, SCC;
4428 // cast from setcc result type to select result type
4429 if (AfterLegalize) {
4430 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4431 if (N2.getValueType() < SCC.getValueType())
4432 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
4434 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4436 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
4437 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
4439 AddToWorkList(SCC.Val);
4440 AddToWorkList(Temp.Val);
4442 if (N2C->getValue() == 1)
4444 // shl setcc result by log2 n2c
4445 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
4446 DAG.getConstant(Log2_64(N2C->getValue()),
4447 TLI.getShiftAmountTy()));
4450 // Check to see if this is the equivalent of setcc
4451 // FIXME: Turn all of these into setcc if setcc if setcc is legal
4452 // otherwise, go ahead with the folds.
4453 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
4454 MVT::ValueType XType = N0.getValueType();
4455 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
4456 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
4457 if (Res.getValueType() != VT)
4458 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
4462 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
4463 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
4464 TLI.isOperationLegal(ISD::CTLZ, XType)) {
4465 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
4466 return DAG.getNode(ISD::SRL, XType, Ctlz,
4467 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
4468 TLI.getShiftAmountTy()));
4470 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
4471 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
4472 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
4474 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
4475 DAG.getConstant(~0ULL, XType));
4476 return DAG.getNode(ISD::SRL, XType,
4477 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
4478 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4479 TLI.getShiftAmountTy()));
4481 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
4482 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
4483 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
4484 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4485 TLI.getShiftAmountTy()));
4486 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
4490 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
4491 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4492 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
4493 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
4494 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
4495 MVT::ValueType XType = N0.getValueType();
4496 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4497 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4498 TLI.getShiftAmountTy()));
4499 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4500 AddToWorkList(Shift.Val);
4501 AddToWorkList(Add.Val);
4502 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4504 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
4505 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
4506 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
4507 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
4508 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
4509 MVT::ValueType XType = N0.getValueType();
4510 if (SubC->isNullValue() && MVT::isInteger(XType)) {
4511 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
4512 DAG.getConstant(MVT::getSizeInBits(XType)-1,
4513 TLI.getShiftAmountTy()));
4514 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
4515 AddToWorkList(Shift.Val);
4516 AddToWorkList(Add.Val);
4517 return DAG.getNode(ISD::XOR, XType, Add, Shift);
4525 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
4526 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
4527 SDOperand N1, ISD::CondCode Cond,
4528 bool foldBooleans) {
4529 TargetLowering::DAGCombinerInfo
4530 DagCombineInfo(DAG, !AfterLegalize, false, this);
4531 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo);
4534 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4535 /// return a DAG expression to select that will generate the same value by
4536 /// multiplying by a magic number. See:
4537 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4538 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4539 std::vector<SDNode*> Built;
4540 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4542 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4548 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4549 /// return a DAG expression to select that will generate the same value by
4550 /// multiplying by a magic number. See:
4551 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4552 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4553 std::vector<SDNode*> Built;
4554 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4556 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4562 /// FindBaseOffset - Return true if base is known not to alias with anything
4563 /// but itself. Provides base object and offset as results.
4564 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4565 // Assume it is a primitive operation.
4566 Base = Ptr; Offset = 0;
4568 // If it's an adding a simple constant then integrate the offset.
4569 if (Base.getOpcode() == ISD::ADD) {
4570 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4571 Base = Base.getOperand(0);
4572 Offset += C->getValue();
4576 // If it's any of the following then it can't alias with anything but itself.
4577 return isa<FrameIndexSDNode>(Base) ||
4578 isa<ConstantPoolSDNode>(Base) ||
4579 isa<GlobalAddressSDNode>(Base);
4582 /// isAlias - Return true if there is any possibility that the two addresses
4584 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4585 const Value *SrcValue1, int SrcValueOffset1,
4586 SDOperand Ptr2, int64_t Size2,
4587 const Value *SrcValue2, int SrcValueOffset2)
4589 // If they are the same then they must be aliases.
4590 if (Ptr1 == Ptr2) return true;
4592 // Gather base node and offset information.
4593 SDOperand Base1, Base2;
4594 int64_t Offset1, Offset2;
4595 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4596 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4598 // If they have a same base address then...
4599 if (Base1 == Base2) {
4600 // Check to see if the addresses overlap.
4601 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4604 // If we know both bases then they can't alias.
4605 if (KnownBase1 && KnownBase2) return false;
4607 if (CombinerGlobalAA) {
4608 // Use alias analysis information.
4609 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
4610 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
4611 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
4612 AliasAnalysis::AliasResult AAResult =
4613 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4614 if (AAResult == AliasAnalysis::NoAlias)
4618 // Otherwise we have to assume they alias.
4622 /// FindAliasInfo - Extracts the relevant alias information from the memory
4623 /// node. Returns true if the operand was a load.
4624 bool DAGCombiner::FindAliasInfo(SDNode *N,
4625 SDOperand &Ptr, int64_t &Size,
4626 const Value *&SrcValue, int &SrcValueOffset) {
4627 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4628 Ptr = LD->getBasePtr();
4629 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4630 SrcValue = LD->getSrcValue();
4631 SrcValueOffset = LD->getSrcValueOffset();
4633 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4634 Ptr = ST->getBasePtr();
4635 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4636 SrcValue = ST->getSrcValue();
4637 SrcValueOffset = ST->getSrcValueOffset();
4639 assert(0 && "FindAliasInfo expected a memory operand");
4645 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4646 /// looking for aliasing nodes and adding them to the Aliases vector.
4647 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4648 SmallVector<SDOperand, 8> &Aliases) {
4649 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4650 std::set<SDNode *> Visited; // Visited node set.
4652 // Get alias information for node.
4655 const Value *SrcValue;
4657 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4660 Chains.push_back(OriginalChain);
4662 // Look at each chain and determine if it is an alias. If so, add it to the
4663 // aliases list. If not, then continue up the chain looking for the next
4665 while (!Chains.empty()) {
4666 SDOperand Chain = Chains.back();
4669 // Don't bother if we've been before.
4670 if (Visited.find(Chain.Val) != Visited.end()) continue;
4671 Visited.insert(Chain.Val);
4673 switch (Chain.getOpcode()) {
4674 case ISD::EntryToken:
4675 // Entry token is ideal chain operand, but handled in FindBetterChain.
4680 // Get alias information for Chain.
4683 const Value *OpSrcValue;
4684 int OpSrcValueOffset;
4685 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4686 OpSrcValue, OpSrcValueOffset);
4688 // If chain is alias then stop here.
4689 if (!(IsLoad && IsOpLoad) &&
4690 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4691 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4692 Aliases.push_back(Chain);
4694 // Look further up the chain.
4695 Chains.push_back(Chain.getOperand(0));
4696 // Clean up old chain.
4697 AddToWorkList(Chain.Val);
4702 case ISD::TokenFactor:
4703 // We have to check each of the operands of the token factor, so we queue
4704 // then up. Adding the operands to the queue (stack) in reverse order
4705 // maintains the original order and increases the likelihood that getNode
4706 // will find a matching token factor (CSE.)
4707 for (unsigned n = Chain.getNumOperands(); n;)
4708 Chains.push_back(Chain.getOperand(--n));
4709 // Eliminate the token factor if we can.
4710 AddToWorkList(Chain.Val);
4714 // For all other instructions we will just have to take what we can get.
4715 Aliases.push_back(Chain);
4721 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4722 /// for a better chain (aliasing node.)
4723 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4724 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4726 // Accumulate all the aliases to this node.
4727 GatherAllAliases(N, OldChain, Aliases);
4729 if (Aliases.size() == 0) {
4730 // If no operands then chain to entry token.
4731 return DAG.getEntryNode();
4732 } else if (Aliases.size() == 1) {
4733 // If a single operand then chain to it. We don't need to revisit it.
4737 // Construct a custom tailored token factor.
4738 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4739 &Aliases[0], Aliases.size());
4741 // Make sure the old chain gets cleaned up.
4742 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4747 // SelectionDAG::Combine - This is the entry point for the file.
4749 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4750 if (!RunningAfterLegalize && ViewDAGCombine1)
4752 if (RunningAfterLegalize && ViewDAGCombine2)
4754 /// run - This is the main entry point to this class.
4756 DAGCombiner(*this, AA).Run(RunningAfterLegalize);