1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/ADT/SetVector.h"
21 #include "llvm/ADT/SmallBitVector.h"
22 #include "llvm/ADT/SmallPtrSet.h"
23 #include "llvm/ADT/Statistic.h"
24 #include "llvm/Analysis/AliasAnalysis.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetLowering.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
39 #include "llvm/Target/TargetSubtargetInfo.h"
43 #define DEBUG_TYPE "dagcombine"
45 STATISTIC(NodesCombined , "Number of dag nodes combined");
46 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
47 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
48 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
49 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
50 STATISTIC(SlicedLoads, "Number of load sliced");
54 CombinerAA("combiner-alias-analysis", cl::Hidden,
55 cl::desc("Enable DAG combiner alias-analysis heuristics"));
58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
59 cl::desc("Enable DAG combiner's use of IR alias analysis"));
62 UseTBAA("combiner-use-tbaa", cl::Hidden, cl::init(true),
63 cl::desc("Enable DAG combiner's use of TBAA"));
66 static cl::opt<std::string>
67 CombinerAAOnlyFunc("combiner-aa-only-func", cl::Hidden,
68 cl::desc("Only use DAG-combiner alias analysis in this"
72 /// Hidden option to stress test load slicing, i.e., when this option
73 /// is enabled, load slicing bypasses most of its profitability guards.
75 StressLoadSlicing("combiner-stress-load-slicing", cl::Hidden,
76 cl::desc("Bypass the profitability model of load "
81 MaySplitLoadIndex("combiner-split-load-index", cl::Hidden, cl::init(true),
82 cl::desc("DAG combiner may split indexing from loads"));
84 //------------------------------ DAGCombiner ---------------------------------//
88 const TargetLowering &TLI;
90 CodeGenOpt::Level OptLevel;
95 /// \brief Worklist of all of the nodes that need to be simplified.
97 /// This must behave as a stack -- new nodes to process are pushed onto the
98 /// back and when processing we pop off of the back.
100 /// The worklist will not contain duplicates but may contain null entries
101 /// due to nodes being deleted from the underlying DAG.
102 SmallVector<SDNode *, 64> Worklist;
104 /// \brief Mapping from an SDNode to its position on the worklist.
106 /// This is used to find and remove nodes from the worklist (by nulling
107 /// them) when they are deleted from the underlying DAG. It relies on
108 /// stable indices of nodes within the worklist.
109 DenseMap<SDNode *, unsigned> WorklistMap;
111 /// \brief Set of nodes which have been combined (at least once).
113 /// This is used to allow us to reliably add any operands of a DAG node
114 /// which have not yet been combined to the worklist.
115 SmallPtrSet<SDNode *, 64> CombinedNodes;
117 // AA - Used for DAG load/store alias analysis.
120 /// When an instruction is simplified, add all users of the instruction to
121 /// the work lists because they might get more simplified now.
122 void AddUsersToWorklist(SDNode *N) {
123 for (SDNode *Node : N->uses())
127 /// Call the node-specific routine that folds each particular type of node.
128 SDValue visit(SDNode *N);
131 /// Add to the worklist making sure its instance is at the back (next to be
133 void AddToWorklist(SDNode *N) {
134 // Skip handle nodes as they can't usefully be combined and confuse the
135 // zero-use deletion strategy.
136 if (N->getOpcode() == ISD::HANDLENODE)
139 if (WorklistMap.insert(std::make_pair(N, Worklist.size())).second)
140 Worklist.push_back(N);
143 /// Remove all instances of N from the worklist.
144 void removeFromWorklist(SDNode *N) {
145 CombinedNodes.erase(N);
147 auto It = WorklistMap.find(N);
148 if (It == WorklistMap.end())
149 return; // Not in the worklist.
151 // Null out the entry rather than erasing it to avoid a linear operation.
152 Worklist[It->second] = nullptr;
153 WorklistMap.erase(It);
156 void deleteAndRecombine(SDNode *N);
157 bool recursivelyDeleteUnusedNodes(SDNode *N);
159 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
162 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
163 return CombineTo(N, &Res, 1, AddTo);
166 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
168 SDValue To[] = { Res0, Res1 };
169 return CombineTo(N, To, 2, AddTo);
172 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
176 /// Check the specified integer node value to see if it can be simplified or
177 /// if things it uses can be simplified by bit propagation.
178 /// If so, return true.
179 bool SimplifyDemandedBits(SDValue Op) {
180 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
181 APInt Demanded = APInt::getAllOnesValue(BitWidth);
182 return SimplifyDemandedBits(Op, Demanded);
185 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
187 bool CombineToPreIndexedLoadStore(SDNode *N);
188 bool CombineToPostIndexedLoadStore(SDNode *N);
189 SDValue SplitIndexingFromLoad(LoadSDNode *LD);
190 bool SliceUpLoad(SDNode *N);
192 /// \brief Replace an ISD::EXTRACT_VECTOR_ELT of a load with a narrowed
195 /// \param EVE ISD::EXTRACT_VECTOR_ELT to be replaced.
196 /// \param InVecVT type of the input vector to EVE with bitcasts resolved.
197 /// \param EltNo index of the vector element to load.
198 /// \param OriginalLoad load that EVE came from to be replaced.
199 /// \returns EVE on success SDValue() on failure.
200 SDValue ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
201 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad);
202 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
203 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
204 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
205 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
206 SDValue PromoteIntBinOp(SDValue Op);
207 SDValue PromoteIntShiftOp(SDValue Op);
208 SDValue PromoteExtend(SDValue Op);
209 bool PromoteLoad(SDValue Op);
211 void ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
212 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
213 ISD::NodeType ExtType);
215 /// Call the node-specific routine that knows how to fold each
216 /// particular type of node. If that doesn't do anything, try the
217 /// target-specific DAG combines.
218 SDValue combine(SDNode *N);
220 // Visitation implementation - Implement dag node combining for different
221 // node types. The semantics are as follows:
223 // SDValue.getNode() == 0 - No change was made
224 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
225 // otherwise - N should be replaced by the returned Operand.
227 SDValue visitTokenFactor(SDNode *N);
228 SDValue visitMERGE_VALUES(SDNode *N);
229 SDValue visitADD(SDNode *N);
230 SDValue visitSUB(SDNode *N);
231 SDValue visitADDC(SDNode *N);
232 SDValue visitSUBC(SDNode *N);
233 SDValue visitADDE(SDNode *N);
234 SDValue visitSUBE(SDNode *N);
235 SDValue visitMUL(SDNode *N);
236 SDValue visitSDIV(SDNode *N);
237 SDValue visitUDIV(SDNode *N);
238 SDValue visitSREM(SDNode *N);
239 SDValue visitUREM(SDNode *N);
240 SDValue visitMULHU(SDNode *N);
241 SDValue visitMULHS(SDNode *N);
242 SDValue visitSMUL_LOHI(SDNode *N);
243 SDValue visitUMUL_LOHI(SDNode *N);
244 SDValue visitSMULO(SDNode *N);
245 SDValue visitUMULO(SDNode *N);
246 SDValue visitSDIVREM(SDNode *N);
247 SDValue visitUDIVREM(SDNode *N);
248 SDValue visitAND(SDNode *N);
249 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *LocReference);
250 SDValue visitOR(SDNode *N);
251 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *LocReference);
252 SDValue visitXOR(SDNode *N);
253 SDValue SimplifyVBinOp(SDNode *N);
254 SDValue visitSHL(SDNode *N);
255 SDValue visitSRA(SDNode *N);
256 SDValue visitSRL(SDNode *N);
257 SDValue visitRotate(SDNode *N);
258 SDValue visitBSWAP(SDNode *N);
259 SDValue visitCTLZ(SDNode *N);
260 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N);
261 SDValue visitCTTZ(SDNode *N);
262 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N);
263 SDValue visitCTPOP(SDNode *N);
264 SDValue visitSELECT(SDNode *N);
265 SDValue visitVSELECT(SDNode *N);
266 SDValue visitSELECT_CC(SDNode *N);
267 SDValue visitSETCC(SDNode *N);
268 SDValue visitSIGN_EXTEND(SDNode *N);
269 SDValue visitZERO_EXTEND(SDNode *N);
270 SDValue visitANY_EXTEND(SDNode *N);
271 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
272 SDValue visitSIGN_EXTEND_VECTOR_INREG(SDNode *N);
273 SDValue visitTRUNCATE(SDNode *N);
274 SDValue visitBITCAST(SDNode *N);
275 SDValue visitBUILD_PAIR(SDNode *N);
276 SDValue visitFADD(SDNode *N);
277 SDValue visitFSUB(SDNode *N);
278 SDValue visitFMUL(SDNode *N);
279 SDValue visitFMA(SDNode *N);
280 SDValue visitFDIV(SDNode *N);
281 SDValue visitFREM(SDNode *N);
282 SDValue visitFSQRT(SDNode *N);
283 SDValue visitFCOPYSIGN(SDNode *N);
284 SDValue visitSINT_TO_FP(SDNode *N);
285 SDValue visitUINT_TO_FP(SDNode *N);
286 SDValue visitFP_TO_SINT(SDNode *N);
287 SDValue visitFP_TO_UINT(SDNode *N);
288 SDValue visitFP_ROUND(SDNode *N);
289 SDValue visitFP_ROUND_INREG(SDNode *N);
290 SDValue visitFP_EXTEND(SDNode *N);
291 SDValue visitFNEG(SDNode *N);
292 SDValue visitFABS(SDNode *N);
293 SDValue visitFCEIL(SDNode *N);
294 SDValue visitFTRUNC(SDNode *N);
295 SDValue visitFFLOOR(SDNode *N);
296 SDValue visitFMINNUM(SDNode *N);
297 SDValue visitFMAXNUM(SDNode *N);
298 SDValue visitBRCOND(SDNode *N);
299 SDValue visitBR_CC(SDNode *N);
300 SDValue visitLOAD(SDNode *N);
301 SDValue visitSTORE(SDNode *N);
302 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
303 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
304 SDValue visitBUILD_VECTOR(SDNode *N);
305 SDValue visitCONCAT_VECTORS(SDNode *N);
306 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
307 SDValue visitVECTOR_SHUFFLE(SDNode *N);
308 SDValue visitSCALAR_TO_VECTOR(SDNode *N);
309 SDValue visitINSERT_SUBVECTOR(SDNode *N);
310 SDValue visitMLOAD(SDNode *N);
311 SDValue visitMSTORE(SDNode *N);
312 SDValue visitMGATHER(SDNode *N);
313 SDValue visitMSCATTER(SDNode *N);
314 SDValue visitFP_TO_FP16(SDNode *N);
316 SDValue visitFADDForFMACombine(SDNode *N);
317 SDValue visitFSUBForFMACombine(SDNode *N);
319 SDValue XformToShuffleWithZero(SDNode *N);
320 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS);
322 SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
324 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
325 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
326 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
327 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
328 SDValue N3, ISD::CondCode CC,
329 bool NotExtCompare = false);
330 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
331 SDLoc DL, bool foldBooleans = true);
333 bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
335 bool isOneUseSetCC(SDValue N) const;
337 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
339 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
340 SDValue CombineExtLoad(SDNode *N);
341 SDValue combineRepeatedFPDivisors(SDNode *N);
342 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
343 SDValue BuildSDIV(SDNode *N);
344 SDValue BuildSDIVPow2(SDNode *N);
345 SDValue BuildUDIV(SDNode *N);
346 SDValue BuildReciprocalEstimate(SDValue Op);
347 SDValue BuildRsqrtEstimate(SDValue Op);
348 SDValue BuildRsqrtNROneConst(SDValue Op, SDValue Est, unsigned Iterations);
349 SDValue BuildRsqrtNRTwoConst(SDValue Op, SDValue Est, unsigned Iterations);
350 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
351 bool DemandHighBits = true);
352 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
353 SDNode *MatchRotatePosNeg(SDValue Shifted, SDValue Pos, SDValue Neg,
354 SDValue InnerPos, SDValue InnerNeg,
355 unsigned PosOpcode, unsigned NegOpcode,
357 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL);
358 SDValue ReduceLoadWidth(SDNode *N);
359 SDValue ReduceLoadOpStoreWidth(SDNode *N);
360 SDValue TransformFPLoadStorePair(SDNode *N);
361 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N);
362 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N);
364 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
366 /// Walk up chain skipping non-aliasing memory nodes,
367 /// looking for aliasing nodes and adding them to the Aliases vector.
368 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
369 SmallVectorImpl<SDValue> &Aliases);
371 /// Return true if there is any possibility that the two addresses overlap.
372 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const;
374 /// Walk up chain skipping non-aliasing memory nodes, looking for a better
375 /// chain (aliasing node.)
376 SDValue FindBetterChain(SDNode *N, SDValue Chain);
378 /// Holds a pointer to an LSBaseSDNode as well as information on where it
379 /// is located in a sequence of memory operations connected by a chain.
381 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq):
382 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { }
383 // Ptr to the mem node.
384 LSBaseSDNode *MemNode;
385 // Offset from the base ptr.
386 int64_t OffsetFromBase;
387 // What is the sequence number of this mem node.
388 // Lowest mem operand in the DAG starts at zero.
389 unsigned SequenceNum;
392 /// This is a helper function for MergeStoresOfConstantsOrVecElts. Returns a
393 /// constant build_vector of the stored constant values in Stores.
394 SDValue getMergedConstantVectorStore(SelectionDAG &DAG,
396 ArrayRef<MemOpLink> Stores,
399 /// This is a helper function for MergeConsecutiveStores. When the source
400 /// elements of the consecutive stores are all constants or all extracted
401 /// vector elements, try to merge them into one larger store.
402 /// \return True if a merged store was created.
403 bool MergeStoresOfConstantsOrVecElts(SmallVectorImpl<MemOpLink> &StoreNodes,
404 EVT MemVT, unsigned NumElem,
405 bool IsConstantSrc, bool UseVector);
407 /// This is a helper function for MergeConsecutiveStores.
408 /// Stores that may be merged are placed in StoreNodes.
409 /// Loads that may alias with those stores are placed in AliasLoadNodes.
410 void getStoreMergeAndAliasCandidates(
411 StoreSDNode* St, SmallVectorImpl<MemOpLink> &StoreNodes,
412 SmallVectorImpl<LSBaseSDNode*> &AliasLoadNodes);
414 /// Merge consecutive store operations into a wide store.
415 /// This optimization uses wide integers or vectors when possible.
416 /// \return True if some memory operations were changed.
417 bool MergeConsecutiveStores(StoreSDNode *N);
419 /// \brief Try to transform a truncation where C is a constant:
420 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
422 /// \p N needs to be a truncation and its first operand an AND. Other
423 /// requirements are checked by the function (e.g. that trunc is
424 /// single-use) and if missed an empty SDValue is returned.
425 SDValue distributeTruncateThroughAnd(SDNode *N);
428 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
429 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
430 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {
431 ForCodeSize = DAG.getMachineFunction().getFunction()->optForSize();
434 /// Runs the dag combiner on all nodes in the work list
435 void Run(CombineLevel AtLevel);
437 SelectionDAG &getDAG() const { return DAG; }
439 /// Returns a type large enough to hold any valid shift amount - before type
440 /// legalization these can be huge.
441 EVT getShiftAmountTy(EVT LHSTy) {
442 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
443 if (LHSTy.isVector())
445 auto &DL = DAG.getDataLayout();
446 return LegalTypes ? TLI.getScalarShiftAmountTy(DL, LHSTy)
447 : TLI.getPointerTy(DL);
450 /// This method returns true if we are running before type legalization or
451 /// if the specified VT is legal.
452 bool isTypeLegal(const EVT &VT) {
453 if (!LegalTypes) return true;
454 return TLI.isTypeLegal(VT);
457 /// Convenience wrapper around TargetLowering::getSetCCResultType
458 EVT getSetCCResultType(EVT VT) const {
459 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
466 /// This class is a DAGUpdateListener that removes any deleted
467 /// nodes from the worklist.
468 class WorklistRemover : public SelectionDAG::DAGUpdateListener {
471 explicit WorklistRemover(DAGCombiner &dc)
472 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {}
474 void NodeDeleted(SDNode *N, SDNode *E) override {
475 DC.removeFromWorklist(N);
480 //===----------------------------------------------------------------------===//
481 // TargetLowering::DAGCombinerInfo implementation
482 //===----------------------------------------------------------------------===//
484 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
485 ((DAGCombiner*)DC)->AddToWorklist(N);
488 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
489 ((DAGCombiner*)DC)->removeFromWorklist(N);
492 SDValue TargetLowering::DAGCombinerInfo::
493 CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo) {
494 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
497 SDValue TargetLowering::DAGCombinerInfo::
498 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
499 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
503 SDValue TargetLowering::DAGCombinerInfo::
504 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
505 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
508 void TargetLowering::DAGCombinerInfo::
509 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
510 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
513 //===----------------------------------------------------------------------===//
515 //===----------------------------------------------------------------------===//
517 void DAGCombiner::deleteAndRecombine(SDNode *N) {
518 removeFromWorklist(N);
520 // If the operands of this node are only used by the node, they will now be
521 // dead. Make sure to re-visit them and recursively delete dead nodes.
522 for (const SDValue &Op : N->ops())
523 // For an operand generating multiple values, one of the values may
524 // become dead allowing further simplification (e.g. split index
525 // arithmetic from an indexed load).
526 if (Op->hasOneUse() || Op->getNumValues() > 1)
527 AddToWorklist(Op.getNode());
532 /// Return 1 if we can compute the negated form of the specified expression for
533 /// the same cost as the expression itself, or 2 if we can compute the negated
534 /// form more cheaply than the expression itself.
535 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
536 const TargetLowering &TLI,
537 const TargetOptions *Options,
538 unsigned Depth = 0) {
539 // fneg is removable even if it has multiple uses.
540 if (Op.getOpcode() == ISD::FNEG) return 2;
542 // Don't allow anything with multiple uses.
543 if (!Op.hasOneUse()) return 0;
545 // Don't recurse exponentially.
546 if (Depth > 6) return 0;
548 switch (Op.getOpcode()) {
549 default: return false;
550 case ISD::ConstantFP:
551 // Don't invert constant FP values after legalize. The negated constant
552 // isn't necessarily legal.
553 return LegalOperations ? 0 : 1;
555 // FIXME: determine better conditions for this xform.
556 if (!Options->UnsafeFPMath) return 0;
558 // After operation legalization, it might not be legal to create new FSUBs.
559 if (LegalOperations &&
560 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType()))
563 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
564 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
567 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
568 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
571 // We can't turn -(A-B) into B-A when we honor signed zeros.
572 if (!Options->UnsafeFPMath) return 0;
574 // fold (fneg (fsub A, B)) -> (fsub B, A)
579 if (Options->HonorSignDependentRoundingFPMath()) return 0;
581 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
582 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI,
586 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options,
592 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options,
597 /// If isNegatibleForFree returns true, return the newly negated expression.
598 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
599 bool LegalOperations, unsigned Depth = 0) {
600 const TargetOptions &Options = DAG.getTarget().Options;
601 // fneg is removable even if it has multiple uses.
602 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
604 // Don't allow anything with multiple uses.
605 assert(Op.hasOneUse() && "Unknown reuse!");
607 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
608 switch (Op.getOpcode()) {
609 default: llvm_unreachable("Unknown code");
610 case ISD::ConstantFP: {
611 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
613 return DAG.getConstantFP(V, SDLoc(Op), Op.getValueType());
616 // FIXME: determine better conditions for this xform.
617 assert(Options.UnsafeFPMath);
619 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
620 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
621 DAG.getTargetLoweringInfo(), &Options, Depth+1))
622 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
623 GetNegatedExpression(Op.getOperand(0), DAG,
624 LegalOperations, Depth+1),
626 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
627 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
628 GetNegatedExpression(Op.getOperand(1), DAG,
629 LegalOperations, Depth+1),
632 // We can't turn -(A-B) into B-A when we honor signed zeros.
633 assert(Options.UnsafeFPMath);
635 // fold (fneg (fsub 0, B)) -> B
636 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
638 return Op.getOperand(1);
640 // fold (fneg (fsub A, B)) -> (fsub B, A)
641 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(),
642 Op.getOperand(1), Op.getOperand(0));
646 assert(!Options.HonorSignDependentRoundingFPMath());
648 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
649 if (isNegatibleForFree(Op.getOperand(0), LegalOperations,
650 DAG.getTargetLoweringInfo(), &Options, Depth+1))
651 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
652 GetNegatedExpression(Op.getOperand(0), DAG,
653 LegalOperations, Depth+1),
656 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
657 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
659 GetNegatedExpression(Op.getOperand(1), DAG,
660 LegalOperations, Depth+1));
664 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
665 GetNegatedExpression(Op.getOperand(0), DAG,
666 LegalOperations, Depth+1));
668 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(),
669 GetNegatedExpression(Op.getOperand(0), DAG,
670 LegalOperations, Depth+1),
675 // Return true if this node is a setcc, or is a select_cc
676 // that selects between the target values used for true and false, making it
677 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
678 // the appropriate nodes based on the type of node we are checking. This
679 // simplifies life a bit for the callers.
680 bool DAGCombiner::isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
682 if (N.getOpcode() == ISD::SETCC) {
683 LHS = N.getOperand(0);
684 RHS = N.getOperand(1);
685 CC = N.getOperand(2);
689 if (N.getOpcode() != ISD::SELECT_CC ||
690 !TLI.isConstTrueVal(N.getOperand(2).getNode()) ||
691 !TLI.isConstFalseVal(N.getOperand(3).getNode()))
694 if (TLI.getBooleanContents(N.getValueType()) ==
695 TargetLowering::UndefinedBooleanContent)
698 LHS = N.getOperand(0);
699 RHS = N.getOperand(1);
700 CC = N.getOperand(4);
704 /// Return true if this is a SetCC-equivalent operation with only one use.
705 /// If this is true, it allows the users to invert the operation for free when
706 /// it is profitable to do so.
707 bool DAGCombiner::isOneUseSetCC(SDValue N) const {
709 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
714 /// Returns true if N is a BUILD_VECTOR node whose
715 /// elements are all the same constant or undefined.
716 static bool isConstantSplatVector(SDNode *N, APInt& SplatValue) {
717 BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(N);
722 unsigned SplatBitSize;
724 EVT EltVT = N->getValueType(0).getVectorElementType();
725 return (C->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
727 EltVT.getSizeInBits() >= SplatBitSize);
730 // \brief Returns the SDNode if it is a constant integer BuildVector
731 // or constant integer.
732 static SDNode *isConstantIntBuildVectorOrConstantInt(SDValue N) {
733 if (isa<ConstantSDNode>(N))
735 if (ISD::isBuildVectorOfConstantSDNodes(N.getNode()))
740 // \brief Returns the SDNode if it is a constant float BuildVector
741 // or constant float.
742 static SDNode *isConstantFPBuildVectorOrConstantFP(SDValue N) {
743 if (isa<ConstantFPSDNode>(N))
745 if (ISD::isBuildVectorOfConstantFPSDNodes(N.getNode()))
750 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
752 static ConstantSDNode *isConstOrConstSplat(SDValue N) {
753 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
756 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
757 BitVector UndefElements;
758 ConstantSDNode *CN = BV->getConstantSplatNode(&UndefElements);
760 // BuildVectors can truncate their operands. Ignore that case here.
761 // FIXME: We blindly ignore splats which include undef which is overly
763 if (CN && UndefElements.none() &&
764 CN->getValueType(0) == N.getValueType().getScalarType())
771 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
773 static ConstantFPSDNode *isConstOrConstSplatFP(SDValue N) {
774 if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
777 if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
778 BitVector UndefElements;
779 ConstantFPSDNode *CN = BV->getConstantFPSplatNode(&UndefElements);
781 if (CN && UndefElements.none())
788 SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL,
789 SDValue N0, SDValue N1) {
790 EVT VT = N0.getValueType();
791 if (N0.getOpcode() == Opc) {
792 if (SDNode *L = isConstantIntBuildVectorOrConstantInt(N0.getOperand(1))) {
793 if (SDNode *R = isConstantIntBuildVectorOrConstantInt(N1)) {
794 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
795 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, L, R))
796 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
799 if (N0.hasOneUse()) {
800 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one
802 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N0.getOperand(0), N1);
803 if (!OpNode.getNode())
805 AddToWorklist(OpNode.getNode());
806 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
811 if (N1.getOpcode() == Opc) {
812 if (SDNode *R = isConstantIntBuildVectorOrConstantInt(N1.getOperand(1))) {
813 if (SDNode *L = isConstantIntBuildVectorOrConstantInt(N0)) {
814 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
815 if (SDValue OpNode = DAG.FoldConstantArithmetic(Opc, DL, VT, R, L))
816 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
819 if (N1.hasOneUse()) {
820 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one
822 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, N1.getOperand(0), N0);
823 if (!OpNode.getNode())
825 AddToWorklist(OpNode.getNode());
826 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
834 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
836 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
838 DEBUG(dbgs() << "\nReplacing.1 ";
840 dbgs() << "\nWith: ";
841 To[0].getNode()->dump(&DAG);
842 dbgs() << " and " << NumTo-1 << " other values\n");
843 for (unsigned i = 0, e = NumTo; i != e; ++i)
844 assert((!To[i].getNode() ||
845 N->getValueType(i) == To[i].getValueType()) &&
846 "Cannot combine value to value of different type!");
848 WorklistRemover DeadNodes(*this);
849 DAG.ReplaceAllUsesWith(N, To);
851 // Push the new nodes and any users onto the worklist
852 for (unsigned i = 0, e = NumTo; i != e; ++i) {
853 if (To[i].getNode()) {
854 AddToWorklist(To[i].getNode());
855 AddUsersToWorklist(To[i].getNode());
860 // Finally, if the node is now dead, remove it from the graph. The node
861 // may not be dead if the replacement process recursively simplified to
862 // something else needing this node.
864 deleteAndRecombine(N);
865 return SDValue(N, 0);
869 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
870 // Replace all uses. If any nodes become isomorphic to other nodes and
871 // are deleted, make sure to remove them from our worklist.
872 WorklistRemover DeadNodes(*this);
873 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New);
875 // Push the new node and any (possibly new) users onto the worklist.
876 AddToWorklist(TLO.New.getNode());
877 AddUsersToWorklist(TLO.New.getNode());
879 // Finally, if the node is now dead, remove it from the graph. The node
880 // may not be dead if the replacement process recursively simplified to
881 // something else needing this node.
882 if (TLO.Old.getNode()->use_empty())
883 deleteAndRecombine(TLO.Old.getNode());
886 /// Check the specified integer node value to see if it can be simplified or if
887 /// things it uses can be simplified by bit propagation. If so, return true.
888 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
889 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
890 APInt KnownZero, KnownOne;
891 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
895 AddToWorklist(Op.getNode());
897 // Replace the old value with the new one.
899 DEBUG(dbgs() << "\nReplacing.2 ";
900 TLO.Old.getNode()->dump(&DAG);
901 dbgs() << "\nWith: ";
902 TLO.New.getNode()->dump(&DAG);
905 CommitTargetLoweringOpt(TLO);
909 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
911 EVT VT = Load->getValueType(0);
912 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
914 DEBUG(dbgs() << "\nReplacing.9 ";
916 dbgs() << "\nWith: ";
917 Trunc.getNode()->dump(&DAG);
919 WorklistRemover DeadNodes(*this);
920 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc);
921 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1));
922 deleteAndRecombine(Load);
923 AddToWorklist(Trunc.getNode());
926 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
929 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
930 EVT MemVT = LD->getMemoryVT();
931 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
932 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
934 : LD->getExtensionType();
936 return DAG.getExtLoad(ExtType, dl, PVT,
937 LD->getChain(), LD->getBasePtr(),
938 MemVT, LD->getMemOperand());
941 unsigned Opc = Op.getOpcode();
944 case ISD::AssertSext:
945 return DAG.getNode(ISD::AssertSext, dl, PVT,
946 SExtPromoteOperand(Op.getOperand(0), PVT),
948 case ISD::AssertZext:
949 return DAG.getNode(ISD::AssertZext, dl, PVT,
950 ZExtPromoteOperand(Op.getOperand(0), PVT),
952 case ISD::Constant: {
954 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
955 return DAG.getNode(ExtOpc, dl, PVT, Op);
959 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
961 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
964 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
965 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
967 EVT OldVT = Op.getValueType();
969 bool Replace = false;
970 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
971 if (!NewOp.getNode())
973 AddToWorklist(NewOp.getNode());
976 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
977 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
978 DAG.getValueType(OldVT));
981 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
982 EVT OldVT = Op.getValueType();
984 bool Replace = false;
985 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
986 if (!NewOp.getNode())
988 AddToWorklist(NewOp.getNode());
991 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
992 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
995 /// Promote the specified integer binary operation if the target indicates it is
996 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
997 /// i32 since i16 instructions are longer.
998 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
999 if (!LegalOperations)
1002 EVT VT = Op.getValueType();
1003 if (VT.isVector() || !VT.isInteger())
1006 // If operation type is 'undesirable', e.g. i16 on x86, consider
1008 unsigned Opc = Op.getOpcode();
1009 if (TLI.isTypeDesirableForOp(Opc, VT))
1013 // Consult target whether it is a good idea to promote this operation and
1014 // what's the right type to promote it to.
1015 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1016 assert(PVT != VT && "Don't know what type to promote to!");
1018 bool Replace0 = false;
1019 SDValue N0 = Op.getOperand(0);
1020 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
1024 bool Replace1 = false;
1025 SDValue N1 = Op.getOperand(1);
1030 NN1 = PromoteOperand(N1, PVT, Replace1);
1035 AddToWorklist(NN0.getNode());
1037 AddToWorklist(NN1.getNode());
1040 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
1042 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
1044 DEBUG(dbgs() << "\nPromoting ";
1045 Op.getNode()->dump(&DAG));
1047 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1048 DAG.getNode(Opc, dl, PVT, NN0, NN1));
1053 /// Promote the specified integer shift operation if the target indicates it is
1054 /// beneficial. e.g. On x86, it's usually better to promote i16 operations to
1055 /// i32 since i16 instructions are longer.
1056 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
1057 if (!LegalOperations)
1060 EVT VT = Op.getValueType();
1061 if (VT.isVector() || !VT.isInteger())
1064 // If operation type is 'undesirable', e.g. i16 on x86, consider
1066 unsigned Opc = Op.getOpcode();
1067 if (TLI.isTypeDesirableForOp(Opc, VT))
1071 // Consult target whether it is a good idea to promote this operation and
1072 // what's the right type to promote it to.
1073 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1074 assert(PVT != VT && "Don't know what type to promote to!");
1076 bool Replace = false;
1077 SDValue N0 = Op.getOperand(0);
1078 if (Opc == ISD::SRA)
1079 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
1080 else if (Opc == ISD::SRL)
1081 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
1083 N0 = PromoteOperand(N0, PVT, Replace);
1087 AddToWorklist(N0.getNode());
1089 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
1091 DEBUG(dbgs() << "\nPromoting ";
1092 Op.getNode()->dump(&DAG));
1094 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1095 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
1100 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
1101 if (!LegalOperations)
1104 EVT VT = Op.getValueType();
1105 if (VT.isVector() || !VT.isInteger())
1108 // If operation type is 'undesirable', e.g. i16 on x86, consider
1110 unsigned Opc = Op.getOpcode();
1111 if (TLI.isTypeDesirableForOp(Opc, VT))
1115 // Consult target whether it is a good idea to promote this operation and
1116 // what's the right type to promote it to.
1117 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1118 assert(PVT != VT && "Don't know what type to promote to!");
1119 // fold (aext (aext x)) -> (aext x)
1120 // fold (aext (zext x)) -> (zext x)
1121 // fold (aext (sext x)) -> (sext x)
1122 DEBUG(dbgs() << "\nPromoting ";
1123 Op.getNode()->dump(&DAG));
1124 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0));
1129 bool DAGCombiner::PromoteLoad(SDValue Op) {
1130 if (!LegalOperations)
1133 EVT VT = Op.getValueType();
1134 if (VT.isVector() || !VT.isInteger())
1137 // If operation type is 'undesirable', e.g. i16 on x86, consider
1139 unsigned Opc = Op.getOpcode();
1140 if (TLI.isTypeDesirableForOp(Opc, VT))
1144 // Consult target whether it is a good idea to promote this operation and
1145 // what's the right type to promote it to.
1146 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
1147 assert(PVT != VT && "Don't know what type to promote to!");
1150 SDNode *N = Op.getNode();
1151 LoadSDNode *LD = cast<LoadSDNode>(N);
1152 EVT MemVT = LD->getMemoryVT();
1153 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
1154 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, PVT, MemVT) ? ISD::ZEXTLOAD
1156 : LD->getExtensionType();
1157 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
1158 LD->getChain(), LD->getBasePtr(),
1159 MemVT, LD->getMemOperand());
1160 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
1162 DEBUG(dbgs() << "\nPromoting ";
1165 Result.getNode()->dump(&DAG);
1167 WorklistRemover DeadNodes(*this);
1168 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
1169 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1));
1170 deleteAndRecombine(N);
1171 AddToWorklist(Result.getNode());
1177 /// \brief Recursively delete a node which has no uses and any operands for
1178 /// which it is the only use.
1180 /// Note that this both deletes the nodes and removes them from the worklist.
1181 /// It also adds any nodes who have had a user deleted to the worklist as they
1182 /// may now have only one use and subject to other combines.
1183 bool DAGCombiner::recursivelyDeleteUnusedNodes(SDNode *N) {
1184 if (!N->use_empty())
1187 SmallSetVector<SDNode *, 16> Nodes;
1190 N = Nodes.pop_back_val();
1194 if (N->use_empty()) {
1195 for (const SDValue &ChildN : N->op_values())
1196 Nodes.insert(ChildN.getNode());
1198 removeFromWorklist(N);
1203 } while (!Nodes.empty());
1207 //===----------------------------------------------------------------------===//
1208 // Main DAG Combiner implementation
1209 //===----------------------------------------------------------------------===//
1211 void DAGCombiner::Run(CombineLevel AtLevel) {
1212 // set the instance variables, so that the various visit routines may use it.
1214 LegalOperations = Level >= AfterLegalizeVectorOps;
1215 LegalTypes = Level >= AfterLegalizeTypes;
1217 // Add all the dag nodes to the worklist.
1218 for (SDNode &Node : DAG.allnodes())
1219 AddToWorklist(&Node);
1221 // Create a dummy node (which is not added to allnodes), that adds a reference
1222 // to the root node, preventing it from being deleted, and tracking any
1223 // changes of the root.
1224 HandleSDNode Dummy(DAG.getRoot());
1226 // while the worklist isn't empty, find a node and
1227 // try and combine it.
1228 while (!WorklistMap.empty()) {
1230 // The Worklist holds the SDNodes in order, but it may contain null entries.
1232 N = Worklist.pop_back_val();
1235 bool GoodWorklistEntry = WorklistMap.erase(N);
1236 (void)GoodWorklistEntry;
1237 assert(GoodWorklistEntry &&
1238 "Found a worklist entry without a corresponding map entry!");
1240 // If N has no uses, it is dead. Make sure to revisit all N's operands once
1241 // N is deleted from the DAG, since they too may now be dead or may have a
1242 // reduced number of uses, allowing other xforms.
1243 if (recursivelyDeleteUnusedNodes(N))
1246 WorklistRemover DeadNodes(*this);
1248 // If this combine is running after legalizing the DAG, re-legalize any
1249 // nodes pulled off the worklist.
1250 if (Level == AfterLegalizeDAG) {
1251 SmallSetVector<SDNode *, 16> UpdatedNodes;
1252 bool NIsValid = DAG.LegalizeOp(N, UpdatedNodes);
1254 for (SDNode *LN : UpdatedNodes) {
1256 AddUsersToWorklist(LN);
1262 DEBUG(dbgs() << "\nCombining: "; N->dump(&DAG));
1264 // Add any operands of the new node which have not yet been combined to the
1265 // worklist as well. Because the worklist uniques things already, this
1266 // won't repeatedly process the same operand.
1267 CombinedNodes.insert(N);
1268 for (const SDValue &ChildN : N->op_values())
1269 if (!CombinedNodes.count(ChildN.getNode()))
1270 AddToWorklist(ChildN.getNode());
1272 SDValue RV = combine(N);
1279 // If we get back the same node we passed in, rather than a new node or
1280 // zero, we know that the node must have defined multiple values and
1281 // CombineTo was used. Since CombineTo takes care of the worklist
1282 // mechanics for us, we have no work to do in this case.
1283 if (RV.getNode() == N)
1286 assert(N->getOpcode() != ISD::DELETED_NODE &&
1287 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
1288 "Node was deleted but visit returned new node!");
1290 DEBUG(dbgs() << " ... into: ";
1291 RV.getNode()->dump(&DAG));
1293 // Transfer debug value.
1294 DAG.TransferDbgValues(SDValue(N, 0), RV);
1295 if (N->getNumValues() == RV.getNode()->getNumValues())
1296 DAG.ReplaceAllUsesWith(N, RV.getNode());
1298 assert(N->getValueType(0) == RV.getValueType() &&
1299 N->getNumValues() == 1 && "Type mismatch");
1301 DAG.ReplaceAllUsesWith(N, &OpV);
1304 // Push the new node and any users onto the worklist
1305 AddToWorklist(RV.getNode());
1306 AddUsersToWorklist(RV.getNode());
1308 // Finally, if the node is now dead, remove it from the graph. The node
1309 // may not be dead if the replacement process recursively simplified to
1310 // something else needing this node. This will also take care of adding any
1311 // operands which have lost a user to the worklist.
1312 recursivelyDeleteUnusedNodes(N);
1315 // If the root changed (e.g. it was a dead load, update the root).
1316 DAG.setRoot(Dummy.getValue());
1317 DAG.RemoveDeadNodes();
1320 SDValue DAGCombiner::visit(SDNode *N) {
1321 switch (N->getOpcode()) {
1323 case ISD::TokenFactor: return visitTokenFactor(N);
1324 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1325 case ISD::ADD: return visitADD(N);
1326 case ISD::SUB: return visitSUB(N);
1327 case ISD::ADDC: return visitADDC(N);
1328 case ISD::SUBC: return visitSUBC(N);
1329 case ISD::ADDE: return visitADDE(N);
1330 case ISD::SUBE: return visitSUBE(N);
1331 case ISD::MUL: return visitMUL(N);
1332 case ISD::SDIV: return visitSDIV(N);
1333 case ISD::UDIV: return visitUDIV(N);
1334 case ISD::SREM: return visitSREM(N);
1335 case ISD::UREM: return visitUREM(N);
1336 case ISD::MULHU: return visitMULHU(N);
1337 case ISD::MULHS: return visitMULHS(N);
1338 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1339 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1340 case ISD::SMULO: return visitSMULO(N);
1341 case ISD::UMULO: return visitUMULO(N);
1342 case ISD::SDIVREM: return visitSDIVREM(N);
1343 case ISD::UDIVREM: return visitUDIVREM(N);
1344 case ISD::AND: return visitAND(N);
1345 case ISD::OR: return visitOR(N);
1346 case ISD::XOR: return visitXOR(N);
1347 case ISD::SHL: return visitSHL(N);
1348 case ISD::SRA: return visitSRA(N);
1349 case ISD::SRL: return visitSRL(N);
1351 case ISD::ROTL: return visitRotate(N);
1352 case ISD::BSWAP: return visitBSWAP(N);
1353 case ISD::CTLZ: return visitCTLZ(N);
1354 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N);
1355 case ISD::CTTZ: return visitCTTZ(N);
1356 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N);
1357 case ISD::CTPOP: return visitCTPOP(N);
1358 case ISD::SELECT: return visitSELECT(N);
1359 case ISD::VSELECT: return visitVSELECT(N);
1360 case ISD::SELECT_CC: return visitSELECT_CC(N);
1361 case ISD::SETCC: return visitSETCC(N);
1362 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1363 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1364 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1365 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1366 case ISD::SIGN_EXTEND_VECTOR_INREG: return visitSIGN_EXTEND_VECTOR_INREG(N);
1367 case ISD::TRUNCATE: return visitTRUNCATE(N);
1368 case ISD::BITCAST: return visitBITCAST(N);
1369 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1370 case ISD::FADD: return visitFADD(N);
1371 case ISD::FSUB: return visitFSUB(N);
1372 case ISD::FMUL: return visitFMUL(N);
1373 case ISD::FMA: return visitFMA(N);
1374 case ISD::FDIV: return visitFDIV(N);
1375 case ISD::FREM: return visitFREM(N);
1376 case ISD::FSQRT: return visitFSQRT(N);
1377 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1378 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1379 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1380 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1381 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1382 case ISD::FP_ROUND: return visitFP_ROUND(N);
1383 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1384 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1385 case ISD::FNEG: return visitFNEG(N);
1386 case ISD::FABS: return visitFABS(N);
1387 case ISD::FFLOOR: return visitFFLOOR(N);
1388 case ISD::FMINNUM: return visitFMINNUM(N);
1389 case ISD::FMAXNUM: return visitFMAXNUM(N);
1390 case ISD::FCEIL: return visitFCEIL(N);
1391 case ISD::FTRUNC: return visitFTRUNC(N);
1392 case ISD::BRCOND: return visitBRCOND(N);
1393 case ISD::BR_CC: return visitBR_CC(N);
1394 case ISD::LOAD: return visitLOAD(N);
1395 case ISD::STORE: return visitSTORE(N);
1396 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1397 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1398 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1399 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1400 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1401 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1402 case ISD::SCALAR_TO_VECTOR: return visitSCALAR_TO_VECTOR(N);
1403 case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);
1404 case ISD::MGATHER: return visitMGATHER(N);
1405 case ISD::MLOAD: return visitMLOAD(N);
1406 case ISD::MSCATTER: return visitMSCATTER(N);
1407 case ISD::MSTORE: return visitMSTORE(N);
1408 case ISD::FP_TO_FP16: return visitFP_TO_FP16(N);
1413 SDValue DAGCombiner::combine(SDNode *N) {
1414 SDValue RV = visit(N);
1416 // If nothing happened, try a target-specific DAG combine.
1417 if (!RV.getNode()) {
1418 assert(N->getOpcode() != ISD::DELETED_NODE &&
1419 "Node was deleted but visit returned NULL!");
1421 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1422 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1424 // Expose the DAG combiner to the target combiner impls.
1425 TargetLowering::DAGCombinerInfo
1426 DagCombineInfo(DAG, Level, false, this);
1428 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1432 // If nothing happened still, try promoting the operation.
1433 if (!RV.getNode()) {
1434 switch (N->getOpcode()) {
1442 RV = PromoteIntBinOp(SDValue(N, 0));
1447 RV = PromoteIntShiftOp(SDValue(N, 0));
1449 case ISD::SIGN_EXTEND:
1450 case ISD::ZERO_EXTEND:
1451 case ISD::ANY_EXTEND:
1452 RV = PromoteExtend(SDValue(N, 0));
1455 if (PromoteLoad(SDValue(N, 0)))
1461 // If N is a commutative binary node, try commuting it to enable more
1463 if (!RV.getNode() && SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1464 N->getNumValues() == 1) {
1465 SDValue N0 = N->getOperand(0);
1466 SDValue N1 = N->getOperand(1);
1468 // Constant operands are canonicalized to RHS.
1469 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1470 SDValue Ops[] = {N1, N0};
1472 if (const auto *BinNode = dyn_cast<BinaryWithFlagsSDNode>(N)) {
1473 CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
1476 CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops);
1479 return SDValue(CSENode, 0);
1486 /// Given a node, return its input chain if it has one, otherwise return a null
1488 static SDValue getInputChainForNode(SDNode *N) {
1489 if (unsigned NumOps = N->getNumOperands()) {
1490 if (N->getOperand(0).getValueType() == MVT::Other)
1491 return N->getOperand(0);
1492 if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1493 return N->getOperand(NumOps-1);
1494 for (unsigned i = 1; i < NumOps-1; ++i)
1495 if (N->getOperand(i).getValueType() == MVT::Other)
1496 return N->getOperand(i);
1501 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1502 // If N has two operands, where one has an input chain equal to the other,
1503 // the 'other' chain is redundant.
1504 if (N->getNumOperands() == 2) {
1505 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1506 return N->getOperand(0);
1507 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1508 return N->getOperand(1);
1511 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1512 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1513 SmallPtrSet<SDNode*, 16> SeenOps;
1514 bool Changed = false; // If we should replace this token factor.
1516 // Start out with this token factor.
1519 // Iterate through token factors. The TFs grows when new token factors are
1521 for (unsigned i = 0; i < TFs.size(); ++i) {
1522 SDNode *TF = TFs[i];
1524 // Check each of the operands.
1525 for (const SDValue &Op : TF->op_values()) {
1527 switch (Op.getOpcode()) {
1528 case ISD::EntryToken:
1529 // Entry tokens don't need to be added to the list. They are
1534 case ISD::TokenFactor:
1535 if (Op.hasOneUse() &&
1536 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1537 // Queue up for processing.
1538 TFs.push_back(Op.getNode());
1539 // Clean up in case the token factor is removed.
1540 AddToWorklist(Op.getNode());
1547 // Only add if it isn't already in the list.
1548 if (SeenOps.insert(Op.getNode()).second)
1559 // If we've changed things around then replace token factor.
1562 // The entry token is the only possible outcome.
1563 Result = DAG.getEntryNode();
1565 // New and improved token factor.
1566 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Ops);
1569 // Add users to worklist if AA is enabled, since it may introduce
1570 // a lot of new chained token factors while removing memory deps.
1571 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
1572 : DAG.getSubtarget().useAA();
1573 return CombineTo(N, Result, UseAA /*add to worklist*/);
1579 /// MERGE_VALUES can always be eliminated.
1580 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1581 WorklistRemover DeadNodes(*this);
1582 // Replacing results may cause a different MERGE_VALUES to suddenly
1583 // be CSE'd with N, and carry its uses with it. Iterate until no
1584 // uses remain, to ensure that the node can be safely deleted.
1585 // First add the users of this node to the work list so that they
1586 // can be tried again once they have new operands.
1587 AddUsersToWorklist(N);
1589 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1590 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i));
1591 } while (!N->use_empty());
1592 deleteAndRecombine(N);
1593 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1596 static bool isNullConstant(SDValue V) {
1597 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
1598 return Const != nullptr && Const->isNullValue();
1601 static bool isNullFPConstant(SDValue V) {
1602 ConstantFPSDNode *Const = dyn_cast<ConstantFPSDNode>(V);
1603 return Const != nullptr && Const->isZero() && !Const->isNegative();
1606 static bool isAllOnesConstant(SDValue V) {
1607 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
1608 return Const != nullptr && Const->isAllOnesValue();
1611 static bool isOneConstant(SDValue V) {
1612 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
1613 return Const != nullptr && Const->isOne();
1616 /// If \p N is a ContantSDNode with isOpaque() == false return it casted to a
1617 /// ContantSDNode pointer else nullptr.
1618 static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) {
1619 ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N);
1620 return Const != nullptr && !Const->isOpaque() ? Const : nullptr;
1623 SDValue DAGCombiner::visitADD(SDNode *N) {
1624 SDValue N0 = N->getOperand(0);
1625 SDValue N1 = N->getOperand(1);
1626 EVT VT = N0.getValueType();
1629 if (VT.isVector()) {
1630 if (SDValue FoldedVOp = SimplifyVBinOp(N))
1633 // fold (add x, 0) -> x, vector edition
1634 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1636 if (ISD::isBuildVectorAllZeros(N0.getNode()))
1640 // fold (add x, undef) -> undef
1641 if (N0.getOpcode() == ISD::UNDEF)
1643 if (N1.getOpcode() == ISD::UNDEF)
1645 // fold (add c1, c2) -> c1+c2
1646 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
1647 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
1649 return DAG.FoldConstantArithmetic(ISD::ADD, SDLoc(N), VT, N0C, N1C);
1650 // canonicalize constant to RHS
1651 if (isConstantIntBuildVectorOrConstantInt(N0) &&
1652 !isConstantIntBuildVectorOrConstantInt(N1))
1653 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0);
1654 // fold (add x, 0) -> x
1655 if (isNullConstant(N1))
1657 // fold (add Sym, c) -> Sym+c
1658 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1659 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1660 GA->getOpcode() == ISD::GlobalAddress)
1661 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1663 (uint64_t)N1C->getSExtValue());
1664 // fold ((c1-A)+c2) -> (c1+c2)-A
1665 if (N1C && N0.getOpcode() == ISD::SUB)
1666 if (ConstantSDNode *N0C = getAsNonOpaqueConstant(N0.getOperand(0))) {
1668 return DAG.getNode(ISD::SUB, DL, VT,
1669 DAG.getConstant(N1C->getAPIntValue()+
1670 N0C->getAPIntValue(), DL, VT),
1674 if (SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1))
1676 // fold ((0-A) + B) -> B-A
1677 if (N0.getOpcode() == ISD::SUB && isNullConstant(N0.getOperand(0)))
1678 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1));
1679 // fold (A + (0-B)) -> A-B
1680 if (N1.getOpcode() == ISD::SUB && isNullConstant(N1.getOperand(0)))
1681 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1));
1682 // fold (A+(B-A)) -> B
1683 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1684 return N1.getOperand(0);
1685 // fold ((B-A)+A) -> B
1686 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1687 return N0.getOperand(0);
1688 // fold (A+(B-(A+C))) to (B-C)
1689 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1690 N0 == N1.getOperand(1).getOperand(0))
1691 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1692 N1.getOperand(1).getOperand(1));
1693 // fold (A+(B-(C+A))) to (B-C)
1694 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1695 N0 == N1.getOperand(1).getOperand(1))
1696 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0),
1697 N1.getOperand(1).getOperand(0));
1698 // fold (A+((B-A)+or-C)) to (B+or-C)
1699 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1700 N1.getOperand(0).getOpcode() == ISD::SUB &&
1701 N0 == N1.getOperand(0).getOperand(1))
1702 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT,
1703 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1705 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1706 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1707 SDValue N00 = N0.getOperand(0);
1708 SDValue N01 = N0.getOperand(1);
1709 SDValue N10 = N1.getOperand(0);
1710 SDValue N11 = N1.getOperand(1);
1712 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1713 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1714 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
1715 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
1718 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1719 return SDValue(N, 0);
1721 // fold (a+b) -> (a|b) iff a and b share no bits.
1722 if (VT.isInteger() && !VT.isVector()) {
1723 APInt LHSZero, LHSOne;
1724 APInt RHSZero, RHSOne;
1725 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1727 if (LHSZero.getBoolValue()) {
1728 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1730 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1731 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1732 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero){
1733 if (!LegalOperations || TLI.isOperationLegal(ISD::OR, VT))
1734 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1);
1739 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1740 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
1741 isNullConstant(N1.getOperand(0).getOperand(0)))
1742 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0,
1743 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1744 N1.getOperand(0).getOperand(1),
1746 if (N0.getOpcode() == ISD::SHL && N0.getOperand(0).getOpcode() == ISD::SUB &&
1747 isNullConstant(N0.getOperand(0).getOperand(0)))
1748 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1,
1749 DAG.getNode(ISD::SHL, SDLoc(N), VT,
1750 N0.getOperand(0).getOperand(1),
1753 if (N1.getOpcode() == ISD::AND) {
1754 SDValue AndOp0 = N1.getOperand(0);
1755 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1756 unsigned DestBits = VT.getScalarType().getSizeInBits();
1758 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1759 // and similar xforms where the inner op is either ~0 or 0.
1760 if (NumSignBits == DestBits && isOneConstant(N1->getOperand(1))) {
1762 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1766 // add (sext i1), X -> sub X, (zext i1)
1767 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1768 N0.getOperand(0).getValueType() == MVT::i1 &&
1769 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1771 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1772 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1775 // add X, (sextinreg Y i1) -> sub X, (and Y 1)
1776 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1777 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
1778 if (TN->getVT() == MVT::i1) {
1780 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
1781 DAG.getConstant(1, DL, VT));
1782 return DAG.getNode(ISD::SUB, DL, VT, N0, ZExt);
1789 SDValue DAGCombiner::visitADDC(SDNode *N) {
1790 SDValue N0 = N->getOperand(0);
1791 SDValue N1 = N->getOperand(1);
1792 EVT VT = N0.getValueType();
1794 // If the flag result is dead, turn this into an ADD.
1795 if (!N->hasAnyUseOfValue(1))
1796 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1),
1797 DAG.getNode(ISD::CARRY_FALSE,
1798 SDLoc(N), MVT::Glue));
1800 // canonicalize constant to RHS.
1801 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1802 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1804 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
1806 // fold (addc x, 0) -> x + no carry out
1807 if (isNullConstant(N1))
1808 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1809 SDLoc(N), MVT::Glue));
1811 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1812 APInt LHSZero, LHSOne;
1813 APInt RHSZero, RHSOne;
1814 DAG.computeKnownBits(N0, LHSZero, LHSOne);
1816 if (LHSZero.getBoolValue()) {
1817 DAG.computeKnownBits(N1, RHSZero, RHSOne);
1819 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1820 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1821 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero)
1822 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1),
1823 DAG.getNode(ISD::CARRY_FALSE,
1824 SDLoc(N), MVT::Glue));
1830 SDValue DAGCombiner::visitADDE(SDNode *N) {
1831 SDValue N0 = N->getOperand(0);
1832 SDValue N1 = N->getOperand(1);
1833 SDValue CarryIn = N->getOperand(2);
1835 // canonicalize constant to RHS
1836 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1837 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1839 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
1842 // fold (adde x, y, false) -> (addc x, y)
1843 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1844 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1);
1849 // Since it may not be valid to emit a fold to zero for vector initializers
1850 // check if we can before folding.
1851 static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT,
1853 bool LegalOperations, bool LegalTypes) {
1855 return DAG.getConstant(0, DL, VT);
1856 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
1857 return DAG.getConstant(0, DL, VT);
1861 SDValue DAGCombiner::visitSUB(SDNode *N) {
1862 SDValue N0 = N->getOperand(0);
1863 SDValue N1 = N->getOperand(1);
1864 EVT VT = N0.getValueType();
1867 if (VT.isVector()) {
1868 if (SDValue FoldedVOp = SimplifyVBinOp(N))
1871 // fold (sub x, 0) -> x, vector edition
1872 if (ISD::isBuildVectorAllZeros(N1.getNode()))
1876 // fold (sub x, x) -> 0
1877 // FIXME: Refactor this and xor and other similar operations together.
1879 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
1880 // fold (sub c1, c2) -> c1-c2
1881 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
1882 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
1884 return DAG.FoldConstantArithmetic(ISD::SUB, SDLoc(N), VT, N0C, N1C);
1885 // fold (sub x, c) -> (add x, -c)
1888 return DAG.getNode(ISD::ADD, DL, VT, N0,
1889 DAG.getConstant(-N1C->getAPIntValue(), DL, VT));
1891 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1892 if (isAllOnesConstant(N0))
1893 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
1894 // fold A-(A-B) -> B
1895 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1896 return N1.getOperand(1);
1897 // fold (A+B)-A -> B
1898 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1899 return N0.getOperand(1);
1900 // fold (A+B)-B -> A
1901 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1902 return N0.getOperand(0);
1903 // fold C2-(A+C1) -> (C2-C1)-A
1904 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? nullptr :
1905 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1906 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1908 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(),
1910 return DAG.getNode(ISD::SUB, DL, VT, NewC,
1913 // fold ((A+(B+or-C))-B) -> A+or-C
1914 if (N0.getOpcode() == ISD::ADD &&
1915 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1916 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1917 N0.getOperand(1).getOperand(0) == N1)
1918 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT,
1919 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1920 // fold ((A+(C+B))-B) -> A+C
1921 if (N0.getOpcode() == ISD::ADD &&
1922 N0.getOperand(1).getOpcode() == ISD::ADD &&
1923 N0.getOperand(1).getOperand(1) == N1)
1924 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
1925 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1926 // fold ((A-(B-C))-C) -> A-B
1927 if (N0.getOpcode() == ISD::SUB &&
1928 N0.getOperand(1).getOpcode() == ISD::SUB &&
1929 N0.getOperand(1).getOperand(1) == N1)
1930 return DAG.getNode(ISD::SUB, SDLoc(N), VT,
1931 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1933 // If either operand of a sub is undef, the result is undef
1934 if (N0.getOpcode() == ISD::UNDEF)
1936 if (N1.getOpcode() == ISD::UNDEF)
1939 // If the relocation model supports it, consider symbol offsets.
1940 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1941 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1942 // fold (sub Sym, c) -> Sym-c
1943 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1944 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT,
1946 (uint64_t)N1C->getSExtValue());
1947 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1948 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1949 if (GA->getGlobal() == GB->getGlobal())
1950 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1954 // sub X, (sextinreg Y i1) -> add X, (and Y 1)
1955 if (N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
1956 VTSDNode *TN = cast<VTSDNode>(N1.getOperand(1));
1957 if (TN->getVT() == MVT::i1) {
1959 SDValue ZExt = DAG.getNode(ISD::AND, DL, VT, N1.getOperand(0),
1960 DAG.getConstant(1, DL, VT));
1961 return DAG.getNode(ISD::ADD, DL, VT, N0, ZExt);
1968 SDValue DAGCombiner::visitSUBC(SDNode *N) {
1969 SDValue N0 = N->getOperand(0);
1970 SDValue N1 = N->getOperand(1);
1971 EVT VT = N0.getValueType();
1973 // If the flag result is dead, turn this into an SUB.
1974 if (!N->hasAnyUseOfValue(1))
1975 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1),
1976 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1979 // fold (subc x, x) -> 0 + no borrow
1982 return CombineTo(N, DAG.getConstant(0, DL, VT),
1983 DAG.getNode(ISD::CARRY_FALSE, DL,
1987 // fold (subc x, 0) -> x + no borrow
1988 if (isNullConstant(N1))
1989 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
1992 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow
1993 if (isAllOnesConstant(N0))
1994 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0),
1995 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N),
2001 SDValue DAGCombiner::visitSUBE(SDNode *N) {
2002 SDValue N0 = N->getOperand(0);
2003 SDValue N1 = N->getOperand(1);
2004 SDValue CarryIn = N->getOperand(2);
2006 // fold (sube x, y, false) -> (subc x, y)
2007 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
2008 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);
2013 SDValue DAGCombiner::visitMUL(SDNode *N) {
2014 SDValue N0 = N->getOperand(0);
2015 SDValue N1 = N->getOperand(1);
2016 EVT VT = N0.getValueType();
2018 // fold (mul x, undef) -> 0
2019 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2020 return DAG.getConstant(0, SDLoc(N), VT);
2022 bool N0IsConst = false;
2023 bool N1IsConst = false;
2024 bool N1IsOpaqueConst = false;
2025 bool N0IsOpaqueConst = false;
2026 APInt ConstValue0, ConstValue1;
2028 if (VT.isVector()) {
2029 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2032 N0IsConst = isConstantSplatVector(N0.getNode(), ConstValue0);
2033 N1IsConst = isConstantSplatVector(N1.getNode(), ConstValue1);
2035 N0IsConst = isa<ConstantSDNode>(N0);
2037 ConstValue0 = cast<ConstantSDNode>(N0)->getAPIntValue();
2038 N0IsOpaqueConst = cast<ConstantSDNode>(N0)->isOpaque();
2040 N1IsConst = isa<ConstantSDNode>(N1);
2042 ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
2043 N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
2047 // fold (mul c1, c2) -> c1*c2
2048 if (N0IsConst && N1IsConst && !N0IsOpaqueConst && !N1IsOpaqueConst)
2049 return DAG.FoldConstantArithmetic(ISD::MUL, SDLoc(N), VT,
2050 N0.getNode(), N1.getNode());
2052 // canonicalize constant to RHS (vector doesn't have to splat)
2053 if (isConstantIntBuildVectorOrConstantInt(N0) &&
2054 !isConstantIntBuildVectorOrConstantInt(N1))
2055 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
2056 // fold (mul x, 0) -> 0
2057 if (N1IsConst && ConstValue1 == 0)
2059 // We require a splat of the entire scalar bit width for non-contiguous
2062 ConstValue1.getBitWidth() == VT.getScalarType().getSizeInBits();
2063 // fold (mul x, 1) -> x
2064 if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
2066 // fold (mul x, -1) -> 0-x
2067 if (N1IsConst && ConstValue1.isAllOnesValue()) {
2069 return DAG.getNode(ISD::SUB, DL, VT,
2070 DAG.getConstant(0, DL, VT), N0);
2072 // fold (mul x, (1 << c)) -> x << c
2073 if (N1IsConst && !N1IsOpaqueConst && ConstValue1.isPowerOf2() &&
2076 return DAG.getNode(ISD::SHL, DL, VT, N0,
2077 DAG.getConstant(ConstValue1.logBase2(), DL,
2078 getShiftAmountTy(N0.getValueType())));
2080 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
2081 if (N1IsConst && !N1IsOpaqueConst && (-ConstValue1).isPowerOf2() &&
2083 unsigned Log2Val = (-ConstValue1).logBase2();
2085 // FIXME: If the input is something that is easily negated (e.g. a
2086 // single-use add), we should put the negate there.
2087 return DAG.getNode(ISD::SUB, DL, VT,
2088 DAG.getConstant(0, DL, VT),
2089 DAG.getNode(ISD::SHL, DL, VT, N0,
2090 DAG.getConstant(Log2Val, DL,
2091 getShiftAmountTy(N0.getValueType()))));
2095 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
2096 if (N1IsConst && N0.getOpcode() == ISD::SHL &&
2097 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2098 isa<ConstantSDNode>(N0.getOperand(1)))) {
2099 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT,
2100 N1, N0.getOperand(1));
2101 AddToWorklist(C3.getNode());
2102 return DAG.getNode(ISD::MUL, SDLoc(N), VT,
2103 N0.getOperand(0), C3);
2106 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
2109 SDValue Sh(nullptr,0), Y(nullptr,0);
2110 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
2111 if (N0.getOpcode() == ISD::SHL &&
2112 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2113 isa<ConstantSDNode>(N0.getOperand(1))) &&
2114 N0.getNode()->hasOneUse()) {
2116 } else if (N1.getOpcode() == ISD::SHL &&
2117 isa<ConstantSDNode>(N1.getOperand(1)) &&
2118 N1.getNode()->hasOneUse()) {
2123 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2124 Sh.getOperand(0), Y);
2125 return DAG.getNode(ISD::SHL, SDLoc(N), VT,
2126 Mul, Sh.getOperand(1));
2130 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
2131 if (N1IsConst && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
2132 (isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
2133 isa<ConstantSDNode>(N0.getOperand(1))))
2134 return DAG.getNode(ISD::ADD, SDLoc(N), VT,
2135 DAG.getNode(ISD::MUL, SDLoc(N0), VT,
2136 N0.getOperand(0), N1),
2137 DAG.getNode(ISD::MUL, SDLoc(N1), VT,
2138 N0.getOperand(1), N1));
2141 if (SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1))
2147 SDValue DAGCombiner::visitSDIV(SDNode *N) {
2148 SDValue N0 = N->getOperand(0);
2149 SDValue N1 = N->getOperand(1);
2150 EVT VT = N->getValueType(0);
2154 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2157 // fold (sdiv c1, c2) -> c1/c2
2158 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2159 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2160 if (N0C && N1C && !N0C->isOpaque() && !N1C->isOpaque())
2161 return DAG.FoldConstantArithmetic(ISD::SDIV, SDLoc(N), VT, N0C, N1C);
2162 // fold (sdiv X, 1) -> X
2163 if (N1C && N1C->isOne())
2165 // fold (sdiv X, -1) -> 0-X
2166 if (N1C && N1C->isAllOnesValue()) {
2168 return DAG.getNode(ISD::SUB, DL, VT,
2169 DAG.getConstant(0, DL, VT), N0);
2171 // If we know the sign bits of both operands are zero, strength reduce to a
2172 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
2173 if (!VT.isVector()) {
2174 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2175 return DAG.getNode(ISD::UDIV, SDLoc(N), N1.getValueType(),
2179 // fold (sdiv X, pow2) -> simple ops after legalize
2180 // FIXME: We check for the exact bit here because the generic lowering gives
2181 // better results in that case. The target-specific lowering should learn how
2182 // to handle exact sdivs efficiently.
2183 if (N1C && !N1C->isNullValue() && !N1C->isOpaque() &&
2184 !cast<BinaryWithFlagsSDNode>(N)->Flags.hasExact() &&
2185 (N1C->getAPIntValue().isPowerOf2() ||
2186 (-N1C->getAPIntValue()).isPowerOf2())) {
2187 // If dividing by powers of two is cheap, then don't perform the following
2189 if (TLI.isPow2SDivCheap())
2192 // Target-specific implementation of sdiv x, pow2.
2193 if (SDValue Res = BuildSDIVPow2(N))
2196 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
2199 // Splat the sign bit into the register
2201 DAG.getNode(ISD::SRA, DL, VT, N0,
2202 DAG.getConstant(VT.getScalarSizeInBits() - 1, DL,
2203 getShiftAmountTy(N0.getValueType())));
2204 AddToWorklist(SGN.getNode());
2206 // Add (N0 < 0) ? abs2 - 1 : 0;
2208 DAG.getNode(ISD::SRL, DL, VT, SGN,
2209 DAG.getConstant(VT.getScalarSizeInBits() - lg2, DL,
2210 getShiftAmountTy(SGN.getValueType())));
2211 SDValue ADD = DAG.getNode(ISD::ADD, DL, VT, N0, SRL);
2212 AddToWorklist(SRL.getNode());
2213 AddToWorklist(ADD.getNode()); // Divide by pow2
2214 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, ADD,
2215 DAG.getConstant(lg2, DL,
2216 getShiftAmountTy(ADD.getValueType())));
2218 // If we're dividing by a positive value, we're done. Otherwise, we must
2219 // negate the result.
2220 if (N1C->getAPIntValue().isNonNegative())
2223 AddToWorklist(SRA.getNode());
2224 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
2227 // If integer divide is expensive and we satisfy the requirements, emit an
2228 // alternate sequence.
2229 if (N1C && !TLI.isIntDivCheap())
2230 if (SDValue Op = BuildSDIV(N))
2234 if (N0.getOpcode() == ISD::UNDEF)
2235 return DAG.getConstant(0, SDLoc(N), VT);
2236 // X / undef -> undef
2237 if (N1.getOpcode() == ISD::UNDEF)
2243 SDValue DAGCombiner::visitUDIV(SDNode *N) {
2244 SDValue N0 = N->getOperand(0);
2245 SDValue N1 = N->getOperand(1);
2246 EVT VT = N->getValueType(0);
2250 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2253 // fold (udiv c1, c2) -> c1/c2
2254 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2255 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2257 if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::UDIV, SDLoc(N), VT,
2260 // fold (udiv x, (1 << c)) -> x >>u c
2261 if (N1C && !N1C->isOpaque() && N1C->getAPIntValue().isPowerOf2()) {
2263 return DAG.getNode(ISD::SRL, DL, VT, N0,
2264 DAG.getConstant(N1C->getAPIntValue().logBase2(), DL,
2265 getShiftAmountTy(N0.getValueType())));
2267 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
2268 if (N1.getOpcode() == ISD::SHL) {
2269 if (ConstantSDNode *SHC = getAsNonOpaqueConstant(N1.getOperand(0))) {
2270 if (SHC->getAPIntValue().isPowerOf2()) {
2271 EVT ADDVT = N1.getOperand(1).getValueType();
2273 SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT,
2275 DAG.getConstant(SHC->getAPIntValue()
2278 AddToWorklist(Add.getNode());
2279 return DAG.getNode(ISD::SRL, DL, VT, N0, Add);
2283 // fold (udiv x, c) -> alternate
2284 if (N1C && !TLI.isIntDivCheap())
2285 if (SDValue Op = BuildUDIV(N))
2289 if (N0.getOpcode() == ISD::UNDEF)
2290 return DAG.getConstant(0, SDLoc(N), VT);
2291 // X / undef -> undef
2292 if (N1.getOpcode() == ISD::UNDEF)
2298 SDValue DAGCombiner::visitSREM(SDNode *N) {
2299 SDValue N0 = N->getOperand(0);
2300 SDValue N1 = N->getOperand(1);
2301 EVT VT = N->getValueType(0);
2303 // fold (srem c1, c2) -> c1%c2
2304 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2305 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2307 if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::SREM, SDLoc(N), VT,
2310 // If we know the sign bits of both operands are zero, strength reduce to a
2311 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
2312 if (!VT.isVector()) {
2313 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
2314 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1);
2317 // If X/C can be simplified by the division-by-constant logic, lower
2318 // X%C to the equivalent of X-X/C*C.
2319 if (N1C && !N1C->isNullValue()) {
2320 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1);
2321 AddToWorklist(Div.getNode());
2322 SDValue OptimizedDiv = combine(Div.getNode());
2323 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2324 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2326 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2327 AddToWorklist(Mul.getNode());
2333 if (N0.getOpcode() == ISD::UNDEF)
2334 return DAG.getConstant(0, SDLoc(N), VT);
2335 // X % undef -> undef
2336 if (N1.getOpcode() == ISD::UNDEF)
2342 SDValue DAGCombiner::visitUREM(SDNode *N) {
2343 SDValue N0 = N->getOperand(0);
2344 SDValue N1 = N->getOperand(1);
2345 EVT VT = N->getValueType(0);
2347 // fold (urem c1, c2) -> c1%c2
2348 ConstantSDNode *N0C = isConstOrConstSplat(N0);
2349 ConstantSDNode *N1C = isConstOrConstSplat(N1);
2351 if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::UREM, SDLoc(N), VT,
2354 // fold (urem x, pow2) -> (and x, pow2-1)
2355 if (N1C && !N1C->isNullValue() && !N1C->isOpaque() &&
2356 N1C->getAPIntValue().isPowerOf2()) {
2358 return DAG.getNode(ISD::AND, DL, VT, N0,
2359 DAG.getConstant(N1C->getAPIntValue() - 1, DL, VT));
2361 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
2362 if (N1.getOpcode() == ISD::SHL) {
2363 if (ConstantSDNode *SHC = getAsNonOpaqueConstant(N1.getOperand(0))) {
2364 if (SHC->getAPIntValue().isPowerOf2()) {
2367 DAG.getNode(ISD::ADD, DL, VT, N1,
2368 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), DL,
2370 AddToWorklist(Add.getNode());
2371 return DAG.getNode(ISD::AND, DL, VT, N0, Add);
2376 // If X/C can be simplified by the division-by-constant logic, lower
2377 // X%C to the equivalent of X-X/C*C.
2378 if (N1C && !N1C->isNullValue()) {
2379 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1);
2380 AddToWorklist(Div.getNode());
2381 SDValue OptimizedDiv = combine(Div.getNode());
2382 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
2383 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT,
2385 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul);
2386 AddToWorklist(Mul.getNode());
2392 if (N0.getOpcode() == ISD::UNDEF)
2393 return DAG.getConstant(0, SDLoc(N), VT);
2394 // X % undef -> undef
2395 if (N1.getOpcode() == ISD::UNDEF)
2401 SDValue DAGCombiner::visitMULHS(SDNode *N) {
2402 SDValue N0 = N->getOperand(0);
2403 SDValue N1 = N->getOperand(1);
2404 EVT VT = N->getValueType(0);
2407 // fold (mulhs x, 0) -> 0
2408 if (isNullConstant(N1))
2410 // fold (mulhs x, 1) -> (sra x, size(x)-1)
2411 if (isOneConstant(N1)) {
2413 return DAG.getNode(ISD::SRA, DL, N0.getValueType(), N0,
2414 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
2416 getShiftAmountTy(N0.getValueType())));
2418 // fold (mulhs x, undef) -> 0
2419 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2420 return DAG.getConstant(0, SDLoc(N), VT);
2422 // If the type twice as wide is legal, transform the mulhs to a wider multiply
2424 if (VT.isSimple() && !VT.isVector()) {
2425 MVT Simple = VT.getSimpleVT();
2426 unsigned SimpleSize = Simple.getSizeInBits();
2427 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2428 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2429 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2430 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2431 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2432 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2433 DAG.getConstant(SimpleSize, DL,
2434 getShiftAmountTy(N1.getValueType())));
2435 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2442 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2443 SDValue N0 = N->getOperand(0);
2444 SDValue N1 = N->getOperand(1);
2445 EVT VT = N->getValueType(0);
2448 // fold (mulhu x, 0) -> 0
2449 if (isNullConstant(N1))
2451 // fold (mulhu x, 1) -> 0
2452 if (isOneConstant(N1))
2453 return DAG.getConstant(0, DL, N0.getValueType());
2454 // fold (mulhu x, undef) -> 0
2455 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2456 return DAG.getConstant(0, DL, VT);
2458 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2460 if (VT.isSimple() && !VT.isVector()) {
2461 MVT Simple = VT.getSimpleVT();
2462 unsigned SimpleSize = Simple.getSizeInBits();
2463 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2464 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2465 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2466 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2467 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2468 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2469 DAG.getConstant(SimpleSize, DL,
2470 getShiftAmountTy(N1.getValueType())));
2471 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2478 /// Perform optimizations common to nodes that compute two values. LoOp and HiOp
2479 /// give the opcodes for the two computations that are being performed. Return
2480 /// true if a simplification was made.
2481 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2483 // If the high half is not needed, just compute the low half.
2484 bool HiExists = N->hasAnyUseOfValue(1);
2486 (!LegalOperations ||
2487 TLI.isOperationLegalOrCustom(LoOp, N->getValueType(0)))) {
2488 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2489 return CombineTo(N, Res, Res);
2492 // If the low half is not needed, just compute the high half.
2493 bool LoExists = N->hasAnyUseOfValue(0);
2495 (!LegalOperations ||
2496 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2497 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2498 return CombineTo(N, Res, Res);
2501 // If both halves are used, return as it is.
2502 if (LoExists && HiExists)
2505 // If the two computed results can be simplified separately, separate them.
2507 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), N->ops());
2508 AddToWorklist(Lo.getNode());
2509 SDValue LoOpt = combine(Lo.getNode());
2510 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2511 (!LegalOperations ||
2512 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2513 return CombineTo(N, LoOpt, LoOpt);
2517 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), N->ops());
2518 AddToWorklist(Hi.getNode());
2519 SDValue HiOpt = combine(Hi.getNode());
2520 if (HiOpt.getNode() && HiOpt != Hi &&
2521 (!LegalOperations ||
2522 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2523 return CombineTo(N, HiOpt, HiOpt);
2529 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2530 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS))
2533 EVT VT = N->getValueType(0);
2536 // If the type is twice as wide is legal, transform the mulhu to a wider
2537 // multiply plus a shift.
2538 if (VT.isSimple() && !VT.isVector()) {
2539 MVT Simple = VT.getSimpleVT();
2540 unsigned SimpleSize = Simple.getSizeInBits();
2541 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2542 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2543 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2544 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2545 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2546 // Compute the high part as N1.
2547 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2548 DAG.getConstant(SimpleSize, DL,
2549 getShiftAmountTy(Lo.getValueType())));
2550 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2551 // Compute the low part as N0.
2552 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2553 return CombineTo(N, Lo, Hi);
2560 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2561 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU))
2564 EVT VT = N->getValueType(0);
2567 // If the type is twice as wide is legal, transform the mulhu to a wider
2568 // multiply plus a shift.
2569 if (VT.isSimple() && !VT.isVector()) {
2570 MVT Simple = VT.getSimpleVT();
2571 unsigned SimpleSize = Simple.getSizeInBits();
2572 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2573 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2574 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2575 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2576 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2577 // Compute the high part as N1.
2578 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2579 DAG.getConstant(SimpleSize, DL,
2580 getShiftAmountTy(Lo.getValueType())));
2581 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2582 // Compute the low part as N0.
2583 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2584 return CombineTo(N, Lo, Hi);
2591 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2592 // (smulo x, 2) -> (saddo x, x)
2593 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2594 if (C2->getAPIntValue() == 2)
2595 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
2596 N->getOperand(0), N->getOperand(0));
2601 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2602 // (umulo x, 2) -> (uaddo x, x)
2603 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2604 if (C2->getAPIntValue() == 2)
2605 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
2606 N->getOperand(0), N->getOperand(0));
2611 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2612 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM))
2618 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2619 if (SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM))
2625 /// If this is a binary operator with two operands of the same opcode, try to
2627 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2628 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2629 EVT VT = N0.getValueType();
2630 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2632 // Bail early if none of these transforms apply.
2633 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2635 // For each of OP in AND/OR/XOR:
2636 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2637 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2638 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2639 // fold (OP (bswap x), (bswap y)) -> (bswap (OP x, y))
2640 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2642 // do not sink logical op inside of a vector extend, since it may combine
2644 EVT Op0VT = N0.getOperand(0).getValueType();
2645 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2646 N0.getOpcode() == ISD::SIGN_EXTEND ||
2647 N0.getOpcode() == ISD::BSWAP ||
2648 // Avoid infinite looping with PromoteIntBinOp.
2649 (N0.getOpcode() == ISD::ANY_EXTEND &&
2650 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2651 (N0.getOpcode() == ISD::TRUNCATE &&
2652 (!TLI.isZExtFree(VT, Op0VT) ||
2653 !TLI.isTruncateFree(Op0VT, VT)) &&
2654 TLI.isTypeLegal(Op0VT))) &&
2656 Op0VT == N1.getOperand(0).getValueType() &&
2657 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2658 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2659 N0.getOperand(0).getValueType(),
2660 N0.getOperand(0), N1.getOperand(0));
2661 AddToWorklist(ORNode.getNode());
2662 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode);
2665 // For each of OP in SHL/SRL/SRA/AND...
2666 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2667 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2668 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2669 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2670 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2671 N0.getOperand(1) == N1.getOperand(1)) {
2672 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
2673 N0.getOperand(0).getValueType(),
2674 N0.getOperand(0), N1.getOperand(0));
2675 AddToWorklist(ORNode.getNode());
2676 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
2677 ORNode, N0.getOperand(1));
2680 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
2681 // Only perform this optimization after type legalization and before
2682 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
2683 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
2684 // we don't want to undo this promotion.
2685 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
2687 if ((N0.getOpcode() == ISD::BITCAST ||
2688 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
2689 Level == AfterLegalizeTypes) {
2690 SDValue In0 = N0.getOperand(0);
2691 SDValue In1 = N1.getOperand(0);
2692 EVT In0Ty = In0.getValueType();
2693 EVT In1Ty = In1.getValueType();
2695 // If both incoming values are integers, and the original types are the
2697 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
2698 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1);
2699 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op);
2700 AddToWorklist(Op.getNode());
2705 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value).
2706 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B))
2707 // If both shuffles use the same mask, and both shuffle within a single
2708 // vector, then it is worthwhile to move the swizzle after the operation.
2709 // The type-legalizer generates this pattern when loading illegal
2710 // vector types from memory. In many cases this allows additional shuffle
2712 // There are other cases where moving the shuffle after the xor/and/or
2713 // is profitable even if shuffles don't perform a swizzle.
2714 // If both shuffles use the same mask, and both shuffles have the same first
2715 // or second operand, then it might still be profitable to move the shuffle
2716 // after the xor/and/or operation.
2717 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) {
2718 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0);
2719 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1);
2721 assert(N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType() &&
2722 "Inputs to shuffles are not the same type");
2724 // Check that both shuffles use the same mask. The masks are known to be of
2725 // the same length because the result vector type is the same.
2726 // Check also that shuffles have only one use to avoid introducing extra
2728 if (SVN0->hasOneUse() && SVN1->hasOneUse() &&
2729 SVN0->getMask().equals(SVN1->getMask())) {
2730 SDValue ShOp = N0->getOperand(1);
2732 // Don't try to fold this node if it requires introducing a
2733 // build vector of all zeros that might be illegal at this stage.
2734 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2736 ShOp = DAG.getConstant(0, SDLoc(N), VT);
2741 // (AND (shuf (A, C), shuf (B, C)) -> shuf (AND (A, B), C)
2742 // (OR (shuf (A, C), shuf (B, C)) -> shuf (OR (A, B), C)
2743 // (XOR (shuf (A, C), shuf (B, C)) -> shuf (XOR (A, B), V_0)
2744 if (N0.getOperand(1) == N1.getOperand(1) && ShOp.getNode()) {
2745 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2746 N0->getOperand(0), N1->getOperand(0));
2747 AddToWorklist(NewNode.getNode());
2748 return DAG.getVectorShuffle(VT, SDLoc(N), NewNode, ShOp,
2749 &SVN0->getMask()[0]);
2752 // Don't try to fold this node if it requires introducing a
2753 // build vector of all zeros that might be illegal at this stage.
2754 ShOp = N0->getOperand(0);
2755 if (N->getOpcode() == ISD::XOR && ShOp.getOpcode() != ISD::UNDEF) {
2757 ShOp = DAG.getConstant(0, SDLoc(N), VT);
2762 // (AND (shuf (C, A), shuf (C, B)) -> shuf (C, AND (A, B))
2763 // (OR (shuf (C, A), shuf (C, B)) -> shuf (C, OR (A, B))
2764 // (XOR (shuf (C, A), shuf (C, B)) -> shuf (V_0, XOR (A, B))
2765 if (N0->getOperand(0) == N1->getOperand(0) && ShOp.getNode()) {
2766 SDValue NewNode = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
2767 N0->getOperand(1), N1->getOperand(1));
2768 AddToWorklist(NewNode.getNode());
2769 return DAG.getVectorShuffle(VT, SDLoc(N), ShOp, NewNode,
2770 &SVN0->getMask()[0]);
2778 /// This contains all DAGCombine rules which reduce two values combined by
2779 /// an And operation to a single value. This makes them reusable in the context
2780 /// of visitSELECT(). Rules involving constants are not included as
2781 /// visitSELECT() already handles those cases.
2782 SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1,
2783 SDNode *LocReference) {
2784 EVT VT = N1.getValueType();
2786 // fold (and x, undef) -> 0
2787 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2788 return DAG.getConstant(0, SDLoc(LocReference), VT);
2789 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2790 SDValue LL, LR, RL, RR, CC0, CC1;
2791 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2792 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2793 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2795 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2796 LL.getValueType().isInteger()) {
2797 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2798 if (isNullConstant(LR) && Op1 == ISD::SETEQ) {
2799 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2800 LR.getValueType(), LL, RL);
2801 AddToWorklist(ORNode.getNode());
2802 return DAG.getSetCC(SDLoc(LocReference), VT, ORNode, LR, Op1);
2804 if (isAllOnesConstant(LR)) {
2805 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2806 if (Op1 == ISD::SETEQ) {
2807 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0),
2808 LR.getValueType(), LL, RL);
2809 AddToWorklist(ANDNode.getNode());
2810 return DAG.getSetCC(SDLoc(LocReference), VT, ANDNode, LR, Op1);
2812 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2813 if (Op1 == ISD::SETGT) {
2814 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0),
2815 LR.getValueType(), LL, RL);
2816 AddToWorklist(ORNode.getNode());
2817 return DAG.getSetCC(SDLoc(LocReference), VT, ORNode, LR, Op1);
2821 // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
2822 if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
2823 Op0 == Op1 && LL.getValueType().isInteger() &&
2824 Op0 == ISD::SETNE && ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
2825 (isAllOnesConstant(LR) && isNullConstant(RR)))) {
2827 SDValue ADDNode = DAG.getNode(ISD::ADD, DL, LL.getValueType(),
2828 LL, DAG.getConstant(1, DL,
2829 LL.getValueType()));
2830 AddToWorklist(ADDNode.getNode());
2831 return DAG.getSetCC(SDLoc(LocReference), VT, ADDNode,
2832 DAG.getConstant(2, DL, LL.getValueType()),
2835 // canonicalize equivalent to ll == rl
2836 if (LL == RR && LR == RL) {
2837 Op1 = ISD::getSetCCSwappedOperands(Op1);
2840 if (LL == RL && LR == RR) {
2841 bool isInteger = LL.getValueType().isInteger();
2842 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2843 if (Result != ISD::SETCC_INVALID &&
2844 (!LegalOperations ||
2845 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
2846 TLI.isOperationLegal(ISD::SETCC,
2847 getSetCCResultType(N0.getSimpleValueType())))))
2848 return DAG.getSetCC(SDLoc(LocReference), N0.getValueType(),
2853 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
2854 VT.getSizeInBits() <= 64) {
2855 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2856 APInt ADDC = ADDI->getAPIntValue();
2857 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2858 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
2859 // immediate for an add, but it is legal if its top c2 bits are set,
2860 // transform the ADD so the immediate doesn't need to be materialized
2862 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
2863 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
2864 SRLI->getZExtValue());
2865 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
2867 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
2870 DAG.getNode(ISD::ADD, DL, VT,
2871 N0.getOperand(0), DAG.getConstant(ADDC, DL, VT));
2872 CombineTo(N0.getNode(), NewAdd);
2873 // Return N so it doesn't get rechecked!
2874 return SDValue(LocReference, 0);
2885 SDValue DAGCombiner::visitAND(SDNode *N) {
2886 SDValue N0 = N->getOperand(0);
2887 SDValue N1 = N->getOperand(1);
2888 EVT VT = N1.getValueType();
2891 if (VT.isVector()) {
2892 if (SDValue FoldedVOp = SimplifyVBinOp(N))
2895 // fold (and x, 0) -> 0, vector edition
2896 if (ISD::isBuildVectorAllZeros(N0.getNode()))
2897 // do not return N0, because undef node may exist in N0
2898 return DAG.getConstant(
2899 APInt::getNullValue(
2900 N0.getValueType().getScalarType().getSizeInBits()),
2901 SDLoc(N), N0.getValueType());
2902 if (ISD::isBuildVectorAllZeros(N1.getNode()))
2903 // do not return N1, because undef node may exist in N1
2904 return DAG.getConstant(
2905 APInt::getNullValue(
2906 N1.getValueType().getScalarType().getSizeInBits()),
2907 SDLoc(N), N1.getValueType());
2909 // fold (and x, -1) -> x, vector edition
2910 if (ISD::isBuildVectorAllOnes(N0.getNode()))
2912 if (ISD::isBuildVectorAllOnes(N1.getNode()))
2916 // fold (and c1, c2) -> c1&c2
2917 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
2918 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2919 if (N0C && N1C && !N1C->isOpaque())
2920 return DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, N0C, N1C);
2921 // canonicalize constant to RHS
2922 if (isConstantIntBuildVectorOrConstantInt(N0) &&
2923 !isConstantIntBuildVectorOrConstantInt(N1))
2924 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0);
2925 // fold (and x, -1) -> x
2926 if (isAllOnesConstant(N1))
2928 // if (and x, c) is known to be zero, return 0
2929 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2930 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2931 APInt::getAllOnesValue(BitWidth)))
2932 return DAG.getConstant(0, SDLoc(N), VT);
2934 if (SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1))
2936 // fold (and (or x, C), D) -> D if (C & D) == D
2937 if (N1C && N0.getOpcode() == ISD::OR)
2938 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2939 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2941 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2942 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2943 SDValue N0Op0 = N0.getOperand(0);
2944 APInt Mask = ~N1C->getAPIntValue();
2945 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2946 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2947 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
2948 N0.getValueType(), N0Op0);
2950 // Replace uses of the AND with uses of the Zero extend node.
2953 // We actually want to replace all uses of the any_extend with the
2954 // zero_extend, to avoid duplicating things. This will later cause this
2955 // AND to be folded.
2956 CombineTo(N0.getNode(), Zext);
2957 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2960 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) ->
2961 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must
2962 // already be zero by virtue of the width of the base type of the load.
2964 // the 'X' node here can either be nothing or an extract_vector_elt to catch
2966 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
2967 N0.getOperand(0).getOpcode() == ISD::LOAD) ||
2968 N0.getOpcode() == ISD::LOAD) {
2969 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ?
2970 N0 : N0.getOperand(0) );
2972 // Get the constant (if applicable) the zero'th operand is being ANDed with.
2973 // This can be a pure constant or a vector splat, in which case we treat the
2974 // vector as a scalar and use the splat value.
2975 APInt Constant = APInt::getNullValue(1);
2976 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
2977 Constant = C->getAPIntValue();
2978 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
2979 APInt SplatValue, SplatUndef;
2980 unsigned SplatBitSize;
2982 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef,
2983 SplatBitSize, HasAnyUndefs);
2985 // Undef bits can contribute to a possible optimisation if set, so
2987 SplatValue |= SplatUndef;
2989 // The splat value may be something like "0x00FFFFFF", which means 0 for
2990 // the first vector value and FF for the rest, repeating. We need a mask
2991 // that will apply equally to all members of the vector, so AND all the
2992 // lanes of the constant together.
2993 EVT VT = Vector->getValueType(0);
2994 unsigned BitWidth = VT.getVectorElementType().getSizeInBits();
2996 // If the splat value has been compressed to a bitlength lower
2997 // than the size of the vector lane, we need to re-expand it to
2999 if (BitWidth > SplatBitSize)
3000 for (SplatValue = SplatValue.zextOrTrunc(BitWidth);
3001 SplatBitSize < BitWidth;
3002 SplatBitSize = SplatBitSize * 2)
3003 SplatValue |= SplatValue.shl(SplatBitSize);
3005 // Make sure that variable 'Constant' is only set if 'SplatBitSize' is a
3006 // multiple of 'BitWidth'. Otherwise, we could propagate a wrong value.
3007 if (SplatBitSize % BitWidth == 0) {
3008 Constant = APInt::getAllOnesValue(BitWidth);
3009 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i)
3010 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth);
3015 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is
3016 // actually legal and isn't going to get expanded, else this is a false
3018 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
3019 Load->getValueType(0),
3020 Load->getMemoryVT());
3022 // Resize the constant to the same size as the original memory access before
3023 // extension. If it is still the AllOnesValue then this AND is completely
3026 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits());
3029 switch (Load->getExtensionType()) {
3030 default: B = false; break;
3031 case ISD::EXTLOAD: B = CanZextLoadProfitably; break;
3033 case ISD::NON_EXTLOAD: B = true; break;
3036 if (B && Constant.isAllOnesValue()) {
3037 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to
3038 // preserve semantics once we get rid of the AND.
3039 SDValue NewLoad(Load, 0);
3040 if (Load->getExtensionType() == ISD::EXTLOAD) {
3041 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
3042 Load->getValueType(0), SDLoc(Load),
3043 Load->getChain(), Load->getBasePtr(),
3044 Load->getOffset(), Load->getMemoryVT(),
3045 Load->getMemOperand());
3046 // Replace uses of the EXTLOAD with the new ZEXTLOAD.
3047 if (Load->getNumValues() == 3) {
3048 // PRE/POST_INC loads have 3 values.
3049 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1),
3050 NewLoad.getValue(2) };
3051 CombineTo(Load, To, 3, true);
3053 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1));
3057 // Fold the AND away, taking care not to fold to the old load node if we
3059 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
3061 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3065 // fold (and (load x), 255) -> (zextload x, i8)
3066 // fold (and (extload x, i16), 255) -> (zextload x, i8)
3067 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
3068 if (N1C && (N0.getOpcode() == ISD::LOAD ||
3069 (N0.getOpcode() == ISD::ANY_EXTEND &&
3070 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
3071 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
3072 LoadSDNode *LN0 = HasAnyExt
3073 ? cast<LoadSDNode>(N0.getOperand(0))
3074 : cast<LoadSDNode>(N0);
3075 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
3076 LN0->isUnindexed() && N0.hasOneUse() && SDValue(LN0, 0).hasOneUse()) {
3077 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
3078 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
3079 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
3080 EVT LoadedVT = LN0->getMemoryVT();
3081 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
3083 if (ExtVT == LoadedVT &&
3084 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy,
3088 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
3089 LN0->getChain(), LN0->getBasePtr(), ExtVT,
3090 LN0->getMemOperand());
3092 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
3093 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3096 // Do not change the width of a volatile load.
3097 // Do not generate loads of non-round integer types since these can
3098 // be expensive (and would be wrong if the type is not byte sized).
3099 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
3100 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy,
3102 EVT PtrType = LN0->getOperand(1).getValueType();
3104 unsigned Alignment = LN0->getAlignment();
3105 SDValue NewPtr = LN0->getBasePtr();
3107 // For big endian targets, we need to add an offset to the pointer
3108 // to load the correct bytes. For little endian systems, we merely
3109 // need to read fewer bytes from the same pointer.
3110 if (DAG.getDataLayout().isBigEndian()) {
3111 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
3112 unsigned EVTStoreBytes = ExtVT.getStoreSize();
3113 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
3115 NewPtr = DAG.getNode(ISD::ADD, DL, PtrType,
3116 NewPtr, DAG.getConstant(PtrOff, DL, PtrType));
3117 Alignment = MinAlign(Alignment, PtrOff);
3120 AddToWorklist(NewPtr.getNode());
3123 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy,
3124 LN0->getChain(), NewPtr,
3125 LN0->getPointerInfo(),
3126 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
3127 LN0->isInvariant(), Alignment, LN0->getAAInfo());
3129 CombineTo(LN0, Load, Load.getValue(1));
3130 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3136 if (SDValue Combined = visitANDLike(N0, N1, N))
3139 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
3140 if (N0.getOpcode() == N1.getOpcode())
3141 if (SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N))
3144 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
3145 // fold (and (sra)) -> (and (srl)) when possible.
3146 if (!VT.isVector() &&
3147 SimplifyDemandedBits(SDValue(N, 0)))
3148 return SDValue(N, 0);
3150 // fold (zext_inreg (extload x)) -> (zextload x)
3151 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
3152 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3153 EVT MemVT = LN0->getMemoryVT();
3154 // If we zero all the possible extended bits, then we can turn this into
3155 // a zextload if we are running before legalize or the operation is legal.
3156 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
3157 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
3158 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
3159 ((!LegalOperations && !LN0->isVolatile()) ||
3160 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
3161 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
3162 LN0->getChain(), LN0->getBasePtr(),
3163 MemVT, LN0->getMemOperand());
3165 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3166 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3169 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
3170 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
3172 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
3173 EVT MemVT = LN0->getMemoryVT();
3174 // If we zero all the possible extended bits, then we can turn this into
3175 // a zextload if we are running before legalize or the operation is legal.
3176 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
3177 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
3178 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
3179 ((!LegalOperations && !LN0->isVolatile()) ||
3180 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
3181 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT,
3182 LN0->getChain(), LN0->getBasePtr(),
3183 MemVT, LN0->getMemOperand());
3185 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
3186 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3189 // fold (and (or (srl N, 8), (shl N, 8)), 0xffff) -> (srl (bswap N), const)
3190 if (N1C && N1C->getAPIntValue() == 0xffff && N0.getOpcode() == ISD::OR) {
3191 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
3192 N0.getOperand(1), false);
3193 if (BSwap.getNode())
3200 /// Match (a >> 8) | (a << 8) as (bswap a) >> 16.
3201 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
3202 bool DemandHighBits) {
3203 if (!LegalOperations)
3206 EVT VT = N->getValueType(0);
3207 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
3209 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3212 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
3213 bool LookPassAnd0 = false;
3214 bool LookPassAnd1 = false;
3215 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
3217 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
3219 if (N0.getOpcode() == ISD::AND) {
3220 if (!N0.getNode()->hasOneUse())
3222 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3223 if (!N01C || N01C->getZExtValue() != 0xFF00)
3225 N0 = N0.getOperand(0);
3226 LookPassAnd0 = true;
3229 if (N1.getOpcode() == ISD::AND) {
3230 if (!N1.getNode()->hasOneUse())
3232 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3233 if (!N11C || N11C->getZExtValue() != 0xFF)
3235 N1 = N1.getOperand(0);
3236 LookPassAnd1 = true;
3239 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
3241 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
3243 if (!N0.getNode()->hasOneUse() ||
3244 !N1.getNode()->hasOneUse())
3247 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3248 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
3251 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
3254 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
3255 SDValue N00 = N0->getOperand(0);
3256 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
3257 if (!N00.getNode()->hasOneUse())
3259 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
3260 if (!N001C || N001C->getZExtValue() != 0xFF)
3262 N00 = N00.getOperand(0);
3263 LookPassAnd0 = true;
3266 SDValue N10 = N1->getOperand(0);
3267 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
3268 if (!N10.getNode()->hasOneUse())
3270 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
3271 if (!N101C || N101C->getZExtValue() != 0xFF00)
3273 N10 = N10.getOperand(0);
3274 LookPassAnd1 = true;
3280 // Make sure everything beyond the low halfword gets set to zero since the SRL
3281 // 16 will clear the top bits.
3282 unsigned OpSizeInBits = VT.getSizeInBits();
3283 if (DemandHighBits && OpSizeInBits > 16) {
3284 // If the left-shift isn't masked out then the only way this is a bswap is
3285 // if all bits beyond the low 8 are 0. In that case the entire pattern
3286 // reduces to a left shift anyway: leave it for other parts of the combiner.
3290 // However, if the right shift isn't masked out then it might be because
3291 // it's not needed. See if we can spot that too.
3292 if (!LookPassAnd1 &&
3293 !DAG.MaskedValueIsZero(
3294 N10, APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - 16)))
3298 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00);
3299 if (OpSizeInBits > 16) {
3301 Res = DAG.getNode(ISD::SRL, DL, VT, Res,
3302 DAG.getConstant(OpSizeInBits - 16, DL,
3303 getShiftAmountTy(VT)));
3308 /// Return true if the specified node is an element that makes up a 32-bit
3309 /// packed halfword byteswap.
3310 /// ((x & 0x000000ff) << 8) |
3311 /// ((x & 0x0000ff00) >> 8) |
3312 /// ((x & 0x00ff0000) << 8) |
3313 /// ((x & 0xff000000) >> 8)
3314 static bool isBSwapHWordElement(SDValue N, MutableArrayRef<SDNode *> Parts) {
3315 if (!N.getNode()->hasOneUse())
3318 unsigned Opc = N.getOpcode();
3319 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
3322 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3327 switch (N1C->getZExtValue()) {
3330 case 0xFF: Num = 0; break;
3331 case 0xFF00: Num = 1; break;
3332 case 0xFF0000: Num = 2; break;
3333 case 0xFF000000: Num = 3; break;
3336 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
3337 SDValue N0 = N.getOperand(0);
3338 if (Opc == ISD::AND) {
3339 if (Num == 0 || Num == 2) {
3341 // (x >> 8) & 0xff0000
3342 if (N0.getOpcode() != ISD::SRL)
3344 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3345 if (!C || C->getZExtValue() != 8)
3348 // (x << 8) & 0xff00
3349 // (x << 8) & 0xff000000
3350 if (N0.getOpcode() != ISD::SHL)
3352 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3353 if (!C || C->getZExtValue() != 8)
3356 } else if (Opc == ISD::SHL) {
3358 // (x & 0xff0000) << 8
3359 if (Num != 0 && Num != 2)
3361 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3362 if (!C || C->getZExtValue() != 8)
3364 } else { // Opc == ISD::SRL
3365 // (x & 0xff00) >> 8
3366 // (x & 0xff000000) >> 8
3367 if (Num != 1 && Num != 3)
3369 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
3370 if (!C || C->getZExtValue() != 8)
3377 Parts[Num] = N0.getOperand(0).getNode();
3381 /// Match a 32-bit packed halfword bswap. That is
3382 /// ((x & 0x000000ff) << 8) |
3383 /// ((x & 0x0000ff00) >> 8) |
3384 /// ((x & 0x00ff0000) << 8) |
3385 /// ((x & 0xff000000) >> 8)
3386 /// => (rotl (bswap x), 16)
3387 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
3388 if (!LegalOperations)
3391 EVT VT = N->getValueType(0);
3394 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
3398 // (or (or (and), (and)), (or (and), (and)))
3399 // (or (or (or (and), (and)), (and)), (and))
3400 if (N0.getOpcode() != ISD::OR)
3402 SDValue N00 = N0.getOperand(0);
3403 SDValue N01 = N0.getOperand(1);
3404 SDNode *Parts[4] = {};
3406 if (N1.getOpcode() == ISD::OR &&
3407 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) {
3408 // (or (or (and), (and)), (or (and), (and)))
3409 SDValue N000 = N00.getOperand(0);
3410 if (!isBSwapHWordElement(N000, Parts))
3413 SDValue N001 = N00.getOperand(1);
3414 if (!isBSwapHWordElement(N001, Parts))
3416 SDValue N010 = N01.getOperand(0);
3417 if (!isBSwapHWordElement(N010, Parts))
3419 SDValue N011 = N01.getOperand(1);
3420 if (!isBSwapHWordElement(N011, Parts))
3423 // (or (or (or (and), (and)), (and)), (and))
3424 if (!isBSwapHWordElement(N1, Parts))
3426 if (!isBSwapHWordElement(N01, Parts))
3428 if (N00.getOpcode() != ISD::OR)
3430 SDValue N000 = N00.getOperand(0);
3431 if (!isBSwapHWordElement(N000, Parts))
3433 SDValue N001 = N00.getOperand(1);
3434 if (!isBSwapHWordElement(N001, Parts))
3438 // Make sure the parts are all coming from the same node.
3439 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
3443 SDValue BSwap = DAG.getNode(ISD::BSWAP, DL, VT,
3444 SDValue(Parts[0], 0));
3446 // Result of the bswap should be rotated by 16. If it's not legal, then
3447 // do (x << 16) | (x >> 16).
3448 SDValue ShAmt = DAG.getConstant(16, DL, getShiftAmountTy(VT));
3449 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
3450 return DAG.getNode(ISD::ROTL, DL, VT, BSwap, ShAmt);
3451 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
3452 return DAG.getNode(ISD::ROTR, DL, VT, BSwap, ShAmt);
3453 return DAG.getNode(ISD::OR, DL, VT,
3454 DAG.getNode(ISD::SHL, DL, VT, BSwap, ShAmt),
3455 DAG.getNode(ISD::SRL, DL, VT, BSwap, ShAmt));
3458 /// This contains all DAGCombine rules which reduce two values combined by
3459 /// an Or operation to a single value \see visitANDLike().
3460 SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, SDNode *LocReference) {
3461 EVT VT = N1.getValueType();
3462 // fold (or x, undef) -> -1
3463 if (!LegalOperations &&
3464 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
3465 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
3466 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()),
3467 SDLoc(LocReference), VT);
3469 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
3470 SDValue LL, LR, RL, RR, CC0, CC1;
3471 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
3472 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
3473 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
3475 if (LR == RR && Op0 == Op1 && LL.getValueType().isInteger()) {
3476 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
3477 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
3478 if (isNullConstant(LR) && (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
3479 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR),
3480 LR.getValueType(), LL, RL);
3481 AddToWorklist(ORNode.getNode());
3482 return DAG.getSetCC(SDLoc(LocReference), VT, ORNode, LR, Op1);
3484 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
3485 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
3486 if (isAllOnesConstant(LR) && (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
3487 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR),
3488 LR.getValueType(), LL, RL);
3489 AddToWorklist(ANDNode.getNode());
3490 return DAG.getSetCC(SDLoc(LocReference), VT, ANDNode, LR, Op1);
3493 // canonicalize equivalent to ll == rl
3494 if (LL == RR && LR == RL) {
3495 Op1 = ISD::getSetCCSwappedOperands(Op1);
3498 if (LL == RL && LR == RR) {
3499 bool isInteger = LL.getValueType().isInteger();
3500 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
3501 if (Result != ISD::SETCC_INVALID &&
3502 (!LegalOperations ||
3503 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) &&
3504 TLI.isOperationLegal(ISD::SETCC,
3505 getSetCCResultType(N0.getValueType())))))
3506 return DAG.getSetCC(SDLoc(LocReference), N0.getValueType(),
3511 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
3512 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == ISD::AND &&
3513 // Don't increase # computations.
3514 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3515 // We can only do this xform if we know that bits from X that are set in C2
3516 // but not in C1 are already zero. Likewise for Y.
3517 if (const ConstantSDNode *N0O1C =
3518 getAsNonOpaqueConstant(N0.getOperand(1))) {
3519 if (const ConstantSDNode *N1O1C =
3520 getAsNonOpaqueConstant(N1.getOperand(1))) {
3521 // We can only do this xform if we know that bits from X that are set in
3522 // C2 but not in C1 are already zero. Likewise for Y.
3523 const APInt &LHSMask = N0O1C->getAPIntValue();
3524 const APInt &RHSMask = N1O1C->getAPIntValue();
3526 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
3527 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
3528 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3529 N0.getOperand(0), N1.getOperand(0));
3530 SDLoc DL(LocReference);
3531 return DAG.getNode(ISD::AND, DL, VT, X,
3532 DAG.getConstant(LHSMask | RHSMask, DL, VT));
3538 // (or (and X, M), (and X, N)) -> (and X, (or M, N))
3539 if (N0.getOpcode() == ISD::AND &&
3540 N1.getOpcode() == ISD::AND &&
3541 N0.getOperand(0) == N1.getOperand(0) &&
3542 // Don't increase # computations.
3543 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
3544 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT,
3545 N0.getOperand(1), N1.getOperand(1));
3546 return DAG.getNode(ISD::AND, SDLoc(LocReference), VT, N0.getOperand(0), X);
3552 SDValue DAGCombiner::visitOR(SDNode *N) {
3553 SDValue N0 = N->getOperand(0);
3554 SDValue N1 = N->getOperand(1);
3555 EVT VT = N1.getValueType();
3558 if (VT.isVector()) {
3559 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3562 // fold (or x, 0) -> x, vector edition
3563 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3565 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3568 // fold (or x, -1) -> -1, vector edition
3569 if (ISD::isBuildVectorAllOnes(N0.getNode()))
3570 // do not return N0, because undef node may exist in N0
3571 return DAG.getConstant(
3572 APInt::getAllOnesValue(
3573 N0.getValueType().getScalarType().getSizeInBits()),
3574 SDLoc(N), N0.getValueType());
3575 if (ISD::isBuildVectorAllOnes(N1.getNode()))
3576 // do not return N1, because undef node may exist in N1
3577 return DAG.getConstant(
3578 APInt::getAllOnesValue(
3579 N1.getValueType().getScalarType().getSizeInBits()),
3580 SDLoc(N), N1.getValueType());
3582 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf A, B, Mask1)
3583 // fold (or (shuf A, V_0, MA), (shuf B, V_0, MB)) -> (shuf B, A, Mask2)
3584 // Do this only if the resulting shuffle is legal.
3585 if (isa<ShuffleVectorSDNode>(N0) &&
3586 isa<ShuffleVectorSDNode>(N1) &&
3587 // Avoid folding a node with illegal type.
3588 TLI.isTypeLegal(VT) &&
3589 N0->getOperand(1) == N1->getOperand(1) &&
3590 ISD::isBuildVectorAllZeros(N0.getOperand(1).getNode())) {
3591 bool CanFold = true;
3592 unsigned NumElts = VT.getVectorNumElements();
3593 const ShuffleVectorSDNode *SV0 = cast<ShuffleVectorSDNode>(N0);
3594 const ShuffleVectorSDNode *SV1 = cast<ShuffleVectorSDNode>(N1);
3595 // We construct two shuffle masks:
3596 // - Mask1 is a shuffle mask for a shuffle with N0 as the first operand
3597 // and N1 as the second operand.
3598 // - Mask2 is a shuffle mask for a shuffle with N1 as the first operand
3599 // and N0 as the second operand.
3600 // We do this because OR is commutable and therefore there might be
3601 // two ways to fold this node into a shuffle.
3602 SmallVector<int,4> Mask1;
3603 SmallVector<int,4> Mask2;
3605 for (unsigned i = 0; i != NumElts && CanFold; ++i) {
3606 int M0 = SV0->getMaskElt(i);
3607 int M1 = SV1->getMaskElt(i);
3609 // Both shuffle indexes are undef. Propagate Undef.
3610 if (M0 < 0 && M1 < 0) {
3611 Mask1.push_back(M0);
3612 Mask2.push_back(M0);
3616 if (M0 < 0 || M1 < 0 ||
3617 (M0 < (int)NumElts && M1 < (int)NumElts) ||
3618 (M0 >= (int)NumElts && M1 >= (int)NumElts)) {
3623 Mask1.push_back(M0 < (int)NumElts ? M0 : M1 + NumElts);
3624 Mask2.push_back(M1 < (int)NumElts ? M1 : M0 + NumElts);
3628 // Fold this sequence only if the resulting shuffle is 'legal'.
3629 if (TLI.isShuffleMaskLegal(Mask1, VT))
3630 return DAG.getVectorShuffle(VT, SDLoc(N), N0->getOperand(0),
3631 N1->getOperand(0), &Mask1[0]);
3632 if (TLI.isShuffleMaskLegal(Mask2, VT))
3633 return DAG.getVectorShuffle(VT, SDLoc(N), N1->getOperand(0),
3634 N0->getOperand(0), &Mask2[0]);
3639 // fold (or c1, c2) -> c1|c2
3640 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
3641 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3642 if (N0C && N1C && !N1C->isOpaque())
3643 return DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N), VT, N0C, N1C);
3644 // canonicalize constant to RHS
3645 if (isConstantIntBuildVectorOrConstantInt(N0) &&
3646 !isConstantIntBuildVectorOrConstantInt(N1))
3647 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0);
3648 // fold (or x, 0) -> x
3649 if (isNullConstant(N1))
3651 // fold (or x, -1) -> -1
3652 if (isAllOnesConstant(N1))
3654 // fold (or x, c) -> c iff (x & ~c) == 0
3655 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
3658 if (SDValue Combined = visitORLike(N0, N1, N))
3661 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
3662 if (SDValue BSwap = MatchBSwapHWord(N, N0, N1))
3664 if (SDValue BSwap = MatchBSwapHWordLow(N, N0, N1))
3668 if (SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1))
3670 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
3671 // iff (c1 & c2) == 0.
3672 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
3673 isa<ConstantSDNode>(N0.getOperand(1))) {
3674 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
3675 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) {
3676 if (SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N1), VT,
3679 ISD::AND, SDLoc(N), VT,
3680 DAG.getNode(ISD::OR, SDLoc(N0), VT, N0.getOperand(0), N1), COR);
3684 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
3685 if (N0.getOpcode() == N1.getOpcode())
3686 if (SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N))
3689 // See if this is some rotate idiom.
3690 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N)))
3691 return SDValue(Rot, 0);
3693 // Simplify the operands using demanded-bits information.
3694 if (!VT.isVector() &&
3695 SimplifyDemandedBits(SDValue(N, 0)))
3696 return SDValue(N, 0);
3701 /// Match "(X shl/srl V1) & V2" where V2 may not be present.
3702 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
3703 if (Op.getOpcode() == ISD::AND) {
3704 if (isa<ConstantSDNode>(Op.getOperand(1))) {
3705 Mask = Op.getOperand(1);
3706 Op = Op.getOperand(0);
3712 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
3720 // Return true if we can prove that, whenever Neg and Pos are both in the
3721 // range [0, OpSize), Neg == (Pos == 0 ? 0 : OpSize - Pos). This means that
3722 // for two opposing shifts shift1 and shift2 and a value X with OpBits bits:
3724 // (or (shift1 X, Neg), (shift2 X, Pos))
3726 // reduces to a rotate in direction shift2 by Pos or (equivalently) a rotate
3727 // in direction shift1 by Neg. The range [0, OpSize) means that we only need
3728 // to consider shift amounts with defined behavior.
3729 static bool matchRotateSub(SDValue Pos, SDValue Neg, unsigned OpSize) {
3730 // If OpSize is a power of 2 then:
3732 // (a) (Pos == 0 ? 0 : OpSize - Pos) == (OpSize - Pos) & (OpSize - 1)
3733 // (b) Neg == Neg & (OpSize - 1) whenever Neg is in [0, OpSize).
3735 // So if OpSize is a power of 2 and Neg is (and Neg', OpSize-1), we check
3736 // for the stronger condition:
3738 // Neg & (OpSize - 1) == (OpSize - Pos) & (OpSize - 1) [A]
3740 // for all Neg and Pos. Since Neg & (OpSize - 1) == Neg' & (OpSize - 1)
3741 // we can just replace Neg with Neg' for the rest of the function.
3743 // In other cases we check for the even stronger condition:
3745 // Neg == OpSize - Pos [B]
3747 // for all Neg and Pos. Note that the (or ...) then invokes undefined
3748 // behavior if Pos == 0 (and consequently Neg == OpSize).
3750 // We could actually use [A] whenever OpSize is a power of 2, but the
3751 // only extra cases that it would match are those uninteresting ones
3752 // where Neg and Pos are never in range at the same time. E.g. for
3753 // OpSize == 32, using [A] would allow a Neg of the form (sub 64, Pos)
3754 // as well as (sub 32, Pos), but:
3756 // (or (shift1 X, (sub 64, Pos)), (shift2 X, Pos))
3758 // always invokes undefined behavior for 32-bit X.
3760 // Below, Mask == OpSize - 1 when using [A] and is all-ones otherwise.
3761 unsigned MaskLoBits = 0;
3762 if (Neg.getOpcode() == ISD::AND &&
3763 isPowerOf2_64(OpSize) &&
3764 Neg.getOperand(1).getOpcode() == ISD::Constant &&
3765 cast<ConstantSDNode>(Neg.getOperand(1))->getAPIntValue() == OpSize - 1) {
3766 Neg = Neg.getOperand(0);
3767 MaskLoBits = Log2_64(OpSize);
3770 // Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
3771 if (Neg.getOpcode() != ISD::SUB)
3773 ConstantSDNode *NegC = dyn_cast<ConstantSDNode>(Neg.getOperand(0));
3776 SDValue NegOp1 = Neg.getOperand(1);
3778 // On the RHS of [A], if Pos is Pos' & (OpSize - 1), just replace Pos with
3779 // Pos'. The truncation is redundant for the purpose of the equality.
3781 Pos.getOpcode() == ISD::AND &&
3782 Pos.getOperand(1).getOpcode() == ISD::Constant &&
3783 cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() == OpSize - 1)
3784 Pos = Pos.getOperand(0);
3786 // The condition we need is now:
3788 // (NegC - NegOp1) & Mask == (OpSize - Pos) & Mask
3790 // If NegOp1 == Pos then we need:
3792 // OpSize & Mask == NegC & Mask
3794 // (because "x & Mask" is a truncation and distributes through subtraction).
3797 Width = NegC->getAPIntValue();
3798 // Check for cases where Pos has the form (add NegOp1, PosC) for some PosC.
3799 // Then the condition we want to prove becomes:
3801 // (NegC - NegOp1) & Mask == (OpSize - (NegOp1 + PosC)) & Mask
3803 // which, again because "x & Mask" is a truncation, becomes:
3805 // NegC & Mask == (OpSize - PosC) & Mask
3806 // OpSize & Mask == (NegC + PosC) & Mask
3807 else if (Pos.getOpcode() == ISD::ADD &&
3808 Pos.getOperand(0) == NegOp1 &&
3809 Pos.getOperand(1).getOpcode() == ISD::Constant)
3810 Width = (cast<ConstantSDNode>(Pos.getOperand(1))->getAPIntValue() +
3811 NegC->getAPIntValue());
3815 // Now we just need to check that OpSize & Mask == Width & Mask.
3817 // Opsize & Mask is 0 since Mask is Opsize - 1.
3818 return Width.getLoBits(MaskLoBits) == 0;
3819 return Width == OpSize;
3822 // A subroutine of MatchRotate used once we have found an OR of two opposite
3823 // shifts of Shifted. If Neg == <operand size> - Pos then the OR reduces
3824 // to both (PosOpcode Shifted, Pos) and (NegOpcode Shifted, Neg), with the
3825 // former being preferred if supported. InnerPos and InnerNeg are Pos and
3826 // Neg with outer conversions stripped away.
3827 SDNode *DAGCombiner::MatchRotatePosNeg(SDValue Shifted, SDValue Pos,
3828 SDValue Neg, SDValue InnerPos,
3829 SDValue InnerNeg, unsigned PosOpcode,
3830 unsigned NegOpcode, SDLoc DL) {
3831 // fold (or (shl x, (*ext y)),
3832 // (srl x, (*ext (sub 32, y)))) ->
3833 // (rotl x, y) or (rotr x, (sub 32, y))
3835 // fold (or (shl x, (*ext (sub 32, y))),
3836 // (srl x, (*ext y))) ->
3837 // (rotr x, y) or (rotl x, (sub 32, y))
3838 EVT VT = Shifted.getValueType();
3839 if (matchRotateSub(InnerPos, InnerNeg, VT.getSizeInBits())) {
3840 bool HasPos = TLI.isOperationLegalOrCustom(PosOpcode, VT);
3841 return DAG.getNode(HasPos ? PosOpcode : NegOpcode, DL, VT, Shifted,
3842 HasPos ? Pos : Neg).getNode();
3848 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
3849 // idioms for rotate, and if the target supports rotation instructions, generate
3851 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
3852 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
3853 EVT VT = LHS.getValueType();
3854 if (!TLI.isTypeLegal(VT)) return nullptr;
3856 // The target must have at least one rotate flavor.
3857 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
3858 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
3859 if (!HasROTL && !HasROTR) return nullptr;
3861 // Match "(X shl/srl V1) & V2" where V2 may not be present.
3862 SDValue LHSShift; // The shift.
3863 SDValue LHSMask; // AND value if any.
3864 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
3865 return nullptr; // Not part of a rotate.
3867 SDValue RHSShift; // The shift.
3868 SDValue RHSMask; // AND value if any.
3869 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
3870 return nullptr; // Not part of a rotate.
3872 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
3873 return nullptr; // Not shifting the same value.
3875 if (LHSShift.getOpcode() == RHSShift.getOpcode())
3876 return nullptr; // Shifts must disagree.
3878 // Canonicalize shl to left side in a shl/srl pair.
3879 if (RHSShift.getOpcode() == ISD::SHL) {
3880 std::swap(LHS, RHS);
3881 std::swap(LHSShift, RHSShift);
3882 std::swap(LHSMask , RHSMask );
3885 unsigned OpSizeInBits = VT.getSizeInBits();
3886 SDValue LHSShiftArg = LHSShift.getOperand(0);
3887 SDValue LHSShiftAmt = LHSShift.getOperand(1);
3888 SDValue RHSShiftArg = RHSShift.getOperand(0);
3889 SDValue RHSShiftAmt = RHSShift.getOperand(1);
3891 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
3892 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
3893 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
3894 RHSShiftAmt.getOpcode() == ISD::Constant) {
3895 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
3896 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
3897 if ((LShVal + RShVal) != OpSizeInBits)
3900 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3901 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt);
3903 // If there is an AND of either shifted operand, apply it to the result.
3904 if (LHSMask.getNode() || RHSMask.getNode()) {
3905 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
3907 if (LHSMask.getNode()) {
3908 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
3909 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
3911 if (RHSMask.getNode()) {
3912 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
3913 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
3916 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, DL, VT));
3919 return Rot.getNode();
3922 // If there is a mask here, and we have a variable shift, we can't be sure
3923 // that we're masking out the right stuff.
3924 if (LHSMask.getNode() || RHSMask.getNode())
3927 // If the shift amount is sign/zext/any-extended just peel it off.
3928 SDValue LExtOp0 = LHSShiftAmt;
3929 SDValue RExtOp0 = RHSShiftAmt;
3930 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3931 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3932 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3933 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3934 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND ||
3935 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND ||
3936 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND ||
3937 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3938 LExtOp0 = LHSShiftAmt.getOperand(0);
3939 RExtOp0 = RHSShiftAmt.getOperand(0);
3942 SDNode *TryL = MatchRotatePosNeg(LHSShiftArg, LHSShiftAmt, RHSShiftAmt,
3943 LExtOp0, RExtOp0, ISD::ROTL, ISD::ROTR, DL);
3947 SDNode *TryR = MatchRotatePosNeg(RHSShiftArg, RHSShiftAmt, LHSShiftAmt,
3948 RExtOp0, LExtOp0, ISD::ROTR, ISD::ROTL, DL);
3955 SDValue DAGCombiner::visitXOR(SDNode *N) {
3956 SDValue N0 = N->getOperand(0);
3957 SDValue N1 = N->getOperand(1);
3958 EVT VT = N0.getValueType();
3961 if (VT.isVector()) {
3962 if (SDValue FoldedVOp = SimplifyVBinOp(N))
3965 // fold (xor x, 0) -> x, vector edition
3966 if (ISD::isBuildVectorAllZeros(N0.getNode()))
3968 if (ISD::isBuildVectorAllZeros(N1.getNode()))
3972 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3973 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3974 return DAG.getConstant(0, SDLoc(N), VT);
3975 // fold (xor x, undef) -> undef
3976 if (N0.getOpcode() == ISD::UNDEF)
3978 if (N1.getOpcode() == ISD::UNDEF)
3980 // fold (xor c1, c2) -> c1^c2
3981 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
3982 ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
3984 return DAG.FoldConstantArithmetic(ISD::XOR, SDLoc(N), VT, N0C, N1C);
3985 // canonicalize constant to RHS
3986 if (isConstantIntBuildVectorOrConstantInt(N0) &&
3987 !isConstantIntBuildVectorOrConstantInt(N1))
3988 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0);
3989 // fold (xor x, 0) -> x
3990 if (isNullConstant(N1))
3993 if (SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1))
3996 // fold !(x cc y) -> (x !cc y)
3997 SDValue LHS, RHS, CC;
3998 if (TLI.isConstTrueVal(N1.getNode()) && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3999 bool isInt = LHS.getValueType().isInteger();
4000 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
4003 if (!LegalOperations ||
4004 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
4005 switch (N0.getOpcode()) {
4007 llvm_unreachable("Unhandled SetCC Equivalent!");
4009 return DAG.getSetCC(SDLoc(N), VT, LHS, RHS, NotCC);
4010 case ISD::SELECT_CC:
4011 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2),
4012 N0.getOperand(3), NotCC);
4017 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
4018 if (isOneConstant(N1) && N0.getOpcode() == ISD::ZERO_EXTEND &&
4019 N0.getNode()->hasOneUse() &&
4020 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
4021 SDValue V = N0.getOperand(0);
4023 V = DAG.getNode(ISD::XOR, DL, V.getValueType(), V,
4024 DAG.getConstant(1, DL, V.getValueType()));
4025 AddToWorklist(V.getNode());
4026 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V);
4029 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
4030 if (isOneConstant(N1) && VT == MVT::i1 &&
4031 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
4032 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
4033 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
4034 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
4035 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
4036 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
4037 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
4038 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
4041 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
4042 if (isAllOnesConstant(N1) &&
4043 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
4044 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
4045 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
4046 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
4047 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
4048 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
4049 AddToWorklist(LHS.getNode()); AddToWorklist(RHS.getNode());
4050 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
4053 // fold (xor (and x, y), y) -> (and (not x), y)
4054 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
4055 N0->getOperand(1) == N1) {
4056 SDValue X = N0->getOperand(0);
4057 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT);
4058 AddToWorklist(NotX.getNode());
4059 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1);
4061 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
4062 if (N1C && N0.getOpcode() == ISD::XOR) {
4063 if (const ConstantSDNode *N00C = getAsNonOpaqueConstant(N0.getOperand(0))) {
4065 return DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1),
4066 DAG.getConstant(N1C->getAPIntValue() ^
4067 N00C->getAPIntValue(), DL, VT));
4069 if (const ConstantSDNode *N01C = getAsNonOpaqueConstant(N0.getOperand(1))) {
4071 return DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
4072 DAG.getConstant(N1C->getAPIntValue() ^
4073 N01C->getAPIntValue(), DL, VT));
4076 // fold (xor x, x) -> 0
4078 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations, LegalTypes);
4080 // fold (xor (shl 1, x), -1) -> (rotl ~1, x)
4081 // Here is a concrete example of this equivalence:
4083 // i16 shl == 1 << 14 == 16384 == 0b0100000000000000
4084 // i16 xor == ~(1 << 14) == 49151 == 0b1011111111111111
4088 // i16 ~1 == 0b1111111111111110
4089 // i16 rol(~1, 14) == 0b1011111111111111
4091 // Some additional tips to help conceptualize this transform:
4092 // - Try to see the operation as placing a single zero in a value of all ones.
4093 // - There exists no value for x which would allow the result to contain zero.
4094 // - Values of x larger than the bitwidth are undefined and do not require a
4095 // consistent result.
4096 // - Pushing the zero left requires shifting one bits in from the right.
4097 // A rotate left of ~1 is a nice way of achieving the desired result.
4098 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT) && N0.getOpcode() == ISD::SHL
4099 && isAllOnesConstant(N1) && isOneConstant(N0.getOperand(0))) {
4101 return DAG.getNode(ISD::ROTL, DL, VT, DAG.getConstant(~1, DL, VT),
4105 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
4106 if (N0.getOpcode() == N1.getOpcode())
4107 if (SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N))
4110 // Simplify the expression using non-local knowledge.
4111 if (!VT.isVector() &&
4112 SimplifyDemandedBits(SDValue(N, 0)))
4113 return SDValue(N, 0);
4118 /// Handle transforms common to the three shifts, when the shift amount is a
4120 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, ConstantSDNode *Amt) {
4121 SDNode *LHS = N->getOperand(0).getNode();
4122 if (!LHS->hasOneUse()) return SDValue();
4124 // We want to pull some binops through shifts, so that we have (and (shift))
4125 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
4126 // thing happens with address calculations, so it's important to canonicalize
4128 bool HighBitSet = false; // Can we transform this if the high bit is set?
4130 switch (LHS->getOpcode()) {
4131 default: return SDValue();
4134 HighBitSet = false; // We can only transform sra if the high bit is clear.
4137 HighBitSet = true; // We can only transform sra if the high bit is set.
4140 if (N->getOpcode() != ISD::SHL)
4141 return SDValue(); // only shl(add) not sr[al](add).
4142 HighBitSet = false; // We can only transform sra if the high bit is clear.
4146 // We require the RHS of the binop to be a constant and not opaque as well.
4147 ConstantSDNode *BinOpCst = getAsNonOpaqueConstant(LHS->getOperand(1));
4148 if (!BinOpCst) return SDValue();
4150 // FIXME: disable this unless the input to the binop is a shift by a constant.
4151 // If it is not a shift, it pessimizes some common cases like:
4153 // void foo(int *X, int i) { X[i & 1235] = 1; }
4154 // int bar(int *X, int i) { return X[i & 255]; }
4155 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
4156 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
4157 BinOpLHSVal->getOpcode() != ISD::SRA &&
4158 BinOpLHSVal->getOpcode() != ISD::SRL) ||
4159 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
4162 EVT VT = N->getValueType(0);
4164 // If this is a signed shift right, and the high bit is modified by the
4165 // logical operation, do not perform the transformation. The highBitSet
4166 // boolean indicates the value of the high bit of the constant which would
4167 // cause it to be modified for this operation.
4168 if (N->getOpcode() == ISD::SRA) {
4169 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
4170 if (BinOpRHSSignSet != HighBitSet)
4174 if (!TLI.isDesirableToCommuteWithShift(LHS))
4177 // Fold the constants, shifting the binop RHS by the shift amount.
4178 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)),
4180 LHS->getOperand(1), N->getOperand(1));
4181 assert(isa<ConstantSDNode>(NewRHS) && "Folding was not successful!");
4183 // Create the new shift.
4184 SDValue NewShift = DAG.getNode(N->getOpcode(),
4185 SDLoc(LHS->getOperand(0)),
4186 VT, LHS->getOperand(0), N->getOperand(1));
4188 // Create the new binop.
4189 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS);
4192 SDValue DAGCombiner::distributeTruncateThroughAnd(SDNode *N) {
4193 assert(N->getOpcode() == ISD::TRUNCATE);
4194 assert(N->getOperand(0).getOpcode() == ISD::AND);
4196 // (truncate:TruncVT (and N00, N01C)) -> (and (truncate:TruncVT N00), TruncC)
4197 if (N->hasOneUse() && N->getOperand(0).hasOneUse()) {
4198 SDValue N01 = N->getOperand(0).getOperand(1);
4200 if (ConstantSDNode *N01C = isConstOrConstSplat(N01)) {
4201 if (!N01C->isOpaque()) {
4202 EVT TruncVT = N->getValueType(0);
4203 SDValue N00 = N->getOperand(0).getOperand(0);
4204 APInt TruncC = N01C->getAPIntValue();
4205 TruncC = TruncC.trunc(TruncVT.getScalarSizeInBits());
4208 return DAG.getNode(ISD::AND, DL, TruncVT,
4209 DAG.getNode(ISD::TRUNCATE, DL, TruncVT, N00),
4210 DAG.getConstant(TruncC, DL, TruncVT));
4218 SDValue DAGCombiner::visitRotate(SDNode *N) {
4219 // fold (rot* x, (trunc (and y, c))) -> (rot* x, (and (trunc y), (trunc c))).
4220 if (N->getOperand(1).getOpcode() == ISD::TRUNCATE &&
4221 N->getOperand(1).getOperand(0).getOpcode() == ISD::AND) {
4222 SDValue NewOp1 = distributeTruncateThroughAnd(N->getOperand(1).getNode());
4223 if (NewOp1.getNode())
4224 return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
4225 N->getOperand(0), NewOp1);
4230 SDValue DAGCombiner::visitSHL(SDNode *N) {
4231 SDValue N0 = N->getOperand(0);
4232 SDValue N1 = N->getOperand(1);
4233 EVT VT = N0.getValueType();
4234 unsigned OpSizeInBits = VT.getScalarSizeInBits();
4237 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4238 if (VT.isVector()) {
4239 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4242 BuildVectorSDNode *N1CV = dyn_cast<BuildVectorSDNode>(N1);
4243 // If setcc produces all-one true value then:
4244 // (shl (and (setcc) N01CV) N1CV) -> (and (setcc) N01CV<<N1CV)
4245 if (N1CV && N1CV->isConstant()) {
4246 if (N0.getOpcode() == ISD::AND) {
4247 SDValue N00 = N0->getOperand(0);
4248 SDValue N01 = N0->getOperand(1);
4249 BuildVectorSDNode *N01CV = dyn_cast<BuildVectorSDNode>(N01);
4251 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC &&
4252 TLI.getBooleanContents(N00.getOperand(0).getValueType()) ==
4253 TargetLowering::ZeroOrNegativeOneBooleanContent) {
4254 if (SDValue C = DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT,
4256 return DAG.getNode(ISD::AND, SDLoc(N), VT, N00, C);
4259 N1C = isConstOrConstSplat(N1);
4264 // fold (shl c1, c2) -> c1<<c2
4265 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4266 if (N0C && N1C && !N1C->isOpaque())
4267 return DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT, N0C, N1C);
4268 // fold (shl 0, x) -> 0
4269 if (isNullConstant(N0))
4271 // fold (shl x, c >= size(x)) -> undef
4272 if (N1C && N1C->getAPIntValue().uge(OpSizeInBits))
4273 return DAG.getUNDEF(VT);
4274 // fold (shl x, 0) -> x
4275 if (N1C && N1C->isNullValue())
4277 // fold (shl undef, x) -> 0
4278 if (N0.getOpcode() == ISD::UNDEF)
4279 return DAG.getConstant(0, SDLoc(N), VT);
4280 // if (shl x, c) is known to be zero, return 0
4281 if (DAG.MaskedValueIsZero(SDValue(N, 0),
4282 APInt::getAllOnesValue(OpSizeInBits)))
4283 return DAG.getConstant(0, SDLoc(N), VT);
4284 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
4285 if (N1.getOpcode() == ISD::TRUNCATE &&
4286 N1.getOperand(0).getOpcode() == ISD::AND) {
4287 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4288 if (NewOp1.getNode())
4289 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, NewOp1);
4292 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4293 return SDValue(N, 0);
4295 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
4296 if (N1C && N0.getOpcode() == ISD::SHL) {
4297 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4298 uint64_t c1 = N0C1->getZExtValue();
4299 uint64_t c2 = N1C->getZExtValue();
4301 if (c1 + c2 >= OpSizeInBits)
4302 return DAG.getConstant(0, DL, VT);
4303 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
4304 DAG.getConstant(c1 + c2, DL, N1.getValueType()));
4308 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
4309 // For this to be valid, the second form must not preserve any of the bits
4310 // that are shifted out by the inner shift in the first form. This means
4311 // the outer shift size must be >= the number of bits added by the ext.
4312 // As a corollary, we don't care what kind of ext it is.
4313 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
4314 N0.getOpcode() == ISD::ANY_EXTEND ||
4315 N0.getOpcode() == ISD::SIGN_EXTEND) &&
4316 N0.getOperand(0).getOpcode() == ISD::SHL) {
4317 SDValue N0Op0 = N0.getOperand(0);
4318 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4319 uint64_t c1 = N0Op0C1->getZExtValue();
4320 uint64_t c2 = N1C->getZExtValue();
4321 EVT InnerShiftVT = N0Op0.getValueType();
4322 uint64_t InnerShiftSize = InnerShiftVT.getScalarSizeInBits();
4323 if (c2 >= OpSizeInBits - InnerShiftSize) {
4325 if (c1 + c2 >= OpSizeInBits)
4326 return DAG.getConstant(0, DL, VT);
4327 return DAG.getNode(ISD::SHL, DL, VT,
4328 DAG.getNode(N0.getOpcode(), DL, VT,
4329 N0Op0->getOperand(0)),
4330 DAG.getConstant(c1 + c2, DL, N1.getValueType()));
4335 // fold (shl (zext (srl x, C)), C) -> (zext (shl (srl x, C), C))
4336 // Only fold this if the inner zext has no other uses to avoid increasing
4337 // the total number of instructions.
4338 if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
4339 N0.getOperand(0).getOpcode() == ISD::SRL) {
4340 SDValue N0Op0 = N0.getOperand(0);
4341 if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
4342 uint64_t c1 = N0Op0C1->getZExtValue();
4343 if (c1 < VT.getScalarSizeInBits()) {
4344 uint64_t c2 = N1C->getZExtValue();
4346 SDValue NewOp0 = N0.getOperand(0);
4347 EVT CountVT = NewOp0.getOperand(1).getValueType();
4349 SDValue NewSHL = DAG.getNode(ISD::SHL, DL, NewOp0.getValueType(),
4351 DAG.getConstant(c2, DL, CountVT));
4352 AddToWorklist(NewSHL.getNode());
4353 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N0), VT, NewSHL);
4359 // fold (shl (sr[la] exact X, C1), C2) -> (shl X, (C2-C1)) if C1 <= C2
4360 // fold (shl (sr[la] exact X, C1), C2) -> (sr[la] X, (C2-C1)) if C1 > C2
4361 if (N1C && (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) &&
4362 cast<BinaryWithFlagsSDNode>(N0)->Flags.hasExact()) {
4363 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4364 uint64_t C1 = N0C1->getZExtValue();
4365 uint64_t C2 = N1C->getZExtValue();
4368 return DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
4369 DAG.getConstant(C2 - C1, DL, N1.getValueType()));
4370 return DAG.getNode(N0.getOpcode(), DL, VT, N0.getOperand(0),
4371 DAG.getConstant(C1 - C2, DL, N1.getValueType()));
4375 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
4376 // (and (srl x, (sub c1, c2), MASK)
4377 // Only fold this if the inner shift has no other uses -- if it does, folding
4378 // this will increase the total number of instructions.
4379 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4380 if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
4381 uint64_t c1 = N0C1->getZExtValue();
4382 if (c1 < OpSizeInBits) {
4383 uint64_t c2 = N1C->getZExtValue();
4384 APInt Mask = APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - c1);
4387 Mask = Mask.shl(c2 - c1);
4389 Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
4390 DAG.getConstant(c2 - c1, DL, N1.getValueType()));
4392 Mask = Mask.lshr(c1 - c2);
4394 Shift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4395 DAG.getConstant(c1 - c2, DL, N1.getValueType()));
4398 return DAG.getNode(ISD::AND, DL, VT, Shift,
4399 DAG.getConstant(Mask, DL, VT));
4403 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
4404 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
4405 unsigned BitSize = VT.getScalarSizeInBits();
4407 SDValue HiBitsMask =
4408 DAG.getConstant(APInt::getHighBitsSet(BitSize,
4409 BitSize - N1C->getZExtValue()),
4411 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0),
4415 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2)
4416 // Variant of version done on multiply, except mul by a power of 2 is turned
4419 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
4420 (isa<ConstantSDNode>(N0.getOperand(1)) ||
4421 isConstantSplatVector(N0.getOperand(1).getNode(), Val))) {
4422 SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
4423 SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
4424 return DAG.getNode(ISD::ADD, SDLoc(N), VT, Shl0, Shl1);
4427 if (N1C && !N1C->isOpaque())
4428 if (SDValue NewSHL = visitShiftByConstant(N, N1C))
4434 SDValue DAGCombiner::visitSRA(SDNode *N) {
4435 SDValue N0 = N->getOperand(0);
4436 SDValue N1 = N->getOperand(1);
4437 EVT VT = N0.getValueType();
4438 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4441 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4442 if (VT.isVector()) {
4443 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4446 N1C = isConstOrConstSplat(N1);
4449 // fold (sra c1, c2) -> (sra c1, c2)
4450 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4451 if (N0C && N1C && !N1C->isOpaque())
4452 return DAG.FoldConstantArithmetic(ISD::SRA, SDLoc(N), VT, N0C, N1C);
4453 // fold (sra 0, x) -> 0
4454 if (isNullConstant(N0))
4456 // fold (sra -1, x) -> -1
4457 if (isAllOnesConstant(N0))
4459 // fold (sra x, (setge c, size(x))) -> undef
4460 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4461 return DAG.getUNDEF(VT);
4462 // fold (sra x, 0) -> x
4463 if (N1C && N1C->isNullValue())
4465 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
4467 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
4468 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
4469 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
4471 ExtVT = EVT::getVectorVT(*DAG.getContext(),
4472 ExtVT, VT.getVectorNumElements());
4473 if ((!LegalOperations ||
4474 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
4475 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
4476 N0.getOperand(0), DAG.getValueType(ExtVT));
4479 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
4480 if (N1C && N0.getOpcode() == ISD::SRA) {
4481 if (ConstantSDNode *C1 = isConstOrConstSplat(N0.getOperand(1))) {
4482 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
4483 if (Sum >= OpSizeInBits)
4484 Sum = OpSizeInBits - 1;
4486 return DAG.getNode(ISD::SRA, DL, VT, N0.getOperand(0),
4487 DAG.getConstant(Sum, DL, N1.getValueType()));
4491 // fold (sra (shl X, m), (sub result_size, n))
4492 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
4493 // result_size - n != m.
4494 // If truncate is free for the target sext(shl) is likely to result in better
4496 if (N0.getOpcode() == ISD::SHL && N1C) {
4497 // Get the two constanst of the shifts, CN0 = m, CN = n.
4498 const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
4500 LLVMContext &Ctx = *DAG.getContext();
4501 // Determine what the truncate's result bitsize and type would be.
4502 EVT TruncVT = EVT::getIntegerVT(Ctx, OpSizeInBits - N1C->getZExtValue());
4505 TruncVT = EVT::getVectorVT(Ctx, TruncVT, VT.getVectorNumElements());
4507 // Determine the residual right-shift amount.
4508 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
4510 // If the shift is not a no-op (in which case this should be just a sign
4511 // extend already), the truncated to type is legal, sign_extend is legal
4512 // on that type, and the truncate to that type is both legal and free,
4513 // perform the transform.
4514 if ((ShiftAmt > 0) &&
4515 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
4516 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
4517 TLI.isTruncateFree(VT, TruncVT)) {
4520 SDValue Amt = DAG.getConstant(ShiftAmt, DL,
4521 getShiftAmountTy(N0.getOperand(0).getValueType()));
4522 SDValue Shift = DAG.getNode(ISD::SRL, DL, VT,
4523 N0.getOperand(0), Amt);
4524 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, TruncVT,
4526 return DAG.getNode(ISD::SIGN_EXTEND, DL,
4527 N->getValueType(0), Trunc);
4532 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
4533 if (N1.getOpcode() == ISD::TRUNCATE &&
4534 N1.getOperand(0).getOpcode() == ISD::AND) {
4535 SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode());
4536 if (NewOp1.getNode())
4537 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
4540 // fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
4541 // if c1 is equal to the number of bits the trunc removes
4542 if (N0.getOpcode() == ISD::TRUNCATE &&
4543 (N0.getOperand(0).getOpcode() == ISD::SRL ||
4544 N0.getOperand(0).getOpcode() == ISD::SRA) &&
4545 N0.getOperand(0).hasOneUse() &&
4546 N0.getOperand(0).getOperand(1).hasOneUse() &&
4548 SDValue N0Op0 = N0.getOperand(0);
4549 if (ConstantSDNode *LargeShift = isConstOrConstSplat(N0Op0.getOperand(1))) {
4550 unsigned LargeShiftVal = LargeShift->getZExtValue();
4551 EVT LargeVT = N0Op0.getValueType();
4553 if (LargeVT.getScalarSizeInBits() - OpSizeInBits == LargeShiftVal) {
4556 DAG.getConstant(LargeShiftVal + N1C->getZExtValue(), DL,
4557 getShiftAmountTy(N0Op0.getOperand(0).getValueType()));
4558 SDValue SRA = DAG.getNode(ISD::SRA, DL, LargeVT,
4559 N0Op0.getOperand(0), Amt);
4560 return DAG.getNode(ISD::TRUNCATE, DL, VT, SRA);
4565 // Simplify, based on bits shifted out of the LHS.
4566 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4567 return SDValue(N, 0);
4570 // If the sign bit is known to be zero, switch this to a SRL.
4571 if (DAG.SignBitIsZero(N0))
4572 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1);
4574 if (N1C && !N1C->isOpaque())
4575 if (SDValue NewSRA = visitShiftByConstant(N, N1C))
4581 SDValue DAGCombiner::visitSRL(SDNode *N) {
4582 SDValue N0 = N->getOperand(0);
4583 SDValue N1 = N->getOperand(1);
4584 EVT VT = N0.getValueType();
4585 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
4588 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4589 if (VT.isVector()) {
4590 if (SDValue FoldedVOp = SimplifyVBinOp(N))
4593 N1C = isConstOrConstSplat(N1);
4596 // fold (srl c1, c2) -> c1 >>u c2
4597 ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
4598 if (N0C && N1C && !N1C->isOpaque())
4599 return DAG.FoldConstantArithmetic(ISD::SRL, SDLoc(N), VT, N0C, N1C);
4600 // fold (srl 0, x) -> 0
4601 if (isNullConstant(N0))
4603 // fold (srl x, c >= size(x)) -> undef
4604 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
4605 return DAG.getUNDEF(VT);
4606 // fold (srl x, 0) -> x
4607 if (N1C && N1C->isNullValue())
4609 // if (srl x, c) is known to be zero, return 0
4610 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
4611 APInt::getAllOnesValue(OpSizeInBits)))
4612 return DAG.getConstant(0, SDLoc(N), VT);
4614 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
4615 if (N1C && N0.getOpcode() == ISD::SRL) {
4616 if (ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1))) {
4617 uint64_t c1 = N01C->getZExtValue();
4618 uint64_t c2 = N1C->getZExtValue();
4620 if (c1 + c2 >= OpSizeInBits)
4621 return DAG.getConstant(0, DL, VT);
4622 return DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4623 DAG.getConstant(c1 + c2, DL, N1.getValueType()));
4627 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
4628 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
4629 N0.getOperand(0).getOpcode() == ISD::SRL &&
4630 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
4632 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
4633 uint64_t c2 = N1C->getZExtValue();
4634 EVT InnerShiftVT = N0.getOperand(0).getValueType();
4635 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
4636 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
4637 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
4638 if (c1 + OpSizeInBits == InnerShiftSize) {
4640 if (c1 + c2 >= InnerShiftSize)
4641 return DAG.getConstant(0, DL, VT);
4642 return DAG.getNode(ISD::TRUNCATE, DL, VT,
4643 DAG.getNode(ISD::SRL, DL, InnerShiftVT,
4644 N0.getOperand(0)->getOperand(0),
4645 DAG.getConstant(c1 + c2, DL,
4650 // fold (srl (shl x, c), c) -> (and x, cst2)
4651 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
4652 unsigned BitSize = N0.getScalarValueSizeInBits();
4653 if (BitSize <= 64) {
4654 uint64_t ShAmt = N1C->getZExtValue() + 64 - BitSize;
4656 return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0),
4657 DAG.getConstant(~0ULL >> ShAmt, DL, VT));
4661 // fold (srl (anyextend x), c) -> (and (anyextend (srl x, c)), mask)
4662 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
4663 // Shifting in all undef bits?
4664 EVT SmallVT = N0.getOperand(0).getValueType();
4665 unsigned BitSize = SmallVT.getScalarSizeInBits();
4666 if (N1C->getZExtValue() >= BitSize)
4667 return DAG.getUNDEF(VT);
4669 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
4670 uint64_t ShiftAmt = N1C->getZExtValue();
4672 SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT,
4674 DAG.getConstant(ShiftAmt, DL0,
4675 getShiftAmountTy(SmallVT)));
4676 AddToWorklist(SmallShift.getNode());
4677 APInt Mask = APInt::getAllOnesValue(OpSizeInBits).lshr(ShiftAmt);
4679 return DAG.getNode(ISD::AND, DL, VT,
4680 DAG.getNode(ISD::ANY_EXTEND, DL, VT, SmallShift),
4681 DAG.getConstant(Mask, DL, VT));
4685 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
4686 // bit, which is unmodified by sra.
4687 if (N1C && N1C->getZExtValue() + 1 == OpSizeInBits) {
4688 if (N0.getOpcode() == ISD::SRA)
4689 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
4692 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
4693 if (N1C && N0.getOpcode() == ISD::CTLZ &&
4694 N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
4695 APInt KnownZero, KnownOne;
4696 DAG.computeKnownBits(N0.getOperand(0), KnownZero, KnownOne);
4698 // If any of the input bits are KnownOne, then the input couldn't be all
4699 // zeros, thus the result of the srl will always be zero.
4700 if (KnownOne.getBoolValue()) return DAG.getConstant(0, SDLoc(N0), VT);
4702 // If all of the bits input the to ctlz node are known to be zero, then
4703 // the result of the ctlz is "32" and the result of the shift is one.
4704 APInt UnknownBits = ~KnownZero;
4705 if (UnknownBits == 0) return DAG.getConstant(1, SDLoc(N0), VT);
4707 // Otherwise, check to see if there is exactly one bit input to the ctlz.
4708 if ((UnknownBits & (UnknownBits - 1)) == 0) {
4709 // Okay, we know that only that the single bit specified by UnknownBits
4710 // could be set on input to the CTLZ node. If this bit is set, the SRL
4711 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
4712 // to an SRL/XOR pair, which is likely to simplify more.
4713 unsigned ShAmt = UnknownBits.countTrailingZeros();
4714 SDValue Op = N0.getOperand(0);
4718 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
4719 DAG.getConstant(ShAmt, DL,
4720 getShiftAmountTy(Op.getValueType())));
4721 AddToWorklist(Op.getNode());
4725 return DAG.getNode(ISD::XOR, DL, VT,
4726 Op, DAG.getConstant(1, DL, VT));
4730 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
4731 if (N1.getOpcode() == ISD::TRUNCATE &&
4732 N1.getOperand(0).getOpcode() == ISD::AND) {
4733 if (SDValue NewOp1 = distributeTruncateThroughAnd(N1.getNode()))
4734 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, NewOp1);
4737 // fold operands of srl based on knowledge that the low bits are not
4739 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
4740 return SDValue(N, 0);
4742 if (N1C && !N1C->isOpaque())
4743 if (SDValue NewSRL = visitShiftByConstant(N, N1C))
4746 // Attempt to convert a srl of a load into a narrower zero-extending load.
4747 if (SDValue NarrowLoad = ReduceLoadWidth(N))
4750 // Here is a common situation. We want to optimize:
4753 // %b = and i32 %a, 2
4754 // %c = srl i32 %b, 1
4755 // brcond i32 %c ...
4761 // %c = setcc eq %b, 0
4764 // However when after the source operand of SRL is optimized into AND, the SRL
4765 // itself may not be optimized further. Look for it and add the BRCOND into
4767 if (N->hasOneUse()) {
4768 SDNode *Use = *N->use_begin();
4769 if (Use->getOpcode() == ISD::BRCOND)
4771 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
4772 // Also look pass the truncate.
4773 Use = *Use->use_begin();
4774 if (Use->getOpcode() == ISD::BRCOND)
4782 SDValue DAGCombiner::visitBSWAP(SDNode *N) {
4783 SDValue N0 = N->getOperand(0);
4784 EVT VT = N->getValueType(0);
4786 // fold (bswap c1) -> c2
4787 if (isConstantIntBuildVectorOrConstantInt(N0))
4788 return DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N0);
4789 // fold (bswap (bswap x)) -> x
4790 if (N0.getOpcode() == ISD::BSWAP)
4791 return N0->getOperand(0);
4795 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
4796 SDValue N0 = N->getOperand(0);
4797 EVT VT = N->getValueType(0);
4799 // fold (ctlz c1) -> c2
4800 if (isConstantIntBuildVectorOrConstantInt(N0))
4801 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0);
4805 SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) {
4806 SDValue N0 = N->getOperand(0);
4807 EVT VT = N->getValueType(0);
4809 // fold (ctlz_zero_undef c1) -> c2
4810 if (isConstantIntBuildVectorOrConstantInt(N0))
4811 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4815 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
4816 SDValue N0 = N->getOperand(0);
4817 EVT VT = N->getValueType(0);
4819 // fold (cttz c1) -> c2
4820 if (isConstantIntBuildVectorOrConstantInt(N0))
4821 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0);
4825 SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) {
4826 SDValue N0 = N->getOperand(0);
4827 EVT VT = N->getValueType(0);
4829 // fold (cttz_zero_undef c1) -> c2
4830 if (isConstantIntBuildVectorOrConstantInt(N0))
4831 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0);
4835 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
4836 SDValue N0 = N->getOperand(0);
4837 EVT VT = N->getValueType(0);
4839 // fold (ctpop c1) -> c2
4840 if (isConstantIntBuildVectorOrConstantInt(N0))
4841 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0);
4846 /// \brief Generate Min/Max node
4847 static SDValue combineMinNumMaxNum(SDLoc DL, EVT VT, SDValue LHS, SDValue RHS,
4848 SDValue True, SDValue False,
4849 ISD::CondCode CC, const TargetLowering &TLI,
4850 SelectionDAG &DAG) {
4851 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
4861 unsigned Opcode = (LHS == True) ? ISD::FMINNUM : ISD::FMAXNUM;
4862 if (TLI.isOperationLegal(Opcode, VT))
4863 return DAG.getNode(Opcode, DL, VT, LHS, RHS);
4872 unsigned Opcode = (LHS == True) ? ISD::FMAXNUM : ISD::FMINNUM;
4873 if (TLI.isOperationLegal(Opcode, VT))
4874 return DAG.getNode(Opcode, DL, VT, LHS, RHS);
4882 SDValue DAGCombiner::visitSELECT(SDNode *N) {
4883 SDValue N0 = N->getOperand(0);
4884 SDValue N1 = N->getOperand(1);
4885 SDValue N2 = N->getOperand(2);
4886 EVT VT = N->getValueType(0);
4887 EVT VT0 = N0.getValueType();
4889 // fold (select C, X, X) -> X
4892 if (const ConstantSDNode *N0C = dyn_cast<const ConstantSDNode>(N0)) {
4893 // fold (select true, X, Y) -> X
4894 // fold (select false, X, Y) -> Y
4895 return !N0C->isNullValue() ? N1 : N2;
4897 // fold (select C, 1, X) -> (or C, X)
4898 if (VT == MVT::i1 && isOneConstant(N1))
4899 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4900 // fold (select C, 0, 1) -> (xor C, 1)
4901 // We can't do this reliably if integer based booleans have different contents
4902 // to floating point based booleans. This is because we can't tell whether we
4903 // have an integer-based boolean or a floating-point-based boolean unless we
4904 // can find the SETCC that produced it and inspect its operands. This is
4905 // fairly easy if C is the SETCC node, but it can potentially be
4906 // undiscoverable (or not reasonably discoverable). For example, it could be
4907 // in another basic block or it could require searching a complicated
4909 if (VT.isInteger() &&
4910 (VT0 == MVT::i1 || (VT0.isInteger() &&
4911 TLI.getBooleanContents(false, false) ==
4912 TLI.getBooleanContents(false, true) &&
4913 TLI.getBooleanContents(false, false) ==
4914 TargetLowering::ZeroOrOneBooleanContent)) &&
4915 isNullConstant(N1) && isOneConstant(N2)) {
4919 return DAG.getNode(ISD::XOR, DL, VT0,
4920 N0, DAG.getConstant(1, DL, VT0));
4923 XORNode = DAG.getNode(ISD::XOR, DL0, VT0,
4924 N0, DAG.getConstant(1, DL0, VT0));
4925 AddToWorklist(XORNode.getNode());
4927 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, XORNode);
4928 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, XORNode);
4930 // fold (select C, 0, X) -> (and (not C), X)
4931 if (VT == VT0 && VT == MVT::i1 && isNullConstant(N1)) {
4932 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4933 AddToWorklist(NOTNode.getNode());
4934 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2);
4936 // fold (select C, X, 1) -> (or (not C), X)
4937 if (VT == VT0 && VT == MVT::i1 && isOneConstant(N2)) {
4938 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT);
4939 AddToWorklist(NOTNode.getNode());
4940 return DAG.getNode(ISD::OR, SDLoc(N), VT, NOTNode, N1);
4942 // fold (select C, X, 0) -> (and C, X)
4943 if (VT == MVT::i1 && isNullConstant(N2))
4944 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4945 // fold (select X, X, Y) -> (or X, Y)
4946 // fold (select X, 1, Y) -> (or X, Y)
4947 if (VT == MVT::i1 && (N0 == N1 || isOneConstant(N1)))
4948 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2);
4949 // fold (select X, Y, X) -> (and X, Y)
4950 // fold (select X, Y, 0) -> (and X, Y)
4951 if (VT == MVT::i1 && (N0 == N2 || isNullConstant(N2)))
4952 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1);
4954 // If we can fold this based on the true/false value, do so.
4955 if (SimplifySelectOps(N, N1, N2))
4956 return SDValue(N, 0); // Don't revisit N.
4958 // fold selects based on a setcc into other things, such as min/max/abs
4959 if (N0.getOpcode() == ISD::SETCC) {
4960 // select x, y (fcmp lt x, y) -> fminnum x, y
4961 // select x, y (fcmp gt x, y) -> fmaxnum x, y
4963 // This is OK if we don't care about what happens if either operand is a
4967 // FIXME: Instead of testing for UnsafeFPMath, this should be checking for
4968 // no signed zeros as well as no nans.
4969 const TargetOptions &Options = DAG.getTarget().Options;
4970 if (Options.UnsafeFPMath &&
4971 VT.isFloatingPoint() && N0.hasOneUse() &&
4972 DAG.isKnownNeverNaN(N1) && DAG.isKnownNeverNaN(N2)) {
4973 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4976 combineMinNumMaxNum(SDLoc(N), VT, N0.getOperand(0), N0.getOperand(1),
4977 N1, N2, CC, TLI, DAG);
4982 if ((!LegalOperations &&
4983 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) ||
4984 TLI.isOperationLegal(ISD::SELECT_CC, VT))
4985 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT,
4986 N0.getOperand(0), N0.getOperand(1),
4987 N1, N2, N0.getOperand(2));
4988 return SimplifySelect(SDLoc(N), N0, N1, N2);
4991 if (VT0 == MVT::i1) {
4992 if (TLI.shouldNormalizeToSelectSequence(*DAG.getContext(), VT)) {
4993 // select (and Cond0, Cond1), X, Y
4994 // -> select Cond0, (select Cond1, X, Y), Y
4995 if (N0->getOpcode() == ISD::AND && N0->hasOneUse()) {
4996 SDValue Cond0 = N0->getOperand(0);
4997 SDValue Cond1 = N0->getOperand(1);
4998 SDValue InnerSelect = DAG.getNode(ISD::SELECT, SDLoc(N),
4999 N1.getValueType(), Cond1, N1, N2);
5000 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Cond0,
5003 // select (or Cond0, Cond1), X, Y -> select Cond0, X, (select Cond1, X, Y)
5004 if (N0->getOpcode() == ISD::OR && N0->hasOneUse()) {
5005 SDValue Cond0 = N0->getOperand(0);
5006 SDValue Cond1 = N0->getOperand(1);
5007 SDValue InnerSelect = DAG.getNode(ISD::SELECT, SDLoc(N),
5008 N1.getValueType(), Cond1, N1, N2);
5009 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Cond0, N1,
5014 // select Cond0, (select Cond1, X, Y), Y -> select (and Cond0, Cond1), X, Y
5015 if (N1->getOpcode() == ISD::SELECT) {
5016 SDValue N1_0 = N1->getOperand(0);
5017 SDValue N1_1 = N1->getOperand(1);
5018 SDValue N1_2 = N1->getOperand(2);
5019 if (N1_2 == N2 && N0.getValueType() == N1_0.getValueType()) {
5020 // Create the actual and node if we can generate good code for it.
5021 if (!TLI.shouldNormalizeToSelectSequence(*DAG.getContext(), VT)) {
5022 SDValue And = DAG.getNode(ISD::AND, SDLoc(N), N0.getValueType(),
5024 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), And,
5027 // Otherwise see if we can optimize the "and" to a better pattern.
5028 if (SDValue Combined = visitANDLike(N0, N1_0, N))
5029 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Combined,
5033 // select Cond0, X, (select Cond1, X, Y) -> select (or Cond0, Cond1), X, Y
5034 if (N2->getOpcode() == ISD::SELECT) {
5035 SDValue N2_0 = N2->getOperand(0);
5036 SDValue N2_1 = N2->getOperand(1);
5037 SDValue N2_2 = N2->getOperand(2);
5038 if (N2_1 == N1 && N0.getValueType() == N2_0.getValueType()) {
5039 // Create the actual or node if we can generate good code for it.
5040 if (!TLI.shouldNormalizeToSelectSequence(*DAG.getContext(), VT)) {
5041 SDValue Or = DAG.getNode(ISD::OR, SDLoc(N), N0.getValueType(),
5043 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Or,
5046 // Otherwise see if we can optimize to a better pattern.
5047 if (SDValue Combined = visitORLike(N0, N2_0, N))
5048 return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(), Combined,
5058 std::pair<SDValue, SDValue> SplitVSETCC(const SDNode *N, SelectionDAG &DAG) {
5061 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
5063 // Split the inputs.
5064 SDValue Lo, Hi, LL, LH, RL, RH;
5065 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 0);
5066 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 1);
5068 Lo = DAG.getNode(N->getOpcode(), DL, LoVT, LL, RL, N->getOperand(2));
5069 Hi = DAG.getNode(N->getOpcode(), DL, HiVT, LH, RH, N->getOperand(2));
5071 return std::make_pair(Lo, Hi);
5074 // This function assumes all the vselect's arguments are CONCAT_VECTOR
5075 // nodes and that the condition is a BV of ConstantSDNodes (or undefs).
5076 static SDValue ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) {
5078 SDValue Cond = N->getOperand(0);
5079 SDValue LHS = N->getOperand(1);
5080 SDValue RHS = N->getOperand(2);
5081 EVT VT = N->getValueType(0);
5082 int NumElems = VT.getVectorNumElements();
5083 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS &&
5084 RHS.getOpcode() == ISD::CONCAT_VECTORS &&
5085 Cond.getOpcode() == ISD::BUILD_VECTOR);
5087 // CONCAT_VECTOR can take an arbitrary number of arguments. We only care about
5088 // binary ones here.
5089 if (LHS->getNumOperands() != 2 || RHS->getNumOperands() != 2)
5092 // We're sure we have an even number of elements due to the
5093 // concat_vectors we have as arguments to vselect.
5094 // Skip BV elements until we find one that's not an UNDEF
5095 // After we find an UNDEF element, keep looping until we get to half the
5096 // length of the BV and see if all the non-undef nodes are the same.
5097 ConstantSDNode *BottomHalf = nullptr;
5098 for (int i = 0; i < NumElems / 2; ++i) {
5099 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
5102 if (BottomHalf == nullptr)
5103 BottomHalf = cast<ConstantSDNode>(Cond.getOperand(i));
5104 else if (Cond->getOperand(i).getNode() != BottomHalf)
5108 // Do the same for the second half of the BuildVector
5109 ConstantSDNode *TopHalf = nullptr;
5110 for (int i = NumElems / 2; i < NumElems; ++i) {
5111 if (Cond->getOperand(i)->getOpcode() == ISD::UNDEF)
5114 if (TopHalf == nullptr)
5115 TopHalf = cast<ConstantSDNode>(Cond.getOperand(i));
5116 else if (Cond->getOperand(i).getNode() != TopHalf)
5120 assert(TopHalf && BottomHalf &&
5121 "One half of the selector was all UNDEFs and the other was all the "
5122 "same value. This should have been addressed before this function.");
5124 ISD::CONCAT_VECTORS, dl, VT,
5125 BottomHalf->isNullValue() ? RHS->getOperand(0) : LHS->getOperand(0),
5126 TopHalf->isNullValue() ? RHS->getOperand(1) : LHS->getOperand(1));
5129 SDValue DAGCombiner::visitMSCATTER(SDNode *N) {
5131 if (Level >= AfterLegalizeTypes)
5134 MaskedScatterSDNode *MSC = cast<MaskedScatterSDNode>(N);
5135 SDValue Mask = MSC->getMask();
5136 SDValue Data = MSC->getValue();
5139 // If the MSCATTER data type requires splitting and the mask is provided by a
5140 // SETCC, then split both nodes and its operands before legalization. This
5141 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5142 // and enables future optimizations (e.g. min/max pattern matching on X86).
5143 if (Mask.getOpcode() != ISD::SETCC)
5146 // Check if any splitting is required.
5147 if (TLI.getTypeAction(*DAG.getContext(), Data.getValueType()) !=
5148 TargetLowering::TypeSplitVector)
5150 SDValue MaskLo, MaskHi, Lo, Hi;
5151 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
5154 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MSC->getValueType(0));
5156 SDValue Chain = MSC->getChain();
5158 EVT MemoryVT = MSC->getMemoryVT();
5159 unsigned Alignment = MSC->getOriginalAlignment();
5161 EVT LoMemVT, HiMemVT;
5162 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
5164 SDValue DataLo, DataHi;
5165 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
5167 SDValue BasePtr = MSC->getBasePtr();
5168 SDValue IndexLo, IndexHi;
5169 std::tie(IndexLo, IndexHi) = DAG.SplitVector(MSC->getIndex(), DL);
5171 MachineMemOperand *MMO = DAG.getMachineFunction().
5172 getMachineMemOperand(MSC->getPointerInfo(),
5173 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
5174 Alignment, MSC->getAAInfo(), MSC->getRanges());
5176 SDValue OpsLo[] = { Chain, DataLo, MaskLo, BasePtr, IndexLo };
5177 Lo = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataLo.getValueType(),
5180 SDValue OpsHi[] = {Chain, DataHi, MaskHi, BasePtr, IndexHi};
5181 Hi = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), DataHi.getValueType(),
5184 AddToWorklist(Lo.getNode());
5185 AddToWorklist(Hi.getNode());
5187 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
5190 SDValue DAGCombiner::visitMSTORE(SDNode *N) {
5192 if (Level >= AfterLegalizeTypes)
5195 MaskedStoreSDNode *MST = dyn_cast<MaskedStoreSDNode>(N);
5196 SDValue Mask = MST->getMask();
5197 SDValue Data = MST->getValue();
5200 // If the MSTORE data type requires splitting and the mask is provided by a
5201 // SETCC, then split both nodes and its operands before legalization. This
5202 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5203 // and enables future optimizations (e.g. min/max pattern matching on X86).
5204 if (Mask.getOpcode() == ISD::SETCC) {
5206 // Check if any splitting is required.
5207 if (TLI.getTypeAction(*DAG.getContext(), Data.getValueType()) !=
5208 TargetLowering::TypeSplitVector)
5211 SDValue MaskLo, MaskHi, Lo, Hi;
5212 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
5215 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MST->getValueType(0));
5217 SDValue Chain = MST->getChain();
5218 SDValue Ptr = MST->getBasePtr();
5220 EVT MemoryVT = MST->getMemoryVT();
5221 unsigned Alignment = MST->getOriginalAlignment();
5223 // if Alignment is equal to the vector size,
5224 // take the half of it for the second part
5225 unsigned SecondHalfAlignment =
5226 (Alignment == Data->getValueType(0).getSizeInBits()/8) ?
5227 Alignment/2 : Alignment;
5229 EVT LoMemVT, HiMemVT;
5230 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
5232 SDValue DataLo, DataHi;
5233 std::tie(DataLo, DataHi) = DAG.SplitVector(Data, DL);
5235 MachineMemOperand *MMO = DAG.getMachineFunction().
5236 getMachineMemOperand(MST->getPointerInfo(),
5237 MachineMemOperand::MOStore, LoMemVT.getStoreSize(),
5238 Alignment, MST->getAAInfo(), MST->getRanges());
5240 Lo = DAG.getMaskedStore(Chain, DL, DataLo, Ptr, MaskLo, LoMemVT, MMO,
5241 MST->isTruncatingStore());
5243 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
5244 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5245 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
5247 MMO = DAG.getMachineFunction().
5248 getMachineMemOperand(MST->getPointerInfo(),
5249 MachineMemOperand::MOStore, HiMemVT.getStoreSize(),
5250 SecondHalfAlignment, MST->getAAInfo(),
5253 Hi = DAG.getMaskedStore(Chain, DL, DataHi, Ptr, MaskHi, HiMemVT, MMO,
5254 MST->isTruncatingStore());
5256 AddToWorklist(Lo.getNode());
5257 AddToWorklist(Hi.getNode());
5259 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
5264 SDValue DAGCombiner::visitMGATHER(SDNode *N) {
5266 if (Level >= AfterLegalizeTypes)
5269 MaskedGatherSDNode *MGT = dyn_cast<MaskedGatherSDNode>(N);
5270 SDValue Mask = MGT->getMask();
5273 // If the MGATHER result requires splitting and the mask is provided by a
5274 // SETCC, then split both nodes and its operands before legalization. This
5275 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5276 // and enables future optimizations (e.g. min/max pattern matching on X86).
5278 if (Mask.getOpcode() != ISD::SETCC)
5281 EVT VT = N->getValueType(0);
5283 // Check if any splitting is required.
5284 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
5285 TargetLowering::TypeSplitVector)
5288 SDValue MaskLo, MaskHi, Lo, Hi;
5289 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
5291 SDValue Src0 = MGT->getValue();
5292 SDValue Src0Lo, Src0Hi;
5293 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL);
5296 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
5298 SDValue Chain = MGT->getChain();
5299 EVT MemoryVT = MGT->getMemoryVT();
5300 unsigned Alignment = MGT->getOriginalAlignment();
5302 EVT LoMemVT, HiMemVT;
5303 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
5305 SDValue BasePtr = MGT->getBasePtr();
5306 SDValue Index = MGT->getIndex();
5307 SDValue IndexLo, IndexHi;
5308 std::tie(IndexLo, IndexHi) = DAG.SplitVector(Index, DL);
5310 MachineMemOperand *MMO = DAG.getMachineFunction().
5311 getMachineMemOperand(MGT->getPointerInfo(),
5312 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
5313 Alignment, MGT->getAAInfo(), MGT->getRanges());
5315 SDValue OpsLo[] = { Chain, Src0Lo, MaskLo, BasePtr, IndexLo };
5316 Lo = DAG.getMaskedGather(DAG.getVTList(LoVT, MVT::Other), LoVT, DL, OpsLo,
5319 SDValue OpsHi[] = {Chain, Src0Hi, MaskHi, BasePtr, IndexHi};
5320 Hi = DAG.getMaskedGather(DAG.getVTList(HiVT, MVT::Other), HiVT, DL, OpsHi,
5323 AddToWorklist(Lo.getNode());
5324 AddToWorklist(Hi.getNode());
5326 // Build a factor node to remember that this load is independent of the
5328 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo.getValue(1),
5331 // Legalized the chain result - switch anything that used the old chain to
5333 DAG.ReplaceAllUsesOfValueWith(SDValue(MGT, 1), Chain);
5335 SDValue GatherRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
5337 SDValue RetOps[] = { GatherRes, Chain };
5338 return DAG.getMergeValues(RetOps, DL);
5341 SDValue DAGCombiner::visitMLOAD(SDNode *N) {
5343 if (Level >= AfterLegalizeTypes)
5346 MaskedLoadSDNode *MLD = dyn_cast<MaskedLoadSDNode>(N);
5347 SDValue Mask = MLD->getMask();
5350 // If the MLOAD result requires splitting and the mask is provided by a
5351 // SETCC, then split both nodes and its operands before legalization. This
5352 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5353 // and enables future optimizations (e.g. min/max pattern matching on X86).
5355 if (Mask.getOpcode() == ISD::SETCC) {
5356 EVT VT = N->getValueType(0);
5358 // Check if any splitting is required.
5359 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
5360 TargetLowering::TypeSplitVector)
5363 SDValue MaskLo, MaskHi, Lo, Hi;
5364 std::tie(MaskLo, MaskHi) = SplitVSETCC(Mask.getNode(), DAG);
5366 SDValue Src0 = MLD->getSrc0();
5367 SDValue Src0Lo, Src0Hi;
5368 std::tie(Src0Lo, Src0Hi) = DAG.SplitVector(Src0, DL);
5371 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(MLD->getValueType(0));
5373 SDValue Chain = MLD->getChain();
5374 SDValue Ptr = MLD->getBasePtr();
5375 EVT MemoryVT = MLD->getMemoryVT();
5376 unsigned Alignment = MLD->getOriginalAlignment();
5378 // if Alignment is equal to the vector size,
5379 // take the half of it for the second part
5380 unsigned SecondHalfAlignment =
5381 (Alignment == MLD->getValueType(0).getSizeInBits()/8) ?
5382 Alignment/2 : Alignment;
5384 EVT LoMemVT, HiMemVT;
5385 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemoryVT);
5387 MachineMemOperand *MMO = DAG.getMachineFunction().
5388 getMachineMemOperand(MLD->getPointerInfo(),
5389 MachineMemOperand::MOLoad, LoMemVT.getStoreSize(),
5390 Alignment, MLD->getAAInfo(), MLD->getRanges());
5392 Lo = DAG.getMaskedLoad(LoVT, DL, Chain, Ptr, MaskLo, Src0Lo, LoMemVT, MMO,
5395 unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
5396 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
5397 DAG.getConstant(IncrementSize, DL, Ptr.getValueType()));
5399 MMO = DAG.getMachineFunction().
5400 getMachineMemOperand(MLD->getPointerInfo(),
5401 MachineMemOperand::MOLoad, HiMemVT.getStoreSize(),
5402 SecondHalfAlignment, MLD->getAAInfo(), MLD->getRanges());
5404 Hi = DAG.getMaskedLoad(HiVT, DL, Chain, Ptr, MaskHi, Src0Hi, HiMemVT, MMO,
5407 AddToWorklist(Lo.getNode());
5408 AddToWorklist(Hi.getNode());
5410 // Build a factor node to remember that this load is independent of the
5412 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo.getValue(1),
5415 // Legalized the chain result - switch anything that used the old chain to
5417 DAG.ReplaceAllUsesOfValueWith(SDValue(MLD, 1), Chain);
5419 SDValue LoadRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
5421 SDValue RetOps[] = { LoadRes, Chain };
5422 return DAG.getMergeValues(RetOps, DL);
5427 SDValue DAGCombiner::visitVSELECT(SDNode *N) {
5428 SDValue N0 = N->getOperand(0);
5429 SDValue N1 = N->getOperand(1);
5430 SDValue N2 = N->getOperand(2);
5433 // Canonicalize integer abs.
5434 // vselect (setg[te] X, 0), X, -X ->
5435 // vselect (setgt X, -1), X, -X ->
5436 // vselect (setl[te] X, 0), -X, X ->
5437 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
5438 if (N0.getOpcode() == ISD::SETCC) {
5439 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
5440 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
5442 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
5444 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
5445 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) &&
5446 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1))
5447 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode());
5448 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) &&
5449 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1))
5450 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode());
5453 EVT VT = LHS.getValueType();
5454 SDValue Shift = DAG.getNode(
5455 ISD::SRA, DL, VT, LHS,
5456 DAG.getConstant(VT.getScalarType().getSizeInBits() - 1, DL, VT));
5457 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift);
5458 AddToWorklist(Shift.getNode());
5459 AddToWorklist(Add.getNode());
5460 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift);
5464 if (SimplifySelectOps(N, N1, N2))
5465 return SDValue(N, 0); // Don't revisit N.
5467 // If the VSELECT result requires splitting and the mask is provided by a
5468 // SETCC, then split both nodes and its operands before legalization. This
5469 // prevents the type legalizer from unrolling SETCC into scalar comparisons
5470 // and enables future optimizations (e.g. min/max pattern matching on X86).
5471 if (N0.getOpcode() == ISD::SETCC) {
5472 EVT VT = N->getValueType(0);
5474 // Check if any splitting is required.
5475 if (TLI.getTypeAction(*DAG.getContext(), VT) !=
5476 TargetLowering::TypeSplitVector)
5479 SDValue Lo, Hi, CCLo, CCHi, LL, LH, RL, RH;
5480 std::tie(CCLo, CCHi) = SplitVSETCC(N0.getNode(), DAG);
5481 std::tie(LL, LH) = DAG.SplitVectorOperand(N, 1);
5482 std::tie(RL, RH) = DAG.SplitVectorOperand(N, 2);
5484 Lo = DAG.getNode(N->getOpcode(), DL, LL.getValueType(), CCLo, LL, RL);
5485 Hi = DAG.getNode(N->getOpcode(), DL, LH.getValueType(), CCHi, LH, RH);
5487 // Add the new VSELECT nodes to the work list in case they need to be split
5489 AddToWorklist(Lo.getNode());
5490 AddToWorklist(Hi.getNode());
5492 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
5495 // Fold (vselect (build_vector all_ones), N1, N2) -> N1
5496 if (ISD::isBuildVectorAllOnes(N0.getNode()))
5498 // Fold (vselect (build_vector all_zeros), N1, N2) -> N2
5499 if (ISD::isBuildVectorAllZeros(N0.getNode()))
5502 // The ConvertSelectToConcatVector function is assuming both the above
5503 // checks for (vselect (build_vector all{ones,zeros) ...) have been made
5505 if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
5506 N2.getOpcode() == ISD::CONCAT_VECTORS &&
5507 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
5508 if (SDValue CV = ConvertSelectToConcatVector(N, DAG))
5515 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
5516 SDValue N0 = N->getOperand(0);
5517 SDValue N1 = N->getOperand(1);
5518 SDValue N2 = N->getOperand(2);
5519 SDValue N3 = N->getOperand(3);
5520 SDValue N4 = N->getOperand(4);
5521 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
5523 // fold select_cc lhs, rhs, x, x, cc -> x
5527 // Determine if the condition we're dealing with is constant
5528 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
5529 N0, N1, CC, SDLoc(N), false);
5530 if (SCC.getNode()) {
5531 AddToWorklist(SCC.getNode());
5533 if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) {
5534 if (!SCCC->isNullValue())
5535 return N2; // cond always true -> true val
5537 return N3; // cond always false -> false val
5538 } else if (SCC->getOpcode() == ISD::UNDEF) {
5539 // When the condition is UNDEF, just return the first operand. This is
5540 // coherent the DAG creation, no setcc node is created in this case
5542 } else if (SCC.getOpcode() == ISD::SETCC) {
5543 // Fold to a simpler select_cc
5544 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(),
5545 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
5550 // If we can fold this based on the true/false value, do so.
5551 if (SimplifySelectOps(N, N2, N3))
5552 return SDValue(N, 0); // Don't revisit N.
5554 // fold select_cc into other things, such as min/max/abs
5555 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC);
5558 SDValue DAGCombiner::visitSETCC(SDNode *N) {
5559 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
5560 cast<CondCodeSDNode>(N->getOperand(2))->get(),
5564 /// Try to fold a sext/zext/aext dag node into a ConstantSDNode or
5565 /// a build_vector of constants.
5566 /// This function is called by the DAGCombiner when visiting sext/zext/aext
5567 /// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
5568 /// Vector extends are not folded if operations are legal; this is to
5569 /// avoid introducing illegal build_vector dag nodes.
5570 static SDNode *tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI,
5571 SelectionDAG &DAG, bool LegalTypes,
5572 bool LegalOperations) {
5573 unsigned Opcode = N->getOpcode();
5574 SDValue N0 = N->getOperand(0);
5575 EVT VT = N->getValueType(0);
5577 assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
5578 Opcode == ISD::ANY_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
5579 && "Expected EXTEND dag node in input!");
5581 // fold (sext c1) -> c1
5582 // fold (zext c1) -> c1
5583 // fold (aext c1) -> c1
5584 if (isa<ConstantSDNode>(N0))
5585 return DAG.getNode(Opcode, SDLoc(N), VT, N0).getNode();
5587 // fold (sext (build_vector AllConstants) -> (build_vector AllConstants)
5588 // fold (zext (build_vector AllConstants) -> (build_vector AllConstants)
5589 // fold (aext (build_vector AllConstants) -> (build_vector AllConstants)
5590 EVT SVT = VT.getScalarType();
5591 if (!(VT.isVector() &&
5592 (!LegalTypes || (!LegalOperations && TLI.isTypeLegal(SVT))) &&
5593 ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
5596 // We can fold this node into a build_vector.
5597 unsigned VTBits = SVT.getSizeInBits();
5598 unsigned EVTBits = N0->getValueType(0).getScalarType().getSizeInBits();
5599 SmallVector<SDValue, 8> Elts;
5600 unsigned NumElts = VT.getVectorNumElements();
5603 for (unsigned i=0; i != NumElts; ++i) {
5604 SDValue Op = N0->getOperand(i);
5605 if (Op->getOpcode() == ISD::UNDEF) {
5606 Elts.push_back(DAG.getUNDEF(SVT));
5611 // Get the constant value and if needed trunc it to the size of the type.
5612 // Nodes like build_vector might have constants wider than the scalar type.
5613 APInt C = cast<ConstantSDNode>(Op)->getAPIntValue().zextOrTrunc(EVTBits);
5614 if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
5615 Elts.push_back(DAG.getConstant(C.sext(VTBits), DL, SVT));
5617 Elts.push_back(DAG.getConstant(C.zext(VTBits), DL, SVT));
5620 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Elts).getNode();
5623 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
5624 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
5625 // transformation. Returns true if extension are possible and the above
5626 // mentioned transformation is profitable.
5627 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
5629 SmallVectorImpl<SDNode *> &ExtendNodes,
5630 const TargetLowering &TLI) {
5631 bool HasCopyToRegUses = false;
5632 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
5633 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
5634 UE = N0.getNode()->use_end();
5639 if (UI.getUse().getResNo() != N0.getResNo())
5641 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
5642 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
5643 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
5644 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
5645 // Sign bits will be lost after a zext.
5648 for (unsigned i = 0; i != 2; ++i) {
5649 SDValue UseOp = User->getOperand(i);
5652 if (!isa<ConstantSDNode>(UseOp))
5657 ExtendNodes.push_back(User);
5660 // If truncates aren't free and there are users we can't
5661 // extend, it isn't worthwhile.
5664 // Remember if this value is live-out.
5665 if (User->getOpcode() == ISD::CopyToReg)
5666 HasCopyToRegUses = true;
5669 if (HasCopyToRegUses) {
5670 bool BothLiveOut = false;
5671 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
5673 SDUse &Use = UI.getUse();
5674 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
5680 // Both unextended and extended values are live out. There had better be
5681 // a good reason for the transformation.
5682 return ExtendNodes.size();
5687 void DAGCombiner::ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs,
5688 SDValue Trunc, SDValue ExtLoad, SDLoc DL,
5689 ISD::NodeType ExtType) {
5690 // Extend SetCC uses if necessary.
5691 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
5692 SDNode *SetCC = SetCCs[i];
5693 SmallVector<SDValue, 4> Ops;
5695 for (unsigned j = 0; j != 2; ++j) {
5696 SDValue SOp = SetCC->getOperand(j);
5698 Ops.push_back(ExtLoad);
5700 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
5703 Ops.push_back(SetCC->getOperand(2));
5704 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), Ops));
5708 // FIXME: Bring more similar combines here, common to sext/zext (maybe aext?).
5709 SDValue DAGCombiner::CombineExtLoad(SDNode *N) {
5710 SDValue N0 = N->getOperand(0);
5711 EVT DstVT = N->getValueType(0);
5712 EVT SrcVT = N0.getValueType();
5714 assert((N->getOpcode() == ISD::SIGN_EXTEND ||
5715 N->getOpcode() == ISD::ZERO_EXTEND) &&
5716 "Unexpected node type (not an extend)!");
5718 // fold (sext (load x)) to multiple smaller sextloads; same for zext.
5719 // For example, on a target with legal v4i32, but illegal v8i32, turn:
5720 // (v8i32 (sext (v8i16 (load x))))
5722 // (v8i32 (concat_vectors (v4i32 (sextload x)),
5723 // (v4i32 (sextload (x + 16)))))
5724 // Where uses of the original load, i.e.:
5726 // are replaced with:
5728 // (v8i32 (concat_vectors (v4i32 (sextload x)),
5729 // (v4i32 (sextload (x + 16)))))))
5731 // This combine is only applicable to illegal, but splittable, vectors.
5732 // All legal types, and illegal non-vector types, are handled elsewhere.
5733 // This combine is controlled by TargetLowering::isVectorLoadExtDesirable.
5735 if (N0->getOpcode() != ISD::LOAD)
5738 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5740 if (!ISD::isNON_EXTLoad(LN0) || !ISD::isUNINDEXEDLoad(LN0) ||
5741 !N0.hasOneUse() || LN0->isVolatile() || !DstVT.isVector() ||
5742 !DstVT.isPow2VectorType() || !TLI.isVectorLoadExtDesirable(SDValue(N, 0)))
5745 SmallVector<SDNode *, 4> SetCCs;
5746 if (!ExtendUsesToFormExtLoad(N, N0, N->getOpcode(), SetCCs, TLI))
5749 ISD::LoadExtType ExtType =
5750 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
5752 // Try to split the vector types to get down to legal types.
5753 EVT SplitSrcVT = SrcVT;
5754 EVT SplitDstVT = DstVT;
5755 while (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT) &&
5756 SplitSrcVT.getVectorNumElements() > 1) {
5757 SplitDstVT = DAG.GetSplitDestVTs(SplitDstVT).first;
5758 SplitSrcVT = DAG.GetSplitDestVTs(SplitSrcVT).first;
5761 if (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT))
5765 const unsigned NumSplits =
5766 DstVT.getVectorNumElements() / SplitDstVT.getVectorNumElements();
5767 const unsigned Stride = SplitSrcVT.getStoreSize();
5768 SmallVector<SDValue, 4> Loads;
5769 SmallVector<SDValue, 4> Chains;
5771 SDValue BasePtr = LN0->getBasePtr();
5772 for (unsigned Idx = 0; Idx < NumSplits; Idx++) {
5773 const unsigned Offset = Idx * Stride;
5774 const unsigned Align = MinAlign(LN0->getAlignment(), Offset);
5776 SDValue SplitLoad = DAG.getExtLoad(
5777 ExtType, DL, SplitDstVT, LN0->getChain(), BasePtr,
5778 LN0->getPointerInfo().getWithOffset(Offset), SplitSrcVT,
5779 LN0->isVolatile(), LN0->isNonTemporal(), LN0->isInvariant(),
5780 Align, LN0->getAAInfo());
5782 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
5783 DAG.getConstant(Stride, DL, BasePtr.getValueType()));
5785 Loads.push_back(SplitLoad.getValue(0));
5786 Chains.push_back(SplitLoad.getValue(1));
5789 SDValue NewChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
5790 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads);
5792 CombineTo(N, NewValue);
5794 // Replace uses of the original load (before extension)
5795 // with a truncate of the concatenated sextloaded vectors.
5797 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), NewValue);
5798 CombineTo(N0.getNode(), Trunc, NewChain);
5799 ExtendSetCCUses(SetCCs, Trunc, NewValue, DL,
5800 (ISD::NodeType)N->getOpcode());
5801 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5804 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
5805 SDValue N0 = N->getOperand(0);
5806 EVT VT = N->getValueType(0);
5808 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
5810 return SDValue(Res, 0);
5812 // fold (sext (sext x)) -> (sext x)
5813 // fold (sext (aext x)) -> (sext x)
5814 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
5815 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT,
5818 if (N0.getOpcode() == ISD::TRUNCATE) {
5819 // fold (sext (truncate (load x))) -> (sext (smaller load x))
5820 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
5821 if (SDValue NarrowLoad = ReduceLoadWidth(N0.getNode())) {
5822 SDNode* oye = N0.getNode()->getOperand(0).getNode();
5823 if (NarrowLoad.getNode() != N0.getNode()) {
5824 CombineTo(N0.getNode(), NarrowLoad);
5825 // CombineTo deleted the truncate, if needed, but not what's under it.
5828 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5831 // See if the value being truncated is already sign extended. If so, just
5832 // eliminate the trunc/sext pair.
5833 SDValue Op = N0.getOperand(0);
5834 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
5835 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
5836 unsigned DestBits = VT.getScalarType().getSizeInBits();
5837 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
5839 if (OpBits == DestBits) {
5840 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
5841 // bits, it is already ready.
5842 if (NumSignBits > DestBits-MidBits)
5844 } else if (OpBits < DestBits) {
5845 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
5846 // bits, just sext from i32.
5847 if (NumSignBits > OpBits-MidBits)
5848 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, Op);
5850 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
5851 // bits, just truncate to i32.
5852 if (NumSignBits > OpBits-MidBits)
5853 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
5856 // fold (sext (truncate x)) -> (sextinreg x).
5857 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
5858 N0.getValueType())) {
5859 if (OpBits < DestBits)
5860 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op);
5861 else if (OpBits > DestBits)
5862 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op);
5863 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op,
5864 DAG.getValueType(N0.getValueType()));
5868 // fold (sext (load x)) -> (sext (truncate (sextload x)))
5869 // Only generate vector extloads when 1) they're legal, and 2) they are
5870 // deemed desirable by the target.
5871 if (ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
5872 ((!LegalOperations && !VT.isVector() &&
5873 !cast<LoadSDNode>(N0)->isVolatile()) ||
5874 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()))) {
5875 bool DoXform = true;
5876 SmallVector<SDNode*, 4> SetCCs;
5877 if (!N0.hasOneUse())
5878 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
5880 DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0));
5882 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5883 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5885 LN0->getBasePtr(), N0.getValueType(),
5886 LN0->getMemOperand());
5887 CombineTo(N, ExtLoad);
5888 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5889 N0.getValueType(), ExtLoad);
5890 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
5891 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
5893 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5897 // fold (sext (load x)) to multiple smaller sextloads.
5898 // Only on illegal but splittable vectors.
5899 if (SDValue ExtLoad = CombineExtLoad(N))
5902 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
5903 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
5904 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
5905 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
5906 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5907 EVT MemVT = LN0->getMemoryVT();
5908 if ((!LegalOperations && !LN0->isVolatile()) ||
5909 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, MemVT)) {
5910 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
5912 LN0->getBasePtr(), MemVT,
5913 LN0->getMemOperand());
5914 CombineTo(N, ExtLoad);
5915 CombineTo(N0.getNode(),
5916 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
5917 N0.getValueType(), ExtLoad),
5918 ExtLoad.getValue(1));
5919 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5923 // fold (sext (and/or/xor (load x), cst)) ->
5924 // (and/or/xor (sextload x), (sext cst))
5925 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
5926 N0.getOpcode() == ISD::XOR) &&
5927 isa<LoadSDNode>(N0.getOperand(0)) &&
5928 N0.getOperand(1).getOpcode() == ISD::Constant &&
5929 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, N0.getValueType()) &&
5930 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
5931 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
5932 if (LN0->getExtensionType() != ISD::ZEXTLOAD && LN0->isUnindexed()) {
5933 bool DoXform = true;
5934 SmallVector<SDNode*, 4> SetCCs;
5935 if (!N0.hasOneUse())
5936 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
5939 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT,
5940 LN0->getChain(), LN0->getBasePtr(),
5942 LN0->getMemOperand());
5943 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
5944 Mask = Mask.sext(VT.getSizeInBits());
5946 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
5947 ExtLoad, DAG.getConstant(Mask, DL, VT));
5948 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
5949 SDLoc(N0.getOperand(0)),
5950 N0.getOperand(0).getValueType(), ExtLoad);
5952 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
5953 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL,
5955 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5960 if (N0.getOpcode() == ISD::SETCC) {
5961 EVT N0VT = N0.getOperand(0).getValueType();
5962 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
5963 // Only do this before legalize for now.
5964 if (VT.isVector() && !LegalOperations &&
5965 TLI.getBooleanContents(N0VT) ==
5966 TargetLowering::ZeroOrNegativeOneBooleanContent) {
5967 // On some architectures (such as SSE/NEON/etc) the SETCC result type is
5968 // of the same size as the compared operands. Only optimize sext(setcc())
5969 // if this is the case.
5970 EVT SVT = getSetCCResultType(N0VT);
5972 // We know that the # elements of the results is the same as the
5973 // # elements of the compare (and the # elements of the compare result
5974 // for that matter). Check to see that they are the same size. If so,
5975 // we know that the element size of the sext'd result matches the
5976 // element size of the compare operands.
5977 if (VT.getSizeInBits() == SVT.getSizeInBits())
5978 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
5980 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5982 // If the desired elements are smaller or larger than the source
5983 // elements we can use a matching integer vector type and then
5984 // truncate/sign extend
5985 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
5986 if (SVT == MatchingVectorType) {
5987 SDValue VsetCC = DAG.getSetCC(SDLoc(N), MatchingVectorType,
5988 N0.getOperand(0), N0.getOperand(1),
5989 cast<CondCodeSDNode>(N0.getOperand(2))->get());
5990 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT);
5994 // sext(setcc x, y, cc) -> (select (setcc x, y, cc), -1, 0)
5995 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
5998 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), DL, VT);
6000 SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1),
6001 NegOne, DAG.getConstant(0, DL, VT),
6002 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
6003 if (SCC.getNode()) return SCC;
6005 if (!VT.isVector()) {
6006 EVT SetCCVT = getSetCCResultType(N0.getOperand(0).getValueType());
6007 if (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, SetCCVT)) {
6009 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
6010 SDValue SetCC = DAG.getSetCC(DL, SetCCVT,
6011 N0.getOperand(0), N0.getOperand(1), CC);
6012 return DAG.getSelect(DL, VT, SetCC,
6013 NegOne, DAG.getConstant(0, DL, VT));
6018 // fold (sext x) -> (zext x) if the sign bit is known zero.
6019 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
6020 DAG.SignBitIsZero(N0))
6021 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0);
6026 // isTruncateOf - If N is a truncate of some other value, return true, record
6027 // the value being truncated in Op and which of Op's bits are zero in KnownZero.
6028 // This function computes KnownZero to avoid a duplicated call to
6029 // computeKnownBits in the caller.
6030 static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
6033 if (N->getOpcode() == ISD::TRUNCATE) {
6034 Op = N->getOperand(0);
6035 DAG.computeKnownBits(Op, KnownZero, KnownOne);
6039 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 ||
6040 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE)
6043 SDValue Op0 = N->getOperand(0);
6044 SDValue Op1 = N->getOperand(1);
6045 assert(Op0.getValueType() == Op1.getValueType());
6047 if (isNullConstant(Op0))
6049 else if (isNullConstant(Op1))
6054 DAG.computeKnownBits(Op, KnownZero, KnownOne);
6056 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
6062 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
6063 SDValue N0 = N->getOperand(0);
6064 EVT VT = N->getValueType(0);
6066 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
6068 return SDValue(Res, 0);
6070 // fold (zext (zext x)) -> (zext x)
6071 // fold (zext (aext x)) -> (zext x)
6072 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
6073 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT,
6076 // fold (zext (truncate x)) -> (zext x) or
6077 // (zext (truncate x)) -> (truncate x)
6078 // This is valid when the truncated bits of x are already zero.
6079 // FIXME: We should extend this to work for vectors too.
6082 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) {
6083 APInt TruncatedBits =
6084 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ?
6085 APInt(Op.getValueSizeInBits(), 0) :
6086 APInt::getBitsSet(Op.getValueSizeInBits(),
6087 N0.getValueSizeInBits(),
6088 std::min(Op.getValueSizeInBits(),
6089 VT.getSizeInBits()));
6090 if (TruncatedBits == (KnownZero & TruncatedBits)) {
6091 if (VT.bitsGT(Op.getValueType()))
6092 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op);
6093 if (VT.bitsLT(Op.getValueType()))
6094 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
6100 // fold (zext (truncate (load x))) -> (zext (smaller load x))
6101 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
6102 if (N0.getOpcode() == ISD::TRUNCATE) {
6103 if (SDValue NarrowLoad = ReduceLoadWidth(N0.getNode())) {
6104 SDNode* oye = N0.getNode()->getOperand(0).getNode();
6105 if (NarrowLoad.getNode() != N0.getNode()) {
6106 CombineTo(N0.getNode(), NarrowLoad);
6107 // CombineTo deleted the truncate, if needed, but not what's under it.
6110 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6114 // fold (zext (truncate x)) -> (and x, mask)
6115 if (N0.getOpcode() == ISD::TRUNCATE &&
6116 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
6118 // fold (zext (truncate (load x))) -> (zext (smaller load x))
6119 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
6120 if (SDValue NarrowLoad = ReduceLoadWidth(N0.getNode())) {
6121 SDNode* oye = N0.getNode()->getOperand(0).getNode();
6122 if (NarrowLoad.getNode() != N0.getNode()) {
6123 CombineTo(N0.getNode(), NarrowLoad);
6124 // CombineTo deleted the truncate, if needed, but not what's under it.
6127 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6130 SDValue Op = N0.getOperand(0);
6131 if (Op.getValueType().bitsLT(VT)) {
6132 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Op);
6133 AddToWorklist(Op.getNode());
6134 } else if (Op.getValueType().bitsGT(VT)) {
6135 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op);
6136 AddToWorklist(Op.getNode());
6138 return DAG.getZeroExtendInReg(Op, SDLoc(N),
6139 N0.getValueType().getScalarType());
6142 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
6143 // if either of the casts is not free.
6144 if (N0.getOpcode() == ISD::AND &&
6145 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
6146 N0.getOperand(1).getOpcode() == ISD::Constant &&
6147 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
6148 N0.getValueType()) ||
6149 !TLI.isZExtFree(N0.getValueType(), VT))) {
6150 SDValue X = N0.getOperand(0).getOperand(0);
6151 if (X.getValueType().bitsLT(VT)) {
6152 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(X), VT, X);
6153 } else if (X.getValueType().bitsGT(VT)) {
6154 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
6156 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
6157 Mask = Mask.zext(VT.getSizeInBits());
6159 return DAG.getNode(ISD::AND, DL, VT,
6160 X, DAG.getConstant(Mask, DL, VT));
6163 // fold (zext (load x)) -> (zext (truncate (zextload x)))
6164 // Only generate vector extloads when 1) they're legal, and 2) they are
6165 // deemed desirable by the target.
6166 if (ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6167 ((!LegalOperations && !VT.isVector() &&
6168 !cast<LoadSDNode>(N0)->isVolatile()) ||
6169 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()))) {
6170 bool DoXform = true;
6171 SmallVector<SDNode*, 4> SetCCs;
6172 if (!N0.hasOneUse())
6173 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
6175 DoXform &= TLI.isVectorLoadExtDesirable(SDValue(N, 0));
6177 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6178 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
6180 LN0->getBasePtr(), N0.getValueType(),
6181 LN0->getMemOperand());
6182 CombineTo(N, ExtLoad);
6183 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
6184 N0.getValueType(), ExtLoad);
6185 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
6187 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
6189 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6193 // fold (zext (load x)) to multiple smaller zextloads.
6194 // Only on illegal but splittable vectors.
6195 if (SDValue ExtLoad = CombineExtLoad(N))
6198 // fold (zext (and/or/xor (load x), cst)) ->
6199 // (and/or/xor (zextload x), (zext cst))
6200 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
6201 N0.getOpcode() == ISD::XOR) &&
6202 isa<LoadSDNode>(N0.getOperand(0)) &&
6203 N0.getOperand(1).getOpcode() == ISD::Constant &&
6204 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, N0.getValueType()) &&
6205 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
6206 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
6207 if (LN0->getExtensionType() != ISD::SEXTLOAD && LN0->isUnindexed()) {
6208 bool DoXform = true;
6209 SmallVector<SDNode*, 4> SetCCs;
6210 if (!N0.hasOneUse())
6211 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
6214 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT,
6215 LN0->getChain(), LN0->getBasePtr(),
6217 LN0->getMemOperand());
6218 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
6219 Mask = Mask.zext(VT.getSizeInBits());
6221 SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
6222 ExtLoad, DAG.getConstant(Mask, DL, VT));
6223 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
6224 SDLoc(N0.getOperand(0)),
6225 N0.getOperand(0).getValueType(), ExtLoad);
6227 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
6228 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, DL,
6230 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6235 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
6236 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
6237 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
6238 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
6239 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6240 EVT MemVT = LN0->getMemoryVT();
6241 if ((!LegalOperations && !LN0->isVolatile()) ||
6242 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT)) {
6243 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT,
6245 LN0->getBasePtr(), MemVT,
6246 LN0->getMemOperand());
6247 CombineTo(N, ExtLoad);
6248 CombineTo(N0.getNode(),
6249 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(),
6251 ExtLoad.getValue(1));
6252 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6256 if (N0.getOpcode() == ISD::SETCC) {
6257 if (!LegalOperations && VT.isVector() &&
6258 N0.getValueType().getVectorElementType() == MVT::i1) {
6259 EVT N0VT = N0.getOperand(0).getValueType();
6260 if (getSetCCResultType(N0VT) == N0.getValueType())
6263 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
6264 // Only do this before legalize for now.
6265 EVT EltVT = VT.getVectorElementType();
6267 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
6268 DAG.getConstant(1, DL, EltVT));
6269 if (VT.getSizeInBits() == N0VT.getSizeInBits())
6270 // We know that the # elements of the results is the same as the
6271 // # elements of the compare (and the # elements of the compare result
6272 // for that matter). Check to see that they are the same size. If so,
6273 // we know that the element size of the sext'd result matches the
6274 // element size of the compare operands.
6275 return DAG.getNode(ISD::AND, DL, VT,
6276 DAG.getSetCC(DL, VT, N0.getOperand(0),
6278 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
6279 DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
6282 // If the desired elements are smaller or larger than the source
6283 // elements we can use a matching integer vector type and then
6284 // truncate/sign extend
6285 EVT MatchingElementType =
6286 EVT::getIntegerVT(*DAG.getContext(),
6287 N0VT.getScalarType().getSizeInBits());
6288 EVT MatchingVectorType =
6289 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
6290 N0VT.getVectorNumElements());
6292 DAG.getSetCC(DL, MatchingVectorType, N0.getOperand(0),
6294 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6295 return DAG.getNode(ISD::AND, DL, VT,
6296 DAG.getSExtOrTrunc(VsetCC, DL, VT),
6297 DAG.getNode(ISD::BUILD_VECTOR, DL, VT, OneOps));
6300 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
6303 SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1),
6304 DAG.getConstant(1, DL, VT), DAG.getConstant(0, DL, VT),
6305 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
6306 if (SCC.getNode()) return SCC;
6309 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
6310 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
6311 isa<ConstantSDNode>(N0.getOperand(1)) &&
6312 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
6314 SDValue ShAmt = N0.getOperand(1);
6315 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
6316 if (N0.getOpcode() == ISD::SHL) {
6317 SDValue InnerZExt = N0.getOperand(0);
6318 // If the original shl may be shifting out bits, do not perform this
6320 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
6321 InnerZExt.getOperand(0).getValueType().getSizeInBits();
6322 if (ShAmtVal > KnownZeroBits)
6328 // Ensure that the shift amount is wide enough for the shifted value.
6329 if (VT.getSizeInBits() >= 256)
6330 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
6332 return DAG.getNode(N0.getOpcode(), DL, VT,
6333 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
6340 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
6341 SDValue N0 = N->getOperand(0);
6342 EVT VT = N->getValueType(0);
6344 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
6346 return SDValue(Res, 0);
6348 // fold (aext (aext x)) -> (aext x)
6349 // fold (aext (zext x)) -> (zext x)
6350 // fold (aext (sext x)) -> (sext x)
6351 if (N0.getOpcode() == ISD::ANY_EXTEND ||
6352 N0.getOpcode() == ISD::ZERO_EXTEND ||
6353 N0.getOpcode() == ISD::SIGN_EXTEND)
6354 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0));
6356 // fold (aext (truncate (load x))) -> (aext (smaller load x))
6357 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
6358 if (N0.getOpcode() == ISD::TRUNCATE) {
6359 if (SDValue NarrowLoad = ReduceLoadWidth(N0.getNode())) {
6360 SDNode* oye = N0.getNode()->getOperand(0).getNode();
6361 if (NarrowLoad.getNode() != N0.getNode()) {
6362 CombineTo(N0.getNode(), NarrowLoad);
6363 // CombineTo deleted the truncate, if needed, but not what's under it.
6366 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6370 // fold (aext (truncate x))
6371 if (N0.getOpcode() == ISD::TRUNCATE) {
6372 SDValue TruncOp = N0.getOperand(0);
6373 if (TruncOp.getValueType() == VT)
6374 return TruncOp; // x iff x size == zext size.
6375 if (TruncOp.getValueType().bitsGT(VT))
6376 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, TruncOp);
6377 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, TruncOp);
6380 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
6381 // if the trunc is not free.
6382 if (N0.getOpcode() == ISD::AND &&
6383 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
6384 N0.getOperand(1).getOpcode() == ISD::Constant &&
6385 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
6386 N0.getValueType())) {
6387 SDValue X = N0.getOperand(0).getOperand(0);
6388 if (X.getValueType().bitsLT(VT)) {
6389 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, X);
6390 } else if (X.getValueType().bitsGT(VT)) {
6391 X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X);
6393 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
6394 Mask = Mask.zext(VT.getSizeInBits());
6396 return DAG.getNode(ISD::AND, DL, VT,
6397 X, DAG.getConstant(Mask, DL, VT));
6400 // fold (aext (load x)) -> (aext (truncate (extload x)))
6401 // None of the supported targets knows how to perform load and any_ext
6402 // on vectors in one instruction. We only perform this transformation on
6404 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
6405 ISD::isUNINDEXEDLoad(N0.getNode()) &&
6406 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
6407 bool DoXform = true;
6408 SmallVector<SDNode*, 4> SetCCs;
6409 if (!N0.hasOneUse())
6410 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
6412 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6413 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
6415 LN0->getBasePtr(), N0.getValueType(),
6416 LN0->getMemOperand());
6417 CombineTo(N, ExtLoad);
6418 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
6419 N0.getValueType(), ExtLoad);
6420 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
6421 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N),
6423 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6427 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
6428 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
6429 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
6430 if (N0.getOpcode() == ISD::LOAD &&
6431 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6433 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6434 ISD::LoadExtType ExtType = LN0->getExtensionType();
6435 EVT MemVT = LN0->getMemoryVT();
6436 if (!LegalOperations || TLI.isLoadExtLegal(ExtType, VT, MemVT)) {
6437 SDValue ExtLoad = DAG.getExtLoad(ExtType, SDLoc(N),
6438 VT, LN0->getChain(), LN0->getBasePtr(),
6439 MemVT, LN0->getMemOperand());
6440 CombineTo(N, ExtLoad);
6441 CombineTo(N0.getNode(),
6442 DAG.getNode(ISD::TRUNCATE, SDLoc(N0),
6443 N0.getValueType(), ExtLoad),
6444 ExtLoad.getValue(1));
6445 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6449 if (N0.getOpcode() == ISD::SETCC) {
6451 // aext(setcc) -> vsetcc
6452 // aext(setcc) -> truncate(vsetcc)
6453 // aext(setcc) -> aext(vsetcc)
6454 // Only do this before legalize for now.
6455 if (VT.isVector() && !LegalOperations) {
6456 EVT N0VT = N0.getOperand(0).getValueType();
6457 // We know that the # elements of the results is the same as the
6458 // # elements of the compare (and the # elements of the compare result
6459 // for that matter). Check to see that they are the same size. If so,
6460 // we know that the element size of the sext'd result matches the
6461 // element size of the compare operands.
6462 if (VT.getSizeInBits() == N0VT.getSizeInBits())
6463 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0),
6465 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6466 // If the desired elements are smaller or larger than the source
6467 // elements we can use a matching integer vector type and then
6468 // truncate/any extend
6470 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger();
6472 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0),
6474 cast<CondCodeSDNode>(N0.getOperand(2))->get());
6475 return DAG.getAnyExtOrTrunc(VsetCC, SDLoc(N), VT);
6479 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
6482 SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1),
6483 DAG.getConstant(1, DL, VT), DAG.getConstant(0, DL, VT),
6484 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
6492 /// See if the specified operand can be simplified with the knowledge that only
6493 /// the bits specified by Mask are used. If so, return the simpler operand,
6494 /// otherwise return a null SDValue.
6495 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
6496 switch (V.getOpcode()) {
6498 case ISD::Constant: {
6499 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
6500 assert(CV && "Const value should be ConstSDNode.");
6501 const APInt &CVal = CV->getAPIntValue();
6502 APInt NewVal = CVal & Mask;
6504 return DAG.getConstant(NewVal, SDLoc(V), V.getValueType());
6509 // If the LHS or RHS don't contribute bits to the or, drop them.
6510 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
6511 return V.getOperand(1);
6512 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
6513 return V.getOperand(0);
6516 // Only look at single-use SRLs.
6517 if (!V.getNode()->hasOneUse())
6519 if (ConstantSDNode *RHSC = getAsNonOpaqueConstant(V.getOperand(1))) {
6520 // See if we can recursively simplify the LHS.
6521 unsigned Amt = RHSC->getZExtValue();
6523 // Watch out for shift count overflow though.
6524 if (Amt >= Mask.getBitWidth()) break;
6525 APInt NewMask = Mask << Amt;
6526 if (SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask))
6527 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(),
6528 SimplifyLHS, V.getOperand(1));
6534 /// If the result of a wider load is shifted to right of N bits and then
6535 /// truncated to a narrower type and where N is a multiple of number of bits of
6536 /// the narrower type, transform it to a narrower load from address + N / num of
6537 /// bits of new type. If the result is to be extended, also fold the extension
6538 /// to form a extending load.
6539 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
6540 unsigned Opc = N->getOpcode();
6542 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
6543 SDValue N0 = N->getOperand(0);
6544 EVT VT = N->getValueType(0);
6547 // This transformation isn't valid for vector loads.
6551 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
6553 if (Opc == ISD::SIGN_EXTEND_INREG) {
6554 ExtType = ISD::SEXTLOAD;
6555 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
6556 } else if (Opc == ISD::SRL) {
6557 // Another special-case: SRL is basically zero-extending a narrower value.
6558 ExtType = ISD::ZEXTLOAD;
6560 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
6561 if (!N01) return SDValue();
6562 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
6563 VT.getSizeInBits() - N01->getZExtValue());
6565 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, VT, ExtVT))
6568 unsigned EVTBits = ExtVT.getSizeInBits();
6570 // Do not generate loads of non-round integer types since these can
6571 // be expensive (and would be wrong if the type is not byte sized).
6572 if (!ExtVT.isRound())
6576 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
6577 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6578 ShAmt = N01->getZExtValue();
6579 // Is the shift amount a multiple of size of VT?
6580 if ((ShAmt & (EVTBits-1)) == 0) {
6581 N0 = N0.getOperand(0);
6582 // Is the load width a multiple of size of VT?
6583 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
6587 // At this point, we must have a load or else we can't do the transform.
6588 if (!isa<LoadSDNode>(N0)) return SDValue();
6590 // Because a SRL must be assumed to *need* to zero-extend the high bits
6591 // (as opposed to anyext the high bits), we can't combine the zextload
6592 // lowering of SRL and an sextload.
6593 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD)
6596 // If the shift amount is larger than the input type then we're not
6597 // accessing any of the loaded bytes. If the load was a zextload/extload
6598 // then the result of the shift+trunc is zero/undef (handled elsewhere).
6599 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
6604 // If the load is shifted left (and the result isn't shifted back right),
6605 // we can fold the truncate through the shift.
6606 unsigned ShLeftAmt = 0;
6607 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
6608 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
6609 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
6610 ShLeftAmt = N01->getZExtValue();
6611 N0 = N0.getOperand(0);
6615 // If we haven't found a load, we can't narrow it. Don't transform one with
6616 // multiple uses, this would require adding a new load.
6617 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse())
6620 // Don't change the width of a volatile load.
6621 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6622 if (LN0->isVolatile())
6625 // Verify that we are actually reducing a load width here.
6626 if (LN0->getMemoryVT().getSizeInBits() < EVTBits)
6629 // For the transform to be legal, the load must produce only two values
6630 // (the value loaded and the chain). Don't transform a pre-increment
6631 // load, for example, which produces an extra value. Otherwise the
6632 // transformation is not equivalent, and the downstream logic to replace
6633 // uses gets things wrong.
6634 if (LN0->getNumValues() > 2)
6637 // If the load that we're shrinking is an extload and we're not just
6638 // discarding the extension we can't simply shrink the load. Bail.
6639 // TODO: It would be possible to merge the extensions in some cases.
6640 if (LN0->getExtensionType() != ISD::NON_EXTLOAD &&
6641 LN0->getMemoryVT().getSizeInBits() < ExtVT.getSizeInBits() + ShAmt)
6644 if (!TLI.shouldReduceLoadWidth(LN0, ExtType, ExtVT))
6647 EVT PtrType = N0.getOperand(1).getValueType();
6649 if (PtrType == MVT::Untyped || PtrType.isExtended())
6650 // It's not possible to generate a constant of extended or untyped type.
6653 // For big endian targets, we need to adjust the offset to the pointer to
6654 // load the correct bytes.
6655 if (DAG.getDataLayout().isBigEndian()) {
6656 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
6657 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
6658 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
6661 uint64_t PtrOff = ShAmt / 8;
6662 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
6664 SDValue NewPtr = DAG.getNode(ISD::ADD, DL,
6665 PtrType, LN0->getBasePtr(),
6666 DAG.getConstant(PtrOff, DL, PtrType));
6667 AddToWorklist(NewPtr.getNode());
6670 if (ExtType == ISD::NON_EXTLOAD)
6671 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr,
6672 LN0->getPointerInfo().getWithOffset(PtrOff),
6673 LN0->isVolatile(), LN0->isNonTemporal(),
6674 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
6676 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr,
6677 LN0->getPointerInfo().getWithOffset(PtrOff),
6678 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
6679 LN0->isInvariant(), NewAlign, LN0->getAAInfo());
6681 // Replace the old load's chain with the new load's chain.
6682 WorklistRemover DeadNodes(*this);
6683 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
6685 // Shift the result left, if we've swallowed a left shift.
6686 SDValue Result = Load;
6687 if (ShLeftAmt != 0) {
6688 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
6689 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
6691 // If the shift amount is as large as the result size (but, presumably,
6692 // no larger than the source) then the useful bits of the result are
6693 // zero; we can't simply return the shortened shift, because the result
6694 // of that operation is undefined.
6696 if (ShLeftAmt >= VT.getSizeInBits())
6697 Result = DAG.getConstant(0, DL, VT);
6699 Result = DAG.getNode(ISD::SHL, DL, VT,
6700 Result, DAG.getConstant(ShLeftAmt, DL, ShImmTy));
6703 // Return the new loaded value.
6707 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
6708 SDValue N0 = N->getOperand(0);
6709 SDValue N1 = N->getOperand(1);
6710 EVT VT = N->getValueType(0);
6711 EVT EVT = cast<VTSDNode>(N1)->getVT();
6712 unsigned VTBits = VT.getScalarType().getSizeInBits();
6713 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
6715 // fold (sext_in_reg c1) -> c1
6716 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
6717 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1);
6719 // If the input is already sign extended, just drop the extension.
6720 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
6723 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
6724 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
6725 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT()))
6726 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6727 N0.getOperand(0), N1);
6729 // fold (sext_in_reg (sext x)) -> (sext x)
6730 // fold (sext_in_reg (aext x)) -> (sext x)
6731 // if x is small enough.
6732 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
6733 SDValue N00 = N0.getOperand(0);
6734 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
6735 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
6736 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1);
6739 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
6740 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
6741 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT);
6743 // fold operands of sext_in_reg based on knowledge that the top bits are not
6745 if (SimplifyDemandedBits(SDValue(N, 0)))
6746 return SDValue(N, 0);
6748 // fold (sext_in_reg (load x)) -> (smaller sextload x)
6749 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
6750 if (SDValue NarrowLoad = ReduceLoadWidth(N))
6753 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
6754 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
6755 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
6756 if (N0.getOpcode() == ISD::SRL) {
6757 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
6758 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
6759 // We can turn this into an SRA iff the input to the SRL is already sign
6761 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
6762 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
6763 return DAG.getNode(ISD::SRA, SDLoc(N), VT,
6764 N0.getOperand(0), N0.getOperand(1));
6768 // fold (sext_inreg (extload x)) -> (sextload x)
6769 if (ISD::isEXTLoad(N0.getNode()) &&
6770 ISD::isUNINDEXEDLoad(N0.getNode()) &&
6771 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6772 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6773 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
6774 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6775 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6777 LN0->getBasePtr(), EVT,
6778 LN0->getMemOperand());
6779 CombineTo(N, ExtLoad);
6780 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6781 AddToWorklist(ExtLoad.getNode());
6782 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6784 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
6785 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
6787 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
6788 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
6789 TLI.isLoadExtLegal(ISD::SEXTLOAD, VT, EVT))) {
6790 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6791 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT,
6793 LN0->getBasePtr(), EVT,
6794 LN0->getMemOperand());
6795 CombineTo(N, ExtLoad);
6796 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
6797 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6800 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
6801 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
6802 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
6803 N0.getOperand(1), false);
6804 if (BSwap.getNode())
6805 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
6809 // Fold a sext_inreg of a build_vector of ConstantSDNodes or undefs
6810 // into a build_vector.
6811 if (ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
6812 SmallVector<SDValue, 8> Elts;
6813 unsigned NumElts = N0->getNumOperands();
6814 unsigned ShAmt = VTBits - EVTBits;
6816 for (unsigned i = 0; i != NumElts; ++i) {
6817 SDValue Op = N0->getOperand(i);
6818 if (Op->getOpcode() == ISD::UNDEF) {
6823 ConstantSDNode *CurrentND = cast<ConstantSDNode>(Op);
6824 const APInt &C = APInt(VTBits, CurrentND->getAPIntValue().getZExtValue());
6825 Elts.push_back(DAG.getConstant(C.shl(ShAmt).ashr(ShAmt).getZExtValue(),
6826 SDLoc(Op), Op.getValueType()));
6829 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Elts);
6835 SDValue DAGCombiner::visitSIGN_EXTEND_VECTOR_INREG(SDNode *N) {
6836 SDValue N0 = N->getOperand(0);
6837 EVT VT = N->getValueType(0);
6839 if (N0.getOpcode() == ISD::UNDEF)
6840 return DAG.getUNDEF(VT);
6842 if (SDNode *Res = tryToFoldExtendOfConstant(N, TLI, DAG, LegalTypes,
6844 return SDValue(Res, 0);
6849 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
6850 SDValue N0 = N->getOperand(0);
6851 EVT VT = N->getValueType(0);
6852 bool isLE = DAG.getDataLayout().isLittleEndian();
6855 if (N0.getValueType() == N->getValueType(0))
6857 // fold (truncate c1) -> c1
6858 if (isConstantIntBuildVectorOrConstantInt(N0))
6859 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0);
6860 // fold (truncate (truncate x)) -> (truncate x)
6861 if (N0.getOpcode() == ISD::TRUNCATE)
6862 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6863 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
6864 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
6865 N0.getOpcode() == ISD::SIGN_EXTEND ||
6866 N0.getOpcode() == ISD::ANY_EXTEND) {
6867 if (N0.getOperand(0).getValueType().bitsLT(VT))
6868 // if the source is smaller than the dest, we still need an extend
6869 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
6871 if (N0.getOperand(0).getValueType().bitsGT(VT))
6872 // if the source is larger than the dest, than we just need the truncate
6873 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0));
6874 // if the source and dest are the same type, we can drop both the extend
6875 // and the truncate.
6876 return N0.getOperand(0);
6879 // Fold extract-and-trunc into a narrow extract. For example:
6880 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1)
6881 // i32 y = TRUNCATE(i64 x)
6883 // v16i8 b = BITCAST (v2i64 val)
6884 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8)
6886 // Note: We only run this optimization after type legalization (which often
6887 // creates this pattern) and before operation legalization after which
6888 // we need to be more careful about the vector instructions that we generate.
6889 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
6890 LegalTypes && !LegalOperations && N0->hasOneUse() && VT != MVT::i1) {
6892 EVT VecTy = N0.getOperand(0).getValueType();
6893 EVT ExTy = N0.getValueType();
6894 EVT TrTy = N->getValueType(0);
6896 unsigned NumElem = VecTy.getVectorNumElements();
6897 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits();
6899 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem);
6900 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
6902 SDValue EltNo = N0->getOperand(1);
6903 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
6904 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6905 EVT IndexTy = TLI.getVectorIdxTy(DAG.getDataLayout());
6906 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
6908 SDValue V = DAG.getNode(ISD::BITCAST, SDLoc(N),
6909 NVT, N0.getOperand(0));
6912 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
6914 DAG.getConstant(Index, DL, IndexTy));
6918 // trunc (select c, a, b) -> select c, (trunc a), (trunc b)
6919 if (N0.getOpcode() == ISD::SELECT) {
6920 EVT SrcVT = N0.getValueType();
6921 if ((!LegalOperations || TLI.isOperationLegal(ISD::SELECT, SrcVT)) &&
6922 TLI.isTruncateFree(SrcVT, VT)) {
6924 SDValue Cond = N0.getOperand(0);
6925 SDValue TruncOp0 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(1));
6926 SDValue TruncOp1 = DAG.getNode(ISD::TRUNCATE, SL, VT, N0.getOperand(2));
6927 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, Cond, TruncOp0, TruncOp1);
6931 // Fold a series of buildvector, bitcast, and truncate if possible.
6933 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to
6934 // (2xi32 (buildvector x, y)).
6935 if (Level == AfterLegalizeVectorOps && VT.isVector() &&
6936 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
6937 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
6938 N0.getOperand(0).hasOneUse()) {
6940 SDValue BuildVect = N0.getOperand(0);
6941 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType();
6942 EVT TruncVecEltTy = VT.getVectorElementType();
6944 // Check that the element types match.
6945 if (BuildVectEltTy == TruncVecEltTy) {
6946 // Now we only need to compute the offset of the truncated elements.
6947 unsigned BuildVecNumElts = BuildVect.getNumOperands();
6948 unsigned TruncVecNumElts = VT.getVectorNumElements();
6949 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts;
6951 assert((BuildVecNumElts % TruncVecNumElts) == 0 &&
6952 "Invalid number of elements");
6954 SmallVector<SDValue, 8> Opnds;
6955 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset)
6956 Opnds.push_back(BuildVect.getOperand(i));
6958 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
6962 // See if we can simplify the input to this truncate through knowledge that
6963 // only the low bits are being used.
6964 // For example "trunc (or (shl x, 8), y)" // -> trunc y
6965 // Currently we only perform this optimization on scalars because vectors
6966 // may have different active low bits.
6967 if (!VT.isVector()) {
6969 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
6970 VT.getSizeInBits()));
6971 if (Shorter.getNode())
6972 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter);
6974 // fold (truncate (load x)) -> (smaller load x)
6975 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
6976 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
6977 if (SDValue Reduced = ReduceLoadWidth(N))
6980 // Handle the case where the load remains an extending load even
6981 // after truncation.
6982 if (N0.hasOneUse() && ISD::isUNINDEXEDLoad(N0.getNode())) {
6983 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
6984 if (!LN0->isVolatile() &&
6985 LN0->getMemoryVT().getStoreSizeInBits() < VT.getSizeInBits()) {
6986 SDValue NewLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(LN0),
6987 VT, LN0->getChain(), LN0->getBasePtr(),
6989 LN0->getMemOperand());
6990 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLoad.getValue(1));
6995 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)),
6996 // where ... are all 'undef'.
6997 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) {
6998 SmallVector<EVT, 8> VTs;
7001 unsigned NumDefs = 0;
7003 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) {
7004 SDValue X = N0.getOperand(i);
7005 if (X.getOpcode() != ISD::UNDEF) {
7010 // Stop if more than one members are non-undef.
7013 VTs.push_back(EVT::getVectorVT(*DAG.getContext(),
7014 VT.getVectorElementType(),
7015 X.getValueType().getVectorNumElements()));
7019 return DAG.getUNDEF(VT);
7022 assert(V.getNode() && "The single defined operand is empty!");
7023 SmallVector<SDValue, 8> Opnds;
7024 for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
7026 Opnds.push_back(DAG.getUNDEF(VTs[i]));
7029 SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V);
7030 AddToWorklist(NV.getNode());
7031 Opnds.push_back(NV);
7033 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Opnds);
7037 // Simplify the operands using demanded-bits information.
7038 if (!VT.isVector() &&
7039 SimplifyDemandedBits(SDValue(N, 0)))
7040 return SDValue(N, 0);
7045 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
7046 SDValue Elt = N->getOperand(i);
7047 if (Elt.getOpcode() != ISD::MERGE_VALUES)
7048 return Elt.getNode();
7049 return Elt.getOperand(Elt.getResNo()).getNode();
7052 /// build_pair (load, load) -> load
7053 /// if load locations are consecutive.
7054 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
7055 assert(N->getOpcode() == ISD::BUILD_PAIR);
7057 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
7058 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
7059 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
7060 LD1->getAddressSpace() != LD2->getAddressSpace())
7062 EVT LD1VT = LD1->getValueType(0);
7064 if (ISD::isNON_EXTLoad(LD2) &&
7066 // If both are volatile this would reduce the number of volatile loads.
7067 // If one is volatile it might be ok, but play conservative and bail out.
7068 !LD1->isVolatile() &&
7069 !LD2->isVolatile() &&
7070 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
7071 unsigned Align = LD1->getAlignment();
7072 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
7073 VT.getTypeForEVT(*DAG.getContext()));
7075 if (NewAlign <= Align &&
7076 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
7077 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(),
7078 LD1->getBasePtr(), LD1->getPointerInfo(),
7079 false, false, false, Align);
7085 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
7086 SDValue N0 = N->getOperand(0);
7087 EVT VT = N->getValueType(0);
7089 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
7090 // Only do this before legalize, since afterward the target may be depending
7091 // on the bitconvert.
7092 // First check to see if this is all constant.
7094 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
7096 bool isSimple = cast<BuildVectorSDNode>(N0)->isConstant();
7098 EVT DestEltVT = N->getValueType(0).getVectorElementType();
7099 assert(!DestEltVT.isVector() &&
7100 "Element type of vector ValueType must not be vector!");
7102 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
7105 // If the input is a constant, let getNode fold it.
7106 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
7107 // If we can't allow illegal operations, we need to check that this is just
7108 // a fp -> int or int -> conversion and that the resulting operation will
7110 if (!LegalOperations ||
7111 (isa<ConstantSDNode>(N0) && VT.isFloatingPoint() && !VT.isVector() &&
7112 TLI.isOperationLegal(ISD::ConstantFP, VT)) ||
7113 (isa<ConstantFPSDNode>(N0) && VT.isInteger() && !VT.isVector() &&
7114 TLI.isOperationLegal(ISD::Constant, VT)))
7115 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0);
7118 // (conv (conv x, t1), t2) -> (conv x, t2)
7119 if (N0.getOpcode() == ISD::BITCAST)
7120 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT,
7123 // fold (conv (load x)) -> (load (conv*)x)
7124 // If the resultant load doesn't need a higher alignment than the original!
7125 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
7126 // Do not change the width of a volatile load.
7127 !cast<LoadSDNode>(N0)->isVolatile() &&
7128 // Do not remove the cast if the types differ in endian layout.
7129 TLI.hasBigEndianPartOrdering(N0.getValueType(), DAG.getDataLayout()) ==
7130 TLI.hasBigEndianPartOrdering(VT, DAG.getDataLayout()) &&
7131 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)) &&
7132 TLI.isLoadBitCastBeneficial(N0.getValueType(), VT)) {
7133 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
7134 unsigned Align = DAG.getDataLayout().getABITypeAlignment(
7135 VT.getTypeForEVT(*DAG.getContext()));
7136 unsigned OrigAlign = LN0->getAlignment();
7138 if (Align <= OrigAlign) {
7139 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(),
7140 LN0->getBasePtr(), LN0->getPointerInfo(),
7141 LN0->isVolatile(), LN0->isNonTemporal(),
7142 LN0->isInvariant(), OrigAlign,
7144 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1));
7149 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
7150 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
7151 // This often reduces constant pool loads.
7152 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(N0.getValueType())) ||
7153 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(N0.getValueType()))) &&
7154 N0.getNode()->hasOneUse() && VT.isInteger() &&
7155 !VT.isVector() && !N0.getValueType().isVector()) {
7156 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT,
7158 AddToWorklist(NewConv.getNode());
7161 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
7162 if (N0.getOpcode() == ISD::FNEG)
7163 return DAG.getNode(ISD::XOR, DL, VT,
7164 NewConv, DAG.getConstant(SignBit, DL, VT));
7165 assert(N0.getOpcode() == ISD::FABS);
7166 return DAG.getNode(ISD::AND, DL, VT,
7167 NewConv, DAG.getConstant(~SignBit, DL, VT));
7170 // fold (bitconvert (fcopysign cst, x)) ->
7171 // (or (and (bitconvert x), sign), (and cst, (not sign)))
7172 // Note that we don't handle (copysign x, cst) because this can always be
7173 // folded to an fneg or fabs.
7174 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
7175 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
7176 VT.isInteger() && !VT.isVector()) {
7177 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
7178 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
7179 if (isTypeLegal(IntXVT)) {
7180 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0),
7181 IntXVT, N0.getOperand(1));
7182 AddToWorklist(X.getNode());
7184 // If X has a different width than the result/lhs, sext it or truncate it.
7185 unsigned VTWidth = VT.getSizeInBits();
7186 if (OrigXWidth < VTWidth) {
7187 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X);
7188 AddToWorklist(X.getNode());
7189 } else if (OrigXWidth > VTWidth) {
7190 // To get the sign bit in the right place, we have to shift it right
7191 // before truncating.
7193 X = DAG.getNode(ISD::SRL, DL,
7194 X.getValueType(), X,
7195 DAG.getConstant(OrigXWidth-VTWidth, DL,
7197 AddToWorklist(X.getNode());
7198 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
7199 AddToWorklist(X.getNode());
7202 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
7203 X = DAG.getNode(ISD::AND, SDLoc(X), VT,
7204 X, DAG.getConstant(SignBit, SDLoc(X), VT));
7205 AddToWorklist(X.getNode());
7207 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0),
7208 VT, N0.getOperand(0));
7209 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT,
7210 Cst, DAG.getConstant(~SignBit, SDLoc(Cst), VT));
7211 AddToWorklist(Cst.getNode());
7213 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst);
7217 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
7218 if (N0.getOpcode() == ISD::BUILD_PAIR)
7219 if (SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT))
7222 // Remove double bitcasts from shuffles - this is often a legacy of
7223 // XformToShuffleWithZero being used to combine bitmaskings (of
7224 // float vectors bitcast to integer vectors) into shuffles.
7225 // bitcast(shuffle(bitcast(s0),bitcast(s1))) -> shuffle(s0,s1)
7226 if (Level < AfterLegalizeDAG && TLI.isTypeLegal(VT) && VT.isVector() &&
7227 N0->getOpcode() == ISD::VECTOR_SHUFFLE &&
7228 VT.getVectorNumElements() >= N0.getValueType().getVectorNumElements() &&
7229 !(VT.getVectorNumElements() % N0.getValueType().getVectorNumElements())) {
7230 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N0);
7232 // If operands are a bitcast, peek through if it casts the original VT.
7233 // If operands are a constant, just bitcast back to original VT.
7234 auto PeekThroughBitcast = [&](SDValue Op) {
7235 if (Op.getOpcode() == ISD::BITCAST &&
7236 Op.getOperand(0).getValueType() == VT)
7237 return SDValue(Op.getOperand(0));
7238 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) ||
7239 ISD::isBuildVectorOfConstantFPSDNodes(Op.getNode()))
7240 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
7244 SDValue SV0 = PeekThroughBitcast(N0->getOperand(0));
7245 SDValue SV1 = PeekThroughBitcast(N0->getOperand(1));
7250 VT.getVectorNumElements() / N0.getValueType().getVectorNumElements();
7251 SmallVector<int, 8> NewMask;
7252 for (int M : SVN->getMask())
7253 for (int i = 0; i != MaskScale; ++i)
7254 NewMask.push_back(M < 0 ? -1 : M * MaskScale + i);
7256 bool LegalMask = TLI.isShuffleMaskLegal(NewMask, VT);
7258 std::swap(SV0, SV1);
7259 ShuffleVectorSDNode::commuteMask(NewMask);
7260 LegalMask = TLI.isShuffleMaskLegal(NewMask, VT);
7264 return DAG.getVectorShuffle(VT, SDLoc(N), SV0, SV1, NewMask);
7270 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
7271 EVT VT = N->getValueType(0);
7272 return CombineConsecutiveLoads(N, VT);
7275 /// We know that BV is a build_vector node with Constant, ConstantFP or Undef
7276 /// operands. DstEltVT indicates the destination element value type.
7277 SDValue DAGCombiner::
7278 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
7279 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
7281 // If this is already the right type, we're done.
7282 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
7284 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
7285 unsigned DstBitSize = DstEltVT.getSizeInBits();
7287 // If this is a conversion of N elements of one type to N elements of another
7288 // type, convert each element. This handles FP<->INT cases.
7289 if (SrcBitSize == DstBitSize) {
7290 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
7291 BV->getValueType(0).getVectorNumElements());
7293 // Due to the FP element handling below calling this routine recursively,
7294 // we can end up with a scalar-to-vector node here.
7295 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
7296 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT,
7297 DAG.getNode(ISD::BITCAST, SDLoc(BV),
7298 DstEltVT, BV->getOperand(0)));
7300 SmallVector<SDValue, 8> Ops;
7301 for (SDValue Op : BV->op_values()) {
7302 // If the vector element type is not legal, the BUILD_VECTOR operands
7303 // are promoted and implicitly truncated. Make that explicit here.
7304 if (Op.getValueType() != SrcEltVT)
7305 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op);
7306 Ops.push_back(DAG.getNode(ISD::BITCAST, SDLoc(BV),
7308 AddToWorklist(Ops.back().getNode());
7310 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, Ops);
7313 // Otherwise, we're growing or shrinking the elements. To avoid having to
7314 // handle annoying details of growing/shrinking FP values, we convert them to
7316 if (SrcEltVT.isFloatingPoint()) {
7317 // Convert the input float vector to a int vector where the elements are the
7319 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
7320 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
7324 // Now we know the input is an integer vector. If the output is a FP type,
7325 // convert to integer first, then to FP of the right size.
7326 if (DstEltVT.isFloatingPoint()) {
7327 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
7328 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
7330 // Next, convert to FP elements of the same size.
7331 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
7336 // Okay, we know the src/dst types are both integers of differing types.
7337 // Handling growing first.
7338 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
7339 if (SrcBitSize < DstBitSize) {
7340 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
7342 SmallVector<SDValue, 8> Ops;
7343 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
7344 i += NumInputsPerOutput) {
7345 bool isLE = DAG.getDataLayout().isLittleEndian();
7346 APInt NewBits = APInt(DstBitSize, 0);
7347 bool EltIsUndef = true;
7348 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
7349 // Shift the previously computed bits over.
7350 NewBits <<= SrcBitSize;
7351 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
7352 if (Op.getOpcode() == ISD::UNDEF) continue;
7355 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
7356 zextOrTrunc(SrcBitSize).zext(DstBitSize);
7360 Ops.push_back(DAG.getUNDEF(DstEltVT));
7362 Ops.push_back(DAG.getConstant(NewBits, DL, DstEltVT));
7365 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
7366 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
7369 // Finally, this must be the case where we are shrinking elements: each input
7370 // turns into multiple outputs.
7371 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
7372 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
7373 NumOutputsPerInput*BV->getNumOperands());
7374 SmallVector<SDValue, 8> Ops;
7376 for (const SDValue &Op : BV->op_values()) {
7377 if (Op.getOpcode() == ISD::UNDEF) {
7378 Ops.append(NumOutputsPerInput, DAG.getUNDEF(DstEltVT));
7382 APInt OpVal = cast<ConstantSDNode>(Op)->
7383 getAPIntValue().zextOrTrunc(SrcBitSize);
7385 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
7386 APInt ThisVal = OpVal.trunc(DstBitSize);
7387 Ops.push_back(DAG.getConstant(ThisVal, DL, DstEltVT));
7388 OpVal = OpVal.lshr(DstBitSize);
7391 // For big endian targets, swap the order of the pieces of each element.
7392 if (DAG.getDataLayout().isBigEndian())
7393 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
7396 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
7399 /// Try to perform FMA combining on a given FADD node.
7400 SDValue DAGCombiner::visitFADDForFMACombine(SDNode *N) {
7401 SDValue N0 = N->getOperand(0);
7402 SDValue N1 = N->getOperand(1);
7403 EVT VT = N->getValueType(0);
7406 const TargetOptions &Options = DAG.getTarget().Options;
7407 bool UnsafeFPMath = (Options.AllowFPOpFusion == FPOpFusion::Fast ||
7408 Options.UnsafeFPMath);
7410 // Floating-point multiply-add with intermediate rounding.
7411 bool HasFMAD = (LegalOperations &&
7412 TLI.isOperationLegal(ISD::FMAD, VT));
7414 // Floating-point multiply-add without intermediate rounding.
7415 bool HasFMA = ((!LegalOperations ||
7416 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) &&
7417 TLI.isFMAFasterThanFMulAndFAdd(VT) &&
7420 // No valid opcode, do not combine.
7421 if (!HasFMAD && !HasFMA)
7424 // Always prefer FMAD to FMA for precision.
7425 unsigned int PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
7426 bool Aggressive = TLI.enableAggressiveFMAFusion(VT);
7427 bool LookThroughFPExt = TLI.isFPExtFree(VT);
7429 // fold (fadd (fmul x, y), z) -> (fma x, y, z)
7430 if (N0.getOpcode() == ISD::FMUL &&
7431 (Aggressive || N0->hasOneUse())) {
7432 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7433 N0.getOperand(0), N0.getOperand(1), N1);
7436 // fold (fadd x, (fmul y, z)) -> (fma y, z, x)
7437 // Note: Commutes FADD operands.
7438 if (N1.getOpcode() == ISD::FMUL &&
7439 (Aggressive || N1->hasOneUse())) {
7440 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7441 N1.getOperand(0), N1.getOperand(1), N0);
7444 // Look through FP_EXTEND nodes to do more combining.
7445 if (UnsafeFPMath && LookThroughFPExt) {
7446 // fold (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
7447 if (N0.getOpcode() == ISD::FP_EXTEND) {
7448 SDValue N00 = N0.getOperand(0);
7449 if (N00.getOpcode() == ISD::FMUL)
7450 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7451 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7453 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7454 N00.getOperand(1)), N1);
7457 // fold (fadd x, (fpext (fmul y, z))) -> (fma (fpext y), (fpext z), x)
7458 // Note: Commutes FADD operands.
7459 if (N1.getOpcode() == ISD::FP_EXTEND) {
7460 SDValue N10 = N1.getOperand(0);
7461 if (N10.getOpcode() == ISD::FMUL)
7462 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7463 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7465 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7466 N10.getOperand(1)), N0);
7470 // More folding opportunities when target permits.
7471 if ((UnsafeFPMath || HasFMAD) && Aggressive) {
7472 // fold (fadd (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, z))
7473 if (N0.getOpcode() == PreferredFusedOpcode &&
7474 N0.getOperand(2).getOpcode() == ISD::FMUL) {
7475 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7476 N0.getOperand(0), N0.getOperand(1),
7477 DAG.getNode(PreferredFusedOpcode, SL, VT,
7478 N0.getOperand(2).getOperand(0),
7479 N0.getOperand(2).getOperand(1),
7483 // fold (fadd x, (fma y, z, (fmul u, v)) -> (fma y, z (fma u, v, x))
7484 if (N1->getOpcode() == PreferredFusedOpcode &&
7485 N1.getOperand(2).getOpcode() == ISD::FMUL) {
7486 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7487 N1.getOperand(0), N1.getOperand(1),
7488 DAG.getNode(PreferredFusedOpcode, SL, VT,
7489 N1.getOperand(2).getOperand(0),
7490 N1.getOperand(2).getOperand(1),
7494 if (UnsafeFPMath && LookThroughFPExt) {
7495 // fold (fadd (fma x, y, (fpext (fmul u, v))), z)
7496 // -> (fma x, y, (fma (fpext u), (fpext v), z))
7497 auto FoldFAddFMAFPExtFMul = [&] (
7498 SDValue X, SDValue Y, SDValue U, SDValue V, SDValue Z) {
7499 return DAG.getNode(PreferredFusedOpcode, SL, VT, X, Y,
7500 DAG.getNode(PreferredFusedOpcode, SL, VT,
7501 DAG.getNode(ISD::FP_EXTEND, SL, VT, U),
7502 DAG.getNode(ISD::FP_EXTEND, SL, VT, V),
7505 if (N0.getOpcode() == PreferredFusedOpcode) {
7506 SDValue N02 = N0.getOperand(2);
7507 if (N02.getOpcode() == ISD::FP_EXTEND) {
7508 SDValue N020 = N02.getOperand(0);
7509 if (N020.getOpcode() == ISD::FMUL)
7510 return FoldFAddFMAFPExtFMul(N0.getOperand(0), N0.getOperand(1),
7511 N020.getOperand(0), N020.getOperand(1),
7516 // fold (fadd (fpext (fma x, y, (fmul u, v))), z)
7517 // -> (fma (fpext x), (fpext y), (fma (fpext u), (fpext v), z))
7518 // FIXME: This turns two single-precision and one double-precision
7519 // operation into two double-precision operations, which might not be
7520 // interesting for all targets, especially GPUs.
7521 auto FoldFAddFPExtFMAFMul = [&] (
7522 SDValue X, SDValue Y, SDValue U, SDValue V, SDValue Z) {
7523 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7524 DAG.getNode(ISD::FP_EXTEND, SL, VT, X),
7525 DAG.getNode(ISD::FP_EXTEND, SL, VT, Y),
7526 DAG.getNode(PreferredFusedOpcode, SL, VT,
7527 DAG.getNode(ISD::FP_EXTEND, SL, VT, U),
7528 DAG.getNode(ISD::FP_EXTEND, SL, VT, V),
7531 if (N0.getOpcode() == ISD::FP_EXTEND) {
7532 SDValue N00 = N0.getOperand(0);
7533 if (N00.getOpcode() == PreferredFusedOpcode) {
7534 SDValue N002 = N00.getOperand(2);
7535 if (N002.getOpcode() == ISD::FMUL)
7536 return FoldFAddFPExtFMAFMul(N00.getOperand(0), N00.getOperand(1),
7537 N002.getOperand(0), N002.getOperand(1),
7542 // fold (fadd x, (fma y, z, (fpext (fmul u, v)))
7543 // -> (fma y, z, (fma (fpext u), (fpext v), x))
7544 if (N1.getOpcode() == PreferredFusedOpcode) {
7545 SDValue N12 = N1.getOperand(2);
7546 if (N12.getOpcode() == ISD::FP_EXTEND) {
7547 SDValue N120 = N12.getOperand(0);
7548 if (N120.getOpcode() == ISD::FMUL)
7549 return FoldFAddFMAFPExtFMul(N1.getOperand(0), N1.getOperand(1),
7550 N120.getOperand(0), N120.getOperand(1),
7555 // fold (fadd x, (fpext (fma y, z, (fmul u, v)))
7556 // -> (fma (fpext y), (fpext z), (fma (fpext u), (fpext v), x))
7557 // FIXME: This turns two single-precision and one double-precision
7558 // operation into two double-precision operations, which might not be
7559 // interesting for all targets, especially GPUs.
7560 if (N1.getOpcode() == ISD::FP_EXTEND) {
7561 SDValue N10 = N1.getOperand(0);
7562 if (N10.getOpcode() == PreferredFusedOpcode) {
7563 SDValue N102 = N10.getOperand(2);
7564 if (N102.getOpcode() == ISD::FMUL)
7565 return FoldFAddFPExtFMAFMul(N10.getOperand(0), N10.getOperand(1),
7566 N102.getOperand(0), N102.getOperand(1),
7576 /// Try to perform FMA combining on a given FSUB node.
7577 SDValue DAGCombiner::visitFSUBForFMACombine(SDNode *N) {
7578 SDValue N0 = N->getOperand(0);
7579 SDValue N1 = N->getOperand(1);
7580 EVT VT = N->getValueType(0);
7583 const TargetOptions &Options = DAG.getTarget().Options;
7584 bool UnsafeFPMath = (Options.AllowFPOpFusion == FPOpFusion::Fast ||
7585 Options.UnsafeFPMath);
7587 // Floating-point multiply-add with intermediate rounding.
7588 bool HasFMAD = (LegalOperations &&
7589 TLI.isOperationLegal(ISD::FMAD, VT));
7591 // Floating-point multiply-add without intermediate rounding.
7592 bool HasFMA = ((!LegalOperations ||
7593 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) &&
7594 TLI.isFMAFasterThanFMulAndFAdd(VT) &&
7597 // No valid opcode, do not combine.
7598 if (!HasFMAD && !HasFMA)
7601 // Always prefer FMAD to FMA for precision.
7602 unsigned int PreferredFusedOpcode = HasFMAD ? ISD::FMAD : ISD::FMA;
7603 bool Aggressive = TLI.enableAggressiveFMAFusion(VT);
7604 bool LookThroughFPExt = TLI.isFPExtFree(VT);
7606 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
7607 if (N0.getOpcode() == ISD::FMUL &&
7608 (Aggressive || N0->hasOneUse())) {
7609 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7610 N0.getOperand(0), N0.getOperand(1),
7611 DAG.getNode(ISD::FNEG, SL, VT, N1));
7614 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
7615 // Note: Commutes FSUB operands.
7616 if (N1.getOpcode() == ISD::FMUL &&
7617 (Aggressive || N1->hasOneUse()))
7618 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7619 DAG.getNode(ISD::FNEG, SL, VT,
7621 N1.getOperand(1), N0);
7623 // fold (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
7624 if (N0.getOpcode() == ISD::FNEG &&
7625 N0.getOperand(0).getOpcode() == ISD::FMUL &&
7626 (Aggressive || (N0->hasOneUse() && N0.getOperand(0).hasOneUse()))) {
7627 SDValue N00 = N0.getOperand(0).getOperand(0);
7628 SDValue N01 = N0.getOperand(0).getOperand(1);
7629 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7630 DAG.getNode(ISD::FNEG, SL, VT, N00), N01,
7631 DAG.getNode(ISD::FNEG, SL, VT, N1));
7634 // Look through FP_EXTEND nodes to do more combining.
7635 if (UnsafeFPMath && LookThroughFPExt) {
7636 // fold (fsub (fpext (fmul x, y)), z)
7637 // -> (fma (fpext x), (fpext y), (fneg z))
7638 if (N0.getOpcode() == ISD::FP_EXTEND) {
7639 SDValue N00 = N0.getOperand(0);
7640 if (N00.getOpcode() == ISD::FMUL)
7641 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7642 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7644 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7646 DAG.getNode(ISD::FNEG, SL, VT, N1));
7649 // fold (fsub x, (fpext (fmul y, z)))
7650 // -> (fma (fneg (fpext y)), (fpext z), x)
7651 // Note: Commutes FSUB operands.
7652 if (N1.getOpcode() == ISD::FP_EXTEND) {
7653 SDValue N10 = N1.getOperand(0);
7654 if (N10.getOpcode() == ISD::FMUL)
7655 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7656 DAG.getNode(ISD::FNEG, SL, VT,
7657 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7658 N10.getOperand(0))),
7659 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7664 // fold (fsub (fpext (fneg (fmul, x, y))), z)
7665 // -> (fneg (fma (fpext x), (fpext y), z))
7666 // Note: This could be removed with appropriate canonicalization of the
7667 // input expression into (fneg (fadd (fpext (fmul, x, y)), z). However, the
7668 // orthogonal flags -fp-contract=fast and -enable-unsafe-fp-math prevent
7669 // from implementing the canonicalization in visitFSUB.
7670 if (N0.getOpcode() == ISD::FP_EXTEND) {
7671 SDValue N00 = N0.getOperand(0);
7672 if (N00.getOpcode() == ISD::FNEG) {
7673 SDValue N000 = N00.getOperand(0);
7674 if (N000.getOpcode() == ISD::FMUL) {
7675 return DAG.getNode(ISD::FNEG, SL, VT,
7676 DAG.getNode(PreferredFusedOpcode, SL, VT,
7677 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7678 N000.getOperand(0)),
7679 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7680 N000.getOperand(1)),
7686 // fold (fsub (fneg (fpext (fmul, x, y))), z)
7687 // -> (fneg (fma (fpext x)), (fpext y), z)
7688 // Note: This could be removed with appropriate canonicalization of the
7689 // input expression into (fneg (fadd (fpext (fmul, x, y)), z). However, the
7690 // orthogonal flags -fp-contract=fast and -enable-unsafe-fp-math prevent
7691 // from implementing the canonicalization in visitFSUB.
7692 if (N0.getOpcode() == ISD::FNEG) {
7693 SDValue N00 = N0.getOperand(0);
7694 if (N00.getOpcode() == ISD::FP_EXTEND) {
7695 SDValue N000 = N00.getOperand(0);
7696 if (N000.getOpcode() == ISD::FMUL) {
7697 return DAG.getNode(ISD::FNEG, SL, VT,
7698 DAG.getNode(PreferredFusedOpcode, SL, VT,
7699 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7700 N000.getOperand(0)),
7701 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7702 N000.getOperand(1)),
7710 // More folding opportunities when target permits.
7711 if ((UnsafeFPMath || HasFMAD) && Aggressive) {
7712 // fold (fsub (fma x, y, (fmul u, v)), z)
7713 // -> (fma x, y (fma u, v, (fneg z)))
7714 if (N0.getOpcode() == PreferredFusedOpcode &&
7715 N0.getOperand(2).getOpcode() == ISD::FMUL) {
7716 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7717 N0.getOperand(0), N0.getOperand(1),
7718 DAG.getNode(PreferredFusedOpcode, SL, VT,
7719 N0.getOperand(2).getOperand(0),
7720 N0.getOperand(2).getOperand(1),
7721 DAG.getNode(ISD::FNEG, SL, VT,
7725 // fold (fsub x, (fma y, z, (fmul u, v)))
7726 // -> (fma (fneg y), z, (fma (fneg u), v, x))
7727 if (N1.getOpcode() == PreferredFusedOpcode &&
7728 N1.getOperand(2).getOpcode() == ISD::FMUL) {
7729 SDValue N20 = N1.getOperand(2).getOperand(0);
7730 SDValue N21 = N1.getOperand(2).getOperand(1);
7731 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7732 DAG.getNode(ISD::FNEG, SL, VT,
7735 DAG.getNode(PreferredFusedOpcode, SL, VT,
7736 DAG.getNode(ISD::FNEG, SL, VT, N20),
7741 if (UnsafeFPMath && LookThroughFPExt) {
7742 // fold (fsub (fma x, y, (fpext (fmul u, v))), z)
7743 // -> (fma x, y (fma (fpext u), (fpext v), (fneg z)))
7744 if (N0.getOpcode() == PreferredFusedOpcode) {
7745 SDValue N02 = N0.getOperand(2);
7746 if (N02.getOpcode() == ISD::FP_EXTEND) {
7747 SDValue N020 = N02.getOperand(0);
7748 if (N020.getOpcode() == ISD::FMUL)
7749 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7750 N0.getOperand(0), N0.getOperand(1),
7751 DAG.getNode(PreferredFusedOpcode, SL, VT,
7752 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7753 N020.getOperand(0)),
7754 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7755 N020.getOperand(1)),
7756 DAG.getNode(ISD::FNEG, SL, VT,
7761 // fold (fsub (fpext (fma x, y, (fmul u, v))), z)
7762 // -> (fma (fpext x), (fpext y),
7763 // (fma (fpext u), (fpext v), (fneg z)))
7764 // FIXME: This turns two single-precision and one double-precision
7765 // operation into two double-precision operations, which might not be
7766 // interesting for all targets, especially GPUs.
7767 if (N0.getOpcode() == ISD::FP_EXTEND) {
7768 SDValue N00 = N0.getOperand(0);
7769 if (N00.getOpcode() == PreferredFusedOpcode) {
7770 SDValue N002 = N00.getOperand(2);
7771 if (N002.getOpcode() == ISD::FMUL)
7772 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7773 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7775 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7777 DAG.getNode(PreferredFusedOpcode, SL, VT,
7778 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7779 N002.getOperand(0)),
7780 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7781 N002.getOperand(1)),
7782 DAG.getNode(ISD::FNEG, SL, VT,
7787 // fold (fsub x, (fma y, z, (fpext (fmul u, v))))
7788 // -> (fma (fneg y), z, (fma (fneg (fpext u)), (fpext v), x))
7789 if (N1.getOpcode() == PreferredFusedOpcode &&
7790 N1.getOperand(2).getOpcode() == ISD::FP_EXTEND) {
7791 SDValue N120 = N1.getOperand(2).getOperand(0);
7792 if (N120.getOpcode() == ISD::FMUL) {
7793 SDValue N1200 = N120.getOperand(0);
7794 SDValue N1201 = N120.getOperand(1);
7795 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7796 DAG.getNode(ISD::FNEG, SL, VT, N1.getOperand(0)),
7798 DAG.getNode(PreferredFusedOpcode, SL, VT,
7799 DAG.getNode(ISD::FNEG, SL, VT,
7800 DAG.getNode(ISD::FP_EXTEND, SL,
7802 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7808 // fold (fsub x, (fpext (fma y, z, (fmul u, v))))
7809 // -> (fma (fneg (fpext y)), (fpext z),
7810 // (fma (fneg (fpext u)), (fpext v), x))
7811 // FIXME: This turns two single-precision and one double-precision
7812 // operation into two double-precision operations, which might not be
7813 // interesting for all targets, especially GPUs.
7814 if (N1.getOpcode() == ISD::FP_EXTEND &&
7815 N1.getOperand(0).getOpcode() == PreferredFusedOpcode) {
7816 SDValue N100 = N1.getOperand(0).getOperand(0);
7817 SDValue N101 = N1.getOperand(0).getOperand(1);
7818 SDValue N102 = N1.getOperand(0).getOperand(2);
7819 if (N102.getOpcode() == ISD::FMUL) {
7820 SDValue N1020 = N102.getOperand(0);
7821 SDValue N1021 = N102.getOperand(1);
7822 return DAG.getNode(PreferredFusedOpcode, SL, VT,
7823 DAG.getNode(ISD::FNEG, SL, VT,
7824 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7826 DAG.getNode(ISD::FP_EXTEND, SL, VT, N101),
7827 DAG.getNode(PreferredFusedOpcode, SL, VT,
7828 DAG.getNode(ISD::FNEG, SL, VT,
7829 DAG.getNode(ISD::FP_EXTEND, SL,
7831 DAG.getNode(ISD::FP_EXTEND, SL, VT,
7842 SDValue DAGCombiner::visitFADD(SDNode *N) {
7843 SDValue N0 = N->getOperand(0);
7844 SDValue N1 = N->getOperand(1);
7845 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
7846 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
7847 EVT VT = N->getValueType(0);
7849 const TargetOptions &Options = DAG.getTarget().Options;
7853 if (SDValue FoldedVOp = SimplifyVBinOp(N))
7856 // fold (fadd c1, c2) -> c1 + c2
7858 return DAG.getNode(ISD::FADD, DL, VT, N0, N1);
7860 // canonicalize constant to RHS
7861 if (N0CFP && !N1CFP)
7862 return DAG.getNode(ISD::FADD, DL, VT, N1, N0);
7864 // fold (fadd A, (fneg B)) -> (fsub A, B)
7865 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
7866 isNegatibleForFree(N1, LegalOperations, TLI, &Options) == 2)
7867 return DAG.getNode(ISD::FSUB, DL, VT, N0,
7868 GetNegatedExpression(N1, DAG, LegalOperations));
7870 // fold (fadd (fneg A), B) -> (fsub B, A)
7871 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) &&
7872 isNegatibleForFree(N0, LegalOperations, TLI, &Options) == 2)
7873 return DAG.getNode(ISD::FSUB, DL, VT, N1,
7874 GetNegatedExpression(N0, DAG, LegalOperations));
7876 // If 'unsafe math' is enabled, fold lots of things.
7877 if (Options.UnsafeFPMath) {
7878 // No FP constant should be created after legalization as Instruction
7879 // Selection pass has a hard time dealing with FP constants.
7880 bool AllowNewConst = (Level < AfterLegalizeDAG);
7882 // fold (fadd A, 0) -> A
7883 if (N1CFP && N1CFP->isZero())
7886 // fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
7887 if (N1CFP && N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() &&
7888 isa<ConstantFPSDNode>(N0.getOperand(1)))
7889 return DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(0),
7890 DAG.getNode(ISD::FADD, DL, VT, N0.getOperand(1), N1));
7892 // If allowed, fold (fadd (fneg x), x) -> 0.0
7893 if (AllowNewConst && N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1)
7894 return DAG.getConstantFP(0.0, DL, VT);
7896 // If allowed, fold (fadd x, (fneg x)) -> 0.0
7897 if (AllowNewConst && N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0)
7898 return DAG.getConstantFP(0.0, DL, VT);
7900 // We can fold chains of FADD's of the same value into multiplications.
7901 // This transform is not safe in general because we are reducing the number
7902 // of rounding steps.
7903 if (TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && !N0CFP && !N1CFP) {
7904 if (N0.getOpcode() == ISD::FMUL) {
7905 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
7906 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
7908 // (fadd (fmul x, c), x) -> (fmul x, c+1)
7909 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) {
7910 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, SDValue(CFP01, 0),
7911 DAG.getConstantFP(1.0, DL, VT));
7912 return DAG.getNode(ISD::FMUL, DL, VT, N1, NewCFP);
7915 // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2)
7916 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD &&
7917 N1.getOperand(0) == N1.getOperand(1) &&
7918 N0.getOperand(0) == N1.getOperand(0)) {
7919 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, SDValue(CFP01, 0),
7920 DAG.getConstantFP(2.0, DL, VT));
7921 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), NewCFP);
7925 if (N1.getOpcode() == ISD::FMUL) {
7926 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
7927 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1));
7929 // (fadd x, (fmul x, c)) -> (fmul x, c+1)
7930 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) {
7931 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, SDValue(CFP11, 0),
7932 DAG.getConstantFP(1.0, DL, VT));
7933 return DAG.getNode(ISD::FMUL, DL, VT, N0, NewCFP);
7936 // (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2)
7937 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD &&
7938 N0.getOperand(0) == N0.getOperand(1) &&
7939 N1.getOperand(0) == N0.getOperand(0)) {
7940 SDValue NewCFP = DAG.getNode(ISD::FADD, DL, VT, SDValue(CFP11, 0),
7941 DAG.getConstantFP(2.0, DL, VT));
7942 return DAG.getNode(ISD::FMUL, DL, VT, N1.getOperand(0), NewCFP);
7946 if (N0.getOpcode() == ISD::FADD && AllowNewConst) {
7947 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0));
7948 // (fadd (fadd x, x), x) -> (fmul x, 3.0)
7949 if (!CFP && N0.getOperand(0) == N0.getOperand(1) &&
7950 (N0.getOperand(0) == N1)) {
7951 return DAG.getNode(ISD::FMUL, DL, VT,
7952 N1, DAG.getConstantFP(3.0, DL, VT));
7956 if (N1.getOpcode() == ISD::FADD && AllowNewConst) {
7957 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0));
7958 // (fadd x, (fadd x, x)) -> (fmul x, 3.0)
7959 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) &&
7960 N1.getOperand(0) == N0) {
7961 return DAG.getNode(ISD::FMUL, DL, VT,
7962 N0, DAG.getConstantFP(3.0, DL, VT));
7966 // (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0)
7967 if (AllowNewConst &&
7968 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD &&
7969 N0.getOperand(0) == N0.getOperand(1) &&
7970 N1.getOperand(0) == N1.getOperand(1) &&
7971 N0.getOperand(0) == N1.getOperand(0)) {
7972 return DAG.getNode(ISD::FMUL, DL, VT,
7973 N0.getOperand(0), DAG.getConstantFP(4.0, DL, VT));
7976 } // enable-unsafe-fp-math
7978 // FADD -> FMA combines:
7979 if (SDValue Fused = visitFADDForFMACombine(N)) {
7980 AddToWorklist(Fused.getNode());
7987 SDValue DAGCombiner::visitFSUB(SDNode *N) {
7988 SDValue N0 = N->getOperand(0);
7989 SDValue N1 = N->getOperand(1);
7990 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
7991 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
7992 EVT VT = N->getValueType(0);
7994 const TargetOptions &Options = DAG.getTarget().Options;
7998 if (SDValue FoldedVOp = SimplifyVBinOp(N))
8001 // fold (fsub c1, c2) -> c1-c2
8003 return DAG.getNode(ISD::FSUB, dl, VT, N0, N1);
8005 // fold (fsub A, (fneg B)) -> (fadd A, B)
8006 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
8007 return DAG.getNode(ISD::FADD, dl, VT, N0,
8008 GetNegatedExpression(N1, DAG, LegalOperations));
8010 // If 'unsafe math' is enabled, fold lots of things.
8011 if (Options.UnsafeFPMath) {
8013 if (N1CFP && N1CFP->isZero())
8016 // (fsub 0, B) -> -B
8017 if (N0CFP && N0CFP->isZero()) {
8018 if (isNegatibleForFree(N1, LegalOperations, TLI, &Options))
8019 return GetNegatedExpression(N1, DAG, LegalOperations);
8020 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
8021 return DAG.getNode(ISD::FNEG, dl, VT, N1);
8024 // (fsub x, x) -> 0.0
8026 return DAG.getConstantFP(0.0f, dl, VT);
8028 // (fsub x, (fadd x, y)) -> (fneg y)
8029 // (fsub x, (fadd y, x)) -> (fneg y)
8030 if (N1.getOpcode() == ISD::FADD) {
8031 SDValue N10 = N1->getOperand(0);
8032 SDValue N11 = N1->getOperand(1);
8034 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, &Options))
8035 return GetNegatedExpression(N11, DAG, LegalOperations);
8037 if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, &Options))
8038 return GetNegatedExpression(N10, DAG, LegalOperations);
8042 // FSUB -> FMA combines:
8043 if (SDValue Fused = visitFSUBForFMACombine(N)) {
8044 AddToWorklist(Fused.getNode());
8051 SDValue DAGCombiner::visitFMUL(SDNode *N) {
8052 SDValue N0 = N->getOperand(0);
8053 SDValue N1 = N->getOperand(1);
8054 ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
8055 ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
8056 EVT VT = N->getValueType(0);
8058 const TargetOptions &Options = DAG.getTarget().Options;
8061 if (VT.isVector()) {
8062 // This just handles C1 * C2 for vectors. Other vector folds are below.
8063 if (SDValue FoldedVOp = SimplifyVBinOp(N))
8067 // fold (fmul c1, c2) -> c1*c2
8069 return DAG.getNode(ISD::FMUL, DL, VT, N0, N1);
8071 // canonicalize constant to RHS
8072 if (isConstantFPBuildVectorOrConstantFP(N0) &&
8073 !isConstantFPBuildVectorOrConstantFP(N1))
8074 return DAG.getNode(ISD::FMUL, DL, VT, N1, N0);
8076 // fold (fmul A, 1.0) -> A
8077 if (N1CFP && N1CFP->isExactlyValue(1.0))
8080 if (Options.UnsafeFPMath) {
8081 // fold (fmul A, 0) -> 0
8082 if (N1CFP && N1CFP->isZero())
8085 // fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
8086 if (N0.getOpcode() == ISD::FMUL) {
8087 // Fold scalars or any vector constants (not just splats).
8088 // This fold is done in general by InstCombine, but extra fmul insts
8089 // may have been generated during lowering.
8090 SDValue N00 = N0.getOperand(0);
8091 SDValue N01 = N0.getOperand(1);
8092 auto *BV1 = dyn_cast<BuildVectorSDNode>(N1);
8093 auto *BV00 = dyn_cast<BuildVectorSDNode>(N00);
8094 auto *BV01 = dyn_cast<BuildVectorSDNode>(N01);
8096 // Check 1: Make sure that the first operand of the inner multiply is NOT
8097 // a constant. Otherwise, we may induce infinite looping.
8098 if (!(isConstOrConstSplatFP(N00) || (BV00 && BV00->isConstant()))) {
8099 // Check 2: Make sure that the second operand of the inner multiply and
8100 // the second operand of the outer multiply are constants.
8101 if ((N1CFP && isConstOrConstSplatFP(N01)) ||
8102 (BV1 && BV01 && BV1->isConstant() && BV01->isConstant())) {
8103 SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, N01, N1);
8104 return DAG.getNode(ISD::FMUL, DL, VT, N00, MulConsts);
8109 // fold (fmul (fadd x, x), c) -> (fmul x, (fmul 2.0, c))
8110 // Undo the fmul 2.0, x -> fadd x, x transformation, since if it occurs
8111 // during an early run of DAGCombiner can prevent folding with fmuls
8112 // inserted during lowering.
8113 if (N0.getOpcode() == ISD::FADD &&
8114 (N0.getOperand(0) == N0.getOperand(1)) &&
8116 const SDValue Two = DAG.getConstantFP(2.0, DL, VT);
8117 SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, Two, N1);
8118 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), MulConsts);
8122 // fold (fmul X, 2.0) -> (fadd X, X)
8123 if (N1CFP && N1CFP->isExactlyValue(+2.0))
8124 return DAG.getNode(ISD::FADD, DL, VT, N0, N0);
8126 // fold (fmul X, -1.0) -> (fneg X)
8127 if (N1CFP && N1CFP->isExactlyValue(-1.0))
8128 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
8129 return DAG.getNode(ISD::FNEG, DL, VT, N0);
8131 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
8132 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
8133 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
8134 // Both can be negated for free, check to see if at least one is cheaper
8136 if (LHSNeg == 2 || RHSNeg == 2)
8137 return DAG.getNode(ISD::FMUL, DL, VT,
8138 GetNegatedExpression(N0, DAG, LegalOperations),
8139 GetNegatedExpression(N1, DAG, LegalOperations));
8146 SDValue DAGCombiner::visitFMA(SDNode *N) {
8147 SDValue N0 = N->getOperand(0);
8148 SDValue N1 = N->getOperand(1);
8149 SDValue N2 = N->getOperand(2);
8150 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8151 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8152 EVT VT = N->getValueType(0);
8154 const TargetOptions &Options = DAG.getTarget().Options;
8156 // Constant fold FMA.
8157 if (isa<ConstantFPSDNode>(N0) &&
8158 isa<ConstantFPSDNode>(N1) &&
8159 isa<ConstantFPSDNode>(N2)) {
8160 return DAG.getNode(ISD::FMA, dl, VT, N0, N1, N2);
8163 if (Options.UnsafeFPMath) {
8164 if (N0CFP && N0CFP->isZero())
8166 if (N1CFP && N1CFP->isZero())
8169 if (N0CFP && N0CFP->isExactlyValue(1.0))
8170 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2);
8171 if (N1CFP && N1CFP->isExactlyValue(1.0))
8172 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2);
8174 // Canonicalize (fma c, x, y) -> (fma x, c, y)
8175 if (N0CFP && !N1CFP)
8176 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2);
8178 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2)
8179 if (Options.UnsafeFPMath && N1CFP &&
8180 N2.getOpcode() == ISD::FMUL &&
8181 N0 == N2.getOperand(0) &&
8182 N2.getOperand(1).getOpcode() == ISD::ConstantFP) {
8183 return DAG.getNode(ISD::FMUL, dl, VT, N0,
8184 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1)));
8188 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y)
8189 if (Options.UnsafeFPMath &&
8190 N0.getOpcode() == ISD::FMUL && N1CFP &&
8191 N0.getOperand(1).getOpcode() == ISD::ConstantFP) {
8192 return DAG.getNode(ISD::FMA, dl, VT,
8194 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)),
8198 // (fma x, 1, y) -> (fadd x, y)
8199 // (fma x, -1, y) -> (fadd (fneg x), y)
8201 if (N1CFP->isExactlyValue(1.0))
8202 return DAG.getNode(ISD::FADD, dl, VT, N0, N2);
8204 if (N1CFP->isExactlyValue(-1.0) &&
8205 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) {
8206 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0);
8207 AddToWorklist(RHSNeg.getNode());
8208 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg);
8212 // (fma x, c, x) -> (fmul x, (c+1))
8213 if (Options.UnsafeFPMath && N1CFP && N0 == N2)
8214 return DAG.getNode(ISD::FMUL, dl, VT, N0,
8215 DAG.getNode(ISD::FADD, dl, VT,
8216 N1, DAG.getConstantFP(1.0, dl, VT)));
8218 // (fma x, c, (fneg x)) -> (fmul x, (c-1))
8219 if (Options.UnsafeFPMath && N1CFP &&
8220 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0)
8221 return DAG.getNode(ISD::FMUL, dl, VT, N0,
8222 DAG.getNode(ISD::FADD, dl, VT,
8223 N1, DAG.getConstantFP(-1.0, dl, VT)));
8229 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
8231 // E.g., (a / D; b / D;) -> (recip = 1.0 / D; a * recip; b * recip)
8232 // Notice that this is not always beneficial. One reason is different target
8233 // may have different costs for FDIV and FMUL, so sometimes the cost of two
8234 // FDIVs may be lower than the cost of one FDIV and two FMULs. Another reason
8235 // is the critical path is increased from "one FDIV" to "one FDIV + one FMUL".
8236 SDValue DAGCombiner::combineRepeatedFPDivisors(SDNode *N) {
8237 if (!DAG.getTarget().Options.UnsafeFPMath)
8240 // Skip if current node is a reciprocal.
8241 SDValue N0 = N->getOperand(0);
8242 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8243 if (N0CFP && N0CFP->isExactlyValue(1.0))
8246 // Exit early if the target does not want this transform or if there can't
8247 // possibly be enough uses of the divisor to make the transform worthwhile.
8248 SDValue N1 = N->getOperand(1);
8249 unsigned MinUses = TLI.combineRepeatedFPDivisors();
8250 if (!MinUses || N1->use_size() < MinUses)
8253 // Find all FDIV users of the same divisor.
8254 // Use a set because duplicates may be present in the user list.
8255 SetVector<SDNode *> Users;
8256 for (auto *U : N1->uses())
8257 if (U->getOpcode() == ISD::FDIV && U->getOperand(1) == N1)
8260 // Now that we have the actual number of divisor uses, make sure it meets
8261 // the minimum threshold specified by the target.
8262 if (Users.size() < MinUses)
8265 EVT VT = N->getValueType(0);
8267 SDValue FPOne = DAG.getConstantFP(1.0, DL, VT);
8268 // FIXME: This optimization requires some level of fast-math, so the
8269 // created reciprocal node should at least have the 'allowReciprocal'
8270 // fast-math-flag set.
8271 SDValue Reciprocal = DAG.getNode(ISD::FDIV, DL, VT, FPOne, N1);
8273 // Dividend / Divisor -> Dividend * Reciprocal
8274 for (auto *U : Users) {
8275 SDValue Dividend = U->getOperand(0);
8276 if (Dividend != FPOne) {
8277 SDValue NewNode = DAG.getNode(ISD::FMUL, SDLoc(U), VT, Dividend,
8279 CombineTo(U, NewNode);
8280 } else if (U != Reciprocal.getNode()) {
8281 // In the absence of fast-math-flags, this user node is always the
8282 // same node as Reciprocal, but with FMF they may be different nodes.
8283 CombineTo(U, Reciprocal);
8286 return SDValue(N, 0); // N was replaced.
8289 SDValue DAGCombiner::visitFDIV(SDNode *N) {
8290 SDValue N0 = N->getOperand(0);
8291 SDValue N1 = N->getOperand(1);
8292 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8293 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8294 EVT VT = N->getValueType(0);
8296 const TargetOptions &Options = DAG.getTarget().Options;
8300 if (SDValue FoldedVOp = SimplifyVBinOp(N))
8303 // fold (fdiv c1, c2) -> c1/c2
8305 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1);
8307 if (Options.UnsafeFPMath) {
8308 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable.
8310 // Compute the reciprocal 1.0 / c2.
8311 APFloat N1APF = N1CFP->getValueAPF();
8312 APFloat Recip(N1APF.getSemantics(), 1); // 1.0
8313 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven);
8314 // Only do the transform if the reciprocal is a legal fp immediate that
8315 // isn't too nasty (eg NaN, denormal, ...).
8316 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty
8317 (!LegalOperations ||
8318 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM
8319 // backend)... we should handle this gracefully after Legalize.
8320 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) ||
8321 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) ||
8322 TLI.isFPImmLegal(Recip, VT)))
8323 return DAG.getNode(ISD::FMUL, DL, VT, N0,
8324 DAG.getConstantFP(Recip, DL, VT));
8327 // If this FDIV is part of a reciprocal square root, it may be folded
8328 // into a target-specific square root estimate instruction.
8329 if (N1.getOpcode() == ISD::FSQRT) {
8330 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0))) {
8331 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
8333 } else if (N1.getOpcode() == ISD::FP_EXTEND &&
8334 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
8335 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0).getOperand(0))) {
8336 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N1), VT, RV);
8337 AddToWorklist(RV.getNode());
8338 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
8340 } else if (N1.getOpcode() == ISD::FP_ROUND &&
8341 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
8342 if (SDValue RV = BuildRsqrtEstimate(N1.getOperand(0).getOperand(0))) {
8343 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N1), VT, RV, N1.getOperand(1));
8344 AddToWorklist(RV.getNode());
8345 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
8347 } else if (N1.getOpcode() == ISD::FMUL) {
8348 // Look through an FMUL. Even though this won't remove the FDIV directly,
8349 // it's still worthwhile to get rid of the FSQRT if possible.
8352 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) {
8353 SqrtOp = N1.getOperand(0);
8354 OtherOp = N1.getOperand(1);
8355 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) {
8356 SqrtOp = N1.getOperand(1);
8357 OtherOp = N1.getOperand(0);
8359 if (SqrtOp.getNode()) {
8360 // We found a FSQRT, so try to make this fold:
8361 // x / (y * sqrt(z)) -> x * (rsqrt(z) / y)
8362 if (SDValue RV = BuildRsqrtEstimate(SqrtOp.getOperand(0))) {
8363 RV = DAG.getNode(ISD::FDIV, SDLoc(N1), VT, RV, OtherOp);
8364 AddToWorklist(RV.getNode());
8365 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
8370 // Fold into a reciprocal estimate and multiply instead of a real divide.
8371 if (SDValue RV = BuildReciprocalEstimate(N1)) {
8372 AddToWorklist(RV.getNode());
8373 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV);
8377 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
8378 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, &Options)) {
8379 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, &Options)) {
8380 // Both can be negated for free, check to see if at least one is cheaper
8382 if (LHSNeg == 2 || RHSNeg == 2)
8383 return DAG.getNode(ISD::FDIV, SDLoc(N), VT,
8384 GetNegatedExpression(N0, DAG, LegalOperations),
8385 GetNegatedExpression(N1, DAG, LegalOperations));
8389 if (SDValue CombineRepeatedDivisors = combineRepeatedFPDivisors(N))
8390 return CombineRepeatedDivisors;
8395 SDValue DAGCombiner::visitFREM(SDNode *N) {
8396 SDValue N0 = N->getOperand(0);
8397 SDValue N1 = N->getOperand(1);
8398 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8399 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8400 EVT VT = N->getValueType(0);
8402 // fold (frem c1, c2) -> fmod(c1,c2)
8404 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1);
8409 SDValue DAGCombiner::visitFSQRT(SDNode *N) {
8410 if (!DAG.getTarget().Options.UnsafeFPMath || TLI.isFsqrtCheap())
8413 // Compute this as X * (1/sqrt(X)) = X * (X ** -0.5)
8414 SDValue RV = BuildRsqrtEstimate(N->getOperand(0));
8418 EVT VT = RV.getValueType();
8420 RV = DAG.getNode(ISD::FMUL, DL, VT, N->getOperand(0), RV);
8421 AddToWorklist(RV.getNode());
8423 // Unfortunately, RV is now NaN if the input was exactly 0.
8424 // Select out this case and force the answer to 0.
8425 SDValue Zero = DAG.getConstantFP(0.0, DL, VT);
8426 EVT CCVT = TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
8427 SDValue ZeroCmp = DAG.getSetCC(DL, CCVT, N->getOperand(0), Zero, ISD::SETEQ);
8428 AddToWorklist(ZeroCmp.getNode());
8429 AddToWorklist(RV.getNode());
8431 return DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT,
8435 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
8436 SDValue N0 = N->getOperand(0);
8437 SDValue N1 = N->getOperand(1);
8438 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8439 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8440 EVT VT = N->getValueType(0);
8442 if (N0CFP && N1CFP) // Constant fold
8443 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1);
8446 const APFloat& V = N1CFP->getValueAPF();
8447 // copysign(x, c1) -> fabs(x) iff ispos(c1)
8448 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
8449 if (!V.isNegative()) {
8450 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
8451 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
8453 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
8454 return DAG.getNode(ISD::FNEG, SDLoc(N), VT,
8455 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0));
8459 // copysign(fabs(x), y) -> copysign(x, y)
8460 // copysign(fneg(x), y) -> copysign(x, y)
8461 // copysign(copysign(x,z), y) -> copysign(x, y)
8462 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
8463 N0.getOpcode() == ISD::FCOPYSIGN)
8464 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
8465 N0.getOperand(0), N1);
8467 // copysign(x, abs(y)) -> abs(x)
8468 if (N1.getOpcode() == ISD::FABS)
8469 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
8471 // copysign(x, copysign(y,z)) -> copysign(x, z)
8472 if (N1.getOpcode() == ISD::FCOPYSIGN)
8473 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
8474 N0, N1.getOperand(1));
8476 // copysign(x, fp_extend(y)) -> copysign(x, y)
8477 // copysign(x, fp_round(y)) -> copysign(x, y)
8478 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
8479 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
8480 N0, N1.getOperand(0));
8485 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
8486 SDValue N0 = N->getOperand(0);
8487 EVT VT = N->getValueType(0);
8488 EVT OpVT = N0.getValueType();
8490 // fold (sint_to_fp c1) -> c1fp
8491 if (isConstantIntBuildVectorOrConstantInt(N0) &&
8492 // ...but only if the target supports immediate floating-point values
8493 (!LegalOperations ||
8494 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
8495 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
8497 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
8498 // but UINT_TO_FP is legal on this target, try to convert.
8499 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
8500 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
8501 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
8502 if (DAG.SignBitIsZero(N0))
8503 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
8506 // The next optimizations are desirable only if SELECT_CC can be lowered.
8507 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
8508 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
8509 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 &&
8511 (!LegalOperations ||
8512 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
8515 { N0.getOperand(0), N0.getOperand(1),
8516 DAG.getConstantFP(-1.0, DL, VT), DAG.getConstantFP(0.0, DL, VT),
8518 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
8521 // fold (sint_to_fp (zext (setcc x, y, cc))) ->
8522 // (select_cc x, y, 1.0, 0.0,, cc)
8523 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
8524 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() &&
8525 (!LegalOperations ||
8526 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
8529 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1),
8530 DAG.getConstantFP(1.0, DL, VT), DAG.getConstantFP(0.0, DL, VT),
8531 N0.getOperand(0).getOperand(2) };
8532 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
8539 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
8540 SDValue N0 = N->getOperand(0);
8541 EVT VT = N->getValueType(0);
8542 EVT OpVT = N0.getValueType();
8544 // fold (uint_to_fp c1) -> c1fp
8545 if (isConstantIntBuildVectorOrConstantInt(N0) &&
8546 // ...but only if the target supports immediate floating-point values
8547 (!LegalOperations ||
8548 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
8549 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0);
8551 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
8552 // but SINT_TO_FP is legal on this target, try to convert.
8553 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
8554 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
8555 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
8556 if (DAG.SignBitIsZero(N0))
8557 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0);
8560 // The next optimizations are desirable only if SELECT_CC can be lowered.
8561 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT) || !LegalOperations) {
8562 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc)
8564 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() &&
8565 (!LegalOperations ||
8566 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) {
8569 { N0.getOperand(0), N0.getOperand(1),
8570 DAG.getConstantFP(1.0, DL, VT), DAG.getConstantFP(0.0, DL, VT),
8572 return DAG.getNode(ISD::SELECT_CC, DL, VT, Ops);
8579 // Fold (fp_to_{s/u}int ({s/u}int_to_fpx)) -> zext x, sext x, trunc x, or x
8580 static SDValue FoldIntToFPToInt(SDNode *N, SelectionDAG &DAG) {
8581 SDValue N0 = N->getOperand(0);
8582 EVT VT = N->getValueType(0);
8584 if (N0.getOpcode() != ISD::UINT_TO_FP && N0.getOpcode() != ISD::SINT_TO_FP)
8587 SDValue Src = N0.getOperand(0);
8588 EVT SrcVT = Src.getValueType();
8589 bool IsInputSigned = N0.getOpcode() == ISD::SINT_TO_FP;
8590 bool IsOutputSigned = N->getOpcode() == ISD::FP_TO_SINT;
8592 // We can safely assume the conversion won't overflow the output range,
8593 // because (for example) (uint8_t)18293.f is undefined behavior.
8595 // Since we can assume the conversion won't overflow, our decision as to
8596 // whether the input will fit in the float should depend on the minimum
8597 // of the input range and output range.
8599 // This means this is also safe for a signed input and unsigned output, since
8600 // a negative input would lead to undefined behavior.
8601 unsigned InputSize = (int)SrcVT.getScalarSizeInBits() - IsInputSigned;
8602 unsigned OutputSize = (int)VT.getScalarSizeInBits() - IsOutputSigned;
8603 unsigned ActualSize = std::min(InputSize, OutputSize);
8604 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(N0.getValueType());
8606 // We can only fold away the float conversion if the input range can be
8607 // represented exactly in the float range.
8608 if (APFloat::semanticsPrecision(sem) >= ActualSize) {
8609 if (VT.getScalarSizeInBits() > SrcVT.getScalarSizeInBits()) {
8610 unsigned ExtOp = IsInputSigned && IsOutputSigned ? ISD::SIGN_EXTEND
8612 return DAG.getNode(ExtOp, SDLoc(N), VT, Src);
8614 if (VT.getScalarSizeInBits() < SrcVT.getScalarSizeInBits())
8615 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Src);
8618 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Src);
8623 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
8624 SDValue N0 = N->getOperand(0);
8625 EVT VT = N->getValueType(0);
8627 // fold (fp_to_sint c1fp) -> c1
8628 if (isConstantFPBuildVectorOrConstantFP(N0))
8629 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0);
8631 return FoldIntToFPToInt(N, DAG);
8634 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
8635 SDValue N0 = N->getOperand(0);
8636 EVT VT = N->getValueType(0);
8638 // fold (fp_to_uint c1fp) -> c1
8639 if (isConstantFPBuildVectorOrConstantFP(N0))
8640 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0);
8642 return FoldIntToFPToInt(N, DAG);
8645 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
8646 SDValue N0 = N->getOperand(0);
8647 SDValue N1 = N->getOperand(1);
8648 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8649 EVT VT = N->getValueType(0);
8651 // fold (fp_round c1fp) -> c1fp
8653 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1);
8655 // fold (fp_round (fp_extend x)) -> x
8656 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
8657 return N0.getOperand(0);
8659 // fold (fp_round (fp_round x)) -> (fp_round x)
8660 if (N0.getOpcode() == ISD::FP_ROUND) {
8661 const bool NIsTrunc = N->getConstantOperandVal(1) == 1;
8662 const bool N0IsTrunc = N0.getNode()->getConstantOperandVal(1) == 1;
8663 // If the first fp_round isn't a value preserving truncation, it might
8664 // introduce a tie in the second fp_round, that wouldn't occur in the
8665 // single-step fp_round we want to fold to.
8666 // In other words, double rounding isn't the same as rounding.
8667 // Also, this is a value preserving truncation iff both fp_round's are.
8668 if (DAG.getTarget().Options.UnsafeFPMath || N0IsTrunc) {
8670 return DAG.getNode(ISD::FP_ROUND, DL, VT, N0.getOperand(0),
8671 DAG.getIntPtrConstant(NIsTrunc && N0IsTrunc, DL));
8675 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
8676 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
8677 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT,
8678 N0.getOperand(0), N1);
8679 AddToWorklist(Tmp.getNode());
8680 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT,
8681 Tmp, N0.getOperand(1));
8687 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
8688 SDValue N0 = N->getOperand(0);
8689 EVT VT = N->getValueType(0);
8690 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
8691 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8693 // fold (fp_round_inreg c1fp) -> c1fp
8694 if (N0CFP && isTypeLegal(EVT)) {
8696 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), DL, EVT);
8697 return DAG.getNode(ISD::FP_EXTEND, DL, VT, Round);
8703 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
8704 SDValue N0 = N->getOperand(0);
8705 EVT VT = N->getValueType(0);
8707 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
8708 if (N->hasOneUse() &&
8709 N->use_begin()->getOpcode() == ISD::FP_ROUND)
8712 // fold (fp_extend c1fp) -> c1fp
8713 if (isConstantFPBuildVectorOrConstantFP(N0))
8714 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);
8716 // fold (fp_extend (fp16_to_fp op)) -> (fp16_to_fp op)
8717 if (N0.getOpcode() == ISD::FP16_TO_FP &&
8718 TLI.getOperationAction(ISD::FP16_TO_FP, VT) == TargetLowering::Legal)
8719 return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), VT, N0.getOperand(0));
8721 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
8723 if (N0.getOpcode() == ISD::FP_ROUND
8724 && N0.getNode()->getConstantOperandVal(1) == 1) {
8725 SDValue In = N0.getOperand(0);
8726 if (In.getValueType() == VT) return In;
8727 if (VT.bitsLT(In.getValueType()))
8728 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT,
8729 In, N0.getOperand(1));
8730 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In);
8733 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
8734 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
8735 TLI.isLoadExtLegal(ISD::EXTLOAD, VT, N0.getValueType())) {
8736 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
8737 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT,
8739 LN0->getBasePtr(), N0.getValueType(),
8740 LN0->getMemOperand());
8741 CombineTo(N, ExtLoad);
8742 CombineTo(N0.getNode(),
8743 DAG.getNode(ISD::FP_ROUND, SDLoc(N0),
8744 N0.getValueType(), ExtLoad,
8745 DAG.getIntPtrConstant(1, SDLoc(N0))),
8746 ExtLoad.getValue(1));
8747 return SDValue(N, 0); // Return N so it doesn't get rechecked!
8753 SDValue DAGCombiner::visitFCEIL(SDNode *N) {
8754 SDValue N0 = N->getOperand(0);
8755 EVT VT = N->getValueType(0);
8757 // fold (fceil c1) -> fceil(c1)
8758 if (isConstantFPBuildVectorOrConstantFP(N0))
8759 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0);
8764 SDValue DAGCombiner::visitFTRUNC(SDNode *N) {
8765 SDValue N0 = N->getOperand(0);
8766 EVT VT = N->getValueType(0);
8768 // fold (ftrunc c1) -> ftrunc(c1)
8769 if (isConstantFPBuildVectorOrConstantFP(N0))
8770 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0);
8775 SDValue DAGCombiner::visitFFLOOR(SDNode *N) {
8776 SDValue N0 = N->getOperand(0);
8777 EVT VT = N->getValueType(0);
8779 // fold (ffloor c1) -> ffloor(c1)
8780 if (isConstantFPBuildVectorOrConstantFP(N0))
8781 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0);
8786 // FIXME: FNEG and FABS have a lot in common; refactor.
8787 SDValue DAGCombiner::visitFNEG(SDNode *N) {
8788 SDValue N0 = N->getOperand(0);
8789 EVT VT = N->getValueType(0);
8791 // Constant fold FNEG.
8792 if (isConstantFPBuildVectorOrConstantFP(N0))
8793 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0);
8795 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(),
8796 &DAG.getTarget().Options))
8797 return GetNegatedExpression(N0, DAG, LegalOperations);
8799 // Transform fneg(bitconvert(x)) -> bitconvert(x ^ sign) to avoid loading
8800 // constant pool values.
8801 if (!TLI.isFNegFree(VT) &&
8802 N0.getOpcode() == ISD::BITCAST &&
8803 N0.getNode()->hasOneUse()) {
8804 SDValue Int = N0.getOperand(0);
8805 EVT IntVT = Int.getValueType();
8806 if (IntVT.isInteger() && !IntVT.isVector()) {
8808 if (N0.getValueType().isVector()) {
8809 // For a vector, get a mask such as 0x80... per scalar element
8811 SignMask = APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
8812 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
8814 // For a scalar, just generate 0x80...
8815 SignMask = APInt::getSignBit(IntVT.getSizeInBits());
8818 Int = DAG.getNode(ISD::XOR, DL0, IntVT, Int,
8819 DAG.getConstant(SignMask, DL0, IntVT));
8820 AddToWorklist(Int.getNode());
8821 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Int);
8825 // (fneg (fmul c, x)) -> (fmul -c, x)
8826 if (N0.getOpcode() == ISD::FMUL &&
8827 (N0.getNode()->hasOneUse() || !TLI.isFNegFree(VT))) {
8828 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));
8830 APFloat CVal = CFP1->getValueAPF();
8832 if (Level >= AfterLegalizeDAG &&
8833 (TLI.isFPImmLegal(CVal, N->getValueType(0)) ||
8834 TLI.isOperationLegal(ISD::ConstantFP, N->getValueType(0))))
8836 ISD::FMUL, SDLoc(N), VT, N0.getOperand(0),
8837 DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0.getOperand(1)));
8844 SDValue DAGCombiner::visitFMINNUM(SDNode *N) {
8845 SDValue N0 = N->getOperand(0);
8846 SDValue N1 = N->getOperand(1);
8847 const ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8848 const ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8850 if (N0CFP && N1CFP) {
8851 const APFloat &C0 = N0CFP->getValueAPF();
8852 const APFloat &C1 = N1CFP->getValueAPF();
8853 return DAG.getConstantFP(minnum(C0, C1), SDLoc(N), N->getValueType(0));
8857 EVT VT = N->getValueType(0);
8858 // Canonicalize to constant on RHS.
8859 return DAG.getNode(ISD::FMINNUM, SDLoc(N), VT, N1, N0);
8865 SDValue DAGCombiner::visitFMAXNUM(SDNode *N) {
8866 SDValue N0 = N->getOperand(0);
8867 SDValue N1 = N->getOperand(1);
8868 const ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
8869 const ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
8871 if (N0CFP && N1CFP) {
8872 const APFloat &C0 = N0CFP->getValueAPF();
8873 const APFloat &C1 = N1CFP->getValueAPF();
8874 return DAG.getConstantFP(maxnum(C0, C1), SDLoc(N), N->getValueType(0));
8878 EVT VT = N->getValueType(0);
8879 // Canonicalize to constant on RHS.
8880 return DAG.getNode(ISD::FMAXNUM, SDLoc(N), VT, N1, N0);
8886 SDValue DAGCombiner::visitFABS(SDNode *N) {
8887 SDValue N0 = N->getOperand(0);
8888 EVT VT = N->getValueType(0);
8890 // fold (fabs c1) -> fabs(c1)
8891 if (isConstantFPBuildVectorOrConstantFP(N0))
8892 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0);
8894 // fold (fabs (fabs x)) -> (fabs x)
8895 if (N0.getOpcode() == ISD::FABS)
8896 return N->getOperand(0);
8898 // fold (fabs (fneg x)) -> (fabs x)
8899 // fold (fabs (fcopysign x, y)) -> (fabs x)
8900 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
8901 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0));
8903 // Transform fabs(bitconvert(x)) -> bitconvert(x & ~sign) to avoid loading
8904 // constant pool values.
8905 if (!TLI.isFAbsFree(VT) &&
8906 N0.getOpcode() == ISD::BITCAST &&
8907 N0.getNode()->hasOneUse()) {
8908 SDValue Int = N0.getOperand(0);
8909 EVT IntVT = Int.getValueType();
8910 if (IntVT.isInteger() && !IntVT.isVector()) {
8912 if (N0.getValueType().isVector()) {
8913 // For a vector, get a mask such as 0x7f... per scalar element
8915 SignMask = ~APInt::getSignBit(N0.getValueType().getScalarSizeInBits());
8916 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask);
8918 // For a scalar, just generate 0x7f...
8919 SignMask = ~APInt::getSignBit(IntVT.getSizeInBits());
8922 Int = DAG.getNode(ISD::AND, DL, IntVT, Int,
8923 DAG.getConstant(SignMask, DL, IntVT));
8924 AddToWorklist(Int.getNode());
8925 return DAG.getNode(ISD::BITCAST, SDLoc(N), N->getValueType(0), Int);
8932 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
8933 SDValue Chain = N->getOperand(0);
8934 SDValue N1 = N->getOperand(1);
8935 SDValue N2 = N->getOperand(2);
8937 // If N is a constant we could fold this into a fallthrough or unconditional
8938 // branch. However that doesn't happen very often in normal code, because
8939 // Instcombine/SimplifyCFG should have handled the available opportunities.
8940 // If we did this folding here, it would be necessary to update the
8941 // MachineBasicBlock CFG, which is awkward.
8943 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
8945 if (N1.getOpcode() == ISD::SETCC &&
8946 TLI.isOperationLegalOrCustom(ISD::BR_CC,
8947 N1.getOperand(0).getValueType())) {
8948 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
8949 Chain, N1.getOperand(2),
8950 N1.getOperand(0), N1.getOperand(1), N2);
8953 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
8954 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
8955 (N1.getOperand(0).hasOneUse() &&
8956 N1.getOperand(0).getOpcode() == ISD::SRL))) {
8957 SDNode *Trunc = nullptr;
8958 if (N1.getOpcode() == ISD::TRUNCATE) {
8959 // Look pass the truncate.
8960 Trunc = N1.getNode();
8961 N1 = N1.getOperand(0);
8964 // Match this pattern so that we can generate simpler code:
8967 // %b = and i32 %a, 2
8968 // %c = srl i32 %b, 1
8969 // brcond i32 %c ...
8974 // %b = and i32 %a, 2
8975 // %c = setcc eq %b, 0
8978 // This applies only when the AND constant value has one bit set and the
8979 // SRL constant is equal to the log2 of the AND constant. The back-end is
8980 // smart enough to convert the result into a TEST/JMP sequence.
8981 SDValue Op0 = N1.getOperand(0);
8982 SDValue Op1 = N1.getOperand(1);
8984 if (Op0.getOpcode() == ISD::AND &&
8985 Op1.getOpcode() == ISD::Constant) {
8986 SDValue AndOp1 = Op0.getOperand(1);
8988 if (AndOp1.getOpcode() == ISD::Constant) {
8989 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
8991 if (AndConst.isPowerOf2() &&
8992 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
8996 getSetCCResultType(Op0.getValueType()),
8997 Op0, DAG.getConstant(0, DL, Op0.getValueType()),
9000 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, DL,
9001 MVT::Other, Chain, SetCC, N2);
9002 // Don't add the new BRCond into the worklist or else SimplifySelectCC
9003 // will convert it back to (X & C1) >> C2.
9004 CombineTo(N, NewBRCond, false);
9005 // Truncate is dead.
9007 deleteAndRecombine(Trunc);
9008 // Replace the uses of SRL with SETCC
9009 WorklistRemover DeadNodes(*this);
9010 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
9011 deleteAndRecombine(N1.getNode());
9012 return SDValue(N, 0); // Return N so it doesn't get rechecked!
9018 // Restore N1 if the above transformation doesn't match.
9019 N1 = N->getOperand(1);
9022 // Transform br(xor(x, y)) -> br(x != y)
9023 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
9024 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
9025 SDNode *TheXor = N1.getNode();
9026 SDValue Op0 = TheXor->getOperand(0);
9027 SDValue Op1 = TheXor->getOperand(1);
9028 if (Op0.getOpcode() == Op1.getOpcode()) {
9029 // Avoid missing important xor optimizations.
9030 if (SDValue Tmp = visitXOR(TheXor)) {
9031 if (Tmp.getNode() != TheXor) {
9032 DEBUG(dbgs() << "\nReplacing.8 ";
9034 dbgs() << "\nWith: ";
9035 Tmp.getNode()->dump(&DAG);
9037 WorklistRemover DeadNodes(*this);
9038 DAG.ReplaceAllUsesOfValueWith(N1, Tmp);
9039 deleteAndRecombine(TheXor);
9040 return DAG.getNode(ISD::BRCOND, SDLoc(N),
9041 MVT::Other, Chain, Tmp, N2);
9044 // visitXOR has changed XOR's operands or replaced the XOR completely,
9046 return SDValue(N, 0);
9050 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
9052 if (isOneConstant(Op0) && Op0.hasOneUse() &&
9053 Op0.getOpcode() == ISD::XOR) {
9054 TheXor = Op0.getNode();
9058 EVT SetCCVT = N1.getValueType();
9060 SetCCVT = getSetCCResultType(SetCCVT);
9061 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor),
9064 Equal ? ISD::SETEQ : ISD::SETNE);
9065 // Replace the uses of XOR with SETCC
9066 WorklistRemover DeadNodes(*this);
9067 DAG.ReplaceAllUsesOfValueWith(N1, SetCC);
9068 deleteAndRecombine(N1.getNode());
9069 return DAG.getNode(ISD::BRCOND, SDLoc(N),
9070 MVT::Other, Chain, SetCC, N2);
9077 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
9079 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
9080 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
9081 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
9083 // If N is a constant we could fold this into a fallthrough or unconditional
9084 // branch. However that doesn't happen very often in normal code, because
9085 // Instcombine/SimplifyCFG should have handled the available opportunities.
9086 // If we did this folding here, it would be necessary to update the
9087 // MachineBasicBlock CFG, which is awkward.
9089 // Use SimplifySetCC to simplify SETCC's.
9090 SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()),
9091 CondLHS, CondRHS, CC->get(), SDLoc(N),
9093 if (Simp.getNode()) AddToWorklist(Simp.getNode());
9095 // fold to a simpler setcc
9096 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
9097 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
9098 N->getOperand(0), Simp.getOperand(2),
9099 Simp.getOperand(0), Simp.getOperand(1),
9105 /// Return true if 'Use' is a load or a store that uses N as its base pointer
9106 /// and that N may be folded in the load / store addressing mode.
9107 static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
9109 const TargetLowering &TLI) {
9113 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) {
9114 if (LD->isIndexed() || LD->getBasePtr().getNode() != N)
9116 VT = LD->getMemoryVT();
9117 AS = LD->getAddressSpace();
9118 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) {
9119 if (ST->isIndexed() || ST->getBasePtr().getNode() != N)
9121 VT = ST->getMemoryVT();
9122 AS = ST->getAddressSpace();
9126 TargetLowering::AddrMode AM;
9127 if (N->getOpcode() == ISD::ADD) {
9128 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
9131 AM.BaseOffs = Offset->getSExtValue();
9135 } else if (N->getOpcode() == ISD::SUB) {
9136 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
9139 AM.BaseOffs = -Offset->getSExtValue();
9146 return TLI.isLegalAddressingMode(DAG.getDataLayout(), AM,
9147 VT.getTypeForEVT(*DAG.getContext()), AS);
9150 /// Try turning a load/store into a pre-indexed load/store when the base
9151 /// pointer is an add or subtract and it has other uses besides the load/store.
9152 /// After the transformation, the new indexed load/store has effectively folded
9153 /// the add/subtract in and all of its other uses are redirected to the
9155 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
9156 if (Level < AfterLegalizeDAG)
9162 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9163 if (LD->isIndexed())
9165 VT = LD->getMemoryVT();
9166 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
9167 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
9169 Ptr = LD->getBasePtr();
9170 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9171 if (ST->isIndexed())
9173 VT = ST->getMemoryVT();
9174 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
9175 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
9177 Ptr = ST->getBasePtr();
9183 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
9184 // out. There is no reason to make this a preinc/predec.
9185 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
9186 Ptr.getNode()->hasOneUse())
9189 // Ask the target to do addressing mode selection.
9192 ISD::MemIndexedMode AM = ISD::UNINDEXED;
9193 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
9196 // Backends without true r+i pre-indexed forms may need to pass a
9197 // constant base with a variable offset so that constant coercion
9198 // will work with the patterns in canonical form.
9199 bool Swapped = false;
9200 if (isa<ConstantSDNode>(BasePtr)) {
9201 std::swap(BasePtr, Offset);
9205 // Don't create a indexed load / store with zero offset.
9206 if (isNullConstant(Offset))
9209 // Try turning it into a pre-indexed load / store except when:
9210 // 1) The new base ptr is a frame index.
9211 // 2) If N is a store and the new base ptr is either the same as or is a
9212 // predecessor of the value being stored.
9213 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
9214 // that would create a cycle.
9215 // 4) All uses are load / store ops that use it as old base ptr.
9217 // Check #1. Preinc'ing a frame index would require copying the stack pointer
9218 // (plus the implicit offset) to a register to preinc anyway.
9219 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
9224 SDValue Val = cast<StoreSDNode>(N)->getValue();
9225 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
9229 // If the offset is a constant, there may be other adds of constants that
9230 // can be folded with this one. We should do this to avoid having to keep
9231 // a copy of the original base pointer.
9232 SmallVector<SDNode *, 16> OtherUses;
9233 if (isa<ConstantSDNode>(Offset))
9234 for (SDNode::use_iterator UI = BasePtr.getNode()->use_begin(),
9235 UE = BasePtr.getNode()->use_end();
9237 SDUse &Use = UI.getUse();
9238 // Skip the use that is Ptr and uses of other results from BasePtr's
9239 // node (important for nodes that return multiple results).
9240 if (Use.getUser() == Ptr.getNode() || Use != BasePtr)
9243 if (Use.getUser()->isPredecessorOf(N))
9246 if (Use.getUser()->getOpcode() != ISD::ADD &&
9247 Use.getUser()->getOpcode() != ISD::SUB) {
9252 SDValue Op1 = Use.getUser()->getOperand((UI.getOperandNo() + 1) & 1);
9253 if (!isa<ConstantSDNode>(Op1)) {
9258 // FIXME: In some cases, we can be smarter about this.
9259 if (Op1.getValueType() != Offset.getValueType()) {
9264 OtherUses.push_back(Use.getUser());
9268 std::swap(BasePtr, Offset);
9270 // Now check for #3 and #4.
9271 bool RealUse = false;
9273 // Caches for hasPredecessorHelper
9274 SmallPtrSet<const SDNode *, 32> Visited;
9275 SmallVector<const SDNode *, 16> Worklist;
9277 for (SDNode *Use : Ptr.getNode()->uses()) {
9280 if (N->hasPredecessorHelper(Use, Visited, Worklist))
9283 // If Ptr may be folded in addressing mode of other use, then it's
9284 // not profitable to do this transformation.
9285 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI))
9294 Result = DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
9295 BasePtr, Offset, AM);
9297 Result = DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
9298 BasePtr, Offset, AM);
9301 DEBUG(dbgs() << "\nReplacing.4 ";
9303 dbgs() << "\nWith: ";
9304 Result.getNode()->dump(&DAG);
9306 WorklistRemover DeadNodes(*this);
9308 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
9309 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
9311 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
9314 // Finally, since the node is now dead, remove it from the graph.
9315 deleteAndRecombine(N);
9318 std::swap(BasePtr, Offset);
9320 // Replace other uses of BasePtr that can be updated to use Ptr
9321 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) {
9322 unsigned OffsetIdx = 1;
9323 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode())
9325 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() ==
9326 BasePtr.getNode() && "Expected BasePtr operand");
9328 // We need to replace ptr0 in the following expression:
9329 // x0 * offset0 + y0 * ptr0 = t0
9331 // x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store)
9333 // where x0, x1, y0 and y1 in {-1, 1} are given by the types of the
9334 // indexed load/store and the expresion that needs to be re-written.
9336 // Therefore, we have:
9337 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
9339 ConstantSDNode *CN =
9340 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
9342 APInt Offset0 = CN->getAPIntValue();
9343 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
9345 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
9346 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
9347 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1;
9348 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1;
9350 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD;
9352 APInt CNV = Offset0;
9353 if (X0 < 0) CNV = -CNV;
9354 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1;
9355 else CNV = CNV - Offset1;
9357 SDLoc DL(OtherUses[i]);
9359 // We can now generate the new expression.
9360 SDValue NewOp1 = DAG.getConstant(CNV, DL, CN->getValueType(0));
9361 SDValue NewOp2 = Result.getValue(isLoad ? 1 : 0);
9363 SDValue NewUse = DAG.getNode(Opcode,
9365 OtherUses[i]->getValueType(0), NewOp1, NewOp2);
9366 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse);
9367 deleteAndRecombine(OtherUses[i]);
9370 // Replace the uses of Ptr with uses of the updated base value.
9371 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0));
9372 deleteAndRecombine(Ptr.getNode());
9377 /// Try to combine a load/store with a add/sub of the base pointer node into a
9378 /// post-indexed load/store. The transformation folded the add/subtract into the
9379 /// new indexed load/store effectively and all of its uses are redirected to the
9381 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
9382 if (Level < AfterLegalizeDAG)
9388 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9389 if (LD->isIndexed())
9391 VT = LD->getMemoryVT();
9392 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
9393 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
9395 Ptr = LD->getBasePtr();
9396 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9397 if (ST->isIndexed())
9399 VT = ST->getMemoryVT();
9400 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
9401 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
9403 Ptr = ST->getBasePtr();
9409 if (Ptr.getNode()->hasOneUse())
9412 for (SDNode *Op : Ptr.getNode()->uses()) {
9414 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
9419 ISD::MemIndexedMode AM = ISD::UNINDEXED;
9420 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
9421 // Don't create a indexed load / store with zero offset.
9422 if (isNullConstant(Offset))
9425 // Try turning it into a post-indexed load / store except when
9426 // 1) All uses are load / store ops that use it as base ptr (and
9427 // it may be folded as addressing mmode).
9428 // 2) Op must be independent of N, i.e. Op is neither a predecessor
9429 // nor a successor of N. Otherwise, if Op is folded that would
9432 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
9436 bool TryNext = false;
9437 for (SDNode *Use : BasePtr.getNode()->uses()) {
9438 if (Use == Ptr.getNode())
9441 // If all the uses are load / store addresses, then don't do the
9443 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
9444 bool RealUse = false;
9445 for (SDNode *UseUse : Use->uses()) {
9446 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI))
9461 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
9462 SDValue Result = isLoad
9463 ? DAG.getIndexedLoad(SDValue(N,0), SDLoc(N),
9464 BasePtr, Offset, AM)
9465 : DAG.getIndexedStore(SDValue(N,0), SDLoc(N),
9466 BasePtr, Offset, AM);
9469 DEBUG(dbgs() << "\nReplacing.5 ";
9471 dbgs() << "\nWith: ";
9472 Result.getNode()->dump(&DAG);
9474 WorklistRemover DeadNodes(*this);
9476 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0));
9477 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2));
9479 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1));
9482 // Finally, since the node is now dead, remove it from the graph.
9483 deleteAndRecombine(N);
9485 // Replace the uses of Use with uses of the updated base value.
9486 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
9487 Result.getValue(isLoad ? 1 : 0));
9488 deleteAndRecombine(Op);
9497 /// \brief Return the base-pointer arithmetic from an indexed \p LD.
9498 SDValue DAGCombiner::SplitIndexingFromLoad(LoadSDNode *LD) {
9499 ISD::MemIndexedMode AM = LD->getAddressingMode();
9500 assert(AM != ISD::UNINDEXED);
9501 SDValue BP = LD->getOperand(1);
9502 SDValue Inc = LD->getOperand(2);
9504 // Some backends use TargetConstants for load offsets, but don't expect
9505 // TargetConstants in general ADD nodes. We can convert these constants into
9506 // regular Constants (if the constant is not opaque).
9507 assert((Inc.getOpcode() != ISD::TargetConstant ||
9508 !cast<ConstantSDNode>(Inc)->isOpaque()) &&
9509 "Cannot split out indexing using opaque target constants");
9510 if (Inc.getOpcode() == ISD::TargetConstant) {
9511 ConstantSDNode *ConstInc = cast<ConstantSDNode>(Inc);
9512 Inc = DAG.getConstant(*ConstInc->getConstantIntValue(), SDLoc(Inc),
9513 ConstInc->getValueType(0));
9517 (AM == ISD::PRE_INC || AM == ISD::POST_INC ? ISD::ADD : ISD::SUB);
9518 return DAG.getNode(Opc, SDLoc(LD), BP.getSimpleValueType(), BP, Inc);
9521 SDValue DAGCombiner::visitLOAD(SDNode *N) {
9522 LoadSDNode *LD = cast<LoadSDNode>(N);
9523 SDValue Chain = LD->getChain();
9524 SDValue Ptr = LD->getBasePtr();
9526 // If load is not volatile and there are no uses of the loaded value (and
9527 // the updated indexed value in case of indexed loads), change uses of the
9528 // chain value into uses of the chain input (i.e. delete the dead load).
9529 if (!LD->isVolatile()) {
9530 if (N->getValueType(1) == MVT::Other) {
9532 if (!N->hasAnyUseOfValue(0)) {
9533 // It's not safe to use the two value CombineTo variant here. e.g.
9534 // v1, chain2 = load chain1, loc
9535 // v2, chain3 = load chain2, loc
9537 // Now we replace use of chain2 with chain1. This makes the second load
9538 // isomorphic to the one we are deleting, and thus makes this load live.
9539 DEBUG(dbgs() << "\nReplacing.6 ";
9541 dbgs() << "\nWith chain: ";
9542 Chain.getNode()->dump(&DAG);
9544 WorklistRemover DeadNodes(*this);
9545 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
9548 deleteAndRecombine(N);
9550 return SDValue(N, 0); // Return N so it doesn't get rechecked!
9554 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
9556 // If this load has an opaque TargetConstant offset, then we cannot split
9557 // the indexing into an add/sub directly (that TargetConstant may not be
9558 // valid for a different type of node, and we cannot convert an opaque
9559 // target constant into a regular constant).
9560 bool HasOTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant &&
9561 cast<ConstantSDNode>(LD->getOperand(2))->isOpaque();
9563 if (!N->hasAnyUseOfValue(0) &&
9564 ((MaySplitLoadIndex && !HasOTCInc) || !N->hasAnyUseOfValue(1))) {
9565 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
9567 if (N->hasAnyUseOfValue(1) && MaySplitLoadIndex && !HasOTCInc) {
9568 Index = SplitIndexingFromLoad(LD);
9569 // Try to fold the base pointer arithmetic into subsequent loads and
9571 AddUsersToWorklist(N);
9573 Index = DAG.getUNDEF(N->getValueType(1));
9574 DEBUG(dbgs() << "\nReplacing.7 ";
9576 dbgs() << "\nWith: ";
9577 Undef.getNode()->dump(&DAG);
9578 dbgs() << " and 2 other values\n");
9579 WorklistRemover DeadNodes(*this);
9580 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef);
9581 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Index);
9582 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain);
9583 deleteAndRecombine(N);
9584 return SDValue(N, 0); // Return N so it doesn't get rechecked!
9589 // If this load is directly stored, replace the load value with the stored
9591 // TODO: Handle store large -> read small portion.
9592 // TODO: Handle TRUNCSTORE/LOADEXT
9593 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
9594 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
9595 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
9596 if (PrevST->getBasePtr() == Ptr &&
9597 PrevST->getValue().getValueType() == N->getValueType(0))
9598 return CombineTo(N, Chain.getOperand(1), Chain);
9602 // Try to infer better alignment information than the load already has.
9603 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
9604 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
9605 if (Align > LD->getMemOperand()->getBaseAlignment()) {
9607 DAG.getExtLoad(LD->getExtensionType(), SDLoc(N),
9608 LD->getValueType(0),
9609 Chain, Ptr, LD->getPointerInfo(),
9611 LD->isVolatile(), LD->isNonTemporal(),
9612 LD->isInvariant(), Align, LD->getAAInfo());
9613 if (NewLoad.getNode() != N)
9614 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true);
9619 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
9620 : DAG.getSubtarget().useAA();
9622 if (CombinerAAOnlyFunc.getNumOccurrences() &&
9623 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
9626 if (UseAA && LD->isUnindexed()) {
9627 // Walk up chain skipping non-aliasing memory nodes.
9628 SDValue BetterChain = FindBetterChain(N, Chain);
9630 // If there is a better chain.
9631 if (Chain != BetterChain) {
9634 // Replace the chain to void dependency.
9635 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
9636 ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD),
9637 BetterChain, Ptr, LD->getMemOperand());
9639 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD),
9640 LD->getValueType(0),
9641 BetterChain, Ptr, LD->getMemoryVT(),
9642 LD->getMemOperand());
9645 // Create token factor to keep old chain connected.
9646 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
9647 MVT::Other, Chain, ReplLoad.getValue(1));
9649 // Make sure the new and old chains are cleaned up.
9650 AddToWorklist(Token.getNode());
9652 // Replace uses with load result and token factor. Don't add users
9654 return CombineTo(N, ReplLoad.getValue(0), Token, false);
9658 // Try transforming N to an indexed load.
9659 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
9660 return SDValue(N, 0);
9662 // Try to slice up N to more direct loads if the slices are mapped to
9663 // different register banks or pairing can take place.
9665 return SDValue(N, 0);
9671 /// \brief Helper structure used to slice a load in smaller loads.
9672 /// Basically a slice is obtained from the following sequence:
9673 /// Origin = load Ty1, Base
9674 /// Shift = srl Ty1 Origin, CstTy Amount
9675 /// Inst = trunc Shift to Ty2
9677 /// Then, it will be rewriten into:
9678 /// Slice = load SliceTy, Base + SliceOffset
9679 /// [Inst = zext Slice to Ty2], only if SliceTy <> Ty2
9681 /// SliceTy is deduced from the number of bits that are actually used to
9683 struct LoadedSlice {
9684 /// \brief Helper structure used to compute the cost of a slice.
9686 /// Are we optimizing for code size.
9691 unsigned CrossRegisterBanksCopies;
9695 Cost(bool ForCodeSize = false)
9696 : ForCodeSize(ForCodeSize), Loads(0), Truncates(0),
9697 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {}
9699 /// \brief Get the cost of one isolated slice.
9700 Cost(const LoadedSlice &LS, bool ForCodeSize = false)
9701 : ForCodeSize(ForCodeSize), Loads(1), Truncates(0),
9702 CrossRegisterBanksCopies(0), ZExts(0), Shift(0) {
9703 EVT TruncType = LS.Inst->getValueType(0);
9704 EVT LoadedType = LS.getLoadedType();
9705 if (TruncType != LoadedType &&
9706 !LS.DAG->getTargetLoweringInfo().isZExtFree(LoadedType, TruncType))
9710 /// \brief Account for slicing gain in the current cost.
9711 /// Slicing provide a few gains like removing a shift or a
9712 /// truncate. This method allows to grow the cost of the original
9713 /// load with the gain from this slice.
9714 void addSliceGain(const LoadedSlice &LS) {
9715 // Each slice saves a truncate.
9716 const TargetLowering &TLI = LS.DAG->getTargetLoweringInfo();
9717 if (!TLI.isTruncateFree(LS.Inst->getValueType(0),
9718 LS.Inst->getOperand(0).getValueType()))
9720 // If there is a shift amount, this slice gets rid of it.
9723 // If this slice can merge a cross register bank copy, account for it.
9724 if (LS.canMergeExpensiveCrossRegisterBankCopy())
9725 ++CrossRegisterBanksCopies;
9728 Cost &operator+=(const Cost &RHS) {
9730 Truncates += RHS.Truncates;
9731 CrossRegisterBanksCopies += RHS.CrossRegisterBanksCopies;
9737 bool operator==(const Cost &RHS) const {
9738 return Loads == RHS.Loads && Truncates == RHS.Truncates &&
9739 CrossRegisterBanksCopies == RHS.CrossRegisterBanksCopies &&
9740 ZExts == RHS.ZExts && Shift == RHS.Shift;
9743 bool operator!=(const Cost &RHS) const { return !(*this == RHS); }
9745 bool operator<(const Cost &RHS) const {
9746 // Assume cross register banks copies are as expensive as loads.
9747 // FIXME: Do we want some more target hooks?
9748 unsigned ExpensiveOpsLHS = Loads + CrossRegisterBanksCopies;
9749 unsigned ExpensiveOpsRHS = RHS.Loads + RHS.CrossRegisterBanksCopies;
9750 // Unless we are optimizing for code size, consider the
9751 // expensive operation first.
9752 if (!ForCodeSize && ExpensiveOpsLHS != ExpensiveOpsRHS)
9753 return ExpensiveOpsLHS < ExpensiveOpsRHS;
9754 return (Truncates + ZExts + Shift + ExpensiveOpsLHS) <
9755 (RHS.Truncates + RHS.ZExts + RHS.Shift + ExpensiveOpsRHS);
9758 bool operator>(const Cost &RHS) const { return RHS < *this; }
9760 bool operator<=(const Cost &RHS) const { return !(RHS < *this); }
9762 bool operator>=(const Cost &RHS) const { return !(*this < RHS); }
9764 // The last instruction that represent the slice. This should be a
9765 // truncate instruction.
9767 // The original load instruction.
9769 // The right shift amount in bits from the original load.
9771 // The DAG from which Origin came from.
9772 // This is used to get some contextual information about legal types, etc.
9775 LoadedSlice(SDNode *Inst = nullptr, LoadSDNode *Origin = nullptr,
9776 unsigned Shift = 0, SelectionDAG *DAG = nullptr)
9777 : Inst(Inst), Origin(Origin), Shift(Shift), DAG(DAG) {}
9779 /// \brief Get the bits used in a chunk of bits \p BitWidth large.
9780 /// \return Result is \p BitWidth and has used bits set to 1 and
9781 /// not used bits set to 0.
9782 APInt getUsedBits() const {
9783 // Reproduce the trunc(lshr) sequence:
9784 // - Start from the truncated value.
9785 // - Zero extend to the desired bit width.
9787 assert(Origin && "No original load to compare against.");
9788 unsigned BitWidth = Origin->getValueSizeInBits(0);
9789 assert(Inst && "This slice is not bound to an instruction");
9790 assert(Inst->getValueSizeInBits(0) <= BitWidth &&
9791 "Extracted slice is bigger than the whole type!");
9792 APInt UsedBits(Inst->getValueSizeInBits(0), 0);
9793 UsedBits.setAllBits();
9794 UsedBits = UsedBits.zext(BitWidth);
9799 /// \brief Get the size of the slice to be loaded in bytes.
9800 unsigned getLoadedSize() const {
9801 unsigned SliceSize = getUsedBits().countPopulation();
9802 assert(!(SliceSize & 0x7) && "Size is not a multiple of a byte.");
9803 return SliceSize / 8;
9806 /// \brief Get the type that will be loaded for this slice.
9807 /// Note: This may not be the final type for the slice.
9808 EVT getLoadedType() const {
9809 assert(DAG && "Missing context");
9810 LLVMContext &Ctxt = *DAG->getContext();
9811 return EVT::getIntegerVT(Ctxt, getLoadedSize() * 8);
9814 /// \brief Get the alignment of the load used for this slice.
9815 unsigned getAlignment() const {
9816 unsigned Alignment = Origin->getAlignment();
9817 unsigned Offset = getOffsetFromBase();
9819 Alignment = MinAlign(Alignment, Alignment + Offset);
9823 /// \brief Check if this slice can be rewritten with legal operations.
9824 bool isLegal() const {
9825 // An invalid slice is not legal.
9826 if (!Origin || !Inst || !DAG)
9829 // Offsets are for indexed load only, we do not handle that.
9830 if (Origin->getOffset().getOpcode() != ISD::UNDEF)
9833 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
9835 // Check that the type is legal.
9836 EVT SliceType = getLoadedType();
9837 if (!TLI.isTypeLegal(SliceType))
9840 // Check that the load is legal for this type.
9841 if (!TLI.isOperationLegal(ISD::LOAD, SliceType))
9844 // Check that the offset can be computed.
9845 // 1. Check its type.
9846 EVT PtrType = Origin->getBasePtr().getValueType();
9847 if (PtrType == MVT::Untyped || PtrType.isExtended())
9850 // 2. Check that it fits in the immediate.
9851 if (!TLI.isLegalAddImmediate(getOffsetFromBase()))
9854 // 3. Check that the computation is legal.
9855 if (!TLI.isOperationLegal(ISD::ADD, PtrType))
9858 // Check that the zext is legal if it needs one.
9859 EVT TruncateType = Inst->getValueType(0);
9860 if (TruncateType != SliceType &&
9861 !TLI.isOperationLegal(ISD::ZERO_EXTEND, TruncateType))
9867 /// \brief Get the offset in bytes of this slice in the original chunk of
9869 /// \pre DAG != nullptr.
9870 uint64_t getOffsetFromBase() const {
9871 assert(DAG && "Missing context.");
9872 bool IsBigEndian = DAG->getDataLayout().isBigEndian();
9873 assert(!(Shift & 0x7) && "Shifts not aligned on Bytes are not supported.");
9874 uint64_t Offset = Shift / 8;
9875 unsigned TySizeInBytes = Origin->getValueSizeInBits(0) / 8;
9876 assert(!(Origin->getValueSizeInBits(0) & 0x7) &&
9877 "The size of the original loaded type is not a multiple of a"
9879 // If Offset is bigger than TySizeInBytes, it means we are loading all
9880 // zeros. This should have been optimized before in the process.
9881 assert(TySizeInBytes > Offset &&
9882 "Invalid shift amount for given loaded size");
9884 Offset = TySizeInBytes - Offset - getLoadedSize();
9888 /// \brief Generate the sequence of instructions to load the slice
9889 /// represented by this object and redirect the uses of this slice to
9890 /// this new sequence of instructions.
9891 /// \pre this->Inst && this->Origin are valid Instructions and this
9892 /// object passed the legal check: LoadedSlice::isLegal returned true.
9893 /// \return The last instruction of the sequence used to load the slice.
9894 SDValue loadSlice() const {
9895 assert(Inst && Origin && "Unable to replace a non-existing slice.");
9896 const SDValue &OldBaseAddr = Origin->getBasePtr();
9897 SDValue BaseAddr = OldBaseAddr;
9898 // Get the offset in that chunk of bytes w.r.t. the endianess.
9899 int64_t Offset = static_cast<int64_t>(getOffsetFromBase());
9900 assert(Offset >= 0 && "Offset too big to fit in int64_t!");
9902 // BaseAddr = BaseAddr + Offset.
9903 EVT ArithType = BaseAddr.getValueType();
9905 BaseAddr = DAG->getNode(ISD::ADD, DL, ArithType, BaseAddr,
9906 DAG->getConstant(Offset, DL, ArithType));
9909 // Create the type of the loaded slice according to its size.
9910 EVT SliceType = getLoadedType();
9912 // Create the load for the slice.
9913 SDValue LastInst = DAG->getLoad(
9914 SliceType, SDLoc(Origin), Origin->getChain(), BaseAddr,
9915 Origin->getPointerInfo().getWithOffset(Offset), Origin->isVolatile(),
9916 Origin->isNonTemporal(), Origin->isInvariant(), getAlignment());
9917 // If the final type is not the same as the loaded type, this means that
9918 // we have to pad with zero. Create a zero extend for that.
9919 EVT FinalType = Inst->getValueType(0);
9920 if (SliceType != FinalType)
9922 DAG->getNode(ISD::ZERO_EXTEND, SDLoc(LastInst), FinalType, LastInst);
9926 /// \brief Check if this slice can be merged with an expensive cross register
9927 /// bank copy. E.g.,
9929 /// f = bitcast i32 i to float
9930 bool canMergeExpensiveCrossRegisterBankCopy() const {
9931 if (!Inst || !Inst->hasOneUse())
9933 SDNode *Use = *Inst->use_begin();
9934 if (Use->getOpcode() != ISD::BITCAST)
9936 assert(DAG && "Missing context");
9937 const TargetLowering &TLI = DAG->getTargetLoweringInfo();
9938 EVT ResVT = Use->getValueType(0);
9939 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT());
9940 const TargetRegisterClass *ArgRC =
9941 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT());
9942 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
9945 // At this point, we know that we perform a cross-register-bank copy.
9946 // Check if it is expensive.
9947 const TargetRegisterInfo *TRI = DAG->getSubtarget().getRegisterInfo();
9948 // Assume bitcasts are cheap, unless both register classes do not
9949 // explicitly share a common sub class.
9950 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC))
9953 // Check if it will be merged with the load.
9954 // 1. Check the alignment constraint.
9955 unsigned RequiredAlignment = DAG->getDataLayout().getABITypeAlignment(
9956 ResVT.getTypeForEVT(*DAG->getContext()));
9958 if (RequiredAlignment > getAlignment())
9961 // 2. Check that the load is a legal operation for that type.
9962 if (!TLI.isOperationLegal(ISD::LOAD, ResVT))
9965 // 3. Check that we do not have a zext in the way.
9966 if (Inst->getValueType(0) != getLoadedType())
9974 /// \brief Check that all bits set in \p UsedBits form a dense region, i.e.,
9975 /// \p UsedBits looks like 0..0 1..1 0..0.
9976 static bool areUsedBitsDense(const APInt &UsedBits) {
9977 // If all the bits are one, this is dense!
9978 if (UsedBits.isAllOnesValue())
9981 // Get rid of the unused bits on the right.
9982 APInt NarrowedUsedBits = UsedBits.lshr(UsedBits.countTrailingZeros());
9983 // Get rid of the unused bits on the left.
9984 if (NarrowedUsedBits.countLeadingZeros())
9985 NarrowedUsedBits = NarrowedUsedBits.trunc(NarrowedUsedBits.getActiveBits());
9986 // Check that the chunk of bits is completely used.
9987 return NarrowedUsedBits.isAllOnesValue();
9990 /// \brief Check whether or not \p First and \p Second are next to each other
9991 /// in memory. This means that there is no hole between the bits loaded
9992 /// by \p First and the bits loaded by \p Second.
9993 static bool areSlicesNextToEachOther(const LoadedSlice &First,
9994 const LoadedSlice &Second) {
9995 assert(First.Origin == Second.Origin && First.Origin &&
9996 "Unable to match different memory origins.");
9997 APInt UsedBits = First.getUsedBits();
9998 assert((UsedBits & Second.getUsedBits()) == 0 &&
9999 "Slices are not supposed to overlap.");
10000 UsedBits |= Second.getUsedBits();
10001 return areUsedBitsDense(UsedBits);
10004 /// \brief Adjust the \p GlobalLSCost according to the target
10005 /// paring capabilities and the layout of the slices.
10006 /// \pre \p GlobalLSCost should account for at least as many loads as
10007 /// there is in the slices in \p LoadedSlices.
10008 static void adjustCostForPairing(SmallVectorImpl<LoadedSlice> &LoadedSlices,
10009 LoadedSlice::Cost &GlobalLSCost) {
10010 unsigned NumberOfSlices = LoadedSlices.size();
10011 // If there is less than 2 elements, no pairing is possible.
10012 if (NumberOfSlices < 2)
10015 // Sort the slices so that elements that are likely to be next to each
10016 // other in memory are next to each other in the list.
10017 std::sort(LoadedSlices.begin(), LoadedSlices.end(),
10018 [](const LoadedSlice &LHS, const LoadedSlice &RHS) {
10019 assert(LHS.Origin == RHS.Origin && "Different bases not implemented.");
10020 return LHS.getOffsetFromBase() < RHS.getOffsetFromBase();
10022 const TargetLowering &TLI = LoadedSlices[0].DAG->getTargetLoweringInfo();
10023 // First (resp. Second) is the first (resp. Second) potentially candidate
10024 // to be placed in a paired load.
10025 const LoadedSlice *First = nullptr;
10026 const LoadedSlice *Second = nullptr;
10027 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice,
10028 // Set the beginning of the pair.
10031 Second = &LoadedSlices[CurrSlice];
10033 // If First is NULL, it means we start a new pair.
10034 // Get to the next slice.
10038 EVT LoadedType = First->getLoadedType();
10040 // If the types of the slices are different, we cannot pair them.
10041 if (LoadedType != Second->getLoadedType())
10044 // Check if the target supplies paired loads for this type.
10045 unsigned RequiredAlignment = 0;
10046 if (!TLI.hasPairedLoad(LoadedType, RequiredAlignment)) {
10047 // move to the next pair, this type is hopeless.
10051 // Check if we meet the alignment requirement.
10052 if (RequiredAlignment > First->getAlignment())
10055 // Check that both loads are next to each other in memory.
10056 if (!areSlicesNextToEachOther(*First, *Second))
10059 assert(GlobalLSCost.Loads > 0 && "We save more loads than we created!");
10060 --GlobalLSCost.Loads;
10061 // Move to the next pair.
10066 /// \brief Check the profitability of all involved LoadedSlice.
10067 /// Currently, it is considered profitable if there is exactly two
10068 /// involved slices (1) which are (2) next to each other in memory, and
10069 /// whose cost (\see LoadedSlice::Cost) is smaller than the original load (3).
10071 /// Note: The order of the elements in \p LoadedSlices may be modified, but not
10072 /// the elements themselves.
10074 /// FIXME: When the cost model will be mature enough, we can relax
10075 /// constraints (1) and (2).
10076 static bool isSlicingProfitable(SmallVectorImpl<LoadedSlice> &LoadedSlices,
10077 const APInt &UsedBits, bool ForCodeSize) {
10078 unsigned NumberOfSlices = LoadedSlices.size();
10079 if (StressLoadSlicing)
10080 return NumberOfSlices > 1;
10083 if (NumberOfSlices != 2)
10087 if (!areUsedBitsDense(UsedBits))
10091 LoadedSlice::Cost OrigCost(ForCodeSize), GlobalSlicingCost(ForCodeSize);
10092 // The original code has one big load.
10093 OrigCost.Loads = 1;
10094 for (unsigned CurrSlice = 0; CurrSlice < NumberOfSlices; ++CurrSlice) {
10095 const LoadedSlice &LS = LoadedSlices[CurrSlice];
10096 // Accumulate the cost of all the slices.
10097 LoadedSlice::Cost SliceCost(LS, ForCodeSize);
10098 GlobalSlicingCost += SliceCost;
10100 // Account as cost in the original configuration the gain obtained
10101 // with the current slices.
10102 OrigCost.addSliceGain(LS);
10105 // If the target supports paired load, adjust the cost accordingly.
10106 adjustCostForPairing(LoadedSlices, GlobalSlicingCost);
10107 return OrigCost > GlobalSlicingCost;
10110 /// \brief If the given load, \p LI, is used only by trunc or trunc(lshr)
10111 /// operations, split it in the various pieces being extracted.
10113 /// This sort of thing is introduced by SROA.
10114 /// This slicing takes care not to insert overlapping loads.
10115 /// \pre LI is a simple load (i.e., not an atomic or volatile load).
10116 bool DAGCombiner::SliceUpLoad(SDNode *N) {
10117 if (Level < AfterLegalizeDAG)
10120 LoadSDNode *LD = cast<LoadSDNode>(N);
10121 if (LD->isVolatile() || !ISD::isNormalLoad(LD) ||
10122 !LD->getValueType(0).isInteger())
10125 // Keep track of already used bits to detect overlapping values.
10126 // In that case, we will just abort the transformation.
10127 APInt UsedBits(LD->getValueSizeInBits(0), 0);
10129 SmallVector<LoadedSlice, 4> LoadedSlices;
10131 // Check if this load is used as several smaller chunks of bits.
10132 // Basically, look for uses in trunc or trunc(lshr) and record a new chain
10133 // of computation for each trunc.
10134 for (SDNode::use_iterator UI = LD->use_begin(), UIEnd = LD->use_end();
10135 UI != UIEnd; ++UI) {
10136 // Skip the uses of the chain.
10137 if (UI.getUse().getResNo() != 0)
10140 SDNode *User = *UI;
10141 unsigned Shift = 0;
10143 // Check if this is a trunc(lshr).
10144 if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
10145 isa<ConstantSDNode>(User->getOperand(1))) {
10146 Shift = cast<ConstantSDNode>(User->getOperand(1))->getZExtValue();
10147 User = *User->use_begin();
10150 // At this point, User is a Truncate, iff we encountered, trunc or
10152 if (User->getOpcode() != ISD::TRUNCATE)
10155 // The width of the type must be a power of 2 and greater than 8-bits.
10156 // Otherwise the load cannot be represented in LLVM IR.
10157 // Moreover, if we shifted with a non-8-bits multiple, the slice
10158 // will be across several bytes. We do not support that.
10159 unsigned Width = User->getValueSizeInBits(0);
10160 if (Width < 8 || !isPowerOf2_32(Width) || (Shift & 0x7))
10163 // Build the slice for this chain of computations.
10164 LoadedSlice LS(User, LD, Shift, &DAG);
10165 APInt CurrentUsedBits = LS.getUsedBits();
10167 // Check if this slice overlaps with another.
10168 if ((CurrentUsedBits & UsedBits) != 0)
10170 // Update the bits used globally.
10171 UsedBits |= CurrentUsedBits;
10173 // Check if the new slice would be legal.
10177 // Record the slice.
10178 LoadedSlices.push_back(LS);
10181 // Abort slicing if it does not seem to be profitable.
10182 if (!isSlicingProfitable(LoadedSlices, UsedBits, ForCodeSize))
10187 // Rewrite each chain to use an independent load.
10188 // By construction, each chain can be represented by a unique load.
10190 // Prepare the argument for the new token factor for all the slices.
10191 SmallVector<SDValue, 8> ArgChains;
10192 for (SmallVectorImpl<LoadedSlice>::const_iterator
10193 LSIt = LoadedSlices.begin(),
10194 LSItEnd = LoadedSlices.end();
10195 LSIt != LSItEnd; ++LSIt) {
10196 SDValue SliceInst = LSIt->loadSlice();
10197 CombineTo(LSIt->Inst, SliceInst, true);
10198 if (SliceInst.getNode()->getOpcode() != ISD::LOAD)
10199 SliceInst = SliceInst.getOperand(0);
10200 assert(SliceInst->getOpcode() == ISD::LOAD &&
10201 "It takes more than a zext to get to the loaded slice!!");
10202 ArgChains.push_back(SliceInst.getValue(1));
10205 SDValue Chain = DAG.getNode(ISD::TokenFactor, SDLoc(LD), MVT::Other,
10207 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain);
10211 /// Check to see if V is (and load (ptr), imm), where the load is having
10212 /// specific bytes cleared out. If so, return the byte size being masked out
10213 /// and the shift amount.
10214 static std::pair<unsigned, unsigned>
10215 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
10216 std::pair<unsigned, unsigned> Result(0, 0);
10218 // Check for the structure we're looking for.
10219 if (V->getOpcode() != ISD::AND ||
10220 !isa<ConstantSDNode>(V->getOperand(1)) ||
10221 !ISD::isNormalLoad(V->getOperand(0).getNode()))
10224 // Check the chain and pointer.
10225 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
10226 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
10228 // The store should be chained directly to the load or be an operand of a
10230 if (LD == Chain.getNode())
10232 else if (Chain->getOpcode() != ISD::TokenFactor)
10233 return Result; // Fail.
10236 for (const SDValue &ChainOp : Chain->op_values())
10237 if (ChainOp.getNode() == LD) {
10241 if (!isOk) return Result;
10244 // This only handles simple types.
10245 if (V.getValueType() != MVT::i16 &&
10246 V.getValueType() != MVT::i32 &&
10247 V.getValueType() != MVT::i64)
10250 // Check the constant mask. Invert it so that the bits being masked out are
10251 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
10252 // follow the sign bit for uniformity.
10253 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
10254 unsigned NotMaskLZ = countLeadingZeros(NotMask);
10255 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
10256 unsigned NotMaskTZ = countTrailingZeros(NotMask);
10257 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
10258 if (NotMaskLZ == 64) return Result; // All zero mask.
10260 // See if we have a continuous run of bits. If so, we have 0*1+0*
10261 if (countTrailingOnes(NotMask >> NotMaskTZ) + NotMaskTZ + NotMaskLZ != 64)
10264 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
10265 if (V.getValueType() != MVT::i64 && NotMaskLZ)
10266 NotMaskLZ -= 64-V.getValueSizeInBits();
10268 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
10269 switch (MaskedBytes) {
10273 default: return Result; // All one mask, or 5-byte mask.
10276 // Verify that the first bit starts at a multiple of mask so that the access
10277 // is aligned the same as the access width.
10278 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
10280 Result.first = MaskedBytes;
10281 Result.second = NotMaskTZ/8;
10286 /// Check to see if IVal is something that provides a value as specified by
10287 /// MaskInfo. If so, replace the specified store with a narrower store of
10288 /// truncated IVal.
10290 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
10291 SDValue IVal, StoreSDNode *St,
10293 unsigned NumBytes = MaskInfo.first;
10294 unsigned ByteShift = MaskInfo.second;
10295 SelectionDAG &DAG = DC->getDAG();
10297 // Check to see if IVal is all zeros in the part being masked in by the 'or'
10298 // that uses this. If not, this is not a replacement.
10299 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
10300 ByteShift*8, (ByteShift+NumBytes)*8);
10301 if (!DAG.MaskedValueIsZero(IVal, Mask)) return nullptr;
10303 // Check that it is legal on the target to do this. It is legal if the new
10304 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
10306 MVT VT = MVT::getIntegerVT(NumBytes*8);
10307 if (!DC->isTypeLegal(VT))
10310 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
10311 // shifted by ByteShift and truncated down to NumBytes.
10314 IVal = DAG.getNode(ISD::SRL, DL, IVal.getValueType(), IVal,
10315 DAG.getConstant(ByteShift*8, DL,
10316 DC->getShiftAmountTy(IVal.getValueType())));
10319 // Figure out the offset for the store and the alignment of the access.
10321 unsigned NewAlign = St->getAlignment();
10323 if (DAG.getDataLayout().isLittleEndian())
10324 StOffset = ByteShift;
10326 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
10328 SDValue Ptr = St->getBasePtr();
10331 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(),
10332 Ptr, DAG.getConstant(StOffset, DL, Ptr.getValueType()));
10333 NewAlign = MinAlign(NewAlign, StOffset);
10336 // Truncate down to the new size.
10337 IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal);
10340 return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr,
10341 St->getPointerInfo().getWithOffset(StOffset),
10342 false, false, NewAlign).getNode();
10346 /// Look for sequence of load / op / store where op is one of 'or', 'xor', and
10347 /// 'and' of immediates. If 'op' is only touching some of the loaded bits, try
10348 /// narrowing the load and store if it would end up being a win for performance
10350 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
10351 StoreSDNode *ST = cast<StoreSDNode>(N);
10352 if (ST->isVolatile())
10355 SDValue Chain = ST->getChain();
10356 SDValue Value = ST->getValue();
10357 SDValue Ptr = ST->getBasePtr();
10358 EVT VT = Value.getValueType();
10360 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
10363 unsigned Opc = Value.getOpcode();
10365 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
10366 // is a byte mask indicating a consecutive number of bytes, check to see if
10367 // Y is known to provide just those bytes. If so, we try to replace the
10368 // load + replace + store sequence with a single (narrower) store, which makes
10370 if (Opc == ISD::OR) {
10371 std::pair<unsigned, unsigned> MaskedLoad;
10372 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
10373 if (MaskedLoad.first)
10374 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
10375 Value.getOperand(1), ST,this))
10376 return SDValue(NewST, 0);
10378 // Or is commutative, so try swapping X and Y.
10379 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
10380 if (MaskedLoad.first)
10381 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
10382 Value.getOperand(0), ST,this))
10383 return SDValue(NewST, 0);
10386 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
10387 Value.getOperand(1).getOpcode() != ISD::Constant)
10390 SDValue N0 = Value.getOperand(0);
10391 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
10392 Chain == SDValue(N0.getNode(), 1)) {
10393 LoadSDNode *LD = cast<LoadSDNode>(N0);
10394 if (LD->getBasePtr() != Ptr ||
10395 LD->getPointerInfo().getAddrSpace() !=
10396 ST->getPointerInfo().getAddrSpace())
10399 // Find the type to narrow it the load / op / store to.
10400 SDValue N1 = Value.getOperand(1);
10401 unsigned BitWidth = N1.getValueSizeInBits();
10402 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
10403 if (Opc == ISD::AND)
10404 Imm ^= APInt::getAllOnesValue(BitWidth);
10405 if (Imm == 0 || Imm.isAllOnesValue())
10407 unsigned ShAmt = Imm.countTrailingZeros();
10408 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
10409 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
10410 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
10411 // The narrowing should be profitable, the load/store operation should be
10412 // legal (or custom) and the store size should be equal to the NewVT width.
10413 while (NewBW < BitWidth &&
10414 (NewVT.getStoreSizeInBits() != NewBW ||
10415 !TLI.isOperationLegalOrCustom(Opc, NewVT) ||
10416 !TLI.isNarrowingProfitable(VT, NewVT))) {
10417 NewBW = NextPowerOf2(NewBW);
10418 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
10420 if (NewBW >= BitWidth)
10423 // If the lsb changed does not start at the type bitwidth boundary,
10424 // start at the previous one.
10426 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
10427 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt,
10428 std::min(BitWidth, ShAmt + NewBW));
10429 if ((Imm & Mask) == Imm) {
10430 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
10431 if (Opc == ISD::AND)
10432 NewImm ^= APInt::getAllOnesValue(NewBW);
10433 uint64_t PtrOff = ShAmt / 8;
10434 // For big endian targets, we need to adjust the offset to the pointer to
10435 // load the correct bytes.
10436 if (DAG.getDataLayout().isBigEndian())
10437 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
10439 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
10440 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
10441 if (NewAlign < DAG.getDataLayout().getABITypeAlignment(NewVTTy))
10444 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD),
10445 Ptr.getValueType(), Ptr,
10446 DAG.getConstant(PtrOff, SDLoc(LD),
10447 Ptr.getValueType()));
10448 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0),
10449 LD->getChain(), NewPtr,
10450 LD->getPointerInfo().getWithOffset(PtrOff),
10451 LD->isVolatile(), LD->isNonTemporal(),
10452 LD->isInvariant(), NewAlign,
10454 SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD,
10455 DAG.getConstant(NewImm, SDLoc(Value),
10457 SDValue NewST = DAG.getStore(Chain, SDLoc(N),
10459 ST->getPointerInfo().getWithOffset(PtrOff),
10460 false, false, NewAlign);
10462 AddToWorklist(NewPtr.getNode());
10463 AddToWorklist(NewLD.getNode());
10464 AddToWorklist(NewVal.getNode());
10465 WorklistRemover DeadNodes(*this);
10466 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1));
10475 /// For a given floating point load / store pair, if the load value isn't used
10476 /// by any other operations, then consider transforming the pair to integer
10477 /// load / store operations if the target deems the transformation profitable.
10478 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
10479 StoreSDNode *ST = cast<StoreSDNode>(N);
10480 SDValue Chain = ST->getChain();
10481 SDValue Value = ST->getValue();
10482 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
10483 Value.hasOneUse() &&
10484 Chain == SDValue(Value.getNode(), 1)) {
10485 LoadSDNode *LD = cast<LoadSDNode>(Value);
10486 EVT VT = LD->getMemoryVT();
10487 if (!VT.isFloatingPoint() ||
10488 VT != ST->getMemoryVT() ||
10489 LD->isNonTemporal() ||
10490 ST->isNonTemporal() ||
10491 LD->getPointerInfo().getAddrSpace() != 0 ||
10492 ST->getPointerInfo().getAddrSpace() != 0)
10495 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
10496 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
10497 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
10498 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
10499 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
10502 unsigned LDAlign = LD->getAlignment();
10503 unsigned STAlign = ST->getAlignment();
10504 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
10505 unsigned ABIAlign = DAG.getDataLayout().getABITypeAlignment(IntVTTy);
10506 if (LDAlign < ABIAlign || STAlign < ABIAlign)
10509 SDValue NewLD = DAG.getLoad(IntVT, SDLoc(Value),
10510 LD->getChain(), LD->getBasePtr(),
10511 LD->getPointerInfo(),
10512 false, false, false, LDAlign);
10514 SDValue NewST = DAG.getStore(NewLD.getValue(1), SDLoc(N),
10515 NewLD, ST->getBasePtr(),
10516 ST->getPointerInfo(),
10517 false, false, STAlign);
10519 AddToWorklist(NewLD.getNode());
10520 AddToWorklist(NewST.getNode());
10521 WorklistRemover DeadNodes(*this);
10522 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1));
10531 /// Helper struct to parse and store a memory address as base + index + offset.
10532 /// We ignore sign extensions when it is safe to do so.
10533 /// The following two expressions are not equivalent. To differentiate we need
10534 /// to store whether there was a sign extension involved in the index
10536 /// (load (i64 add (i64 copyfromreg %c)
10537 /// (i64 signextend (add (i8 load %index)
10541 /// (load (i64 add (i64 copyfromreg %c)
10542 /// (i64 signextend (i32 add (i32 signextend (i8 load %index))
10544 struct BaseIndexOffset {
10548 bool IsIndexSignExt;
10550 BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
10552 BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
10553 bool IsIndexSignExt) :
10554 Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {}
10556 bool equalBaseIndex(const BaseIndexOffset &Other) {
10557 return Other.Base == Base && Other.Index == Index &&
10558 Other.IsIndexSignExt == IsIndexSignExt;
10561 /// Parses tree in Ptr for base, index, offset addresses.
10562 static BaseIndexOffset match(SDValue Ptr) {
10563 bool IsIndexSignExt = false;
10565 // We only can pattern match BASE + INDEX + OFFSET. If Ptr is not an ADD
10566 // instruction, then it could be just the BASE or everything else we don't
10567 // know how to handle. Just use Ptr as BASE and give up.
10568 if (Ptr->getOpcode() != ISD::ADD)
10569 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
10571 // We know that we have at least an ADD instruction. Try to pattern match
10572 // the simple case of BASE + OFFSET.
10573 if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
10574 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
10575 return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
10579 // Inside a loop the current BASE pointer is calculated using an ADD and a
10580 // MUL instruction. In this case Ptr is the actual BASE pointer.
10581 // (i64 add (i64 %array_ptr)
10582 // (i64 mul (i64 %induction_var)
10583 // (i64 %element_size)))
10584 if (Ptr->getOperand(1)->getOpcode() == ISD::MUL)
10585 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
10587 // Look at Base + Index + Offset cases.
10588 SDValue Base = Ptr->getOperand(0);
10589 SDValue IndexOffset = Ptr->getOperand(1);
10591 // Skip signextends.
10592 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
10593 IndexOffset = IndexOffset->getOperand(0);
10594 IsIndexSignExt = true;
10597 // Either the case of Base + Index (no offset) or something else.
10598 if (IndexOffset->getOpcode() != ISD::ADD)
10599 return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt);
10601 // Now we have the case of Base + Index + offset.
10602 SDValue Index = IndexOffset->getOperand(0);
10603 SDValue Offset = IndexOffset->getOperand(1);
10605 if (!isa<ConstantSDNode>(Offset))
10606 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
10608 // Ignore signextends.
10609 if (Index->getOpcode() == ISD::SIGN_EXTEND) {
10610 Index = Index->getOperand(0);
10611 IsIndexSignExt = true;
10612 } else IsIndexSignExt = false;
10614 int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
10615 return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
10620 SDValue DAGCombiner::getMergedConstantVectorStore(SelectionDAG &DAG,
10622 ArrayRef<MemOpLink> Stores,
10624 SmallVector<SDValue, 8> BuildVector;
10626 for (unsigned I = 0, E = Ty.getVectorNumElements(); I != E; ++I)
10627 BuildVector.push_back(cast<StoreSDNode>(Stores[I].MemNode)->getValue());
10629 return DAG.getNode(ISD::BUILD_VECTOR, SL, Ty, BuildVector);
10632 bool DAGCombiner::MergeStoresOfConstantsOrVecElts(
10633 SmallVectorImpl<MemOpLink> &StoreNodes, EVT MemVT,
10634 unsigned NumElem, bool IsConstantSrc, bool UseVector) {
10635 // Make sure we have something to merge.
10639 int64_t ElementSizeBytes = MemVT.getSizeInBits() / 8;
10640 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
10641 unsigned LatestNodeUsed = 0;
10643 for (unsigned i=0; i < NumElem; ++i) {
10644 // Find a chain for the new wide-store operand. Notice that some
10645 // of the store nodes that we found may not be selected for inclusion
10646 // in the wide store. The chain we use needs to be the chain of the
10647 // latest store node which is *used* and replaced by the wide store.
10648 if (StoreNodes[i].SequenceNum < StoreNodes[LatestNodeUsed].SequenceNum)
10649 LatestNodeUsed = i;
10652 // The latest Node in the DAG.
10653 LSBaseSDNode *LatestOp = StoreNodes[LatestNodeUsed].MemNode;
10654 SDLoc DL(StoreNodes[0].MemNode);
10658 // Find a legal type for the vector store.
10659 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem);
10660 assert(TLI.isTypeLegal(Ty) && "Illegal vector store");
10661 if (IsConstantSrc) {
10662 StoredVal = getMergedConstantVectorStore(DAG, DL, StoreNodes, Ty);
10664 SmallVector<SDValue, 8> Ops;
10665 for (unsigned i = 0; i < NumElem ; ++i) {
10666 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
10667 SDValue Val = St->getValue();
10668 // All of the operands of a BUILD_VECTOR must have the same type.
10669 if (Val.getValueType() != MemVT)
10671 Ops.push_back(Val);
10674 // Build the extracted vector elements back into a vector.
10675 StoredVal = DAG.getNode(ISD::BUILD_VECTOR, DL, Ty, Ops);
10678 // We should always use a vector store when merging extracted vector
10679 // elements, so this path implies a store of constants.
10680 assert(IsConstantSrc && "Merged vector elements should use vector store");
10682 unsigned SizeInBits = NumElem * ElementSizeBytes * 8;
10683 APInt StoreInt(SizeInBits, 0);
10685 // Construct a single integer constant which is made of the smaller
10686 // constant inputs.
10687 bool IsLE = DAG.getDataLayout().isLittleEndian();
10688 for (unsigned i = 0; i < NumElem ; ++i) {
10689 unsigned Idx = IsLE ? (NumElem - 1 - i) : i;
10690 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode);
10691 SDValue Val = St->getValue();
10692 StoreInt <<= ElementSizeBytes * 8;
10693 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
10694 StoreInt |= C->getAPIntValue().zext(SizeInBits);
10695 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
10696 StoreInt |= C->getValueAPF().bitcastToAPInt().zext(SizeInBits);
10698 llvm_unreachable("Invalid constant element type");
10702 // Create the new Load and Store operations.
10703 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), SizeInBits);
10704 StoredVal = DAG.getConstant(StoreInt, DL, StoreTy);
10707 SDValue NewStore = DAG.getStore(LatestOp->getChain(), DL, StoredVal,
10708 FirstInChain->getBasePtr(),
10709 FirstInChain->getPointerInfo(),
10711 FirstInChain->getAlignment());
10713 // Replace the last store with the new store
10714 CombineTo(LatestOp, NewStore);
10715 // Erase all other stores.
10716 for (unsigned i = 0; i < NumElem ; ++i) {
10717 if (StoreNodes[i].MemNode == LatestOp)
10719 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
10720 // ReplaceAllUsesWith will replace all uses that existed when it was
10721 // called, but graph optimizations may cause new ones to appear. For
10722 // example, the case in pr14333 looks like
10724 // St's chain -> St -> another store -> X
10726 // And the only difference from St to the other store is the chain.
10727 // When we change it's chain to be St's chain they become identical,
10728 // get CSEed and the net result is that X is now a use of St.
10729 // Since we know that St is redundant, just iterate.
10730 while (!St->use_empty())
10731 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain());
10732 deleteAndRecombine(St);
10738 void DAGCombiner::getStoreMergeAndAliasCandidates(
10739 StoreSDNode* St, SmallVectorImpl<MemOpLink> &StoreNodes,
10740 SmallVectorImpl<LSBaseSDNode*> &AliasLoadNodes) {
10741 // This holds the base pointer, index, and the offset in bytes from the base
10743 BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr());
10745 // We must have a base and an offset.
10746 if (!BasePtr.Base.getNode())
10749 // Do not handle stores to undef base pointers.
10750 if (BasePtr.Base.getOpcode() == ISD::UNDEF)
10753 // Walk up the chain and look for nodes with offsets from the same
10754 // base pointer. Stop when reaching an instruction with a different kind
10755 // or instruction which has a different base pointer.
10756 EVT MemVT = St->getMemoryVT();
10758 StoreSDNode *Index = St;
10760 // If the chain has more than one use, then we can't reorder the mem ops.
10761 if (Index != St && !SDValue(Index, 0)->hasOneUse())
10764 // Find the base pointer and offset for this memory node.
10765 BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr());
10767 // Check that the base pointer is the same as the original one.
10768 if (!Ptr.equalBaseIndex(BasePtr))
10771 // The memory operands must not be volatile.
10772 if (Index->isVolatile() || Index->isIndexed())
10776 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index))
10777 if (St->isTruncatingStore())
10780 // The stored memory type must be the same.
10781 if (Index->getMemoryVT() != MemVT)
10784 // We found a potential memory operand to merge.
10785 StoreNodes.push_back(MemOpLink(Index, Ptr.Offset, Seq++));
10787 // Find the next memory operand in the chain. If the next operand in the
10788 // chain is a store then move up and continue the scan with the next
10789 // memory operand. If the next operand is a load save it and use alias
10790 // information to check if it interferes with anything.
10791 SDNode *NextInChain = Index->getChain().getNode();
10793 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) {
10794 // We found a store node. Use it for the next iteration.
10797 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) {
10798 if (Ldn->isVolatile()) {
10803 // Save the load node for later. Continue the scan.
10804 AliasLoadNodes.push_back(Ldn);
10805 NextInChain = Ldn->getChain().getNode();
10815 bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) {
10816 if (OptLevel == CodeGenOpt::None)
10819 EVT MemVT = St->getMemoryVT();
10820 int64_t ElementSizeBytes = MemVT.getSizeInBits() / 8;
10821 bool NoVectors = DAG.getMachineFunction().getFunction()->hasFnAttribute(
10822 Attribute::NoImplicitFloat);
10824 // This function cannot currently deal with non-byte-sized memory sizes.
10825 if (ElementSizeBytes * 8 != MemVT.getSizeInBits())
10828 // Don't merge vectors into wider inputs.
10829 if (MemVT.isVector() || !MemVT.isSimple())
10832 // Perform an early exit check. Do not bother looking at stored values that
10833 // are not constants, loads, or extracted vector elements.
10834 SDValue StoredVal = St->getValue();
10835 bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
10836 bool IsConstantSrc = isa<ConstantSDNode>(StoredVal) ||
10837 isa<ConstantFPSDNode>(StoredVal);
10838 bool IsExtractVecEltSrc = (StoredVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT);
10840 if (!IsConstantSrc && !IsLoadSrc && !IsExtractVecEltSrc)
10843 // Only look at ends of store sequences.
10844 SDValue Chain = SDValue(St, 0);
10845 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE)
10848 // Save the LoadSDNodes that we find in the chain.
10849 // We need to make sure that these nodes do not interfere with
10850 // any of the store nodes.
10851 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes;
10853 // Save the StoreSDNodes that we find in the chain.
10854 SmallVector<MemOpLink, 8> StoreNodes;
10856 getStoreMergeAndAliasCandidates(St, StoreNodes, AliasLoadNodes);
10858 // Check if there is anything to merge.
10859 if (StoreNodes.size() < 2)
10862 // Sort the memory operands according to their distance from the base pointer.
10863 std::sort(StoreNodes.begin(), StoreNodes.end(),
10864 [](MemOpLink LHS, MemOpLink RHS) {
10865 return LHS.OffsetFromBase < RHS.OffsetFromBase ||
10866 (LHS.OffsetFromBase == RHS.OffsetFromBase &&
10867 LHS.SequenceNum > RHS.SequenceNum);
10870 // Scan the memory operations on the chain and find the first non-consecutive
10871 // store memory address.
10872 unsigned LastConsecutiveStore = 0;
10873 int64_t StartAddress = StoreNodes[0].OffsetFromBase;
10874 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) {
10876 // Check that the addresses are consecutive starting from the second
10877 // element in the list of stores.
10879 int64_t CurrAddress = StoreNodes[i].OffsetFromBase;
10880 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
10884 bool Alias = false;
10885 // Check if this store interferes with any of the loads that we found.
10886 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld)
10887 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) {
10891 // We found a load that alias with this store. Stop the sequence.
10895 // Mark this node as useful.
10896 LastConsecutiveStore = i;
10899 // The node with the lowest store address.
10900 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode;
10901 unsigned FirstStoreAS = FirstInChain->getAddressSpace();
10902 unsigned FirstStoreAlign = FirstInChain->getAlignment();
10903 LLVMContext &Context = *DAG.getContext();
10904 const DataLayout &DL = DAG.getDataLayout();
10906 // Store the constants into memory as one consecutive store.
10907 if (IsConstantSrc) {
10908 unsigned LastLegalType = 0;
10909 unsigned LastLegalVectorType = 0;
10910 bool NonZero = false;
10911 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
10912 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
10913 SDValue StoredVal = St->getValue();
10915 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
10916 NonZero |= !C->isNullValue();
10917 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
10918 NonZero |= !C->getConstantFPValue()->isNullValue();
10924 // Find a legal type for the constant store.
10925 unsigned SizeInBits = (i+1) * ElementSizeBytes * 8;
10926 EVT StoreTy = EVT::getIntegerVT(Context, SizeInBits);
10927 if (TLI.isTypeLegal(StoreTy) &&
10928 TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstStoreAS,
10929 FirstStoreAlign)) {
10930 LastLegalType = i+1;
10931 // Or check whether a truncstore is legal.
10932 } else if (TLI.getTypeAction(Context, StoreTy) ==
10933 TargetLowering::TypePromoteInteger) {
10934 EVT LegalizedStoredValueTy =
10935 TLI.getTypeToTransformTo(Context, StoredVal.getValueType());
10936 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
10937 TLI.allowsMemoryAccess(Context, DL, LegalizedStoredValueTy,
10938 FirstStoreAS, FirstStoreAlign)) {
10939 LastLegalType = i + 1;
10943 // Find a legal type for the vector store.
10944 EVT Ty = EVT::getVectorVT(Context, MemVT, i+1);
10945 if (TLI.isTypeLegal(Ty) &&
10946 TLI.allowsMemoryAccess(Context, DL, Ty, FirstStoreAS,
10947 FirstStoreAlign)) {
10948 LastLegalVectorType = i + 1;
10953 // We only use vectors if the constant is known to be zero or the target
10954 // allows it and the function is not marked with the noimplicitfloat
10957 LastLegalVectorType = 0;
10958 } else if (NonZero && !TLI.storeOfVectorConstantIsCheap(MemVT,
10959 LastLegalVectorType,
10961 LastLegalVectorType = 0;
10964 // Check if we found a legal integer type to store.
10965 if (LastLegalType == 0 && LastLegalVectorType == 0)
10968 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors;
10969 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType;
10971 return MergeStoresOfConstantsOrVecElts(StoreNodes, MemVT, NumElem,
10975 // When extracting multiple vector elements, try to store them
10976 // in one vector store rather than a sequence of scalar stores.
10977 if (IsExtractVecEltSrc) {
10978 unsigned NumElem = 0;
10979 for (unsigned i = 0; i < LastConsecutiveStore + 1; ++i) {
10980 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
10981 SDValue StoredVal = St->getValue();
10982 // This restriction could be loosened.
10983 // Bail out if any stored values are not elements extracted from a vector.
10984 // It should be possible to handle mixed sources, but load sources need
10985 // more careful handling (see the block of code below that handles
10986 // consecutive loads).
10987 if (StoredVal.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
10990 // Find a legal type for the vector store.
10991 EVT Ty = EVT::getVectorVT(Context, MemVT, i+1);
10992 if (TLI.isTypeLegal(Ty) &&
10993 TLI.allowsMemoryAccess(Context, DL, Ty, FirstStoreAS,
10998 return MergeStoresOfConstantsOrVecElts(StoreNodes, MemVT, NumElem,
11002 // Below we handle the case of multiple consecutive stores that
11003 // come from multiple consecutive loads. We merge them into a single
11004 // wide load and a single wide store.
11006 // Look for load nodes which are used by the stored values.
11007 SmallVector<MemOpLink, 8> LoadNodes;
11009 // Find acceptable loads. Loads need to have the same chain (token factor),
11010 // must not be zext, volatile, indexed, and they must be consecutive.
11011 BaseIndexOffset LdBasePtr;
11012 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) {
11013 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
11014 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue());
11017 // Loads must only have one use.
11018 if (!Ld->hasNUsesOfValue(1, 0))
11021 // The memory operands must not be volatile.
11022 if (Ld->isVolatile() || Ld->isIndexed())
11025 // We do not accept ext loads.
11026 if (Ld->getExtensionType() != ISD::NON_EXTLOAD)
11029 // The stored memory type must be the same.
11030 if (Ld->getMemoryVT() != MemVT)
11033 BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld->getBasePtr());
11034 // If this is not the first ptr that we check.
11035 if (LdBasePtr.Base.getNode()) {
11036 // The base ptr must be the same.
11037 if (!LdPtr.equalBaseIndex(LdBasePtr))
11040 // Check that all other base pointers are the same as this one.
11044 // We found a potential memory operand to merge.
11045 LoadNodes.push_back(MemOpLink(Ld, LdPtr.Offset, 0));
11048 if (LoadNodes.size() < 2)
11051 // If we have load/store pair instructions and we only have two values,
11053 unsigned RequiredAlignment;
11054 if (LoadNodes.size() == 2 && TLI.hasPairedLoad(MemVT, RequiredAlignment) &&
11055 St->getAlignment() >= RequiredAlignment)
11058 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode);
11059 unsigned FirstLoadAS = FirstLoad->getAddressSpace();
11060 unsigned FirstLoadAlign = FirstLoad->getAlignment();
11062 // Scan the memory operations on the chain and find the first non-consecutive
11063 // load memory address. These variables hold the index in the store node
11065 unsigned LastConsecutiveLoad = 0;
11066 // This variable refers to the size and not index in the array.
11067 unsigned LastLegalVectorType = 0;
11068 unsigned LastLegalIntegerType = 0;
11069 StartAddress = LoadNodes[0].OffsetFromBase;
11070 SDValue FirstChain = FirstLoad->getChain();
11071 for (unsigned i = 1; i < LoadNodes.size(); ++i) {
11072 // All loads much share the same chain.
11073 if (LoadNodes[i].MemNode->getChain() != FirstChain)
11076 int64_t CurrAddress = LoadNodes[i].OffsetFromBase;
11077 if (CurrAddress - StartAddress != (ElementSizeBytes * i))
11079 LastConsecutiveLoad = i;
11081 // Find a legal type for the vector store.
11082 EVT StoreTy = EVT::getVectorVT(Context, MemVT, i+1);
11083 if (TLI.isTypeLegal(StoreTy) &&
11084 TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstStoreAS,
11085 FirstStoreAlign) &&
11086 TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstLoadAS,
11088 LastLegalVectorType = i + 1;
11091 // Find a legal type for the integer store.
11092 unsigned SizeInBits = (i+1) * ElementSizeBytes * 8;
11093 StoreTy = EVT::getIntegerVT(Context, SizeInBits);
11094 if (TLI.isTypeLegal(StoreTy) &&
11095 TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstStoreAS,
11096 FirstStoreAlign) &&
11097 TLI.allowsMemoryAccess(Context, DL, StoreTy, FirstLoadAS,
11099 LastLegalIntegerType = i + 1;
11100 // Or check whether a truncstore and extload is legal.
11101 else if (TLI.getTypeAction(Context, StoreTy) ==
11102 TargetLowering::TypePromoteInteger) {
11103 EVT LegalizedStoredValueTy =
11104 TLI.getTypeToTransformTo(Context, StoreTy);
11105 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) &&
11106 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
11107 TLI.isLoadExtLegal(ISD::SEXTLOAD, LegalizedStoredValueTy, StoreTy) &&
11108 TLI.isLoadExtLegal(ISD::EXTLOAD, LegalizedStoredValueTy, StoreTy) &&
11109 TLI.allowsMemoryAccess(Context, DL, LegalizedStoredValueTy,
11110 FirstStoreAS, FirstStoreAlign) &&
11111 TLI.allowsMemoryAccess(Context, DL, LegalizedStoredValueTy,
11112 FirstLoadAS, FirstLoadAlign))
11113 LastLegalIntegerType = i+1;
11117 // Only use vector types if the vector type is larger than the integer type.
11118 // If they are the same, use integers.
11119 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors;
11120 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType);
11122 // We add +1 here because the LastXXX variables refer to location while
11123 // the NumElem refers to array/index size.
11124 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1;
11125 NumElem = std::min(LastLegalType, NumElem);
11130 // The latest Node in the DAG.
11131 unsigned LatestNodeUsed = 0;
11132 for (unsigned i=1; i<NumElem; ++i) {
11133 // Find a chain for the new wide-store operand. Notice that some
11134 // of the store nodes that we found may not be selected for inclusion
11135 // in the wide store. The chain we use needs to be the chain of the
11136 // latest store node which is *used* and replaced by the wide store.
11137 if (StoreNodes[i].SequenceNum < StoreNodes[LatestNodeUsed].SequenceNum)
11138 LatestNodeUsed = i;
11141 LSBaseSDNode *LatestOp = StoreNodes[LatestNodeUsed].MemNode;
11143 // Find if it is better to use vectors or integers to load and store
11147 JointMemOpVT = EVT::getVectorVT(Context, MemVT, NumElem);
11149 unsigned SizeInBits = NumElem * ElementSizeBytes * 8;
11150 JointMemOpVT = EVT::getIntegerVT(Context, SizeInBits);
11153 SDLoc LoadDL(LoadNodes[0].MemNode);
11154 SDLoc StoreDL(StoreNodes[0].MemNode);
11156 SDValue NewLoad = DAG.getLoad(
11157 JointMemOpVT, LoadDL, FirstLoad->getChain(), FirstLoad->getBasePtr(),
11158 FirstLoad->getPointerInfo(), false, false, false, FirstLoadAlign);
11160 SDValue NewStore = DAG.getStore(
11161 LatestOp->getChain(), StoreDL, NewLoad, FirstInChain->getBasePtr(),
11162 FirstInChain->getPointerInfo(), false, false, FirstStoreAlign);
11164 // Replace one of the loads with the new load.
11165 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode);
11166 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1),
11167 SDValue(NewLoad.getNode(), 1));
11169 // Remove the rest of the load chains.
11170 for (unsigned i = 1; i < NumElem ; ++i) {
11171 // Replace all chain users of the old load nodes with the chain of the new
11173 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode);
11174 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain());
11177 // Replace the last store with the new store.
11178 CombineTo(LatestOp, NewStore);
11179 // Erase all other stores.
11180 for (unsigned i = 0; i < NumElem ; ++i) {
11181 // Remove all Store nodes.
11182 if (StoreNodes[i].MemNode == LatestOp)
11184 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode);
11185 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain());
11186 deleteAndRecombine(St);
11192 SDValue DAGCombiner::visitSTORE(SDNode *N) {
11193 StoreSDNode *ST = cast<StoreSDNode>(N);
11194 SDValue Chain = ST->getChain();
11195 SDValue Value = ST->getValue();
11196 SDValue Ptr = ST->getBasePtr();
11198 // If this is a store of a bit convert, store the input value if the
11199 // resultant store does not need a higher alignment than the original.
11200 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
11201 ST->isUnindexed()) {
11202 unsigned OrigAlign = ST->getAlignment();
11203 EVT SVT = Value.getOperand(0).getValueType();
11204 unsigned Align = DAG.getDataLayout().getABITypeAlignment(
11205 SVT.getTypeForEVT(*DAG.getContext()));
11206 if (Align <= OrigAlign &&
11207 ((!LegalOperations && !ST->isVolatile()) ||
11208 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
11209 return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0),
11210 Ptr, ST->getPointerInfo(), ST->isVolatile(),
11211 ST->isNonTemporal(), OrigAlign,
11215 // Turn 'store undef, Ptr' -> nothing.
11216 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
11219 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
11220 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
11221 // NOTE: If the original store is volatile, this transform must not increase
11222 // the number of stores. For example, on x86-32 an f64 can be stored in one
11223 // processor operation but an i64 (which is not legal) requires two. So the
11224 // transform should not be done in this case.
11225 if (Value.getOpcode() != ISD::TargetConstantFP) {
11227 switch (CFP->getSimpleValueType(0).SimpleTy) {
11228 default: llvm_unreachable("Unknown FP type");
11229 case MVT::f16: // We don't do this for these yet.
11235 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
11236 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
11238 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
11239 bitcastToAPInt().getZExtValue(), SDLoc(CFP),
11241 return DAG.getStore(Chain, SDLoc(N), Tmp,
11242 Ptr, ST->getMemOperand());
11246 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
11247 !ST->isVolatile()) ||
11248 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
11250 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
11251 getZExtValue(), SDLoc(CFP), MVT::i64);
11252 return DAG.getStore(Chain, SDLoc(N), Tmp,
11253 Ptr, ST->getMemOperand());
11256 if (!ST->isVolatile() &&
11257 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
11258 // Many FP stores are not made apparent until after legalize, e.g. for
11259 // argument passing. Since this is so common, custom legalize the
11260 // 64-bit integer store into two 32-bit stores.
11261 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
11262 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, SDLoc(CFP), MVT::i32);
11263 SDValue Hi = DAG.getConstant(Val >> 32, SDLoc(CFP), MVT::i32);
11264 if (DAG.getDataLayout().isBigEndian())
11267 unsigned Alignment = ST->getAlignment();
11268 bool isVolatile = ST->isVolatile();
11269 bool isNonTemporal = ST->isNonTemporal();
11270 AAMDNodes AAInfo = ST->getAAInfo();
11274 SDValue St0 = DAG.getStore(Chain, SDLoc(ST), Lo,
11275 Ptr, ST->getPointerInfo(),
11276 isVolatile, isNonTemporal,
11277 ST->getAlignment(), AAInfo);
11278 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
11279 DAG.getConstant(4, DL, Ptr.getValueType()));
11280 Alignment = MinAlign(Alignment, 4U);
11281 SDValue St1 = DAG.getStore(Chain, SDLoc(ST), Hi,
11282 Ptr, ST->getPointerInfo().getWithOffset(4),
11283 isVolatile, isNonTemporal,
11284 Alignment, AAInfo);
11285 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
11294 // Try to infer better alignment information than the store already has.
11295 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
11296 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
11297 if (Align > ST->getAlignment()) {
11299 DAG.getTruncStore(Chain, SDLoc(N), Value,
11300 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
11301 ST->isVolatile(), ST->isNonTemporal(), Align,
11303 if (NewStore.getNode() != N)
11304 return CombineTo(ST, NewStore, true);
11309 // Try transforming a pair floating point load / store ops to integer
11310 // load / store ops.
11311 if (SDValue NewST = TransformFPLoadStorePair(N))
11314 bool UseAA = CombinerAA.getNumOccurrences() > 0 ? CombinerAA
11315 : DAG.getSubtarget().useAA();
11317 if (CombinerAAOnlyFunc.getNumOccurrences() &&
11318 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
11321 if (UseAA && ST->isUnindexed()) {
11322 // Walk up chain skipping non-aliasing memory nodes.
11323 SDValue BetterChain = FindBetterChain(N, Chain);
11325 // If there is a better chain.
11326 if (Chain != BetterChain) {
11329 // Replace the chain to avoid dependency.
11330 if (ST->isTruncatingStore()) {
11331 ReplStore = DAG.getTruncStore(BetterChain, SDLoc(N), Value, Ptr,
11332 ST->getMemoryVT(), ST->getMemOperand());
11334 ReplStore = DAG.getStore(BetterChain, SDLoc(N), Value, Ptr,
11335 ST->getMemOperand());
11338 // Create token to keep both nodes around.
11339 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N),
11340 MVT::Other, Chain, ReplStore);
11342 // Make sure the new and old chains are cleaned up.
11343 AddToWorklist(Token.getNode());
11345 // Don't add users to work list.
11346 return CombineTo(N, Token, false);
11350 // Try transforming N to an indexed store.
11351 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
11352 return SDValue(N, 0);
11354 // FIXME: is there such a thing as a truncating indexed store?
11355 if (ST->isTruncatingStore() && ST->isUnindexed() &&
11356 Value.getValueType().isInteger()) {
11357 // See if we can simplify the input to this truncstore with knowledge that
11358 // only the low bits are being used. For example:
11359 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
11361 GetDemandedBits(Value,
11362 APInt::getLowBitsSet(
11363 Value.getValueType().getScalarType().getSizeInBits(),
11364 ST->getMemoryVT().getScalarType().getSizeInBits()));
11365 AddToWorklist(Value.getNode());
11366 if (Shorter.getNode())
11367 return DAG.getTruncStore(Chain, SDLoc(N), Shorter,
11368 Ptr, ST->getMemoryVT(), ST->getMemOperand());
11370 // Otherwise, see if we can simplify the operation with
11371 // SimplifyDemandedBits, which only works if the value has a single use.
11372 if (SimplifyDemandedBits(Value,
11373 APInt::getLowBitsSet(
11374 Value.getValueType().getScalarType().getSizeInBits(),
11375 ST->getMemoryVT().getScalarType().getSizeInBits())))
11376 return SDValue(N, 0);
11379 // If this is a load followed by a store to the same location, then the store
11381 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
11382 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
11383 ST->isUnindexed() && !ST->isVolatile() &&
11384 // There can't be any side effects between the load and store, such as
11385 // a call or store.
11386 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
11387 // The store is dead, remove it.
11392 // If this is a store followed by a store with the same value to the same
11393 // location, then the store is dead/noop.
11394 if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) {
11395 if (ST1->getBasePtr() == Ptr && ST->getMemoryVT() == ST1->getMemoryVT() &&
11396 ST1->getValue() == Value && ST->isUnindexed() && !ST->isVolatile() &&
11397 ST1->isUnindexed() && !ST1->isVolatile()) {
11398 // The store is dead, remove it.
11403 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
11404 // truncating store. We can do this even if this is already a truncstore.
11405 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
11406 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
11407 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
11408 ST->getMemoryVT())) {
11409 return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0),
11410 Ptr, ST->getMemoryVT(), ST->getMemOperand());
11413 // Only perform this optimization before the types are legal, because we
11414 // don't want to perform this optimization on every DAGCombine invocation.
11416 bool EverChanged = false;
11419 // There can be multiple store sequences on the same chain.
11420 // Keep trying to merge store sequences until we are unable to do so
11421 // or until we merge the last store on the chain.
11422 bool Changed = MergeConsecutiveStores(ST);
11423 EverChanged |= Changed;
11424 if (!Changed) break;
11425 } while (ST->getOpcode() != ISD::DELETED_NODE);
11428 return SDValue(N, 0);
11431 return ReduceLoadOpStoreWidth(N);
11434 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
11435 SDValue InVec = N->getOperand(0);
11436 SDValue InVal = N->getOperand(1);
11437 SDValue EltNo = N->getOperand(2);
11440 // If the inserted element is an UNDEF, just use the input vector.
11441 if (InVal.getOpcode() == ISD::UNDEF)
11444 EVT VT = InVec.getValueType();
11446 // If we can't generate a legal BUILD_VECTOR, exit
11447 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
11450 // Check that we know which element is being inserted
11451 if (!isa<ConstantSDNode>(EltNo))
11453 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
11455 // Canonicalize insert_vector_elt dag nodes.
11457 // (insert_vector_elt (insert_vector_elt A, Idx0), Idx1)
11458 // -> (insert_vector_elt (insert_vector_elt A, Idx1), Idx0)
11460 // Do this only if the child insert_vector node has one use; also
11461 // do this only if indices are both constants and Idx1 < Idx0.
11462 if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
11463 && isa<ConstantSDNode>(InVec.getOperand(2))) {
11464 unsigned OtherElt =
11465 cast<ConstantSDNode>(InVec.getOperand(2))->getZExtValue();
11466 if (Elt < OtherElt) {
11468 SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(N), VT,
11469 InVec.getOperand(0), InVal, EltNo);
11470 AddToWorklist(NewOp.getNode());
11471 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(InVec.getNode()),
11472 VT, NewOp, InVec.getOperand(1), InVec.getOperand(2));
11476 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
11477 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
11478 // vector elements.
11479 SmallVector<SDValue, 8> Ops;
11480 // Do not combine these two vectors if the output vector will not replace
11481 // the input vector.
11482 if (InVec.getOpcode() == ISD::BUILD_VECTOR && InVec.hasOneUse()) {
11483 Ops.append(InVec.getNode()->op_begin(),
11484 InVec.getNode()->op_end());
11485 } else if (InVec.getOpcode() == ISD::UNDEF) {
11486 unsigned NElts = VT.getVectorNumElements();
11487 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
11492 // Insert the element
11493 if (Elt < Ops.size()) {
11494 // All the operands of BUILD_VECTOR must have the same type;
11495 // we enforce that here.
11496 EVT OpVT = Ops[0].getValueType();
11497 if (InVal.getValueType() != OpVT)
11498 InVal = OpVT.bitsGT(InVal.getValueType()) ?
11499 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
11500 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
11504 // Return the new vector
11505 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
11508 SDValue DAGCombiner::ReplaceExtractVectorEltOfLoadWithNarrowedLoad(
11509 SDNode *EVE, EVT InVecVT, SDValue EltNo, LoadSDNode *OriginalLoad) {
11510 EVT ResultVT = EVE->getValueType(0);
11511 EVT VecEltVT = InVecVT.getVectorElementType();
11512 unsigned Align = OriginalLoad->getAlignment();
11513 unsigned NewAlign = DAG.getDataLayout().getABITypeAlignment(
11514 VecEltVT.getTypeForEVT(*DAG.getContext()));
11516 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VecEltVT))
11521 SDValue NewPtr = OriginalLoad->getBasePtr();
11523 EVT PtrType = NewPtr.getValueType();
11524 MachinePointerInfo MPI;
11526 if (auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo)) {
11527 int Elt = ConstEltNo->getZExtValue();
11528 unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / 8;
11529 Offset = DAG.getConstant(PtrOff, DL, PtrType);
11530 MPI = OriginalLoad->getPointerInfo().getWithOffset(PtrOff);
11532 Offset = DAG.getZExtOrTrunc(EltNo, DL, PtrType);
11533 Offset = DAG.getNode(
11534 ISD::MUL, DL, PtrType, Offset,
11535 DAG.getConstant(VecEltVT.getStoreSize(), DL, PtrType));
11536 MPI = OriginalLoad->getPointerInfo();
11538 NewPtr = DAG.getNode(ISD::ADD, DL, PtrType, NewPtr, Offset);
11540 // The replacement we need to do here is a little tricky: we need to
11541 // replace an extractelement of a load with a load.
11542 // Use ReplaceAllUsesOfValuesWith to do the replacement.
11543 // Note that this replacement assumes that the extractvalue is the only
11544 // use of the load; that's okay because we don't want to perform this
11545 // transformation in other cases anyway.
11548 if (ResultVT.bitsGT(VecEltVT)) {
11549 // If the result type of vextract is wider than the load, then issue an
11550 // extending load instead.
11551 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, ResultVT,
11555 Load = DAG.getExtLoad(
11556 ExtType, SDLoc(EVE), ResultVT, OriginalLoad->getChain(), NewPtr, MPI,
11557 VecEltVT, OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
11558 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
11559 Chain = Load.getValue(1);
11561 Load = DAG.getLoad(
11562 VecEltVT, SDLoc(EVE), OriginalLoad->getChain(), NewPtr, MPI,
11563 OriginalLoad->isVolatile(), OriginalLoad->isNonTemporal(),
11564 OriginalLoad->isInvariant(), Align, OriginalLoad->getAAInfo());
11565 Chain = Load.getValue(1);
11566 if (ResultVT.bitsLT(VecEltVT))
11567 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(EVE), ResultVT, Load);
11569 Load = DAG.getNode(ISD::BITCAST, SDLoc(EVE), ResultVT, Load);
11571 WorklistRemover DeadNodes(*this);
11572 SDValue From[] = { SDValue(EVE, 0), SDValue(OriginalLoad, 1) };
11573 SDValue To[] = { Load, Chain };
11574 DAG.ReplaceAllUsesOfValuesWith(From, To, 2);
11575 // Since we're explicitly calling ReplaceAllUses, add the new node to the
11576 // worklist explicitly as well.
11577 AddToWorklist(Load.getNode());
11578 AddUsersToWorklist(Load.getNode()); // Add users too
11579 // Make sure to revisit this node to clean it up; it will usually be dead.
11580 AddToWorklist(EVE);
11582 return SDValue(EVE, 0);
11585 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
11586 // (vextract (scalar_to_vector val, 0) -> val
11587 SDValue InVec = N->getOperand(0);
11588 EVT VT = InVec.getValueType();
11589 EVT NVT = N->getValueType(0);
11591 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
11592 // Check if the result type doesn't match the inserted element type. A
11593 // SCALAR_TO_VECTOR may truncate the inserted element and the
11594 // EXTRACT_VECTOR_ELT may widen the extracted vector.
11595 SDValue InOp = InVec.getOperand(0);
11596 if (InOp.getValueType() != NVT) {
11597 assert(InOp.getValueType().isInteger() && NVT.isInteger());
11598 return DAG.getSExtOrTrunc(InOp, SDLoc(InVec), NVT);
11603 SDValue EltNo = N->getOperand(1);
11604 bool ConstEltNo = isa<ConstantSDNode>(EltNo);
11606 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
11607 // We only perform this optimization before the op legalization phase because
11608 // we may introduce new vector instructions which are not backed by TD
11609 // patterns. For example on AVX, extracting elements from a wide vector
11610 // without using extract_subvector. However, if we can find an underlying
11611 // scalar value, then we can always use that.
11612 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE
11614 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
11615 int NumElem = VT.getVectorNumElements();
11616 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec);
11617 // Find the new index to extract from.
11618 int OrigElt = SVOp->getMaskElt(Elt);
11620 // Extracting an undef index is undef.
11622 return DAG.getUNDEF(NVT);
11624 // Select the right vector half to extract from.
11626 if (OrigElt < NumElem) {
11627 SVInVec = InVec->getOperand(0);
11629 SVInVec = InVec->getOperand(1);
11630 OrigElt -= NumElem;
11633 if (SVInVec.getOpcode() == ISD::BUILD_VECTOR) {
11634 SDValue InOp = SVInVec.getOperand(OrigElt);
11635 if (InOp.getValueType() != NVT) {
11636 assert(InOp.getValueType().isInteger() && NVT.isInteger());
11637 InOp = DAG.getSExtOrTrunc(InOp, SDLoc(SVInVec), NVT);
11643 // FIXME: We should handle recursing on other vector shuffles and
11644 // scalar_to_vector here as well.
11646 if (!LegalOperations) {
11647 EVT IndexTy = TLI.getVectorIdxTy(DAG.getDataLayout());
11648 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT, SVInVec,
11649 DAG.getConstant(OrigElt, SDLoc(SVOp), IndexTy));
11653 bool BCNumEltsChanged = false;
11654 EVT ExtVT = VT.getVectorElementType();
11657 // If the result of load has to be truncated, then it's not necessarily
11659 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT))
11662 if (InVec.getOpcode() == ISD::BITCAST) {
11663 // Don't duplicate a load with other uses.
11664 if (!InVec.hasOneUse())
11667 EVT BCVT = InVec.getOperand(0).getValueType();
11668 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
11670 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
11671 BCNumEltsChanged = true;
11672 InVec = InVec.getOperand(0);
11673 ExtVT = BCVT.getVectorElementType();
11676 // (vextract (vN[if]M load $addr), i) -> ([if]M load $addr + i * size)
11677 if (!LegalOperations && !ConstEltNo && InVec.hasOneUse() &&
11678 ISD::isNormalLoad(InVec.getNode()) &&
11679 !N->getOperand(1)->hasPredecessor(InVec.getNode())) {
11680 SDValue Index = N->getOperand(1);
11681 if (LoadSDNode *OrigLoad = dyn_cast<LoadSDNode>(InVec))
11682 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, Index,
11686 // Perform only after legalization to ensure build_vector / vector_shuffle
11687 // optimizations have already been done.
11688 if (!LegalOperations) return SDValue();
11690 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
11691 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
11692 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
11695 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
11697 LoadSDNode *LN0 = nullptr;
11698 const ShuffleVectorSDNode *SVN = nullptr;
11699 if (ISD::isNormalLoad(InVec.getNode())) {
11700 LN0 = cast<LoadSDNode>(InVec);
11701 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
11702 InVec.getOperand(0).getValueType() == ExtVT &&
11703 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
11704 // Don't duplicate a load with other uses.
11705 if (!InVec.hasOneUse())
11708 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
11709 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
11710 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
11712 // (load $addr+1*size)
11714 // Don't duplicate a load with other uses.
11715 if (!InVec.hasOneUse())
11718 // If the bit convert changed the number of elements, it is unsafe
11719 // to examine the mask.
11720 if (BCNumEltsChanged)
11723 // Select the input vector, guarding against out of range extract vector.
11724 unsigned NumElems = VT.getVectorNumElements();
11725 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
11726 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
11728 if (InVec.getOpcode() == ISD::BITCAST) {
11729 // Don't duplicate a load with other uses.
11730 if (!InVec.hasOneUse())
11733 InVec = InVec.getOperand(0);
11735 if (ISD::isNormalLoad(InVec.getNode())) {
11736 LN0 = cast<LoadSDNode>(InVec);
11737 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
11738 EltNo = DAG.getConstant(Elt, SDLoc(EltNo), EltNo.getValueType());
11742 // Make sure we found a non-volatile load and the extractelement is
11744 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
11747 // If Idx was -1 above, Elt is going to be -1, so just return undef.
11749 return DAG.getUNDEF(LVT);
11751 return ReplaceExtractVectorEltOfLoadWithNarrowedLoad(N, VT, EltNo, LN0);
11757 // Simplify (build_vec (ext )) to (bitcast (build_vec ))
11758 SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
11759 // We perform this optimization post type-legalization because
11760 // the type-legalizer often scalarizes integer-promoted vectors.
11761 // Performing this optimization before may create bit-casts which
11762 // will be type-legalized to complex code sequences.
11763 // We perform this optimization only before the operation legalizer because we
11764 // may introduce illegal operations.
11765 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes)
11768 unsigned NumInScalars = N->getNumOperands();
11770 EVT VT = N->getValueType(0);
11772 // Check to see if this is a BUILD_VECTOR of a bunch of values
11773 // which come from any_extend or zero_extend nodes. If so, we can create
11774 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
11775 // optimizations. We do not handle sign-extend because we can't fill the sign
11777 EVT SourceType = MVT::Other;
11778 bool AllAnyExt = true;
11780 for (unsigned i = 0; i != NumInScalars; ++i) {
11781 SDValue In = N->getOperand(i);
11782 // Ignore undef inputs.
11783 if (In.getOpcode() == ISD::UNDEF) continue;
11785 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
11786 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
11788 // Abort if the element is not an extension.
11789 if (!ZeroExt && !AnyExt) {
11790 SourceType = MVT::Other;
11794 // The input is a ZeroExt or AnyExt. Check the original type.
11795 EVT InTy = In.getOperand(0).getValueType();
11797 // Check that all of the widened source types are the same.
11798 if (SourceType == MVT::Other)
11801 else if (InTy != SourceType) {
11802 // Multiple income types. Abort.
11803 SourceType = MVT::Other;
11807 // Check if all of the extends are ANY_EXTENDs.
11808 AllAnyExt &= AnyExt;
11811 // In order to have valid types, all of the inputs must be extended from the
11812 // same source type and all of the inputs must be any or zero extend.
11813 // Scalar sizes must be a power of two.
11814 EVT OutScalarTy = VT.getScalarType();
11815 bool ValidTypes = SourceType != MVT::Other &&
11816 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
11817 isPowerOf2_32(SourceType.getSizeInBits());
11819 // Create a new simpler BUILD_VECTOR sequence which other optimizations can
11820 // turn into a single shuffle instruction.
11824 bool isLE = DAG.getDataLayout().isLittleEndian();
11825 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
11826 assert(ElemRatio > 1 && "Invalid element size ratio");
11827 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType):
11828 DAG.getConstant(0, SDLoc(N), SourceType);
11830 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements();
11831 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
11833 // Populate the new build_vector
11834 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
11835 SDValue Cast = N->getOperand(i);
11836 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
11837 Cast.getOpcode() == ISD::ZERO_EXTEND ||
11838 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
11840 if (Cast.getOpcode() == ISD::UNDEF)
11841 In = DAG.getUNDEF(SourceType);
11843 In = Cast->getOperand(0);
11844 unsigned Index = isLE ? (i * ElemRatio) :
11845 (i * ElemRatio + (ElemRatio - 1));
11847 assert(Index < Ops.size() && "Invalid index");
11851 // The type of the new BUILD_VECTOR node.
11852 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
11853 assert(VecVT.getSizeInBits() == VT.getSizeInBits() &&
11854 "Invalid vector size");
11855 // Check if the new vector type is legal.
11856 if (!isTypeLegal(VecVT)) return SDValue();
11858 // Make the new BUILD_VECTOR.
11859 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
11861 // The new BUILD_VECTOR node has the potential to be further optimized.
11862 AddToWorklist(BV.getNode());
11863 // Bitcast to the desired type.
11864 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
11867 SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) {
11868 EVT VT = N->getValueType(0);
11870 unsigned NumInScalars = N->getNumOperands();
11873 EVT SrcVT = MVT::Other;
11874 unsigned Opcode = ISD::DELETED_NODE;
11875 unsigned NumDefs = 0;
11877 for (unsigned i = 0; i != NumInScalars; ++i) {
11878 SDValue In = N->getOperand(i);
11879 unsigned Opc = In.getOpcode();
11881 if (Opc == ISD::UNDEF)
11884 // If all scalar values are floats and converted from integers.
11885 if (Opcode == ISD::DELETED_NODE &&
11886 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) {
11893 EVT InVT = In.getOperand(0).getValueType();
11895 // If all scalar values are typed differently, bail out. It's chosen to
11896 // simplify BUILD_VECTOR of integer types.
11897 if (SrcVT == MVT::Other)
11904 // If the vector has just one element defined, it's not worth to fold it into
11905 // a vectorized one.
11909 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP)
11910 && "Should only handle conversion from integer to float.");
11911 assert(SrcVT != MVT::Other && "Cannot determine source type!");
11913 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars);
11915 if (!TLI.isOperationLegalOrCustom(Opcode, NVT))
11918 // Just because the floating-point vector type is legal does not necessarily
11919 // mean that the corresponding integer vector type is.
11920 if (!isTypeLegal(NVT))
11923 SmallVector<SDValue, 8> Opnds;
11924 for (unsigned i = 0; i != NumInScalars; ++i) {
11925 SDValue In = N->getOperand(i);
11927 if (In.getOpcode() == ISD::UNDEF)
11928 Opnds.push_back(DAG.getUNDEF(SrcVT));
11930 Opnds.push_back(In.getOperand(0));
11932 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Opnds);
11933 AddToWorklist(BV.getNode());
11935 return DAG.getNode(Opcode, dl, VT, BV);
11938 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
11939 unsigned NumInScalars = N->getNumOperands();
11941 EVT VT = N->getValueType(0);
11943 // A vector built entirely of undefs is undef.
11944 if (ISD::allOperandsUndef(N))
11945 return DAG.getUNDEF(VT);
11947 if (SDValue V = reduceBuildVecExtToExtBuildVec(N))
11950 if (SDValue V = reduceBuildVecConvertToConvertBuildVec(N))
11953 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
11954 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
11955 // at most two distinct vectors, turn this into a shuffle node.
11957 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes.
11958 if (!isTypeLegal(VT))
11961 // May only combine to shuffle after legalize if shuffle is legal.
11962 if (LegalOperations && !TLI.isOperationLegal(ISD::VECTOR_SHUFFLE, VT))
11965 SDValue VecIn1, VecIn2;
11966 bool UsesZeroVector = false;
11967 for (unsigned i = 0; i != NumInScalars; ++i) {
11968 SDValue Op = N->getOperand(i);
11969 // Ignore undef inputs.
11970 if (Op.getOpcode() == ISD::UNDEF) continue;
11972 // See if we can combine this build_vector into a blend with a zero vector.
11973 if (!VecIn2.getNode() && (isNullConstant(Op) || isNullFPConstant(Op))) {
11974 UsesZeroVector = true;
11978 // If this input is something other than a EXTRACT_VECTOR_ELT with a
11979 // constant index, bail out.
11980 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
11981 !isa<ConstantSDNode>(Op.getOperand(1))) {
11982 VecIn1 = VecIn2 = SDValue(nullptr, 0);
11986 // We allow up to two distinct input vectors.
11987 SDValue ExtractedFromVec = Op.getOperand(0);
11988 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
11991 if (!VecIn1.getNode()) {
11992 VecIn1 = ExtractedFromVec;
11993 } else if (!VecIn2.getNode() && !UsesZeroVector) {
11994 VecIn2 = ExtractedFromVec;
11996 // Too many inputs.
11997 VecIn1 = VecIn2 = SDValue(nullptr, 0);
12002 // If everything is good, we can make a shuffle operation.
12003 if (VecIn1.getNode()) {
12004 unsigned InNumElements = VecIn1.getValueType().getVectorNumElements();
12005 SmallVector<int, 8> Mask;
12006 for (unsigned i = 0; i != NumInScalars; ++i) {
12007 unsigned Opcode = N->getOperand(i).getOpcode();
12008 if (Opcode == ISD::UNDEF) {
12009 Mask.push_back(-1);
12013 // Operands can also be zero.
12014 if (Opcode != ISD::EXTRACT_VECTOR_ELT) {
12015 assert(UsesZeroVector &&
12016 (Opcode == ISD::Constant || Opcode == ISD::ConstantFP) &&
12017 "Unexpected node found!");
12018 Mask.push_back(NumInScalars+i);
12022 // If extracting from the first vector, just use the index directly.
12023 SDValue Extract = N->getOperand(i);
12024 SDValue ExtVal = Extract.getOperand(1);
12025 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
12026 if (Extract.getOperand(0) == VecIn1) {
12027 Mask.push_back(ExtIndex);
12031 // Otherwise, use InIdx + InputVecSize
12032 Mask.push_back(InNumElements + ExtIndex);
12035 // Avoid introducing illegal shuffles with zero.
12036 if (UsesZeroVector && !TLI.isVectorClearMaskLegal(Mask, VT))
12039 // We can't generate a shuffle node with mismatched input and output types.
12040 // Attempt to transform a single input vector to the correct type.
12041 if ((VT != VecIn1.getValueType())) {
12042 // If the input vector type has a different base type to the output
12043 // vector type, bail out.
12044 EVT VTElemType = VT.getVectorElementType();
12045 if ((VecIn1.getValueType().getVectorElementType() != VTElemType) ||
12046 (VecIn2.getNode() &&
12047 (VecIn2.getValueType().getVectorElementType() != VTElemType)))
12050 // If the input vector is too small, widen it.
12051 // We only support widening of vectors which are half the size of the
12052 // output registers. For example XMM->YMM widening on X86 with AVX.
12053 EVT VecInT = VecIn1.getValueType();
12054 if (VecInT.getSizeInBits() * 2 == VT.getSizeInBits()) {
12055 // If we only have one small input, widen it by adding undef values.
12056 if (!VecIn2.getNode())
12057 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, VecIn1,
12058 DAG.getUNDEF(VecIn1.getValueType()));
12059 else if (VecIn1.getValueType() == VecIn2.getValueType()) {
12060 // If we have two small inputs of the same type, try to concat them.
12061 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, VecIn1, VecIn2);
12062 VecIn2 = SDValue(nullptr, 0);
12065 } else if (VecInT.getSizeInBits() == VT.getSizeInBits() * 2) {
12066 // If the input vector is too large, try to split it.
12067 // We don't support having two input vectors that are too large.
12068 // If the zero vector was used, we can not split the vector,
12069 // since we'd need 3 inputs.
12070 if (UsesZeroVector || VecIn2.getNode())
12073 if (!TLI.isExtractSubvectorCheap(VT, VT.getVectorNumElements()))
12076 // Try to replace VecIn1 with two extract_subvectors
12077 // No need to update the masks, they should still be correct.
12078 VecIn2 = DAG.getNode(
12079 ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
12080 DAG.getConstant(VT.getVectorNumElements(), dl,
12081 TLI.getVectorIdxTy(DAG.getDataLayout())));
12082 VecIn1 = DAG.getNode(
12083 ISD::EXTRACT_SUBVECTOR, dl, VT, VecIn1,
12084 DAG.getConstant(0, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
12089 if (UsesZeroVector)
12090 VecIn2 = VT.isInteger() ? DAG.getConstant(0, dl, VT) :
12091 DAG.getConstantFP(0.0, dl, VT);
12093 // If VecIn2 is unused then change it to undef.
12094 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
12096 // Check that we were able to transform all incoming values to the same
12098 if (VecIn2.getValueType() != VecIn1.getValueType() ||
12099 VecIn1.getValueType() != VT)
12102 // Return the new VECTOR_SHUFFLE node.
12106 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]);
12112 static SDValue combineConcatVectorOfScalars(SDNode *N, SelectionDAG &DAG) {
12113 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
12114 EVT OpVT = N->getOperand(0).getValueType();
12116 // If the operands are legal vectors, leave them alone.
12117 if (TLI.isTypeLegal(OpVT))
12121 EVT VT = N->getValueType(0);
12122 SmallVector<SDValue, 8> Ops;
12124 EVT SVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits());
12125 SDValue ScalarUndef = DAG.getNode(ISD::UNDEF, DL, SVT);
12127 // Keep track of what we encounter.
12128 bool AnyInteger = false;
12129 bool AnyFP = false;
12130 for (const SDValue &Op : N->ops()) {
12131 if (ISD::BITCAST == Op.getOpcode() &&
12132 !Op.getOperand(0).getValueType().isVector())
12133 Ops.push_back(Op.getOperand(0));
12134 else if (ISD::UNDEF == Op.getOpcode())
12135 Ops.push_back(ScalarUndef);
12139 // Note whether we encounter an integer or floating point scalar.
12140 // If it's neither, bail out, it could be something weird like x86mmx.
12141 EVT LastOpVT = Ops.back().getValueType();
12142 if (LastOpVT.isFloatingPoint())
12144 else if (LastOpVT.isInteger())
12150 // If any of the operands is a floating point scalar bitcast to a vector,
12151 // use floating point types throughout, and bitcast everything.
12152 // Replace UNDEFs by another scalar UNDEF node, of the final desired type.
12154 SVT = EVT::getFloatingPointVT(OpVT.getSizeInBits());
12155 ScalarUndef = DAG.getNode(ISD::UNDEF, DL, SVT);
12157 for (SDValue &Op : Ops) {
12158 if (Op.getValueType() == SVT)
12160 if (Op.getOpcode() == ISD::UNDEF)
12163 Op = DAG.getNode(ISD::BITCAST, DL, SVT, Op);
12168 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SVT,
12169 VT.getSizeInBits() / SVT.getSizeInBits());
12170 return DAG.getNode(ISD::BITCAST, DL, VT,
12171 DAG.getNode(ISD::BUILD_VECTOR, DL, VecVT, Ops));
12174 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
12175 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
12176 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
12177 // inputs come from at most two distinct vectors, turn this into a shuffle
12180 // If we only have one input vector, we don't need to do any concatenation.
12181 if (N->getNumOperands() == 1)
12182 return N->getOperand(0);
12184 // Check if all of the operands are undefs.
12185 EVT VT = N->getValueType(0);
12186 if (ISD::allOperandsUndef(N))
12187 return DAG.getUNDEF(VT);
12189 // Optimize concat_vectors where all but the first of the vectors are undef.
12190 if (std::all_of(std::next(N->op_begin()), N->op_end(), [](const SDValue &Op) {
12191 return Op.getOpcode() == ISD::UNDEF;
12193 SDValue In = N->getOperand(0);
12194 assert(In.getValueType().isVector() && "Must concat vectors");
12196 // Transform: concat_vectors(scalar, undef) -> scalar_to_vector(sclr).
12197 if (In->getOpcode() == ISD::BITCAST &&
12198 !In->getOperand(0)->getValueType(0).isVector()) {
12199 SDValue Scalar = In->getOperand(0);
12201 // If the bitcast type isn't legal, it might be a trunc of a legal type;
12202 // look through the trunc so we can still do the transform:
12203 // concat_vectors(trunc(scalar), undef) -> scalar_to_vector(scalar)
12204 if (Scalar->getOpcode() == ISD::TRUNCATE &&
12205 !TLI.isTypeLegal(Scalar.getValueType()) &&
12206 TLI.isTypeLegal(Scalar->getOperand(0).getValueType()))
12207 Scalar = Scalar->getOperand(0);
12209 EVT SclTy = Scalar->getValueType(0);
12211 if (!SclTy.isFloatingPoint() && !SclTy.isInteger())
12214 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SclTy,
12215 VT.getSizeInBits() / SclTy.getSizeInBits());
12216 if (!TLI.isTypeLegal(NVT) || !TLI.isTypeLegal(Scalar.getValueType()))
12219 SDLoc dl = SDLoc(N);
12220 SDValue Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NVT, Scalar);
12221 return DAG.getNode(ISD::BITCAST, dl, VT, Res);
12225 // Fold any combination of BUILD_VECTOR or UNDEF nodes into one BUILD_VECTOR.
12226 // We have already tested above for an UNDEF only concatenation.
12227 // fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
12228 // -> (BUILD_VECTOR A, B, ..., C, D, ...)
12229 auto IsBuildVectorOrUndef = [](const SDValue &Op) {
12230 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode();
12232 bool AllBuildVectorsOrUndefs =
12233 std::all_of(N->op_begin(), N->op_end(), IsBuildVectorOrUndef);
12234 if (AllBuildVectorsOrUndefs) {
12235 SmallVector<SDValue, 8> Opnds;
12236 EVT SVT = VT.getScalarType();
12239 if (!SVT.isFloatingPoint()) {
12240 // If BUILD_VECTOR are from built from integer, they may have different
12241 // operand types. Get the smallest type and truncate all operands to it.
12242 bool FoundMinVT = false;
12243 for (const SDValue &Op : N->ops())
12244 if (ISD::BUILD_VECTOR == Op.getOpcode()) {
12245 EVT OpSVT = Op.getOperand(0)->getValueType(0);
12246 MinVT = (!FoundMinVT || OpSVT.bitsLE(MinVT)) ? OpSVT : MinVT;
12249 assert(FoundMinVT && "Concat vector type mismatch");
12252 for (const SDValue &Op : N->ops()) {
12253 EVT OpVT = Op.getValueType();
12254 unsigned NumElts = OpVT.getVectorNumElements();
12256 if (ISD::UNDEF == Op.getOpcode())
12257 Opnds.append(NumElts, DAG.getUNDEF(MinVT));
12259 if (ISD::BUILD_VECTOR == Op.getOpcode()) {
12260 if (SVT.isFloatingPoint()) {
12261 assert(SVT == OpVT.getScalarType() && "Concat vector type mismatch");
12262 Opnds.append(Op->op_begin(), Op->op_begin() + NumElts);
12264 for (unsigned i = 0; i != NumElts; ++i)
12266 DAG.getNode(ISD::TRUNCATE, SDLoc(N), MinVT, Op.getOperand(i)));
12271 assert(VT.getVectorNumElements() == Opnds.size() &&
12272 "Concat vector type mismatch");
12273 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Opnds);
12276 // Fold CONCAT_VECTORS of only bitcast scalars (or undef) to BUILD_VECTOR.
12277 if (SDValue V = combineConcatVectorOfScalars(N, DAG))
12280 // Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
12281 // nodes often generate nop CONCAT_VECTOR nodes.
12282 // Scan the CONCAT_VECTOR operands and look for a CONCAT operations that
12283 // place the incoming vectors at the exact same location.
12284 SDValue SingleSource = SDValue();
12285 unsigned PartNumElem = N->getOperand(0).getValueType().getVectorNumElements();
12287 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
12288 SDValue Op = N->getOperand(i);
12290 if (Op.getOpcode() == ISD::UNDEF)
12293 // Check if this is the identity extract:
12294 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR)
12297 // Find the single incoming vector for the extract_subvector.
12298 if (SingleSource.getNode()) {
12299 if (Op.getOperand(0) != SingleSource)
12302 SingleSource = Op.getOperand(0);
12304 // Check the source type is the same as the type of the result.
12305 // If not, this concat may extend the vector, so we can not
12306 // optimize it away.
12307 if (SingleSource.getValueType() != N->getValueType(0))
12311 unsigned IdentityIndex = i * PartNumElem;
12312 ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1));
12313 // The extract index must be constant.
12317 // Check that we are reading from the identity index.
12318 if (CS->getZExtValue() != IdentityIndex)
12322 if (SingleSource.getNode())
12323 return SingleSource;
12328 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
12329 EVT NVT = N->getValueType(0);
12330 SDValue V = N->getOperand(0);
12332 if (V->getOpcode() == ISD::CONCAT_VECTORS) {
12334 // (extract_subvec (concat V1, V2, ...), i)
12337 // Only operand 0 is checked as 'concat' assumes all inputs of the same
12339 if (V->getOperand(0).getValueType() != NVT)
12341 unsigned Idx = N->getConstantOperandVal(1);
12342 unsigned NumElems = NVT.getVectorNumElements();
12343 assert((Idx % NumElems) == 0 &&
12344 "IDX in concat is not a multiple of the result vector length.");
12345 return V->getOperand(Idx / NumElems);
12349 if (V->getOpcode() == ISD::BITCAST)
12350 V = V.getOperand(0);
12352 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
12354 // Handle only simple case where vector being inserted and vector
12355 // being extracted are of same type, and are half size of larger vectors.
12356 EVT BigVT = V->getOperand(0).getValueType();
12357 EVT SmallVT = V->getOperand(1).getValueType();
12358 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
12361 // Only handle cases where both indexes are constants with the same type.
12362 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
12363 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
12365 if (InsIdx && ExtIdx &&
12366 InsIdx->getValueType(0).getSizeInBits() <= 64 &&
12367 ExtIdx->getValueType(0).getSizeInBits() <= 64) {
12369 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
12371 // indices are equal or bit offsets are equal => V1
12372 // otherwise => (extract_subvec V1, ExtIdx)
12373 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() ==
12374 ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits())
12375 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1));
12376 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT,
12377 DAG.getNode(ISD::BITCAST, dl,
12378 N->getOperand(0).getValueType(),
12379 V->getOperand(0)), N->getOperand(1));
12386 static SDValue simplifyShuffleOperandRecursively(SmallBitVector &UsedElements,
12387 SDValue V, SelectionDAG &DAG) {
12389 EVT VT = V.getValueType();
12391 switch (V.getOpcode()) {
12395 case ISD::CONCAT_VECTORS: {
12396 EVT OpVT = V->getOperand(0).getValueType();
12397 int OpSize = OpVT.getVectorNumElements();
12398 SmallBitVector OpUsedElements(OpSize, false);
12399 bool FoundSimplification = false;
12400 SmallVector<SDValue, 4> NewOps;
12401 NewOps.reserve(V->getNumOperands());
12402 for (int i = 0, NumOps = V->getNumOperands(); i < NumOps; ++i) {
12403 SDValue Op = V->getOperand(i);
12404 bool OpUsed = false;
12405 for (int j = 0; j < OpSize; ++j)
12406 if (UsedElements[i * OpSize + j]) {
12407 OpUsedElements[j] = true;
12411 OpUsed ? simplifyShuffleOperandRecursively(OpUsedElements, Op, DAG)
12412 : DAG.getUNDEF(OpVT));
12413 FoundSimplification |= Op == NewOps.back();
12414 OpUsedElements.reset();
12416 if (FoundSimplification)
12417 V = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, NewOps);
12421 case ISD::INSERT_SUBVECTOR: {
12422 SDValue BaseV = V->getOperand(0);
12423 SDValue SubV = V->getOperand(1);
12424 auto *IdxN = dyn_cast<ConstantSDNode>(V->getOperand(2));
12428 int SubSize = SubV.getValueType().getVectorNumElements();
12429 int Idx = IdxN->getZExtValue();
12430 bool SubVectorUsed = false;
12431 SmallBitVector SubUsedElements(SubSize, false);
12432 for (int i = 0; i < SubSize; ++i)
12433 if (UsedElements[i + Idx]) {
12434 SubVectorUsed = true;
12435 SubUsedElements[i] = true;
12436 UsedElements[i + Idx] = false;
12439 // Now recurse on both the base and sub vectors.
12440 SDValue SimplifiedSubV =
12442 ? simplifyShuffleOperandRecursively(SubUsedElements, SubV, DAG)
12443 : DAG.getUNDEF(SubV.getValueType());
12444 SDValue SimplifiedBaseV = simplifyShuffleOperandRecursively(UsedElements, BaseV, DAG);
12445 if (SimplifiedSubV != SubV || SimplifiedBaseV != BaseV)
12446 V = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, VT,
12447 SimplifiedBaseV, SimplifiedSubV, V->getOperand(2));
12453 static SDValue simplifyShuffleOperands(ShuffleVectorSDNode *SVN, SDValue N0,
12454 SDValue N1, SelectionDAG &DAG) {
12455 EVT VT = SVN->getValueType(0);
12456 int NumElts = VT.getVectorNumElements();
12457 SmallBitVector N0UsedElements(NumElts, false), N1UsedElements(NumElts, false);
12458 for (int M : SVN->getMask())
12459 if (M >= 0 && M < NumElts)
12460 N0UsedElements[M] = true;
12461 else if (M >= NumElts)
12462 N1UsedElements[M - NumElts] = true;
12464 SDValue S0 = simplifyShuffleOperandRecursively(N0UsedElements, N0, DAG);
12465 SDValue S1 = simplifyShuffleOperandRecursively(N1UsedElements, N1, DAG);
12466 if (S0 == N0 && S1 == N1)
12469 return DAG.getVectorShuffle(VT, SDLoc(SVN), S0, S1, SVN->getMask());
12472 // Tries to turn a shuffle of two CONCAT_VECTORS into a single concat,
12473 // or turn a shuffle of a single concat into simpler shuffle then concat.
12474 static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) {
12475 EVT VT = N->getValueType(0);
12476 unsigned NumElts = VT.getVectorNumElements();
12478 SDValue N0 = N->getOperand(0);
12479 SDValue N1 = N->getOperand(1);
12480 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
12482 SmallVector<SDValue, 4> Ops;
12483 EVT ConcatVT = N0.getOperand(0).getValueType();
12484 unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements();
12485 unsigned NumConcats = NumElts / NumElemsPerConcat;
12487 // Special case: shuffle(concat(A,B)) can be more efficiently represented
12488 // as concat(shuffle(A,B),UNDEF) if the shuffle doesn't set any of the high
12489 // half vector elements.
12490 if (NumElemsPerConcat * 2 == NumElts && N1.getOpcode() == ISD::UNDEF &&
12491 std::all_of(SVN->getMask().begin() + NumElemsPerConcat,
12492 SVN->getMask().end(), [](int i) { return i == -1; })) {
12493 N0 = DAG.getVectorShuffle(ConcatVT, SDLoc(N), N0.getOperand(0), N0.getOperand(1),
12494 ArrayRef<int>(SVN->getMask().begin(), NumElemsPerConcat));
12495 N1 = DAG.getUNDEF(ConcatVT);
12496 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, N0, N1);
12499 // Look at every vector that's inserted. We're looking for exact
12500 // subvector-sized copies from a concatenated vector
12501 for (unsigned I = 0; I != NumConcats; ++I) {
12502 // Make sure we're dealing with a copy.
12503 unsigned Begin = I * NumElemsPerConcat;
12504 bool AllUndef = true, NoUndef = true;
12505 for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) {
12506 if (SVN->getMaskElt(J) >= 0)
12513 if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0)
12516 for (unsigned J = 1; J != NumElemsPerConcat; ++J)
12517 if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J))
12520 unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat;
12521 if (FirstElt < N0.getNumOperands())
12522 Ops.push_back(N0.getOperand(FirstElt));
12524 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands()));
12526 } else if (AllUndef) {
12527 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType()));
12528 } else { // Mixed with general masks and undefs, can't do optimization.
12533 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops);
12536 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
12537 EVT VT = N->getValueType(0);
12538 unsigned NumElts = VT.getVectorNumElements();
12540 SDValue N0 = N->getOperand(0);
12541 SDValue N1 = N->getOperand(1);
12543 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG");
12545 // Canonicalize shuffle undef, undef -> undef
12546 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
12547 return DAG.getUNDEF(VT);
12549 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
12551 // Canonicalize shuffle v, v -> v, undef
12553 SmallVector<int, 8> NewMask;
12554 for (unsigned i = 0; i != NumElts; ++i) {
12555 int Idx = SVN->getMaskElt(i);
12556 if (Idx >= (int)NumElts) Idx -= NumElts;
12557 NewMask.push_back(Idx);
12559 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT),
12563 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask.
12564 if (N0.getOpcode() == ISD::UNDEF) {
12565 SmallVector<int, 8> NewMask;
12566 for (unsigned i = 0; i != NumElts; ++i) {
12567 int Idx = SVN->getMaskElt(i);
12569 if (Idx >= (int)NumElts)
12572 Idx = -1; // remove reference to lhs
12574 NewMask.push_back(Idx);
12576 return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT),
12580 // Remove references to rhs if it is undef
12581 if (N1.getOpcode() == ISD::UNDEF) {
12582 bool Changed = false;
12583 SmallVector<int, 8> NewMask;
12584 for (unsigned i = 0; i != NumElts; ++i) {
12585 int Idx = SVN->getMaskElt(i);
12586 if (Idx >= (int)NumElts) {
12590 NewMask.push_back(Idx);
12593 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]);
12596 // If it is a splat, check if the argument vector is another splat or a
12598 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
12599 SDNode *V = N0.getNode();
12601 // If this is a bit convert that changes the element type of the vector but
12602 // not the number of vector elements, look through it. Be careful not to
12603 // look though conversions that change things like v4f32 to v2f64.
12604 if (V->getOpcode() == ISD::BITCAST) {
12605 SDValue ConvInput = V->getOperand(0);
12606 if (ConvInput.getValueType().isVector() &&
12607 ConvInput.getValueType().getVectorNumElements() == NumElts)
12608 V = ConvInput.getNode();
12611 if (V->getOpcode() == ISD::BUILD_VECTOR) {
12612 assert(V->getNumOperands() == NumElts &&
12613 "BUILD_VECTOR has wrong number of operands");
12615 bool AllSame = true;
12616 for (unsigned i = 0; i != NumElts; ++i) {
12617 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
12618 Base = V->getOperand(i);
12622 // Splat of <u, u, u, u>, return <u, u, u, u>
12623 if (!Base.getNode())
12625 for (unsigned i = 0; i != NumElts; ++i) {
12626 if (V->getOperand(i) != Base) {
12631 // Splat of <x, x, x, x>, return <x, x, x, x>
12635 // Canonicalize any other splat as a build_vector.
12636 const SDValue &Splatted = V->getOperand(SVN->getSplatIndex());
12637 SmallVector<SDValue, 8> Ops(NumElts, Splatted);
12638 SDValue NewBV = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
12639 V->getValueType(0), Ops);
12641 // We may have jumped through bitcasts, so the type of the
12642 // BUILD_VECTOR may not match the type of the shuffle.
12643 if (V->getValueType(0) != VT)
12644 NewBV = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, NewBV);
12649 // There are various patterns used to build up a vector from smaller vectors,
12650 // subvectors, or elements. Scan chains of these and replace unused insertions
12651 // or components with undef.
12652 if (SDValue S = simplifyShuffleOperands(SVN, N0, N1, DAG))
12655 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
12656 Level < AfterLegalizeVectorOps &&
12657 (N1.getOpcode() == ISD::UNDEF ||
12658 (N1.getOpcode() == ISD::CONCAT_VECTORS &&
12659 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) {
12660 SDValue V = partitionShuffleOfConcats(N, DAG);
12666 // Attempt to combine a shuffle of 2 inputs of 'scalar sources' -
12667 // BUILD_VECTOR or SCALAR_TO_VECTOR into a single BUILD_VECTOR.
12668 if (Level < AfterLegalizeVectorOps && TLI.isTypeLegal(VT)) {
12669 SmallVector<SDValue, 8> Ops;
12670 for (int M : SVN->getMask()) {
12671 SDValue Op = DAG.getUNDEF(VT.getScalarType());
12673 int Idx = M % NumElts;
12674 SDValue &S = (M < (int)NumElts ? N0 : N1);
12675 if (S.getOpcode() == ISD::BUILD_VECTOR && S.hasOneUse()) {
12676 Op = S.getOperand(Idx);
12677 } else if (S.getOpcode() == ISD::SCALAR_TO_VECTOR && S.hasOneUse()) {
12679 Op = S.getOperand(0);
12681 // Operand can't be combined - bail out.
12687 if (Ops.size() == VT.getVectorNumElements()) {
12688 // BUILD_VECTOR requires all inputs to be of the same type, find the
12689 // maximum type and extend them all.
12690 EVT SVT = VT.getScalarType();
12691 if (SVT.isInteger())
12692 for (SDValue &Op : Ops)
12693 SVT = (SVT.bitsLT(Op.getValueType()) ? Op.getValueType() : SVT);
12694 if (SVT != VT.getScalarType())
12695 for (SDValue &Op : Ops)
12696 Op = TLI.isZExtFree(Op.getValueType(), SVT)
12697 ? DAG.getZExtOrTrunc(Op, SDLoc(N), SVT)
12698 : DAG.getSExtOrTrunc(Op, SDLoc(N), SVT);
12699 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, Ops);
12703 // If this shuffle only has a single input that is a bitcasted shuffle,
12704 // attempt to merge the 2 shuffles and suitably bitcast the inputs/output
12705 // back to their original types.
12706 if (N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
12707 N1.getOpcode() == ISD::UNDEF && Level < AfterLegalizeVectorOps &&
12708 TLI.isTypeLegal(VT)) {
12710 // Peek through the bitcast only if there is one user.
12712 while (BC0.getOpcode() == ISD::BITCAST) {
12713 if (!BC0.hasOneUse())
12715 BC0 = BC0.getOperand(0);
12718 auto ScaleShuffleMask = [](ArrayRef<int> Mask, int Scale) {
12720 return SmallVector<int, 8>(Mask.begin(), Mask.end());
12722 SmallVector<int, 8> NewMask;
12724 for (int s = 0; s != Scale; ++s)
12725 NewMask.push_back(M < 0 ? -1 : Scale * M + s);
12729 if (BC0.getOpcode() == ISD::VECTOR_SHUFFLE && BC0.hasOneUse()) {
12730 EVT SVT = VT.getScalarType();
12731 EVT InnerVT = BC0->getValueType(0);
12732 EVT InnerSVT = InnerVT.getScalarType();
12734 // Determine which shuffle works with the smaller scalar type.
12735 EVT ScaleVT = SVT.bitsLT(InnerSVT) ? VT : InnerVT;
12736 EVT ScaleSVT = ScaleVT.getScalarType();
12738 if (TLI.isTypeLegal(ScaleVT) &&
12739 0 == (InnerSVT.getSizeInBits() % ScaleSVT.getSizeInBits()) &&
12740 0 == (SVT.getSizeInBits() % ScaleSVT.getSizeInBits())) {
12742 int InnerScale = InnerSVT.getSizeInBits() / ScaleSVT.getSizeInBits();
12743 int OuterScale = SVT.getSizeInBits() / ScaleSVT.getSizeInBits();
12745 // Scale the shuffle masks to the smaller scalar type.
12746 ShuffleVectorSDNode *InnerSVN = cast<ShuffleVectorSDNode>(BC0);
12747 SmallVector<int, 8> InnerMask =
12748 ScaleShuffleMask(InnerSVN->getMask(), InnerScale);
12749 SmallVector<int, 8> OuterMask =
12750 ScaleShuffleMask(SVN->getMask(), OuterScale);
12752 // Merge the shuffle masks.
12753 SmallVector<int, 8> NewMask;
12754 for (int M : OuterMask)
12755 NewMask.push_back(M < 0 ? -1 : InnerMask[M]);
12757 // Test for shuffle mask legality over both commutations.
12758 SDValue SV0 = BC0->getOperand(0);
12759 SDValue SV1 = BC0->getOperand(1);
12760 bool LegalMask = TLI.isShuffleMaskLegal(NewMask, ScaleVT);
12762 std::swap(SV0, SV1);
12763 ShuffleVectorSDNode::commuteMask(NewMask);
12764 LegalMask = TLI.isShuffleMaskLegal(NewMask, ScaleVT);
12768 SV0 = DAG.getNode(ISD::BITCAST, SDLoc(N), ScaleVT, SV0);
12769 SV1 = DAG.getNode(ISD::BITCAST, SDLoc(N), ScaleVT, SV1);
12770 return DAG.getNode(
12771 ISD::BITCAST, SDLoc(N), VT,
12772 DAG.getVectorShuffle(ScaleVT, SDLoc(N), SV0, SV1, NewMask));
12778 // Canonicalize shuffles according to rules:
12779 // shuffle(A, shuffle(A, B)) -> shuffle(shuffle(A,B), A)
12780 // shuffle(B, shuffle(A, B)) -> shuffle(shuffle(A,B), B)
12781 // shuffle(B, shuffle(A, Undef)) -> shuffle(shuffle(A, Undef), B)
12782 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE &&
12783 N0.getOpcode() != ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG &&
12784 TLI.isTypeLegal(VT)) {
12785 // The incoming shuffle must be of the same type as the result of the
12786 // current shuffle.
12787 assert(N1->getOperand(0).getValueType() == VT &&
12788 "Shuffle types don't match");
12790 SDValue SV0 = N1->getOperand(0);
12791 SDValue SV1 = N1->getOperand(1);
12792 bool HasSameOp0 = N0 == SV0;
12793 bool IsSV1Undef = SV1.getOpcode() == ISD::UNDEF;
12794 if (HasSameOp0 || IsSV1Undef || N0 == SV1)
12795 // Commute the operands of this shuffle so that next rule
12797 return DAG.getCommutedVectorShuffle(*SVN);
12800 // Try to fold according to rules:
12801 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2)
12802 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2)
12803 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2)
12804 // Don't try to fold shuffles with illegal type.
12805 // Only fold if this shuffle is the only user of the other shuffle.
12806 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && N->isOnlyUserOf(N0.getNode()) &&
12807 Level < AfterLegalizeDAG && TLI.isTypeLegal(VT)) {
12808 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0);
12810 // The incoming shuffle must be of the same type as the result of the
12811 // current shuffle.
12812 assert(OtherSV->getOperand(0).getValueType() == VT &&
12813 "Shuffle types don't match");
12816 SmallVector<int, 4> Mask;
12817 // Compute the combined shuffle mask for a shuffle with SV0 as the first
12818 // operand, and SV1 as the second operand.
12819 for (unsigned i = 0; i != NumElts; ++i) {
12820 int Idx = SVN->getMaskElt(i);
12822 // Propagate Undef.
12823 Mask.push_back(Idx);
12827 SDValue CurrentVec;
12828 if (Idx < (int)NumElts) {
12829 // This shuffle index refers to the inner shuffle N0. Lookup the inner
12830 // shuffle mask to identify which vector is actually referenced.
12831 Idx = OtherSV->getMaskElt(Idx);
12833 // Propagate Undef.
12834 Mask.push_back(Idx);
12838 CurrentVec = (Idx < (int) NumElts) ? OtherSV->getOperand(0)
12839 : OtherSV->getOperand(1);
12841 // This shuffle index references an element within N1.
12845 // Simple case where 'CurrentVec' is UNDEF.
12846 if (CurrentVec.getOpcode() == ISD::UNDEF) {
12847 Mask.push_back(-1);
12851 // Canonicalize the shuffle index. We don't know yet if CurrentVec
12852 // will be the first or second operand of the combined shuffle.
12853 Idx = Idx % NumElts;
12854 if (!SV0.getNode() || SV0 == CurrentVec) {
12855 // Ok. CurrentVec is the left hand side.
12856 // Update the mask accordingly.
12858 Mask.push_back(Idx);
12862 // Bail out if we cannot convert the shuffle pair into a single shuffle.
12863 if (SV1.getNode() && SV1 != CurrentVec)
12866 // Ok. CurrentVec is the right hand side.
12867 // Update the mask accordingly.
12869 Mask.push_back(Idx + NumElts);
12872 // Check if all indices in Mask are Undef. In case, propagate Undef.
12873 bool isUndefMask = true;
12874 for (unsigned i = 0; i != NumElts && isUndefMask; ++i)
12875 isUndefMask &= Mask[i] < 0;
12878 return DAG.getUNDEF(VT);
12880 if (!SV0.getNode())
12881 SV0 = DAG.getUNDEF(VT);
12882 if (!SV1.getNode())
12883 SV1 = DAG.getUNDEF(VT);
12885 // Avoid introducing shuffles with illegal mask.
12886 if (!TLI.isShuffleMaskLegal(Mask, VT)) {
12887 ShuffleVectorSDNode::commuteMask(Mask);
12889 if (!TLI.isShuffleMaskLegal(Mask, VT))
12892 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, A, M2)
12893 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, A, M2)
12894 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(C, B, M2)
12895 std::swap(SV0, SV1);
12898 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, B, M2)
12899 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(A, C, M2)
12900 // shuffle(shuffle(A, B, M0), C, M1) -> shuffle(B, C, M2)
12901 return DAG.getVectorShuffle(VT, SDLoc(N), SV0, SV1, &Mask[0]);
12907 SDValue DAGCombiner::visitSCALAR_TO_VECTOR(SDNode *N) {
12908 SDValue InVal = N->getOperand(0);
12909 EVT VT = N->getValueType(0);
12911 // Replace a SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(V,C0)) pattern
12912 // with a VECTOR_SHUFFLE.
12913 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
12914 SDValue InVec = InVal->getOperand(0);
12915 SDValue EltNo = InVal->getOperand(1);
12917 // FIXME: We could support implicit truncation if the shuffle can be
12918 // scaled to a smaller vector scalar type.
12919 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(EltNo);
12920 if (C0 && VT == InVec.getValueType() &&
12921 VT.getScalarType() == InVal.getValueType()) {
12922 SmallVector<int, 8> NewMask(VT.getVectorNumElements(), -1);
12923 int Elt = C0->getZExtValue();
12926 if (TLI.isShuffleMaskLegal(NewMask, VT))
12927 return DAG.getVectorShuffle(VT, SDLoc(N), InVec, DAG.getUNDEF(VT),
12935 SDValue DAGCombiner::visitINSERT_SUBVECTOR(SDNode *N) {
12936 SDValue N0 = N->getOperand(0);
12937 SDValue N2 = N->getOperand(2);
12939 // If the input vector is a concatenation, and the insert replaces
12940 // one of the halves, we can optimize into a single concat_vectors.
12941 if (N0.getOpcode() == ISD::CONCAT_VECTORS &&
12942 N0->getNumOperands() == 2 && N2.getOpcode() == ISD::Constant) {
12943 APInt InsIdx = cast<ConstantSDNode>(N2)->getAPIntValue();
12944 EVT VT = N->getValueType(0);
12946 // Lower half: fold (insert_subvector (concat_vectors X, Y), Z) ->
12947 // (concat_vectors Z, Y)
12949 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
12950 N->getOperand(1), N0.getOperand(1));
12952 // Upper half: fold (insert_subvector (concat_vectors X, Y), Z) ->
12953 // (concat_vectors X, Z)
12954 if (InsIdx == VT.getVectorNumElements()/2)
12955 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
12956 N0.getOperand(0), N->getOperand(1));
12962 SDValue DAGCombiner::visitFP_TO_FP16(SDNode *N) {
12963 SDValue N0 = N->getOperand(0);
12965 // fold (fp_to_fp16 (fp16_to_fp op)) -> op
12966 if (N0->getOpcode() == ISD::FP16_TO_FP)
12967 return N0->getOperand(0);
12972 /// Returns a vector_shuffle if it able to transform an AND to a vector_shuffle
12973 /// with the destination vector and a zero vector.
12974 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
12975 /// vector_shuffle V, Zero, <0, 4, 2, 4>
12976 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
12977 EVT VT = N->getValueType(0);
12978 SDValue LHS = N->getOperand(0);
12979 SDValue RHS = N->getOperand(1);
12982 // Make sure we're not running after operation legalization where it
12983 // may have custom lowered the vector shuffles.
12984 if (LegalOperations)
12987 if (N->getOpcode() != ISD::AND)
12990 if (RHS.getOpcode() == ISD::BITCAST)
12991 RHS = RHS.getOperand(0);
12993 if (RHS.getOpcode() != ISD::BUILD_VECTOR)
12996 EVT RVT = RHS.getValueType();
12997 unsigned NumElts = RHS.getNumOperands();
12999 // Attempt to create a valid clear mask, splitting the mask into
13000 // sub elements and checking to see if each is
13001 // all zeros or all ones - suitable for shuffle masking.
13002 auto BuildClearMask = [&](int Split) {
13003 int NumSubElts = NumElts * Split;
13004 int NumSubBits = RVT.getScalarSizeInBits() / Split;
13006 SmallVector<int, 8> Indices;
13007 for (int i = 0; i != NumSubElts; ++i) {
13008 int EltIdx = i / Split;
13009 int SubIdx = i % Split;
13010 SDValue Elt = RHS.getOperand(EltIdx);
13011 if (Elt.getOpcode() == ISD::UNDEF) {
13012 Indices.push_back(-1);
13017 if (isa<ConstantSDNode>(Elt))
13018 Bits = cast<ConstantSDNode>(Elt)->getAPIntValue();
13019 else if (isa<ConstantFPSDNode>(Elt))
13020 Bits = cast<ConstantFPSDNode>(Elt)->getValueAPF().bitcastToAPInt();
13024 // Extract the sub element from the constant bit mask.
13025 if (DAG.getDataLayout().isBigEndian()) {
13026 Bits = Bits.lshr((Split - SubIdx - 1) * NumSubBits);
13028 Bits = Bits.lshr(SubIdx * NumSubBits);
13032 Bits = Bits.trunc(NumSubBits);
13034 if (Bits.isAllOnesValue())
13035 Indices.push_back(i);
13036 else if (Bits == 0)
13037 Indices.push_back(i + NumSubElts);
13042 // Let's see if the target supports this vector_shuffle.
13043 EVT ClearSVT = EVT::getIntegerVT(*DAG.getContext(), NumSubBits);
13044 EVT ClearVT = EVT::getVectorVT(*DAG.getContext(), ClearSVT, NumSubElts);
13045 if (!TLI.isVectorClearMaskLegal(Indices, ClearVT))
13048 SDValue Zero = DAG.getConstant(0, dl, ClearVT);
13049 return DAG.getBitcast(VT, DAG.getVectorShuffle(ClearVT, dl,
13050 DAG.getBitcast(ClearVT, LHS),
13051 Zero, &Indices[0]));
13054 // Determine maximum split level (byte level masking).
13056 if (RVT.getScalarSizeInBits() % 8 == 0)
13057 MaxSplit = RVT.getScalarSizeInBits() / 8;
13059 for (int Split = 1; Split <= MaxSplit; ++Split)
13060 if (RVT.getScalarSizeInBits() % Split == 0)
13061 if (SDValue S = BuildClearMask(Split))
13067 /// Visit a binary vector operation, like ADD.
13068 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
13069 assert(N->getValueType(0).isVector() &&
13070 "SimplifyVBinOp only works on vectors!");
13072 SDValue LHS = N->getOperand(0);
13073 SDValue RHS = N->getOperand(1);
13075 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
13077 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
13078 RHS.getOpcode() == ISD::BUILD_VECTOR) {
13079 // Check if both vectors are constants. If not bail out.
13080 if (!(cast<BuildVectorSDNode>(LHS)->isConstant() &&
13081 cast<BuildVectorSDNode>(RHS)->isConstant()))
13084 SmallVector<SDValue, 8> Ops;
13085 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
13086 SDValue LHSOp = LHS.getOperand(i);
13087 SDValue RHSOp = RHS.getOperand(i);
13089 // Can't fold divide by zero.
13090 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
13091 N->getOpcode() == ISD::FDIV) {
13092 if (isNullConstant(RHSOp) || (RHSOp.getOpcode() == ISD::ConstantFP &&
13093 cast<ConstantFPSDNode>(RHSOp.getNode())->isZero()))
13097 EVT VT = LHSOp.getValueType();
13098 EVT RVT = RHSOp.getValueType();
13100 // Integer BUILD_VECTOR operands may have types larger than the element
13101 // size (e.g., when the element type is not legal). Prior to type
13102 // legalization, the types may not match between the two BUILD_VECTORS.
13103 // Truncate one of the operands to make them match.
13104 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
13105 RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, RHSOp);
13107 LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), RVT, LHSOp);
13111 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(LHS), VT,
13113 if (FoldOp.getOpcode() != ISD::UNDEF &&
13114 FoldOp.getOpcode() != ISD::Constant &&
13115 FoldOp.getOpcode() != ISD::ConstantFP)
13117 Ops.push_back(FoldOp);
13118 AddToWorklist(FoldOp.getNode());
13121 if (Ops.size() == LHS.getNumOperands())
13122 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), LHS.getValueType(), Ops);
13125 // Try to convert a constant mask AND into a shuffle clear mask.
13126 if (SDValue Shuffle = XformToShuffleWithZero(N))
13129 // Type legalization might introduce new shuffles in the DAG.
13130 // Fold (VBinOp (shuffle (A, Undef, Mask)), (shuffle (B, Undef, Mask)))
13131 // -> (shuffle (VBinOp (A, B)), Undef, Mask).
13132 if (LegalTypes && isa<ShuffleVectorSDNode>(LHS) &&
13133 isa<ShuffleVectorSDNode>(RHS) && LHS.hasOneUse() && RHS.hasOneUse() &&
13134 LHS.getOperand(1).getOpcode() == ISD::UNDEF &&
13135 RHS.getOperand(1).getOpcode() == ISD::UNDEF) {
13136 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(LHS);
13137 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(RHS);
13139 if (SVN0->getMask().equals(SVN1->getMask())) {
13140 EVT VT = N->getValueType(0);
13141 SDValue UndefVector = LHS.getOperand(1);
13142 SDValue NewBinOp = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
13143 LHS.getOperand(0), RHS.getOperand(0));
13144 AddUsersToWorklist(N);
13145 return DAG.getVectorShuffle(VT, SDLoc(N), NewBinOp, UndefVector,
13146 &SVN0->getMask()[0]);
13153 SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0,
13154 SDValue N1, SDValue N2){
13155 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
13157 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
13158 cast<CondCodeSDNode>(N0.getOperand(2))->get());
13160 // If we got a simplified select_cc node back from SimplifySelectCC, then
13161 // break it down into a new SETCC node, and a new SELECT node, and then return
13162 // the SELECT node, since we were called with a SELECT node.
13163 if (SCC.getNode()) {
13164 // Check to see if we got a select_cc back (to turn into setcc/select).
13165 // Otherwise, just return whatever node we got back, like fabs.
13166 if (SCC.getOpcode() == ISD::SELECT_CC) {
13167 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0),
13169 SCC.getOperand(0), SCC.getOperand(1),
13170 SCC.getOperand(4));
13171 AddToWorklist(SETCC.getNode());
13172 return DAG.getSelect(SDLoc(SCC), SCC.getValueType(), SETCC,
13173 SCC.getOperand(2), SCC.getOperand(3));
13181 /// Given a SELECT or a SELECT_CC node, where LHS and RHS are the two values
13182 /// being selected between, see if we can simplify the select. Callers of this
13183 /// should assume that TheSelect is deleted if this returns true. As such, they
13184 /// should return the appropriate thing (e.g. the node) back to the top-level of
13185 /// the DAG combiner loop to avoid it being looked at.
13186 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
13189 // fold (select (setcc x, -0.0, *lt), NaN, (fsqrt x))
13190 // The select + setcc is redundant, because fsqrt returns NaN for X < -0.
13191 if (const ConstantFPSDNode *NaN = isConstOrConstSplatFP(LHS)) {
13192 if (NaN->isNaN() && RHS.getOpcode() == ISD::FSQRT) {
13193 // We have: (select (setcc ?, ?, ?), NaN, (fsqrt ?))
13194 SDValue Sqrt = RHS;
13197 const ConstantFPSDNode *NegZero = nullptr;
13199 if (TheSelect->getOpcode() == ISD::SELECT_CC) {
13200 CC = dyn_cast<CondCodeSDNode>(TheSelect->getOperand(4))->get();
13201 CmpLHS = TheSelect->getOperand(0);
13202 NegZero = isConstOrConstSplatFP(TheSelect->getOperand(1));
13204 // SELECT or VSELECT
13205 SDValue Cmp = TheSelect->getOperand(0);
13206 if (Cmp.getOpcode() == ISD::SETCC) {
13207 CC = dyn_cast<CondCodeSDNode>(Cmp.getOperand(2))->get();
13208 CmpLHS = Cmp.getOperand(0);
13209 NegZero = isConstOrConstSplatFP(Cmp.getOperand(1));
13212 if (NegZero && NegZero->isNegative() && NegZero->isZero() &&
13213 Sqrt.getOperand(0) == CmpLHS && (CC == ISD::SETOLT ||
13214 CC == ISD::SETULT || CC == ISD::SETLT)) {
13215 // We have: (select (setcc x, -0.0, *lt), NaN, (fsqrt x))
13216 CombineTo(TheSelect, Sqrt);
13221 // Cannot simplify select with vector condition
13222 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
13224 // If this is a select from two identical things, try to pull the operation
13225 // through the select.
13226 if (LHS.getOpcode() != RHS.getOpcode() ||
13227 !LHS.hasOneUse() || !RHS.hasOneUse())
13230 // If this is a load and the token chain is identical, replace the select
13231 // of two loads with a load through a select of the address to load from.
13232 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
13233 // constants have been dropped into the constant pool.
13234 if (LHS.getOpcode() == ISD::LOAD) {
13235 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
13236 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
13238 // Token chains must be identical.
13239 if (LHS.getOperand(0) != RHS.getOperand(0) ||
13240 // Do not let this transformation reduce the number of volatile loads.
13241 LLD->isVolatile() || RLD->isVolatile() ||
13242 // FIXME: If either is a pre/post inc/dec load,
13243 // we'd need to split out the address adjustment.
13244 LLD->isIndexed() || RLD->isIndexed() ||
13245 // If this is an EXTLOAD, the VT's must match.
13246 LLD->getMemoryVT() != RLD->getMemoryVT() ||
13247 // If this is an EXTLOAD, the kind of extension must match.
13248 (LLD->getExtensionType() != RLD->getExtensionType() &&
13249 // The only exception is if one of the extensions is anyext.
13250 LLD->getExtensionType() != ISD::EXTLOAD &&
13251 RLD->getExtensionType() != ISD::EXTLOAD) ||
13252 // FIXME: this discards src value information. This is
13253 // over-conservative. It would be beneficial to be able to remember
13254 // both potential memory locations. Since we are discarding
13255 // src value info, don't do the transformation if the memory
13256 // locations are not in the default address space.
13257 LLD->getPointerInfo().getAddrSpace() != 0 ||
13258 RLD->getPointerInfo().getAddrSpace() != 0 ||
13259 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(),
13260 LLD->getBasePtr().getValueType()))
13263 // Check that the select condition doesn't reach either load. If so,
13264 // folding this will induce a cycle into the DAG. If not, this is safe to
13265 // xform, so create a select of the addresses.
13267 if (TheSelect->getOpcode() == ISD::SELECT) {
13268 SDNode *CondNode = TheSelect->getOperand(0).getNode();
13269 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
13270 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
13272 // The loads must not depend on one another.
13273 if (LLD->isPredecessorOf(RLD) ||
13274 RLD->isPredecessorOf(LLD))
13276 Addr = DAG.getSelect(SDLoc(TheSelect),
13277 LLD->getBasePtr().getValueType(),
13278 TheSelect->getOperand(0), LLD->getBasePtr(),
13279 RLD->getBasePtr());
13280 } else { // Otherwise SELECT_CC
13281 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
13282 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
13284 if ((LLD->hasAnyUseOfValue(1) &&
13285 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
13286 (RLD->hasAnyUseOfValue(1) &&
13287 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS))))
13290 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect),
13291 LLD->getBasePtr().getValueType(),
13292 TheSelect->getOperand(0),
13293 TheSelect->getOperand(1),
13294 LLD->getBasePtr(), RLD->getBasePtr(),
13295 TheSelect->getOperand(4));
13299 // It is safe to replace the two loads if they have different alignments,
13300 // but the new load must be the minimum (most restrictive) alignment of the
13302 bool isInvariant = LLD->isInvariant() & RLD->isInvariant();
13303 unsigned Alignment = std::min(LLD->getAlignment(), RLD->getAlignment());
13304 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
13305 Load = DAG.getLoad(TheSelect->getValueType(0),
13307 // FIXME: Discards pointer and AA info.
13308 LLD->getChain(), Addr, MachinePointerInfo(),
13309 LLD->isVolatile(), LLD->isNonTemporal(),
13310 isInvariant, Alignment);
13312 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
13313 RLD->getExtensionType() : LLD->getExtensionType(),
13315 TheSelect->getValueType(0),
13316 // FIXME: Discards pointer and AA info.
13317 LLD->getChain(), Addr, MachinePointerInfo(),
13318 LLD->getMemoryVT(), LLD->isVolatile(),
13319 LLD->isNonTemporal(), isInvariant, Alignment);
13322 // Users of the select now use the result of the load.
13323 CombineTo(TheSelect, Load);
13325 // Users of the old loads now use the new load's chain. We know the
13326 // old-load value is dead now.
13327 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
13328 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
13335 /// Simplify an expression of the form (N0 cond N1) ? N2 : N3
13336 /// where 'cond' is the comparison specified by CC.
13337 SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
13338 SDValue N2, SDValue N3,
13339 ISD::CondCode CC, bool NotExtCompare) {
13340 // (x ? y : y) -> y.
13341 if (N2 == N3) return N2;
13343 EVT VT = N2.getValueType();
13344 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
13345 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
13347 // Determine if the condition we're dealing with is constant
13348 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
13349 N0, N1, CC, DL, false);
13350 if (SCC.getNode()) AddToWorklist(SCC.getNode());
13352 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
13353 // fold select_cc true, x, y -> x
13354 // fold select_cc false, x, y -> y
13355 return !SCCC->isNullValue() ? N2 : N3;
13358 // Check to see if we can simplify the select into an fabs node
13359 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
13360 // Allow either -0.0 or 0.0
13361 if (CFP->isZero()) {
13362 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
13363 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
13364 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
13365 N2 == N3.getOperand(0))
13366 return DAG.getNode(ISD::FABS, DL, VT, N0);
13368 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
13369 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
13370 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
13371 N2.getOperand(0) == N3)
13372 return DAG.getNode(ISD::FABS, DL, VT, N3);
13376 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
13377 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
13378 // in it. This is a win when the constant is not otherwise available because
13379 // it replaces two constant pool loads with one. We only do this if the FP
13380 // type is known to be legal, because if it isn't, then we are before legalize
13381 // types an we want the other legalization to happen first (e.g. to avoid
13382 // messing with soft float) and if the ConstantFP is not legal, because if
13383 // it is legal, we may not need to store the FP constant in a constant pool.
13384 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
13385 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
13386 if (TLI.isTypeLegal(N2.getValueType()) &&
13387 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
13388 TargetLowering::Legal &&
13389 !TLI.isFPImmLegal(TV->getValueAPF(), TV->getValueType(0)) &&
13390 !TLI.isFPImmLegal(FV->getValueAPF(), FV->getValueType(0))) &&
13391 // If both constants have multiple uses, then we won't need to do an
13392 // extra load, they are likely around in registers for other users.
13393 (TV->hasOneUse() || FV->hasOneUse())) {
13394 Constant *Elts[] = {
13395 const_cast<ConstantFP*>(FV->getConstantFPValue()),
13396 const_cast<ConstantFP*>(TV->getConstantFPValue())
13398 Type *FPTy = Elts[0]->getType();
13399 const DataLayout &TD = DAG.getDataLayout();
13401 // Create a ConstantArray of the two constants.
13402 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
13404 DAG.getConstantPool(CA, TLI.getPointerTy(DAG.getDataLayout()),
13405 TD.getPrefTypeAlignment(FPTy));
13406 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
13408 // Get the offsets to the 0 and 1 element of the array so that we can
13409 // select between them.
13410 SDValue Zero = DAG.getIntPtrConstant(0, DL);
13411 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
13412 SDValue One = DAG.getIntPtrConstant(EltSize, SDLoc(FV));
13414 SDValue Cond = DAG.getSetCC(DL,
13415 getSetCCResultType(N0.getValueType()),
13417 AddToWorklist(Cond.getNode());
13418 SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(),
13420 AddToWorklist(CstOffset.getNode());
13421 CPIdx = DAG.getNode(ISD::ADD, DL, CPIdx.getValueType(), CPIdx,
13423 AddToWorklist(CPIdx.getNode());
13424 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
13425 MachinePointerInfo::getConstantPool(), false,
13426 false, false, Alignment);
13430 // Check to see if we can perform the "gzip trick", transforming
13431 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
13432 if (isNullConstant(N3) && CC == ISD::SETLT &&
13433 (isNullConstant(N1) || // (a < 0) ? b : 0
13434 (isOneConstant(N1) && N0 == N2))) { // (a < 1) ? a : 0
13435 EVT XType = N0.getValueType();
13436 EVT AType = N2.getValueType();
13437 if (XType.bitsGE(AType)) {
13438 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
13439 // single-bit constant.
13440 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue() - 1)) == 0)) {
13441 unsigned ShCtV = N2C->getAPIntValue().logBase2();
13442 ShCtV = XType.getSizeInBits() - ShCtV - 1;
13443 SDValue ShCt = DAG.getConstant(ShCtV, SDLoc(N0),
13444 getShiftAmountTy(N0.getValueType()));
13445 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0),
13447 AddToWorklist(Shift.getNode());
13449 if (XType.bitsGT(AType)) {
13450 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
13451 AddToWorklist(Shift.getNode());
13454 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
13457 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0),
13459 DAG.getConstant(XType.getSizeInBits() - 1,
13461 getShiftAmountTy(N0.getValueType())));
13462 AddToWorklist(Shift.getNode());
13464 if (XType.bitsGT(AType)) {
13465 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
13466 AddToWorklist(Shift.getNode());
13469 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
13473 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
13474 // where y is has a single bit set.
13475 // A plaintext description would be, we can turn the SELECT_CC into an AND
13476 // when the condition can be materialized as an all-ones register. Any
13477 // single bit-test can be materialized as an all-ones register with
13478 // shift-left and shift-right-arith.
13479 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
13480 N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) {
13481 SDValue AndLHS = N0->getOperand(0);
13482 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
13483 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
13484 // Shift the tested bit over the sign bit.
13485 APInt AndMask = ConstAndRHS->getAPIntValue();
13487 DAG.getConstant(AndMask.countLeadingZeros(), SDLoc(AndLHS),
13488 getShiftAmountTy(AndLHS.getValueType()));
13489 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt);
13491 // Now arithmetic right shift it all the way over, so the result is either
13492 // all-ones, or zero.
13494 DAG.getConstant(AndMask.getBitWidth() - 1, SDLoc(Shl),
13495 getShiftAmountTy(Shl.getValueType()));
13496 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt);
13498 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
13502 // fold select C, 16, 0 -> shl C, 4
13503 if (N2C && isNullConstant(N3) && N2C->getAPIntValue().isPowerOf2() &&
13504 TLI.getBooleanContents(N0.getValueType()) ==
13505 TargetLowering::ZeroOrOneBooleanContent) {
13507 // If the caller doesn't want us to simplify this into a zext of a compare,
13509 if (NotExtCompare && N2C->isOne())
13512 // Get a SetCC of the condition
13513 // NOTE: Don't create a SETCC if it's not legal on this target.
13514 if (!LegalOperations ||
13515 TLI.isOperationLegal(ISD::SETCC,
13516 LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) {
13518 // cast from setcc result type to select result type
13520 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()),
13522 if (N2.getValueType().bitsLT(SCC.getValueType()))
13523 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2),
13524 N2.getValueType());
13526 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
13527 N2.getValueType(), SCC);
13529 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC);
13530 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2),
13531 N2.getValueType(), SCC);
13534 AddToWorklist(SCC.getNode());
13535 AddToWorklist(Temp.getNode());
13540 // shl setcc result by log2 n2c
13541 return DAG.getNode(
13542 ISD::SHL, DL, N2.getValueType(), Temp,
13543 DAG.getConstant(N2C->getAPIntValue().logBase2(), SDLoc(Temp),
13544 getShiftAmountTy(Temp.getValueType())));
13548 // Check to see if this is the equivalent of setcc
13549 // FIXME: Turn all of these into setcc if setcc if setcc is legal
13550 // otherwise, go ahead with the folds.
13551 if (0 && isNullConstant(N3) && isOneConstant(N2)) {
13552 EVT XType = N0.getValueType();
13553 if (!LegalOperations ||
13554 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) {
13555 SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC);
13556 if (Res.getValueType() != VT)
13557 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
13561 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
13562 if (isNullConstant(N1) && CC == ISD::SETEQ &&
13563 (!LegalOperations ||
13564 TLI.isOperationLegal(ISD::CTLZ, XType))) {
13565 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0);
13566 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
13567 DAG.getConstant(Log2_32(XType.getSizeInBits()),
13569 getShiftAmountTy(Ctlz.getValueType())));
13571 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
13572 if (isNullConstant(N1) && CC == ISD::SETGT) {
13574 SDValue NegN0 = DAG.getNode(ISD::SUB, DL,
13575 XType, DAG.getConstant(0, DL, XType), N0);
13576 SDValue NotN0 = DAG.getNOT(DL, N0, XType);
13577 return DAG.getNode(ISD::SRL, DL, XType,
13578 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
13579 DAG.getConstant(XType.getSizeInBits() - 1, DL,
13580 getShiftAmountTy(XType)));
13582 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
13583 if (isAllOnesConstant(N1) && CC == ISD::SETGT) {
13585 SDValue Sign = DAG.getNode(ISD::SRL, DL, XType, N0,
13586 DAG.getConstant(XType.getSizeInBits() - 1, DL,
13587 getShiftAmountTy(N0.getValueType())));
13588 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, DL,
13593 // Check to see if this is an integer abs.
13594 // select_cc setg[te] X, 0, X, -X ->
13595 // select_cc setgt X, -1, X, -X ->
13596 // select_cc setl[te] X, 0, -X, X ->
13597 // select_cc setlt X, 1, -X, X ->
13598 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
13600 ConstantSDNode *SubC = nullptr;
13601 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
13602 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
13603 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
13604 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
13605 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
13606 (N1C->isOne() && CC == ISD::SETLT)) &&
13607 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
13608 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
13610 EVT XType = N0.getValueType();
13611 if (SubC && SubC->isNullValue() && XType.isInteger()) {
13613 SDValue Shift = DAG.getNode(ISD::SRA, DL, XType,
13615 DAG.getConstant(XType.getSizeInBits() - 1, DL,
13616 getShiftAmountTy(N0.getValueType())));
13617 SDValue Add = DAG.getNode(ISD::ADD, DL,
13619 AddToWorklist(Shift.getNode());
13620 AddToWorklist(Add.getNode());
13621 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
13628 /// This is a stub for TargetLowering::SimplifySetCC.
13629 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
13630 SDValue N1, ISD::CondCode Cond,
13631 SDLoc DL, bool foldBooleans) {
13632 TargetLowering::DAGCombinerInfo
13633 DagCombineInfo(DAG, Level, false, this);
13634 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
13637 /// Given an ISD::SDIV node expressing a divide by constant, return
13638 /// a DAG expression to select that will generate the same value by multiplying
13639 /// by a magic number.
13640 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
13641 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
13642 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
13646 // Avoid division by zero.
13647 if (C->isNullValue())
13650 std::vector<SDNode*> Built;
13652 TLI.BuildSDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
13654 for (SDNode *N : Built)
13659 /// Given an ISD::SDIV node expressing a divide by constant power of 2, return a
13660 /// DAG expression that will generate the same value by right shifting.
13661 SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) {
13662 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
13666 // Avoid division by zero.
13667 if (C->isNullValue())
13670 std::vector<SDNode *> Built;
13671 SDValue S = TLI.BuildSDIVPow2(N, C->getAPIntValue(), DAG, &Built);
13673 for (SDNode *N : Built)
13678 /// Given an ISD::UDIV node expressing a divide by constant, return a DAG
13679 /// expression that will generate the same value by multiplying by a magic
13681 /// Ref: "Hacker's Delight" or "The PowerPC Compiler Writer's Guide".
13682 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
13683 ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
13687 // Avoid division by zero.
13688 if (C->isNullValue())
13691 std::vector<SDNode*> Built;
13693 TLI.BuildUDIV(N, C->getAPIntValue(), DAG, LegalOperations, &Built);
13695 for (SDNode *N : Built)
13700 SDValue DAGCombiner::BuildReciprocalEstimate(SDValue Op) {
13701 if (Level >= AfterLegalizeDAG)
13704 // Expose the DAG combiner to the target combiner implementations.
13705 TargetLowering::DAGCombinerInfo DCI(DAG, Level, false, this);
13707 unsigned Iterations = 0;
13708 if (SDValue Est = TLI.getRecipEstimate(Op, DCI, Iterations)) {
13710 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
13711 // For the reciprocal, we need to find the zero of the function:
13712 // F(X) = A X - 1 [which has a zero at X = 1/A]
13714 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
13715 // does not require additional intermediate precision]
13716 EVT VT = Op.getValueType();
13718 SDValue FPOne = DAG.getConstantFP(1.0, DL, VT);
13720 AddToWorklist(Est.getNode());
13722 // Newton iterations: Est = Est + Est (1 - Arg * Est)
13723 for (unsigned i = 0; i < Iterations; ++i) {
13724 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Op, Est);
13725 AddToWorklist(NewEst.getNode());
13727 NewEst = DAG.getNode(ISD::FSUB, DL, VT, FPOne, NewEst);
13728 AddToWorklist(NewEst.getNode());
13730 NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst);
13731 AddToWorklist(NewEst.getNode());
13733 Est = DAG.getNode(ISD::FADD, DL, VT, Est, NewEst);
13734 AddToWorklist(Est.getNode());
13743 /// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
13744 /// For the reciprocal sqrt, we need to find the zero of the function:
13745 /// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
13747 /// X_{i+1} = X_i (1.5 - A X_i^2 / 2)
13748 /// As a result, we precompute A/2 prior to the iteration loop.
13749 SDValue DAGCombiner::BuildRsqrtNROneConst(SDValue Arg, SDValue Est,
13750 unsigned Iterations) {
13751 EVT VT = Arg.getValueType();
13753 SDValue ThreeHalves = DAG.getConstantFP(1.5, DL, VT);
13755 // We now need 0.5 * Arg which we can write as (1.5 * Arg - Arg) so that
13756 // this entire sequence requires only one FP constant.
13757 SDValue HalfArg = DAG.getNode(ISD::FMUL, DL, VT, ThreeHalves, Arg);
13758 AddToWorklist(HalfArg.getNode());
13760 HalfArg = DAG.getNode(ISD::FSUB, DL, VT, HalfArg, Arg);
13761 AddToWorklist(HalfArg.getNode());
13763 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
13764 for (unsigned i = 0; i < Iterations; ++i) {
13765 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, Est);
13766 AddToWorklist(NewEst.getNode());
13768 NewEst = DAG.getNode(ISD::FMUL, DL, VT, HalfArg, NewEst);
13769 AddToWorklist(NewEst.getNode());
13771 NewEst = DAG.getNode(ISD::FSUB, DL, VT, ThreeHalves, NewEst);
13772 AddToWorklist(NewEst.getNode());
13774 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst);
13775 AddToWorklist(Est.getNode());
13780 /// Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
13781 /// For the reciprocal sqrt, we need to find the zero of the function:
13782 /// F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
13784 /// X_{i+1} = (-0.5 * X_i) * (A * X_i * X_i + (-3.0))
13785 SDValue DAGCombiner::BuildRsqrtNRTwoConst(SDValue Arg, SDValue Est,
13786 unsigned Iterations) {
13787 EVT VT = Arg.getValueType();
13789 SDValue MinusThree = DAG.getConstantFP(-3.0, DL, VT);
13790 SDValue MinusHalf = DAG.getConstantFP(-0.5, DL, VT);
13792 // Newton iterations: Est = -0.5 * Est * (-3.0 + Arg * Est * Est)
13793 for (unsigned i = 0; i < Iterations; ++i) {
13794 SDValue HalfEst = DAG.getNode(ISD::FMUL, DL, VT, Est, MinusHalf);
13795 AddToWorklist(HalfEst.getNode());
13797 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Est);
13798 AddToWorklist(Est.getNode());
13800 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Arg);
13801 AddToWorklist(Est.getNode());
13803 Est = DAG.getNode(ISD::FADD, DL, VT, Est, MinusThree);
13804 AddToWorklist(Est.getNode());
13806 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, HalfEst);
13807 AddToWorklist(Est.getNode());
13812 SDValue DAGCombiner::BuildRsqrtEstimate(SDValue Op) {
13813 if (Level >= AfterLegalizeDAG)
13816 // Expose the DAG combiner to the target combiner implementations.
13817 TargetLowering::DAGCombinerInfo DCI(DAG, Level, false, this);
13818 unsigned Iterations = 0;
13819 bool UseOneConstNR = false;
13820 if (SDValue Est = TLI.getRsqrtEstimate(Op, DCI, Iterations, UseOneConstNR)) {
13821 AddToWorklist(Est.getNode());
13823 Est = UseOneConstNR ?
13824 BuildRsqrtNROneConst(Op, Est, Iterations) :
13825 BuildRsqrtNRTwoConst(Op, Est, Iterations);
13833 /// Return true if base is a frame index, which is known not to alias with
13834 /// anything but itself. Provides base object and offset as results.
13835 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
13836 const GlobalValue *&GV, const void *&CV) {
13837 // Assume it is a primitive operation.
13838 Base = Ptr; Offset = 0; GV = nullptr; CV = nullptr;
13840 // If it's an adding a simple constant then integrate the offset.
13841 if (Base.getOpcode() == ISD::ADD) {
13842 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
13843 Base = Base.getOperand(0);
13844 Offset += C->getZExtValue();
13848 // Return the underlying GlobalValue, and update the Offset. Return false
13849 // for GlobalAddressSDNode since the same GlobalAddress may be represented
13850 // by multiple nodes with different offsets.
13851 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
13852 GV = G->getGlobal();
13853 Offset += G->getOffset();
13857 // Return the underlying Constant value, and update the Offset. Return false
13858 // for ConstantSDNodes since the same constant pool entry may be represented
13859 // by multiple nodes with different offsets.
13860 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
13861 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
13862 : (const void *)C->getConstVal();
13863 Offset += C->getOffset();
13866 // If it's any of the following then it can't alias with anything but itself.
13867 return isa<FrameIndexSDNode>(Base);
13870 /// Return true if there is any possibility that the two addresses overlap.
13871 bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const {
13872 // If they are the same then they must be aliases.
13873 if (Op0->getBasePtr() == Op1->getBasePtr()) return true;
13875 // If they are both volatile then they cannot be reordered.
13876 if (Op0->isVolatile() && Op1->isVolatile()) return true;
13878 // If one operation reads from invariant memory, and the other may store, they
13879 // cannot alias. These should really be checking the equivalent of mayWrite,
13880 // but it only matters for memory nodes other than load /store.
13881 if (Op0->isInvariant() && Op1->writeMem())
13884 if (Op1->isInvariant() && Op0->writeMem())
13887 // Gather base node and offset information.
13888 SDValue Base1, Base2;
13889 int64_t Offset1, Offset2;
13890 const GlobalValue *GV1, *GV2;
13891 const void *CV1, *CV2;
13892 bool isFrameIndex1 = FindBaseOffset(Op0->getBasePtr(),
13893 Base1, Offset1, GV1, CV1);
13894 bool isFrameIndex2 = FindBaseOffset(Op1->getBasePtr(),
13895 Base2, Offset2, GV2, CV2);
13897 // If they have a same base address then check to see if they overlap.
13898 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
13899 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
13900 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
13902 // It is possible for different frame indices to alias each other, mostly
13903 // when tail call optimization reuses return address slots for arguments.
13904 // To catch this case, look up the actual index of frame indices to compute
13905 // the real alias relationship.
13906 if (isFrameIndex1 && isFrameIndex2) {
13907 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
13908 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
13909 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
13910 return !((Offset1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= Offset2 ||
13911 (Offset2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= Offset1);
13914 // Otherwise, if we know what the bases are, and they aren't identical, then
13915 // we know they cannot alias.
13916 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
13919 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
13920 // compared to the size and offset of the access, we may be able to prove they
13921 // do not alias. This check is conservative for now to catch cases created by
13922 // splitting vector types.
13923 if ((Op0->getOriginalAlignment() == Op1->getOriginalAlignment()) &&
13924 (Op0->getSrcValueOffset() != Op1->getSrcValueOffset()) &&
13925 (Op0->getMemoryVT().getSizeInBits() >> 3 ==
13926 Op1->getMemoryVT().getSizeInBits() >> 3) &&
13927 (Op0->getOriginalAlignment() > Op0->getMemoryVT().getSizeInBits()) >> 3) {
13928 int64_t OffAlign1 = Op0->getSrcValueOffset() % Op0->getOriginalAlignment();
13929 int64_t OffAlign2 = Op1->getSrcValueOffset() % Op1->getOriginalAlignment();
13931 // There is no overlap between these relatively aligned accesses of similar
13932 // size, return no alias.
13933 if ((OffAlign1 + (Op0->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign2 ||
13934 (OffAlign2 + (Op1->getMemoryVT().getSizeInBits() >> 3)) <= OffAlign1)
13938 bool UseAA = CombinerGlobalAA.getNumOccurrences() > 0
13940 : DAG.getSubtarget().useAA();
13942 if (CombinerAAOnlyFunc.getNumOccurrences() &&
13943 CombinerAAOnlyFunc != DAG.getMachineFunction().getName())
13947 Op0->getMemOperand()->getValue() && Op1->getMemOperand()->getValue()) {
13948 // Use alias analysis information.
13949 int64_t MinOffset = std::min(Op0->getSrcValueOffset(),
13950 Op1->getSrcValueOffset());
13951 int64_t Overlap1 = (Op0->getMemoryVT().getSizeInBits() >> 3) +
13952 Op0->getSrcValueOffset() - MinOffset;
13953 int64_t Overlap2 = (Op1->getMemoryVT().getSizeInBits() >> 3) +
13954 Op1->getSrcValueOffset() - MinOffset;
13955 AliasResult AAResult =
13956 AA.alias(MemoryLocation(Op0->getMemOperand()->getValue(), Overlap1,
13957 UseTBAA ? Op0->getAAInfo() : AAMDNodes()),
13958 MemoryLocation(Op1->getMemOperand()->getValue(), Overlap2,
13959 UseTBAA ? Op1->getAAInfo() : AAMDNodes()));
13960 if (AAResult == NoAlias)
13964 // Otherwise we have to assume they alias.
13968 /// Walk up chain skipping non-aliasing memory nodes,
13969 /// looking for aliasing nodes and adding them to the Aliases vector.
13970 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
13971 SmallVectorImpl<SDValue> &Aliases) {
13972 SmallVector<SDValue, 8> Chains; // List of chains to visit.
13973 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
13975 // Get alias information for node.
13976 bool IsLoad = isa<LoadSDNode>(N) && !cast<LSBaseSDNode>(N)->isVolatile();
13979 Chains.push_back(OriginalChain);
13980 unsigned Depth = 0;
13982 // Look at each chain and determine if it is an alias. If so, add it to the
13983 // aliases list. If not, then continue up the chain looking for the next
13985 while (!Chains.empty()) {
13986 SDValue Chain = Chains.pop_back_val();
13988 // For TokenFactor nodes, look at each operand and only continue up the
13989 // chain until we find two aliases. If we've seen two aliases, assume we'll
13990 // find more and revert to original chain since the xform is unlikely to be
13993 // FIXME: The depth check could be made to return the last non-aliasing
13994 // chain we found before we hit a tokenfactor rather than the original
13996 if (Depth > 6 || Aliases.size() == 2) {
13998 Aliases.push_back(OriginalChain);
14002 // Don't bother if we've been before.
14003 if (!Visited.insert(Chain.getNode()).second)
14006 switch (Chain.getOpcode()) {
14007 case ISD::EntryToken:
14008 // Entry token is ideal chain operand, but handled in FindBetterChain.
14013 // Get alias information for Chain.
14014 bool IsOpLoad = isa<LoadSDNode>(Chain.getNode()) &&
14015 !cast<LSBaseSDNode>(Chain.getNode())->isVolatile();
14017 // If chain is alias then stop here.
14018 if (!(IsLoad && IsOpLoad) &&
14019 isAlias(cast<LSBaseSDNode>(N), cast<LSBaseSDNode>(Chain.getNode()))) {
14020 Aliases.push_back(Chain);
14022 // Look further up the chain.
14023 Chains.push_back(Chain.getOperand(0));
14029 case ISD::TokenFactor:
14030 // We have to check each of the operands of the token factor for "small"
14031 // token factors, so we queue them up. Adding the operands to the queue
14032 // (stack) in reverse order maintains the original order and increases the
14033 // likelihood that getNode will find a matching token factor (CSE.)
14034 if (Chain.getNumOperands() > 16) {
14035 Aliases.push_back(Chain);
14038 for (unsigned n = Chain.getNumOperands(); n;)
14039 Chains.push_back(Chain.getOperand(--n));
14044 // For all other instructions we will just have to take what we can get.
14045 Aliases.push_back(Chain);
14050 // We need to be careful here to also search for aliases through the
14051 // value operand of a store, etc. Consider the following situation:
14053 // L1 = load Token1, %52
14054 // S1 = store Token1, L1, %51
14055 // L2 = load Token1, %52+8
14056 // S2 = store Token1, L2, %51+8
14057 // Token2 = Token(S1, S2)
14058 // L3 = load Token2, %53
14059 // S3 = store Token2, L3, %52
14060 // L4 = load Token2, %53+8
14061 // S4 = store Token2, L4, %52+8
14062 // If we search for aliases of S3 (which loads address %52), and we look
14063 // only through the chain, then we'll miss the trivial dependence on L1
14064 // (which also loads from %52). We then might change all loads and
14065 // stores to use Token1 as their chain operand, which could result in
14066 // copying %53 into %52 before copying %52 into %51 (which should
14069 // The problem is, however, that searching for such data dependencies
14070 // can become expensive, and the cost is not directly related to the
14071 // chain depth. Instead, we'll rule out such configurations here by
14072 // insisting that we've visited all chain users (except for users
14073 // of the original chain, which is not necessary). When doing this,
14074 // we need to look through nodes we don't care about (otherwise, things
14075 // like register copies will interfere with trivial cases).
14077 SmallVector<const SDNode *, 16> Worklist;
14078 for (const SDNode *N : Visited)
14079 if (N != OriginalChain.getNode())
14080 Worklist.push_back(N);
14082 while (!Worklist.empty()) {
14083 const SDNode *M = Worklist.pop_back_val();
14085 // We have already visited M, and want to make sure we've visited any uses
14086 // of M that we care about. For uses that we've not visisted, and don't
14087 // care about, queue them to the worklist.
14089 for (SDNode::use_iterator UI = M->use_begin(),
14090 UIE = M->use_end(); UI != UIE; ++UI)
14091 if (UI.getUse().getValueType() == MVT::Other &&
14092 Visited.insert(*UI).second) {
14093 if (isa<MemSDNode>(*UI)) {
14094 // We've not visited this use, and we care about it (it could have an
14095 // ordering dependency with the original node).
14097 Aliases.push_back(OriginalChain);
14101 // We've not visited this use, but we don't care about it. Mark it as
14102 // visited and enqueue it to the worklist.
14103 Worklist.push_back(*UI);
14108 /// Walk up chain skipping non-aliasing memory nodes, looking for a better chain
14109 /// (aliasing node.)
14110 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
14111 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
14113 // Accumulate all the aliases to this node.
14114 GatherAllAliases(N, OldChain, Aliases);
14116 // If no operands then chain to entry token.
14117 if (Aliases.size() == 0)
14118 return DAG.getEntryNode();
14120 // If a single operand then chain to it. We don't need to revisit it.
14121 if (Aliases.size() == 1)
14124 // Construct a custom tailored token factor.
14125 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, Aliases);
14128 /// This is the entry point for the file.
14129 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
14130 CodeGenOpt::Level OptLevel) {
14131 /// This is the main entry point to this class.
14132 DAGCombiner(*this, AA, OptLevel).Run(Level);