1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // This pass is not a substitute for the LLVM IR instcombine pass. This pass is
14 // primarily intended to handle simplification opportunities that are implicit
15 // in the LLVM IR and exposed by the various codegen lowering phases.
17 //===----------------------------------------------------------------------===//
19 #define DEBUG_TYPE "dagcombine"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/LLVMContext.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/Target/TargetData.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/ADT/SmallPtrSet.h"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
41 STATISTIC(NodesCombined , "Number of dag nodes combined");
42 STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
43 STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
44 STATISTIC(OpsNarrowed , "Number of load/op/store narrowed");
45 STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int");
49 CombinerAA("combiner-alias-analysis", cl::Hidden,
50 cl::desc("Turn on alias analysis during testing"));
53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
54 cl::desc("Include global information in alias analysis"));
56 //------------------------------ DAGCombiner ---------------------------------//
60 const TargetLowering &TLI;
62 CodeGenOpt::Level OptLevel;
66 // Worklist of all of the nodes that need to be simplified.
67 std::vector<SDNode*> WorkList;
69 // AA - Used for DAG load/store alias analysis.
72 /// AddUsersToWorkList - When an instruction is simplified, add all users of
73 /// the instruction to the work lists because they might get more simplified
76 void AddUsersToWorkList(SDNode *N) {
77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
82 /// visit - call the node-specific routine that knows how to fold each
83 /// particular type of node.
84 SDValue visit(SDNode *N);
87 /// AddToWorkList - Add to the work list making sure it's instance is at the
88 /// the back (next to be processed.)
89 void AddToWorkList(SDNode *N) {
90 removeFromWorkList(N);
91 WorkList.push_back(N);
94 /// removeFromWorkList - remove all instances of N from the worklist.
96 void removeFromWorkList(SDNode *N) {
97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
105 return CombineTo(N, &Res, 1, AddTo);
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
110 SDValue To[] = { Res0, Res1 };
111 return CombineTo(N, To, 2, AddTo);
114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO);
118 /// SimplifyDemandedBits - Check the specified integer node value to see if
119 /// it can be simplified or if things it uses can be simplified by bit
120 /// propagation. If so, return true.
121 bool SimplifyDemandedBits(SDValue Op) {
122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
123 APInt Demanded = APInt::getAllOnesValue(BitWidth);
124 return SimplifyDemandedBits(Op, Demanded);
127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
129 bool CombineToPreIndexedLoadStore(SDNode *N);
130 bool CombineToPostIndexedLoadStore(SDNode *N);
132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad);
133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace);
134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT);
135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT);
136 SDValue PromoteIntBinOp(SDValue Op);
137 SDValue PromoteIntShiftOp(SDValue Op);
138 SDValue PromoteExtend(SDValue Op);
139 bool PromoteLoad(SDValue Op);
141 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
142 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
143 ISD::NodeType ExtType);
145 /// combine - call the node-specific routine that knows how to fold each
146 /// particular type of node. If that doesn't do anything, try the
147 /// target-specific DAG combines.
148 SDValue combine(SDNode *N);
150 // Visitation implementation - Implement dag node combining for different
151 // node types. The semantics are as follows:
153 // SDValue.getNode() == 0 - No change was made
154 // SDValue.getNode() == N - N was replaced, is dead and has been handled.
155 // otherwise - N should be replaced by the returned Operand.
157 SDValue visitTokenFactor(SDNode *N);
158 SDValue visitMERGE_VALUES(SDNode *N);
159 SDValue visitADD(SDNode *N);
160 SDValue visitSUB(SDNode *N);
161 SDValue visitADDC(SDNode *N);
162 SDValue visitADDE(SDNode *N);
163 SDValue visitMUL(SDNode *N);
164 SDValue visitSDIV(SDNode *N);
165 SDValue visitUDIV(SDNode *N);
166 SDValue visitSREM(SDNode *N);
167 SDValue visitUREM(SDNode *N);
168 SDValue visitMULHU(SDNode *N);
169 SDValue visitMULHS(SDNode *N);
170 SDValue visitSMUL_LOHI(SDNode *N);
171 SDValue visitUMUL_LOHI(SDNode *N);
172 SDValue visitSMULO(SDNode *N);
173 SDValue visitUMULO(SDNode *N);
174 SDValue visitSDIVREM(SDNode *N);
175 SDValue visitUDIVREM(SDNode *N);
176 SDValue visitAND(SDNode *N);
177 SDValue visitOR(SDNode *N);
178 SDValue visitXOR(SDNode *N);
179 SDValue SimplifyVBinOp(SDNode *N);
180 SDValue visitSHL(SDNode *N);
181 SDValue visitSRA(SDNode *N);
182 SDValue visitSRL(SDNode *N);
183 SDValue visitCTLZ(SDNode *N);
184 SDValue visitCTTZ(SDNode *N);
185 SDValue visitCTPOP(SDNode *N);
186 SDValue visitSELECT(SDNode *N);
187 SDValue visitSELECT_CC(SDNode *N);
188 SDValue visitSETCC(SDNode *N);
189 SDValue visitSIGN_EXTEND(SDNode *N);
190 SDValue visitZERO_EXTEND(SDNode *N);
191 SDValue visitANY_EXTEND(SDNode *N);
192 SDValue visitSIGN_EXTEND_INREG(SDNode *N);
193 SDValue visitTRUNCATE(SDNode *N);
194 SDValue visitBITCAST(SDNode *N);
195 SDValue visitBUILD_PAIR(SDNode *N);
196 SDValue visitFADD(SDNode *N);
197 SDValue visitFSUB(SDNode *N);
198 SDValue visitFMUL(SDNode *N);
199 SDValue visitFDIV(SDNode *N);
200 SDValue visitFREM(SDNode *N);
201 SDValue visitFCOPYSIGN(SDNode *N);
202 SDValue visitSINT_TO_FP(SDNode *N);
203 SDValue visitUINT_TO_FP(SDNode *N);
204 SDValue visitFP_TO_SINT(SDNode *N);
205 SDValue visitFP_TO_UINT(SDNode *N);
206 SDValue visitFP_ROUND(SDNode *N);
207 SDValue visitFP_ROUND_INREG(SDNode *N);
208 SDValue visitFP_EXTEND(SDNode *N);
209 SDValue visitFNEG(SDNode *N);
210 SDValue visitFABS(SDNode *N);
211 SDValue visitBRCOND(SDNode *N);
212 SDValue visitBR_CC(SDNode *N);
213 SDValue visitLOAD(SDNode *N);
214 SDValue visitSTORE(SDNode *N);
215 SDValue visitINSERT_VECTOR_ELT(SDNode *N);
216 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
217 SDValue visitBUILD_VECTOR(SDNode *N);
218 SDValue visitCONCAT_VECTORS(SDNode *N);
219 SDValue visitEXTRACT_SUBVECTOR(SDNode *N);
220 SDValue visitVECTOR_SHUFFLE(SDNode *N);
221 SDValue visitMEMBARRIER(SDNode *N);
223 SDValue XformToShuffleWithZero(SDNode *N);
224 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS);
226 SDValue visitShiftByConstant(SDNode *N, unsigned Amt);
228 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
229 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N);
230 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2);
231 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
232 SDValue N3, ISD::CondCode CC,
233 bool NotExtCompare = false);
234 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
235 DebugLoc DL, bool foldBooleans = true);
236 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
238 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
239 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
240 SDValue BuildSDIV(SDNode *N);
241 SDValue BuildUDIV(SDNode *N);
242 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
243 bool DemandHighBits = true);
244 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
245 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
246 SDValue ReduceLoadWidth(SDNode *N);
247 SDValue ReduceLoadOpStoreWidth(SDNode *N);
248 SDValue TransformFPLoadStorePair(SDNode *N);
250 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
252 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
253 /// looking for aliasing nodes and adding them to the Aliases vector.
254 void GatherAllAliases(SDNode *N, SDValue OriginalChain,
255 SmallVector<SDValue, 8> &Aliases);
257 /// isAlias - Return true if there is any possibility that the two addresses
259 bool isAlias(SDValue Ptr1, int64_t Size1,
260 const Value *SrcValue1, int SrcValueOffset1,
261 unsigned SrcValueAlign1,
262 const MDNode *TBAAInfo1,
263 SDValue Ptr2, int64_t Size2,
264 const Value *SrcValue2, int SrcValueOffset2,
265 unsigned SrcValueAlign2,
266 const MDNode *TBAAInfo2) const;
268 /// FindAliasInfo - Extracts the relevant alias information from the memory
269 /// node. Returns true if the operand was a load.
270 bool FindAliasInfo(SDNode *N,
271 SDValue &Ptr, int64_t &Size,
272 const Value *&SrcValue, int &SrcValueOffset,
273 unsigned &SrcValueAlignment,
274 const MDNode *&TBAAInfo) const;
276 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
277 /// looking for a better chain (aliasing node.)
278 SDValue FindBetterChain(SDNode *N, SDValue Chain);
281 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL)
282 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted),
283 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {}
285 /// Run - runs the dag combiner on all nodes in the work list
286 void Run(CombineLevel AtLevel);
288 SelectionDAG &getDAG() const { return DAG; }
290 /// getShiftAmountTy - Returns a type large enough to hold any valid
291 /// shift amount - before type legalization these can be huge.
292 EVT getShiftAmountTy(EVT LHSTy) {
293 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy();
296 /// isTypeLegal - This method returns true if we are running before type
297 /// legalization or if the specified VT is legal.
298 bool isTypeLegal(const EVT &VT) {
299 if (!LegalTypes) return true;
300 return TLI.isTypeLegal(VT);
307 /// WorkListRemover - This class is a DAGUpdateListener that removes any deleted
308 /// nodes from the worklist.
309 class WorkListRemover : public SelectionDAG::DAGUpdateListener {
312 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {}
314 virtual void NodeDeleted(SDNode *N, SDNode *E) {
315 DC.removeFromWorkList(N);
318 virtual void NodeUpdated(SDNode *N) {
324 //===----------------------------------------------------------------------===//
325 // TargetLowering::DAGCombinerInfo implementation
326 //===----------------------------------------------------------------------===//
328 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
329 ((DAGCombiner*)DC)->AddToWorkList(N);
332 void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) {
333 ((DAGCombiner*)DC)->removeFromWorkList(N);
336 SDValue TargetLowering::DAGCombinerInfo::
337 CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) {
338 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo);
341 SDValue TargetLowering::DAGCombinerInfo::
342 CombineTo(SDNode *N, SDValue Res, bool AddTo) {
343 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo);
347 SDValue TargetLowering::DAGCombinerInfo::
348 CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) {
349 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo);
352 void TargetLowering::DAGCombinerInfo::
353 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
354 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO);
357 //===----------------------------------------------------------------------===//
359 //===----------------------------------------------------------------------===//
361 /// isNegatibleForFree - Return 1 if we can compute the negated form of the
362 /// specified expression for the same cost as the expression itself, or 2 if we
363 /// can compute the negated form more cheaply than the expression itself.
364 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
365 unsigned Depth = 0) {
366 // No compile time optimizations on this type.
367 if (Op.getValueType() == MVT::ppcf128)
370 // fneg is removable even if it has multiple uses.
371 if (Op.getOpcode() == ISD::FNEG) return 2;
373 // Don't allow anything with multiple uses.
374 if (!Op.hasOneUse()) return 0;
376 // Don't recurse exponentially.
377 if (Depth > 6) return 0;
379 switch (Op.getOpcode()) {
380 default: return false;
381 case ISD::ConstantFP:
382 // Don't invert constant FP values after legalize. The negated constant
383 // isn't necessarily legal.
384 return LegalOperations ? 0 : 1;
386 // FIXME: determine better conditions for this xform.
387 if (!UnsafeFPMath) return 0;
389 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B)
390 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
392 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
393 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
395 // We can't turn -(A-B) into B-A when we honor signed zeros.
396 if (!UnsafeFPMath) return 0;
398 // fold (fneg (fsub A, B)) -> (fsub B, A)
403 if (HonorSignDependentRoundingFPMath()) return 0;
405 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y))
406 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
409 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
414 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
418 /// GetNegatedExpression - If isNegatibleForFree returns true, this function
419 /// returns the newly negated expression.
420 static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG,
421 bool LegalOperations, unsigned Depth = 0) {
422 // fneg is removable even if it has multiple uses.
423 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
425 // Don't allow anything with multiple uses.
426 assert(Op.hasOneUse() && "Unknown reuse!");
428 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree");
429 switch (Op.getOpcode()) {
430 default: llvm_unreachable("Unknown code");
431 case ISD::ConstantFP: {
432 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF();
434 return DAG.getConstantFP(V, Op.getValueType());
437 // FIXME: determine better conditions for this xform.
438 assert(UnsafeFPMath);
440 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B)
441 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
442 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
443 GetNegatedExpression(Op.getOperand(0), DAG,
444 LegalOperations, Depth+1),
446 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A)
447 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
448 GetNegatedExpression(Op.getOperand(1), DAG,
449 LegalOperations, Depth+1),
452 // We can't turn -(A-B) into B-A when we honor signed zeros.
453 assert(UnsafeFPMath);
455 // fold (fneg (fsub 0, B)) -> B
456 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0)))
457 if (N0CFP->getValueAPF().isZero())
458 return Op.getOperand(1);
460 // fold (fneg (fsub A, B)) -> (fsub B, A)
461 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
462 Op.getOperand(1), Op.getOperand(0));
466 assert(!HonorSignDependentRoundingFPMath());
468 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y)
469 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
470 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
471 GetNegatedExpression(Op.getOperand(0), DAG,
472 LegalOperations, Depth+1),
475 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y))
476 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
478 GetNegatedExpression(Op.getOperand(1), DAG,
479 LegalOperations, Depth+1));
483 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(),
484 GetNegatedExpression(Op.getOperand(0), DAG,
485 LegalOperations, Depth+1));
487 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(),
488 GetNegatedExpression(Op.getOperand(0), DAG,
489 LegalOperations, Depth+1),
495 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
496 // that selects between the values 1 and 0, making it equivalent to a setcc.
497 // Also, set the incoming LHS, RHS, and CC references to the appropriate
498 // nodes based on the type of node we are checking. This simplifies life a
499 // bit for the callers.
500 static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS,
502 if (N.getOpcode() == ISD::SETCC) {
503 LHS = N.getOperand(0);
504 RHS = N.getOperand(1);
505 CC = N.getOperand(2);
508 if (N.getOpcode() == ISD::SELECT_CC &&
509 N.getOperand(2).getOpcode() == ISD::Constant &&
510 N.getOperand(3).getOpcode() == ISD::Constant &&
511 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 &&
512 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
513 LHS = N.getOperand(0);
514 RHS = N.getOperand(1);
515 CC = N.getOperand(4);
521 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
522 // one use. If this is true, it allows the users to invert the operation for
523 // free when it is profitable to do so.
524 static bool isOneUseSetCC(SDValue N) {
526 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse())
531 SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
532 SDValue N0, SDValue N1) {
533 EVT VT = N0.getValueType();
534 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
535 if (isa<ConstantSDNode>(N1)) {
536 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
538 DAG.FoldConstantArithmetic(Opc, VT,
539 cast<ConstantSDNode>(N0.getOperand(1)),
540 cast<ConstantSDNode>(N1));
541 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode);
543 if (N0.hasOneUse()) {
544 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
545 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
546 N0.getOperand(0), N1);
547 AddToWorkList(OpNode.getNode());
548 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1));
552 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
553 if (isa<ConstantSDNode>(N0)) {
554 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
556 DAG.FoldConstantArithmetic(Opc, VT,
557 cast<ConstantSDNode>(N1.getOperand(1)),
558 cast<ConstantSDNode>(N0));
559 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode);
561 if (N1.hasOneUse()) {
562 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
563 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT,
564 N1.getOperand(0), N0);
565 AddToWorkList(OpNode.getNode());
566 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1));
573 SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
575 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
577 DEBUG(dbgs() << "\nReplacing.1 ";
579 dbgs() << "\nWith: ";
580 To[0].getNode()->dump(&DAG);
581 dbgs() << " and " << NumTo-1 << " other values\n";
582 for (unsigned i = 0, e = NumTo; i != e; ++i)
583 assert((!To[i].getNode() ||
584 N->getValueType(i) == To[i].getValueType()) &&
585 "Cannot combine value to value of different type!"));
586 WorkListRemover DeadNodes(*this);
587 DAG.ReplaceAllUsesWith(N, To, &DeadNodes);
590 // Push the new nodes and any users onto the worklist
591 for (unsigned i = 0, e = NumTo; i != e; ++i) {
592 if (To[i].getNode()) {
593 AddToWorkList(To[i].getNode());
594 AddUsersToWorkList(To[i].getNode());
599 // Finally, if the node is now dead, remove it from the graph. The node
600 // may not be dead if the replacement process recursively simplified to
601 // something else needing this node.
602 if (N->use_empty()) {
603 // Nodes can be reintroduced into the worklist. Make sure we do not
604 // process a node that has been replaced.
605 removeFromWorkList(N);
607 // Finally, since the node is now dead, remove it from the graph.
610 return SDValue(N, 0);
614 CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) {
615 // Replace all uses. If any nodes become isomorphic to other nodes and
616 // are deleted, make sure to remove them from our worklist.
617 WorkListRemover DeadNodes(*this);
618 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes);
620 // Push the new node and any (possibly new) users onto the worklist.
621 AddToWorkList(TLO.New.getNode());
622 AddUsersToWorkList(TLO.New.getNode());
624 // Finally, if the node is now dead, remove it from the graph. The node
625 // may not be dead if the replacement process recursively simplified to
626 // something else needing this node.
627 if (TLO.Old.getNode()->use_empty()) {
628 removeFromWorkList(TLO.Old.getNode());
630 // If the operands of this node are only used by the node, they will now
631 // be dead. Make sure to visit them first to delete dead nodes early.
632 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i)
633 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse())
634 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode());
636 DAG.DeleteNode(TLO.Old.getNode());
640 /// SimplifyDemandedBits - Check the specified integer node value to see if
641 /// it can be simplified or if things it uses can be simplified by bit
642 /// propagation. If so, return true.
643 bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) {
644 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations);
645 APInt KnownZero, KnownOne;
646 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
650 AddToWorkList(Op.getNode());
652 // Replace the old value with the new one.
654 DEBUG(dbgs() << "\nReplacing.2 ";
655 TLO.Old.getNode()->dump(&DAG);
656 dbgs() << "\nWith: ";
657 TLO.New.getNode()->dump(&DAG);
660 CommitTargetLoweringOpt(TLO);
664 void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) {
665 DebugLoc dl = Load->getDebugLoc();
666 EVT VT = Load->getValueType(0);
667 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0));
669 DEBUG(dbgs() << "\nReplacing.9 ";
671 dbgs() << "\nWith: ";
672 Trunc.getNode()->dump(&DAG);
674 WorkListRemover DeadNodes(*this);
675 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes);
676 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1),
678 removeFromWorkList(Load);
679 DAG.DeleteNode(Load);
680 AddToWorkList(Trunc.getNode());
683 SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) {
685 DebugLoc dl = Op.getDebugLoc();
686 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) {
687 EVT MemVT = LD->getMemoryVT();
688 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
689 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
691 : LD->getExtensionType();
693 return DAG.getExtLoad(ExtType, dl, PVT,
694 LD->getChain(), LD->getBasePtr(),
695 LD->getPointerInfo(),
696 MemVT, LD->isVolatile(),
697 LD->isNonTemporal(), LD->getAlignment());
700 unsigned Opc = Op.getOpcode();
703 case ISD::AssertSext:
704 return DAG.getNode(ISD::AssertSext, dl, PVT,
705 SExtPromoteOperand(Op.getOperand(0), PVT),
707 case ISD::AssertZext:
708 return DAG.getNode(ISD::AssertZext, dl, PVT,
709 ZExtPromoteOperand(Op.getOperand(0), PVT),
711 case ISD::Constant: {
713 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
714 return DAG.getNode(ExtOpc, dl, PVT, Op);
718 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT))
720 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op);
723 SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) {
724 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT))
726 EVT OldVT = Op.getValueType();
727 DebugLoc dl = Op.getDebugLoc();
728 bool Replace = false;
729 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
730 if (NewOp.getNode() == 0)
732 AddToWorkList(NewOp.getNode());
735 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
736 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp,
737 DAG.getValueType(OldVT));
740 SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) {
741 EVT OldVT = Op.getValueType();
742 DebugLoc dl = Op.getDebugLoc();
743 bool Replace = false;
744 SDValue NewOp = PromoteOperand(Op, PVT, Replace);
745 if (NewOp.getNode() == 0)
747 AddToWorkList(NewOp.getNode());
750 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode());
751 return DAG.getZeroExtendInReg(NewOp, dl, OldVT);
754 /// PromoteIntBinOp - Promote the specified integer binary operation if the
755 /// target indicates it is beneficial. e.g. On x86, it's usually better to
756 /// promote i16 operations to i32 since i16 instructions are longer.
757 SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) {
758 if (!LegalOperations)
761 EVT VT = Op.getValueType();
762 if (VT.isVector() || !VT.isInteger())
765 // If operation type is 'undesirable', e.g. i16 on x86, consider
767 unsigned Opc = Op.getOpcode();
768 if (TLI.isTypeDesirableForOp(Opc, VT))
772 // Consult target whether it is a good idea to promote this operation and
773 // what's the right type to promote it to.
774 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
775 assert(PVT != VT && "Don't know what type to promote to!");
777 bool Replace0 = false;
778 SDValue N0 = Op.getOperand(0);
779 SDValue NN0 = PromoteOperand(N0, PVT, Replace0);
780 if (NN0.getNode() == 0)
783 bool Replace1 = false;
784 SDValue N1 = Op.getOperand(1);
789 NN1 = PromoteOperand(N1, PVT, Replace1);
790 if (NN1.getNode() == 0)
794 AddToWorkList(NN0.getNode());
796 AddToWorkList(NN1.getNode());
799 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode());
801 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode());
803 DEBUG(dbgs() << "\nPromoting ";
804 Op.getNode()->dump(&DAG));
805 DebugLoc dl = Op.getDebugLoc();
806 return DAG.getNode(ISD::TRUNCATE, dl, VT,
807 DAG.getNode(Opc, dl, PVT, NN0, NN1));
812 /// PromoteIntShiftOp - Promote the specified integer shift operation if the
813 /// target indicates it is beneficial. e.g. On x86, it's usually better to
814 /// promote i16 operations to i32 since i16 instructions are longer.
815 SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) {
816 if (!LegalOperations)
819 EVT VT = Op.getValueType();
820 if (VT.isVector() || !VT.isInteger())
823 // If operation type is 'undesirable', e.g. i16 on x86, consider
825 unsigned Opc = Op.getOpcode();
826 if (TLI.isTypeDesirableForOp(Opc, VT))
830 // Consult target whether it is a good idea to promote this operation and
831 // what's the right type to promote it to.
832 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
833 assert(PVT != VT && "Don't know what type to promote to!");
835 bool Replace = false;
836 SDValue N0 = Op.getOperand(0);
838 N0 = SExtPromoteOperand(Op.getOperand(0), PVT);
839 else if (Opc == ISD::SRL)
840 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT);
842 N0 = PromoteOperand(N0, PVT, Replace);
843 if (N0.getNode() == 0)
846 AddToWorkList(N0.getNode());
848 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode());
850 DEBUG(dbgs() << "\nPromoting ";
851 Op.getNode()->dump(&DAG));
852 DebugLoc dl = Op.getDebugLoc();
853 return DAG.getNode(ISD::TRUNCATE, dl, VT,
854 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1)));
859 SDValue DAGCombiner::PromoteExtend(SDValue Op) {
860 if (!LegalOperations)
863 EVT VT = Op.getValueType();
864 if (VT.isVector() || !VT.isInteger())
867 // If operation type is 'undesirable', e.g. i16 on x86, consider
869 unsigned Opc = Op.getOpcode();
870 if (TLI.isTypeDesirableForOp(Opc, VT))
874 // Consult target whether it is a good idea to promote this operation and
875 // what's the right type to promote it to.
876 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
877 assert(PVT != VT && "Don't know what type to promote to!");
878 // fold (aext (aext x)) -> (aext x)
879 // fold (aext (zext x)) -> (zext x)
880 // fold (aext (sext x)) -> (sext x)
881 DEBUG(dbgs() << "\nPromoting ";
882 Op.getNode()->dump(&DAG));
883 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0));
888 bool DAGCombiner::PromoteLoad(SDValue Op) {
889 if (!LegalOperations)
892 EVT VT = Op.getValueType();
893 if (VT.isVector() || !VT.isInteger())
896 // If operation type is 'undesirable', e.g. i16 on x86, consider
898 unsigned Opc = Op.getOpcode();
899 if (TLI.isTypeDesirableForOp(Opc, VT))
903 // Consult target whether it is a good idea to promote this operation and
904 // what's the right type to promote it to.
905 if (TLI.IsDesirableToPromoteOp(Op, PVT)) {
906 assert(PVT != VT && "Don't know what type to promote to!");
908 DebugLoc dl = Op.getDebugLoc();
909 SDNode *N = Op.getNode();
910 LoadSDNode *LD = cast<LoadSDNode>(N);
911 EVT MemVT = LD->getMemoryVT();
912 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD)
913 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD
915 : LD->getExtensionType();
916 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
917 LD->getChain(), LD->getBasePtr(),
918 LD->getPointerInfo(),
919 MemVT, LD->isVolatile(),
920 LD->isNonTemporal(), LD->getAlignment());
921 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD);
923 DEBUG(dbgs() << "\nPromoting ";
926 Result.getNode()->dump(&DAG);
928 WorkListRemover DeadNodes(*this);
929 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes);
930 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes);
931 removeFromWorkList(N);
933 AddToWorkList(Result.getNode());
940 //===----------------------------------------------------------------------===//
941 // Main DAG Combiner implementation
942 //===----------------------------------------------------------------------===//
944 void DAGCombiner::Run(CombineLevel AtLevel) {
945 // set the instance variables, so that the various visit routines may use it.
947 LegalOperations = Level >= NoIllegalOperations;
948 LegalTypes = Level >= NoIllegalTypes;
950 // Add all the dag nodes to the worklist.
951 WorkList.reserve(DAG.allnodes_size());
952 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
953 E = DAG.allnodes_end(); I != E; ++I)
954 WorkList.push_back(I);
956 // Create a dummy node (which is not added to allnodes), that adds a reference
957 // to the root node, preventing it from being deleted, and tracking any
958 // changes of the root.
959 HandleSDNode Dummy(DAG.getRoot());
961 // The root of the dag may dangle to deleted nodes until the dag combiner is
962 // done. Set it to null to avoid confusion.
963 DAG.setRoot(SDValue());
965 // while the worklist isn't empty, inspect the node on the end of it and
966 // try and combine it.
967 while (!WorkList.empty()) {
968 SDNode *N = WorkList.back();
971 // If N has no uses, it is dead. Make sure to revisit all N's operands once
972 // N is deleted from the DAG, since they too may now be dead or may have a
973 // reduced number of uses, allowing other xforms.
974 if (N->use_empty() && N != &Dummy) {
975 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
976 AddToWorkList(N->getOperand(i).getNode());
982 SDValue RV = combine(N);
984 if (RV.getNode() == 0)
989 // If we get back the same node we passed in, rather than a new node or
990 // zero, we know that the node must have defined multiple values and
991 // CombineTo was used. Since CombineTo takes care of the worklist
992 // mechanics for us, we have no work to do in this case.
993 if (RV.getNode() == N)
996 assert(N->getOpcode() != ISD::DELETED_NODE &&
997 RV.getNode()->getOpcode() != ISD::DELETED_NODE &&
998 "Node was deleted but visit returned new node!");
1000 DEBUG(dbgs() << "\nReplacing.3 ";
1002 dbgs() << "\nWith: ";
1003 RV.getNode()->dump(&DAG);
1006 // Transfer debug value.
1007 DAG.TransferDbgValues(SDValue(N, 0), RV);
1008 WorkListRemover DeadNodes(*this);
1009 if (N->getNumValues() == RV.getNode()->getNumValues())
1010 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes);
1012 assert(N->getValueType(0) == RV.getValueType() &&
1013 N->getNumValues() == 1 && "Type mismatch");
1015 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes);
1018 // Push the new node and any users onto the worklist
1019 AddToWorkList(RV.getNode());
1020 AddUsersToWorkList(RV.getNode());
1022 // Add any uses of the old node to the worklist in case this node is the
1023 // last one that uses them. They may become dead after this node is
1025 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1026 AddToWorkList(N->getOperand(i).getNode());
1028 // Finally, if the node is now dead, remove it from the graph. The node
1029 // may not be dead if the replacement process recursively simplified to
1030 // something else needing this node.
1031 if (N->use_empty()) {
1032 // Nodes can be reintroduced into the worklist. Make sure we do not
1033 // process a node that has been replaced.
1034 removeFromWorkList(N);
1036 // Finally, since the node is now dead, remove it from the graph.
1041 // If the root changed (e.g. it was a dead load, update the root).
1042 DAG.setRoot(Dummy.getValue());
1045 SDValue DAGCombiner::visit(SDNode *N) {
1046 switch (N->getOpcode()) {
1048 case ISD::TokenFactor: return visitTokenFactor(N);
1049 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N);
1050 case ISD::ADD: return visitADD(N);
1051 case ISD::SUB: return visitSUB(N);
1052 case ISD::ADDC: return visitADDC(N);
1053 case ISD::ADDE: return visitADDE(N);
1054 case ISD::MUL: return visitMUL(N);
1055 case ISD::SDIV: return visitSDIV(N);
1056 case ISD::UDIV: return visitUDIV(N);
1057 case ISD::SREM: return visitSREM(N);
1058 case ISD::UREM: return visitUREM(N);
1059 case ISD::MULHU: return visitMULHU(N);
1060 case ISD::MULHS: return visitMULHS(N);
1061 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N);
1062 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N);
1063 case ISD::SMULO: return visitSMULO(N);
1064 case ISD::UMULO: return visitUMULO(N);
1065 case ISD::SDIVREM: return visitSDIVREM(N);
1066 case ISD::UDIVREM: return visitUDIVREM(N);
1067 case ISD::AND: return visitAND(N);
1068 case ISD::OR: return visitOR(N);
1069 case ISD::XOR: return visitXOR(N);
1070 case ISD::SHL: return visitSHL(N);
1071 case ISD::SRA: return visitSRA(N);
1072 case ISD::SRL: return visitSRL(N);
1073 case ISD::CTLZ: return visitCTLZ(N);
1074 case ISD::CTTZ: return visitCTTZ(N);
1075 case ISD::CTPOP: return visitCTPOP(N);
1076 case ISD::SELECT: return visitSELECT(N);
1077 case ISD::SELECT_CC: return visitSELECT_CC(N);
1078 case ISD::SETCC: return visitSETCC(N);
1079 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
1080 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
1081 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
1082 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
1083 case ISD::TRUNCATE: return visitTRUNCATE(N);
1084 case ISD::BITCAST: return visitBITCAST(N);
1085 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N);
1086 case ISD::FADD: return visitFADD(N);
1087 case ISD::FSUB: return visitFSUB(N);
1088 case ISD::FMUL: return visitFMUL(N);
1089 case ISD::FDIV: return visitFDIV(N);
1090 case ISD::FREM: return visitFREM(N);
1091 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
1092 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
1093 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
1094 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
1095 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
1096 case ISD::FP_ROUND: return visitFP_ROUND(N);
1097 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
1098 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
1099 case ISD::FNEG: return visitFNEG(N);
1100 case ISD::FABS: return visitFABS(N);
1101 case ISD::BRCOND: return visitBRCOND(N);
1102 case ISD::BR_CC: return visitBR_CC(N);
1103 case ISD::LOAD: return visitLOAD(N);
1104 case ISD::STORE: return visitSTORE(N);
1105 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
1106 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N);
1107 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N);
1108 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N);
1109 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N);
1110 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
1111 case ISD::MEMBARRIER: return visitMEMBARRIER(N);
1116 SDValue DAGCombiner::combine(SDNode *N) {
1117 SDValue RV = visit(N);
1119 // If nothing happened, try a target-specific DAG combine.
1120 if (RV.getNode() == 0) {
1121 assert(N->getOpcode() != ISD::DELETED_NODE &&
1122 "Node was deleted but visit returned NULL!");
1124 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
1125 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) {
1127 // Expose the DAG combiner to the target combiner impls.
1128 TargetLowering::DAGCombinerInfo
1129 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
1131 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
1135 // If nothing happened still, try promoting the operation.
1136 if (RV.getNode() == 0) {
1137 switch (N->getOpcode()) {
1145 RV = PromoteIntBinOp(SDValue(N, 0));
1150 RV = PromoteIntShiftOp(SDValue(N, 0));
1152 case ISD::SIGN_EXTEND:
1153 case ISD::ZERO_EXTEND:
1154 case ISD::ANY_EXTEND:
1155 RV = PromoteExtend(SDValue(N, 0));
1158 if (PromoteLoad(SDValue(N, 0)))
1164 // If N is a commutative binary node, try commuting it to enable more
1166 if (RV.getNode() == 0 &&
1167 SelectionDAG::isCommutativeBinOp(N->getOpcode()) &&
1168 N->getNumValues() == 1) {
1169 SDValue N0 = N->getOperand(0);
1170 SDValue N1 = N->getOperand(1);
1172 // Constant operands are canonicalized to RHS.
1173 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
1174 SDValue Ops[] = { N1, N0 };
1175 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(),
1178 return SDValue(CSENode, 0);
1185 /// getInputChainForNode - Given a node, return its input chain if it has one,
1186 /// otherwise return a null sd operand.
1187 static SDValue getInputChainForNode(SDNode *N) {
1188 if (unsigned NumOps = N->getNumOperands()) {
1189 if (N->getOperand(0).getValueType() == MVT::Other)
1190 return N->getOperand(0);
1191 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
1192 return N->getOperand(NumOps-1);
1193 for (unsigned i = 1; i < NumOps-1; ++i)
1194 if (N->getOperand(i).getValueType() == MVT::Other)
1195 return N->getOperand(i);
1200 SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
1201 // If N has two operands, where one has an input chain equal to the other,
1202 // the 'other' chain is redundant.
1203 if (N->getNumOperands() == 2) {
1204 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1))
1205 return N->getOperand(0);
1206 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0))
1207 return N->getOperand(1);
1210 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
1211 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
1212 SmallPtrSet<SDNode*, 16> SeenOps;
1213 bool Changed = false; // If we should replace this token factor.
1215 // Start out with this token factor.
1218 // Iterate through token factors. The TFs grows when new token factors are
1220 for (unsigned i = 0; i < TFs.size(); ++i) {
1221 SDNode *TF = TFs[i];
1223 // Check each of the operands.
1224 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
1225 SDValue Op = TF->getOperand(i);
1227 switch (Op.getOpcode()) {
1228 case ISD::EntryToken:
1229 // Entry tokens don't need to be added to the list. They are
1234 case ISD::TokenFactor:
1235 if (Op.hasOneUse() &&
1236 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) {
1237 // Queue up for processing.
1238 TFs.push_back(Op.getNode());
1239 // Clean up in case the token factor is removed.
1240 AddToWorkList(Op.getNode());
1247 // Only add if it isn't already in the list.
1248 if (SeenOps.insert(Op.getNode()))
1259 // If we've change things around then replace token factor.
1262 // The entry token is the only possible outcome.
1263 Result = DAG.getEntryNode();
1265 // New and improved token factor.
1266 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
1267 MVT::Other, &Ops[0], Ops.size());
1270 // Don't add users to work list.
1271 return CombineTo(N, Result, false);
1277 /// MERGE_VALUES can always be eliminated.
1278 SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) {
1279 WorkListRemover DeadNodes(*this);
1280 // Replacing results may cause a different MERGE_VALUES to suddenly
1281 // be CSE'd with N, and carry its uses with it. Iterate until no
1282 // uses remain, to ensure that the node can be safely deleted.
1284 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
1285 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i),
1287 } while (!N->use_empty());
1288 removeFromWorkList(N);
1290 return SDValue(N, 0); // Return N so it doesn't get rechecked!
1294 SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
1295 SelectionDAG &DAG) {
1296 EVT VT = N0.getValueType();
1297 SDValue N00 = N0.getOperand(0);
1298 SDValue N01 = N0.getOperand(1);
1299 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
1301 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() &&
1302 isa<ConstantSDNode>(N00.getOperand(1))) {
1303 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1304 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
1305 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT,
1306 N00.getOperand(0), N01),
1307 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT,
1308 N00.getOperand(1), N01));
1309 return DAG.getNode(ISD::ADD, DL, VT, N0, N1);
1315 SDValue DAGCombiner::visitADD(SDNode *N) {
1316 SDValue N0 = N->getOperand(0);
1317 SDValue N1 = N->getOperand(1);
1318 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1319 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1320 EVT VT = N0.getValueType();
1323 if (VT.isVector()) {
1324 SDValue FoldedVOp = SimplifyVBinOp(N);
1325 if (FoldedVOp.getNode()) return FoldedVOp;
1328 // fold (add x, undef) -> undef
1329 if (N0.getOpcode() == ISD::UNDEF)
1331 if (N1.getOpcode() == ISD::UNDEF)
1333 // fold (add c1, c2) -> c1+c2
1335 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C);
1336 // canonicalize constant to RHS
1338 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0);
1339 // fold (add x, 0) -> x
1340 if (N1C && N1C->isNullValue())
1342 // fold (add Sym, c) -> Sym+c
1343 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1344 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C &&
1345 GA->getOpcode() == ISD::GlobalAddress)
1346 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1348 (uint64_t)N1C->getSExtValue());
1349 // fold ((c1-A)+c2) -> (c1+c2)-A
1350 if (N1C && N0.getOpcode() == ISD::SUB)
1351 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
1352 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1353 DAG.getConstant(N1C->getAPIntValue()+
1354 N0C->getAPIntValue(), VT),
1357 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1);
1358 if (RADD.getNode() != 0)
1360 // fold ((0-A) + B) -> B-A
1361 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
1362 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
1363 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1));
1364 // fold (A + (0-B)) -> A-B
1365 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
1366 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
1367 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1));
1368 // fold (A+(B-A)) -> B
1369 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
1370 return N1.getOperand(0);
1371 // fold ((B-A)+A) -> B
1372 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1))
1373 return N0.getOperand(0);
1374 // fold (A+(B-(A+C))) to (B-C)
1375 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1376 N0 == N1.getOperand(1).getOperand(0))
1377 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1378 N1.getOperand(1).getOperand(1));
1379 // fold (A+(B-(C+A))) to (B-C)
1380 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD &&
1381 N0 == N1.getOperand(1).getOperand(1))
1382 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0),
1383 N1.getOperand(1).getOperand(0));
1384 // fold (A+((B-A)+or-C)) to (B+or-C)
1385 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) &&
1386 N1.getOperand(0).getOpcode() == ISD::SUB &&
1387 N0 == N1.getOperand(0).getOperand(1))
1388 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT,
1389 N1.getOperand(0).getOperand(0), N1.getOperand(1));
1391 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant
1392 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) {
1393 SDValue N00 = N0.getOperand(0);
1394 SDValue N01 = N0.getOperand(1);
1395 SDValue N10 = N1.getOperand(0);
1396 SDValue N11 = N1.getOperand(1);
1398 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
1399 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1400 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10),
1401 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11));
1404 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0)))
1405 return SDValue(N, 0);
1407 // fold (a+b) -> (a|b) iff a and b share no bits.
1408 if (VT.isInteger() && !VT.isVector()) {
1409 APInt LHSZero, LHSOne;
1410 APInt RHSZero, RHSOne;
1411 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1412 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1414 if (LHSZero.getBoolValue()) {
1415 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1417 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1418 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1419 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1420 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1421 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1);
1425 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), )
1426 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) {
1427 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG);
1428 if (Result.getNode()) return Result;
1430 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) {
1431 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG);
1432 if (Result.getNode()) return Result;
1435 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
1436 if (N1.getOpcode() == ISD::SHL &&
1437 N1.getOperand(0).getOpcode() == ISD::SUB)
1438 if (ConstantSDNode *C =
1439 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0)))
1440 if (C->getAPIntValue() == 0)
1441 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0,
1442 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1443 N1.getOperand(0).getOperand(1),
1445 if (N0.getOpcode() == ISD::SHL &&
1446 N0.getOperand(0).getOpcode() == ISD::SUB)
1447 if (ConstantSDNode *C =
1448 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0)))
1449 if (C->getAPIntValue() == 0)
1450 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1,
1451 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1452 N0.getOperand(0).getOperand(1),
1455 if (N1.getOpcode() == ISD::AND) {
1456 SDValue AndOp0 = N1.getOperand(0);
1457 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1));
1458 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0);
1459 unsigned DestBits = VT.getScalarType().getSizeInBits();
1461 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x))
1462 // and similar xforms where the inner op is either ~0 or 0.
1463 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) {
1464 DebugLoc DL = N->getDebugLoc();
1465 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0);
1469 // add (sext i1), X -> sub X, (zext i1)
1470 if (N0.getOpcode() == ISD::SIGN_EXTEND &&
1471 N0.getOperand(0).getValueType() == MVT::i1 &&
1472 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
1473 DebugLoc DL = N->getDebugLoc();
1474 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0));
1475 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt);
1481 SDValue DAGCombiner::visitADDC(SDNode *N) {
1482 SDValue N0 = N->getOperand(0);
1483 SDValue N1 = N->getOperand(1);
1484 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1485 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1486 EVT VT = N0.getValueType();
1488 // If the flag result is dead, turn this into an ADD.
1489 if (N->hasNUsesOfValue(0, 1))
1490 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
1491 DAG.getNode(ISD::CARRY_FALSE,
1492 N->getDebugLoc(), MVT::Glue));
1494 // canonicalize constant to RHS.
1496 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1498 // fold (addc x, 0) -> x + no carry out
1499 if (N1C && N1C->isNullValue())
1500 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1501 N->getDebugLoc(), MVT::Glue));
1503 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
1504 APInt LHSZero, LHSOne;
1505 APInt RHSZero, RHSOne;
1506 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
1507 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
1509 if (LHSZero.getBoolValue()) {
1510 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
1512 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
1513 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
1514 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
1515 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
1516 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
1517 DAG.getNode(ISD::CARRY_FALSE,
1518 N->getDebugLoc(), MVT::Glue));
1524 SDValue DAGCombiner::visitADDE(SDNode *N) {
1525 SDValue N0 = N->getOperand(0);
1526 SDValue N1 = N->getOperand(1);
1527 SDValue CarryIn = N->getOperand(2);
1528 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1529 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1531 // canonicalize constant to RHS
1533 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(),
1536 // fold (adde x, y, false) -> (addc x, y)
1537 if (CarryIn.getOpcode() == ISD::CARRY_FALSE)
1538 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0);
1543 // Since it may not be valid to emit a fold to zero for vector initializers
1544 // check if we can before folding.
1545 static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT,
1546 SelectionDAG &DAG, bool LegalOperations) {
1547 if (!VT.isVector()) {
1548 return DAG.getConstant(0, VT);
1550 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1551 // Produce a vector of zeros.
1552 SDValue El = DAG.getConstant(0, VT.getVectorElementType());
1553 std::vector<SDValue> Ops(VT.getVectorNumElements(), El);
1554 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT,
1555 &Ops[0], Ops.size());
1560 SDValue DAGCombiner::visitSUB(SDNode *N) {
1561 SDValue N0 = N->getOperand(0);
1562 SDValue N1 = N->getOperand(1);
1563 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1564 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1565 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 :
1566 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode());
1567 EVT VT = N0.getValueType();
1570 if (VT.isVector()) {
1571 SDValue FoldedVOp = SimplifyVBinOp(N);
1572 if (FoldedVOp.getNode()) return FoldedVOp;
1575 // fold (sub x, x) -> 0
1576 // FIXME: Refactor this and xor and other similar operations together.
1578 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
1579 // fold (sub c1, c2) -> c1-c2
1581 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C);
1582 // fold (sub x, c) -> (add x, -c)
1584 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0,
1585 DAG.getConstant(-N1C->getAPIntValue(), VT));
1586 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
1587 if (N0C && N0C->isAllOnesValue())
1588 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
1589 // fold A-(A-B) -> B
1590 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0))
1591 return N1.getOperand(1);
1592 // fold (A+B)-A -> B
1593 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
1594 return N0.getOperand(1);
1595 // fold (A+B)-B -> A
1596 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
1597 return N0.getOperand(0);
1598 // fold C2-(A+C1) -> (C2-C1)-A
1599 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) {
1600 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT);
1601 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC,
1604 // fold ((A+(B+or-C))-B) -> A+or-C
1605 if (N0.getOpcode() == ISD::ADD &&
1606 (N0.getOperand(1).getOpcode() == ISD::SUB ||
1607 N0.getOperand(1).getOpcode() == ISD::ADD) &&
1608 N0.getOperand(1).getOperand(0) == N1)
1609 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT,
1610 N0.getOperand(0), N0.getOperand(1).getOperand(1));
1611 // fold ((A+(C+B))-B) -> A+C
1612 if (N0.getOpcode() == ISD::ADD &&
1613 N0.getOperand(1).getOpcode() == ISD::ADD &&
1614 N0.getOperand(1).getOperand(1) == N1)
1615 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1616 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1617 // fold ((A-(B-C))-C) -> A-B
1618 if (N0.getOpcode() == ISD::SUB &&
1619 N0.getOperand(1).getOpcode() == ISD::SUB &&
1620 N0.getOperand(1).getOperand(1) == N1)
1621 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1622 N0.getOperand(0), N0.getOperand(1).getOperand(0));
1624 // If either operand of a sub is undef, the result is undef
1625 if (N0.getOpcode() == ISD::UNDEF)
1627 if (N1.getOpcode() == ISD::UNDEF)
1630 // If the relocation model supports it, consider symbol offsets.
1631 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))
1632 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) {
1633 // fold (sub Sym, c) -> Sym-c
1634 if (N1C && GA->getOpcode() == ISD::GlobalAddress)
1635 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT,
1637 (uint64_t)N1C->getSExtValue());
1638 // fold (sub Sym+c1, Sym+c2) -> c1-c2
1639 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1))
1640 if (GA->getGlobal() == GB->getGlobal())
1641 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(),
1648 SDValue DAGCombiner::visitMUL(SDNode *N) {
1649 SDValue N0 = N->getOperand(0);
1650 SDValue N1 = N->getOperand(1);
1651 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1652 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1653 EVT VT = N0.getValueType();
1656 if (VT.isVector()) {
1657 SDValue FoldedVOp = SimplifyVBinOp(N);
1658 if (FoldedVOp.getNode()) return FoldedVOp;
1661 // fold (mul x, undef) -> 0
1662 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1663 return DAG.getConstant(0, VT);
1664 // fold (mul c1, c2) -> c1*c2
1666 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C);
1667 // canonicalize constant to RHS
1669 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0);
1670 // fold (mul x, 0) -> 0
1671 if (N1C && N1C->isNullValue())
1673 // fold (mul x, -1) -> 0-x
1674 if (N1C && N1C->isAllOnesValue())
1675 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1676 DAG.getConstant(0, VT), N0);
1677 // fold (mul x, (1 << c)) -> x << c
1678 if (N1C && N1C->getAPIntValue().isPowerOf2())
1679 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1680 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1681 getShiftAmountTy(N0.getValueType())));
1682 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
1683 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) {
1684 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2();
1685 // FIXME: If the input is something that is easily negated (e.g. a
1686 // single-use add), we should put the negate there.
1687 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1688 DAG.getConstant(0, VT),
1689 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
1690 DAG.getConstant(Log2Val,
1691 getShiftAmountTy(N0.getValueType()))));
1693 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
1694 if (N1C && N0.getOpcode() == ISD::SHL &&
1695 isa<ConstantSDNode>(N0.getOperand(1))) {
1696 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1697 N1, N0.getOperand(1));
1698 AddToWorkList(C3.getNode());
1699 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1700 N0.getOperand(0), C3);
1703 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
1706 SDValue Sh(0,0), Y(0,0);
1707 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
1708 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
1709 N0.getNode()->hasOneUse()) {
1711 } else if (N1.getOpcode() == ISD::SHL &&
1712 isa<ConstantSDNode>(N1.getOperand(1)) &&
1713 N1.getNode()->hasOneUse()) {
1718 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1719 Sh.getOperand(0), Y);
1720 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT,
1721 Mul, Sh.getOperand(1));
1725 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
1726 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
1727 isa<ConstantSDNode>(N0.getOperand(1)))
1728 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT,
1729 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT,
1730 N0.getOperand(0), N1),
1731 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT,
1732 N0.getOperand(1), N1));
1735 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1);
1736 if (RMUL.getNode() != 0)
1742 SDValue DAGCombiner::visitSDIV(SDNode *N) {
1743 SDValue N0 = N->getOperand(0);
1744 SDValue N1 = N->getOperand(1);
1745 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1746 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1747 EVT VT = N->getValueType(0);
1750 if (VT.isVector()) {
1751 SDValue FoldedVOp = SimplifyVBinOp(N);
1752 if (FoldedVOp.getNode()) return FoldedVOp;
1755 // fold (sdiv c1, c2) -> c1/c2
1756 if (N0C && N1C && !N1C->isNullValue())
1757 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C);
1758 // fold (sdiv X, 1) -> X
1759 if (N1C && N1C->getAPIntValue() == 1LL)
1761 // fold (sdiv X, -1) -> 0-X
1762 if (N1C && N1C->isAllOnesValue())
1763 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1764 DAG.getConstant(0, VT), N0);
1765 // If we know the sign bits of both operands are zero, strength reduce to a
1766 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1767 if (!VT.isVector()) {
1768 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1769 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(),
1772 // fold (sdiv X, pow2) -> simple ops after legalize
1773 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() &&
1774 (N1C->getAPIntValue().isPowerOf2() ||
1775 (-N1C->getAPIntValue()).isPowerOf2())) {
1776 // If dividing by powers of two is cheap, then don't perform the following
1778 if (TLI.isPow2DivCheap())
1781 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros();
1783 // Splat the sign bit into the register
1784 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
1785 DAG.getConstant(VT.getSizeInBits()-1,
1786 getShiftAmountTy(N0.getValueType())));
1787 AddToWorkList(SGN.getNode());
1789 // Add (N0 < 0) ? abs2 - 1 : 0;
1790 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN,
1791 DAG.getConstant(VT.getSizeInBits() - lg2,
1792 getShiftAmountTy(SGN.getValueType())));
1793 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL);
1794 AddToWorkList(SRL.getNode());
1795 AddToWorkList(ADD.getNode()); // Divide by pow2
1796 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD,
1797 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType())));
1799 // If we're dividing by a positive value, we're done. Otherwise, we must
1800 // negate the result.
1801 if (N1C->getAPIntValue().isNonNegative())
1804 AddToWorkList(SRA.getNode());
1805 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT,
1806 DAG.getConstant(0, VT), SRA);
1809 // if integer divide is expensive and we satisfy the requirements, emit an
1810 // alternate sequence.
1811 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1812 SDValue Op = BuildSDIV(N);
1813 if (Op.getNode()) return Op;
1817 if (N0.getOpcode() == ISD::UNDEF)
1818 return DAG.getConstant(0, VT);
1819 // X / undef -> undef
1820 if (N1.getOpcode() == ISD::UNDEF)
1826 SDValue DAGCombiner::visitUDIV(SDNode *N) {
1827 SDValue N0 = N->getOperand(0);
1828 SDValue N1 = N->getOperand(1);
1829 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
1830 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
1831 EVT VT = N->getValueType(0);
1834 if (VT.isVector()) {
1835 SDValue FoldedVOp = SimplifyVBinOp(N);
1836 if (FoldedVOp.getNode()) return FoldedVOp;
1839 // fold (udiv c1, c2) -> c1/c2
1840 if (N0C && N1C && !N1C->isNullValue())
1841 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C);
1842 // fold (udiv x, (1 << c)) -> x >>u c
1843 if (N1C && N1C->getAPIntValue().isPowerOf2())
1844 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
1845 DAG.getConstant(N1C->getAPIntValue().logBase2(),
1846 getShiftAmountTy(N0.getValueType())));
1847 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
1848 if (N1.getOpcode() == ISD::SHL) {
1849 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1850 if (SHC->getAPIntValue().isPowerOf2()) {
1851 EVT ADDVT = N1.getOperand(1).getValueType();
1852 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
1854 DAG.getConstant(SHC->getAPIntValue()
1857 AddToWorkList(Add.getNode());
1858 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add);
1862 // fold (udiv x, c) -> alternate
1863 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) {
1864 SDValue Op = BuildUDIV(N);
1865 if (Op.getNode()) return Op;
1869 if (N0.getOpcode() == ISD::UNDEF)
1870 return DAG.getConstant(0, VT);
1871 // X / undef -> undef
1872 if (N1.getOpcode() == ISD::UNDEF)
1878 SDValue DAGCombiner::visitSREM(SDNode *N) {
1879 SDValue N0 = N->getOperand(0);
1880 SDValue N1 = N->getOperand(1);
1881 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1882 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1883 EVT VT = N->getValueType(0);
1885 // fold (srem c1, c2) -> c1%c2
1886 if (N0C && N1C && !N1C->isNullValue())
1887 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C);
1888 // If we know the sign bits of both operands are zero, strength reduce to a
1889 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1890 if (!VT.isVector()) {
1891 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
1892 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1);
1895 // If X/C can be simplified by the division-by-constant logic, lower
1896 // X%C to the equivalent of X-X/C*C.
1897 if (N1C && !N1C->isNullValue()) {
1898 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1);
1899 AddToWorkList(Div.getNode());
1900 SDValue OptimizedDiv = combine(Div.getNode());
1901 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1902 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1904 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1905 AddToWorkList(Mul.getNode());
1911 if (N0.getOpcode() == ISD::UNDEF)
1912 return DAG.getConstant(0, VT);
1913 // X % undef -> undef
1914 if (N1.getOpcode() == ISD::UNDEF)
1920 SDValue DAGCombiner::visitUREM(SDNode *N) {
1921 SDValue N0 = N->getOperand(0);
1922 SDValue N1 = N->getOperand(1);
1923 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1924 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1925 EVT VT = N->getValueType(0);
1927 // fold (urem c1, c2) -> c1%c2
1928 if (N0C && N1C && !N1C->isNullValue())
1929 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C);
1930 // fold (urem x, pow2) -> (and x, pow2-1)
1931 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2())
1932 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0,
1933 DAG.getConstant(N1C->getAPIntValue()-1,VT));
1934 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
1935 if (N1.getOpcode() == ISD::SHL) {
1936 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
1937 if (SHC->getAPIntValue().isPowerOf2()) {
1939 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1,
1940 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
1942 AddToWorkList(Add.getNode());
1943 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add);
1948 // If X/C can be simplified by the division-by-constant logic, lower
1949 // X%C to the equivalent of X-X/C*C.
1950 if (N1C && !N1C->isNullValue()) {
1951 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1);
1952 AddToWorkList(Div.getNode());
1953 SDValue OptimizedDiv = combine(Div.getNode());
1954 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) {
1955 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT,
1957 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul);
1958 AddToWorkList(Mul.getNode());
1964 if (N0.getOpcode() == ISD::UNDEF)
1965 return DAG.getConstant(0, VT);
1966 // X % undef -> undef
1967 if (N1.getOpcode() == ISD::UNDEF)
1973 SDValue DAGCombiner::visitMULHS(SDNode *N) {
1974 SDValue N0 = N->getOperand(0);
1975 SDValue N1 = N->getOperand(1);
1976 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1977 EVT VT = N->getValueType(0);
1978 DebugLoc DL = N->getDebugLoc();
1980 // fold (mulhs x, 0) -> 0
1981 if (N1C && N1C->isNullValue())
1983 // fold (mulhs x, 1) -> (sra x, size(x)-1)
1984 if (N1C && N1C->getAPIntValue() == 1)
1985 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0,
1986 DAG.getConstant(N0.getValueType().getSizeInBits() - 1,
1987 getShiftAmountTy(N0.getValueType())));
1988 // fold (mulhs x, undef) -> 0
1989 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
1990 return DAG.getConstant(0, VT);
1992 // If the type twice as wide is legal, transform the mulhs to a wider multiply
1994 if (VT.isSimple() && !VT.isVector()) {
1995 MVT Simple = VT.getSimpleVT();
1996 unsigned SimpleSize = Simple.getSizeInBits();
1997 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
1998 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
1999 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0);
2000 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1);
2001 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2002 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2003 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2004 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2011 SDValue DAGCombiner::visitMULHU(SDNode *N) {
2012 SDValue N0 = N->getOperand(0);
2013 SDValue N1 = N->getOperand(1);
2014 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2015 EVT VT = N->getValueType(0);
2016 DebugLoc DL = N->getDebugLoc();
2018 // fold (mulhu x, 0) -> 0
2019 if (N1C && N1C->isNullValue())
2021 // fold (mulhu x, 1) -> 0
2022 if (N1C && N1C->getAPIntValue() == 1)
2023 return DAG.getConstant(0, N0.getValueType());
2024 // fold (mulhu x, undef) -> 0
2025 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2026 return DAG.getConstant(0, VT);
2028 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2030 if (VT.isSimple() && !VT.isVector()) {
2031 MVT Simple = VT.getSimpleVT();
2032 unsigned SimpleSize = Simple.getSizeInBits();
2033 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2034 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2035 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0);
2036 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1);
2037 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1);
2038 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1,
2039 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType())));
2040 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1);
2047 /// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that
2048 /// compute two values. LoOp and HiOp give the opcodes for the two computations
2049 /// that are being performed. Return true if a simplification was made.
2051 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
2053 // If the high half is not needed, just compute the low half.
2054 bool HiExists = N->hasAnyUseOfValue(1);
2056 (!LegalOperations ||
2057 TLI.isOperationLegal(LoOp, N->getValueType(0)))) {
2058 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2059 N->op_begin(), N->getNumOperands());
2060 return CombineTo(N, Res, Res);
2063 // If the low half is not needed, just compute the high half.
2064 bool LoExists = N->hasAnyUseOfValue(0);
2066 (!LegalOperations ||
2067 TLI.isOperationLegal(HiOp, N->getValueType(1)))) {
2068 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2069 N->op_begin(), N->getNumOperands());
2070 return CombineTo(N, Res, Res);
2073 // If both halves are used, return as it is.
2074 if (LoExists && HiExists)
2077 // If the two computed results can be simplified separately, separate them.
2079 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0),
2080 N->op_begin(), N->getNumOperands());
2081 AddToWorkList(Lo.getNode());
2082 SDValue LoOpt = combine(Lo.getNode());
2083 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() &&
2084 (!LegalOperations ||
2085 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())))
2086 return CombineTo(N, LoOpt, LoOpt);
2090 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1),
2091 N->op_begin(), N->getNumOperands());
2092 AddToWorkList(Hi.getNode());
2093 SDValue HiOpt = combine(Hi.getNode());
2094 if (HiOpt.getNode() && HiOpt != Hi &&
2095 (!LegalOperations ||
2096 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())))
2097 return CombineTo(N, HiOpt, HiOpt);
2103 SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
2104 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS);
2105 if (Res.getNode()) return Res;
2107 EVT VT = N->getValueType(0);
2108 DebugLoc DL = N->getDebugLoc();
2110 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2112 if (VT.isSimple() && !VT.isVector()) {
2113 MVT Simple = VT.getSimpleVT();
2114 unsigned SimpleSize = Simple.getSizeInBits();
2115 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2116 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2117 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0));
2118 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1));
2119 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2120 // Compute the high part as N1.
2121 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2122 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2123 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2124 // Compute the low part as N0.
2125 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2126 return CombineTo(N, Lo, Hi);
2133 SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
2134 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU);
2135 if (Res.getNode()) return Res;
2137 EVT VT = N->getValueType(0);
2138 DebugLoc DL = N->getDebugLoc();
2140 // If the type twice as wide is legal, transform the mulhu to a wider multiply
2142 if (VT.isSimple() && !VT.isVector()) {
2143 MVT Simple = VT.getSimpleVT();
2144 unsigned SimpleSize = Simple.getSizeInBits();
2145 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2);
2146 if (TLI.isOperationLegal(ISD::MUL, NewVT)) {
2147 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0));
2148 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1));
2149 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi);
2150 // Compute the high part as N1.
2151 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo,
2152 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType())));
2153 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi);
2154 // Compute the low part as N0.
2155 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo);
2156 return CombineTo(N, Lo, Hi);
2163 SDValue DAGCombiner::visitSMULO(SDNode *N) {
2164 // (smulo x, 2) -> (saddo x, x)
2165 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2166 if (C2->getAPIntValue() == 2)
2167 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(),
2168 N->getOperand(0), N->getOperand(0));
2173 SDValue DAGCombiner::visitUMULO(SDNode *N) {
2174 // (umulo x, 2) -> (uaddo x, x)
2175 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2176 if (C2->getAPIntValue() == 2)
2177 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(),
2178 N->getOperand(0), N->getOperand(0));
2183 SDValue DAGCombiner::visitSDIVREM(SDNode *N) {
2184 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM);
2185 if (Res.getNode()) return Res;
2190 SDValue DAGCombiner::visitUDIVREM(SDNode *N) {
2191 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM);
2192 if (Res.getNode()) return Res;
2197 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
2198 /// two operands of the same opcode, try to simplify it.
2199 SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
2200 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2201 EVT VT = N0.getValueType();
2202 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
2204 // Bail early if none of these transforms apply.
2205 if (N0.getNode()->getNumOperands() == 0) return SDValue();
2207 // For each of OP in AND/OR/XOR:
2208 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
2209 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
2210 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
2211 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free)
2213 // do not sink logical op inside of a vector extend, since it may combine
2215 EVT Op0VT = N0.getOperand(0).getValueType();
2216 if ((N0.getOpcode() == ISD::ZERO_EXTEND ||
2217 N0.getOpcode() == ISD::SIGN_EXTEND ||
2218 // Avoid infinite looping with PromoteIntBinOp.
2219 (N0.getOpcode() == ISD::ANY_EXTEND &&
2220 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) ||
2221 (N0.getOpcode() == ISD::TRUNCATE &&
2222 (!TLI.isZExtFree(VT, Op0VT) ||
2223 !TLI.isTruncateFree(Op0VT, VT)) &&
2224 TLI.isTypeLegal(Op0VT))) &&
2226 Op0VT == N1.getOperand(0).getValueType() &&
2227 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) {
2228 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2229 N0.getOperand(0).getValueType(),
2230 N0.getOperand(0), N1.getOperand(0));
2231 AddToWorkList(ORNode.getNode());
2232 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode);
2235 // For each of OP in SHL/SRL/SRA/AND...
2236 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
2237 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
2238 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
2239 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
2240 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
2241 N0.getOperand(1) == N1.getOperand(1)) {
2242 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(),
2243 N0.getOperand(0).getValueType(),
2244 N0.getOperand(0), N1.getOperand(0));
2245 AddToWorkList(ORNode.getNode());
2246 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
2247 ORNode, N0.getOperand(1));
2253 SDValue DAGCombiner::visitAND(SDNode *N) {
2254 SDValue N0 = N->getOperand(0);
2255 SDValue N1 = N->getOperand(1);
2256 SDValue LL, LR, RL, RR, CC0, CC1;
2257 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2258 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2259 EVT VT = N1.getValueType();
2260 unsigned BitWidth = VT.getScalarType().getSizeInBits();
2263 if (VT.isVector()) {
2264 SDValue FoldedVOp = SimplifyVBinOp(N);
2265 if (FoldedVOp.getNode()) return FoldedVOp;
2268 // fold (and x, undef) -> 0
2269 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
2270 return DAG.getConstant(0, VT);
2271 // fold (and c1, c2) -> c1&c2
2273 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C);
2274 // canonicalize constant to RHS
2276 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0);
2277 // fold (and x, -1) -> x
2278 if (N1C && N1C->isAllOnesValue())
2280 // if (and x, c) is known to be zero, return 0
2281 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
2282 APInt::getAllOnesValue(BitWidth)))
2283 return DAG.getConstant(0, VT);
2285 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1);
2286 if (RAND.getNode() != 0)
2288 // fold (and (or x, C), D) -> D if (C & D) == D
2289 if (N1C && N0.getOpcode() == ISD::OR)
2290 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2291 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
2293 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
2294 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
2295 SDValue N0Op0 = N0.getOperand(0);
2296 APInt Mask = ~N1C->getAPIntValue();
2297 Mask = Mask.trunc(N0Op0.getValueSizeInBits());
2298 if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
2299 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(),
2300 N0.getValueType(), N0Op0);
2302 // Replace uses of the AND with uses of the Zero extend node.
2305 // We actually want to replace all uses of the any_extend with the
2306 // zero_extend, to avoid duplicating things. This will later cause this
2307 // AND to be folded.
2308 CombineTo(N0.getNode(), Zext);
2309 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2312 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
2313 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2314 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2315 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2317 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2318 LL.getValueType().isInteger()) {
2319 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
2320 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
2321 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2322 LR.getValueType(), LL, RL);
2323 AddToWorkList(ORNode.getNode());
2324 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2326 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1)
2327 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
2328 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(),
2329 LR.getValueType(), LL, RL);
2330 AddToWorkList(ANDNode.getNode());
2331 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2333 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1)
2334 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
2335 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(),
2336 LR.getValueType(), LL, RL);
2337 AddToWorkList(ORNode.getNode());
2338 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2341 // canonicalize equivalent to ll == rl
2342 if (LL == RR && LR == RL) {
2343 Op1 = ISD::getSetCCSwappedOperands(Op1);
2346 if (LL == RL && LR == RR) {
2347 bool isInteger = LL.getValueType().isInteger();
2348 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
2349 if (Result != ISD::SETCC_INVALID &&
2350 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2351 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2356 // Simplify: (and (op x...), (op y...)) -> (op (and x, y))
2357 if (N0.getOpcode() == N1.getOpcode()) {
2358 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2359 if (Tmp.getNode()) return Tmp;
2362 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
2363 // fold (and (sra)) -> (and (srl)) when possible.
2364 if (!VT.isVector() &&
2365 SimplifyDemandedBits(SDValue(N, 0)))
2366 return SDValue(N, 0);
2368 // fold (zext_inreg (extload x)) -> (zextload x)
2369 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
2370 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2371 EVT MemVT = LN0->getMemoryVT();
2372 // If we zero all the possible extended bits, then we can turn this into
2373 // a zextload if we are running before legalize or the operation is legal.
2374 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2375 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2376 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2377 ((!LegalOperations && !LN0->isVolatile()) ||
2378 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2379 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2380 LN0->getChain(), LN0->getBasePtr(),
2381 LN0->getPointerInfo(), MemVT,
2382 LN0->isVolatile(), LN0->isNonTemporal(),
2383 LN0->getAlignment());
2385 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2386 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2389 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
2390 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
2392 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2393 EVT MemVT = LN0->getMemoryVT();
2394 // If we zero all the possible extended bits, then we can turn this into
2395 // a zextload if we are running before legalize or the operation is legal.
2396 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits();
2397 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
2398 BitWidth - MemVT.getScalarType().getSizeInBits())) &&
2399 ((!LegalOperations && !LN0->isVolatile()) ||
2400 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) {
2401 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT,
2403 LN0->getBasePtr(), LN0->getPointerInfo(),
2405 LN0->isVolatile(), LN0->isNonTemporal(),
2406 LN0->getAlignment());
2408 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
2409 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2413 // fold (and (load x), 255) -> (zextload x, i8)
2414 // fold (and (extload x, i16), 255) -> (zextload x, i8)
2415 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
2416 if (N1C && (N0.getOpcode() == ISD::LOAD ||
2417 (N0.getOpcode() == ISD::ANY_EXTEND &&
2418 N0.getOperand(0).getOpcode() == ISD::LOAD))) {
2419 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;
2420 LoadSDNode *LN0 = HasAnyExt
2421 ? cast<LoadSDNode>(N0.getOperand(0))
2422 : cast<LoadSDNode>(N0);
2423 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
2424 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) {
2425 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
2426 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){
2427 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2428 EVT LoadedVT = LN0->getMemoryVT();
2430 if (ExtVT == LoadedVT &&
2431 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2432 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2435 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2436 LN0->getChain(), LN0->getBasePtr(),
2437 LN0->getPointerInfo(),
2438 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2439 LN0->getAlignment());
2441 CombineTo(LN0, NewLoad, NewLoad.getValue(1));
2442 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2445 // Do not change the width of a volatile load.
2446 // Do not generate loads of non-round integer types since these can
2447 // be expensive (and would be wrong if the type is not byte sized).
2448 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2449 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2450 EVT PtrType = LN0->getOperand(1).getValueType();
2452 unsigned Alignment = LN0->getAlignment();
2453 SDValue NewPtr = LN0->getBasePtr();
2455 // For big endian targets, we need to add an offset to the pointer
2456 // to load the correct bytes. For little endian systems, we merely
2457 // need to read fewer bytes from the same pointer.
2458 if (TLI.isBigEndian()) {
2459 unsigned LVTStoreBytes = LoadedVT.getStoreSize();
2460 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2461 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
2462 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType,
2463 NewPtr, DAG.getConstant(PtrOff, PtrType));
2464 Alignment = MinAlign(Alignment, PtrOff);
2467 AddToWorkList(NewPtr.getNode());
2469 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT;
2471 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy,
2472 LN0->getChain(), NewPtr,
2473 LN0->getPointerInfo(),
2474 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2477 CombineTo(LN0, Load, Load.getValue(1));
2478 return SDValue(N, 0); // Return N so it doesn't get rechecked!
2487 /// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
2489 SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
2490 bool DemandHighBits) {
2491 if (!LegalOperations)
2494 EVT VT = N->getValueType(0);
2495 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
2497 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2500 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
2501 bool LookPassAnd0 = false;
2502 bool LookPassAnd1 = false;
2503 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
2505 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
2507 if (N0.getOpcode() == ISD::AND) {
2508 if (!N0.getNode()->hasOneUse())
2510 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2511 if (!N01C || N01C->getZExtValue() != 0xFF00)
2513 N0 = N0.getOperand(0);
2514 LookPassAnd0 = true;
2517 if (N1.getOpcode() == ISD::AND) {
2518 if (!N1.getNode()->hasOneUse())
2520 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2521 if (!N11C || N11C->getZExtValue() != 0xFF)
2523 N1 = N1.getOperand(0);
2524 LookPassAnd1 = true;
2527 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
2529 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
2531 if (!N0.getNode()->hasOneUse() ||
2532 !N1.getNode()->hasOneUse())
2535 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2536 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
2539 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
2542 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
2543 SDValue N00 = N0->getOperand(0);
2544 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
2545 if (!N00.getNode()->hasOneUse())
2547 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
2548 if (!N001C || N001C->getZExtValue() != 0xFF)
2550 N00 = N00.getOperand(0);
2551 LookPassAnd0 = true;
2554 SDValue N10 = N1->getOperand(0);
2555 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
2556 if (!N10.getNode()->hasOneUse())
2558 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
2559 if (!N101C || N101C->getZExtValue() != 0xFF00)
2561 N10 = N10.getOperand(0);
2562 LookPassAnd1 = true;
2568 // Make sure everything beyond the low halfword is zero since the SRL 16
2569 // will clear the top bits.
2570 unsigned OpSizeInBits = VT.getSizeInBits();
2571 if (DemandHighBits && OpSizeInBits > 16 &&
2572 (!LookPassAnd0 || !LookPassAnd1) &&
2573 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
2576 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
2577 if (OpSizeInBits > 16)
2578 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
2579 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
2583 /// isBSwapHWordElement - Return true if the specified node is an element
2584 /// that makes up a 32-bit packed halfword byteswap. i.e.
2585 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2586 static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
2587 if (!N.getNode()->hasOneUse())
2590 unsigned Opc = N.getOpcode();
2591 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
2594 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2599 switch (N1C->getZExtValue()) {
2602 case 0xFF: Num = 0; break;
2603 case 0xFF00: Num = 1; break;
2604 case 0xFF0000: Num = 2; break;
2605 case 0xFF000000: Num = 3; break;
2608 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
2609 SDValue N0 = N.getOperand(0);
2610 if (Opc == ISD::AND) {
2611 if (Num == 0 || Num == 2) {
2613 // (x >> 8) & 0xff0000
2614 if (N0.getOpcode() != ISD::SRL)
2616 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2617 if (!C || C->getZExtValue() != 8)
2620 // (x << 8) & 0xff00
2621 // (x << 8) & 0xff000000
2622 if (N0.getOpcode() != ISD::SHL)
2624 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2625 if (!C || C->getZExtValue() != 8)
2628 } else if (Opc == ISD::SHL) {
2630 // (x & 0xff0000) << 8
2631 if (Num != 0 && Num != 2)
2633 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2634 if (!C || C->getZExtValue() != 8)
2636 } else { // Opc == ISD::SRL
2637 // (x & 0xff00) >> 8
2638 // (x & 0xff000000) >> 8
2639 if (Num != 1 && Num != 3)
2641 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
2642 if (!C || C->getZExtValue() != 8)
2649 Parts[Num] = N0.getOperand(0).getNode();
2653 /// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
2654 /// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
2655 /// => (rotl (bswap x), 16)
2656 SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
2657 if (!LegalOperations)
2660 EVT VT = N->getValueType(0);
2663 if (!TLI.isOperationLegal(ISD::BSWAP, VT))
2666 SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
2668 // (or (or (and), (and)), (or (and), (and)))
2669 // (or (or (or (and), (and)), (and)), (and))
2670 if (N0.getOpcode() != ISD::OR)
2672 SDValue N00 = N0.getOperand(0);
2673 SDValue N01 = N0.getOperand(1);
2675 if (N1.getOpcode() == ISD::OR) {
2676 // (or (or (and), (and)), (or (and), (and)))
2677 SDValue N000 = N00.getOperand(0);
2678 if (!isBSwapHWordElement(N000, Parts))
2681 SDValue N001 = N00.getOperand(1);
2682 if (!isBSwapHWordElement(N001, Parts))
2684 SDValue N010 = N01.getOperand(0);
2685 if (!isBSwapHWordElement(N010, Parts))
2687 SDValue N011 = N01.getOperand(1);
2688 if (!isBSwapHWordElement(N011, Parts))
2691 // (or (or (or (and), (and)), (and)), (and))
2692 if (!isBSwapHWordElement(N1, Parts))
2694 if (!isBSwapHWordElement(N01, Parts))
2696 if (N00.getOpcode() != ISD::OR)
2698 SDValue N000 = N00.getOperand(0);
2699 if (!isBSwapHWordElement(N000, Parts))
2701 SDValue N001 = N00.getOperand(1);
2702 if (!isBSwapHWordElement(N001, Parts))
2706 // Make sure the parts are all coming from the same node.
2707 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
2710 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
2711 SDValue(Parts[0],0));
2713 // Result of the bswap should be rotated by 16. If it's not legal, than
2714 // do (x << 16) | (x >> 16).
2715 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
2716 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
2717 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
2718 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
2719 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
2720 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
2721 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
2722 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
2725 SDValue DAGCombiner::visitOR(SDNode *N) {
2726 SDValue N0 = N->getOperand(0);
2727 SDValue N1 = N->getOperand(1);
2728 SDValue LL, LR, RL, RR, CC0, CC1;
2729 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2730 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2731 EVT VT = N1.getValueType();
2734 if (VT.isVector()) {
2735 SDValue FoldedVOp = SimplifyVBinOp(N);
2736 if (FoldedVOp.getNode()) return FoldedVOp;
2739 // fold (or x, undef) -> -1
2740 if (!LegalOperations &&
2741 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) {
2742 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
2743 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
2745 // fold (or c1, c2) -> c1|c2
2747 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C);
2748 // canonicalize constant to RHS
2750 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0);
2751 // fold (or x, 0) -> x
2752 if (N1C && N1C->isNullValue())
2754 // fold (or x, -1) -> -1
2755 if (N1C && N1C->isAllOnesValue())
2757 // fold (or x, c) -> c iff (x & ~c) == 0
2758 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
2761 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
2762 SDValue BSwap = MatchBSwapHWord(N, N0, N1);
2763 if (BSwap.getNode() != 0)
2765 BSwap = MatchBSwapHWordLow(N, N0, N1);
2766 if (BSwap.getNode() != 0)
2770 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
2771 if (ROR.getNode() != 0)
2773 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
2774 // iff (c1 & c2) == 0.
2775 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
2776 isa<ConstantSDNode>(N0.getOperand(1))) {
2777 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
2778 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0)
2779 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
2780 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2781 N0.getOperand(0), N1),
2782 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1));
2784 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
2785 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
2786 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
2787 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
2789 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
2790 LL.getValueType().isInteger()) {
2791 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0)
2792 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0)
2793 if (cast<ConstantSDNode>(LR)->isNullValue() &&
2794 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
2795 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(),
2796 LR.getValueType(), LL, RL);
2797 AddToWorkList(ORNode.getNode());
2798 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1);
2800 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1)
2801 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1)
2802 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
2803 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
2804 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(),
2805 LR.getValueType(), LL, RL);
2806 AddToWorkList(ANDNode.getNode());
2807 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1);
2810 // canonicalize equivalent to ll == rl
2811 if (LL == RR && LR == RL) {
2812 Op1 = ISD::getSetCCSwappedOperands(Op1);
2815 if (LL == RL && LR == RR) {
2816 bool isInteger = LL.getValueType().isInteger();
2817 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
2818 if (Result != ISD::SETCC_INVALID &&
2819 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType())))
2820 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(),
2825 // Simplify: (or (op x...), (op y...)) -> (op (or x, y))
2826 if (N0.getOpcode() == N1.getOpcode()) {
2827 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
2828 if (Tmp.getNode()) return Tmp;
2831 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible.
2832 if (N0.getOpcode() == ISD::AND &&
2833 N1.getOpcode() == ISD::AND &&
2834 N0.getOperand(1).getOpcode() == ISD::Constant &&
2835 N1.getOperand(1).getOpcode() == ISD::Constant &&
2836 // Don't increase # computations.
2837 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
2838 // We can only do this xform if we know that bits from X that are set in C2
2839 // but not in C1 are already zero. Likewise for Y.
2840 const APInt &LHSMask =
2841 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
2842 const APInt &RHSMask =
2843 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue();
2845 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
2846 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
2847 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT,
2848 N0.getOperand(0), N1.getOperand(0));
2849 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X,
2850 DAG.getConstant(LHSMask | RHSMask, VT));
2854 // See if this is some rotate idiom.
2855 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc()))
2856 return SDValue(Rot, 0);
2858 // Simplify the operands using demanded-bits information.
2859 if (!VT.isVector() &&
2860 SimplifyDemandedBits(SDValue(N, 0)))
2861 return SDValue(N, 0);
2866 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
2867 static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) {
2868 if (Op.getOpcode() == ISD::AND) {
2869 if (isa<ConstantSDNode>(Op.getOperand(1))) {
2870 Mask = Op.getOperand(1);
2871 Op = Op.getOperand(0);
2877 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
2885 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
2886 // idioms for rotate, and if the target supports rotation instructions, generate
2888 SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
2889 // Must be a legal type. Expanded 'n promoted things won't work with rotates.
2890 EVT VT = LHS.getValueType();
2891 if (!TLI.isTypeLegal(VT)) return 0;
2893 // The target must have at least one rotate flavor.
2894 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
2895 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
2896 if (!HasROTL && !HasROTR) return 0;
2898 // Match "(X shl/srl V1) & V2" where V2 may not be present.
2899 SDValue LHSShift; // The shift.
2900 SDValue LHSMask; // AND value if any.
2901 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
2902 return 0; // Not part of a rotate.
2904 SDValue RHSShift; // The shift.
2905 SDValue RHSMask; // AND value if any.
2906 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
2907 return 0; // Not part of a rotate.
2909 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
2910 return 0; // Not shifting the same value.
2912 if (LHSShift.getOpcode() == RHSShift.getOpcode())
2913 return 0; // Shifts must disagree.
2915 // Canonicalize shl to left side in a shl/srl pair.
2916 if (RHSShift.getOpcode() == ISD::SHL) {
2917 std::swap(LHS, RHS);
2918 std::swap(LHSShift, RHSShift);
2919 std::swap(LHSMask , RHSMask );
2922 unsigned OpSizeInBits = VT.getSizeInBits();
2923 SDValue LHSShiftArg = LHSShift.getOperand(0);
2924 SDValue LHSShiftAmt = LHSShift.getOperand(1);
2925 SDValue RHSShiftAmt = RHSShift.getOperand(1);
2927 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
2928 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
2929 if (LHSShiftAmt.getOpcode() == ISD::Constant &&
2930 RHSShiftAmt.getOpcode() == ISD::Constant) {
2931 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue();
2932 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue();
2933 if ((LShVal + RShVal) != OpSizeInBits)
2938 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt);
2940 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt);
2942 // If there is an AND of either shifted operand, apply it to the result.
2943 if (LHSMask.getNode() || RHSMask.getNode()) {
2944 APInt Mask = APInt::getAllOnesValue(OpSizeInBits);
2946 if (LHSMask.getNode()) {
2947 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal);
2948 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits;
2950 if (RHSMask.getNode()) {
2951 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal);
2952 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits;
2955 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT));
2958 return Rot.getNode();
2961 // If there is a mask here, and we have a variable shift, we can't be sure
2962 // that we're masking out the right stuff.
2963 if (LHSMask.getNode() || RHSMask.getNode())
2966 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
2967 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
2968 if (RHSShiftAmt.getOpcode() == ISD::SUB &&
2969 LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
2970 if (ConstantSDNode *SUBC =
2971 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) {
2972 if (SUBC->getAPIntValue() == OpSizeInBits) {
2974 return DAG.getNode(ISD::ROTL, DL, VT,
2975 LHSShiftArg, LHSShiftAmt).getNode();
2977 return DAG.getNode(ISD::ROTR, DL, VT,
2978 LHSShiftArg, RHSShiftAmt).getNode();
2983 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
2984 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
2985 if (LHSShiftAmt.getOpcode() == ISD::SUB &&
2986 RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
2987 if (ConstantSDNode *SUBC =
2988 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) {
2989 if (SUBC->getAPIntValue() == OpSizeInBits) {
2991 return DAG.getNode(ISD::ROTR, DL, VT,
2992 LHSShiftArg, RHSShiftAmt).getNode();
2994 return DAG.getNode(ISD::ROTL, DL, VT,
2995 LHSShiftArg, LHSShiftAmt).getNode();
3000 // Look for sign/zext/any-extended or truncate cases:
3001 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3002 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3003 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3004 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) &&
3005 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
3006 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
3007 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND
3008 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) {
3009 SDValue LExtOp0 = LHSShiftAmt.getOperand(0);
3010 SDValue RExtOp0 = RHSShiftAmt.getOperand(0);
3011 if (RExtOp0.getOpcode() == ISD::SUB &&
3012 RExtOp0.getOperand(1) == LExtOp0) {
3013 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3015 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) ->
3016 // (rotr x, (sub 32, y))
3017 if (ConstantSDNode *SUBC =
3018 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) {
3019 if (SUBC->getAPIntValue() == OpSizeInBits) {
3020 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT,
3022 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode();
3025 } else if (LExtOp0.getOpcode() == ISD::SUB &&
3026 RExtOp0 == LExtOp0.getOperand(1)) {
3027 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3029 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) ->
3030 // (rotl x, (sub 32, y))
3031 if (ConstantSDNode *SUBC =
3032 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) {
3033 if (SUBC->getAPIntValue() == OpSizeInBits) {
3034 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT,
3036 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode();
3045 SDValue DAGCombiner::visitXOR(SDNode *N) {
3046 SDValue N0 = N->getOperand(0);
3047 SDValue N1 = N->getOperand(1);
3048 SDValue LHS, RHS, CC;
3049 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3050 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3051 EVT VT = N0.getValueType();
3054 if (VT.isVector()) {
3055 SDValue FoldedVOp = SimplifyVBinOp(N);
3056 if (FoldedVOp.getNode()) return FoldedVOp;
3059 // fold (xor undef, undef) -> 0. This is a common idiom (misuse).
3060 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF)
3061 return DAG.getConstant(0, VT);
3062 // fold (xor x, undef) -> undef
3063 if (N0.getOpcode() == ISD::UNDEF)
3065 if (N1.getOpcode() == ISD::UNDEF)
3067 // fold (xor c1, c2) -> c1^c2
3069 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C);
3070 // canonicalize constant to RHS
3072 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0);
3073 // fold (xor x, 0) -> x
3074 if (N1C && N1C->isNullValue())
3077 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1);
3078 if (RXOR.getNode() != 0)
3081 // fold !(x cc y) -> (x !cc y)
3082 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
3083 bool isInt = LHS.getValueType().isInteger();
3084 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
3087 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) {
3088 switch (N0.getOpcode()) {
3090 llvm_unreachable("Unhandled SetCC Equivalent!");
3092 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC);
3093 case ISD::SELECT_CC:
3094 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2),
3095 N0.getOperand(3), NotCC);
3100 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y)))
3101 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND &&
3102 N0.getNode()->hasOneUse() &&
3103 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){
3104 SDValue V = N0.getOperand(0);
3105 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V,
3106 DAG.getConstant(1, V.getValueType()));
3107 AddToWorkList(V.getNode());
3108 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V);
3111 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
3112 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
3113 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3114 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3115 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
3116 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3117 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3118 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3119 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3120 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3123 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants
3124 if (N1C && N1C->isAllOnesValue() &&
3125 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
3126 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
3127 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
3128 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
3129 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS
3130 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS
3131 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode());
3132 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
3135 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
3136 if (N1C && N0.getOpcode() == ISD::XOR) {
3137 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
3138 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3140 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1),
3141 DAG.getConstant(N1C->getAPIntValue() ^
3142 N00C->getAPIntValue(), VT));
3144 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0),
3145 DAG.getConstant(N1C->getAPIntValue() ^
3146 N01C->getAPIntValue(), VT));
3148 // fold (xor x, x) -> 0
3150 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations);
3152 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
3153 if (N0.getOpcode() == N1.getOpcode()) {
3154 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N);
3155 if (Tmp.getNode()) return Tmp;
3158 // Simplify the expression using non-local knowledge.
3159 if (!VT.isVector() &&
3160 SimplifyDemandedBits(SDValue(N, 0)))
3161 return SDValue(N, 0);
3166 /// visitShiftByConstant - Handle transforms common to the three shifts, when
3167 /// the shift amount is a constant.
3168 SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
3169 SDNode *LHS = N->getOperand(0).getNode();
3170 if (!LHS->hasOneUse()) return SDValue();
3172 // We want to pull some binops through shifts, so that we have (and (shift))
3173 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of
3174 // thing happens with address calculations, so it's important to canonicalize
3176 bool HighBitSet = false; // Can we transform this if the high bit is set?
3178 switch (LHS->getOpcode()) {
3179 default: return SDValue();
3182 HighBitSet = false; // We can only transform sra if the high bit is clear.
3185 HighBitSet = true; // We can only transform sra if the high bit is set.
3188 if (N->getOpcode() != ISD::SHL)
3189 return SDValue(); // only shl(add) not sr[al](add).
3190 HighBitSet = false; // We can only transform sra if the high bit is clear.
3194 // We require the RHS of the binop to be a constant as well.
3195 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
3196 if (!BinOpCst) return SDValue();
3198 // FIXME: disable this unless the input to the binop is a shift by a constant.
3199 // If it is not a shift, it pessimizes some common cases like:
3201 // void foo(int *X, int i) { X[i & 1235] = 1; }
3202 // int bar(int *X, int i) { return X[i & 255]; }
3203 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode();
3204 if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
3205 BinOpLHSVal->getOpcode() != ISD::SRA &&
3206 BinOpLHSVal->getOpcode() != ISD::SRL) ||
3207 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
3210 EVT VT = N->getValueType(0);
3212 // If this is a signed shift right, and the high bit is modified by the
3213 // logical operation, do not perform the transformation. The highBitSet
3214 // boolean indicates the value of the high bit of the constant which would
3215 // cause it to be modified for this operation.
3216 if (N->getOpcode() == ISD::SRA) {
3217 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative();
3218 if (BinOpRHSSignSet != HighBitSet)
3222 // Fold the constants, shifting the binop RHS by the shift amount.
3223 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(),
3225 LHS->getOperand(1), N->getOperand(1));
3227 // Create the new shift.
3228 SDValue NewShift = DAG.getNode(N->getOpcode(),
3229 LHS->getOperand(0).getDebugLoc(),
3230 VT, LHS->getOperand(0), N->getOperand(1));
3232 // Create the new binop.
3233 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS);
3236 SDValue DAGCombiner::visitSHL(SDNode *N) {
3237 SDValue N0 = N->getOperand(0);
3238 SDValue N1 = N->getOperand(1);
3239 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3240 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3241 EVT VT = N0.getValueType();
3242 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3244 // fold (shl c1, c2) -> c1<<c2
3246 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C);
3247 // fold (shl 0, x) -> 0
3248 if (N0C && N0C->isNullValue())
3250 // fold (shl x, c >= size(x)) -> undef
3251 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3252 return DAG.getUNDEF(VT);
3253 // fold (shl x, 0) -> x
3254 if (N1C && N1C->isNullValue())
3256 // fold (shl undef, x) -> 0
3257 if (N0.getOpcode() == ISD::UNDEF)
3258 return DAG.getConstant(0, VT);
3259 // if (shl x, c) is known to be zero, return 0
3260 if (DAG.MaskedValueIsZero(SDValue(N, 0),
3261 APInt::getAllOnesValue(OpSizeInBits)))
3262 return DAG.getConstant(0, VT);
3263 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))).
3264 if (N1.getOpcode() == ISD::TRUNCATE &&
3265 N1.getOperand(0).getOpcode() == ISD::AND &&
3266 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3267 SDValue N101 = N1.getOperand(0).getOperand(1);
3268 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3269 EVT TruncVT = N1.getValueType();
3270 SDValue N100 = N1.getOperand(0).getOperand(0);
3271 APInt TruncC = N101C->getAPIntValue();
3272 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3273 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0,
3274 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT,
3275 DAG.getNode(ISD::TRUNCATE,
3278 DAG.getConstant(TruncC, TruncVT)));
3282 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3283 return SDValue(N, 0);
3285 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
3286 if (N1C && N0.getOpcode() == ISD::SHL &&
3287 N0.getOperand(1).getOpcode() == ISD::Constant) {
3288 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3289 uint64_t c2 = N1C->getZExtValue();
3290 if (c1 + c2 >= OpSizeInBits)
3291 return DAG.getConstant(0, VT);
3292 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3293 DAG.getConstant(c1 + c2, N1.getValueType()));
3296 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2)))
3297 // For this to be valid, the second form must not preserve any of the bits
3298 // that are shifted out by the inner shift in the first form. This means
3299 // the outer shift size must be >= the number of bits added by the ext.
3300 // As a corollary, we don't care what kind of ext it is.
3301 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND ||
3302 N0.getOpcode() == ISD::ANY_EXTEND ||
3303 N0.getOpcode() == ISD::SIGN_EXTEND) &&
3304 N0.getOperand(0).getOpcode() == ISD::SHL &&
3305 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3307 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3308 uint64_t c2 = N1C->getZExtValue();
3309 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3310 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3311 if (c2 >= OpSizeInBits - InnerShiftSize) {
3312 if (c1 + c2 >= OpSizeInBits)
3313 return DAG.getConstant(0, VT);
3314 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT,
3315 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT,
3316 N0.getOperand(0)->getOperand(0)),
3317 DAG.getConstant(c1 + c2, N1.getValueType()));
3321 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or
3322 // (and (srl x, (sub c1, c2), MASK)
3323 if (N1C && N0.getOpcode() == ISD::SRL &&
3324 N0.getOperand(1).getOpcode() == ISD::Constant) {
3325 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3326 if (c1 < VT.getSizeInBits()) {
3327 uint64_t c2 = N1C->getZExtValue();
3328 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
3329 VT.getSizeInBits() - c1);
3332 Mask = Mask.shl(c2-c1);
3333 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0),
3334 DAG.getConstant(c2-c1, N1.getValueType()));
3336 Mask = Mask.lshr(c1-c2);
3337 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3338 DAG.getConstant(c1-c2, N1.getValueType()));
3340 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift,
3341 DAG.getConstant(Mask, VT));
3344 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1))
3345 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) {
3346 SDValue HiBitsMask =
3347 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(),
3348 VT.getSizeInBits() -
3349 N1C->getZExtValue()),
3351 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3356 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue());
3357 if (NewSHL.getNode())
3364 SDValue DAGCombiner::visitSRA(SDNode *N) {
3365 SDValue N0 = N->getOperand(0);
3366 SDValue N1 = N->getOperand(1);
3367 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3368 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3369 EVT VT = N0.getValueType();
3370 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3372 // fold (sra c1, c2) -> (sra c1, c2)
3374 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C);
3375 // fold (sra 0, x) -> 0
3376 if (N0C && N0C->isNullValue())
3378 // fold (sra -1, x) -> -1
3379 if (N0C && N0C->isAllOnesValue())
3381 // fold (sra x, (setge c, size(x))) -> undef
3382 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3383 return DAG.getUNDEF(VT);
3384 // fold (sra x, 0) -> x
3385 if (N1C && N1C->isNullValue())
3387 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
3389 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
3390 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
3391 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3393 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3394 ExtVT, VT.getVectorNumElements());
3395 if ((!LegalOperations ||
3396 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3397 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
3398 N0.getOperand(0), DAG.getValueType(ExtVT));
3401 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
3402 if (N1C && N0.getOpcode() == ISD::SRA) {
3403 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
3404 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue();
3405 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1;
3406 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0),
3407 DAG.getConstant(Sum, N1C->getValueType(0)));
3411 // fold (sra (shl X, m), (sub result_size, n))
3412 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for
3413 // result_size - n != m.
3414 // If truncate is free for the target sext(shl) is likely to result in better
3416 if (N0.getOpcode() == ISD::SHL) {
3417 // Get the two constanst of the shifts, CN0 = m, CN = n.
3418 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3420 // Determine what the truncate's result bitsize and type would be.
3422 EVT::getIntegerVT(*DAG.getContext(),
3423 OpSizeInBits - N1C->getZExtValue());
3424 // Determine the residual right-shift amount.
3425 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
3427 // If the shift is not a no-op (in which case this should be just a sign
3428 // extend already), the truncated to type is legal, sign_extend is legal
3429 // on that type, and the truncate to that type is both legal and free,
3430 // perform the transform.
3431 if ((ShiftAmt > 0) &&
3432 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) &&
3433 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) &&
3434 TLI.isTruncateFree(VT, TruncVT)) {
3436 SDValue Amt = DAG.getConstant(ShiftAmt,
3437 getShiftAmountTy(N0.getOperand(0).getValueType()));
3438 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT,
3439 N0.getOperand(0), Amt);
3440 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT,
3442 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(),
3443 N->getValueType(0), Trunc);
3448 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
3449 if (N1.getOpcode() == ISD::TRUNCATE &&
3450 N1.getOperand(0).getOpcode() == ISD::AND &&
3451 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3452 SDValue N101 = N1.getOperand(0).getOperand(1);
3453 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3454 EVT TruncVT = N1.getValueType();
3455 SDValue N100 = N1.getOperand(0).getOperand(0);
3456 APInt TruncC = N101C->getAPIntValue();
3457 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits());
3458 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0,
3459 DAG.getNode(ISD::AND, N->getDebugLoc(),
3461 DAG.getNode(ISD::TRUNCATE,
3464 DAG.getConstant(TruncC, TruncVT)));
3468 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2))
3469 // if c1 is equal to the number of bits the trunc removes
3470 if (N0.getOpcode() == ISD::TRUNCATE &&
3471 (N0.getOperand(0).getOpcode() == ISD::SRL ||
3472 N0.getOperand(0).getOpcode() == ISD::SRA) &&
3473 N0.getOperand(0).hasOneUse() &&
3474 N0.getOperand(0).getOperand(1).hasOneUse() &&
3475 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) {
3476 EVT LargeVT = N0.getOperand(0).getValueType();
3477 ConstantSDNode *LargeShiftAmt =
3478 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1));
3480 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits ==
3481 LargeShiftAmt->getZExtValue()) {
3483 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(),
3484 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType()));
3485 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT,
3486 N0.getOperand(0).getOperand(0), Amt);
3487 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA);
3491 // Simplify, based on bits shifted out of the LHS.
3492 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3493 return SDValue(N, 0);
3496 // If the sign bit is known to be zero, switch this to a SRL.
3497 if (DAG.SignBitIsZero(N0))
3498 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1);
3501 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue());
3502 if (NewSRA.getNode())
3509 SDValue DAGCombiner::visitSRL(SDNode *N) {
3510 SDValue N0 = N->getOperand(0);
3511 SDValue N1 = N->getOperand(1);
3512 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3513 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3514 EVT VT = N0.getValueType();
3515 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits();
3517 // fold (srl c1, c2) -> c1 >>u c2
3519 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C);
3520 // fold (srl 0, x) -> 0
3521 if (N0C && N0C->isNullValue())
3523 // fold (srl x, c >= size(x)) -> undef
3524 if (N1C && N1C->getZExtValue() >= OpSizeInBits)
3525 return DAG.getUNDEF(VT);
3526 // fold (srl x, 0) -> x
3527 if (N1C && N1C->isNullValue())
3529 // if (srl x, c) is known to be zero, return 0
3530 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0),
3531 APInt::getAllOnesValue(OpSizeInBits)))
3532 return DAG.getConstant(0, VT);
3534 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
3535 if (N1C && N0.getOpcode() == ISD::SRL &&
3536 N0.getOperand(1).getOpcode() == ISD::Constant) {
3537 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
3538 uint64_t c2 = N1C->getZExtValue();
3539 if (c1 + c2 >= OpSizeInBits)
3540 return DAG.getConstant(0, VT);
3541 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0),
3542 DAG.getConstant(c1 + c2, N1.getValueType()));
3545 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
3546 if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
3547 N0.getOperand(0).getOpcode() == ISD::SRL &&
3548 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
3550 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
3551 uint64_t c2 = N1C->getZExtValue();
3552 EVT InnerShiftVT = N0.getOperand(0).getValueType();
3553 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
3554 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits();
3555 // This is only valid if the OpSizeInBits + c1 = size of inner shift.
3556 if (c1 + OpSizeInBits == InnerShiftSize) {
3557 if (c1 + c2 >= InnerShiftSize)
3558 return DAG.getConstant(0, VT);
3559 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT,
3560 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT,
3561 N0.getOperand(0)->getOperand(0),
3562 DAG.getConstant(c1 + c2, ShiftCountVT)));
3566 // fold (srl (shl x, c), c) -> (and x, cst2)
3567 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 &&
3568 N0.getValueSizeInBits() <= 64) {
3569 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits();
3570 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0),
3571 DAG.getConstant(~0ULL >> ShAmt, VT));
3575 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
3576 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
3577 // Shifting in all undef bits?
3578 EVT SmallVT = N0.getOperand(0).getValueType();
3579 if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
3580 return DAG.getUNDEF(VT);
3582 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
3583 uint64_t ShiftAmt = N1C->getZExtValue();
3584 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT,
3586 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT)));
3587 AddToWorkList(SmallShift.getNode());
3588 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift);
3592 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
3593 // bit, which is unmodified by sra.
3594 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) {
3595 if (N0.getOpcode() == ISD::SRA)
3596 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1);
3599 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
3600 if (N1C && N0.getOpcode() == ISD::CTLZ &&
3601 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
3602 APInt KnownZero, KnownOne;
3603 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
3604 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
3606 // If any of the input bits are KnownOne, then the input couldn't be all
3607 // zeros, thus the result of the srl will always be zero.
3608 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT);
3610 // If all of the bits input the to ctlz node are known to be zero, then
3611 // the result of the ctlz is "32" and the result of the shift is one.
3612 APInt UnknownBits = ~KnownZero & Mask;
3613 if (UnknownBits == 0) return DAG.getConstant(1, VT);
3615 // Otherwise, check to see if there is exactly one bit input to the ctlz.
3616 if ((UnknownBits & (UnknownBits - 1)) == 0) {
3617 // Okay, we know that only that the single bit specified by UnknownBits
3618 // could be set on input to the CTLZ node. If this bit is set, the SRL
3619 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
3620 // to an SRL/XOR pair, which is likely to simplify more.
3621 unsigned ShAmt = UnknownBits.countTrailingZeros();
3622 SDValue Op = N0.getOperand(0);
3625 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op,
3626 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType())));
3627 AddToWorkList(Op.getNode());
3630 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
3631 Op, DAG.getConstant(1, VT));
3635 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))).
3636 if (N1.getOpcode() == ISD::TRUNCATE &&
3637 N1.getOperand(0).getOpcode() == ISD::AND &&
3638 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
3639 SDValue N101 = N1.getOperand(0).getOperand(1);
3640 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
3641 EVT TruncVT = N1.getValueType();
3642 SDValue N100 = N1.getOperand(0).getOperand(0);
3643 APInt TruncC = N101C->getAPIntValue();
3644 TruncC = TruncC.trunc(TruncVT.getSizeInBits());
3645 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0,
3646 DAG.getNode(ISD::AND, N->getDebugLoc(),
3648 DAG.getNode(ISD::TRUNCATE,
3651 DAG.getConstant(TruncC, TruncVT)));
3655 // fold operands of srl based on knowledge that the low bits are not
3657 if (N1C && SimplifyDemandedBits(SDValue(N, 0)))
3658 return SDValue(N, 0);
3661 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue());
3662 if (NewSRL.getNode())
3666 // Attempt to convert a srl of a load into a narrower zero-extending load.
3667 SDValue NarrowLoad = ReduceLoadWidth(N);
3668 if (NarrowLoad.getNode())
3671 // Here is a common situation. We want to optimize:
3674 // %b = and i32 %a, 2
3675 // %c = srl i32 %b, 1
3676 // brcond i32 %c ...
3682 // %c = setcc eq %b, 0
3685 // However when after the source operand of SRL is optimized into AND, the SRL
3686 // itself may not be optimized further. Look for it and add the BRCOND into
3688 if (N->hasOneUse()) {
3689 SDNode *Use = *N->use_begin();
3690 if (Use->getOpcode() == ISD::BRCOND)
3692 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) {
3693 // Also look pass the truncate.
3694 Use = *Use->use_begin();
3695 if (Use->getOpcode() == ISD::BRCOND)
3703 SDValue DAGCombiner::visitCTLZ(SDNode *N) {
3704 SDValue N0 = N->getOperand(0);
3705 EVT VT = N->getValueType(0);
3707 // fold (ctlz c1) -> c2
3708 if (isa<ConstantSDNode>(N0))
3709 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0);
3713 SDValue DAGCombiner::visitCTTZ(SDNode *N) {
3714 SDValue N0 = N->getOperand(0);
3715 EVT VT = N->getValueType(0);
3717 // fold (cttz c1) -> c2
3718 if (isa<ConstantSDNode>(N0))
3719 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0);
3723 SDValue DAGCombiner::visitCTPOP(SDNode *N) {
3724 SDValue N0 = N->getOperand(0);
3725 EVT VT = N->getValueType(0);
3727 // fold (ctpop c1) -> c2
3728 if (isa<ConstantSDNode>(N0))
3729 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0);
3733 SDValue DAGCombiner::visitSELECT(SDNode *N) {
3734 SDValue N0 = N->getOperand(0);
3735 SDValue N1 = N->getOperand(1);
3736 SDValue N2 = N->getOperand(2);
3737 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
3738 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
3739 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
3740 EVT VT = N->getValueType(0);
3741 EVT VT0 = N0.getValueType();
3743 // fold (select C, X, X) -> X
3746 // fold (select true, X, Y) -> X
3747 if (N0C && !N0C->isNullValue())
3749 // fold (select false, X, Y) -> Y
3750 if (N0C && N0C->isNullValue())
3752 // fold (select C, 1, X) -> (or C, X)
3753 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
3754 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3755 // fold (select C, 0, 1) -> (xor C, 1)
3756 if (VT.isInteger() &&
3759 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) &&
3760 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
3763 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0,
3764 N0, DAG.getConstant(1, VT0));
3765 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0,
3766 N0, DAG.getConstant(1, VT0));
3767 AddToWorkList(XORNode.getNode());
3769 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode);
3770 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
3772 // fold (select C, 0, X) -> (and (not C), X)
3773 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
3774 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3775 AddToWorkList(NOTNode.getNode());
3776 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
3778 // fold (select C, X, 1) -> (or (not C), X)
3779 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
3780 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
3781 AddToWorkList(NOTNode.getNode());
3782 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
3784 // fold (select C, X, 0) -> (and C, X)
3785 if (VT == MVT::i1 && N2C && N2C->isNullValue())
3786 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3787 // fold (select X, X, Y) -> (or X, Y)
3788 // fold (select X, 1, Y) -> (or X, Y)
3789 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
3790 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
3791 // fold (select X, Y, X) -> (and X, Y)
3792 // fold (select X, Y, 0) -> (and X, Y)
3793 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
3794 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
3796 // If we can fold this based on the true/false value, do so.
3797 if (SimplifySelectOps(N, N1, N2))
3798 return SDValue(N, 0); // Don't revisit N.
3800 // fold selects based on a setcc into other things, such as min/max/abs
3801 if (N0.getOpcode() == ISD::SETCC) {
3803 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
3804 // having to say they don't support SELECT_CC on every type the DAG knows
3805 // about, since there is no way to mark an opcode illegal at all value types
3806 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
3807 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
3808 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
3809 N0.getOperand(0), N0.getOperand(1),
3810 N1, N2, N0.getOperand(2));
3811 return SimplifySelect(N->getDebugLoc(), N0, N1, N2);
3817 SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
3818 SDValue N0 = N->getOperand(0);
3819 SDValue N1 = N->getOperand(1);
3820 SDValue N2 = N->getOperand(2);
3821 SDValue N3 = N->getOperand(3);
3822 SDValue N4 = N->getOperand(4);
3823 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
3825 // fold select_cc lhs, rhs, x, x, cc -> x
3829 // Determine if the condition we're dealing with is constant
3830 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
3831 N0, N1, CC, N->getDebugLoc(), false);
3832 if (SCC.getNode()) AddToWorkList(SCC.getNode());
3834 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
3835 if (!SCCC->isNullValue())
3836 return N2; // cond always true -> true val
3838 return N3; // cond always false -> false val
3841 // Fold to a simpler select_cc
3842 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC)
3843 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(),
3844 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
3847 // If we can fold this based on the true/false value, do so.
3848 if (SimplifySelectOps(N, N2, N3))
3849 return SDValue(N, 0); // Don't revisit N.
3851 // fold select_cc into other things, such as min/max/abs
3852 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC);
3855 SDValue DAGCombiner::visitSETCC(SDNode *N) {
3856 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
3857 cast<CondCodeSDNode>(N->getOperand(2))->get(),
3861 // ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this:
3862 // "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))"
3863 // transformation. Returns true if extension are possible and the above
3864 // mentioned transformation is profitable.
3865 static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0,
3867 SmallVector<SDNode*, 4> &ExtendNodes,
3868 const TargetLowering &TLI) {
3869 bool HasCopyToRegUses = false;
3870 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType());
3871 for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3872 UE = N0.getNode()->use_end();
3877 if (UI.getUse().getResNo() != N0.getResNo())
3879 // FIXME: Only extend SETCC N, N and SETCC N, c for now.
3880 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) {
3881 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get();
3882 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC))
3883 // Sign bits will be lost after a zext.
3886 for (unsigned i = 0; i != 2; ++i) {
3887 SDValue UseOp = User->getOperand(i);
3890 if (!isa<ConstantSDNode>(UseOp))
3895 ExtendNodes.push_back(User);
3898 // If truncates aren't free and there are users we can't
3899 // extend, it isn't worthwhile.
3902 // Remember if this value is live-out.
3903 if (User->getOpcode() == ISD::CopyToReg)
3904 HasCopyToRegUses = true;
3907 if (HasCopyToRegUses) {
3908 bool BothLiveOut = false;
3909 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3911 SDUse &Use = UI.getUse();
3912 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) {
3918 // Both unextended and extended values are live out. There had better be
3919 // a good reason for the transformation.
3920 return ExtendNodes.size();
3925 void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs,
3926 SDValue Trunc, SDValue ExtLoad, DebugLoc DL,
3927 ISD::NodeType ExtType) {
3928 // Extend SetCC uses if necessary.
3929 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) {
3930 SDNode *SetCC = SetCCs[i];
3931 SmallVector<SDValue, 4> Ops;
3933 for (unsigned j = 0; j != 2; ++j) {
3934 SDValue SOp = SetCC->getOperand(j);
3936 Ops.push_back(ExtLoad);
3938 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
3941 Ops.push_back(SetCC->getOperand(2));
3942 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0),
3943 &Ops[0], Ops.size()));
3947 SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
3948 SDValue N0 = N->getOperand(0);
3949 EVT VT = N->getValueType(0);
3951 // fold (sext c1) -> c1
3952 if (isa<ConstantSDNode>(N0))
3953 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0);
3955 // fold (sext (sext x)) -> (sext x)
3956 // fold (sext (aext x)) -> (sext x)
3957 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
3958 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT,
3961 if (N0.getOpcode() == ISD::TRUNCATE) {
3962 // fold (sext (truncate (load x))) -> (sext (smaller load x))
3963 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
3964 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
3965 if (NarrowLoad.getNode()) {
3966 SDNode* oye = N0.getNode()->getOperand(0).getNode();
3967 if (NarrowLoad.getNode() != N0.getNode()) {
3968 CombineTo(N0.getNode(), NarrowLoad);
3969 // CombineTo deleted the truncate, if needed, but not what's under it.
3972 return SDValue(N, 0); // Return N so it doesn't get rechecked!
3975 // See if the value being truncated is already sign extended. If so, just
3976 // eliminate the trunc/sext pair.
3977 SDValue Op = N0.getOperand(0);
3978 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits();
3979 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits();
3980 unsigned DestBits = VT.getScalarType().getSizeInBits();
3981 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
3983 if (OpBits == DestBits) {
3984 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
3985 // bits, it is already ready.
3986 if (NumSignBits > DestBits-MidBits)
3988 } else if (OpBits < DestBits) {
3989 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
3990 // bits, just sext from i32.
3991 if (NumSignBits > OpBits-MidBits)
3992 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op);
3994 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
3995 // bits, just truncate to i32.
3996 if (NumSignBits > OpBits-MidBits)
3997 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4000 // fold (sext (truncate x)) -> (sextinreg x).
4001 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
4002 N0.getValueType())) {
4003 if (OpBits < DestBits)
4004 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op);
4005 else if (OpBits > DestBits)
4006 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op);
4007 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op,
4008 DAG.getValueType(N0.getValueType()));
4012 // fold (sext (load x)) -> (sext (truncate (sextload x)))
4013 // None of the supported targets knows how to perform load and sign extend
4014 // on vectors in one instruction. We only perform this transformation on
4016 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4017 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4018 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) {
4019 bool DoXform = true;
4020 SmallVector<SDNode*, 4> SetCCs;
4021 if (!N0.hasOneUse())
4022 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI);
4024 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4025 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4027 LN0->getBasePtr(), LN0->getPointerInfo(),
4029 LN0->isVolatile(), LN0->isNonTemporal(),
4030 LN0->getAlignment());
4031 CombineTo(N, ExtLoad);
4032 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4033 N0.getValueType(), ExtLoad);
4034 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4035 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4037 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4041 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
4042 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
4043 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4044 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4045 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4046 EVT MemVT = LN0->getMemoryVT();
4047 if ((!LegalOperations && !LN0->isVolatile()) ||
4048 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) {
4049 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4051 LN0->getBasePtr(), LN0->getPointerInfo(),
4053 LN0->isVolatile(), LN0->isNonTemporal(),
4054 LN0->getAlignment());
4055 CombineTo(N, ExtLoad);
4056 CombineTo(N0.getNode(),
4057 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4058 N0.getValueType(), ExtLoad),
4059 ExtLoad.getValue(1));
4060 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4064 // fold (sext (and/or/xor (load x), cst)) ->
4065 // (and/or/xor (sextload x), (sext cst))
4066 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4067 N0.getOpcode() == ISD::XOR) &&
4068 isa<LoadSDNode>(N0.getOperand(0)) &&
4069 N0.getOperand(1).getOpcode() == ISD::Constant &&
4070 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) &&
4071 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4072 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4073 if (LN0->getExtensionType() != ISD::ZEXTLOAD) {
4074 bool DoXform = true;
4075 SmallVector<SDNode*, 4> SetCCs;
4076 if (!N0.hasOneUse())
4077 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND,
4080 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT,
4081 LN0->getChain(), LN0->getBasePtr(),
4082 LN0->getPointerInfo(),
4085 LN0->isNonTemporal(),
4086 LN0->getAlignment());
4087 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4088 Mask = Mask.sext(VT.getSizeInBits());
4089 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4090 ExtLoad, DAG.getConstant(Mask, VT));
4091 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4092 N0.getOperand(0).getDebugLoc(),
4093 N0.getOperand(0).getValueType(), ExtLoad);
4095 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4096 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4098 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4103 if (N0.getOpcode() == ISD::SETCC) {
4104 // sext(setcc) -> sext_in_reg(vsetcc) for vectors.
4105 // Only do this before legalize for now.
4106 if (VT.isVector() && !LegalOperations) {
4107 EVT N0VT = N0.getOperand(0).getValueType();
4108 // We know that the # elements of the results is the same as the
4109 // # elements of the compare (and the # elements of the compare result
4110 // for that matter). Check to see that they are the same size. If so,
4111 // we know that the element size of the sext'd result matches the
4112 // element size of the compare operands.
4113 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4114 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4116 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4117 // If the desired elements are smaller or larger than the source
4118 // elements we can use a matching integer vector type and then
4119 // truncate/sign extend
4121 EVT MatchingElementType =
4122 EVT::getIntegerVT(*DAG.getContext(),
4123 N0VT.getScalarType().getSizeInBits());
4124 EVT MatchingVectorType =
4125 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4126 N0VT.getVectorNumElements());
4128 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4130 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4131 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4135 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc)
4136 unsigned ElementWidth = VT.getScalarType().getSizeInBits();
4138 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT);
4140 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4141 NegOne, DAG.getConstant(0, VT),
4142 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4143 if (SCC.getNode()) return SCC;
4144 if (!LegalOperations ||
4145 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT)))
4146 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4147 DAG.getSetCC(N->getDebugLoc(),
4148 TLI.getSetCCResultType(VT),
4149 N0.getOperand(0), N0.getOperand(1),
4150 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4151 NegOne, DAG.getConstant(0, VT));
4154 // fold (sext x) -> (zext x) if the sign bit is known zero.
4155 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) &&
4156 DAG.SignBitIsZero(N0))
4157 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4162 SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
4163 SDValue N0 = N->getOperand(0);
4164 EVT VT = N->getValueType(0);
4166 // fold (zext c1) -> c1
4167 if (isa<ConstantSDNode>(N0))
4168 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0);
4169 // fold (zext (zext x)) -> (zext x)
4170 // fold (zext (aext x)) -> (zext x)
4171 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
4172 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT,
4175 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4176 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
4177 if (N0.getOpcode() == ISD::TRUNCATE) {
4178 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4179 if (NarrowLoad.getNode()) {
4180 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4181 if (NarrowLoad.getNode() != N0.getNode()) {
4182 CombineTo(N0.getNode(), NarrowLoad);
4183 // CombineTo deleted the truncate, if needed, but not what's under it.
4186 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4190 // fold (zext (truncate x)) -> (and x, mask)
4191 if (N0.getOpcode() == ISD::TRUNCATE &&
4192 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) {
4194 // fold (zext (truncate (load x))) -> (zext (smaller load x))
4195 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n)))
4196 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4197 if (NarrowLoad.getNode()) {
4198 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4199 if (NarrowLoad.getNode() != N0.getNode()) {
4200 CombineTo(N0.getNode(), NarrowLoad);
4201 // CombineTo deleted the truncate, if needed, but not what's under it.
4204 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4207 SDValue Op = N0.getOperand(0);
4208 if (Op.getValueType().bitsLT(VT)) {
4209 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op);
4210 } else if (Op.getValueType().bitsGT(VT)) {
4211 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op);
4213 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(),
4214 N0.getValueType().getScalarType());
4217 // Fold (zext (and (trunc x), cst)) -> (and x, cst),
4218 // if either of the casts is not free.
4219 if (N0.getOpcode() == ISD::AND &&
4220 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4221 N0.getOperand(1).getOpcode() == ISD::Constant &&
4222 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4223 N0.getValueType()) ||
4224 !TLI.isZExtFree(N0.getValueType(), VT))) {
4225 SDValue X = N0.getOperand(0).getOperand(0);
4226 if (X.getValueType().bitsLT(VT)) {
4227 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X);
4228 } else if (X.getValueType().bitsGT(VT)) {
4229 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
4231 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4232 Mask = Mask.zext(VT.getSizeInBits());
4233 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4234 X, DAG.getConstant(Mask, VT));
4237 // fold (zext (load x)) -> (zext (truncate (zextload x)))
4238 // None of the supported targets knows how to perform load and vector_zext
4239 // on vectors in one instruction. We only perform this transformation on
4241 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4242 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4243 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
4244 bool DoXform = true;
4245 SmallVector<SDNode*, 4> SetCCs;
4246 if (!N0.hasOneUse())
4247 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI);
4249 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4250 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4252 LN0->getBasePtr(), LN0->getPointerInfo(),
4254 LN0->isVolatile(), LN0->isNonTemporal(),
4255 LN0->getAlignment());
4256 CombineTo(N, ExtLoad);
4257 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4258 N0.getValueType(), ExtLoad);
4259 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4261 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4263 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4267 // fold (zext (and/or/xor (load x), cst)) ->
4268 // (and/or/xor (zextload x), (zext cst))
4269 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR ||
4270 N0.getOpcode() == ISD::XOR) &&
4271 isa<LoadSDNode>(N0.getOperand(0)) &&
4272 N0.getOperand(1).getOpcode() == ISD::Constant &&
4273 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) &&
4274 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) {
4275 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0));
4276 if (LN0->getExtensionType() != ISD::SEXTLOAD) {
4277 bool DoXform = true;
4278 SmallVector<SDNode*, 4> SetCCs;
4279 if (!N0.hasOneUse())
4280 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND,
4283 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT,
4284 LN0->getChain(), LN0->getBasePtr(),
4285 LN0->getPointerInfo(),
4288 LN0->isNonTemporal(),
4289 LN0->getAlignment());
4290 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4291 Mask = Mask.zext(VT.getSizeInBits());
4292 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4293 ExtLoad, DAG.getConstant(Mask, VT));
4294 SDValue Trunc = DAG.getNode(ISD::TRUNCATE,
4295 N0.getOperand(0).getDebugLoc(),
4296 N0.getOperand(0).getValueType(), ExtLoad);
4298 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1));
4299 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4301 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4306 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
4307 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
4308 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
4309 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
4310 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4311 EVT MemVT = LN0->getMemoryVT();
4312 if ((!LegalOperations && !LN0->isVolatile()) ||
4313 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) {
4314 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
4316 LN0->getBasePtr(), LN0->getPointerInfo(),
4318 LN0->isVolatile(), LN0->isNonTemporal(),
4319 LN0->getAlignment());
4320 CombineTo(N, ExtLoad);
4321 CombineTo(N0.getNode(),
4322 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(),
4324 ExtLoad.getValue(1));
4325 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4329 if (N0.getOpcode() == ISD::SETCC) {
4330 if (!LegalOperations && VT.isVector()) {
4331 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors.
4332 // Only do this before legalize for now.
4333 EVT N0VT = N0.getOperand(0).getValueType();
4334 EVT EltVT = VT.getVectorElementType();
4335 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(),
4336 DAG.getConstant(1, EltVT));
4337 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4338 // We know that the # elements of the results is the same as the
4339 // # elements of the compare (and the # elements of the compare result
4340 // for that matter). Check to see that they are the same size. If so,
4341 // we know that the element size of the sext'd result matches the
4342 // element size of the compare operands.
4343 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4344 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4346 cast<CondCodeSDNode>(N0.getOperand(2))->get()),
4347 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4348 &OneOps[0], OneOps.size()));
4350 // If the desired elements are smaller or larger than the source
4351 // elements we can use a matching integer vector type and then
4352 // truncate/sign extend
4353 EVT MatchingElementType =
4354 EVT::getIntegerVT(*DAG.getContext(),
4355 N0VT.getScalarType().getSizeInBits());
4356 EVT MatchingVectorType =
4357 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4358 N0VT.getVectorNumElements());
4360 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4362 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4363 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4364 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT),
4365 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
4366 &OneOps[0], OneOps.size()));
4369 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4371 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4372 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4373 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4374 if (SCC.getNode()) return SCC;
4377 // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
4378 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
4379 isa<ConstantSDNode>(N0.getOperand(1)) &&
4380 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
4382 SDValue ShAmt = N0.getOperand(1);
4383 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4384 if (N0.getOpcode() == ISD::SHL) {
4385 SDValue InnerZExt = N0.getOperand(0);
4386 // If the original shl may be shifting out bits, do not perform this
4388 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() -
4389 InnerZExt.getOperand(0).getValueType().getSizeInBits();
4390 if (ShAmtVal > KnownZeroBits)
4394 DebugLoc DL = N->getDebugLoc();
4396 // Ensure that the shift amount is wide enough for the shifted value.
4397 if (VT.getSizeInBits() >= 256)
4398 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt);
4400 return DAG.getNode(N0.getOpcode(), DL, VT,
4401 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)),
4408 SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
4409 SDValue N0 = N->getOperand(0);
4410 EVT VT = N->getValueType(0);
4412 // fold (aext c1) -> c1
4413 if (isa<ConstantSDNode>(N0))
4414 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0);
4415 // fold (aext (aext x)) -> (aext x)
4416 // fold (aext (zext x)) -> (zext x)
4417 // fold (aext (sext x)) -> (sext x)
4418 if (N0.getOpcode() == ISD::ANY_EXTEND ||
4419 N0.getOpcode() == ISD::ZERO_EXTEND ||
4420 N0.getOpcode() == ISD::SIGN_EXTEND)
4421 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0));
4423 // fold (aext (truncate (load x))) -> (aext (smaller load x))
4424 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
4425 if (N0.getOpcode() == ISD::TRUNCATE) {
4426 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode());
4427 if (NarrowLoad.getNode()) {
4428 SDNode* oye = N0.getNode()->getOperand(0).getNode();
4429 if (NarrowLoad.getNode() != N0.getNode()) {
4430 CombineTo(N0.getNode(), NarrowLoad);
4431 // CombineTo deleted the truncate, if needed, but not what's under it.
4434 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4438 // fold (aext (truncate x))
4439 if (N0.getOpcode() == ISD::TRUNCATE) {
4440 SDValue TruncOp = N0.getOperand(0);
4441 if (TruncOp.getValueType() == VT)
4442 return TruncOp; // x iff x size == zext size.
4443 if (TruncOp.getValueType().bitsGT(VT))
4444 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp);
4445 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp);
4448 // Fold (aext (and (trunc x), cst)) -> (and x, cst)
4449 // if the trunc is not free.
4450 if (N0.getOpcode() == ISD::AND &&
4451 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
4452 N0.getOperand(1).getOpcode() == ISD::Constant &&
4453 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(),
4454 N0.getValueType())) {
4455 SDValue X = N0.getOperand(0).getOperand(0);
4456 if (X.getValueType().bitsLT(VT)) {
4457 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X);
4458 } else if (X.getValueType().bitsGT(VT)) {
4459 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X);
4461 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
4462 Mask = Mask.zext(VT.getSizeInBits());
4463 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
4464 X, DAG.getConstant(Mask, VT));
4467 // fold (aext (load x)) -> (aext (truncate (extload x)))
4468 // None of the supported targets knows how to perform load and any_ext
4469 // on vectors in one instruction. We only perform this transformation on
4471 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() &&
4472 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4473 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
4474 bool DoXform = true;
4475 SmallVector<SDNode*, 4> SetCCs;
4476 if (!N0.hasOneUse())
4477 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI);
4479 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4480 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
4482 LN0->getBasePtr(), LN0->getPointerInfo(),
4484 LN0->isVolatile(), LN0->isNonTemporal(),
4485 LN0->getAlignment());
4486 CombineTo(N, ExtLoad);
4487 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4488 N0.getValueType(), ExtLoad);
4489 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1));
4490 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(),
4492 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4496 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
4497 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
4498 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
4499 if (N0.getOpcode() == ISD::LOAD &&
4500 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4502 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4503 EVT MemVT = LN0->getMemoryVT();
4504 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
4505 VT, LN0->getChain(), LN0->getBasePtr(),
4506 LN0->getPointerInfo(), MemVT,
4507 LN0->isVolatile(), LN0->isNonTemporal(),
4508 LN0->getAlignment());
4509 CombineTo(N, ExtLoad);
4510 CombineTo(N0.getNode(),
4511 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(),
4512 N0.getValueType(), ExtLoad),
4513 ExtLoad.getValue(1));
4514 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4517 if (N0.getOpcode() == ISD::SETCC) {
4518 // aext(setcc) -> sext_in_reg(vsetcc) for vectors.
4519 // Only do this before legalize for now.
4520 if (VT.isVector() && !LegalOperations) {
4521 EVT N0VT = N0.getOperand(0).getValueType();
4522 // We know that the # elements of the results is the same as the
4523 // # elements of the compare (and the # elements of the compare result
4524 // for that matter). Check to see that they are the same size. If so,
4525 // we know that the element size of the sext'd result matches the
4526 // element size of the compare operands.
4527 if (VT.getSizeInBits() == N0VT.getSizeInBits())
4528 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0),
4530 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4531 // If the desired elements are smaller or larger than the source
4532 // elements we can use a matching integer vector type and then
4533 // truncate/sign extend
4535 EVT MatchingElementType =
4536 EVT::getIntegerVT(*DAG.getContext(),
4537 N0VT.getScalarType().getSizeInBits());
4538 EVT MatchingVectorType =
4539 EVT::getVectorVT(*DAG.getContext(), MatchingElementType,
4540 N0VT.getVectorNumElements());
4542 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0),
4544 cast<CondCodeSDNode>(N0.getOperand(2))->get());
4545 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT);
4549 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
4551 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1),
4552 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
4553 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true);
4561 /// GetDemandedBits - See if the specified operand can be simplified with the
4562 /// knowledge that only the bits specified by Mask are used. If so, return the
4563 /// simpler operand, otherwise return a null SDValue.
4564 SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) {
4565 switch (V.getOpcode()) {
4569 // If the LHS or RHS don't contribute bits to the or, drop them.
4570 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask))
4571 return V.getOperand(1);
4572 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask))
4573 return V.getOperand(0);
4576 // Only look at single-use SRLs.
4577 if (!V.getNode()->hasOneUse())
4579 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) {
4580 // See if we can recursively simplify the LHS.
4581 unsigned Amt = RHSC->getZExtValue();
4583 // Watch out for shift count overflow though.
4584 if (Amt >= Mask.getBitWidth()) break;
4585 APInt NewMask = Mask << Amt;
4586 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask);
4587 if (SimplifyLHS.getNode())
4588 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(),
4589 SimplifyLHS, V.getOperand(1));
4595 /// ReduceLoadWidth - If the result of a wider load is shifted to right of N
4596 /// bits and then truncated to a narrower type and where N is a multiple
4597 /// of number of bits of the narrower type, transform it to a narrower load
4598 /// from address + N / num of bits of new type. If the result is to be
4599 /// extended, also fold the extension to form a extending load.
4600 SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
4601 unsigned Opc = N->getOpcode();
4603 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
4604 SDValue N0 = N->getOperand(0);
4605 EVT VT = N->getValueType(0);
4608 // This transformation isn't valid for vector loads.
4612 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4614 if (Opc == ISD::SIGN_EXTEND_INREG) {
4615 ExtType = ISD::SEXTLOAD;
4616 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4617 } else if (Opc == ISD::SRL) {
4618 // Another special-case: SRL is basically zero-extending a narrower value.
4619 ExtType = ISD::ZEXTLOAD;
4621 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4622 if (!N01) return SDValue();
4623 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4624 VT.getSizeInBits() - N01->getZExtValue());
4626 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
4629 unsigned EVTBits = ExtVT.getSizeInBits();
4631 // Do not generate loads of non-round integer types since these can
4632 // be expensive (and would be wrong if the type is not byte sized).
4633 if (!ExtVT.isRound())
4637 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
4638 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4639 ShAmt = N01->getZExtValue();
4640 // Is the shift amount a multiple of size of VT?
4641 if ((ShAmt & (EVTBits-1)) == 0) {
4642 N0 = N0.getOperand(0);
4643 // Is the load width a multiple of size of VT?
4644 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0)
4648 // At this point, we must have a load or else we can't do the transform.
4649 if (!isa<LoadSDNode>(N0)) return SDValue();
4651 // If the shift amount is larger than the input type then we're not
4652 // accessing any of the loaded bytes. If the load was a zextload/extload
4653 // then the result of the shift+trunc is zero/undef (handled elsewhere).
4654 // If the load was a sextload then the result is a splat of the sign bit
4655 // of the extended byte. This is not worth optimizing for.
4656 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits())
4661 // If the load is shifted left (and the result isn't shifted back right),
4662 // we can fold the truncate through the shift.
4663 unsigned ShLeftAmt = 0;
4664 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
4665 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
4666 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4667 ShLeftAmt = N01->getZExtValue();
4668 N0 = N0.getOperand(0);
4672 // If we haven't found a load, we can't narrow it. Don't transform one with
4673 // multiple uses, this would require adding a new load.
4674 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() ||
4675 // Don't change the width of a volatile load.
4676 cast<LoadSDNode>(N0)->isVolatile())
4679 // Verify that we are actually reducing a load width here.
4680 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits)
4683 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4684 EVT PtrType = N0.getOperand(1).getValueType();
4686 // For big endian targets, we need to adjust the offset to the pointer to
4687 // load the correct bytes.
4688 if (TLI.isBigEndian()) {
4689 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
4690 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4691 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
4694 uint64_t PtrOff = ShAmt / 8;
4695 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff);
4696 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(),
4697 PtrType, LN0->getBasePtr(),
4698 DAG.getConstant(PtrOff, PtrType));
4699 AddToWorkList(NewPtr.getNode());
4702 if (ExtType == ISD::NON_EXTLOAD)
4703 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr,
4704 LN0->getPointerInfo().getWithOffset(PtrOff),
4705 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign);
4707 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr,
4708 LN0->getPointerInfo().getWithOffset(PtrOff),
4709 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
4712 // Replace the old load's chain with the new load's chain.
4713 WorkListRemover DeadNodes(*this);
4714 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
4717 // Shift the result left, if we've swallowed a left shift.
4718 SDValue Result = Load;
4719 if (ShLeftAmt != 0) {
4720 EVT ShImmTy = getShiftAmountTy(Result.getValueType());
4721 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt))
4723 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT,
4724 Result, DAG.getConstant(ShLeftAmt, ShImmTy));
4727 // Return the new loaded value.
4731 SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
4732 SDValue N0 = N->getOperand(0);
4733 SDValue N1 = N->getOperand(1);
4734 EVT VT = N->getValueType(0);
4735 EVT EVT = cast<VTSDNode>(N1)->getVT();
4736 unsigned VTBits = VT.getScalarType().getSizeInBits();
4737 unsigned EVTBits = EVT.getScalarType().getSizeInBits();
4739 // fold (sext_in_reg c1) -> c1
4740 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
4741 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1);
4743 // If the input is already sign extended, just drop the extension.
4744 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1)
4747 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
4748 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
4749 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) {
4750 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4751 N0.getOperand(0), N1);
4754 // fold (sext_in_reg (sext x)) -> (sext x)
4755 // fold (sext_in_reg (aext x)) -> (sext x)
4756 // if x is small enough.
4757 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) {
4758 SDValue N00 = N0.getOperand(0);
4759 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits &&
4760 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT)))
4761 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1);
4764 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
4765 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits)))
4766 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT);
4768 // fold operands of sext_in_reg based on knowledge that the top bits are not
4770 if (SimplifyDemandedBits(SDValue(N, 0)))
4771 return SDValue(N, 0);
4773 // fold (sext_in_reg (load x)) -> (smaller sextload x)
4774 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
4775 SDValue NarrowLoad = ReduceLoadWidth(N);
4776 if (NarrowLoad.getNode())
4779 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24)
4780 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
4781 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
4782 if (N0.getOpcode() == ISD::SRL) {
4783 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
4784 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
4785 // We can turn this into an SRA iff the input to the SRL is already sign
4787 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
4788 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
4789 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT,
4790 N0.getOperand(0), N0.getOperand(1));
4794 // fold (sext_inreg (extload x)) -> (sextload x)
4795 if (ISD::isEXTLoad(N0.getNode()) &&
4796 ISD::isUNINDEXEDLoad(N0.getNode()) &&
4797 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4798 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4799 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4800 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4801 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4803 LN0->getBasePtr(), LN0->getPointerInfo(),
4805 LN0->isVolatile(), LN0->isNonTemporal(),
4806 LN0->getAlignment());
4807 CombineTo(N, ExtLoad);
4808 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4809 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4811 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
4812 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
4814 EVT == cast<LoadSDNode>(N0)->getMemoryVT() &&
4815 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
4816 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) {
4817 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4818 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
4820 LN0->getBasePtr(), LN0->getPointerInfo(),
4822 LN0->isVolatile(), LN0->isNonTemporal(),
4823 LN0->getAlignment());
4824 CombineTo(N, ExtLoad);
4825 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
4826 return SDValue(N, 0); // Return N so it doesn't get rechecked!
4829 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
4830 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
4831 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
4832 N0.getOperand(1), false);
4833 if (BSwap.getNode() != 0)
4834 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
4841 SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
4842 SDValue N0 = N->getOperand(0);
4843 EVT VT = N->getValueType(0);
4846 if (N0.getValueType() == N->getValueType(0))
4848 // fold (truncate c1) -> c1
4849 if (isa<ConstantSDNode>(N0))
4850 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0);
4851 // fold (truncate (truncate x)) -> (truncate x)
4852 if (N0.getOpcode() == ISD::TRUNCATE)
4853 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4854 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
4855 if (N0.getOpcode() == ISD::ZERO_EXTEND ||
4856 N0.getOpcode() == ISD::SIGN_EXTEND ||
4857 N0.getOpcode() == ISD::ANY_EXTEND) {
4858 if (N0.getOperand(0).getValueType().bitsLT(VT))
4859 // if the source is smaller than the dest, we still need an extend
4860 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT,
4862 else if (N0.getOperand(0).getValueType().bitsGT(VT))
4863 // if the source is larger than the dest, than we just need the truncate
4864 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0));
4866 // if the source and dest are the same type, we can drop both the extend
4867 // and the truncate.
4868 return N0.getOperand(0);
4871 // See if we can simplify the input to this truncate through knowledge that
4872 // only the low bits are being used.
4873 // For example "trunc (or (shl x, 8), y)" // -> trunc y
4874 // Currently we only perform this optimization on scalars because vectors
4875 // may have different active low bits.
4876 if (!VT.isVector()) {
4878 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
4879 VT.getSizeInBits()));
4880 if (Shorter.getNode())
4881 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter);
4883 // fold (truncate (load x)) -> (smaller load x)
4884 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
4885 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {
4886 SDValue Reduced = ReduceLoadWidth(N);
4887 if (Reduced.getNode())
4891 // Simplify the operands using demanded-bits information.
4892 if (!VT.isVector() &&
4893 SimplifyDemandedBits(SDValue(N, 0)))
4894 return SDValue(N, 0);
4899 static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
4900 SDValue Elt = N->getOperand(i);
4901 if (Elt.getOpcode() != ISD::MERGE_VALUES)
4902 return Elt.getNode();
4903 return Elt.getOperand(Elt.getResNo()).getNode();
4906 /// CombineConsecutiveLoads - build_pair (load, load) -> load
4907 /// if load locations are consecutive.
4908 SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
4909 assert(N->getOpcode() == ISD::BUILD_PAIR);
4911 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
4912 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
4913 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() ||
4914 LD1->getPointerInfo().getAddrSpace() !=
4915 LD2->getPointerInfo().getAddrSpace())
4917 EVT LD1VT = LD1->getValueType(0);
4919 if (ISD::isNON_EXTLoad(LD2) &&
4921 // If both are volatile this would reduce the number of volatile loads.
4922 // If one is volatile it might be ok, but play conservative and bail out.
4923 !LD1->isVolatile() &&
4924 !LD2->isVolatile() &&
4925 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) {
4926 unsigned Align = LD1->getAlignment();
4927 unsigned NewAlign = TLI.getTargetData()->
4928 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4930 if (NewAlign <= Align &&
4931 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
4932 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(),
4933 LD1->getBasePtr(), LD1->getPointerInfo(),
4934 false, false, Align);
4940 SDValue DAGCombiner::visitBITCAST(SDNode *N) {
4941 SDValue N0 = N->getOperand(0);
4942 EVT VT = N->getValueType(0);
4944 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
4945 // Only do this before legalize, since afterward the target may be depending
4946 // on the bitconvert.
4947 // First check to see if this is all constant.
4949 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() &&
4951 bool isSimple = true;
4952 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
4953 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
4954 N0.getOperand(i).getOpcode() != ISD::Constant &&
4955 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
4960 EVT DestEltVT = N->getValueType(0).getVectorElementType();
4961 assert(!DestEltVT.isVector() &&
4962 "Element type of vector ValueType must not be vector!");
4964 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT);
4967 // If the input is a constant, let getNode fold it.
4968 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
4969 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0);
4970 if (Res.getNode() != N) {
4971 if (!LegalOperations ||
4972 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT))
4975 // Folding it resulted in an illegal node, and it's too late to
4976 // do that. Clean up the old node and forego the transformation.
4977 // Ideally this won't happen very often, because instcombine
4978 // and the earlier dagcombine runs (where illegal nodes are
4979 // permitted) should have folded most of them already.
4980 DAG.DeleteNode(Res.getNode());
4984 // (conv (conv x, t1), t2) -> (conv x, t2)
4985 if (N0.getOpcode() == ISD::BITCAST)
4986 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT,
4989 // fold (conv (load x)) -> (load (conv*)x)
4990 // If the resultant load doesn't need a higher alignment than the original!
4991 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
4992 // Do not change the width of a volatile load.
4993 !cast<LoadSDNode>(N0)->isVolatile() &&
4994 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
4995 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
4996 unsigned Align = TLI.getTargetData()->
4997 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext()));
4998 unsigned OrigAlign = LN0->getAlignment();
5000 if (Align <= OrigAlign) {
5001 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(),
5002 LN0->getBasePtr(), LN0->getPointerInfo(),
5003 LN0->isVolatile(), LN0->isNonTemporal(),
5006 CombineTo(N0.getNode(),
5007 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5008 N0.getValueType(), Load),
5014 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit)
5015 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit))
5016 // This often reduces constant pool loads.
5017 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
5018 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) {
5019 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT,
5021 AddToWorkList(NewConv.getNode());
5023 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5024 if (N0.getOpcode() == ISD::FNEG)
5025 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT,
5026 NewConv, DAG.getConstant(SignBit, VT));
5027 assert(N0.getOpcode() == ISD::FABS);
5028 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT,
5029 NewConv, DAG.getConstant(~SignBit, VT));
5032 // fold (bitconvert (fcopysign cst, x)) ->
5033 // (or (and (bitconvert x), sign), (and cst, (not sign)))
5034 // Note that we don't handle (copysign x, cst) because this can always be
5035 // folded to an fneg or fabs.
5036 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() &&
5037 isa<ConstantFPSDNode>(N0.getOperand(0)) &&
5038 VT.isInteger() && !VT.isVector()) {
5039 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
5040 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth);
5041 if (isTypeLegal(IntXVT)) {
5042 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5043 IntXVT, N0.getOperand(1));
5044 AddToWorkList(X.getNode());
5046 // If X has a different width than the result/lhs, sext it or truncate it.
5047 unsigned VTWidth = VT.getSizeInBits();
5048 if (OrigXWidth < VTWidth) {
5049 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X);
5050 AddToWorkList(X.getNode());
5051 } else if (OrigXWidth > VTWidth) {
5052 // To get the sign bit in the right place, we have to shift it right
5053 // before truncating.
5054 X = DAG.getNode(ISD::SRL, X.getDebugLoc(),
5055 X.getValueType(), X,
5056 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType()));
5057 AddToWorkList(X.getNode());
5058 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X);
5059 AddToWorkList(X.getNode());
5062 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
5063 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT,
5064 X, DAG.getConstant(SignBit, VT));
5065 AddToWorkList(X.getNode());
5067 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(),
5068 VT, N0.getOperand(0));
5069 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT,
5070 Cst, DAG.getConstant(~SignBit, VT));
5071 AddToWorkList(Cst.getNode());
5073 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst);
5077 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive.
5078 if (N0.getOpcode() == ISD::BUILD_PAIR) {
5079 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT);
5080 if (CombineLD.getNode())
5087 SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
5088 EVT VT = N->getValueType(0);
5089 return CombineConsecutiveLoads(N, VT);
5092 /// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector
5093 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
5094 /// destination element value type.
5095 SDValue DAGCombiner::
5096 ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
5097 EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
5099 // If this is already the right type, we're done.
5100 if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
5102 unsigned SrcBitSize = SrcEltVT.getSizeInBits();
5103 unsigned DstBitSize = DstEltVT.getSizeInBits();
5105 // If this is a conversion of N elements of one type to N elements of another
5106 // type, convert each element. This handles FP<->INT cases.
5107 if (SrcBitSize == DstBitSize) {
5108 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5109 BV->getValueType(0).getVectorNumElements());
5111 // Due to the FP element handling below calling this routine recursively,
5112 // we can end up with a scalar-to-vector node here.
5113 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR)
5114 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5115 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5116 DstEltVT, BV->getOperand(0)));
5118 SmallVector<SDValue, 8> Ops;
5119 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5120 SDValue Op = BV->getOperand(i);
5121 // If the vector element type is not legal, the BUILD_VECTOR operands
5122 // are promoted and implicitly truncated. Make that explicit here.
5123 if (Op.getValueType() != SrcEltVT)
5124 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op);
5125 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(),
5127 AddToWorkList(Ops.back().getNode());
5129 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5130 &Ops[0], Ops.size());
5133 // Otherwise, we're growing or shrinking the elements. To avoid having to
5134 // handle annoying details of growing/shrinking FP values, we convert them to
5136 if (SrcEltVT.isFloatingPoint()) {
5137 // Convert the input float vector to a int vector where the elements are the
5139 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
5140 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits());
5141 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode();
5145 // Now we know the input is an integer vector. If the output is a FP type,
5146 // convert to integer first, then to FP of the right size.
5147 if (DstEltVT.isFloatingPoint()) {
5148 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
5149 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits());
5150 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode();
5152 // Next, convert to FP elements of the same size.
5153 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT);
5156 // Okay, we know the src/dst types are both integers of differing types.
5157 // Handling growing first.
5158 assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
5159 if (SrcBitSize < DstBitSize) {
5160 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
5162 SmallVector<SDValue, 8> Ops;
5163 for (unsigned i = 0, e = BV->getNumOperands(); i != e;
5164 i += NumInputsPerOutput) {
5165 bool isLE = TLI.isLittleEndian();
5166 APInt NewBits = APInt(DstBitSize, 0);
5167 bool EltIsUndef = true;
5168 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
5169 // Shift the previously computed bits over.
5170 NewBits <<= SrcBitSize;
5171 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
5172 if (Op.getOpcode() == ISD::UNDEF) continue;
5175 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
5176 zextOrTrunc(SrcBitSize).zext(DstBitSize);
5180 Ops.push_back(DAG.getUNDEF(DstEltVT));
5182 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
5185 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size());
5186 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5187 &Ops[0], Ops.size());
5190 // Finally, this must be the case where we are shrinking elements: each input
5191 // turns into multiple outputs.
5192 bool isS2V = ISD::isScalarToVector(BV);
5193 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
5194 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT,
5195 NumOutputsPerInput*BV->getNumOperands());
5196 SmallVector<SDValue, 8> Ops;
5198 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
5199 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
5200 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
5201 Ops.push_back(DAG.getUNDEF(DstEltVT));
5205 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->
5206 getAPIntValue().zextOrTrunc(SrcBitSize);
5208 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
5209 APInt ThisVal = OpVal.trunc(DstBitSize);
5210 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
5211 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal)
5212 // Simply turn this into a SCALAR_TO_VECTOR of the new type.
5213 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT,
5215 OpVal = OpVal.lshr(DstBitSize);
5218 // For big endian targets, swap the order of the pieces of each element.
5219 if (TLI.isBigEndian())
5220 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
5223 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
5224 &Ops[0], Ops.size());
5227 SDValue DAGCombiner::visitFADD(SDNode *N) {
5228 SDValue N0 = N->getOperand(0);
5229 SDValue N1 = N->getOperand(1);
5230 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5231 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5232 EVT VT = N->getValueType(0);
5235 if (VT.isVector()) {
5236 SDValue FoldedVOp = SimplifyVBinOp(N);
5237 if (FoldedVOp.getNode()) return FoldedVOp;
5240 // fold (fadd c1, c2) -> (fadd c1, c2)
5241 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5242 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
5243 // canonicalize constant to RHS
5244 if (N0CFP && !N1CFP)
5245 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0);
5246 // fold (fadd A, 0) -> A
5247 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5249 // fold (fadd A, (fneg B)) -> (fsub A, B)
5250 if (isNegatibleForFree(N1, LegalOperations) == 2)
5251 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0,
5252 GetNegatedExpression(N1, DAG, LegalOperations));
5253 // fold (fadd (fneg A), B) -> (fsub B, A)
5254 if (isNegatibleForFree(N0, LegalOperations) == 2)
5255 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1,
5256 GetNegatedExpression(N0, DAG, LegalOperations));
5258 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2))
5259 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD &&
5260 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5261 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0),
5262 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT,
5263 N0.getOperand(1), N1));
5268 SDValue DAGCombiner::visitFSUB(SDNode *N) {
5269 SDValue N0 = N->getOperand(0);
5270 SDValue N1 = N->getOperand(1);
5271 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5272 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5273 EVT VT = N->getValueType(0);
5276 if (VT.isVector()) {
5277 SDValue FoldedVOp = SimplifyVBinOp(N);
5278 if (FoldedVOp.getNode()) return FoldedVOp;
5281 // fold (fsub c1, c2) -> c1-c2
5282 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5283 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
5284 // fold (fsub A, 0) -> A
5285 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5287 // fold (fsub 0, B) -> -B
5288 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) {
5289 if (isNegatibleForFree(N1, LegalOperations))
5290 return GetNegatedExpression(N1, DAG, LegalOperations);
5291 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5292 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1);
5294 // fold (fsub A, (fneg B)) -> (fadd A, B)
5295 if (isNegatibleForFree(N1, LegalOperations))
5296 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0,
5297 GetNegatedExpression(N1, DAG, LegalOperations));
5302 SDValue DAGCombiner::visitFMUL(SDNode *N) {
5303 SDValue N0 = N->getOperand(0);
5304 SDValue N1 = N->getOperand(1);
5305 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5306 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5307 EVT VT = N->getValueType(0);
5310 if (VT.isVector()) {
5311 SDValue FoldedVOp = SimplifyVBinOp(N);
5312 if (FoldedVOp.getNode()) return FoldedVOp;
5315 // fold (fmul c1, c2) -> c1*c2
5316 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5317 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
5318 // canonicalize constant to RHS
5319 if (N0CFP && !N1CFP)
5320 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0);
5321 // fold (fmul A, 0) -> 0
5322 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
5324 // fold (fmul A, 0) -> 0, vector edition.
5325 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode()))
5327 // fold (fmul X, 2.0) -> (fadd X, X)
5328 if (N1CFP && N1CFP->isExactlyValue(+2.0))
5329 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0);
5330 // fold (fmul X, -1.0) -> (fneg X)
5331 if (N1CFP && N1CFP->isExactlyValue(-1.0))
5332 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5333 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0);
5335 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y)
5336 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5337 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5338 // Both can be negated for free, check to see if at least one is cheaper
5340 if (LHSNeg == 2 || RHSNeg == 2)
5341 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5342 GetNegatedExpression(N0, DAG, LegalOperations),
5343 GetNegatedExpression(N1, DAG, LegalOperations));
5347 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2))
5348 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
5349 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
5350 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
5351 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
5352 N0.getOperand(1), N1));
5357 SDValue DAGCombiner::visitFDIV(SDNode *N) {
5358 SDValue N0 = N->getOperand(0);
5359 SDValue N1 = N->getOperand(1);
5360 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5361 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5362 EVT VT = N->getValueType(0);
5365 if (VT.isVector()) {
5366 SDValue FoldedVOp = SimplifyVBinOp(N);
5367 if (FoldedVOp.getNode()) return FoldedVOp;
5370 // fold (fdiv c1, c2) -> c1/c2
5371 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5372 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
5375 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y)
5376 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) {
5377 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) {
5378 // Both can be negated for free, check to see if at least one is cheaper
5380 if (LHSNeg == 2 || RHSNeg == 2)
5381 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT,
5382 GetNegatedExpression(N0, DAG, LegalOperations),
5383 GetNegatedExpression(N1, DAG, LegalOperations));
5390 SDValue DAGCombiner::visitFREM(SDNode *N) {
5391 SDValue N0 = N->getOperand(0);
5392 SDValue N1 = N->getOperand(1);
5393 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5394 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5395 EVT VT = N->getValueType(0);
5397 // fold (frem c1, c2) -> fmod(c1,c2)
5398 if (N0CFP && N1CFP && VT != MVT::ppcf128)
5399 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
5404 SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) {
5405 SDValue N0 = N->getOperand(0);
5406 SDValue N1 = N->getOperand(1);
5407 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5408 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
5409 EVT VT = N->getValueType(0);
5411 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
5412 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
5415 const APFloat& V = N1CFP->getValueAPF();
5416 // copysign(x, c1) -> fabs(x) iff ispos(c1)
5417 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
5418 if (!V.isNegative()) {
5419 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT))
5420 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5422 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))
5423 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT,
5424 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0));
5428 // copysign(fabs(x), y) -> copysign(x, y)
5429 // copysign(fneg(x), y) -> copysign(x, y)
5430 // copysign(copysign(x,z), y) -> copysign(x, y)
5431 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
5432 N0.getOpcode() == ISD::FCOPYSIGN)
5433 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5434 N0.getOperand(0), N1);
5436 // copysign(x, abs(y)) -> abs(x)
5437 if (N1.getOpcode() == ISD::FABS)
5438 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5440 // copysign(x, copysign(y,z)) -> copysign(x, z)
5441 if (N1.getOpcode() == ISD::FCOPYSIGN)
5442 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5443 N0, N1.getOperand(1));
5445 // copysign(x, fp_extend(y)) -> copysign(x, y)
5446 // copysign(x, fp_round(y)) -> copysign(x, y)
5447 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
5448 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5449 N0, N1.getOperand(0));
5454 SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
5455 SDValue N0 = N->getOperand(0);
5456 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5457 EVT VT = N->getValueType(0);
5458 EVT OpVT = N0.getValueType();
5460 // fold (sint_to_fp c1) -> c1fp
5461 if (N0C && OpVT != MVT::ppcf128 &&
5462 // ...but only if the target supports immediate floating-point values
5463 (Level == llvm::Unrestricted ||
5464 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5465 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5467 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
5468 // but UINT_TO_FP is legal on this target, try to convert.
5469 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) &&
5470 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) {
5471 // If the sign bit is known to be zero, we can change this to UINT_TO_FP.
5472 if (DAG.SignBitIsZero(N0))
5473 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5479 SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
5480 SDValue N0 = N->getOperand(0);
5481 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
5482 EVT VT = N->getValueType(0);
5483 EVT OpVT = N0.getValueType();
5485 // fold (uint_to_fp c1) -> c1fp
5486 if (N0C && OpVT != MVT::ppcf128 &&
5487 // ...but only if the target supports immediate floating-point values
5488 (Level == llvm::Unrestricted ||
5489 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
5490 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
5492 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
5493 // but SINT_TO_FP is legal on this target, try to convert.
5494 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) &&
5495 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) {
5496 // If the sign bit is known to be zero, we can change this to SINT_TO_FP.
5497 if (DAG.SignBitIsZero(N0))
5498 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
5504 SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
5505 SDValue N0 = N->getOperand(0);
5506 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5507 EVT VT = N->getValueType(0);
5509 // fold (fp_to_sint c1fp) -> c1
5511 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0);
5516 SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
5517 SDValue N0 = N->getOperand(0);
5518 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5519 EVT VT = N->getValueType(0);
5521 // fold (fp_to_uint c1fp) -> c1
5522 if (N0CFP && VT != MVT::ppcf128)
5523 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
5528 SDValue DAGCombiner::visitFP_ROUND(SDNode *N) {
5529 SDValue N0 = N->getOperand(0);
5530 SDValue N1 = N->getOperand(1);
5531 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5532 EVT VT = N->getValueType(0);
5534 // fold (fp_round c1fp) -> c1fp
5535 if (N0CFP && N0.getValueType() != MVT::ppcf128)
5536 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
5538 // fold (fp_round (fp_extend x)) -> x
5539 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
5540 return N0.getOperand(0);
5542 // fold (fp_round (fp_round x)) -> (fp_round x)
5543 if (N0.getOpcode() == ISD::FP_ROUND) {
5544 // This is a value preserving truncation if both round's are.
5545 bool IsTrunc = N->getConstantOperandVal(1) == 1 &&
5546 N0.getNode()->getConstantOperandVal(1) == 1;
5547 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0),
5548 DAG.getIntPtrConstant(IsTrunc));
5551 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
5552 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) {
5553 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT,
5554 N0.getOperand(0), N1);
5555 AddToWorkList(Tmp.getNode());
5556 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT,
5557 Tmp, N0.getOperand(1));
5563 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
5564 SDValue N0 = N->getOperand(0);
5565 EVT VT = N->getValueType(0);
5566 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
5567 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5569 // fold (fp_round_inreg c1fp) -> c1fp
5570 if (N0CFP && isTypeLegal(EVT)) {
5571 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT);
5572 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round);
5578 SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
5579 SDValue N0 = N->getOperand(0);
5580 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5581 EVT VT = N->getValueType(0);
5583 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
5584 if (N->hasOneUse() &&
5585 N->use_begin()->getOpcode() == ISD::FP_ROUND)
5588 // fold (fp_extend c1fp) -> c1fp
5589 if (N0CFP && VT != MVT::ppcf128)
5590 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
5592 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
5594 if (N0.getOpcode() == ISD::FP_ROUND
5595 && N0.getNode()->getConstantOperandVal(1) == 1) {
5596 SDValue In = N0.getOperand(0);
5597 if (In.getValueType() == VT) return In;
5598 if (VT.bitsLT(In.getValueType()))
5599 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT,
5600 In, N0.getOperand(1));
5601 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In);
5604 // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))
5605 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() &&
5606 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) ||
5607 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) {
5608 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
5609 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT,
5611 LN0->getBasePtr(), LN0->getPointerInfo(),
5613 LN0->isVolatile(), LN0->isNonTemporal(),
5614 LN0->getAlignment());
5615 CombineTo(N, ExtLoad);
5616 CombineTo(N0.getNode(),
5617 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(),
5618 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)),
5619 ExtLoad.getValue(1));
5620 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5626 SDValue DAGCombiner::visitFNEG(SDNode *N) {
5627 SDValue N0 = N->getOperand(0);
5628 EVT VT = N->getValueType(0);
5630 if (isNegatibleForFree(N0, LegalOperations))
5631 return GetNegatedExpression(N0, DAG, LegalOperations);
5633 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
5634 // constant pool values.
5635 if (N0.getOpcode() == ISD::BITCAST &&
5637 N0.getNode()->hasOneUse() &&
5638 N0.getOperand(0).getValueType().isInteger()) {
5639 SDValue Int = N0.getOperand(0);
5640 EVT IntVT = Int.getValueType();
5641 if (IntVT.isInteger() && !IntVT.isVector()) {
5642 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
5643 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5644 AddToWorkList(Int.getNode());
5645 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5653 SDValue DAGCombiner::visitFABS(SDNode *N) {
5654 SDValue N0 = N->getOperand(0);
5655 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
5656 EVT VT = N->getValueType(0);
5658 // fold (fabs c1) -> fabs(c1)
5659 if (N0CFP && VT != MVT::ppcf128)
5660 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
5661 // fold (fabs (fabs x)) -> (fabs x)
5662 if (N0.getOpcode() == ISD::FABS)
5663 return N->getOperand(0);
5664 // fold (fabs (fneg x)) -> (fabs x)
5665 // fold (fabs (fcopysign x, y)) -> (fabs x)
5666 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
5667 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0));
5669 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
5670 // constant pool values.
5671 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() &&
5672 N0.getOperand(0).getValueType().isInteger() &&
5673 !N0.getOperand(0).getValueType().isVector()) {
5674 SDValue Int = N0.getOperand(0);
5675 EVT IntVT = Int.getValueType();
5676 if (IntVT.isInteger() && !IntVT.isVector()) {
5677 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
5678 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
5679 AddToWorkList(Int.getNode());
5680 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5681 N->getValueType(0), Int);
5688 SDValue DAGCombiner::visitBRCOND(SDNode *N) {
5689 SDValue Chain = N->getOperand(0);
5690 SDValue N1 = N->getOperand(1);
5691 SDValue N2 = N->getOperand(2);
5693 // If N is a constant we could fold this into a fallthrough or unconditional
5694 // branch. However that doesn't happen very often in normal code, because
5695 // Instcombine/SimplifyCFG should have handled the available opportunities.
5696 // If we did this folding here, it would be necessary to update the
5697 // MachineBasicBlock CFG, which is awkward.
5699 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
5701 if (N1.getOpcode() == ISD::SETCC &&
5702 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
5703 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5704 Chain, N1.getOperand(2),
5705 N1.getOperand(0), N1.getOperand(1), N2);
5708 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) ||
5709 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) &&
5710 (N1.getOperand(0).hasOneUse() &&
5711 N1.getOperand(0).getOpcode() == ISD::SRL))) {
5713 if (N1.getOpcode() == ISD::TRUNCATE) {
5714 // Look pass the truncate.
5715 Trunc = N1.getNode();
5716 N1 = N1.getOperand(0);
5719 // Match this pattern so that we can generate simpler code:
5722 // %b = and i32 %a, 2
5723 // %c = srl i32 %b, 1
5724 // brcond i32 %c ...
5729 // %b = and i32 %a, 2
5730 // %c = setcc eq %b, 0
5733 // This applies only when the AND constant value has one bit set and the
5734 // SRL constant is equal to the log2 of the AND constant. The back-end is
5735 // smart enough to convert the result into a TEST/JMP sequence.
5736 SDValue Op0 = N1.getOperand(0);
5737 SDValue Op1 = N1.getOperand(1);
5739 if (Op0.getOpcode() == ISD::AND &&
5740 Op1.getOpcode() == ISD::Constant) {
5741 SDValue AndOp1 = Op0.getOperand(1);
5743 if (AndOp1.getOpcode() == ISD::Constant) {
5744 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
5746 if (AndConst.isPowerOf2() &&
5747 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
5749 DAG.getSetCC(N->getDebugLoc(),
5750 TLI.getSetCCResultType(Op0.getValueType()),
5751 Op0, DAG.getConstant(0, Op0.getValueType()),
5754 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5755 MVT::Other, Chain, SetCC, N2);
5756 // Don't add the new BRCond into the worklist or else SimplifySelectCC
5757 // will convert it back to (X & C1) >> C2.
5758 CombineTo(N, NewBRCond, false);
5759 // Truncate is dead.
5761 removeFromWorkList(Trunc);
5762 DAG.DeleteNode(Trunc);
5764 // Replace the uses of SRL with SETCC
5765 WorkListRemover DeadNodes(*this);
5766 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5767 removeFromWorkList(N1.getNode());
5768 DAG.DeleteNode(N1.getNode());
5769 return SDValue(N, 0); // Return N so it doesn't get rechecked!
5775 // Restore N1 if the above transformation doesn't match.
5776 N1 = N->getOperand(1);
5779 // Transform br(xor(x, y)) -> br(x != y)
5780 // Transform br(xor(xor(x,y), 1)) -> br (x == y)
5781 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) {
5782 SDNode *TheXor = N1.getNode();
5783 SDValue Op0 = TheXor->getOperand(0);
5784 SDValue Op1 = TheXor->getOperand(1);
5785 if (Op0.getOpcode() == Op1.getOpcode()) {
5786 // Avoid missing important xor optimizations.
5787 SDValue Tmp = visitXOR(TheXor);
5788 if (Tmp.getNode() && Tmp.getNode() != TheXor) {
5789 DEBUG(dbgs() << "\nReplacing.8 ";
5791 dbgs() << "\nWith: ";
5792 Tmp.getNode()->dump(&DAG);
5794 WorkListRemover DeadNodes(*this);
5795 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes);
5796 removeFromWorkList(TheXor);
5797 DAG.DeleteNode(TheXor);
5798 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5799 MVT::Other, Chain, Tmp, N2);
5803 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) {
5805 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0))
5806 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() &&
5807 Op0.getOpcode() == ISD::XOR) {
5808 TheXor = Op0.getNode();
5812 EVT SetCCVT = N1.getValueType();
5814 SetCCVT = TLI.getSetCCResultType(SetCCVT);
5815 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(),
5818 Equal ? ISD::SETEQ : ISD::SETNE);
5819 // Replace the uses of XOR with SETCC
5820 WorkListRemover DeadNodes(*this);
5821 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes);
5822 removeFromWorkList(N1.getNode());
5823 DAG.DeleteNode(N1.getNode());
5824 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
5825 MVT::Other, Chain, SetCC, N2);
5832 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
5834 SDValue DAGCombiner::visitBR_CC(SDNode *N) {
5835 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
5836 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
5838 // If N is a constant we could fold this into a fallthrough or unconditional
5839 // branch. However that doesn't happen very often in normal code, because
5840 // Instcombine/SimplifyCFG should have handled the available opportunities.
5841 // If we did this folding here, it would be necessary to update the
5842 // MachineBasicBlock CFG, which is awkward.
5844 // Use SimplifySetCC to simplify SETCC's.
5845 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()),
5846 CondLHS, CondRHS, CC->get(), N->getDebugLoc(),
5848 if (Simp.getNode()) AddToWorkList(Simp.getNode());
5850 // fold to a simpler setcc
5851 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
5852 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
5853 N->getOperand(0), Simp.getOperand(2),
5854 Simp.getOperand(0), Simp.getOperand(1),
5860 /// CombineToPreIndexedLoadStore - Try turning a load / store into a
5861 /// pre-indexed load / store when the base pointer is an add or subtract
5862 /// and it has other uses besides the load / store. After the
5863 /// transformation, the new indexed load / store has effectively folded
5864 /// the add / subtract in and all of its other uses are redirected to the
5865 /// new load / store.
5866 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
5867 if (!LegalOperations)
5873 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5874 if (LD->isIndexed())
5876 VT = LD->getMemoryVT();
5877 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
5878 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
5880 Ptr = LD->getBasePtr();
5881 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5882 if (ST->isIndexed())
5884 VT = ST->getMemoryVT();
5885 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
5886 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
5888 Ptr = ST->getBasePtr();
5894 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
5895 // out. There is no reason to make this a preinc/predec.
5896 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
5897 Ptr.getNode()->hasOneUse())
5900 // Ask the target to do addressing mode selection.
5903 ISD::MemIndexedMode AM = ISD::UNINDEXED;
5904 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
5906 // Don't create a indexed load / store with zero offset.
5907 if (isa<ConstantSDNode>(Offset) &&
5908 cast<ConstantSDNode>(Offset)->isNullValue())
5911 // Try turning it into a pre-indexed load / store except when:
5912 // 1) The new base ptr is a frame index.
5913 // 2) If N is a store and the new base ptr is either the same as or is a
5914 // predecessor of the value being stored.
5915 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
5916 // that would create a cycle.
5917 // 4) All uses are load / store ops that use it as old base ptr.
5919 // Check #1. Preinc'ing a frame index would require copying the stack pointer
5920 // (plus the implicit offset) to a register to preinc anyway.
5921 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
5926 SDValue Val = cast<StoreSDNode>(N)->getValue();
5927 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode()))
5931 // Now check for #3 and #4.
5932 bool RealUse = false;
5934 // Caches for hasPredecessorHelper
5935 SmallPtrSet<const SDNode *, 32> Visited;
5936 SmallVector<const SDNode *, 16> Worklist;
5938 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
5939 E = Ptr.getNode()->use_end(); I != E; ++I) {
5943 if (N->hasPredecessorHelper(Use, Visited, Worklist))
5946 if (!((Use->getOpcode() == ISD::LOAD &&
5947 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
5948 (Use->getOpcode() == ISD::STORE &&
5949 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)))
5958 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
5959 BasePtr, Offset, AM);
5961 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
5962 BasePtr, Offset, AM);
5965 DEBUG(dbgs() << "\nReplacing.4 ";
5967 dbgs() << "\nWith: ";
5968 Result.getNode()->dump(&DAG);
5970 WorkListRemover DeadNodes(*this);
5972 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
5974 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
5977 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
5981 // Finally, since the node is now dead, remove it from the graph.
5984 // Replace the uses of Ptr with uses of the updated base value.
5985 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
5987 removeFromWorkList(Ptr.getNode());
5988 DAG.DeleteNode(Ptr.getNode());
5993 /// CombineToPostIndexedLoadStore - Try to combine a load / store with a
5994 /// add / sub of the base pointer node into a post-indexed load / store.
5995 /// The transformation folded the add / subtract into the new indexed
5996 /// load / store effectively and all of its uses are redirected to the
5997 /// new load / store.
5998 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
5999 if (!LegalOperations)
6005 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
6006 if (LD->isIndexed())
6008 VT = LD->getMemoryVT();
6009 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
6010 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
6012 Ptr = LD->getBasePtr();
6013 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
6014 if (ST->isIndexed())
6016 VT = ST->getMemoryVT();
6017 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
6018 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
6020 Ptr = ST->getBasePtr();
6026 if (Ptr.getNode()->hasOneUse())
6029 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(),
6030 E = Ptr.getNode()->use_end(); I != E; ++I) {
6033 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
6038 ISD::MemIndexedMode AM = ISD::UNINDEXED;
6039 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
6040 // Don't create a indexed load / store with zero offset.
6041 if (isa<ConstantSDNode>(Offset) &&
6042 cast<ConstantSDNode>(Offset)->isNullValue())
6045 // Try turning it into a post-indexed load / store except when
6046 // 1) All uses are load / store ops that use it as base ptr.
6047 // 2) Op must be independent of N, i.e. Op is neither a predecessor
6048 // nor a successor of N. Otherwise, if Op is folded that would
6051 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr))
6055 bool TryNext = false;
6056 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(),
6057 EE = BasePtr.getNode()->use_end(); II != EE; ++II) {
6059 if (Use == Ptr.getNode())
6062 // If all the uses are load / store addresses, then don't do the
6064 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
6065 bool RealUse = false;
6066 for (SDNode::use_iterator III = Use->use_begin(),
6067 EEE = Use->use_end(); III != EEE; ++III) {
6068 SDNode *UseUse = *III;
6069 if (!((UseUse->getOpcode() == ISD::LOAD &&
6070 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) ||
6071 (UseUse->getOpcode() == ISD::STORE &&
6072 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use)))
6087 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) {
6088 SDValue Result = isLoad
6089 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(),
6090 BasePtr, Offset, AM)
6091 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(),
6092 BasePtr, Offset, AM);
6095 DEBUG(dbgs() << "\nReplacing.5 ";
6097 dbgs() << "\nWith: ";
6098 Result.getNode()->dump(&DAG);
6100 WorkListRemover DeadNodes(*this);
6102 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0),
6104 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2),
6107 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1),
6111 // Finally, since the node is now dead, remove it from the graph.
6114 // Replace the uses of Use with uses of the updated base value.
6115 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0),
6116 Result.getValue(isLoad ? 1 : 0),
6118 removeFromWorkList(Op);
6128 SDValue DAGCombiner::visitLOAD(SDNode *N) {
6129 LoadSDNode *LD = cast<LoadSDNode>(N);
6130 SDValue Chain = LD->getChain();
6131 SDValue Ptr = LD->getBasePtr();
6133 // If load is not volatile and there are no uses of the loaded value (and
6134 // the updated indexed value in case of indexed loads), change uses of the
6135 // chain value into uses of the chain input (i.e. delete the dead load).
6136 if (!LD->isVolatile()) {
6137 if (N->getValueType(1) == MVT::Other) {
6139 if (N->hasNUsesOfValue(0, 0)) {
6140 // It's not safe to use the two value CombineTo variant here. e.g.
6141 // v1, chain2 = load chain1, loc
6142 // v2, chain3 = load chain2, loc
6144 // Now we replace use of chain2 with chain1. This makes the second load
6145 // isomorphic to the one we are deleting, and thus makes this load live.
6146 DEBUG(dbgs() << "\nReplacing.6 ";
6148 dbgs() << "\nWith chain: ";
6149 Chain.getNode()->dump(&DAG);
6151 WorkListRemover DeadNodes(*this);
6152 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes);
6154 if (N->use_empty()) {
6155 removeFromWorkList(N);
6159 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6163 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
6164 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
6165 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
6166 DEBUG(dbgs() << "\nReplacing.7 ";
6168 dbgs() << "\nWith: ";
6169 Undef.getNode()->dump(&DAG);
6170 dbgs() << " and 2 other values\n");
6171 WorkListRemover DeadNodes(*this);
6172 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes);
6173 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1),
6174 DAG.getUNDEF(N->getValueType(1)),
6176 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes);
6177 removeFromWorkList(N);
6179 return SDValue(N, 0); // Return N so it doesn't get rechecked!
6184 // If this load is directly stored, replace the load value with the stored
6186 // TODO: Handle store large -> read small portion.
6187 // TODO: Handle TRUNCSTORE/LOADEXT
6188 if (ISD::isNormalLoad(N) && !LD->isVolatile()) {
6189 if (ISD::isNON_TRUNCStore(Chain.getNode())) {
6190 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
6191 if (PrevST->getBasePtr() == Ptr &&
6192 PrevST->getValue().getValueType() == N->getValueType(0))
6193 return CombineTo(N, Chain.getOperand(1), Chain);
6197 // Try to infer better alignment information than the load already has.
6198 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) {
6199 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6200 if (Align > LD->getAlignment())
6201 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(),
6202 LD->getValueType(0),
6203 Chain, Ptr, LD->getPointerInfo(),
6205 LD->isVolatile(), LD->isNonTemporal(), Align);
6210 // Walk up chain skipping non-aliasing memory nodes.
6211 SDValue BetterChain = FindBetterChain(N, Chain);
6213 // If there is a better chain.
6214 if (Chain != BetterChain) {
6217 // Replace the chain to void dependency.
6218 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
6219 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(),
6220 BetterChain, Ptr, LD->getPointerInfo(),
6221 LD->isVolatile(), LD->isNonTemporal(),
6222 LD->getAlignment());
6224 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(),
6225 LD->getValueType(0),
6226 BetterChain, Ptr, LD->getPointerInfo(),
6229 LD->isNonTemporal(),
6230 LD->getAlignment());
6233 // Create token factor to keep old chain connected.
6234 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6235 MVT::Other, Chain, ReplLoad.getValue(1));
6237 // Make sure the new and old chains are cleaned up.
6238 AddToWorkList(Token.getNode());
6240 // Replace uses with load result and token factor. Don't add users
6242 return CombineTo(N, ReplLoad.getValue(0), Token, false);
6246 // Try transforming N to an indexed load.
6247 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6248 return SDValue(N, 0);
6253 /// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the
6254 /// load is having specific bytes cleared out. If so, return the byte size
6255 /// being masked out and the shift amount.
6256 static std::pair<unsigned, unsigned>
6257 CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) {
6258 std::pair<unsigned, unsigned> Result(0, 0);
6260 // Check for the structure we're looking for.
6261 if (V->getOpcode() != ISD::AND ||
6262 !isa<ConstantSDNode>(V->getOperand(1)) ||
6263 !ISD::isNormalLoad(V->getOperand(0).getNode()))
6266 // Check the chain and pointer.
6267 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0));
6268 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer.
6270 // The store should be chained directly to the load or be an operand of a
6272 if (LD == Chain.getNode())
6274 else if (Chain->getOpcode() != ISD::TokenFactor)
6275 return Result; // Fail.
6278 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i)
6279 if (Chain->getOperand(i).getNode() == LD) {
6283 if (!isOk) return Result;
6286 // This only handles simple types.
6287 if (V.getValueType() != MVT::i16 &&
6288 V.getValueType() != MVT::i32 &&
6289 V.getValueType() != MVT::i64)
6292 // Check the constant mask. Invert it so that the bits being masked out are
6293 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits
6294 // follow the sign bit for uniformity.
6295 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
6296 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask);
6297 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte.
6298 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask);
6299 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte.
6300 if (NotMaskLZ == 64) return Result; // All zero mask.
6302 // See if we have a continuous run of bits. If so, we have 0*1+0*
6303 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64)
6306 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64.
6307 if (V.getValueType() != MVT::i64 && NotMaskLZ)
6308 NotMaskLZ -= 64-V.getValueSizeInBits();
6310 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8;
6311 switch (MaskedBytes) {
6315 default: return Result; // All one mask, or 5-byte mask.
6318 // Verify that the first bit starts at a multiple of mask so that the access
6319 // is aligned the same as the access width.
6320 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result;
6322 Result.first = MaskedBytes;
6323 Result.second = NotMaskTZ/8;
6328 /// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that
6329 /// provides a value as specified by MaskInfo. If so, replace the specified
6330 /// store with a narrower store of truncated IVal.
6332 ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo,
6333 SDValue IVal, StoreSDNode *St,
6335 unsigned NumBytes = MaskInfo.first;
6336 unsigned ByteShift = MaskInfo.second;
6337 SelectionDAG &DAG = DC->getDAG();
6339 // Check to see if IVal is all zeros in the part being masked in by the 'or'
6340 // that uses this. If not, this is not a replacement.
6341 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(),
6342 ByteShift*8, (ByteShift+NumBytes)*8);
6343 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0;
6345 // Check that it is legal on the target to do this. It is legal if the new
6346 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type
6348 MVT VT = MVT::getIntegerVT(NumBytes*8);
6349 if (!DC->isTypeLegal(VT))
6352 // Okay, we can do this! Replace the 'St' store with a store of IVal that is
6353 // shifted by ByteShift and truncated down to NumBytes.
6355 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal,
6356 DAG.getConstant(ByteShift*8,
6357 DC->getShiftAmountTy(IVal.getValueType())));
6359 // Figure out the offset for the store and the alignment of the access.
6361 unsigned NewAlign = St->getAlignment();
6363 if (DAG.getTargetLoweringInfo().isLittleEndian())
6364 StOffset = ByteShift;
6366 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes;
6368 SDValue Ptr = St->getBasePtr();
6370 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(),
6371 Ptr, DAG.getConstant(StOffset, Ptr.getValueType()));
6372 NewAlign = MinAlign(NewAlign, StOffset);
6375 // Truncate down to the new size.
6376 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal);
6379 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr,
6380 St->getPointerInfo().getWithOffset(StOffset),
6381 false, false, NewAlign).getNode();
6385 /// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is
6386 /// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some
6387 /// of the loaded bits, try narrowing the load and store if it would end up
6388 /// being a win for performance or code size.
6389 SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
6390 StoreSDNode *ST = cast<StoreSDNode>(N);
6391 if (ST->isVolatile())
6394 SDValue Chain = ST->getChain();
6395 SDValue Value = ST->getValue();
6396 SDValue Ptr = ST->getBasePtr();
6397 EVT VT = Value.getValueType();
6399 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
6402 unsigned Opc = Value.getOpcode();
6404 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst
6405 // is a byte mask indicating a consecutive number of bytes, check to see if
6406 // Y is known to provide just those bytes. If so, we try to replace the
6407 // load + replace + store sequence with a single (narrower) store, which makes
6409 if (Opc == ISD::OR) {
6410 std::pair<unsigned, unsigned> MaskedLoad;
6411 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain);
6412 if (MaskedLoad.first)
6413 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6414 Value.getOperand(1), ST,this))
6415 return SDValue(NewST, 0);
6417 // Or is commutative, so try swapping X and Y.
6418 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain);
6419 if (MaskedLoad.first)
6420 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad,
6421 Value.getOperand(0), ST,this))
6422 return SDValue(NewST, 0);
6425 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) ||
6426 Value.getOperand(1).getOpcode() != ISD::Constant)
6429 SDValue N0 = Value.getOperand(0);
6430 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() &&
6431 Chain == SDValue(N0.getNode(), 1)) {
6432 LoadSDNode *LD = cast<LoadSDNode>(N0);
6433 if (LD->getBasePtr() != Ptr ||
6434 LD->getPointerInfo().getAddrSpace() !=
6435 ST->getPointerInfo().getAddrSpace())
6438 // Find the type to narrow it the load / op / store to.
6439 SDValue N1 = Value.getOperand(1);
6440 unsigned BitWidth = N1.getValueSizeInBits();
6441 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
6442 if (Opc == ISD::AND)
6443 Imm ^= APInt::getAllOnesValue(BitWidth);
6444 if (Imm == 0 || Imm.isAllOnesValue())
6446 unsigned ShAmt = Imm.countTrailingZeros();
6447 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
6448 unsigned NewBW = NextPowerOf2(MSB - ShAmt);
6449 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6450 while (NewBW < BitWidth &&
6451 !(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
6452 TLI.isNarrowingProfitable(VT, NewVT))) {
6453 NewBW = NextPowerOf2(NewBW);
6454 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW);
6456 if (NewBW >= BitWidth)
6459 // If the lsb changed does not start at the type bitwidth boundary,
6460 // start at the previous one.
6462 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW;
6463 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW);
6464 if ((Imm & Mask) == Imm) {
6465 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW);
6466 if (Opc == ISD::AND)
6467 NewImm ^= APInt::getAllOnesValue(NewBW);
6468 uint64_t PtrOff = ShAmt / 8;
6469 // For big endian targets, we need to adjust the offset to the pointer to
6470 // load the correct bytes.
6471 if (TLI.isBigEndian())
6472 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff;
6474 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
6475 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext());
6476 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy))
6479 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
6480 Ptr.getValueType(), Ptr,
6481 DAG.getConstant(PtrOff, Ptr.getValueType()));
6482 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(),
6483 LD->getChain(), NewPtr,
6484 LD->getPointerInfo().getWithOffset(PtrOff),
6485 LD->isVolatile(), LD->isNonTemporal(),
6487 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD,
6488 DAG.getConstant(NewImm, NewVT));
6489 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(),
6491 ST->getPointerInfo().getWithOffset(PtrOff),
6492 false, false, NewAlign);
6494 AddToWorkList(NewPtr.getNode());
6495 AddToWorkList(NewLD.getNode());
6496 AddToWorkList(NewVal.getNode());
6497 WorkListRemover DeadNodes(*this);
6498 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1),
6508 /// TransformFPLoadStorePair - For a given floating point load / store pair,
6509 /// if the load value isn't used by any other operations, then consider
6510 /// transforming the pair to integer load / store operations if the target
6511 /// deems the transformation profitable.
6512 SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
6513 StoreSDNode *ST = cast<StoreSDNode>(N);
6514 SDValue Chain = ST->getChain();
6515 SDValue Value = ST->getValue();
6516 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) &&
6517 Value.hasOneUse() &&
6518 Chain == SDValue(Value.getNode(), 1)) {
6519 LoadSDNode *LD = cast<LoadSDNode>(Value);
6520 EVT VT = LD->getMemoryVT();
6521 if (!VT.isFloatingPoint() ||
6522 VT != ST->getMemoryVT() ||
6523 LD->isNonTemporal() ||
6524 ST->isNonTemporal() ||
6525 LD->getPointerInfo().getAddrSpace() != 0 ||
6526 ST->getPointerInfo().getAddrSpace() != 0)
6529 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
6530 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
6531 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
6532 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
6533 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
6536 unsigned LDAlign = LD->getAlignment();
6537 unsigned STAlign = ST->getAlignment();
6538 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext());
6539 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy);
6540 if (LDAlign < ABIAlign || STAlign < ABIAlign)
6543 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(),
6544 LD->getChain(), LD->getBasePtr(),
6545 LD->getPointerInfo(),
6546 false, false, LDAlign);
6548 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(),
6549 NewLD, ST->getBasePtr(),
6550 ST->getPointerInfo(),
6551 false, false, STAlign);
6553 AddToWorkList(NewLD.getNode());
6554 AddToWorkList(NewST.getNode());
6555 WorkListRemover DeadNodes(*this);
6556 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1),
6565 SDValue DAGCombiner::visitSTORE(SDNode *N) {
6566 StoreSDNode *ST = cast<StoreSDNode>(N);
6567 SDValue Chain = ST->getChain();
6568 SDValue Value = ST->getValue();
6569 SDValue Ptr = ST->getBasePtr();
6571 // If this is a store of a bit convert, store the input value if the
6572 // resultant store does not need a higher alignment than the original.
6573 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() &&
6574 ST->isUnindexed()) {
6575 unsigned OrigAlign = ST->getAlignment();
6576 EVT SVT = Value.getOperand(0).getValueType();
6577 unsigned Align = TLI.getTargetData()->
6578 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext()));
6579 if (Align <= OrigAlign &&
6580 ((!LegalOperations && !ST->isVolatile()) ||
6581 TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
6582 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6583 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6584 ST->isNonTemporal(), OrigAlign);
6587 // Turn 'store undef, Ptr' -> nothing.
6588 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed())
6591 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
6592 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
6593 // NOTE: If the original store is volatile, this transform must not increase
6594 // the number of stores. For example, on x86-32 an f64 can be stored in one
6595 // processor operation but an i64 (which is not legal) requires two. So the
6596 // transform should not be done in this case.
6597 if (Value.getOpcode() != ISD::TargetConstantFP) {
6599 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
6600 default: llvm_unreachable("Unknown FP type");
6601 case MVT::f80: // We don't do this for these yet.
6606 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) ||
6607 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6608 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
6609 bitcastToAPInt().getZExtValue(), MVT::i32);
6610 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6611 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6612 ST->isNonTemporal(), ST->getAlignment());
6616 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations &&
6617 !ST->isVolatile()) ||
6618 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
6619 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
6620 getZExtValue(), MVT::i64);
6621 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
6622 Ptr, ST->getPointerInfo(), ST->isVolatile(),
6623 ST->isNonTemporal(), ST->getAlignment());
6626 if (!ST->isVolatile() &&
6627 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
6628 // Many FP stores are not made apparent until after legalize, e.g. for
6629 // argument passing. Since this is so common, custom legalize the
6630 // 64-bit integer store into two 32-bit stores.
6631 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
6632 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
6633 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
6634 if (TLI.isBigEndian()) std::swap(Lo, Hi);
6636 unsigned Alignment = ST->getAlignment();
6637 bool isVolatile = ST->isVolatile();
6638 bool isNonTemporal = ST->isNonTemporal();
6640 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo,
6641 Ptr, ST->getPointerInfo(),
6642 isVolatile, isNonTemporal,
6643 ST->getAlignment());
6644 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr,
6645 DAG.getConstant(4, Ptr.getValueType()));
6646 Alignment = MinAlign(Alignment, 4U);
6647 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
6648 Ptr, ST->getPointerInfo().getWithOffset(4),
6649 isVolatile, isNonTemporal,
6651 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
6660 // Try to infer better alignment information than the store already has.
6661 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) {
6662 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) {
6663 if (Align > ST->getAlignment())
6664 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value,
6665 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6666 ST->isVolatile(), ST->isNonTemporal(), Align);
6670 // Try transforming a pair floating point load / store ops to integer
6671 // load / store ops.
6672 SDValue NewST = TransformFPLoadStorePair(N);
6673 if (NewST.getNode())
6677 // Walk up chain skipping non-aliasing memory nodes.
6678 SDValue BetterChain = FindBetterChain(N, Chain);
6680 // If there is a better chain.
6681 if (Chain != BetterChain) {
6684 // Replace the chain to avoid dependency.
6685 if (ST->isTruncatingStore()) {
6686 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6687 ST->getPointerInfo(),
6688 ST->getMemoryVT(), ST->isVolatile(),
6689 ST->isNonTemporal(), ST->getAlignment());
6691 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr,
6692 ST->getPointerInfo(),
6693 ST->isVolatile(), ST->isNonTemporal(),
6694 ST->getAlignment());
6697 // Create token to keep both nodes around.
6698 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
6699 MVT::Other, Chain, ReplStore);
6701 // Make sure the new and old chains are cleaned up.
6702 AddToWorkList(Token.getNode());
6704 // Don't add users to work list.
6705 return CombineTo(N, Token, false);
6709 // Try transforming N to an indexed store.
6710 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
6711 return SDValue(N, 0);
6713 // FIXME: is there such a thing as a truncating indexed store?
6714 if (ST->isTruncatingStore() && ST->isUnindexed() &&
6715 Value.getValueType().isInteger()) {
6716 // See if we can simplify the input to this truncstore with knowledge that
6717 // only the low bits are being used. For example:
6718 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
6720 GetDemandedBits(Value,
6721 APInt::getLowBitsSet(
6722 Value.getValueType().getScalarType().getSizeInBits(),
6723 ST->getMemoryVT().getScalarType().getSizeInBits()));
6724 AddToWorkList(Value.getNode());
6725 if (Shorter.getNode())
6726 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter,
6727 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6728 ST->isVolatile(), ST->isNonTemporal(),
6729 ST->getAlignment());
6731 // Otherwise, see if we can simplify the operation with
6732 // SimplifyDemandedBits, which only works if the value has a single use.
6733 if (SimplifyDemandedBits(Value,
6734 APInt::getLowBitsSet(
6735 Value.getValueType().getScalarType().getSizeInBits(),
6736 ST->getMemoryVT().getScalarType().getSizeInBits())))
6737 return SDValue(N, 0);
6740 // If this is a load followed by a store to the same location, then the store
6742 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) {
6743 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
6744 ST->isUnindexed() && !ST->isVolatile() &&
6745 // There can't be any side effects between the load and store, such as
6747 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
6748 // The store is dead, remove it.
6753 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a
6754 // truncating store. We can do this even if this is already a truncstore.
6755 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE)
6756 && Value.getNode()->hasOneUse() && ST->isUnindexed() &&
6757 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(),
6758 ST->getMemoryVT())) {
6759 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0),
6760 Ptr, ST->getPointerInfo(), ST->getMemoryVT(),
6761 ST->isVolatile(), ST->isNonTemporal(),
6762 ST->getAlignment());
6765 return ReduceLoadOpStoreWidth(N);
6768 SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
6769 SDValue InVec = N->getOperand(0);
6770 SDValue InVal = N->getOperand(1);
6771 SDValue EltNo = N->getOperand(2);
6772 DebugLoc dl = N->getDebugLoc();
6774 // If the inserted element is an UNDEF, just use the input vector.
6775 if (InVal.getOpcode() == ISD::UNDEF)
6778 EVT VT = InVec.getValueType();
6780 // If we can't generate a legal BUILD_VECTOR, exit
6781 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT))
6784 // Check that we know which element is being inserted
6785 if (!isa<ConstantSDNode>(EltNo))
6787 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6789 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
6790 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the
6792 SmallVector<SDValue, 8> Ops;
6793 if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
6794 Ops.append(InVec.getNode()->op_begin(),
6795 InVec.getNode()->op_end());
6796 } else if (InVec.getOpcode() == ISD::UNDEF) {
6797 unsigned NElts = VT.getVectorNumElements();
6798 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType()));
6803 // Insert the element
6804 if (Elt < Ops.size()) {
6805 // All the operands of BUILD_VECTOR must have the same type;
6806 // we enforce that here.
6807 EVT OpVT = Ops[0].getValueType();
6808 if (InVal.getValueType() != OpVT)
6809 InVal = OpVT.bitsGT(InVal.getValueType()) ?
6810 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) :
6811 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal);
6815 // Return the new vector
6816 return DAG.getNode(ISD::BUILD_VECTOR, dl,
6817 VT, &Ops[0], Ops.size());
6820 SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
6821 // (vextract (scalar_to_vector val, 0) -> val
6822 SDValue InVec = N->getOperand(0);
6824 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
6825 // Check if the result type doesn't match the inserted element type. A
6826 // SCALAR_TO_VECTOR may truncate the inserted element and the
6827 // EXTRACT_VECTOR_ELT may widen the extracted vector.
6828 SDValue InOp = InVec.getOperand(0);
6829 EVT NVT = N->getValueType(0);
6830 if (InOp.getValueType() != NVT) {
6831 assert(InOp.getValueType().isInteger() && NVT.isInteger());
6832 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT);
6837 // Perform only after legalization to ensure build_vector / vector_shuffle
6838 // optimizations have already been done.
6839 if (!LegalOperations) return SDValue();
6841 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
6842 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
6843 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
6844 SDValue EltNo = N->getOperand(1);
6846 if (isa<ConstantSDNode>(EltNo)) {
6847 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
6848 bool NewLoad = false;
6849 bool BCNumEltsChanged = false;
6850 EVT VT = InVec.getValueType();
6851 EVT ExtVT = VT.getVectorElementType();
6854 if (InVec.getOpcode() == ISD::BITCAST) {
6855 EVT BCVT = InVec.getOperand(0).getValueType();
6856 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
6858 if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
6859 BCNumEltsChanged = true;
6860 InVec = InVec.getOperand(0);
6861 ExtVT = BCVT.getVectorElementType();
6865 LoadSDNode *LN0 = NULL;
6866 const ShuffleVectorSDNode *SVN = NULL;
6867 if (ISD::isNormalLoad(InVec.getNode())) {
6868 LN0 = cast<LoadSDNode>(InVec);
6869 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
6870 InVec.getOperand(0).getValueType() == ExtVT &&
6871 ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
6872 LN0 = cast<LoadSDNode>(InVec.getOperand(0));
6873 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
6874 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1)
6876 // (load $addr+1*size)
6878 // If the bit convert changed the number of elements, it is unsafe
6879 // to examine the mask.
6880 if (BCNumEltsChanged)
6883 // Select the input vector, guarding against out of range extract vector.
6884 unsigned NumElems = VT.getVectorNumElements();
6885 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt);
6886 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1);
6888 if (InVec.getOpcode() == ISD::BITCAST)
6889 InVec = InVec.getOperand(0);
6890 if (ISD::isNormalLoad(InVec.getNode())) {
6891 LN0 = cast<LoadSDNode>(InVec);
6892 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems;
6896 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile())
6899 // If Idx was -1 above, Elt is going to be -1, so just return undef.
6901 return DAG.getUNDEF(LVT);
6903 unsigned Align = LN0->getAlignment();
6905 // Check the resultant load doesn't need a higher alignment than the
6909 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext()));
6911 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
6917 SDValue NewPtr = LN0->getBasePtr();
6918 unsigned PtrOff = 0;
6921 PtrOff = LVT.getSizeInBits() * Elt / 8;
6922 EVT PtrType = NewPtr.getValueType();
6923 if (TLI.isBigEndian())
6924 PtrOff = VT.getSizeInBits() / 8 - PtrOff;
6925 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
6926 DAG.getConstant(PtrOff, PtrType));
6929 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr,
6930 LN0->getPointerInfo().getWithOffset(PtrOff),
6931 LN0->isVolatile(), LN0->isNonTemporal(), Align);
6937 SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
6938 unsigned NumInScalars = N->getNumOperands();
6939 DebugLoc dl = N->getDebugLoc();
6940 EVT VT = N->getValueType(0);
6941 // Check to see if this is a BUILD_VECTOR of a bunch of values
6942 // which come from any_extend or zero_extend nodes. If so, we can create
6943 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR
6944 // optimizations. We do not handle sign-extend because we can't fill the sign
6946 EVT SourceType = MVT::Other;
6947 bool allAnyExt = true;
6948 for (unsigned i = 0; i < NumInScalars; ++i) {
6949 SDValue In = N->getOperand(i);
6950 // Ignore undef inputs.
6951 if (In.getOpcode() == ISD::UNDEF) continue;
6953 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND;
6954 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND;
6956 // Abort if the element is not an extension.
6957 if (!ZeroExt && !AnyExt) {
6958 SourceType = MVT::Other;
6962 // The input is a ZeroExt or AnyExt. Check the original type.
6963 EVT InTy = In.getOperand(0).getValueType();
6965 // Check that all of the widened source types are the same.
6966 if (SourceType == MVT::Other)
6969 else if (InTy != SourceType) {
6970 // Multiple income types. Abort.
6971 SourceType = MVT::Other;
6975 // Check if all of the extends are ANY_EXTENDs.
6976 allAnyExt &= AnyExt;
6980 // In order to have valid types, all of the inputs must be extended from the
6981 // same source type and all of the inputs must be any or zero extend.
6982 // Scalar sizes must be a power of two.
6983 EVT OutScalarTy = N->getValueType(0).getScalarType();
6984 bool validTypes = SourceType != MVT::Other &&
6985 isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
6986 isPowerOf2_32(SourceType.getSizeInBits());
6988 // We perform this optimization post type-legalization because
6989 // the type-legalizer often scalarizes integer-promoted vectors.
6990 // Performing this optimization before may create bit-casts which
6991 // will be type-legalized to complex code sequences.
6992 // We perform this optimization only before the operation legalizer because we
6993 // may introduce illegal operations.
6994 if (LegalTypes && !LegalOperations && validTypes) {
6995 bool isLE = TLI.isLittleEndian();
6996 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits();
6997 assert(ElemRatio > 1 && "Invalid element size ratio");
6998 SDValue Filler = allAnyExt ? DAG.getUNDEF(SourceType):
6999 DAG.getConstant(0, SourceType);
7001 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements();
7002 SmallVector<SDValue, 8> Ops(NewBVElems, Filler);
7004 // Populate the new build_vector
7005 for (unsigned i=0; i < N->getNumOperands(); ++i) {
7006 SDValue Cast = N->getOperand(i);
7007 assert((Cast.getOpcode() == ISD::ANY_EXTEND ||
7008 Cast.getOpcode() == ISD::ZERO_EXTEND ||
7009 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode");
7011 if (Cast.getOpcode() == ISD::UNDEF)
7012 In = DAG.getUNDEF(SourceType);
7014 In = Cast->getOperand(0);
7015 unsigned Index = isLE ? (i * ElemRatio) :
7016 (i * ElemRatio + (ElemRatio - 1));
7018 assert(Index < Ops.size() && "Invalid index");
7022 // The type of the new BUILD_VECTOR node.
7023 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems);
7024 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() &&
7025 "Invalid vector size");
7026 // Check if the new vector type is legal.
7027 if (!isTypeLegal(VecVT)) return SDValue();
7029 // Make the new BUILD_VECTOR.
7030 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7031 VecVT, &Ops[0], Ops.size());
7033 // Bitcast to the desired type.
7034 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV);
7037 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
7038 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
7039 // at most two distinct vectors, turn this into a shuffle node.
7040 SDValue VecIn1, VecIn2;
7041 for (unsigned i = 0; i != NumInScalars; ++i) {
7042 // Ignore undef inputs.
7043 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
7045 // If this input is something other than a EXTRACT_VECTOR_ELT with a
7046 // constant index, bail out.
7047 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
7048 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
7049 VecIn1 = VecIn2 = SDValue(0, 0);
7053 // If the input vector type disagrees with the result of the build_vector,
7054 // we can't make a shuffle.
7055 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0);
7056 if (ExtractedFromVec.getValueType() != VT) {
7057 VecIn1 = VecIn2 = SDValue(0, 0);
7061 // Otherwise, remember this. We allow up to two distinct input vectors.
7062 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
7065 if (VecIn1.getNode() == 0) {
7066 VecIn1 = ExtractedFromVec;
7067 } else if (VecIn2.getNode() == 0) {
7068 VecIn2 = ExtractedFromVec;
7071 VecIn1 = VecIn2 = SDValue(0, 0);
7076 // If everything is good, we can make a shuffle operation.
7077 if (VecIn1.getNode()) {
7078 SmallVector<int, 8> Mask;
7079 for (unsigned i = 0; i != NumInScalars; ++i) {
7080 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
7085 // If extracting from the first vector, just use the index directly.
7086 SDValue Extract = N->getOperand(i);
7087 SDValue ExtVal = Extract.getOperand(1);
7088 if (Extract.getOperand(0) == VecIn1) {
7089 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7090 if (ExtIndex > VT.getVectorNumElements())
7093 Mask.push_back(ExtIndex);
7097 // Otherwise, use InIdx + VecSize
7098 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue();
7099 Mask.push_back(Idx+NumInScalars);
7102 // Add count and size info.
7103 if (!isTypeLegal(VT))
7106 // Return the new VECTOR_SHUFFLE node.
7109 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT);
7110 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]);
7116 SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
7117 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
7118 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector
7119 // inputs come from at most two distinct vectors, turn this into a shuffle
7122 // If we only have one input vector, we don't need to do any concatenation.
7123 if (N->getNumOperands() == 1)
7124 return N->getOperand(0);
7129 SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
7130 EVT NVT = N->getValueType(0);
7131 SDValue V = N->getOperand(0);
7133 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) {
7134 // Handle only simple case where vector being inserted and vector
7135 // being extracted are of same type, and are half size of larger vectors.
7136 EVT BigVT = V->getOperand(0).getValueType();
7137 EVT SmallVT = V->getOperand(1).getValueType();
7138 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits())
7142 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx)
7144 // indicies are equal => V1
7145 // otherwise => (extract_subvec V1, ExtIdx)
7147 SDValue InsIdx = N->getOperand(1);
7148 SDValue ExtIdx = V->getOperand(2);
7150 if (InsIdx == ExtIdx)
7151 return V->getOperand(1);
7152 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT,
7153 V->getOperand(0), N->getOperand(1));
7159 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
7160 EVT VT = N->getValueType(0);
7161 unsigned NumElts = VT.getVectorNumElements();
7163 SDValue N0 = N->getOperand(0);
7165 assert(N0.getValueType().getVectorNumElements() == NumElts &&
7166 "Vector shuffle must be normalized in DAG");
7168 // FIXME: implement canonicalizations from DAG.getVectorShuffle()
7170 // If it is a splat, check if the argument vector is another splat or a
7171 // build_vector with all scalar elements the same.
7172 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7173 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) {
7174 SDNode *V = N0.getNode();
7176 // If this is a bit convert that changes the element type of the vector but
7177 // not the number of vector elements, look through it. Be careful not to
7178 // look though conversions that change things like v4f32 to v2f64.
7179 if (V->getOpcode() == ISD::BITCAST) {
7180 SDValue ConvInput = V->getOperand(0);
7181 if (ConvInput.getValueType().isVector() &&
7182 ConvInput.getValueType().getVectorNumElements() == NumElts)
7183 V = ConvInput.getNode();
7186 if (V->getOpcode() == ISD::BUILD_VECTOR) {
7187 assert(V->getNumOperands() == NumElts &&
7188 "BUILD_VECTOR has wrong number of operands");
7190 bool AllSame = true;
7191 for (unsigned i = 0; i != NumElts; ++i) {
7192 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
7193 Base = V->getOperand(i);
7197 // Splat of <u, u, u, u>, return <u, u, u, u>
7198 if (!Base.getNode())
7200 for (unsigned i = 0; i != NumElts; ++i) {
7201 if (V->getOperand(i) != Base) {
7206 // Splat of <x, x, x, x>, return <x, x, x, x>
7214 SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) {
7215 if (!TLI.getShouldFoldAtomicFences())
7218 SDValue atomic = N->getOperand(0);
7219 switch (atomic.getOpcode()) {
7220 case ISD::ATOMIC_CMP_SWAP:
7221 case ISD::ATOMIC_SWAP:
7222 case ISD::ATOMIC_LOAD_ADD:
7223 case ISD::ATOMIC_LOAD_SUB:
7224 case ISD::ATOMIC_LOAD_AND:
7225 case ISD::ATOMIC_LOAD_OR:
7226 case ISD::ATOMIC_LOAD_XOR:
7227 case ISD::ATOMIC_LOAD_NAND:
7228 case ISD::ATOMIC_LOAD_MIN:
7229 case ISD::ATOMIC_LOAD_MAX:
7230 case ISD::ATOMIC_LOAD_UMIN:
7231 case ISD::ATOMIC_LOAD_UMAX:
7237 SDValue fence = atomic.getOperand(0);
7238 if (fence.getOpcode() != ISD::MEMBARRIER)
7241 switch (atomic.getOpcode()) {
7242 case ISD::ATOMIC_CMP_SWAP:
7243 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7244 fence.getOperand(0),
7245 atomic.getOperand(1), atomic.getOperand(2),
7246 atomic.getOperand(3)), atomic.getResNo());
7247 case ISD::ATOMIC_SWAP:
7248 case ISD::ATOMIC_LOAD_ADD:
7249 case ISD::ATOMIC_LOAD_SUB:
7250 case ISD::ATOMIC_LOAD_AND:
7251 case ISD::ATOMIC_LOAD_OR:
7252 case ISD::ATOMIC_LOAD_XOR:
7253 case ISD::ATOMIC_LOAD_NAND:
7254 case ISD::ATOMIC_LOAD_MIN:
7255 case ISD::ATOMIC_LOAD_MAX:
7256 case ISD::ATOMIC_LOAD_UMIN:
7257 case ISD::ATOMIC_LOAD_UMAX:
7258 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
7259 fence.getOperand(0),
7260 atomic.getOperand(1), atomic.getOperand(2)),
7267 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
7268 /// an AND to a vector_shuffle with the destination vector and a zero vector.
7269 /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
7270 /// vector_shuffle V, Zero, <0, 4, 2, 4>
7271 SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
7272 EVT VT = N->getValueType(0);
7273 DebugLoc dl = N->getDebugLoc();
7274 SDValue LHS = N->getOperand(0);
7275 SDValue RHS = N->getOperand(1);
7276 if (N->getOpcode() == ISD::AND) {
7277 if (RHS.getOpcode() == ISD::BITCAST)
7278 RHS = RHS.getOperand(0);
7279 if (RHS.getOpcode() == ISD::BUILD_VECTOR) {
7280 SmallVector<int, 8> Indices;
7281 unsigned NumElts = RHS.getNumOperands();
7282 for (unsigned i = 0; i != NumElts; ++i) {
7283 SDValue Elt = RHS.getOperand(i);
7284 if (!isa<ConstantSDNode>(Elt))
7286 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
7287 Indices.push_back(i);
7288 else if (cast<ConstantSDNode>(Elt)->isNullValue())
7289 Indices.push_back(NumElts);
7294 // Let's see if the target supports this vector_shuffle.
7295 EVT RVT = RHS.getValueType();
7296 if (!TLI.isVectorClearMaskLegal(Indices, RVT))
7299 // Return the new VECTOR_SHUFFLE node.
7300 EVT EltVT = RVT.getVectorElementType();
7301 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
7302 DAG.getConstant(0, EltVT));
7303 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7304 RVT, &ZeroOps[0], ZeroOps.size());
7305 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS);
7306 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]);
7307 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf);
7314 /// SimplifyVBinOp - Visit a binary vector operation, like ADD.
7315 SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) {
7316 // After legalize, the target may be depending on adds and other
7317 // binary ops to provide legal ways to construct constants or other
7318 // things. Simplifying them may result in a loss of legality.
7319 if (LegalOperations) return SDValue();
7321 assert(N->getValueType(0).isVector() &&
7322 "SimplifyVBinOp only works on vectors!");
7324 SDValue LHS = N->getOperand(0);
7325 SDValue RHS = N->getOperand(1);
7326 SDValue Shuffle = XformToShuffleWithZero(N);
7327 if (Shuffle.getNode()) return Shuffle;
7329 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold
7331 if (LHS.getOpcode() == ISD::BUILD_VECTOR &&
7332 RHS.getOpcode() == ISD::BUILD_VECTOR) {
7333 SmallVector<SDValue, 8> Ops;
7334 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) {
7335 SDValue LHSOp = LHS.getOperand(i);
7336 SDValue RHSOp = RHS.getOperand(i);
7337 // If these two elements can't be folded, bail out.
7338 if ((LHSOp.getOpcode() != ISD::UNDEF &&
7339 LHSOp.getOpcode() != ISD::Constant &&
7340 LHSOp.getOpcode() != ISD::ConstantFP) ||
7341 (RHSOp.getOpcode() != ISD::UNDEF &&
7342 RHSOp.getOpcode() != ISD::Constant &&
7343 RHSOp.getOpcode() != ISD::ConstantFP))
7346 // Can't fold divide by zero.
7347 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV ||
7348 N->getOpcode() == ISD::FDIV) {
7349 if ((RHSOp.getOpcode() == ISD::Constant &&
7350 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) ||
7351 (RHSOp.getOpcode() == ISD::ConstantFP &&
7352 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero()))
7356 EVT VT = LHSOp.getValueType();
7357 EVT RVT = RHSOp.getValueType();
7359 // Integer BUILD_VECTOR operands may have types larger than the element
7360 // size (e.g., when the element type is not legal). Prior to type
7361 // legalization, the types may not match between the two BUILD_VECTORS.
7362 // Truncate one of the operands to make them match.
7363 if (RVT.getSizeInBits() > VT.getSizeInBits()) {
7364 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp);
7366 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp);
7370 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT,
7372 if (FoldOp.getOpcode() != ISD::UNDEF &&
7373 FoldOp.getOpcode() != ISD::Constant &&
7374 FoldOp.getOpcode() != ISD::ConstantFP)
7376 Ops.push_back(FoldOp);
7377 AddToWorkList(FoldOp.getNode());
7380 if (Ops.size() == LHS.getNumOperands())
7381 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
7382 LHS.getValueType(), &Ops[0], Ops.size());
7388 SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0,
7389 SDValue N1, SDValue N2){
7390 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
7392 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2,
7393 cast<CondCodeSDNode>(N0.getOperand(2))->get());
7395 // If we got a simplified select_cc node back from SimplifySelectCC, then
7396 // break it down into a new SETCC node, and a new SELECT node, and then return
7397 // the SELECT node, since we were called with a SELECT node.
7398 if (SCC.getNode()) {
7399 // Check to see if we got a select_cc back (to turn into setcc/select).
7400 // Otherwise, just return whatever node we got back, like fabs.
7401 if (SCC.getOpcode() == ISD::SELECT_CC) {
7402 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(),
7404 SCC.getOperand(0), SCC.getOperand(1),
7406 AddToWorkList(SETCC.getNode());
7407 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(),
7408 SCC.getOperand(2), SCC.getOperand(3), SETCC);
7416 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
7417 /// are the two values being selected between, see if we can simplify the
7418 /// select. Callers of this should assume that TheSelect is deleted if this
7419 /// returns true. As such, they should return the appropriate thing (e.g. the
7420 /// node) back to the top-level of the DAG combiner loop to avoid it being
7422 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
7425 // Cannot simplify select with vector condition
7426 if (TheSelect->getOperand(0).getValueType().isVector()) return false;
7428 // If this is a select from two identical things, try to pull the operation
7429 // through the select.
7430 if (LHS.getOpcode() != RHS.getOpcode() ||
7431 !LHS.hasOneUse() || !RHS.hasOneUse())
7434 // If this is a load and the token chain is identical, replace the select
7435 // of two loads with a load through a select of the address to load from.
7436 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
7437 // constants have been dropped into the constant pool.
7438 if (LHS.getOpcode() == ISD::LOAD) {
7439 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
7440 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
7442 // Token chains must be identical.
7443 if (LHS.getOperand(0) != RHS.getOperand(0) ||
7444 // Do not let this transformation reduce the number of volatile loads.
7445 LLD->isVolatile() || RLD->isVolatile() ||
7446 // If this is an EXTLOAD, the VT's must match.
7447 LLD->getMemoryVT() != RLD->getMemoryVT() ||
7448 // If this is an EXTLOAD, the kind of extension must match.
7449 (LLD->getExtensionType() != RLD->getExtensionType() &&
7450 // The only exception is if one of the extensions is anyext.
7451 LLD->getExtensionType() != ISD::EXTLOAD &&
7452 RLD->getExtensionType() != ISD::EXTLOAD) ||
7453 // FIXME: this discards src value information. This is
7454 // over-conservative. It would be beneficial to be able to remember
7455 // both potential memory locations. Since we are discarding
7456 // src value info, don't do the transformation if the memory
7457 // locations are not in the default address space.
7458 LLD->getPointerInfo().getAddrSpace() != 0 ||
7459 RLD->getPointerInfo().getAddrSpace() != 0)
7462 // Check that the select condition doesn't reach either load. If so,
7463 // folding this will induce a cycle into the DAG. If not, this is safe to
7464 // xform, so create a select of the addresses.
7466 if (TheSelect->getOpcode() == ISD::SELECT) {
7467 SDNode *CondNode = TheSelect->getOperand(0).getNode();
7468 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) ||
7469 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode)))
7471 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
7472 LLD->getBasePtr().getValueType(),
7473 TheSelect->getOperand(0), LLD->getBasePtr(),
7475 } else { // Otherwise SELECT_CC
7476 SDNode *CondLHS = TheSelect->getOperand(0).getNode();
7477 SDNode *CondRHS = TheSelect->getOperand(1).getNode();
7479 if ((LLD->hasAnyUseOfValue(1) &&
7480 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) ||
7481 (LLD->hasAnyUseOfValue(1) &&
7482 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))))
7485 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
7486 LLD->getBasePtr().getValueType(),
7487 TheSelect->getOperand(0),
7488 TheSelect->getOperand(1),
7489 LLD->getBasePtr(), RLD->getBasePtr(),
7490 TheSelect->getOperand(4));
7494 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) {
7495 Load = DAG.getLoad(TheSelect->getValueType(0),
7496 TheSelect->getDebugLoc(),
7497 // FIXME: Discards pointer info.
7498 LLD->getChain(), Addr, MachinePointerInfo(),
7499 LLD->isVolatile(), LLD->isNonTemporal(),
7500 LLD->getAlignment());
7502 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ?
7503 RLD->getExtensionType() : LLD->getExtensionType(),
7504 TheSelect->getDebugLoc(),
7505 TheSelect->getValueType(0),
7506 // FIXME: Discards pointer info.
7507 LLD->getChain(), Addr, MachinePointerInfo(),
7508 LLD->getMemoryVT(), LLD->isVolatile(),
7509 LLD->isNonTemporal(), LLD->getAlignment());
7512 // Users of the select now use the result of the load.
7513 CombineTo(TheSelect, Load);
7515 // Users of the old loads now use the new load's chain. We know the
7516 // old-load value is dead now.
7517 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1));
7518 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1));
7525 /// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3
7526 /// where 'cond' is the comparison specified by CC.
7527 SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
7528 SDValue N2, SDValue N3,
7529 ISD::CondCode CC, bool NotExtCompare) {
7530 // (x ? y : y) -> y.
7531 if (N2 == N3) return N2;
7533 EVT VT = N2.getValueType();
7534 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
7535 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
7536 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
7538 // Determine if the condition we're dealing with is constant
7539 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()),
7540 N0, N1, CC, DL, false);
7541 if (SCC.getNode()) AddToWorkList(SCC.getNode());
7542 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode());
7544 // fold select_cc true, x, y -> x
7545 if (SCCC && !SCCC->isNullValue())
7547 // fold select_cc false, x, y -> y
7548 if (SCCC && SCCC->isNullValue())
7551 // Check to see if we can simplify the select into an fabs node
7552 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
7553 // Allow either -0.0 or 0.0
7554 if (CFP->getValueAPF().isZero()) {
7555 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
7556 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
7557 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
7558 N2 == N3.getOperand(0))
7559 return DAG.getNode(ISD::FABS, DL, VT, N0);
7561 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
7562 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
7563 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
7564 N2.getOperand(0) == N3)
7565 return DAG.getNode(ISD::FABS, DL, VT, N3);
7569 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)"
7570 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0
7571 // in it. This is a win when the constant is not otherwise available because
7572 // it replaces two constant pool loads with one. We only do this if the FP
7573 // type is known to be legal, because if it isn't, then we are before legalize
7574 // types an we want the other legalization to happen first (e.g. to avoid
7575 // messing with soft float) and if the ConstantFP is not legal, because if
7576 // it is legal, we may not need to store the FP constant in a constant pool.
7577 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2))
7578 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
7579 if (TLI.isTypeLegal(N2.getValueType()) &&
7580 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
7581 TargetLowering::Legal) &&
7582 // If both constants have multiple uses, then we won't need to do an
7583 // extra load, they are likely around in registers for other users.
7584 (TV->hasOneUse() || FV->hasOneUse())) {
7585 Constant *Elts[] = {
7586 const_cast<ConstantFP*>(FV->getConstantFPValue()),
7587 const_cast<ConstantFP*>(TV->getConstantFPValue())
7589 Type *FPTy = Elts[0]->getType();
7590 const TargetData &TD = *TLI.getTargetData();
7592 // Create a ConstantArray of the two constants.
7593 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
7594 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
7595 TD.getPrefTypeAlignment(FPTy));
7596 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
7598 // Get the offsets to the 0 and 1 element of the array so that we can
7599 // select between them.
7600 SDValue Zero = DAG.getIntPtrConstant(0);
7601 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType());
7602 SDValue One = DAG.getIntPtrConstant(EltSize);
7604 SDValue Cond = DAG.getSetCC(DL,
7605 TLI.getSetCCResultType(N0.getValueType()),
7607 AddToWorkList(Cond.getNode());
7608 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(),
7610 AddToWorkList(CstOffset.getNode());
7611 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx,
7613 AddToWorkList(CPIdx.getNode());
7614 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx,
7615 MachinePointerInfo::getConstantPool(), false,
7621 // Check to see if we can perform the "gzip trick", transforming
7622 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A)
7623 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
7624 (N1C->isNullValue() || // (a < 0) ? b : 0
7625 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
7626 EVT XType = N0.getValueType();
7627 EVT AType = N2.getValueType();
7628 if (XType.bitsGE(AType)) {
7629 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
7630 // single-bit constant.
7631 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
7632 unsigned ShCtV = N2C->getAPIntValue().logBase2();
7633 ShCtV = XType.getSizeInBits()-ShCtV-1;
7634 SDValue ShCt = DAG.getConstant(ShCtV,
7635 getShiftAmountTy(N0.getValueType()));
7636 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(),
7638 AddToWorkList(Shift.getNode());
7640 if (XType.bitsGT(AType)) {
7641 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7642 AddToWorkList(Shift.getNode());
7645 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7648 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(),
7650 DAG.getConstant(XType.getSizeInBits()-1,
7651 getShiftAmountTy(N0.getValueType())));
7652 AddToWorkList(Shift.getNode());
7654 if (XType.bitsGT(AType)) {
7655 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift);
7656 AddToWorkList(Shift.getNode());
7659 return DAG.getNode(ISD::AND, DL, AType, Shift, N2);
7663 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A)
7664 // where y is has a single bit set.
7665 // A plaintext description would be, we can turn the SELECT_CC into an AND
7666 // when the condition can be materialized as an all-ones register. Any
7667 // single bit-test can be materialized as an all-ones register with
7668 // shift-left and shift-right-arith.
7669 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
7670 N0->getValueType(0) == VT &&
7671 N1C && N1C->isNullValue() &&
7672 N2C && N2C->isNullValue()) {
7673 SDValue AndLHS = N0->getOperand(0);
7674 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
7675 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
7676 // Shift the tested bit over the sign bit.
7677 APInt AndMask = ConstAndRHS->getAPIntValue();
7679 DAG.getConstant(AndMask.countLeadingZeros(),
7680 getShiftAmountTy(AndLHS.getValueType()));
7681 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt);
7683 // Now arithmetic right shift it all the way over, so the result is either
7684 // all-ones, or zero.
7686 DAG.getConstant(AndMask.getBitWidth()-1,
7687 getShiftAmountTy(Shl.getValueType()));
7688 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt);
7690 return DAG.getNode(ISD::AND, DL, VT, Shr, N3);
7694 // fold select C, 16, 0 -> shl C, 4
7695 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() &&
7696 TLI.getBooleanContents(N0.getValueType().isVector()) ==
7697 TargetLowering::ZeroOrOneBooleanContent) {
7699 // If the caller doesn't want us to simplify this into a zext of a compare,
7701 if (NotExtCompare && N2C->getAPIntValue() == 1)
7704 // Get a SetCC of the condition
7705 // FIXME: Should probably make sure that setcc is legal if we ever have a
7706 // target where it isn't.
7708 // cast from setcc result type to select result type
7710 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()),
7712 if (N2.getValueType().bitsLT(SCC.getValueType()))
7713 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType());
7715 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7716 N2.getValueType(), SCC);
7718 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
7719 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
7720 N2.getValueType(), SCC);
7723 AddToWorkList(SCC.getNode());
7724 AddToWorkList(Temp.getNode());
7726 if (N2C->getAPIntValue() == 1)
7729 // shl setcc result by log2 n2c
7730 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
7731 DAG.getConstant(N2C->getAPIntValue().logBase2(),
7732 getShiftAmountTy(Temp.getValueType())));
7735 // Check to see if this is the equivalent of setcc
7736 // FIXME: Turn all of these into setcc if setcc if setcc is legal
7737 // otherwise, go ahead with the folds.
7738 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
7739 EVT XType = N0.getValueType();
7740 if (!LegalOperations ||
7741 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
7742 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
7743 if (Res.getValueType() != VT)
7744 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res);
7748 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X))))
7749 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
7750 (!LegalOperations ||
7751 TLI.isOperationLegal(ISD::CTLZ, XType))) {
7752 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0);
7753 return DAG.getNode(ISD::SRL, DL, XType, Ctlz,
7754 DAG.getConstant(Log2_32(XType.getSizeInBits()),
7755 getShiftAmountTy(Ctlz.getValueType())));
7757 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1))
7758 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
7759 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(),
7760 XType, DAG.getConstant(0, XType), N0);
7761 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType);
7762 return DAG.getNode(ISD::SRL, DL, XType,
7763 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0),
7764 DAG.getConstant(XType.getSizeInBits()-1,
7765 getShiftAmountTy(XType)));
7767 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1))
7768 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
7769 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0,
7770 DAG.getConstant(XType.getSizeInBits()-1,
7771 getShiftAmountTy(N0.getValueType())));
7772 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType));
7776 // Check to see if this is an integer abs.
7777 // select_cc setg[te] X, 0, X, -X ->
7778 // select_cc setgt X, -1, X, -X ->
7779 // select_cc setl[te] X, 0, -X, X ->
7780 // select_cc setlt X, 1, -X, X ->
7781 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
7783 ConstantSDNode *SubC = NULL;
7784 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
7785 (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
7786 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
7787 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
7788 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
7789 (N1C->isOne() && CC == ISD::SETLT)) &&
7790 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
7791 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
7793 EVT XType = N0.getValueType();
7794 if (SubC && SubC->isNullValue() && XType.isInteger()) {
7795 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
7797 DAG.getConstant(XType.getSizeInBits()-1,
7798 getShiftAmountTy(N0.getValueType())));
7799 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
7801 AddToWorkList(Shift.getNode());
7802 AddToWorkList(Add.getNode());
7803 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
7810 /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
7811 SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
7812 SDValue N1, ISD::CondCode Cond,
7813 DebugLoc DL, bool foldBooleans) {
7814 TargetLowering::DAGCombinerInfo
7815 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this);
7816 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL);
7819 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
7820 /// return a DAG expression to select that will generate the same value by
7821 /// multiplying by a magic number. See:
7822 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7823 SDValue DAGCombiner::BuildSDIV(SDNode *N) {
7824 std::vector<SDNode*> Built;
7825 SDValue S = TLI.BuildSDIV(N, DAG, &Built);
7827 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7833 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
7834 /// return a DAG expression to select that will generate the same value by
7835 /// multiplying by a magic number. See:
7836 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
7837 SDValue DAGCombiner::BuildUDIV(SDNode *N) {
7838 std::vector<SDNode*> Built;
7839 SDValue S = TLI.BuildUDIV(N, DAG, &Built);
7841 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
7847 /// FindBaseOffset - Return true if base is a frame index, which is known not
7848 // to alias with anything but itself. Provides base object and offset as
7850 static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset,
7851 const GlobalValue *&GV, void *&CV) {
7852 // Assume it is a primitive operation.
7853 Base = Ptr; Offset = 0; GV = 0; CV = 0;
7855 // If it's an adding a simple constant then integrate the offset.
7856 if (Base.getOpcode() == ISD::ADD) {
7857 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
7858 Base = Base.getOperand(0);
7859 Offset += C->getZExtValue();
7863 // Return the underlying GlobalValue, and update the Offset. Return false
7864 // for GlobalAddressSDNode since the same GlobalAddress may be represented
7865 // by multiple nodes with different offsets.
7866 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) {
7867 GV = G->getGlobal();
7868 Offset += G->getOffset();
7872 // Return the underlying Constant value, and update the Offset. Return false
7873 // for ConstantSDNodes since the same constant pool entry may be represented
7874 // by multiple nodes with different offsets.
7875 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
7876 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal()
7877 : (void *)C->getConstVal();
7878 Offset += C->getOffset();
7881 // If it's any of the following then it can't alias with anything but itself.
7882 return isa<FrameIndexSDNode>(Base);
7885 /// isAlias - Return true if there is any possibility that the two addresses
7887 bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1,
7888 const Value *SrcValue1, int SrcValueOffset1,
7889 unsigned SrcValueAlign1,
7890 const MDNode *TBAAInfo1,
7891 SDValue Ptr2, int64_t Size2,
7892 const Value *SrcValue2, int SrcValueOffset2,
7893 unsigned SrcValueAlign2,
7894 const MDNode *TBAAInfo2) const {
7895 // If they are the same then they must be aliases.
7896 if (Ptr1 == Ptr2) return true;
7898 // Gather base node and offset information.
7899 SDValue Base1, Base2;
7900 int64_t Offset1, Offset2;
7901 const GlobalValue *GV1, *GV2;
7903 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1);
7904 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2);
7906 // If they have a same base address then check to see if they overlap.
7907 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2)))
7908 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7910 // It is possible for different frame indices to alias each other, mostly
7911 // when tail call optimization reuses return address slots for arguments.
7912 // To catch this case, look up the actual index of frame indices to compute
7913 // the real alias relationship.
7914 if (isFrameIndex1 && isFrameIndex2) {
7915 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7916 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex());
7917 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex());
7918 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
7921 // Otherwise, if we know what the bases are, and they aren't identical, then
7922 // we know they cannot alias.
7923 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2))
7926 // If we know required SrcValue1 and SrcValue2 have relatively large alignment
7927 // compared to the size and offset of the access, we may be able to prove they
7928 // do not alias. This check is conservative for now to catch cases created by
7929 // splitting vector types.
7930 if ((SrcValueAlign1 == SrcValueAlign2) &&
7931 (SrcValueOffset1 != SrcValueOffset2) &&
7932 (Size1 == Size2) && (SrcValueAlign1 > Size1)) {
7933 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1;
7934 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1;
7936 // There is no overlap between these relatively aligned accesses of similar
7937 // size, return no alias.
7938 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1)
7942 if (CombinerGlobalAA) {
7943 // Use alias analysis information.
7944 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2);
7945 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset;
7946 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset;
7947 AliasAnalysis::AliasResult AAResult =
7948 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1),
7949 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2));
7950 if (AAResult == AliasAnalysis::NoAlias)
7954 // Otherwise we have to assume they alias.
7958 /// FindAliasInfo - Extracts the relevant alias information from the memory
7959 /// node. Returns true if the operand was a load.
7960 bool DAGCombiner::FindAliasInfo(SDNode *N,
7961 SDValue &Ptr, int64_t &Size,
7962 const Value *&SrcValue,
7963 int &SrcValueOffset,
7964 unsigned &SrcValueAlign,
7965 const MDNode *&TBAAInfo) const {
7966 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7967 Ptr = LD->getBasePtr();
7968 Size = LD->getMemoryVT().getSizeInBits() >> 3;
7969 SrcValue = LD->getSrcValue();
7970 SrcValueOffset = LD->getSrcValueOffset();
7971 SrcValueAlign = LD->getOriginalAlignment();
7972 TBAAInfo = LD->getTBAAInfo();
7975 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7976 Ptr = ST->getBasePtr();
7977 Size = ST->getMemoryVT().getSizeInBits() >> 3;
7978 SrcValue = ST->getSrcValue();
7979 SrcValueOffset = ST->getSrcValueOffset();
7980 SrcValueAlign = ST->getOriginalAlignment();
7981 TBAAInfo = ST->getTBAAInfo();
7984 llvm_unreachable("FindAliasInfo expected a memory operand");
7987 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
7988 /// looking for aliasing nodes and adding them to the Aliases vector.
7989 void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain,
7990 SmallVector<SDValue, 8> &Aliases) {
7991 SmallVector<SDValue, 8> Chains; // List of chains to visit.
7992 SmallPtrSet<SDNode *, 16> Visited; // Visited node set.
7994 // Get alias information for node.
7997 const Value *SrcValue;
7999 unsigned SrcValueAlign;
8000 const MDNode *SrcTBAAInfo;
8001 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset,
8002 SrcValueAlign, SrcTBAAInfo);
8005 Chains.push_back(OriginalChain);
8008 // Look at each chain and determine if it is an alias. If so, add it to the
8009 // aliases list. If not, then continue up the chain looking for the next
8011 while (!Chains.empty()) {
8012 SDValue Chain = Chains.back();
8015 // For TokenFactor nodes, look at each operand and only continue up the
8016 // chain until we find two aliases. If we've seen two aliases, assume we'll
8017 // find more and revert to original chain since the xform is unlikely to be
8020 // FIXME: The depth check could be made to return the last non-aliasing
8021 // chain we found before we hit a tokenfactor rather than the original
8023 if (Depth > 6 || Aliases.size() == 2) {
8025 Aliases.push_back(OriginalChain);
8029 // Don't bother if we've been before.
8030 if (!Visited.insert(Chain.getNode()))
8033 switch (Chain.getOpcode()) {
8034 case ISD::EntryToken:
8035 // Entry token is ideal chain operand, but handled in FindBetterChain.
8040 // Get alias information for Chain.
8043 const Value *OpSrcValue;
8044 int OpSrcValueOffset;
8045 unsigned OpSrcValueAlign;
8046 const MDNode *OpSrcTBAAInfo;
8047 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize,
8048 OpSrcValue, OpSrcValueOffset,
8052 // If chain is alias then stop here.
8053 if (!(IsLoad && IsOpLoad) &&
8054 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign,
8056 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset,
8057 OpSrcValueAlign, OpSrcTBAAInfo)) {
8058 Aliases.push_back(Chain);
8060 // Look further up the chain.
8061 Chains.push_back(Chain.getOperand(0));
8067 case ISD::TokenFactor:
8068 // We have to check each of the operands of the token factor for "small"
8069 // token factors, so we queue them up. Adding the operands to the queue
8070 // (stack) in reverse order maintains the original order and increases the
8071 // likelihood that getNode will find a matching token factor (CSE.)
8072 if (Chain.getNumOperands() > 16) {
8073 Aliases.push_back(Chain);
8076 for (unsigned n = Chain.getNumOperands(); n;)
8077 Chains.push_back(Chain.getOperand(--n));
8082 // For all other instructions we will just have to take what we can get.
8083 Aliases.push_back(Chain);
8089 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
8090 /// for a better chain (aliasing node.)
8091 SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) {
8092 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor.
8094 // Accumulate all the aliases to this node.
8095 GatherAllAliases(N, OldChain, Aliases);
8097 // If no operands then chain to entry token.
8098 if (Aliases.size() == 0)
8099 return DAG.getEntryNode();
8101 // If a single operand then chain to it. We don't need to revisit it.
8102 if (Aliases.size() == 1)
8105 // Construct a custom tailored token factor.
8106 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
8107 &Aliases[0], Aliases.size());
8110 // SelectionDAG::Combine - This is the entry point for the file.
8112 void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA,
8113 CodeGenOpt::Level OptLevel) {
8114 /// run - This is the main entry point to this class.
8116 DAGCombiner(*this, AA, OptLevel).Run(Level);