1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: select C, pow2, pow2 -> something smart
20 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
21 // FIXME: Dead stores -> nuke
22 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
23 // FIXME: mul (x, const) -> shifts + adds
24 // FIXME: undef values
25 // FIXME: divide by zero is currently left unfolded. do we want to turn this
27 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
29 //===----------------------------------------------------------------------===//
31 #define DEBUG_TYPE "dagcombine"
32 #include "llvm/ADT/Statistic.h"
33 #include "llvm/Analysis/AliasAnalysis.h"
34 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Target/TargetLowering.h"
38 #include "llvm/Support/Compiler.h"
39 #include "llvm/Support/CommandLine.h"
44 static Statistic NodesCombined ("dagcombiner",
45 "Number of dag nodes combined");
47 static Statistic PreIndexedNodes ("pre_indexed_ops",
48 "Number of pre-indexed nodes created");
49 static Statistic PostIndexedNodes ("post_indexed_ops",
50 "Number of post-indexed nodes created");
53 CombinerAA("combiner-alias-analysis", cl::Hidden,
54 cl::desc("Turn on alias analysis during testing"));
57 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden,
58 cl::desc("Include global information in alias analysis"));
60 //------------------------------ DAGCombiner ---------------------------------//
62 class VISIBILITY_HIDDEN DAGCombiner {
67 // Worklist of all of the nodes that need to be simplified.
68 std::vector<SDNode*> WorkList;
70 // AA - Used for DAG load/store alias analysis.
73 /// AddUsersToWorkList - When an instruction is simplified, add all users of
74 /// the instruction to the work lists because they might get more simplified
77 void AddUsersToWorkList(SDNode *N) {
78 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
83 /// removeFromWorkList - remove all instances of N from the worklist.
85 void removeFromWorkList(SDNode *N) {
86 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
91 /// AddToWorkList - Add to the work list making sure it's instance is at the
92 /// the back (next to be processed.)
93 void AddToWorkList(SDNode *N) {
94 removeFromWorkList(N);
95 WorkList.push_back(N);
98 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo,
100 assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
102 DOUT << "\nReplacing.1 "; DEBUG(N->dump());
103 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
104 DOUT << " and " << NumTo-1 << " other values\n";
105 std::vector<SDNode*> NowDead;
106 DAG.ReplaceAllUsesWith(N, To, &NowDead);
109 // Push the new nodes and any users onto the worklist
110 for (unsigned i = 0, e = NumTo; i != e; ++i) {
111 AddToWorkList(To[i].Val);
112 AddUsersToWorkList(To[i].Val);
116 // Nodes can be reintroduced into the worklist. Make sure we do not
117 // process a node that has been replaced.
118 removeFromWorkList(N);
119 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
120 removeFromWorkList(NowDead[i]);
122 // Finally, since the node is now dead, remove it from the graph.
124 return SDOperand(N, 0);
127 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) {
128 return CombineTo(N, &Res, 1, AddTo);
131 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1,
133 SDOperand To[] = { Res0, Res1 };
134 return CombineTo(N, To, 2, AddTo);
138 /// SimplifyDemandedBits - Check the specified integer node value to see if
139 /// it can be simplified or if things it uses can be simplified by bit
140 /// propagation. If so, return true.
141 bool SimplifyDemandedBits(SDOperand Op) {
142 TargetLowering::TargetLoweringOpt TLO(DAG);
143 uint64_t KnownZero, KnownOne;
144 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType());
145 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
149 AddToWorkList(Op.Val);
151 // Replace the old value with the new one.
153 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump());
154 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
157 std::vector<SDNode*> NowDead;
158 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
160 // Push the new node and any (possibly new) users onto the worklist.
161 AddToWorkList(TLO.New.Val);
162 AddUsersToWorkList(TLO.New.Val);
164 // Nodes can end up on the worklist more than once. Make sure we do
165 // not process a node that has been replaced.
166 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
167 removeFromWorkList(NowDead[i]);
169 // Finally, if the node is now dead, remove it from the graph. The node
170 // may not be dead if the replacement process recursively simplified to
171 // something else needing this node.
172 if (TLO.Old.Val->use_empty()) {
173 removeFromWorkList(TLO.Old.Val);
174 DAG.DeleteNode(TLO.Old.Val);
179 bool CombineToPreIndexedLoadStore(SDNode *N);
180 bool CombineToPostIndexedLoadStore(SDNode *N);
183 /// visit - call the node-specific routine that knows how to fold each
184 /// particular type of node.
185 SDOperand visit(SDNode *N);
187 // Visitation implementation - Implement dag node combining for different
188 // node types. The semantics are as follows:
190 // SDOperand.Val == 0 - No change was made
191 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
192 // otherwise - N should be replaced by the returned Operand.
194 SDOperand visitTokenFactor(SDNode *N);
195 SDOperand visitADD(SDNode *N);
196 SDOperand visitSUB(SDNode *N);
197 SDOperand visitMUL(SDNode *N);
198 SDOperand visitSDIV(SDNode *N);
199 SDOperand visitUDIV(SDNode *N);
200 SDOperand visitSREM(SDNode *N);
201 SDOperand visitUREM(SDNode *N);
202 SDOperand visitMULHU(SDNode *N);
203 SDOperand visitMULHS(SDNode *N);
204 SDOperand visitAND(SDNode *N);
205 SDOperand visitOR(SDNode *N);
206 SDOperand visitXOR(SDNode *N);
207 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp);
208 SDOperand visitSHL(SDNode *N);
209 SDOperand visitSRA(SDNode *N);
210 SDOperand visitSRL(SDNode *N);
211 SDOperand visitCTLZ(SDNode *N);
212 SDOperand visitCTTZ(SDNode *N);
213 SDOperand visitCTPOP(SDNode *N);
214 SDOperand visitSELECT(SDNode *N);
215 SDOperand visitSELECT_CC(SDNode *N);
216 SDOperand visitSETCC(SDNode *N);
217 SDOperand visitSIGN_EXTEND(SDNode *N);
218 SDOperand visitZERO_EXTEND(SDNode *N);
219 SDOperand visitANY_EXTEND(SDNode *N);
220 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
221 SDOperand visitTRUNCATE(SDNode *N);
222 SDOperand visitBIT_CONVERT(SDNode *N);
223 SDOperand visitVBIT_CONVERT(SDNode *N);
224 SDOperand visitFADD(SDNode *N);
225 SDOperand visitFSUB(SDNode *N);
226 SDOperand visitFMUL(SDNode *N);
227 SDOperand visitFDIV(SDNode *N);
228 SDOperand visitFREM(SDNode *N);
229 SDOperand visitFCOPYSIGN(SDNode *N);
230 SDOperand visitSINT_TO_FP(SDNode *N);
231 SDOperand visitUINT_TO_FP(SDNode *N);
232 SDOperand visitFP_TO_SINT(SDNode *N);
233 SDOperand visitFP_TO_UINT(SDNode *N);
234 SDOperand visitFP_ROUND(SDNode *N);
235 SDOperand visitFP_ROUND_INREG(SDNode *N);
236 SDOperand visitFP_EXTEND(SDNode *N);
237 SDOperand visitFNEG(SDNode *N);
238 SDOperand visitFABS(SDNode *N);
239 SDOperand visitBRCOND(SDNode *N);
240 SDOperand visitBR_CC(SDNode *N);
241 SDOperand visitLOAD(SDNode *N);
242 SDOperand visitSTORE(SDNode *N);
243 SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
244 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
245 SDOperand visitVBUILD_VECTOR(SDNode *N);
246 SDOperand visitVECTOR_SHUFFLE(SDNode *N);
247 SDOperand visitVVECTOR_SHUFFLE(SDNode *N);
249 SDOperand XformToShuffleWithZero(SDNode *N);
250 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
252 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
253 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
254 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
255 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
256 SDOperand N3, ISD::CondCode CC);
257 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
258 ISD::CondCode Cond, bool foldBooleans = true);
259 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType);
260 SDOperand BuildSDIV(SDNode *N);
261 SDOperand BuildUDIV(SDNode *N);
262 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
264 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
265 /// looking for aliasing nodes and adding them to the Aliases vector.
266 void GatherAllAliases(SDNode *N, SDOperand OriginalChain,
267 SmallVector<SDOperand, 8> &Aliases);
269 /// isAlias - Return true if there is any possibility that the two addresses
271 bool isAlias(SDOperand Ptr1, int64_t Size1,
272 const Value *SrcValue1, int SrcValueOffset1,
273 SDOperand Ptr2, int64_t Size2,
274 const Value *SrcValue2, int SrcValueOffset2);
276 /// FindAliasInfo - Extracts the relevant alias information from the memory
277 /// node. Returns true if the operand was a load.
278 bool FindAliasInfo(SDNode *N,
279 SDOperand &Ptr, int64_t &Size,
280 const Value *&SrcValue, int &SrcValueOffset);
282 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes,
283 /// looking for a better chain (aliasing node.)
284 SDOperand FindBetterChain(SDNode *N, SDOperand Chain);
287 DAGCombiner(SelectionDAG &D, AliasAnalysis &A)
289 TLI(D.getTargetLoweringInfo()),
290 AfterLegalize(false),
293 /// Run - runs the dag combiner on all nodes in the work list
294 void Run(bool RunningAfterLegalize);
298 //===----------------------------------------------------------------------===//
299 // TargetLowering::DAGCombinerInfo implementation
300 //===----------------------------------------------------------------------===//
302 void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) {
303 ((DAGCombiner*)DC)->AddToWorkList(N);
306 SDOperand TargetLowering::DAGCombinerInfo::
307 CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
308 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size());
311 SDOperand TargetLowering::DAGCombinerInfo::
312 CombineTo(SDNode *N, SDOperand Res) {
313 return ((DAGCombiner*)DC)->CombineTo(N, Res);
317 SDOperand TargetLowering::DAGCombinerInfo::
318 CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
319 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1);
325 //===----------------------------------------------------------------------===//
328 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
329 // that selects between the values 1 and 0, making it equivalent to a setcc.
330 // Also, set the incoming LHS, RHS, and CC references to the appropriate
331 // nodes based on the type of node we are checking. This simplifies life a
332 // bit for the callers.
333 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
335 if (N.getOpcode() == ISD::SETCC) {
336 LHS = N.getOperand(0);
337 RHS = N.getOperand(1);
338 CC = N.getOperand(2);
341 if (N.getOpcode() == ISD::SELECT_CC &&
342 N.getOperand(2).getOpcode() == ISD::Constant &&
343 N.getOperand(3).getOpcode() == ISD::Constant &&
344 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
345 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
346 LHS = N.getOperand(0);
347 RHS = N.getOperand(1);
348 CC = N.getOperand(4);
354 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
355 // one use. If this is true, it allows the users to invert the operation for
356 // free when it is profitable to do so.
357 static bool isOneUseSetCC(SDOperand N) {
358 SDOperand N0, N1, N2;
359 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
364 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
365 MVT::ValueType VT = N0.getValueType();
366 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
367 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
368 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
369 if (isa<ConstantSDNode>(N1)) {
370 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
371 AddToWorkList(OpNode.Val);
372 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
373 } else if (N0.hasOneUse()) {
374 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
375 AddToWorkList(OpNode.Val);
376 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
379 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
380 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
381 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
382 if (isa<ConstantSDNode>(N0)) {
383 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
384 AddToWorkList(OpNode.Val);
385 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
386 } else if (N1.hasOneUse()) {
387 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
388 AddToWorkList(OpNode.Val);
389 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
395 void DAGCombiner::Run(bool RunningAfterLegalize) {
396 // set the instance variable, so that the various visit routines may use it.
397 AfterLegalize = RunningAfterLegalize;
399 // Add all the dag nodes to the worklist.
400 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
401 E = DAG.allnodes_end(); I != E; ++I)
402 WorkList.push_back(I);
404 // Create a dummy node (which is not added to allnodes), that adds a reference
405 // to the root node, preventing it from being deleted, and tracking any
406 // changes of the root.
407 HandleSDNode Dummy(DAG.getRoot());
409 // The root of the dag may dangle to deleted nodes until the dag combiner is
410 // done. Set it to null to avoid confusion.
411 DAG.setRoot(SDOperand());
413 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
414 TargetLowering::DAGCombinerInfo
415 DagCombineInfo(DAG, !RunningAfterLegalize, this);
417 // while the worklist isn't empty, inspect the node on the end of it and
418 // try and combine it.
419 while (!WorkList.empty()) {
420 SDNode *N = WorkList.back();
423 // If N has no uses, it is dead. Make sure to revisit all N's operands once
424 // N is deleted from the DAG, since they too may now be dead or may have a
425 // reduced number of uses, allowing other xforms.
426 if (N->use_empty() && N != &Dummy) {
427 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
428 AddToWorkList(N->getOperand(i).Val);
434 SDOperand RV = visit(N);
436 // If nothing happened, try a target-specific DAG combine.
438 assert(N->getOpcode() != ISD::DELETED_NODE &&
439 "Node was deleted but visit returned NULL!");
440 if (N->getOpcode() >= ISD::BUILTIN_OP_END ||
441 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode()))
442 RV = TLI.PerformDAGCombine(N, DagCombineInfo);
447 // If we get back the same node we passed in, rather than a new node or
448 // zero, we know that the node must have defined multiple values and
449 // CombineTo was used. Since CombineTo takes care of the worklist
450 // mechanics for us, we have no work to do in this case.
452 assert(N->getOpcode() != ISD::DELETED_NODE &&
453 RV.Val->getOpcode() != ISD::DELETED_NODE &&
454 "Node was deleted but visit returned new node!");
456 DOUT << "\nReplacing.3 "; DEBUG(N->dump());
457 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
459 std::vector<SDNode*> NowDead;
460 if (N->getNumValues() == RV.Val->getNumValues())
461 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
463 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch");
465 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead);
468 // Push the new node and any users onto the worklist
469 AddToWorkList(RV.Val);
470 AddUsersToWorkList(RV.Val);
472 // Nodes can be reintroduced into the worklist. Make sure we do not
473 // process a node that has been replaced.
474 removeFromWorkList(N);
475 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
476 removeFromWorkList(NowDead[i]);
478 // Finally, since the node is now dead, remove it from the graph.
484 // If the root changed (e.g. it was a dead load, update the root).
485 DAG.setRoot(Dummy.getValue());
488 SDOperand DAGCombiner::visit(SDNode *N) {
489 switch(N->getOpcode()) {
491 case ISD::TokenFactor: return visitTokenFactor(N);
492 case ISD::ADD: return visitADD(N);
493 case ISD::SUB: return visitSUB(N);
494 case ISD::MUL: return visitMUL(N);
495 case ISD::SDIV: return visitSDIV(N);
496 case ISD::UDIV: return visitUDIV(N);
497 case ISD::SREM: return visitSREM(N);
498 case ISD::UREM: return visitUREM(N);
499 case ISD::MULHU: return visitMULHU(N);
500 case ISD::MULHS: return visitMULHS(N);
501 case ISD::AND: return visitAND(N);
502 case ISD::OR: return visitOR(N);
503 case ISD::XOR: return visitXOR(N);
504 case ISD::SHL: return visitSHL(N);
505 case ISD::SRA: return visitSRA(N);
506 case ISD::SRL: return visitSRL(N);
507 case ISD::CTLZ: return visitCTLZ(N);
508 case ISD::CTTZ: return visitCTTZ(N);
509 case ISD::CTPOP: return visitCTPOP(N);
510 case ISD::SELECT: return visitSELECT(N);
511 case ISD::SELECT_CC: return visitSELECT_CC(N);
512 case ISD::SETCC: return visitSETCC(N);
513 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
514 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
515 case ISD::ANY_EXTEND: return visitANY_EXTEND(N);
516 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
517 case ISD::TRUNCATE: return visitTRUNCATE(N);
518 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
519 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N);
520 case ISD::FADD: return visitFADD(N);
521 case ISD::FSUB: return visitFSUB(N);
522 case ISD::FMUL: return visitFMUL(N);
523 case ISD::FDIV: return visitFDIV(N);
524 case ISD::FREM: return visitFREM(N);
525 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N);
526 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
527 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
528 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
529 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
530 case ISD::FP_ROUND: return visitFP_ROUND(N);
531 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
532 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
533 case ISD::FNEG: return visitFNEG(N);
534 case ISD::FABS: return visitFABS(N);
535 case ISD::BRCOND: return visitBRCOND(N);
536 case ISD::BR_CC: return visitBR_CC(N);
537 case ISD::LOAD: return visitLOAD(N);
538 case ISD::STORE: return visitSTORE(N);
539 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
540 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
541 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
542 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
543 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N);
544 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD);
545 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB);
546 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL);
547 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV);
548 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV);
549 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND);
550 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR);
551 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR);
556 /// getInputChainForNode - Given a node, return its input chain if it has one,
557 /// otherwise return a null sd operand.
558 static SDOperand getInputChainForNode(SDNode *N) {
559 if (unsigned NumOps = N->getNumOperands()) {
560 if (N->getOperand(0).getValueType() == MVT::Other)
561 return N->getOperand(0);
562 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
563 return N->getOperand(NumOps-1);
564 for (unsigned i = 1; i < NumOps-1; ++i)
565 if (N->getOperand(i).getValueType() == MVT::Other)
566 return N->getOperand(i);
568 return SDOperand(0, 0);
571 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
572 // If N has two operands, where one has an input chain equal to the other,
573 // the 'other' chain is redundant.
574 if (N->getNumOperands() == 2) {
575 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1))
576 return N->getOperand(0);
577 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0))
578 return N->getOperand(1);
582 SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
583 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor.
584 bool Changed = false; // If we should replace this token factor.
586 // Start out with this token factor.
589 // Iterate through token factors. The TFs grows when new token factors are
591 for (unsigned i = 0; i < TFs.size(); ++i) {
594 // Check each of the operands.
595 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) {
596 SDOperand Op = TF->getOperand(i);
598 switch (Op.getOpcode()) {
599 case ISD::EntryToken:
600 // Entry tokens don't need to be added to the list. They are
605 case ISD::TokenFactor:
606 if ((CombinerAA || Op.hasOneUse()) &&
607 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) {
608 // Queue up for processing.
609 TFs.push_back(Op.Val);
610 // Clean up in case the token factor is removed.
611 AddToWorkList(Op.Val);
618 // Only add if not there prior.
619 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end())
628 // If we've change things around then replace token factor.
630 if (Ops.size() == 0) {
631 // The entry token is the only possible outcome.
632 Result = DAG.getEntryNode();
634 // New and improved token factor.
635 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size());
638 // Don't add users to work list.
639 return CombineTo(N, Result, false);
645 SDOperand DAGCombiner::visitADD(SDNode *N) {
646 SDOperand N0 = N->getOperand(0);
647 SDOperand N1 = N->getOperand(1);
648 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
649 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
650 MVT::ValueType VT = N0.getValueType();
652 // fold (add c1, c2) -> c1+c2
654 return DAG.getNode(ISD::ADD, VT, N0, N1);
655 // canonicalize constant to RHS
657 return DAG.getNode(ISD::ADD, VT, N1, N0);
658 // fold (add x, 0) -> x
659 if (N1C && N1C->isNullValue())
661 // fold ((c1-A)+c2) -> (c1+c2)-A
662 if (N1C && N0.getOpcode() == ISD::SUB)
663 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
664 return DAG.getNode(ISD::SUB, VT,
665 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
668 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
671 // fold ((0-A) + B) -> B-A
672 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
673 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
674 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
675 // fold (A + (0-B)) -> A-B
676 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
677 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
678 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
679 // fold (A+(B-A)) -> B
680 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
681 return N1.getOperand(0);
683 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
684 return SDOperand(N, 0);
686 // fold (a+b) -> (a|b) iff a and b share no bits.
687 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
688 uint64_t LHSZero, LHSOne;
689 uint64_t RHSZero, RHSOne;
690 uint64_t Mask = MVT::getIntVTBitMask(VT);
691 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
693 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
695 // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
696 // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
697 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
698 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
699 return DAG.getNode(ISD::OR, VT, N0, N1);
706 SDOperand DAGCombiner::visitSUB(SDNode *N) {
707 SDOperand N0 = N->getOperand(0);
708 SDOperand N1 = N->getOperand(1);
709 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
710 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
711 MVT::ValueType VT = N0.getValueType();
713 // fold (sub x, x) -> 0
715 return DAG.getConstant(0, N->getValueType(0));
716 // fold (sub c1, c2) -> c1-c2
718 return DAG.getNode(ISD::SUB, VT, N0, N1);
719 // fold (sub x, c) -> (add x, -c)
721 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
723 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
724 return N0.getOperand(1);
726 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
727 return N0.getOperand(0);
731 SDOperand DAGCombiner::visitMUL(SDNode *N) {
732 SDOperand N0 = N->getOperand(0);
733 SDOperand N1 = N->getOperand(1);
734 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
735 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
736 MVT::ValueType VT = N0.getValueType();
738 // fold (mul c1, c2) -> c1*c2
740 return DAG.getNode(ISD::MUL, VT, N0, N1);
741 // canonicalize constant to RHS
743 return DAG.getNode(ISD::MUL, VT, N1, N0);
744 // fold (mul x, 0) -> 0
745 if (N1C && N1C->isNullValue())
747 // fold (mul x, -1) -> 0-x
748 if (N1C && N1C->isAllOnesValue())
749 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
750 // fold (mul x, (1 << c)) -> x << c
751 if (N1C && isPowerOf2_64(N1C->getValue()))
752 return DAG.getNode(ISD::SHL, VT, N0,
753 DAG.getConstant(Log2_64(N1C->getValue()),
754 TLI.getShiftAmountTy()));
755 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
756 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
757 // FIXME: If the input is something that is easily negated (e.g. a
758 // single-use add), we should put the negate there.
759 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
760 DAG.getNode(ISD::SHL, VT, N0,
761 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
762 TLI.getShiftAmountTy())));
765 // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
766 if (N1C && N0.getOpcode() == ISD::SHL &&
767 isa<ConstantSDNode>(N0.getOperand(1))) {
768 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1));
769 AddToWorkList(C3.Val);
770 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3);
773 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one
776 SDOperand Sh(0,0), Y(0,0);
777 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)).
778 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) &&
779 N0.Val->hasOneUse()) {
781 } else if (N1.getOpcode() == ISD::SHL &&
782 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) {
786 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y);
787 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1));
790 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2)
791 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
792 isa<ConstantSDNode>(N0.getOperand(1))) {
793 return DAG.getNode(ISD::ADD, VT,
794 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1),
795 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1));
799 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
805 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
806 SDOperand N0 = N->getOperand(0);
807 SDOperand N1 = N->getOperand(1);
808 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
809 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
810 MVT::ValueType VT = N->getValueType(0);
812 // fold (sdiv c1, c2) -> c1/c2
813 if (N0C && N1C && !N1C->isNullValue())
814 return DAG.getNode(ISD::SDIV, VT, N0, N1);
815 // fold (sdiv X, 1) -> X
816 if (N1C && N1C->getSignExtended() == 1LL)
818 // fold (sdiv X, -1) -> 0-X
819 if (N1C && N1C->isAllOnesValue())
820 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
821 // If we know the sign bits of both operands are zero, strength reduce to a
822 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
823 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
824 if (TLI.MaskedValueIsZero(N1, SignBit) &&
825 TLI.MaskedValueIsZero(N0, SignBit))
826 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
827 // fold (sdiv X, pow2) -> simple ops after legalize
828 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
829 (isPowerOf2_64(N1C->getSignExtended()) ||
830 isPowerOf2_64(-N1C->getSignExtended()))) {
831 // If dividing by powers of two is cheap, then don't perform the following
833 if (TLI.isPow2DivCheap())
835 int64_t pow2 = N1C->getSignExtended();
836 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
837 unsigned lg2 = Log2_64(abs2);
838 // Splat the sign bit into the register
839 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
840 DAG.getConstant(MVT::getSizeInBits(VT)-1,
841 TLI.getShiftAmountTy()));
842 AddToWorkList(SGN.Val);
843 // Add (N0 < 0) ? abs2 - 1 : 0;
844 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
845 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
846 TLI.getShiftAmountTy()));
847 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
848 AddToWorkList(SRL.Val);
849 AddToWorkList(ADD.Val); // Divide by pow2
850 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
851 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
852 // If we're dividing by a positive value, we're done. Otherwise, we must
853 // negate the result.
856 AddToWorkList(SRA.Val);
857 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
859 // if integer divide is expensive and we satisfy the requirements, emit an
860 // alternate sequence.
861 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
862 !TLI.isIntDivCheap()) {
863 SDOperand Op = BuildSDIV(N);
864 if (Op.Val) return Op;
869 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
870 SDOperand N0 = N->getOperand(0);
871 SDOperand N1 = N->getOperand(1);
872 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
873 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
874 MVT::ValueType VT = N->getValueType(0);
876 // fold (udiv c1, c2) -> c1/c2
877 if (N0C && N1C && !N1C->isNullValue())
878 return DAG.getNode(ISD::UDIV, VT, N0, N1);
879 // fold (udiv x, (1 << c)) -> x >>u c
880 if (N1C && isPowerOf2_64(N1C->getValue()))
881 return DAG.getNode(ISD::SRL, VT, N0,
882 DAG.getConstant(Log2_64(N1C->getValue()),
883 TLI.getShiftAmountTy()));
884 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
885 if (N1.getOpcode() == ISD::SHL) {
886 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
887 if (isPowerOf2_64(SHC->getValue())) {
888 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
889 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
890 DAG.getConstant(Log2_64(SHC->getValue()),
892 AddToWorkList(Add.Val);
893 return DAG.getNode(ISD::SRL, VT, N0, Add);
897 // fold (udiv x, c) -> alternate
898 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
899 SDOperand Op = BuildUDIV(N);
900 if (Op.Val) return Op;
905 SDOperand DAGCombiner::visitSREM(SDNode *N) {
906 SDOperand N0 = N->getOperand(0);
907 SDOperand N1 = N->getOperand(1);
908 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
909 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
910 MVT::ValueType VT = N->getValueType(0);
912 // fold (srem c1, c2) -> c1%c2
913 if (N0C && N1C && !N1C->isNullValue())
914 return DAG.getNode(ISD::SREM, VT, N0, N1);
915 // If we know the sign bits of both operands are zero, strength reduce to a
916 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
917 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
918 if (TLI.MaskedValueIsZero(N1, SignBit) &&
919 TLI.MaskedValueIsZero(N0, SignBit))
920 return DAG.getNode(ISD::UREM, VT, N0, N1);
922 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
923 // the remainder operation.
924 if (N1C && !N1C->isNullValue()) {
925 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1);
926 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
927 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
928 AddToWorkList(Div.Val);
929 AddToWorkList(Mul.Val);
936 SDOperand DAGCombiner::visitUREM(SDNode *N) {
937 SDOperand N0 = N->getOperand(0);
938 SDOperand N1 = N->getOperand(1);
939 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
940 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
941 MVT::ValueType VT = N->getValueType(0);
943 // fold (urem c1, c2) -> c1%c2
944 if (N0C && N1C && !N1C->isNullValue())
945 return DAG.getNode(ISD::UREM, VT, N0, N1);
946 // fold (urem x, pow2) -> (and x, pow2-1)
947 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
948 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
949 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
950 if (N1.getOpcode() == ISD::SHL) {
951 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
952 if (isPowerOf2_64(SHC->getValue())) {
953 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
954 AddToWorkList(Add.Val);
955 return DAG.getNode(ISD::AND, VT, N0, Add);
960 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on
961 // the remainder operation.
962 if (N1C && !N1C->isNullValue()) {
963 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1);
964 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1);
965 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul);
966 AddToWorkList(Div.Val);
967 AddToWorkList(Mul.Val);
974 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
975 SDOperand N0 = N->getOperand(0);
976 SDOperand N1 = N->getOperand(1);
977 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
979 // fold (mulhs x, 0) -> 0
980 if (N1C && N1C->isNullValue())
982 // fold (mulhs x, 1) -> (sra x, size(x)-1)
983 if (N1C && N1C->getValue() == 1)
984 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
985 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
986 TLI.getShiftAmountTy()));
990 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
991 SDOperand N0 = N->getOperand(0);
992 SDOperand N1 = N->getOperand(1);
993 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
995 // fold (mulhu x, 0) -> 0
996 if (N1C && N1C->isNullValue())
998 // fold (mulhu x, 1) -> 0
999 if (N1C && N1C->getValue() == 1)
1000 return DAG.getConstant(0, N0.getValueType());
1004 /// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with
1005 /// two operands of the same opcode, try to simplify it.
1006 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
1007 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1008 MVT::ValueType VT = N0.getValueType();
1009 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
1011 // For each of OP in AND/OR/XOR:
1012 // fold (OP (zext x), (zext y)) -> (zext (OP x, y))
1013 // fold (OP (sext x), (sext y)) -> (sext (OP x, y))
1014 // fold (OP (aext x), (aext y)) -> (aext (OP x, y))
1015 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
1016 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND||
1017 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) &&
1018 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1019 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1020 N0.getOperand(0).getValueType(),
1021 N0.getOperand(0), N1.getOperand(0));
1022 AddToWorkList(ORNode.Val);
1023 return DAG.getNode(N0.getOpcode(), VT, ORNode);
1026 // For each of OP in SHL/SRL/SRA/AND...
1027 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z)
1028 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z)
1029 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z)
1030 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL ||
1031 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) &&
1032 N0.getOperand(1) == N1.getOperand(1)) {
1033 SDOperand ORNode = DAG.getNode(N->getOpcode(),
1034 N0.getOperand(0).getValueType(),
1035 N0.getOperand(0), N1.getOperand(0));
1036 AddToWorkList(ORNode.Val);
1037 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1043 SDOperand DAGCombiner::visitAND(SDNode *N) {
1044 SDOperand N0 = N->getOperand(0);
1045 SDOperand N1 = N->getOperand(1);
1046 SDOperand LL, LR, RL, RR, CC0, CC1;
1047 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1048 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1049 MVT::ValueType VT = N1.getValueType();
1051 // fold (and c1, c2) -> c1&c2
1053 return DAG.getNode(ISD::AND, VT, N0, N1);
1054 // canonicalize constant to RHS
1056 return DAG.getNode(ISD::AND, VT, N1, N0);
1057 // fold (and x, -1) -> x
1058 if (N1C && N1C->isAllOnesValue())
1060 // if (and x, c) is known to be zero, return 0
1061 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1062 return DAG.getConstant(0, VT);
1064 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
1067 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
1068 if (N1C && N0.getOpcode() == ISD::OR)
1069 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
1070 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
1072 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
1073 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1074 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType());
1075 if (TLI.MaskedValueIsZero(N0.getOperand(0),
1076 ~N1C->getValue() & InMask)) {
1077 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
1080 // Replace uses of the AND with uses of the Zero extend node.
1083 // We actually want to replace all uses of the any_extend with the
1084 // zero_extend, to avoid duplicating things. This will later cause this
1085 // AND to be folded.
1086 CombineTo(N0.Val, Zext);
1087 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1090 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
1091 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1092 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1093 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1095 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1096 MVT::isInteger(LL.getValueType())) {
1097 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
1098 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
1099 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1100 AddToWorkList(ORNode.Val);
1101 return DAG.getSetCC(VT, ORNode, LR, Op1);
1103 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
1104 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
1105 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1106 AddToWorkList(ANDNode.Val);
1107 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1109 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
1110 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
1111 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1112 AddToWorkList(ORNode.Val);
1113 return DAG.getSetCC(VT, ORNode, LR, Op1);
1116 // canonicalize equivalent to ll == rl
1117 if (LL == RR && LR == RL) {
1118 Op1 = ISD::getSetCCSwappedOperands(Op1);
1121 if (LL == RL && LR == RR) {
1122 bool isInteger = MVT::isInteger(LL.getValueType());
1123 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
1124 if (Result != ISD::SETCC_INVALID)
1125 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1129 // Simplify: and (op x...), (op y...) -> (op (and x, y))
1130 if (N0.getOpcode() == N1.getOpcode()) {
1131 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1132 if (Tmp.Val) return Tmp;
1135 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
1136 // fold (and (sra)) -> (and (srl)) when possible.
1137 if (!MVT::isVector(VT) &&
1138 SimplifyDemandedBits(SDOperand(N, 0)))
1139 return SDOperand(N, 0);
1140 // fold (zext_inreg (extload x)) -> (zextload x)
1141 if (ISD::isEXTLoad(N0.Val)) {
1142 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1143 MVT::ValueType EVT = LN0->getLoadedVT();
1144 // If we zero all the possible extended bits, then we can turn this into
1145 // a zextload if we are running before legalize or the operation is legal.
1146 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1147 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1148 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1149 LN0->getBasePtr(), LN0->getSrcValue(),
1150 LN0->getSrcValueOffset(), EVT);
1152 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1153 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1156 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1157 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
1158 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1159 MVT::ValueType EVT = LN0->getLoadedVT();
1160 // If we zero all the possible extended bits, then we can turn this into
1161 // a zextload if we are running before legalize or the operation is legal.
1162 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1163 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1164 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
1165 LN0->getBasePtr(), LN0->getSrcValue(),
1166 LN0->getSrcValueOffset(), EVT);
1168 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1169 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1173 // fold (and (load x), 255) -> (zextload x, i8)
1174 // fold (and (extload x, i16), 255) -> (zextload x, i8)
1175 if (N1C && N0.getOpcode() == ISD::LOAD) {
1176 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1177 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
1179 MVT::ValueType EVT, LoadedVT;
1180 if (N1C->getValue() == 255)
1182 else if (N1C->getValue() == 65535)
1184 else if (N1C->getValue() == ~0U)
1189 LoadedVT = LN0->getLoadedVT();
1190 if (EVT != MVT::Other && LoadedVT > EVT &&
1191 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1192 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1193 // For big endian targets, we need to add an offset to the pointer to
1194 // load the correct bytes. For little endian systems, we merely need to
1195 // read fewer bytes from the same pointer.
1197 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8;
1198 SDOperand NewPtr = LN0->getBasePtr();
1199 if (!TLI.isLittleEndian())
1200 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
1201 DAG.getConstant(PtrOff, PtrType));
1202 AddToWorkList(NewPtr.Val);
1204 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
1205 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
1207 CombineTo(N0.Val, Load, Load.getValue(1));
1208 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1216 SDOperand DAGCombiner::visitOR(SDNode *N) {
1217 SDOperand N0 = N->getOperand(0);
1218 SDOperand N1 = N->getOperand(1);
1219 SDOperand LL, LR, RL, RR, CC0, CC1;
1220 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1221 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1222 MVT::ValueType VT = N1.getValueType();
1223 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1225 // fold (or c1, c2) -> c1|c2
1227 return DAG.getNode(ISD::OR, VT, N0, N1);
1228 // canonicalize constant to RHS
1230 return DAG.getNode(ISD::OR, VT, N1, N0);
1231 // fold (or x, 0) -> x
1232 if (N1C && N1C->isNullValue())
1234 // fold (or x, -1) -> -1
1235 if (N1C && N1C->isAllOnesValue())
1237 // fold (or x, c) -> c iff (x & ~c) == 0
1239 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1242 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1245 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1246 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1247 isa<ConstantSDNode>(N0.getOperand(1))) {
1248 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1249 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1251 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1253 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1254 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1255 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1256 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1258 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1259 MVT::isInteger(LL.getValueType())) {
1260 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1261 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1262 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1263 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1264 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1265 AddToWorkList(ORNode.Val);
1266 return DAG.getSetCC(VT, ORNode, LR, Op1);
1268 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1269 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1270 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1271 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1272 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1273 AddToWorkList(ANDNode.Val);
1274 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1277 // canonicalize equivalent to ll == rl
1278 if (LL == RR && LR == RL) {
1279 Op1 = ISD::getSetCCSwappedOperands(Op1);
1282 if (LL == RL && LR == RR) {
1283 bool isInteger = MVT::isInteger(LL.getValueType());
1284 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1285 if (Result != ISD::SETCC_INVALID)
1286 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1290 // Simplify: or (op x...), (op y...) -> (op (or x, y))
1291 if (N0.getOpcode() == N1.getOpcode()) {
1292 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1293 if (Tmp.Val) return Tmp;
1296 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible.
1297 if (N0.getOpcode() == ISD::AND &&
1298 N1.getOpcode() == ISD::AND &&
1299 N0.getOperand(1).getOpcode() == ISD::Constant &&
1300 N1.getOperand(1).getOpcode() == ISD::Constant &&
1301 // Don't increase # computations.
1302 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) {
1303 // We can only do this xform if we know that bits from X that are set in C2
1304 // but not in C1 are already zero. Likewise for Y.
1305 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1306 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1308 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) &&
1309 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) {
1310 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0));
1311 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT));
1316 // See if this is some rotate idiom.
1317 if (SDNode *Rot = MatchRotate(N0, N1))
1318 return SDOperand(Rot, 0);
1324 /// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present.
1325 static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
1326 if (Op.getOpcode() == ISD::AND) {
1327 if (isa<ConstantSDNode>(Op.getOperand(1))) {
1328 Mask = Op.getOperand(1);
1329 Op = Op.getOperand(0);
1335 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) {
1343 // MatchRotate - Handle an 'or' of two operands. If this is one of the many
1344 // idioms for rotate, and if the target supports rotation instructions, generate
1346 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
1347 // Must be a legal type. Expanded an promoted things won't work with rotates.
1348 MVT::ValueType VT = LHS.getValueType();
1349 if (!TLI.isTypeLegal(VT)) return 0;
1351 // The target must have at least one rotate flavor.
1352 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT);
1353 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT);
1354 if (!HasROTL && !HasROTR) return 0;
1356 // Match "(X shl/srl V1) & V2" where V2 may not be present.
1357 SDOperand LHSShift; // The shift.
1358 SDOperand LHSMask; // AND value if any.
1359 if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
1360 return 0; // Not part of a rotate.
1362 SDOperand RHSShift; // The shift.
1363 SDOperand RHSMask; // AND value if any.
1364 if (!MatchRotateHalf(RHS, RHSShift, RHSMask))
1365 return 0; // Not part of a rotate.
1367 if (LHSShift.getOperand(0) != RHSShift.getOperand(0))
1368 return 0; // Not shifting the same value.
1370 if (LHSShift.getOpcode() == RHSShift.getOpcode())
1371 return 0; // Shifts must disagree.
1373 // Canonicalize shl to left side in a shl/srl pair.
1374 if (RHSShift.getOpcode() == ISD::SHL) {
1375 std::swap(LHS, RHS);
1376 std::swap(LHSShift, RHSShift);
1377 std::swap(LHSMask , RHSMask );
1380 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1382 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1383 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
1384 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
1385 RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
1386 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue();
1387 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue();
1388 if ((LShVal + RShVal) != OpSizeInBits)
1393 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1394 LHSShift.getOperand(1));
1396 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1397 RHSShift.getOperand(1));
1399 // If there is an AND of either shifted operand, apply it to the result.
1400 if (LHSMask.Val || RHSMask.Val) {
1401 uint64_t Mask = MVT::getIntVTBitMask(VT);
1404 uint64_t RHSBits = (1ULL << LShVal)-1;
1405 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits;
1408 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1);
1409 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits;
1412 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT));
1418 // If there is a mask here, and we have a variable shift, we can't be sure
1419 // that we're masking out the right stuff.
1420 if (LHSMask.Val || RHSMask.Val)
1423 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1424 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
1425 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1426 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
1427 if (ConstantSDNode *SUBC =
1428 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) {
1429 if (SUBC->getValue() == OpSizeInBits)
1431 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1432 LHSShift.getOperand(1)).Val;
1434 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1435 LHSShift.getOperand(1)).Val;
1439 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1440 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
1441 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
1442 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
1443 if (ConstantSDNode *SUBC =
1444 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) {
1445 if (SUBC->getValue() == OpSizeInBits)
1447 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
1448 LHSShift.getOperand(1)).Val;
1450 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
1451 RHSShift.getOperand(1)).Val;
1459 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1460 SDOperand N0 = N->getOperand(0);
1461 SDOperand N1 = N->getOperand(1);
1462 SDOperand LHS, RHS, CC;
1463 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1464 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1465 MVT::ValueType VT = N0.getValueType();
1467 // fold (xor c1, c2) -> c1^c2
1469 return DAG.getNode(ISD::XOR, VT, N0, N1);
1470 // canonicalize constant to RHS
1472 return DAG.getNode(ISD::XOR, VT, N1, N0);
1473 // fold (xor x, 0) -> x
1474 if (N1C && N1C->isNullValue())
1477 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1480 // fold !(x cc y) -> (x !cc y)
1481 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1482 bool isInt = MVT::isInteger(LHS.getValueType());
1483 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1485 if (N0.getOpcode() == ISD::SETCC)
1486 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1487 if (N0.getOpcode() == ISD::SELECT_CC)
1488 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1489 assert(0 && "Unhandled SetCC Equivalent!");
1492 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1493 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
1494 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1495 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1496 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1497 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1498 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1499 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1500 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1501 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1504 // fold !(x or y) -> (!x and !y) iff x or y are constants
1505 if (N1C && N1C->isAllOnesValue() &&
1506 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1507 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1508 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1509 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1510 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1511 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1512 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val);
1513 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1516 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1517 if (N1C && N0.getOpcode() == ISD::XOR) {
1518 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1519 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1521 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1522 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1524 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1525 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1527 // fold (xor x, x) -> 0
1529 if (!MVT::isVector(VT)) {
1530 return DAG.getConstant(0, VT);
1531 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
1532 // Produce a vector of zeros.
1533 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
1534 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
1535 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1539 // Simplify: xor (op x...), (op y...) -> (op (xor x, y))
1540 if (N0.getOpcode() == N1.getOpcode()) {
1541 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N);
1542 if (Tmp.Val) return Tmp;
1545 // Simplify the expression using non-local knowledge.
1546 if (!MVT::isVector(VT) &&
1547 SimplifyDemandedBits(SDOperand(N, 0)))
1548 return SDOperand(N, 0);
1553 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1554 SDOperand N0 = N->getOperand(0);
1555 SDOperand N1 = N->getOperand(1);
1556 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1557 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1558 MVT::ValueType VT = N0.getValueType();
1559 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1561 // fold (shl c1, c2) -> c1<<c2
1563 return DAG.getNode(ISD::SHL, VT, N0, N1);
1564 // fold (shl 0, x) -> 0
1565 if (N0C && N0C->isNullValue())
1567 // fold (shl x, c >= size(x)) -> undef
1568 if (N1C && N1C->getValue() >= OpSizeInBits)
1569 return DAG.getNode(ISD::UNDEF, VT);
1570 // fold (shl x, 0) -> x
1571 if (N1C && N1C->isNullValue())
1573 // if (shl x, c) is known to be zero, return 0
1574 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1575 return DAG.getConstant(0, VT);
1576 if (SimplifyDemandedBits(SDOperand(N, 0)))
1577 return SDOperand(N, 0);
1578 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1579 if (N1C && N0.getOpcode() == ISD::SHL &&
1580 N0.getOperand(1).getOpcode() == ISD::Constant) {
1581 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1582 uint64_t c2 = N1C->getValue();
1583 if (c1 + c2 > OpSizeInBits)
1584 return DAG.getConstant(0, VT);
1585 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1586 DAG.getConstant(c1 + c2, N1.getValueType()));
1588 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1589 // (srl (and x, -1 << c1), c1-c2)
1590 if (N1C && N0.getOpcode() == ISD::SRL &&
1591 N0.getOperand(1).getOpcode() == ISD::Constant) {
1592 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1593 uint64_t c2 = N1C->getValue();
1594 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1595 DAG.getConstant(~0ULL << c1, VT));
1597 return DAG.getNode(ISD::SHL, VT, Mask,
1598 DAG.getConstant(c2-c1, N1.getValueType()));
1600 return DAG.getNode(ISD::SRL, VT, Mask,
1601 DAG.getConstant(c1-c2, N1.getValueType()));
1603 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1604 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1605 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1606 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1607 // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1<<c2)
1608 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() &&
1609 isa<ConstantSDNode>(N0.getOperand(1))) {
1610 return DAG.getNode(ISD::ADD, VT,
1611 DAG.getNode(ISD::SHL, VT, N0.getOperand(0), N1),
1612 DAG.getNode(ISD::SHL, VT, N0.getOperand(1), N1));
1617 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1618 SDOperand N0 = N->getOperand(0);
1619 SDOperand N1 = N->getOperand(1);
1620 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1621 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1622 MVT::ValueType VT = N0.getValueType();
1624 // fold (sra c1, c2) -> c1>>c2
1626 return DAG.getNode(ISD::SRA, VT, N0, N1);
1627 // fold (sra 0, x) -> 0
1628 if (N0C && N0C->isNullValue())
1630 // fold (sra -1, x) -> -1
1631 if (N0C && N0C->isAllOnesValue())
1633 // fold (sra x, c >= size(x)) -> undef
1634 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1635 return DAG.getNode(ISD::UNDEF, VT);
1636 // fold (sra x, 0) -> x
1637 if (N1C && N1C->isNullValue())
1639 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1641 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1642 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1645 default: EVT = MVT::Other; break;
1646 case 1: EVT = MVT::i1; break;
1647 case 8: EVT = MVT::i8; break;
1648 case 16: EVT = MVT::i16; break;
1649 case 32: EVT = MVT::i32; break;
1651 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1652 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1653 DAG.getValueType(EVT));
1656 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
1657 if (N1C && N0.getOpcode() == ISD::SRA) {
1658 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
1659 unsigned Sum = N1C->getValue() + C1->getValue();
1660 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
1661 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
1662 DAG.getConstant(Sum, N1C->getValueType(0)));
1666 // Simplify, based on bits shifted out of the LHS.
1667 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
1668 return SDOperand(N, 0);
1671 // If the sign bit is known to be zero, switch this to a SRL.
1672 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1673 return DAG.getNode(ISD::SRL, VT, N0, N1);
1677 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1678 SDOperand N0 = N->getOperand(0);
1679 SDOperand N1 = N->getOperand(1);
1680 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1681 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1682 MVT::ValueType VT = N0.getValueType();
1683 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1685 // fold (srl c1, c2) -> c1 >>u c2
1687 return DAG.getNode(ISD::SRL, VT, N0, N1);
1688 // fold (srl 0, x) -> 0
1689 if (N0C && N0C->isNullValue())
1691 // fold (srl x, c >= size(x)) -> undef
1692 if (N1C && N1C->getValue() >= OpSizeInBits)
1693 return DAG.getNode(ISD::UNDEF, VT);
1694 // fold (srl x, 0) -> x
1695 if (N1C && N1C->isNullValue())
1697 // if (srl x, c) is known to be zero, return 0
1698 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1699 return DAG.getConstant(0, VT);
1700 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1701 if (N1C && N0.getOpcode() == ISD::SRL &&
1702 N0.getOperand(1).getOpcode() == ISD::Constant) {
1703 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1704 uint64_t c2 = N1C->getValue();
1705 if (c1 + c2 > OpSizeInBits)
1706 return DAG.getConstant(0, VT);
1707 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1708 DAG.getConstant(c1 + c2, N1.getValueType()));
1711 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
1712 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
1713 // Shifting in all undef bits?
1714 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
1715 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
1716 return DAG.getNode(ISD::UNDEF, VT);
1718 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
1719 AddToWorkList(SmallShift.Val);
1720 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift);
1723 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
1724 // bit, which is unmodified by sra.
1725 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
1726 if (N0.getOpcode() == ISD::SRA)
1727 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
1730 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
1731 if (N1C && N0.getOpcode() == ISD::CTLZ &&
1732 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) {
1733 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT);
1734 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
1736 // If any of the input bits are KnownOne, then the input couldn't be all
1737 // zeros, thus the result of the srl will always be zero.
1738 if (KnownOne) return DAG.getConstant(0, VT);
1740 // If all of the bits input the to ctlz node are known to be zero, then
1741 // the result of the ctlz is "32" and the result of the shift is one.
1742 uint64_t UnknownBits = ~KnownZero & Mask;
1743 if (UnknownBits == 0) return DAG.getConstant(1, VT);
1745 // Otherwise, check to see if there is exactly one bit input to the ctlz.
1746 if ((UnknownBits & (UnknownBits-1)) == 0) {
1747 // Okay, we know that only that the single bit specified by UnknownBits
1748 // could be set on input to the CTLZ node. If this bit is set, the SRL
1749 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair
1750 // to an SRL,XOR pair, which is likely to simplify more.
1751 unsigned ShAmt = CountTrailingZeros_64(UnknownBits);
1752 SDOperand Op = N0.getOperand(0);
1754 Op = DAG.getNode(ISD::SRL, VT, Op,
1755 DAG.getConstant(ShAmt, TLI.getShiftAmountTy()));
1756 AddToWorkList(Op.Val);
1758 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
1765 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1766 SDOperand N0 = N->getOperand(0);
1767 MVT::ValueType VT = N->getValueType(0);
1769 // fold (ctlz c1) -> c2
1770 if (isa<ConstantSDNode>(N0))
1771 return DAG.getNode(ISD::CTLZ, VT, N0);
1775 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1776 SDOperand N0 = N->getOperand(0);
1777 MVT::ValueType VT = N->getValueType(0);
1779 // fold (cttz c1) -> c2
1780 if (isa<ConstantSDNode>(N0))
1781 return DAG.getNode(ISD::CTTZ, VT, N0);
1785 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1786 SDOperand N0 = N->getOperand(0);
1787 MVT::ValueType VT = N->getValueType(0);
1789 // fold (ctpop c1) -> c2
1790 if (isa<ConstantSDNode>(N0))
1791 return DAG.getNode(ISD::CTPOP, VT, N0);
1795 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1796 SDOperand N0 = N->getOperand(0);
1797 SDOperand N1 = N->getOperand(1);
1798 SDOperand N2 = N->getOperand(2);
1799 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1800 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1801 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1802 MVT::ValueType VT = N->getValueType(0);
1804 // fold select C, X, X -> X
1807 // fold select true, X, Y -> X
1808 if (N0C && !N0C->isNullValue())
1810 // fold select false, X, Y -> Y
1811 if (N0C && N0C->isNullValue())
1813 // fold select C, 1, X -> C | X
1814 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1815 return DAG.getNode(ISD::OR, VT, N0, N2);
1816 // fold select C, 0, X -> ~C & X
1817 // FIXME: this should check for C type == X type, not i1?
1818 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1819 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1820 AddToWorkList(XORNode.Val);
1821 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1823 // fold select C, X, 1 -> ~C | X
1824 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1825 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1826 AddToWorkList(XORNode.Val);
1827 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1829 // fold select C, X, 0 -> C & X
1830 // FIXME: this should check for C type == X type, not i1?
1831 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1832 return DAG.getNode(ISD::AND, VT, N0, N1);
1833 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1834 if (MVT::i1 == VT && N0 == N1)
1835 return DAG.getNode(ISD::OR, VT, N0, N2);
1836 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1837 if (MVT::i1 == VT && N0 == N2)
1838 return DAG.getNode(ISD::AND, VT, N0, N1);
1840 // If we can fold this based on the true/false value, do so.
1841 if (SimplifySelectOps(N, N1, N2))
1842 return SDOperand(N, 0); // Don't revisit N.
1844 // fold selects based on a setcc into other things, such as min/max/abs
1845 if (N0.getOpcode() == ISD::SETCC)
1847 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1848 // having to say they don't support SELECT_CC on every type the DAG knows
1849 // about, since there is no way to mark an opcode illegal at all value types
1850 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1851 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1852 N1, N2, N0.getOperand(2));
1854 return SimplifySelect(N0, N1, N2);
1858 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1859 SDOperand N0 = N->getOperand(0);
1860 SDOperand N1 = N->getOperand(1);
1861 SDOperand N2 = N->getOperand(2);
1862 SDOperand N3 = N->getOperand(3);
1863 SDOperand N4 = N->getOperand(4);
1864 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1866 // fold select_cc lhs, rhs, x, x, cc -> x
1870 // Determine if the condition we're dealing with is constant
1871 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1872 if (SCC.Val) AddToWorkList(SCC.Val);
1874 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) {
1875 if (SCCC->getValue())
1876 return N2; // cond always true -> true val
1878 return N3; // cond always false -> false val
1881 // Fold to a simpler select_cc
1882 if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1883 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(),
1884 SCC.getOperand(0), SCC.getOperand(1), N2, N3,
1887 // If we can fold this based on the true/false value, do so.
1888 if (SimplifySelectOps(N, N2, N3))
1889 return SDOperand(N, 0); // Don't revisit N.
1891 // fold select_cc into other things, such as min/max/abs
1892 return SimplifySelectCC(N0, N1, N2, N3, CC);
1895 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1896 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1897 cast<CondCodeSDNode>(N->getOperand(2))->get());
1900 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1901 SDOperand N0 = N->getOperand(0);
1902 MVT::ValueType VT = N->getValueType(0);
1904 // fold (sext c1) -> c1
1905 if (isa<ConstantSDNode>(N0))
1906 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1908 // fold (sext (sext x)) -> (sext x)
1909 // fold (sext (aext x)) -> (sext x)
1910 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1911 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1913 // fold (sext (truncate x)) -> (sextinreg x).
1914 if (N0.getOpcode() == ISD::TRUNCATE &&
1915 (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
1916 N0.getValueType()))) {
1917 SDOperand Op = N0.getOperand(0);
1918 if (Op.getValueType() < VT) {
1919 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1920 } else if (Op.getValueType() > VT) {
1921 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1923 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
1924 DAG.getValueType(N0.getValueType()));
1927 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1928 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
1929 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){
1930 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1931 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1932 LN0->getBasePtr(), LN0->getSrcValue(),
1933 LN0->getSrcValueOffset(),
1935 CombineTo(N, ExtLoad);
1936 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1937 ExtLoad.getValue(1));
1938 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1941 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1942 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1943 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
1944 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
1945 MVT::ValueType EVT = LN0->getLoadedVT();
1946 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
1947 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
1948 LN0->getBasePtr(), LN0->getSrcValue(),
1949 LN0->getSrcValueOffset(), EVT);
1950 CombineTo(N, ExtLoad);
1951 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1952 ExtLoad.getValue(1));
1953 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
1960 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1961 SDOperand N0 = N->getOperand(0);
1962 MVT::ValueType VT = N->getValueType(0);
1964 // fold (zext c1) -> c1
1965 if (isa<ConstantSDNode>(N0))
1966 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1967 // fold (zext (zext x)) -> (zext x)
1968 // fold (zext (aext x)) -> (zext x)
1969 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
1970 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1972 // fold (zext (truncate x)) -> (and x, mask)
1973 if (N0.getOpcode() == ISD::TRUNCATE &&
1974 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
1975 SDOperand Op = N0.getOperand(0);
1976 if (Op.getValueType() < VT) {
1977 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
1978 } else if (Op.getValueType() > VT) {
1979 Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
1981 return DAG.getZeroExtendInReg(Op, N0.getValueType());
1984 // fold (zext (and (trunc x), cst)) -> (and x, cst).
1985 if (N0.getOpcode() == ISD::AND &&
1986 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
1987 N0.getOperand(1).getOpcode() == ISD::Constant) {
1988 SDOperand X = N0.getOperand(0).getOperand(0);
1989 if (X.getValueType() < VT) {
1990 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
1991 } else if (X.getValueType() > VT) {
1992 X = DAG.getNode(ISD::TRUNCATE, VT, X);
1994 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1995 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
1998 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1999 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2000 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) {
2001 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2002 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2003 LN0->getBasePtr(), LN0->getSrcValue(),
2004 LN0->getSrcValueOffset(),
2006 CombineTo(N, ExtLoad);
2007 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2008 ExtLoad.getValue(1));
2009 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2012 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
2013 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
2014 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
2015 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2016 MVT::ValueType EVT = LN0->getLoadedVT();
2017 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
2018 LN0->getBasePtr(), LN0->getSrcValue(),
2019 LN0->getSrcValueOffset(), EVT);
2020 CombineTo(N, ExtLoad);
2021 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2022 ExtLoad.getValue(1));
2023 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2028 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
2029 SDOperand N0 = N->getOperand(0);
2030 MVT::ValueType VT = N->getValueType(0);
2032 // fold (aext c1) -> c1
2033 if (isa<ConstantSDNode>(N0))
2034 return DAG.getNode(ISD::ANY_EXTEND, VT, N0);
2035 // fold (aext (aext x)) -> (aext x)
2036 // fold (aext (zext x)) -> (zext x)
2037 // fold (aext (sext x)) -> (sext x)
2038 if (N0.getOpcode() == ISD::ANY_EXTEND ||
2039 N0.getOpcode() == ISD::ZERO_EXTEND ||
2040 N0.getOpcode() == ISD::SIGN_EXTEND)
2041 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2043 // fold (aext (truncate x))
2044 if (N0.getOpcode() == ISD::TRUNCATE) {
2045 SDOperand TruncOp = N0.getOperand(0);
2046 if (TruncOp.getValueType() == VT)
2047 return TruncOp; // x iff x size == zext size.
2048 if (TruncOp.getValueType() > VT)
2049 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp);
2050 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp);
2053 // fold (aext (and (trunc x), cst)) -> (and x, cst).
2054 if (N0.getOpcode() == ISD::AND &&
2055 N0.getOperand(0).getOpcode() == ISD::TRUNCATE &&
2056 N0.getOperand(1).getOpcode() == ISD::Constant) {
2057 SDOperand X = N0.getOperand(0).getOperand(0);
2058 if (X.getValueType() < VT) {
2059 X = DAG.getNode(ISD::ANY_EXTEND, VT, X);
2060 } else if (X.getValueType() > VT) {
2061 X = DAG.getNode(ISD::TRUNCATE, VT, X);
2063 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
2064 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
2067 // fold (aext (load x)) -> (aext (truncate (extload x)))
2068 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2069 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2070 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2071 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2072 LN0->getBasePtr(), LN0->getSrcValue(),
2073 LN0->getSrcValueOffset(),
2075 CombineTo(N, ExtLoad);
2076 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2077 ExtLoad.getValue(1));
2078 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2081 // fold (aext (zextload x)) -> (aext (truncate (zextload x)))
2082 // fold (aext (sextload x)) -> (aext (truncate (sextload x)))
2083 // fold (aext ( extload x)) -> (aext (truncate (extload x)))
2084 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
2086 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2087 MVT::ValueType EVT = LN0->getLoadedVT();
2088 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
2089 LN0->getChain(), LN0->getBasePtr(),
2091 LN0->getSrcValueOffset(), EVT);
2092 CombineTo(N, ExtLoad);
2093 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
2094 ExtLoad.getValue(1));
2095 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2101 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
2102 SDOperand N0 = N->getOperand(0);
2103 SDOperand N1 = N->getOperand(1);
2104 MVT::ValueType VT = N->getValueType(0);
2105 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
2106 unsigned EVTBits = MVT::getSizeInBits(EVT);
2108 // fold (sext_in_reg c1) -> c1
2109 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
2110 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
2112 // If the input is already sign extended, just drop the extension.
2113 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
2116 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
2117 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2118 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
2119 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
2122 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
2123 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
2124 return DAG.getZeroExtendInReg(N0, EVT);
2126 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
2127 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible.
2128 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
2129 if (N0.getOpcode() == ISD::SRL) {
2130 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2131 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
2132 // We can turn this into an SRA iff the input to the SRL is already sign
2134 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0));
2135 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
2136 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
2140 // fold (sext_inreg (extload x)) -> (sextload x)
2141 if (ISD::isEXTLoad(N0.Val) &&
2142 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2143 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2144 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2145 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2146 LN0->getBasePtr(), LN0->getSrcValue(),
2147 LN0->getSrcValueOffset(), EVT);
2148 CombineTo(N, ExtLoad);
2149 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2150 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2152 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
2153 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
2154 EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
2155 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
2156 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2157 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
2158 LN0->getBasePtr(), LN0->getSrcValue(),
2159 LN0->getSrcValueOffset(), EVT);
2160 CombineTo(N, ExtLoad);
2161 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
2162 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2167 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
2168 SDOperand N0 = N->getOperand(0);
2169 MVT::ValueType VT = N->getValueType(0);
2172 if (N0.getValueType() == N->getValueType(0))
2174 // fold (truncate c1) -> c1
2175 if (isa<ConstantSDNode>(N0))
2176 return DAG.getNode(ISD::TRUNCATE, VT, N0);
2177 // fold (truncate (truncate x)) -> (truncate x)
2178 if (N0.getOpcode() == ISD::TRUNCATE)
2179 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2180 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
2181 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND||
2182 N0.getOpcode() == ISD::ANY_EXTEND) {
2183 if (N0.getOperand(0).getValueType() < VT)
2184 // if the source is smaller than the dest, we still need an extend
2185 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
2186 else if (N0.getOperand(0).getValueType() > VT)
2187 // if the source is larger than the dest, than we just need the truncate
2188 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
2190 // if the source and dest are the same type, we can drop both the extend
2192 return N0.getOperand(0);
2194 // fold (truncate (load x)) -> (smaller load x)
2195 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2196 // Do not allow folding to i1 here. i1 is implicitly stored in memory in
2197 // zero extended form: by shrinking the load, we lose track of the fact
2198 // that it is already zero extended.
2199 // FIXME: This should be reevaluated.
2201 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
2202 "Cannot truncate to larger type!");
2203 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2204 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
2205 // For big endian targets, we need to add an offset to the pointer to load
2206 // the correct bytes. For little endian systems, we merely need to read
2207 // fewer bytes from the same pointer.
2209 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
2210 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() :
2211 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
2212 DAG.getConstant(PtrOff, PtrType));
2213 AddToWorkList(NewPtr.Val);
2214 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr,
2215 LN0->getSrcValue(), LN0->getSrcValueOffset());
2217 CombineTo(N0.Val, Load, Load.getValue(1));
2218 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2223 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
2224 SDOperand N0 = N->getOperand(0);
2225 MVT::ValueType VT = N->getValueType(0);
2227 // If the input is a constant, let getNode() fold it.
2228 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
2229 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
2230 if (Res.Val != N) return Res;
2233 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
2234 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
2236 // fold (conv (load x)) -> (load (conv*)x)
2237 // FIXME: These xforms need to know that the resultant load doesn't need a
2238 // higher alignment than the original!
2239 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
2240 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2241 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
2242 LN0->getSrcValue(), LN0->getSrcValueOffset());
2244 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
2252 SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) {
2253 SDOperand N0 = N->getOperand(0);
2254 MVT::ValueType VT = N->getValueType(0);
2256 // If the input is a VBUILD_VECTOR with all constant elements, fold this now.
2257 // First check to see if this is all constant.
2258 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() &&
2259 VT == MVT::Vector) {
2260 bool isSimple = true;
2261 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i)
2262 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
2263 N0.getOperand(i).getOpcode() != ISD::Constant &&
2264 N0.getOperand(i).getOpcode() != ISD::ConstantFP) {
2269 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT();
2270 if (isSimple && !MVT::isVector(DestEltVT)) {
2271 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT);
2278 /// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector
2279 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
2280 /// destination element value type.
2281 SDOperand DAGCombiner::
2282 ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
2283 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
2285 // If this is already the right type, we're done.
2286 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
2288 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
2289 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
2291 // If this is a conversion of N elements of one type to N elements of another
2292 // type, convert each element. This handles FP<->INT cases.
2293 if (SrcBitSize == DstBitSize) {
2294 SmallVector<SDOperand, 8> Ops;
2295 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2296 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
2297 AddToWorkList(Ops.back().Val);
2299 Ops.push_back(*(BV->op_end()-2)); // Add num elements.
2300 Ops.push_back(DAG.getValueType(DstEltVT));
2301 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2304 // Otherwise, we're growing or shrinking the elements. To avoid having to
2305 // handle annoying details of growing/shrinking FP values, we convert them to
2307 if (MVT::isFloatingPoint(SrcEltVT)) {
2308 // Convert the input float vector to a int vector where the elements are the
2310 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
2311 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2312 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val;
2316 // Now we know the input is an integer vector. If the output is a FP type,
2317 // convert to integer first, then to FP of the right size.
2318 if (MVT::isFloatingPoint(DstEltVT)) {
2319 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
2320 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
2321 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val;
2323 // Next, convert to FP elements of the same size.
2324 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT);
2327 // Okay, we know the src/dst types are both integers of differing types.
2328 // Handling growing first.
2329 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
2330 if (SrcBitSize < DstBitSize) {
2331 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
2333 SmallVector<SDOperand, 8> Ops;
2334 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e;
2335 i += NumInputsPerOutput) {
2336 bool isLE = TLI.isLittleEndian();
2337 uint64_t NewBits = 0;
2338 bool EltIsUndef = true;
2339 for (unsigned j = 0; j != NumInputsPerOutput; ++j) {
2340 // Shift the previously computed bits over.
2341 NewBits <<= SrcBitSize;
2342 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j));
2343 if (Op.getOpcode() == ISD::UNDEF) continue;
2346 NewBits |= cast<ConstantSDNode>(Op)->getValue();
2350 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2352 Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
2355 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2356 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2357 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2360 // Finally, this must be the case where we are shrinking elements: each input
2361 // turns into multiple outputs.
2362 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
2363 SmallVector<SDOperand, 8> Ops;
2364 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) {
2365 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
2366 for (unsigned j = 0; j != NumOutputsPerInput; ++j)
2367 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT));
2370 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue();
2372 for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
2373 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1);
2374 OpVal >>= DstBitSize;
2375 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT));
2378 // For big endian targets, swap the order of the pieces of each element.
2379 if (!TLI.isLittleEndian())
2380 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end());
2382 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
2383 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size.
2384 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
2389 SDOperand DAGCombiner::visitFADD(SDNode *N) {
2390 SDOperand N0 = N->getOperand(0);
2391 SDOperand N1 = N->getOperand(1);
2392 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2393 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2394 MVT::ValueType VT = N->getValueType(0);
2396 // fold (fadd c1, c2) -> c1+c2
2398 return DAG.getNode(ISD::FADD, VT, N0, N1);
2399 // canonicalize constant to RHS
2400 if (N0CFP && !N1CFP)
2401 return DAG.getNode(ISD::FADD, VT, N1, N0);
2402 // fold (A + (-B)) -> A-B
2403 if (N1.getOpcode() == ISD::FNEG)
2404 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
2405 // fold ((-A) + B) -> B-A
2406 if (N0.getOpcode() == ISD::FNEG)
2407 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
2411 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
2412 SDOperand N0 = N->getOperand(0);
2413 SDOperand N1 = N->getOperand(1);
2414 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2415 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2416 MVT::ValueType VT = N->getValueType(0);
2418 // fold (fsub c1, c2) -> c1-c2
2420 return DAG.getNode(ISD::FSUB, VT, N0, N1);
2421 // fold (A-(-B)) -> A+B
2422 if (N1.getOpcode() == ISD::FNEG)
2423 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
2427 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
2428 SDOperand N0 = N->getOperand(0);
2429 SDOperand N1 = N->getOperand(1);
2430 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2431 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2432 MVT::ValueType VT = N->getValueType(0);
2434 // fold (fmul c1, c2) -> c1*c2
2436 return DAG.getNode(ISD::FMUL, VT, N0, N1);
2437 // canonicalize constant to RHS
2438 if (N0CFP && !N1CFP)
2439 return DAG.getNode(ISD::FMUL, VT, N1, N0);
2440 // fold (fmul X, 2.0) -> (fadd X, X)
2441 if (N1CFP && N1CFP->isExactlyValue(+2.0))
2442 return DAG.getNode(ISD::FADD, VT, N0, N0);
2446 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
2447 SDOperand N0 = N->getOperand(0);
2448 SDOperand N1 = N->getOperand(1);
2449 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2450 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2451 MVT::ValueType VT = N->getValueType(0);
2453 // fold (fdiv c1, c2) -> c1/c2
2455 return DAG.getNode(ISD::FDIV, VT, N0, N1);
2459 SDOperand DAGCombiner::visitFREM(SDNode *N) {
2460 SDOperand N0 = N->getOperand(0);
2461 SDOperand N1 = N->getOperand(1);
2462 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2463 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2464 MVT::ValueType VT = N->getValueType(0);
2466 // fold (frem c1, c2) -> fmod(c1,c2)
2468 return DAG.getNode(ISD::FREM, VT, N0, N1);
2472 SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
2473 SDOperand N0 = N->getOperand(0);
2474 SDOperand N1 = N->getOperand(1);
2475 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2476 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2477 MVT::ValueType VT = N->getValueType(0);
2479 if (N0CFP && N1CFP) // Constant fold
2480 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
2483 // copysign(x, c1) -> fabs(x) iff ispos(c1)
2484 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1)
2489 u.d = N1CFP->getValue();
2491 return DAG.getNode(ISD::FABS, VT, N0);
2493 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0));
2496 // copysign(fabs(x), y) -> copysign(x, y)
2497 // copysign(fneg(x), y) -> copysign(x, y)
2498 // copysign(copysign(x,z), y) -> copysign(x, y)
2499 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG ||
2500 N0.getOpcode() == ISD::FCOPYSIGN)
2501 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1);
2503 // copysign(x, abs(y)) -> abs(x)
2504 if (N1.getOpcode() == ISD::FABS)
2505 return DAG.getNode(ISD::FABS, VT, N0);
2507 // copysign(x, copysign(y,z)) -> copysign(x, z)
2508 if (N1.getOpcode() == ISD::FCOPYSIGN)
2509 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1));
2511 // copysign(x, fp_extend(y)) -> copysign(x, y)
2512 // copysign(x, fp_round(y)) -> copysign(x, y)
2513 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND)
2514 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0));
2521 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
2522 SDOperand N0 = N->getOperand(0);
2523 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2524 MVT::ValueType VT = N->getValueType(0);
2526 // fold (sint_to_fp c1) -> c1fp
2528 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
2532 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
2533 SDOperand N0 = N->getOperand(0);
2534 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
2535 MVT::ValueType VT = N->getValueType(0);
2537 // fold (uint_to_fp c1) -> c1fp
2539 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
2543 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
2544 SDOperand N0 = N->getOperand(0);
2545 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2546 MVT::ValueType VT = N->getValueType(0);
2548 // fold (fp_to_sint c1fp) -> c1
2550 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
2554 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
2555 SDOperand N0 = N->getOperand(0);
2556 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2557 MVT::ValueType VT = N->getValueType(0);
2559 // fold (fp_to_uint c1fp) -> c1
2561 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
2565 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
2566 SDOperand N0 = N->getOperand(0);
2567 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2568 MVT::ValueType VT = N->getValueType(0);
2570 // fold (fp_round c1fp) -> c1fp
2572 return DAG.getNode(ISD::FP_ROUND, VT, N0);
2574 // fold (fp_round (fp_extend x)) -> x
2575 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType())
2576 return N0.getOperand(0);
2578 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y)
2579 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) {
2580 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0));
2581 AddToWorkList(Tmp.Val);
2582 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1));
2588 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
2589 SDOperand N0 = N->getOperand(0);
2590 MVT::ValueType VT = N->getValueType(0);
2591 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2592 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2594 // fold (fp_round_inreg c1fp) -> c1fp
2596 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
2597 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
2602 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
2603 SDOperand N0 = N->getOperand(0);
2604 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2605 MVT::ValueType VT = N->getValueType(0);
2607 // fold (fp_extend c1fp) -> c1fp
2609 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
2611 // fold (fpext (load x)) -> (fpext (fpround (extload x)))
2612 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
2613 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) {
2614 LoadSDNode *LN0 = cast<LoadSDNode>(N0);
2615 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(),
2616 LN0->getBasePtr(), LN0->getSrcValue(),
2617 LN0->getSrcValueOffset(),
2619 CombineTo(N, ExtLoad);
2620 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad),
2621 ExtLoad.getValue(1));
2622 return SDOperand(N, 0); // Return N so it doesn't get rechecked!
2629 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
2630 SDOperand N0 = N->getOperand(0);
2631 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2632 MVT::ValueType VT = N->getValueType(0);
2634 // fold (fneg c1) -> -c1
2636 return DAG.getNode(ISD::FNEG, VT, N0);
2637 // fold (fneg (sub x, y)) -> (sub y, x)
2638 if (N0.getOpcode() == ISD::SUB)
2639 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0));
2640 // fold (fneg (fneg x)) -> x
2641 if (N0.getOpcode() == ISD::FNEG)
2642 return N0.getOperand(0);
2646 SDOperand DAGCombiner::visitFABS(SDNode *N) {
2647 SDOperand N0 = N->getOperand(0);
2648 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
2649 MVT::ValueType VT = N->getValueType(0);
2651 // fold (fabs c1) -> fabs(c1)
2653 return DAG.getNode(ISD::FABS, VT, N0);
2654 // fold (fabs (fabs x)) -> (fabs x)
2655 if (N0.getOpcode() == ISD::FABS)
2656 return N->getOperand(0);
2657 // fold (fabs (fneg x)) -> (fabs x)
2658 // fold (fabs (fcopysign x, y)) -> (fabs x)
2659 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN)
2660 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0));
2665 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
2666 SDOperand Chain = N->getOperand(0);
2667 SDOperand N1 = N->getOperand(1);
2668 SDOperand N2 = N->getOperand(2);
2669 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2671 // never taken branch, fold to chain
2672 if (N1C && N1C->isNullValue())
2674 // unconditional branch
2675 if (N1C && N1C->getValue() == 1)
2676 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
2677 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
2679 if (N1.getOpcode() == ISD::SETCC &&
2680 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
2681 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
2682 N1.getOperand(0), N1.getOperand(1), N2);
2687 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
2689 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
2690 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2691 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2693 // Use SimplifySetCC to simplify SETCC's.
2694 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2695 if (Simp.Val) AddToWorkList(Simp.Val);
2697 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2699 // fold br_cc true, dest -> br dest (unconditional branch)
2700 if (SCCC && SCCC->getValue())
2701 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2703 // fold br_cc false, dest -> unconditional fall through
2704 if (SCCC && SCCC->isNullValue())
2705 return N->getOperand(0);
2707 // fold to a simpler setcc
2708 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2709 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2710 Simp.getOperand(2), Simp.getOperand(0),
2711 Simp.getOperand(1), N->getOperand(4));
2716 /// CombineToPreIndexedLoadStore - Try turning a load / store and a
2717 /// pre-indexed load / store when the base pointer is a add or subtract
2718 /// and it has other uses besides the load / store. After the
2719 /// transformation, the new indexed load / store has effectively folded
2720 /// the add / subtract in and all of its other uses are redirected to the
2721 /// new load / store.
2722 bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
2729 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2730 VT = LD->getLoadedVT();
2731 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
2732 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
2734 Ptr = LD->getBasePtr();
2735 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2736 VT = ST->getStoredVT();
2737 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
2738 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
2740 Ptr = ST->getBasePtr();
2745 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail
2746 // out. There is no reason to make this a preinc/predec.
2747 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
2748 Ptr.Val->hasOneUse())
2751 // Ask the target to do addressing mode selection.
2754 ISD::MemIndexedMode AM = ISD::UNINDEXED;
2755 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
2758 // Try turning it into a pre-indexed load / store except when:
2759 // 1) The base is a frame index.
2760 // 2) If N is a store and the ptr is either the same as or is a
2761 // predecessor of the value being stored.
2762 // 3) Another use of base ptr is a predecessor of N. If ptr is folded
2763 // that would create a cycle.
2764 // 4) All uses are load / store ops that use it as base ptr.
2766 // Check #1. Preinc'ing a frame index would require copying the stack pointer
2767 // (plus the implicit offset) to a register to preinc anyway.
2768 if (isa<FrameIndexSDNode>(BasePtr))
2773 SDOperand Val = cast<StoreSDNode>(N)->getValue();
2774 if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val))
2778 // Now check for #2 and #3.
2779 bool RealUse = false;
2780 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
2781 E = Ptr.Val->use_end(); I != E; ++I) {
2785 if (Use->isPredecessor(N))
2788 if (!((Use->getOpcode() == ISD::LOAD &&
2789 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) ||
2790 (Use->getOpcode() == ISD::STORE) &&
2791 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))
2799 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
2801 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
2804 DOUT << "\nReplacing.4 "; DEBUG(N->dump());
2805 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
2807 std::vector<SDNode*> NowDead;
2809 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
2811 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
2814 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
2818 // Nodes can end up on the worklist more than once. Make sure we do
2819 // not process a node that has been replaced.
2820 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
2821 removeFromWorkList(NowDead[i]);
2822 // Finally, since the node is now dead, remove it from the graph.
2825 // Replace the uses of Ptr with uses of the updated base value.
2826 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
2828 removeFromWorkList(Ptr.Val);
2829 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
2830 removeFromWorkList(NowDead[i]);
2831 DAG.DeleteNode(Ptr.Val);
2836 /// CombineToPostIndexedLoadStore - Try combine a load / store with a
2837 /// add / sub of the base pointer node into a post-indexed load / store.
2838 /// The transformation folded the add / subtract into the new indexed
2839 /// load / store effectively and all of its uses are redirected to the
2840 /// new load / store.
2841 bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
2848 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
2849 VT = LD->getLoadedVT();
2850 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
2851 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
2853 Ptr = LD->getBasePtr();
2854 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
2855 VT = ST->getStoredVT();
2856 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
2857 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
2859 Ptr = ST->getBasePtr();
2864 if (Ptr.Val->hasOneUse())
2867 for (SDNode::use_iterator I = Ptr.Val->use_begin(),
2868 E = Ptr.Val->use_end(); I != E; ++I) {
2871 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB))
2876 ISD::MemIndexedMode AM = ISD::UNINDEXED;
2877 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) {
2879 std::swap(BasePtr, Offset);
2883 // Try turning it into a post-indexed load / store except when
2884 // 1) All uses are load / store ops that use it as base ptr.
2885 // 2) Op must be independent of N, i.e. Op is neither a predecessor
2886 // nor a successor of N. Otherwise, if Op is folded that would
2890 bool TryNext = false;
2891 for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
2892 EE = BasePtr.Val->use_end(); II != EE; ++II) {
2897 // If all the uses are load / store addresses, then don't do the
2899 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){
2900 bool RealUse = false;
2901 for (SDNode::use_iterator III = Use->use_begin(),
2902 EEE = Use->use_end(); III != EEE; ++III) {
2903 SDNode *UseUse = *III;
2904 if (!((UseUse->getOpcode() == ISD::LOAD &&
2905 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) ||
2906 (UseUse->getOpcode() == ISD::STORE) &&
2907 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use))
2921 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
2922 SDOperand Result = isLoad
2923 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
2924 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
2927 DOUT << "\nReplacing.5 "; DEBUG(N->dump());
2928 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
2930 std::vector<SDNode*> NowDead;
2932 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
2934 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
2937 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
2941 // Nodes can end up on the worklist more than once. Make sure we do
2942 // not process a node that has been replaced.
2943 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
2944 removeFromWorkList(NowDead[i]);
2945 // Finally, since the node is now dead, remove it from the graph.
2948 // Replace the uses of Use with uses of the updated base value.
2949 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0),
2950 Result.getValue(isLoad ? 1 : 0),
2952 removeFromWorkList(Op);
2953 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
2954 removeFromWorkList(NowDead[i]);
2965 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2966 LoadSDNode *LD = cast<LoadSDNode>(N);
2967 SDOperand Chain = LD->getChain();
2968 SDOperand Ptr = LD->getBasePtr();
2970 // If there are no uses of the loaded value, change uses of the chain value
2971 // into uses of the chain input (i.e. delete the dead load).
2972 if (N->hasNUsesOfValue(0, 0))
2973 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
2975 // If this load is directly stored, replace the load value with the stored
2977 // TODO: Handle store large -> read small portion.
2978 // TODO: Handle TRUNCSTORE/LOADEXT
2979 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2980 if (ISD::isNON_TRUNCStore(Chain.Val)) {
2981 StoreSDNode *PrevST = cast<StoreSDNode>(Chain);
2982 if (PrevST->getBasePtr() == Ptr &&
2983 PrevST->getValue().getValueType() == N->getValueType(0))
2984 return CombineTo(N, Chain.getOperand(1), Chain);
2989 // Walk up chain skipping non-aliasing memory nodes.
2990 SDOperand BetterChain = FindBetterChain(N, Chain);
2992 // If there is a better chain.
2993 if (Chain != BetterChain) {
2996 // Replace the chain to void dependency.
2997 if (LD->getExtensionType() == ISD::NON_EXTLOAD) {
2998 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr,
2999 LD->getSrcValue(), LD->getSrcValueOffset());
3001 ReplLoad = DAG.getExtLoad(LD->getExtensionType(),
3002 LD->getValueType(0),
3003 BetterChain, Ptr, LD->getSrcValue(),
3004 LD->getSrcValueOffset(),
3008 // Create token factor to keep old chain connected.
3009 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other,
3010 Chain, ReplLoad.getValue(1));
3012 // Replace uses with load result and token factor. Don't add users
3014 return CombineTo(N, ReplLoad.getValue(0), Token, false);
3018 // Try transforming N to an indexed load.
3019 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3020 return SDOperand(N, 0);
3025 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
3026 StoreSDNode *ST = cast<StoreSDNode>(N);
3027 SDOperand Chain = ST->getChain();
3028 SDOperand Value = ST->getValue();
3029 SDOperand Ptr = ST->getBasePtr();
3031 // If this is a store of a bit convert, store the input value.
3032 // FIXME: This needs to know that the resultant store does not need a
3033 // higher alignment than the original.
3034 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
3035 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
3036 ST->getSrcValueOffset());
3039 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
3040 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
3041 if (Value.getOpcode() != ISD::TargetConstantFP) {
3043 switch (CFP->getValueType(0)) {
3044 default: assert(0 && "Unknown FP type");
3046 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
3047 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
3048 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3049 ST->getSrcValueOffset());
3053 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
3054 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
3055 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
3056 ST->getSrcValueOffset());
3057 } else if (TLI.isTypeLegal(MVT::i32)) {
3058 // Many FP stores are not make apparent until after legalize, e.g. for
3059 // argument passing. Since this is so common, custom legalize the
3060 // 64-bit integer store into two 32-bit stores.
3061 uint64_t Val = DoubleToBits(CFP->getValue());
3062 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
3063 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
3064 if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
3066 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
3067 ST->getSrcValueOffset());
3068 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3069 DAG.getConstant(4, Ptr.getValueType()));
3070 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
3071 ST->getSrcValueOffset()+4);
3072 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
3080 // Walk up chain skipping non-aliasing memory nodes.
3081 SDOperand BetterChain = FindBetterChain(N, Chain);
3083 // If there is a better chain.
3084 if (Chain != BetterChain) {
3085 // Replace the chain to avoid dependency.
3086 SDOperand ReplStore;
3087 if (ST->isTruncatingStore()) {
3088 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr,
3089 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT());
3091 ReplStore = DAG.getStore(BetterChain, Value, Ptr,
3092 ST->getSrcValue(), ST->getSrcValueOffset());
3095 // Create token to keep both nodes around.
3097 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore);
3099 // Don't add users to work list.
3100 return CombineTo(N, Token, false);
3104 // Try transforming N to an indexed store.
3105 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N))
3106 return SDOperand(N, 0);
3111 SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
3112 SDOperand InVec = N->getOperand(0);
3113 SDOperand InVal = N->getOperand(1);
3114 SDOperand EltNo = N->getOperand(2);
3116 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new
3117 // vector with the inserted element.
3118 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3119 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3120 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3121 if (Elt < Ops.size())
3123 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(),
3124 &Ops[0], Ops.size());
3130 SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) {
3131 SDOperand InVec = N->getOperand(0);
3132 SDOperand InVal = N->getOperand(1);
3133 SDOperand EltNo = N->getOperand(2);
3134 SDOperand NumElts = N->getOperand(3);
3135 SDOperand EltType = N->getOperand(4);
3137 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new
3138 // vector with the inserted element.
3139 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) {
3140 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
3141 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end());
3142 if (Elt < Ops.size()-2)
3144 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(),
3145 &Ops[0], Ops.size());
3151 SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
3152 unsigned NumInScalars = N->getNumOperands()-2;
3153 SDOperand NumElts = N->getOperand(NumInScalars);
3154 SDOperand EltType = N->getOperand(NumInScalars+1);
3156 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT
3157 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most
3158 // two distinct vectors, turn this into a shuffle node.
3159 SDOperand VecIn1, VecIn2;
3160 for (unsigned i = 0; i != NumInScalars; ++i) {
3161 // Ignore undef inputs.
3162 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3164 // If this input is something other than a VEXTRACT_VECTOR_ELT with a
3165 // constant index, bail out.
3166 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT ||
3167 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) {
3168 VecIn1 = VecIn2 = SDOperand(0, 0);
3172 // If the input vector type disagrees with the result of the vbuild_vector,
3173 // we can't make a shuffle.
3174 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0);
3175 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts ||
3176 *(ExtractedFromVec.Val->op_end()-1) != EltType) {
3177 VecIn1 = VecIn2 = SDOperand(0, 0);
3181 // Otherwise, remember this. We allow up to two distinct input vectors.
3182 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2)
3185 if (VecIn1.Val == 0) {
3186 VecIn1 = ExtractedFromVec;
3187 } else if (VecIn2.Val == 0) {
3188 VecIn2 = ExtractedFromVec;
3191 VecIn1 = VecIn2 = SDOperand(0, 0);
3196 // If everything is good, we can make a shuffle operation.
3198 SmallVector<SDOperand, 8> BuildVecIndices;
3199 for (unsigned i = 0; i != NumInScalars; ++i) {
3200 if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
3201 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
3205 SDOperand Extract = N->getOperand(i);
3207 // If extracting from the first vector, just use the index directly.
3208 if (Extract.getOperand(0) == VecIn1) {
3209 BuildVecIndices.push_back(Extract.getOperand(1));
3213 // Otherwise, use InIdx + VecSize
3214 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue();
3215 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
3218 // Add count and size info.
3219 BuildVecIndices.push_back(NumElts);
3220 BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
3222 // Return the new VVECTOR_SHUFFLE node.
3228 // Use an undef vbuild_vector as input for the second operand.
3229 std::vector<SDOperand> UnOps(NumInScalars,
3230 DAG.getNode(ISD::UNDEF,
3231 cast<VTSDNode>(EltType)->getVT()));
3232 UnOps.push_back(NumElts);
3233 UnOps.push_back(EltType);
3234 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3235 &UnOps[0], UnOps.size());
3236 AddToWorkList(Ops[1].Val);
3238 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3239 &BuildVecIndices[0], BuildVecIndices.size());
3242 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5);
3248 SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
3249 SDOperand ShufMask = N->getOperand(2);
3250 unsigned NumElts = ShufMask.getNumOperands();
3252 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3253 bool isIdentity = true;
3254 for (unsigned i = 0; i != NumElts; ++i) {
3255 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3256 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3261 if (isIdentity) return N->getOperand(0);
3263 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3265 for (unsigned i = 0; i != NumElts; ++i) {
3266 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3267 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3272 if (isIdentity) return N->getOperand(1);
3274 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3276 bool isUnary = true;
3277 bool isSplat = true;
3279 unsigned BaseIdx = 0;
3280 for (unsigned i = 0; i != NumElts; ++i)
3281 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3282 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3283 int V = (Idx < NumElts) ? 0 : 1;
3297 SDOperand N0 = N->getOperand(0);
3298 SDOperand N1 = N->getOperand(1);
3299 // Normalize unary shuffle so the RHS is undef.
3300 if (isUnary && VecNum == 1)
3303 // If it is a splat, check if the argument vector is a build_vector with
3304 // all scalar elements the same.
3307 if (V->getOpcode() == ISD::BIT_CONVERT)
3308 V = V->getOperand(0).Val;
3309 if (V->getOpcode() == ISD::BUILD_VECTOR) {
3310 unsigned NumElems = V->getNumOperands()-2;
3311 if (NumElems > BaseIdx) {
3313 bool AllSame = true;
3314 for (unsigned i = 0; i != NumElems; ++i) {
3315 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3316 Base = V->getOperand(i);
3320 // Splat of <u, u, u, u>, return <u, u, u, u>
3323 for (unsigned i = 0; i != NumElems; ++i) {
3324 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3325 V->getOperand(i) != Base) {
3330 // Splat of <x, x, x, x>, return <x, x, x, x>
3337 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3339 if (isUnary || N0 == N1) {
3340 if (N0.getOpcode() == ISD::UNDEF)
3341 return DAG.getNode(ISD::UNDEF, N->getValueType(0));
3342 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3344 SmallVector<SDOperand, 8> MappedOps;
3345 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
3346 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3347 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3348 MappedOps.push_back(ShufMask.getOperand(i));
3351 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3352 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3355 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
3356 &MappedOps[0], MappedOps.size());
3357 AddToWorkList(ShufMask.Val);
3358 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
3360 DAG.getNode(ISD::UNDEF, N->getValueType(0)),
3367 SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) {
3368 SDOperand ShufMask = N->getOperand(2);
3369 unsigned NumElts = ShufMask.getNumOperands()-2;
3371 // If the shuffle mask is an identity operation on the LHS, return the LHS.
3372 bool isIdentity = true;
3373 for (unsigned i = 0; i != NumElts; ++i) {
3374 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3375 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) {
3380 if (isIdentity) return N->getOperand(0);
3382 // If the shuffle mask is an identity operation on the RHS, return the RHS.
3384 for (unsigned i = 0; i != NumElts; ++i) {
3385 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF &&
3386 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) {
3391 if (isIdentity) return N->getOperand(1);
3393 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not
3395 bool isUnary = true;
3396 bool isSplat = true;
3398 unsigned BaseIdx = 0;
3399 for (unsigned i = 0; i != NumElts; ++i)
3400 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) {
3401 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue();
3402 int V = (Idx < NumElts) ? 0 : 1;
3416 SDOperand N0 = N->getOperand(0);
3417 SDOperand N1 = N->getOperand(1);
3418 // Normalize unary shuffle so the RHS is undef.
3419 if (isUnary && VecNum == 1)
3422 // If it is a splat, check if the argument vector is a build_vector with
3423 // all scalar elements the same.
3427 // If this is a vbit convert that changes the element type of the vector but
3428 // not the number of vector elements, look through it. Be careful not to
3429 // look though conversions that change things like v4f32 to v2f64.
3430 if (V->getOpcode() == ISD::VBIT_CONVERT) {
3431 SDOperand ConvInput = V->getOperand(0);
3432 if (ConvInput.getValueType() == MVT::Vector &&
3434 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2))
3438 if (V->getOpcode() == ISD::VBUILD_VECTOR) {
3439 unsigned NumElems = V->getNumOperands()-2;
3440 if (NumElems > BaseIdx) {
3442 bool AllSame = true;
3443 for (unsigned i = 0; i != NumElems; ++i) {
3444 if (V->getOperand(i).getOpcode() != ISD::UNDEF) {
3445 Base = V->getOperand(i);
3449 // Splat of <u, u, u, u>, return <u, u, u, u>
3452 for (unsigned i = 0; i != NumElems; ++i) {
3453 if (V->getOperand(i).getOpcode() != ISD::UNDEF &&
3454 V->getOperand(i) != Base) {
3459 // Splat of <x, x, x, x>, return <x, x, x, x>
3466 // If it is a unary or the LHS and the RHS are the same node, turn the RHS
3468 if (isUnary || N0 == N1) {
3469 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
3471 SmallVector<SDOperand, 8> MappedOps;
3472 for (unsigned i = 0; i != NumElts; ++i) {
3473 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF ||
3474 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) {
3475 MappedOps.push_back(ShufMask.getOperand(i));
3478 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
3479 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
3482 // Add the type/#elts values.
3483 MappedOps.push_back(ShufMask.getOperand(NumElts));
3484 MappedOps.push_back(ShufMask.getOperand(NumElts+1));
3486 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(),
3487 &MappedOps[0], MappedOps.size());
3488 AddToWorkList(ShufMask.Val);
3490 // Build the undef vector.
3491 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType());
3492 for (unsigned i = 0; i != NumElts; ++i)
3493 MappedOps[i] = UDVal;
3494 MappedOps[NumElts ] = *(N0.Val->op_end()-2);
3495 MappedOps[NumElts+1] = *(N0.Val->op_end()-1);
3496 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3497 &MappedOps[0], MappedOps.size());
3499 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3500 N0, UDVal, ShufMask,
3501 MappedOps[NumElts], MappedOps[NumElts+1]);
3507 /// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform
3508 /// a VAND to a vector_shuffle with the destination vector and a zero vector.
3509 /// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
3510 /// vector_shuffle V, Zero, <0, 4, 2, 4>
3511 SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
3512 SDOperand LHS = N->getOperand(0);
3513 SDOperand RHS = N->getOperand(1);
3514 if (N->getOpcode() == ISD::VAND) {
3515 SDOperand DstVecSize = *(LHS.Val->op_end()-2);
3516 SDOperand DstVecEVT = *(LHS.Val->op_end()-1);
3517 if (RHS.getOpcode() == ISD::VBIT_CONVERT)
3518 RHS = RHS.getOperand(0);
3519 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3520 std::vector<SDOperand> IdxOps;
3521 unsigned NumOps = RHS.getNumOperands();
3522 unsigned NumElts = NumOps-2;
3523 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT();
3524 for (unsigned i = 0; i != NumElts; ++i) {
3525 SDOperand Elt = RHS.getOperand(i);
3526 if (!isa<ConstantSDNode>(Elt))
3528 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue())
3529 IdxOps.push_back(DAG.getConstant(i, EVT));
3530 else if (cast<ConstantSDNode>(Elt)->isNullValue())
3531 IdxOps.push_back(DAG.getConstant(NumElts, EVT));
3536 // Let's see if the target supports this vector_shuffle.
3537 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG))
3540 // Return the new VVECTOR_SHUFFLE node.
3541 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32);
3542 SDOperand EVTNode = DAG.getValueType(EVT);
3543 std::vector<SDOperand> Ops;
3544 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode,
3547 AddToWorkList(LHS.Val);
3548 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT));
3549 ZeroOps.push_back(NumEltsNode);
3550 ZeroOps.push_back(EVTNode);
3551 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3552 &ZeroOps[0], ZeroOps.size()));
3553 IdxOps.push_back(NumEltsNode);
3554 IdxOps.push_back(EVTNode);
3555 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector,
3556 &IdxOps[0], IdxOps.size()));
3557 Ops.push_back(NumEltsNode);
3558 Ops.push_back(EVTNode);
3559 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector,
3560 &Ops[0], Ops.size());
3561 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) {
3562 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result,
3563 DstVecSize, DstVecEVT);
3571 /// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates
3572 /// the scalar operation of the vop if it is operating on an integer vector
3573 /// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD).
3574 SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp,
3575 ISD::NodeType FPOp) {
3576 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT();
3577 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp;
3578 SDOperand LHS = N->getOperand(0);
3579 SDOperand RHS = N->getOperand(1);
3580 SDOperand Shuffle = XformToShuffleWithZero(N);
3581 if (Shuffle.Val) return Shuffle;
3583 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold
3585 if (LHS.getOpcode() == ISD::VBUILD_VECTOR &&
3586 RHS.getOpcode() == ISD::VBUILD_VECTOR) {
3587 SmallVector<SDOperand, 8> Ops;
3588 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) {
3589 SDOperand LHSOp = LHS.getOperand(i);
3590 SDOperand RHSOp = RHS.getOperand(i);
3591 // If these two elements can't be folded, bail out.
3592 if ((LHSOp.getOpcode() != ISD::UNDEF &&
3593 LHSOp.getOpcode() != ISD::Constant &&
3594 LHSOp.getOpcode() != ISD::ConstantFP) ||
3595 (RHSOp.getOpcode() != ISD::UNDEF &&
3596 RHSOp.getOpcode() != ISD::Constant &&
3597 RHSOp.getOpcode() != ISD::ConstantFP))
3599 // Can't fold divide by zero.
3600 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) {
3601 if ((RHSOp.getOpcode() == ISD::Constant &&
3602 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) ||
3603 (RHSOp.getOpcode() == ISD::ConstantFP &&
3604 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue()))
3607 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp));
3608 AddToWorkList(Ops.back().Val);
3609 assert((Ops.back().getOpcode() == ISD::UNDEF ||
3610 Ops.back().getOpcode() == ISD::Constant ||
3611 Ops.back().getOpcode() == ISD::ConstantFP) &&
3612 "Scalar binop didn't fold!");
3615 if (Ops.size() == LHS.getNumOperands()-2) {
3616 Ops.push_back(*(LHS.Val->op_end()-2));
3617 Ops.push_back(*(LHS.Val->op_end()-1));
3618 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size());
3625 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
3626 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
3628 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
3629 cast<CondCodeSDNode>(N0.getOperand(2))->get());
3630 // If we got a simplified select_cc node back from SimplifySelectCC, then
3631 // break it down into a new SETCC node, and a new SELECT node, and then return
3632 // the SELECT node, since we were called with a SELECT node.
3634 // Check to see if we got a select_cc back (to turn into setcc/select).
3635 // Otherwise, just return whatever node we got back, like fabs.
3636 if (SCC.getOpcode() == ISD::SELECT_CC) {
3637 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
3638 SCC.getOperand(0), SCC.getOperand(1),
3640 AddToWorkList(SETCC.Val);
3641 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
3642 SCC.getOperand(3), SETCC);
3649 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
3650 /// are the two values being selected between, see if we can simplify the
3651 /// select. Callers of this should assume that TheSelect is deleted if this
3652 /// returns true. As such, they should return the appropriate thing (e.g. the
3653 /// node) back to the top-level of the DAG combiner loop to avoid it being
3656 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
3659 // If this is a select from two identical things, try to pull the operation
3660 // through the select.
3661 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
3662 // If this is a load and the token chain is identical, replace the select
3663 // of two loads with a load through a select of the address to load from.
3664 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
3665 // constants have been dropped into the constant pool.
3666 if (LHS.getOpcode() == ISD::LOAD &&
3667 // Token chains must be identical.
3668 LHS.getOperand(0) == RHS.getOperand(0)) {
3669 LoadSDNode *LLD = cast<LoadSDNode>(LHS);
3670 LoadSDNode *RLD = cast<LoadSDNode>(RHS);
3672 // If this is an EXTLOAD, the VT's must match.
3673 if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
3674 // FIXME: this conflates two src values, discarding one. This is not
3675 // the right thing to do, but nothing uses srcvalues now. When they do,
3676 // turn SrcValue into a list of locations.
3678 if (TheSelect->getOpcode() == ISD::SELECT)
3679 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
3680 TheSelect->getOperand(0), LLD->getBasePtr(),
3683 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
3684 TheSelect->getOperand(0),
3685 TheSelect->getOperand(1),
3686 LLD->getBasePtr(), RLD->getBasePtr(),
3687 TheSelect->getOperand(4));
3690 if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
3691 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
3692 Addr,LLD->getSrcValue(), LLD->getSrcValueOffset());
3694 Load = DAG.getExtLoad(LLD->getExtensionType(),
3695 TheSelect->getValueType(0),
3696 LLD->getChain(), Addr, LLD->getSrcValue(),
3697 LLD->getSrcValueOffset(),
3698 LLD->getLoadedVT());
3700 // Users of the select now use the result of the load.
3701 CombineTo(TheSelect, Load);
3703 // Users of the old loads now use the new load's chain. We know the
3704 // old-load value is dead now.
3705 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
3706 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
3715 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
3716 SDOperand N2, SDOperand N3,
3719 MVT::ValueType VT = N2.getValueType();
3720 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
3721 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
3722 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
3724 // Determine if the condition we're dealing with is constant
3725 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
3726 if (SCC.Val) AddToWorkList(SCC.Val);
3727 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
3729 // fold select_cc true, x, y -> x
3730 if (SCCC && SCCC->getValue())
3732 // fold select_cc false, x, y -> y
3733 if (SCCC && SCCC->getValue() == 0)
3736 // Check to see if we can simplify the select into an fabs node
3737 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
3738 // Allow either -0.0 or 0.0
3739 if (CFP->getValue() == 0.0) {
3740 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
3741 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
3742 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
3743 N2 == N3.getOperand(0))
3744 return DAG.getNode(ISD::FABS, VT, N0);
3746 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
3747 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
3748 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
3749 N2.getOperand(0) == N3)
3750 return DAG.getNode(ISD::FABS, VT, N3);
3754 // Check to see if we can perform the "gzip trick", transforming
3755 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
3756 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
3757 MVT::isInteger(N0.getValueType()) &&
3758 MVT::isInteger(N2.getValueType()) &&
3759 (N1C->isNullValue() || // (a < 0) ? b : 0
3760 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
3761 MVT::ValueType XType = N0.getValueType();
3762 MVT::ValueType AType = N2.getValueType();
3763 if (XType >= AType) {
3764 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
3765 // single-bit constant.
3766 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
3767 unsigned ShCtV = Log2_64(N2C->getValue());
3768 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
3769 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
3770 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
3771 AddToWorkList(Shift.Val);
3772 if (XType > AType) {
3773 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3774 AddToWorkList(Shift.Val);
3776 return DAG.getNode(ISD::AND, AType, Shift, N2);
3778 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3779 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3780 TLI.getShiftAmountTy()));
3781 AddToWorkList(Shift.Val);
3782 if (XType > AType) {
3783 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
3784 AddToWorkList(Shift.Val);
3786 return DAG.getNode(ISD::AND, AType, Shift, N2);
3790 // fold select C, 16, 0 -> shl C, 4
3791 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
3792 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
3793 // Get a SetCC of the condition
3794 // FIXME: Should probably make sure that setcc is legal if we ever have a
3795 // target where it isn't.
3796 SDOperand Temp, SCC;
3797 // cast from setcc result type to select result type
3798 if (AfterLegalize) {
3799 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3800 if (N2.getValueType() < SCC.getValueType())
3801 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
3803 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3805 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
3806 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
3808 AddToWorkList(SCC.Val);
3809 AddToWorkList(Temp.Val);
3810 // shl setcc result by log2 n2c
3811 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
3812 DAG.getConstant(Log2_64(N2C->getValue()),
3813 TLI.getShiftAmountTy()));
3816 // Check to see if this is the equivalent of setcc
3817 // FIXME: Turn all of these into setcc if setcc if setcc is legal
3818 // otherwise, go ahead with the folds.
3819 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
3820 MVT::ValueType XType = N0.getValueType();
3821 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
3822 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
3823 if (Res.getValueType() != VT)
3824 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
3828 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
3829 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
3830 TLI.isOperationLegal(ISD::CTLZ, XType)) {
3831 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
3832 return DAG.getNode(ISD::SRL, XType, Ctlz,
3833 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
3834 TLI.getShiftAmountTy()));
3836 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
3837 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
3838 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
3840 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
3841 DAG.getConstant(~0ULL, XType));
3842 return DAG.getNode(ISD::SRL, XType,
3843 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
3844 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3845 TLI.getShiftAmountTy()));
3847 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
3848 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
3849 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
3850 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3851 TLI.getShiftAmountTy()));
3852 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
3856 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
3857 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
3858 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
3859 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
3860 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
3861 MVT::ValueType XType = N0.getValueType();
3862 if (SubC->isNullValue() && MVT::isInteger(XType)) {
3863 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
3864 DAG.getConstant(MVT::getSizeInBits(XType)-1,
3865 TLI.getShiftAmountTy()));
3866 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
3867 AddToWorkList(Shift.Val);
3868 AddToWorkList(Add.Val);
3869 return DAG.getNode(ISD::XOR, XType, Add, Shift);
3877 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
3878 SDOperand N1, ISD::CondCode Cond,
3879 bool foldBooleans) {
3880 // These setcc operations always fold.
3884 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
3886 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
3889 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
3890 uint64_t C1 = N1C->getValue();
3891 if (isa<ConstantSDNode>(N0.Val)) {
3892 return DAG.FoldSetCC(VT, N0, N1, Cond);
3894 // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
3895 // equality comparison, then we're just comparing whether X itself is
3897 if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
3898 N0.getOperand(0).getOpcode() == ISD::CTLZ &&
3899 N0.getOperand(1).getOpcode() == ISD::Constant) {
3900 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
3901 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
3902 ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType()))) {
3903 if ((C1 == 0) == (Cond == ISD::SETEQ)) {
3904 // (srl (ctlz x), 5) == 0 -> X != 0
3905 // (srl (ctlz x), 5) != 1 -> X != 0
3908 // (srl (ctlz x), 5) != 0 -> X == 0
3909 // (srl (ctlz x), 5) == 1 -> X == 0
3912 SDOperand Zero = DAG.getConstant(0, N0.getValueType());
3913 return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
3918 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
3919 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
3920 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
3922 // If the comparison constant has bits in the upper part, the
3923 // zero-extended value could never match.
3924 if (C1 & (~0ULL << InSize)) {
3925 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
3929 case ISD::SETEQ: return DAG.getConstant(0, VT);
3932 case ISD::SETNE: return DAG.getConstant(1, VT);
3935 // True if the sign bit of C1 is set.
3936 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
3939 // True if the sign bit of C1 isn't set.
3940 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
3946 // Otherwise, we can perform the comparison with the low bits.
3954 return DAG.getSetCC(VT, N0.getOperand(0),
3955 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
3958 break; // todo, be more careful with signed comparisons
3960 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
3961 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3962 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
3963 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
3964 MVT::ValueType ExtDstTy = N0.getValueType();
3965 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
3967 // If the extended part has any inconsistent bits, it cannot ever
3968 // compare equal. In other words, they have to be all ones or all
3971 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
3972 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
3973 return DAG.getConstant(Cond == ISD::SETNE, VT);
3976 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
3977 if (Op0Ty == ExtSrcTy) {
3978 ZextOp = N0.getOperand(0);
3980 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
3981 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
3982 DAG.getConstant(Imm, Op0Ty));
3984 AddToWorkList(ZextOp.Val);
3985 // Otherwise, make this a use of a zext.
3986 return DAG.getSetCC(VT, ZextOp,
3987 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
3990 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
3991 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
3993 // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC
3994 if (N0.getOpcode() == ISD::SETCC) {
3995 bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getValue() != 1);
3999 // Invert the condition.
4000 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
4001 CC = ISD::getSetCCInverse(CC,
4002 MVT::isInteger(N0.getOperand(0).getValueType()));
4003 return DAG.getSetCC(VT, N0.getOperand(0), N0.getOperand(1), CC);
4006 if ((N0.getOpcode() == ISD::XOR ||
4007 (N0.getOpcode() == ISD::AND &&
4008 N0.getOperand(0).getOpcode() == ISD::XOR &&
4009 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
4010 isa<ConstantSDNode>(N0.getOperand(1)) &&
4011 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
4012 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We
4013 // can only do this if the top bits are known zero.
4014 if (TLI.MaskedValueIsZero(N0,
4015 MVT::getIntVTBitMask(N0.getValueType())-1)){
4016 // Okay, get the un-inverted input value.
4018 if (N0.getOpcode() == ISD::XOR)
4019 Val = N0.getOperand(0);
4021 assert(N0.getOpcode() == ISD::AND &&
4022 N0.getOperand(0).getOpcode() == ISD::XOR);
4023 // ((X^1)&1)^1 -> X & 1
4024 Val = DAG.getNode(ISD::AND, N0.getValueType(),
4025 N0.getOperand(0).getOperand(0),
4028 return DAG.getSetCC(VT, Val, N1,
4029 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
4034 uint64_t MinVal, MaxVal;
4035 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
4036 if (ISD::isSignedIntSetCC(Cond)) {
4037 MinVal = 1ULL << (OperandBitSize-1);
4038 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
4039 MaxVal = ~0ULL >> (65-OperandBitSize);
4044 MaxVal = ~0ULL >> (64-OperandBitSize);
4047 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
4048 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
4049 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
4050 --C1; // X >= C0 --> X > (C0-1)
4051 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
4052 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
4055 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
4056 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
4057 ++C1; // X <= C0 --> X < (C0+1)
4058 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
4059 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
4062 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
4063 return DAG.getConstant(0, VT); // X < MIN --> false
4065 // Canonicalize setgt X, Min --> setne X, Min
4066 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
4067 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
4068 // Canonicalize setlt X, Max --> setne X, Max
4069 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
4070 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
4072 // If we have setult X, 1, turn it into seteq X, 0
4073 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
4074 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
4076 // If we have setugt X, Max-1, turn it into seteq X, Max
4077 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
4078 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
4081 // If we have "setcc X, C0", check to see if we can shrink the immediate
4084 // SETUGT X, SINTMAX -> SETLT X, 0
4085 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
4086 C1 == (~0ULL >> (65-OperandBitSize)))
4087 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
4090 // FIXME: Implement the rest of these.
4092 // Fold bit comparisons when we can.
4093 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
4094 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
4095 if (ConstantSDNode *AndRHS =
4096 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4097 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
4098 // Perform the xform if the AND RHS is a single bit.
4099 if (isPowerOf2_64(AndRHS->getValue())) {
4100 return DAG.getNode(ISD::SRL, VT, N0,
4101 DAG.getConstant(Log2_64(AndRHS->getValue()),
4102 TLI.getShiftAmountTy()));
4104 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
4105 // (X & 8) == 8 --> (X & 8) >> 3
4106 // Perform the xform if C1 is a single bit.
4107 if (isPowerOf2_64(C1)) {
4108 return DAG.getNode(ISD::SRL, VT, N0,
4109 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
4114 } else if (isa<ConstantSDNode>(N0.Val)) {
4115 // Ensure that the constant occurs on the RHS.
4116 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
4119 if (isa<ConstantFPSDNode>(N0.Val)) {
4120 // Constant fold or commute setcc.
4121 SDOperand O = DAG.FoldSetCC(VT, N0, N1, Cond);
4122 if (O.Val) return O;
4126 // We can always fold X == X for integer setcc's.
4127 if (MVT::isInteger(N0.getValueType()))
4128 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
4129 unsigned UOF = ISD::getUnorderedFlavor(Cond);
4130 if (UOF == 2) // FP operators that are undefined on NaNs.
4131 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
4132 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
4133 return DAG.getConstant(UOF, VT);
4134 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
4135 // if it is not already.
4136 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
4137 if (NewCond != Cond)
4138 return DAG.getSetCC(VT, N0, N1, NewCond);
4141 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
4142 MVT::isInteger(N0.getValueType())) {
4143 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
4144 N0.getOpcode() == ISD::XOR) {
4145 // Simplify (X+Y) == (X+Z) --> Y == Z
4146 if (N0.getOpcode() == N1.getOpcode()) {
4147 if (N0.getOperand(0) == N1.getOperand(0))
4148 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
4149 if (N0.getOperand(1) == N1.getOperand(1))
4150 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
4151 if (DAG.isCommutativeBinOp(N0.getOpcode())) {
4152 // If X op Y == Y op X, try other combinations.
4153 if (N0.getOperand(0) == N1.getOperand(1))
4154 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
4155 if (N0.getOperand(1) == N1.getOperand(0))
4156 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
4160 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
4161 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
4162 // Turn (X+C1) == C2 --> X == C2-C1
4163 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
4164 return DAG.getSetCC(VT, N0.getOperand(0),
4165 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
4166 N0.getValueType()), Cond);
4169 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
4170 if (N0.getOpcode() == ISD::XOR)
4171 // If we know that all of the inverted bits are zero, don't bother
4172 // performing the inversion.
4173 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
4174 return DAG.getSetCC(VT, N0.getOperand(0),
4175 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
4176 N0.getValueType()), Cond);
4179 // Turn (C1-X) == C2 --> X == C1-C2
4180 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
4181 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
4182 return DAG.getSetCC(VT, N0.getOperand(1),
4183 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
4184 N0.getValueType()), Cond);
4189 // Simplify (X+Z) == X --> Z == 0
4190 if (N0.getOperand(0) == N1)
4191 return DAG.getSetCC(VT, N0.getOperand(1),
4192 DAG.getConstant(0, N0.getValueType()), Cond);
4193 if (N0.getOperand(1) == N1) {
4194 if (DAG.isCommutativeBinOp(N0.getOpcode()))
4195 return DAG.getSetCC(VT, N0.getOperand(0),
4196 DAG.getConstant(0, N0.getValueType()), Cond);
4198 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
4199 // (Z-X) == X --> Z == X<<1
4200 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
4202 DAG.getConstant(1,TLI.getShiftAmountTy()));
4203 AddToWorkList(SH.Val);
4204 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
4209 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
4210 N1.getOpcode() == ISD::XOR) {
4211 // Simplify X == (X+Z) --> Z == 0
4212 if (N1.getOperand(0) == N0) {
4213 return DAG.getSetCC(VT, N1.getOperand(1),
4214 DAG.getConstant(0, N1.getValueType()), Cond);
4215 } else if (N1.getOperand(1) == N0) {
4216 if (DAG.isCommutativeBinOp(N1.getOpcode())) {
4217 return DAG.getSetCC(VT, N1.getOperand(0),
4218 DAG.getConstant(0, N1.getValueType()), Cond);
4220 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
4221 // X == (Z-X) --> X<<1 == Z
4222 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
4223 DAG.getConstant(1,TLI.getShiftAmountTy()));
4224 AddToWorkList(SH.Val);
4225 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
4231 // Fold away ALL boolean setcc's.
4233 if (N0.getValueType() == MVT::i1 && foldBooleans) {
4235 default: assert(0 && "Unknown integer setcc!");
4236 case ISD::SETEQ: // X == Y -> (X^Y)^1
4237 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
4238 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
4239 AddToWorkList(Temp.Val);
4241 case ISD::SETNE: // X != Y --> (X^Y)
4242 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
4244 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
4245 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
4246 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
4247 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
4248 AddToWorkList(Temp.Val);
4250 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
4251 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
4252 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
4253 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
4254 AddToWorkList(Temp.Val);
4256 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
4257 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
4258 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
4259 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
4260 AddToWorkList(Temp.Val);
4262 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
4263 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
4264 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
4265 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
4268 if (VT != MVT::i1) {
4269 AddToWorkList(N0.Val);
4270 // FIXME: If running after legalize, we probably can't do this.
4271 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
4276 // Could not fold it.
4280 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
4281 /// return a DAG expression to select that will generate the same value by
4282 /// multiplying by a magic number. See:
4283 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4284 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
4285 std::vector<SDNode*> Built;
4286 SDOperand S = TLI.BuildSDIV(N, DAG, &Built);
4288 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4294 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
4295 /// return a DAG expression to select that will generate the same value by
4296 /// multiplying by a magic number. See:
4297 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
4298 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
4299 std::vector<SDNode*> Built;
4300 SDOperand S = TLI.BuildUDIV(N, DAG, &Built);
4302 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end();
4308 /// FindBaseOffset - Return true if base is known not to alias with anything
4309 /// but itself. Provides base object and offset as results.
4310 static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) {
4311 // Assume it is a primitive operation.
4312 Base = Ptr; Offset = 0;
4314 // If it's an adding a simple constant then integrate the offset.
4315 if (Base.getOpcode() == ISD::ADD) {
4316 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
4317 Base = Base.getOperand(0);
4318 Offset += C->getValue();
4322 // If it's any of the following then it can't alias with anything but itself.
4323 return isa<FrameIndexSDNode>(Base) ||
4324 isa<ConstantPoolSDNode>(Base) ||
4325 isa<GlobalAddressSDNode>(Base);
4328 /// isAlias - Return true if there is any possibility that the two addresses
4330 bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1,
4331 const Value *SrcValue1, int SrcValueOffset1,
4332 SDOperand Ptr2, int64_t Size2,
4333 const Value *SrcValue2, int SrcValueOffset2)
4335 // If they are the same then they must be aliases.
4336 if (Ptr1 == Ptr2) return true;
4338 // Gather base node and offset information.
4339 SDOperand Base1, Base2;
4340 int64_t Offset1, Offset2;
4341 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1);
4342 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2);
4344 // If they have a same base address then...
4345 if (Base1 == Base2) {
4346 // Check to see if the addresses overlap.
4347 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1);
4350 // If we know both bases then they can't alias.
4351 if (KnownBase1 && KnownBase2) return false;
4353 if (CombinerGlobalAA) {
4354 // Use alias analysis information.
4355 int Overlap1 = Size1 + SrcValueOffset1 + Offset1;
4356 int Overlap2 = Size2 + SrcValueOffset2 + Offset2;
4357 AliasAnalysis::AliasResult AAResult =
4358 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2);
4359 if (AAResult == AliasAnalysis::NoAlias)
4363 // Otherwise we have to assume they alias.
4367 /// FindAliasInfo - Extracts the relevant alias information from the memory
4368 /// node. Returns true if the operand was a load.
4369 bool DAGCombiner::FindAliasInfo(SDNode *N,
4370 SDOperand &Ptr, int64_t &Size,
4371 const Value *&SrcValue, int &SrcValueOffset) {
4372 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4373 Ptr = LD->getBasePtr();
4374 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3;
4375 SrcValue = LD->getSrcValue();
4376 SrcValueOffset = LD->getSrcValueOffset();
4378 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4379 Ptr = ST->getBasePtr();
4380 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3;
4381 SrcValue = ST->getSrcValue();
4382 SrcValueOffset = ST->getSrcValueOffset();
4384 assert(0 && "FindAliasInfo expected a memory operand");
4390 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
4391 /// looking for aliasing nodes and adding them to the Aliases vector.
4392 void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain,
4393 SmallVector<SDOperand, 8> &Aliases) {
4394 SmallVector<SDOperand, 8> Chains; // List of chains to visit.
4395 std::set<SDNode *> Visited; // Visited node set.
4397 // Get alias information for node.
4400 const Value *SrcValue;
4402 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset);
4405 Chains.push_back(OriginalChain);
4407 // Look at each chain and determine if it is an alias. If so, add it to the
4408 // aliases list. If not, then continue up the chain looking for the next
4410 while (!Chains.empty()) {
4411 SDOperand Chain = Chains.back();
4414 // Don't bother if we've been before.
4415 if (Visited.find(Chain.Val) != Visited.end()) continue;
4416 Visited.insert(Chain.Val);
4418 switch (Chain.getOpcode()) {
4419 case ISD::EntryToken:
4420 // Entry token is ideal chain operand, but handled in FindBetterChain.
4425 // Get alias information for Chain.
4428 const Value *OpSrcValue;
4429 int OpSrcValueOffset;
4430 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize,
4431 OpSrcValue, OpSrcValueOffset);
4433 // If chain is alias then stop here.
4434 if (!(IsLoad && IsOpLoad) &&
4435 isAlias(Ptr, Size, SrcValue, SrcValueOffset,
4436 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) {
4437 Aliases.push_back(Chain);
4439 // Look further up the chain.
4440 Chains.push_back(Chain.getOperand(0));
4441 // Clean up old chain.
4442 AddToWorkList(Chain.Val);
4447 case ISD::TokenFactor:
4448 // We have to check each of the operands of the token factor, so we queue
4449 // then up. Adding the operands to the queue (stack) in reverse order
4450 // maintains the original order and increases the likelihood that getNode
4451 // will find a matching token factor (CSE.)
4452 for (unsigned n = Chain.getNumOperands(); n;)
4453 Chains.push_back(Chain.getOperand(--n));
4454 // Eliminate the token factor if we can.
4455 AddToWorkList(Chain.Val);
4459 // For all other instructions we will just have to take what we can get.
4460 Aliases.push_back(Chain);
4466 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking
4467 /// for a better chain (aliasing node.)
4468 SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) {
4469 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor.
4471 // Accumulate all the aliases to this node.
4472 GatherAllAliases(N, OldChain, Aliases);
4474 if (Aliases.size() == 0) {
4475 // If no operands then chain to entry token.
4476 return DAG.getEntryNode();
4477 } else if (Aliases.size() == 1) {
4478 // If a single operand then chain to it. We don't need to revisit it.
4482 // Construct a custom tailored token factor.
4483 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4484 &Aliases[0], Aliases.size());
4486 // Make sure the old chain gets cleaned up.
4487 if (NewChain != OldChain) AddToWorkList(OldChain.Val);
4492 // SelectionDAG::Combine - This is the entry point for the file.
4494 void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
4495 /// run - This is the main entry point to this class.
4497 DAGCombiner(*this, AA).Run(RunningAfterLegalize);