1 //===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
11 // both before and after the DAG is legalized.
13 // FIXME: Missing folds
14 // sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15 // a sequence of multiplies, shifts, and adds. This should be controlled by
16 // some kind of hint from the target that int div is expensive.
17 // various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
19 // FIXME: Should add a corresponding version of fold AND with
20 // ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
23 // FIXME: select C, pow2, pow2 -> something smart
24 // FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
25 // FIXME: Dead stores -> nuke
26 // FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!)
27 // FIXME: mul (x, const) -> shifts + adds
28 // FIXME: undef values
29 // FIXME: make truncate see through SIGN_EXTEND and AND
30 // FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
31 // FIXME: verify that getNode can't return extends with an operand whose type
32 // is >= to that of the extend.
33 // FIXME: divide by zero is currently left unfolded. do we want to turn this
35 // FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
37 //===----------------------------------------------------------------------===//
39 #define DEBUG_TYPE "dagcombine"
40 #include "llvm/ADT/Statistic.h"
41 #include "llvm/CodeGen/SelectionDAG.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Target/TargetLowering.h"
51 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
58 // Worklist of all of the nodes that need to be simplified.
59 std::vector<SDNode*> WorkList;
61 /// AddUsersToWorkList - When an instruction is simplified, add all users of
62 /// the instruction to the work lists because they might get more simplified
65 void AddUsersToWorkList(SDNode *N) {
66 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
68 WorkList.push_back(*UI);
71 /// removeFromWorkList - remove all instances of N from the worklist.
72 void removeFromWorkList(SDNode *N) {
73 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
77 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
79 DEBUG(std::cerr << "\nReplacing "; N->dump();
80 std::cerr << "\nWith: "; To[0].Val->dump();
81 std::cerr << " and " << To.size()-1 << " other values\n");
82 std::vector<SDNode*> NowDead;
83 DAG.ReplaceAllUsesWith(N, To, &NowDead);
85 // Push the new nodes and any users onto the worklist
86 for (unsigned i = 0, e = To.size(); i != e; ++i) {
87 WorkList.push_back(To[i].Val);
88 AddUsersToWorkList(To[i].Val);
91 // Nodes can end up on the worklist more than once. Make sure we do
92 // not process a node that has been replaced.
93 removeFromWorkList(N);
94 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
95 removeFromWorkList(NowDead[i]);
97 // Finally, since the node is now dead, remove it from the graph.
99 return SDOperand(N, 0);
102 bool DemandedBitsAreZero(SDOperand Op, uint64_t DemandedMask) {
103 TargetLowering::TargetLoweringOpt TLO(DAG);
104 uint64_t KnownZero, KnownOne;
105 if (TLI.SimplifyDemandedBits(Op, DemandedMask, KnownZero, KnownOne, TLO)){
106 WorkList.push_back(Op.Val);
107 CombineTo(TLO.Old.Val, TLO.New);
113 SDOperand CombineTo(SDNode *N, SDOperand Res) {
114 std::vector<SDOperand> To;
116 return CombineTo(N, To);
119 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
120 std::vector<SDOperand> To;
123 return CombineTo(N, To);
126 /// visit - call the node-specific routine that knows how to fold each
127 /// particular type of node.
128 SDOperand visit(SDNode *N);
130 // Visitation implementation - Implement dag node combining for different
131 // node types. The semantics are as follows:
133 // SDOperand.Val == 0 - No change was made
134 // SDOperand.Val == N - N was replaced, is dead, and is already handled.
135 // otherwise - N should be replaced by the returned Operand.
137 SDOperand visitTokenFactor(SDNode *N);
138 SDOperand visitADD(SDNode *N);
139 SDOperand visitSUB(SDNode *N);
140 SDOperand visitMUL(SDNode *N);
141 SDOperand visitSDIV(SDNode *N);
142 SDOperand visitUDIV(SDNode *N);
143 SDOperand visitSREM(SDNode *N);
144 SDOperand visitUREM(SDNode *N);
145 SDOperand visitMULHU(SDNode *N);
146 SDOperand visitMULHS(SDNode *N);
147 SDOperand visitAND(SDNode *N);
148 SDOperand visitOR(SDNode *N);
149 SDOperand visitXOR(SDNode *N);
150 SDOperand visitSHL(SDNode *N);
151 SDOperand visitSRA(SDNode *N);
152 SDOperand visitSRL(SDNode *N);
153 SDOperand visitCTLZ(SDNode *N);
154 SDOperand visitCTTZ(SDNode *N);
155 SDOperand visitCTPOP(SDNode *N);
156 SDOperand visitSELECT(SDNode *N);
157 SDOperand visitSELECT_CC(SDNode *N);
158 SDOperand visitSETCC(SDNode *N);
159 SDOperand visitSIGN_EXTEND(SDNode *N);
160 SDOperand visitZERO_EXTEND(SDNode *N);
161 SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
162 SDOperand visitTRUNCATE(SDNode *N);
163 SDOperand visitBIT_CONVERT(SDNode *N);
164 SDOperand visitFADD(SDNode *N);
165 SDOperand visitFSUB(SDNode *N);
166 SDOperand visitFMUL(SDNode *N);
167 SDOperand visitFDIV(SDNode *N);
168 SDOperand visitFREM(SDNode *N);
169 SDOperand visitSINT_TO_FP(SDNode *N);
170 SDOperand visitUINT_TO_FP(SDNode *N);
171 SDOperand visitFP_TO_SINT(SDNode *N);
172 SDOperand visitFP_TO_UINT(SDNode *N);
173 SDOperand visitFP_ROUND(SDNode *N);
174 SDOperand visitFP_ROUND_INREG(SDNode *N);
175 SDOperand visitFP_EXTEND(SDNode *N);
176 SDOperand visitFNEG(SDNode *N);
177 SDOperand visitFABS(SDNode *N);
178 SDOperand visitBRCOND(SDNode *N);
179 SDOperand visitBRCONDTWOWAY(SDNode *N);
180 SDOperand visitBR_CC(SDNode *N);
181 SDOperand visitBRTWOWAY_CC(SDNode *N);
182 SDOperand visitLOAD(SDNode *N);
183 SDOperand visitSTORE(SDNode *N);
185 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
187 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS);
188 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
189 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
190 SDOperand N3, ISD::CondCode CC);
191 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
192 ISD::CondCode Cond, bool foldBooleans = true);
194 SDOperand BuildSDIV(SDNode *N);
195 SDOperand BuildUDIV(SDNode *N);
197 DAGCombiner(SelectionDAG &D)
198 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
200 /// Run - runs the dag combiner on all nodes in the work list
201 void Run(bool RunningAfterLegalize);
206 int64_t m; // magic number
207 int64_t s; // shift amount
211 uint64_t m; // magic number
212 int64_t a; // add indicator
213 int64_t s; // shift amount
216 /// magic - calculate the magic numbers required to codegen an integer sdiv as
217 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
219 static ms magic32(int32_t d) {
221 uint32_t ad, anc, delta, q1, r1, q2, r2, t;
222 const uint32_t two31 = 0x80000000U;
226 t = two31 + ((uint32_t)d >> 31);
227 anc = t - 1 - t%ad; // absolute value of nc
228 p = 31; // initialize p
229 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
230 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
231 q2 = two31/ad; // initialize q2 = 2p/abs(d)
232 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
235 q1 = 2*q1; // update q1 = 2p/abs(nc)
236 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
237 if (r1 >= anc) { // must be unsigned comparison
241 q2 = 2*q2; // update q2 = 2p/abs(d)
242 r2 = 2*r2; // update r2 = rem(2p/abs(d))
243 if (r2 >= ad) { // must be unsigned comparison
248 } while (q1 < delta || (q1 == delta && r1 == 0));
250 mag.m = (int32_t)(q2 + 1); // make sure to sign extend
251 if (d < 0) mag.m = -mag.m; // resulting magic number
252 mag.s = p - 32; // resulting shift
256 /// magicu - calculate the magic numbers required to codegen an integer udiv as
257 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
258 static mu magicu32(uint32_t d) {
260 uint32_t nc, delta, q1, r1, q2, r2;
262 magu.a = 0; // initialize "add" indicator
264 p = 31; // initialize p
265 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
266 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
267 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
268 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
271 if (r1 >= nc - r1 ) {
272 q1 = 2*q1 + 1; // update q1
273 r1 = 2*r1 - nc; // update r1
276 q1 = 2*q1; // update q1
277 r1 = 2*r1; // update r1
279 if (r2 + 1 >= d - r2) {
280 if (q2 >= 0x7FFFFFFF) magu.a = 1;
281 q2 = 2*q2 + 1; // update q2
282 r2 = 2*r2 + 1 - d; // update r2
285 if (q2 >= 0x80000000) magu.a = 1;
286 q2 = 2*q2; // update q2
287 r2 = 2*r2 + 1; // update r2
290 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
291 magu.m = q2 + 1; // resulting magic number
292 magu.s = p - 32; // resulting shift
296 /// magic - calculate the magic numbers required to codegen an integer sdiv as
297 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
299 static ms magic64(int64_t d) {
301 uint64_t ad, anc, delta, q1, r1, q2, r2, t;
302 const uint64_t two63 = 9223372036854775808ULL; // 2^63
305 ad = d >= 0 ? d : -d;
306 t = two63 + ((uint64_t)d >> 63);
307 anc = t - 1 - t%ad; // absolute value of nc
308 p = 63; // initialize p
309 q1 = two63/anc; // initialize q1 = 2p/abs(nc)
310 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc))
311 q2 = two63/ad; // initialize q2 = 2p/abs(d)
312 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d))
315 q1 = 2*q1; // update q1 = 2p/abs(nc)
316 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
317 if (r1 >= anc) { // must be unsigned comparison
321 q2 = 2*q2; // update q2 = 2p/abs(d)
322 r2 = 2*r2; // update r2 = rem(2p/abs(d))
323 if (r2 >= ad) { // must be unsigned comparison
328 } while (q1 < delta || (q1 == delta && r1 == 0));
331 if (d < 0) mag.m = -mag.m; // resulting magic number
332 mag.s = p - 64; // resulting shift
336 /// magicu - calculate the magic numbers required to codegen an integer udiv as
337 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
338 static mu magicu64(uint64_t d)
341 uint64_t nc, delta, q1, r1, q2, r2;
343 magu.a = 0; // initialize "add" indicator
345 p = 63; // initialize p
346 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc
347 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc)
348 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d
349 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d)
352 if (r1 >= nc - r1 ) {
353 q1 = 2*q1 + 1; // update q1
354 r1 = 2*r1 - nc; // update r1
357 q1 = 2*q1; // update q1
358 r1 = 2*r1; // update r1
360 if (r2 + 1 >= d - r2) {
361 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1;
362 q2 = 2*q2 + 1; // update q2
363 r2 = 2*r2 + 1 - d; // update r2
366 if (q2 >= 0x8000000000000000ull) magu.a = 1;
367 q2 = 2*q2; // update q2
368 r2 = 2*r2 + 1; // update r2
371 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
372 magu.m = q2 + 1; // resulting magic number
373 magu.s = p - 64; // resulting shift
377 // isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
378 // that selects between the values 1 and 0, making it equivalent to a setcc.
379 // Also, set the incoming LHS, RHS, and CC references to the appropriate
380 // nodes based on the type of node we are checking. This simplifies life a
381 // bit for the callers.
382 static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
384 if (N.getOpcode() == ISD::SETCC) {
385 LHS = N.getOperand(0);
386 RHS = N.getOperand(1);
387 CC = N.getOperand(2);
390 if (N.getOpcode() == ISD::SELECT_CC &&
391 N.getOperand(2).getOpcode() == ISD::Constant &&
392 N.getOperand(3).getOpcode() == ISD::Constant &&
393 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
394 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
395 LHS = N.getOperand(0);
396 RHS = N.getOperand(1);
397 CC = N.getOperand(4);
403 // isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
404 // one use. If this is true, it allows the users to invert the operation for
405 // free when it is profitable to do so.
406 static bool isOneUseSetCC(SDOperand N) {
407 SDOperand N0, N1, N2;
408 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
413 // FIXME: This should probably go in the ISD class rather than being duplicated
415 static bool isCommutativeBinOp(unsigned Opcode) {
421 case ISD::XOR: return true;
422 default: return false; // FIXME: Need commutative info for user ops!
426 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
427 MVT::ValueType VT = N0.getValueType();
428 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
429 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
430 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
431 if (isa<ConstantSDNode>(N1)) {
432 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1);
433 WorkList.push_back(OpNode.Val);
434 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0));
435 } else if (N0.hasOneUse()) {
436 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1);
437 WorkList.push_back(OpNode.Val);
438 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1));
441 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use
442 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2))
443 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) {
444 if (isa<ConstantSDNode>(N0)) {
445 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0);
446 WorkList.push_back(OpNode.Val);
447 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0));
448 } else if (N1.hasOneUse()) {
449 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0);
450 WorkList.push_back(OpNode.Val);
451 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1));
457 void DAGCombiner::Run(bool RunningAfterLegalize) {
458 // set the instance variable, so that the various visit routines may use it.
459 AfterLegalize = RunningAfterLegalize;
461 // Add all the dag nodes to the worklist.
462 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
463 E = DAG.allnodes_end(); I != E; ++I)
464 WorkList.push_back(I);
466 // Create a dummy node (which is not added to allnodes), that adds a reference
467 // to the root node, preventing it from being deleted, and tracking any
468 // changes of the root.
469 HandleSDNode Dummy(DAG.getRoot());
471 // while the worklist isn't empty, inspect the node on the end of it and
472 // try and combine it.
473 while (!WorkList.empty()) {
474 SDNode *N = WorkList.back();
477 // If N has no uses, it is dead. Make sure to revisit all N's operands once
478 // N is deleted from the DAG, since they too may now be dead or may have a
479 // reduced number of uses, allowing other xforms.
480 if (N->use_empty() && N != &Dummy) {
481 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
482 WorkList.push_back(N->getOperand(i).Val);
484 removeFromWorkList(N);
489 SDOperand RV = visit(N);
492 // If we get back the same node we passed in, rather than a new node or
493 // zero, we know that the node must have defined multiple values and
494 // CombineTo was used. Since CombineTo takes care of the worklist
495 // mechanics for us, we have no work to do in this case.
497 DEBUG(std::cerr << "\nReplacing "; N->dump();
498 std::cerr << "\nWith: "; RV.Val->dump();
500 std::vector<SDNode*> NowDead;
501 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
503 // Push the new node and any users onto the worklist
504 WorkList.push_back(RV.Val);
505 AddUsersToWorkList(RV.Val);
507 // Nodes can end up on the worklist more than once. Make sure we do
508 // not process a node that has been replaced.
509 removeFromWorkList(N);
510 for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
511 removeFromWorkList(NowDead[i]);
513 // Finally, since the node is now dead, remove it from the graph.
519 // If the root changed (e.g. it was a dead load, update the root).
520 DAG.setRoot(Dummy.getValue());
523 SDOperand DAGCombiner::visit(SDNode *N) {
524 switch(N->getOpcode()) {
526 case ISD::TokenFactor: return visitTokenFactor(N);
527 case ISD::ADD: return visitADD(N);
528 case ISD::SUB: return visitSUB(N);
529 case ISD::MUL: return visitMUL(N);
530 case ISD::SDIV: return visitSDIV(N);
531 case ISD::UDIV: return visitUDIV(N);
532 case ISD::SREM: return visitSREM(N);
533 case ISD::UREM: return visitUREM(N);
534 case ISD::MULHU: return visitMULHU(N);
535 case ISD::MULHS: return visitMULHS(N);
536 case ISD::AND: return visitAND(N);
537 case ISD::OR: return visitOR(N);
538 case ISD::XOR: return visitXOR(N);
539 case ISD::SHL: return visitSHL(N);
540 case ISD::SRA: return visitSRA(N);
541 case ISD::SRL: return visitSRL(N);
542 case ISD::CTLZ: return visitCTLZ(N);
543 case ISD::CTTZ: return visitCTTZ(N);
544 case ISD::CTPOP: return visitCTPOP(N);
545 case ISD::SELECT: return visitSELECT(N);
546 case ISD::SELECT_CC: return visitSELECT_CC(N);
547 case ISD::SETCC: return visitSETCC(N);
548 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N);
549 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N);
550 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
551 case ISD::TRUNCATE: return visitTRUNCATE(N);
552 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N);
553 case ISD::FADD: return visitFADD(N);
554 case ISD::FSUB: return visitFSUB(N);
555 case ISD::FMUL: return visitFMUL(N);
556 case ISD::FDIV: return visitFDIV(N);
557 case ISD::FREM: return visitFREM(N);
558 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N);
559 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N);
560 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
561 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
562 case ISD::FP_ROUND: return visitFP_ROUND(N);
563 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
564 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
565 case ISD::FNEG: return visitFNEG(N);
566 case ISD::FABS: return visitFABS(N);
567 case ISD::BRCOND: return visitBRCOND(N);
568 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
569 case ISD::BR_CC: return visitBR_CC(N);
570 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N);
571 case ISD::LOAD: return visitLOAD(N);
572 case ISD::STORE: return visitSTORE(N);
577 SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
578 std::vector<SDOperand> Ops;
579 bool Changed = false;
581 // If the token factor has two operands and one is the entry token, replace
582 // the token factor with the other operand.
583 if (N->getNumOperands() == 2) {
584 if (N->getOperand(0).getOpcode() == ISD::EntryToken)
585 return N->getOperand(1);
586 if (N->getOperand(1).getOpcode() == ISD::EntryToken)
587 return N->getOperand(0);
590 // fold (tokenfactor (tokenfactor)) -> tokenfactor
591 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
592 SDOperand Op = N->getOperand(i);
593 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
595 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
596 Ops.push_back(Op.getOperand(j));
602 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
606 SDOperand DAGCombiner::visitADD(SDNode *N) {
607 SDOperand N0 = N->getOperand(0);
608 SDOperand N1 = N->getOperand(1);
609 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
610 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
611 MVT::ValueType VT = N0.getValueType();
613 // fold (add c1, c2) -> c1+c2
615 return DAG.getNode(ISD::ADD, VT, N0, N1);
616 // canonicalize constant to RHS
618 return DAG.getNode(ISD::ADD, VT, N1, N0);
619 // fold (add x, 0) -> x
620 if (N1C && N1C->isNullValue())
622 // fold ((c1-A)+c2) -> (c1+c2)-A
623 if (N1C && N0.getOpcode() == ISD::SUB)
624 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
625 return DAG.getNode(ISD::SUB, VT,
626 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
629 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1);
632 // fold ((0-A) + B) -> B-A
633 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
634 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
635 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
636 // fold (A + (0-B)) -> A-B
637 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
638 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
639 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
640 // fold (A+(B-A)) -> B
641 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
642 return N1.getOperand(0);
646 SDOperand DAGCombiner::visitSUB(SDNode *N) {
647 SDOperand N0 = N->getOperand(0);
648 SDOperand N1 = N->getOperand(1);
649 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
650 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
651 MVT::ValueType VT = N0.getValueType();
653 // fold (sub x, x) -> 0
655 return DAG.getConstant(0, N->getValueType(0));
656 // fold (sub c1, c2) -> c1-c2
658 return DAG.getNode(ISD::SUB, VT, N0, N1);
659 // fold (sub x, c) -> (add x, -c)
661 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT));
663 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
664 return N0.getOperand(1);
666 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
667 return N0.getOperand(0);
671 SDOperand DAGCombiner::visitMUL(SDNode *N) {
672 SDOperand N0 = N->getOperand(0);
673 SDOperand N1 = N->getOperand(1);
674 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
675 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
676 MVT::ValueType VT = N0.getValueType();
678 // fold (mul c1, c2) -> c1*c2
680 return DAG.getNode(ISD::MUL, VT, N0, N1);
681 // canonicalize constant to RHS
683 return DAG.getNode(ISD::MUL, VT, N1, N0);
684 // fold (mul x, 0) -> 0
685 if (N1C && N1C->isNullValue())
687 // fold (mul x, -1) -> 0-x
688 if (N1C && N1C->isAllOnesValue())
689 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
690 // fold (mul x, (1 << c)) -> x << c
691 if (N1C && isPowerOf2_64(N1C->getValue()))
692 return DAG.getNode(ISD::SHL, VT, N0,
693 DAG.getConstant(Log2_64(N1C->getValue()),
694 TLI.getShiftAmountTy()));
695 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c
696 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) {
697 // FIXME: If the input is something that is easily negated (e.g. a
698 // single-use add), we should put the negate there.
699 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT),
700 DAG.getNode(ISD::SHL, VT, N0,
701 DAG.getConstant(Log2_64(-N1C->getSignExtended()),
702 TLI.getShiftAmountTy())));
705 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
711 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
712 SDOperand N0 = N->getOperand(0);
713 SDOperand N1 = N->getOperand(1);
714 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
715 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
716 MVT::ValueType VT = N->getValueType(0);
718 // fold (sdiv c1, c2) -> c1/c2
719 if (N0C && N1C && !N1C->isNullValue())
720 return DAG.getNode(ISD::SDIV, VT, N0, N1);
721 // fold (sdiv X, 1) -> X
722 if (N1C && N1C->getSignExtended() == 1LL)
724 // fold (sdiv X, -1) -> 0-X
725 if (N1C && N1C->isAllOnesValue())
726 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
727 // If we know the sign bits of both operands are zero, strength reduce to a
728 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
729 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
730 if (TLI.MaskedValueIsZero(N1, SignBit) &&
731 TLI.MaskedValueIsZero(N0, SignBit))
732 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
733 // fold (sdiv X, pow2) -> simple ops after legalize
734 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() &&
735 (isPowerOf2_64(N1C->getSignExtended()) ||
736 isPowerOf2_64(-N1C->getSignExtended()))) {
737 // If dividing by powers of two is cheap, then don't perform the following
739 if (TLI.isPow2DivCheap())
741 int64_t pow2 = N1C->getSignExtended();
742 int64_t abs2 = pow2 > 0 ? pow2 : -pow2;
743 unsigned lg2 = Log2_64(abs2);
744 // Splat the sign bit into the register
745 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
746 DAG.getConstant(MVT::getSizeInBits(VT)-1,
747 TLI.getShiftAmountTy()));
748 WorkList.push_back(SGN.Val);
749 // Add (N0 < 0) ? abs2 - 1 : 0;
750 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
751 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
752 TLI.getShiftAmountTy()));
753 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
754 WorkList.push_back(SRL.Val);
755 WorkList.push_back(ADD.Val); // Divide by pow2
756 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD,
757 DAG.getConstant(lg2, TLI.getShiftAmountTy()));
758 // If we're dividing by a positive value, we're done. Otherwise, we must
759 // negate the result.
762 WorkList.push_back(SRA.Val);
763 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA);
765 // if integer divide is expensive and we satisfy the requirements, emit an
766 // alternate sequence.
767 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) &&
768 !TLI.isIntDivCheap()) {
769 SDOperand Op = BuildSDIV(N);
770 if (Op.Val) return Op;
775 SDOperand DAGCombiner::visitUDIV(SDNode *N) {
776 SDOperand N0 = N->getOperand(0);
777 SDOperand N1 = N->getOperand(1);
778 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
779 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
780 MVT::ValueType VT = N->getValueType(0);
782 // fold (udiv c1, c2) -> c1/c2
783 if (N0C && N1C && !N1C->isNullValue())
784 return DAG.getNode(ISD::UDIV, VT, N0, N1);
785 // fold (udiv x, (1 << c)) -> x >>u c
786 if (N1C && isPowerOf2_64(N1C->getValue()))
787 return DAG.getNode(ISD::SRL, VT, N0,
788 DAG.getConstant(Log2_64(N1C->getValue()),
789 TLI.getShiftAmountTy()));
790 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
791 if (N1.getOpcode() == ISD::SHL) {
792 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
793 if (isPowerOf2_64(SHC->getValue())) {
794 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
795 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
796 DAG.getConstant(Log2_64(SHC->getValue()),
798 WorkList.push_back(Add.Val);
799 return DAG.getNode(ISD::SRL, VT, N0, Add);
803 // fold (udiv x, c) -> alternate
804 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) {
805 SDOperand Op = BuildUDIV(N);
806 if (Op.Val) return Op;
811 SDOperand DAGCombiner::visitSREM(SDNode *N) {
812 SDOperand N0 = N->getOperand(0);
813 SDOperand N1 = N->getOperand(1);
814 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
815 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
816 MVT::ValueType VT = N->getValueType(0);
818 // fold (srem c1, c2) -> c1%c2
819 if (N0C && N1C && !N1C->isNullValue())
820 return DAG.getNode(ISD::SREM, VT, N0, N1);
821 // If we know the sign bits of both operands are zero, strength reduce to a
822 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
823 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
824 if (TLI.MaskedValueIsZero(N1, SignBit) &&
825 TLI.MaskedValueIsZero(N0, SignBit))
826 return DAG.getNode(ISD::UREM, VT, N0, N1);
830 SDOperand DAGCombiner::visitUREM(SDNode *N) {
831 SDOperand N0 = N->getOperand(0);
832 SDOperand N1 = N->getOperand(1);
833 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
834 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
835 MVT::ValueType VT = N->getValueType(0);
837 // fold (urem c1, c2) -> c1%c2
838 if (N0C && N1C && !N1C->isNullValue())
839 return DAG.getNode(ISD::UREM, VT, N0, N1);
840 // fold (urem x, pow2) -> (and x, pow2-1)
841 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
842 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT));
843 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
844 if (N1.getOpcode() == ISD::SHL) {
845 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
846 if (isPowerOf2_64(SHC->getValue())) {
847 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT));
848 WorkList.push_back(Add.Val);
849 return DAG.getNode(ISD::AND, VT, N0, Add);
856 SDOperand DAGCombiner::visitMULHS(SDNode *N) {
857 SDOperand N0 = N->getOperand(0);
858 SDOperand N1 = N->getOperand(1);
859 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
861 // fold (mulhs x, 0) -> 0
862 if (N1C && N1C->isNullValue())
864 // fold (mulhs x, 1) -> (sra x, size(x)-1)
865 if (N1C && N1C->getValue() == 1)
866 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
867 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
868 TLI.getShiftAmountTy()));
872 SDOperand DAGCombiner::visitMULHU(SDNode *N) {
873 SDOperand N0 = N->getOperand(0);
874 SDOperand N1 = N->getOperand(1);
875 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
877 // fold (mulhu x, 0) -> 0
878 if (N1C && N1C->isNullValue())
880 // fold (mulhu x, 1) -> 0
881 if (N1C && N1C->getValue() == 1)
882 return DAG.getConstant(0, N0.getValueType());
886 SDOperand DAGCombiner::visitAND(SDNode *N) {
887 SDOperand N0 = N->getOperand(0);
888 SDOperand N1 = N->getOperand(1);
889 SDOperand LL, LR, RL, RR, CC0, CC1;
890 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
891 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
892 MVT::ValueType VT = N1.getValueType();
893 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
895 // fold (and c1, c2) -> c1&c2
897 return DAG.getNode(ISD::AND, VT, N0, N1);
898 // canonicalize constant to RHS
900 return DAG.getNode(ISD::AND, VT, N1, N0);
901 // fold (and x, -1) -> x
902 if (N1C && N1C->isAllOnesValue())
904 // if (and x, c) is known to be zero, return 0
905 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
906 return DAG.getConstant(0, VT);
908 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1);
911 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
912 if (N1C && N0.getOpcode() == ISD::OR)
913 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
914 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
916 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
917 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
918 unsigned InBits = MVT::getSizeInBits(N0.getOperand(0).getValueType());
919 if (TLI.MaskedValueIsZero(N0.getOperand(0),
920 ~N1C->getValue() & ((1ULL << InBits)-1))) {
921 // We actually want to replace all uses of the any_extend with the
922 // zero_extend, to avoid duplicating things. This will later cause this
924 CombineTo(N0.Val, DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(),
929 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
930 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
931 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
932 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
934 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
935 MVT::isInteger(LL.getValueType())) {
936 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
937 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
938 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
939 WorkList.push_back(ORNode.Val);
940 return DAG.getSetCC(VT, ORNode, LR, Op1);
942 // fold (X == -1) & (Y == -1) -> (X&Y == -1)
943 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
944 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
945 WorkList.push_back(ANDNode.Val);
946 return DAG.getSetCC(VT, ANDNode, LR, Op1);
948 // fold (X > -1) & (Y > -1) -> (X|Y > -1)
949 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
950 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
951 WorkList.push_back(ORNode.Val);
952 return DAG.getSetCC(VT, ORNode, LR, Op1);
955 // canonicalize equivalent to ll == rl
956 if (LL == RR && LR == RL) {
957 Op1 = ISD::getSetCCSwappedOperands(Op1);
960 if (LL == RL && LR == RR) {
961 bool isInteger = MVT::isInteger(LL.getValueType());
962 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
963 if (Result != ISD::SETCC_INVALID)
964 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
967 // fold (and (zext x), (zext y)) -> (zext (and x, y))
968 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
969 N1.getOpcode() == ISD::ZERO_EXTEND &&
970 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
971 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
972 N0.getOperand(0), N1.getOperand(0));
973 WorkList.push_back(ANDNode.Val);
974 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
976 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y))
977 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
978 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
979 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
980 N0.getOperand(1) == N1.getOperand(1)) {
981 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
982 N0.getOperand(0), N1.getOperand(0));
983 WorkList.push_back(ANDNode.Val);
984 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
986 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
987 // fold (and (sra)) -> (and (srl)) when possible.
988 if (DemandedBitsAreZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
990 // fold (zext_inreg (extload x)) -> (zextload x)
991 if (N0.getOpcode() == ISD::EXTLOAD) {
992 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
993 // If we zero all the possible extended bits, then we can turn this into
994 // a zextload if we are running before legalize or the operation is legal.
995 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
996 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
997 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
998 N0.getOperand(1), N0.getOperand(2),
1000 WorkList.push_back(N);
1001 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1005 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
1006 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) {
1007 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
1008 // If we zero all the possible extended bits, then we can turn this into
1009 // a zextload if we are running before legalize or the operation is legal.
1010 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
1011 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
1012 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1013 N0.getOperand(1), N0.getOperand(2),
1015 WorkList.push_back(N);
1016 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1023 SDOperand DAGCombiner::visitOR(SDNode *N) {
1024 SDOperand N0 = N->getOperand(0);
1025 SDOperand N1 = N->getOperand(1);
1026 SDOperand LL, LR, RL, RR, CC0, CC1;
1027 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1028 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1029 MVT::ValueType VT = N1.getValueType();
1030 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1032 // fold (or c1, c2) -> c1|c2
1034 return DAG.getNode(ISD::OR, VT, N0, N1);
1035 // canonicalize constant to RHS
1037 return DAG.getNode(ISD::OR, VT, N1, N0);
1038 // fold (or x, 0) -> x
1039 if (N1C && N1C->isNullValue())
1041 // fold (or x, -1) -> -1
1042 if (N1C && N1C->isAllOnesValue())
1044 // fold (or x, c) -> c iff (x & ~c) == 0
1046 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits))))
1049 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1);
1052 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
1053 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() &&
1054 isa<ConstantSDNode>(N0.getOperand(1))) {
1055 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
1056 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0),
1058 DAG.getConstant(N1C->getValue() | C1->getValue(), VT));
1060 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
1061 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
1062 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
1063 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
1065 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
1066 MVT::isInteger(LL.getValueType())) {
1067 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
1068 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
1069 if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
1070 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
1071 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
1072 WorkList.push_back(ORNode.Val);
1073 return DAG.getSetCC(VT, ORNode, LR, Op1);
1075 // fold (X != -1) | (Y != -1) -> (X&Y != -1)
1076 // fold (X > -1) | (Y > -1) -> (X&Y > -1)
1077 if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
1078 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
1079 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
1080 WorkList.push_back(ANDNode.Val);
1081 return DAG.getSetCC(VT, ANDNode, LR, Op1);
1084 // canonicalize equivalent to ll == rl
1085 if (LL == RR && LR == RL) {
1086 Op1 = ISD::getSetCCSwappedOperands(Op1);
1089 if (LL == RL && LR == RR) {
1090 bool isInteger = MVT::isInteger(LL.getValueType());
1091 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
1092 if (Result != ISD::SETCC_INVALID)
1093 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
1096 // fold (or (zext x), (zext y)) -> (zext (or x, y))
1097 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1098 N1.getOpcode() == ISD::ZERO_EXTEND &&
1099 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1100 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1101 N0.getOperand(0), N1.getOperand(0));
1102 WorkList.push_back(ORNode.Val);
1103 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
1105 // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y))
1106 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1107 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1108 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1109 N0.getOperand(1) == N1.getOperand(1)) {
1110 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
1111 N0.getOperand(0), N1.getOperand(0));
1112 WorkList.push_back(ORNode.Val);
1113 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
1115 // canonicalize shl to left side in a shl/srl pair, to match rotate
1116 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
1118 // check for rotl, rotr
1119 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
1120 N0.getOperand(0) == N1.getOperand(0) &&
1121 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
1122 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
1123 if (N0.getOperand(1).getOpcode() == ISD::Constant &&
1124 N1.getOperand(1).getOpcode() == ISD::Constant) {
1125 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1126 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue();
1127 if ((c1val + c2val) == OpSizeInBits)
1128 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1130 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
1131 if (N1.getOperand(1).getOpcode() == ISD::SUB &&
1132 N0.getOperand(1) == N1.getOperand(1).getOperand(1))
1133 if (ConstantSDNode *SUBC =
1134 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0)))
1135 if (SUBC->getValue() == OpSizeInBits)
1136 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
1137 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
1138 if (N0.getOperand(1).getOpcode() == ISD::SUB &&
1139 N1.getOperand(1) == N0.getOperand(1).getOperand(1))
1140 if (ConstantSDNode *SUBC =
1141 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
1142 if (SUBC->getValue() == OpSizeInBits) {
1143 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
1144 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
1147 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
1154 SDOperand DAGCombiner::visitXOR(SDNode *N) {
1155 SDOperand N0 = N->getOperand(0);
1156 SDOperand N1 = N->getOperand(1);
1157 SDOperand LHS, RHS, CC;
1158 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1159 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1160 MVT::ValueType VT = N0.getValueType();
1162 // fold (xor c1, c2) -> c1^c2
1164 return DAG.getNode(ISD::XOR, VT, N0, N1);
1165 // canonicalize constant to RHS
1167 return DAG.getNode(ISD::XOR, VT, N1, N0);
1168 // fold (xor x, 0) -> x
1169 if (N1C && N1C->isNullValue())
1172 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1);
1175 // fold !(x cc y) -> (x !cc y)
1176 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
1177 bool isInt = MVT::isInteger(LHS.getValueType());
1178 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
1180 if (N0.getOpcode() == ISD::SETCC)
1181 return DAG.getSetCC(VT, LHS, RHS, NotCC);
1182 if (N0.getOpcode() == ISD::SELECT_CC)
1183 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
1184 assert(0 && "Unhandled SetCC Equivalent!");
1187 // fold !(x or y) -> (!x and !y) iff x or y are setcc
1188 if (N1C && N1C->getValue() == 1 &&
1189 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1190 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1191 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
1192 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1193 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1194 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1195 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1196 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1199 // fold !(x or y) -> (!x and !y) iff x or y are constants
1200 if (N1C && N1C->isAllOnesValue() &&
1201 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
1202 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
1203 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
1204 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
1205 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS
1206 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS
1207 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
1208 return DAG.getNode(NewOpcode, VT, LHS, RHS);
1211 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
1212 if (N1C && N0.getOpcode() == ISD::XOR) {
1213 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
1214 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
1216 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
1217 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
1219 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
1220 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
1222 // fold (xor x, x) -> 0
1224 return DAG.getConstant(0, VT);
1225 // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
1226 if (N0.getOpcode() == ISD::ZERO_EXTEND &&
1227 N1.getOpcode() == ISD::ZERO_EXTEND &&
1228 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
1229 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1230 N0.getOperand(0), N1.getOperand(0));
1231 WorkList.push_back(XORNode.Val);
1232 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
1234 // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y))
1235 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
1236 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) ||
1237 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) &&
1238 N0.getOperand(1) == N1.getOperand(1)) {
1239 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
1240 N0.getOperand(0), N1.getOperand(0));
1241 WorkList.push_back(XORNode.Val);
1242 return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1));
1247 SDOperand DAGCombiner::visitSHL(SDNode *N) {
1248 SDOperand N0 = N->getOperand(0);
1249 SDOperand N1 = N->getOperand(1);
1250 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1251 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1252 MVT::ValueType VT = N0.getValueType();
1253 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1255 // fold (shl c1, c2) -> c1<<c2
1257 return DAG.getNode(ISD::SHL, VT, N0, N1);
1258 // fold (shl 0, x) -> 0
1259 if (N0C && N0C->isNullValue())
1261 // fold (shl x, c >= size(x)) -> undef
1262 if (N1C && N1C->getValue() >= OpSizeInBits)
1263 return DAG.getNode(ISD::UNDEF, VT);
1264 // fold (shl x, 0) -> x
1265 if (N1C && N1C->isNullValue())
1267 // if (shl x, c) is known to be zero, return 0
1268 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT)))
1269 return DAG.getConstant(0, VT);
1270 if (DemandedBitsAreZero(SDOperand(N,0), MVT::getIntVTBitMask(VT)))
1272 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1273 if (N1C && N0.getOpcode() == ISD::SHL &&
1274 N0.getOperand(1).getOpcode() == ISD::Constant) {
1275 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1276 uint64_t c2 = N1C->getValue();
1277 if (c1 + c2 > OpSizeInBits)
1278 return DAG.getConstant(0, VT);
1279 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1280 DAG.getConstant(c1 + c2, N1.getValueType()));
1282 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1283 // (srl (and x, -1 << c1), c1-c2)
1284 if (N1C && N0.getOpcode() == ISD::SRL &&
1285 N0.getOperand(1).getOpcode() == ISD::Constant) {
1286 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1287 uint64_t c2 = N1C->getValue();
1288 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1289 DAG.getConstant(~0ULL << c1, VT));
1291 return DAG.getNode(ISD::SHL, VT, Mask,
1292 DAG.getConstant(c2-c1, N1.getValueType()));
1294 return DAG.getNode(ISD::SRL, VT, Mask,
1295 DAG.getConstant(c1-c2, N1.getValueType()));
1297 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1298 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1299 return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1300 DAG.getConstant(~0ULL << N1C->getValue(), VT));
1304 SDOperand DAGCombiner::visitSRA(SDNode *N) {
1305 SDOperand N0 = N->getOperand(0);
1306 SDOperand N1 = N->getOperand(1);
1307 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1308 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1309 MVT::ValueType VT = N0.getValueType();
1311 // fold (sra c1, c2) -> c1>>c2
1313 return DAG.getNode(ISD::SRA, VT, N0, N1);
1314 // fold (sra 0, x) -> 0
1315 if (N0C && N0C->isNullValue())
1317 // fold (sra -1, x) -> -1
1318 if (N0C && N0C->isAllOnesValue())
1320 // fold (sra x, c >= size(x)) -> undef
1321 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
1322 return DAG.getNode(ISD::UNDEF, VT);
1323 // fold (sra x, 0) -> x
1324 if (N1C && N1C->isNullValue())
1326 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
1328 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
1329 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
1332 default: EVT = MVT::Other; break;
1333 case 1: EVT = MVT::i1; break;
1334 case 8: EVT = MVT::i8; break;
1335 case 16: EVT = MVT::i16; break;
1336 case 32: EVT = MVT::i32; break;
1338 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))
1339 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1340 DAG.getValueType(EVT));
1342 // If the sign bit is known to be zero, switch this to a SRL.
1343 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
1344 return DAG.getNode(ISD::SRL, VT, N0, N1);
1348 SDOperand DAGCombiner::visitSRL(SDNode *N) {
1349 SDOperand N0 = N->getOperand(0);
1350 SDOperand N1 = N->getOperand(1);
1351 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1352 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1353 MVT::ValueType VT = N0.getValueType();
1354 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1356 // fold (srl c1, c2) -> c1 >>u c2
1358 return DAG.getNode(ISD::SRL, VT, N0, N1);
1359 // fold (srl 0, x) -> 0
1360 if (N0C && N0C->isNullValue())
1362 // fold (srl x, c >= size(x)) -> undef
1363 if (N1C && N1C->getValue() >= OpSizeInBits)
1364 return DAG.getNode(ISD::UNDEF, VT);
1365 // fold (srl x, 0) -> x
1366 if (N1C && N1C->isNullValue())
1368 // if (srl x, c) is known to be zero, return 0
1369 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits)))
1370 return DAG.getConstant(0, VT);
1371 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1372 if (N1C && N0.getOpcode() == ISD::SRL &&
1373 N0.getOperand(1).getOpcode() == ISD::Constant) {
1374 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1375 uint64_t c2 = N1C->getValue();
1376 if (c1 + c2 > OpSizeInBits)
1377 return DAG.getConstant(0, VT);
1378 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1379 DAG.getConstant(c1 + c2, N1.getValueType()));
1384 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1385 SDOperand N0 = N->getOperand(0);
1386 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1387 MVT::ValueType VT = N->getValueType(0);
1389 // fold (ctlz c1) -> c2
1391 return DAG.getNode(ISD::CTLZ, VT, N0);
1395 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1396 SDOperand N0 = N->getOperand(0);
1397 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1398 MVT::ValueType VT = N->getValueType(0);
1400 // fold (cttz c1) -> c2
1402 return DAG.getNode(ISD::CTTZ, VT, N0);
1406 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1407 SDOperand N0 = N->getOperand(0);
1408 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1409 MVT::ValueType VT = N->getValueType(0);
1411 // fold (ctpop c1) -> c2
1413 return DAG.getNode(ISD::CTPOP, VT, N0);
1417 SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1418 SDOperand N0 = N->getOperand(0);
1419 SDOperand N1 = N->getOperand(1);
1420 SDOperand N2 = N->getOperand(2);
1421 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1422 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1423 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1424 MVT::ValueType VT = N->getValueType(0);
1426 // fold select C, X, X -> X
1429 // fold select true, X, Y -> X
1430 if (N0C && !N0C->isNullValue())
1432 // fold select false, X, Y -> Y
1433 if (N0C && N0C->isNullValue())
1435 // fold select C, 1, X -> C | X
1436 if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1437 return DAG.getNode(ISD::OR, VT, N0, N2);
1438 // fold select C, 0, X -> ~C & X
1439 // FIXME: this should check for C type == X type, not i1?
1440 if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1441 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1442 WorkList.push_back(XORNode.Val);
1443 return DAG.getNode(ISD::AND, VT, XORNode, N2);
1445 // fold select C, X, 1 -> ~C | X
1446 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1447 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1448 WorkList.push_back(XORNode.Val);
1449 return DAG.getNode(ISD::OR, VT, XORNode, N1);
1451 // fold select C, X, 0 -> C & X
1452 // FIXME: this should check for C type == X type, not i1?
1453 if (MVT::i1 == VT && N2C && N2C->isNullValue())
1454 return DAG.getNode(ISD::AND, VT, N0, N1);
1455 // fold X ? X : Y --> X ? 1 : Y --> X | Y
1456 if (MVT::i1 == VT && N0 == N1)
1457 return DAG.getNode(ISD::OR, VT, N0, N2);
1458 // fold X ? Y : X --> X ? Y : 0 --> X & Y
1459 if (MVT::i1 == VT && N0 == N2)
1460 return DAG.getNode(ISD::AND, VT, N0, N1);
1461 // If we can fold this based on the true/false value, do so.
1462 if (SimplifySelectOps(N, N1, N2))
1464 // fold selects based on a setcc into other things, such as min/max/abs
1465 if (N0.getOpcode() == ISD::SETCC)
1467 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
1468 // having to say they don't support SELECT_CC on every type the DAG knows
1469 // about, since there is no way to mark an opcode illegal at all value types
1470 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other))
1471 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1),
1472 N1, N2, N0.getOperand(2));
1474 return SimplifySelect(N0, N1, N2);
1478 SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1479 SDOperand N0 = N->getOperand(0);
1480 SDOperand N1 = N->getOperand(1);
1481 SDOperand N2 = N->getOperand(2);
1482 SDOperand N3 = N->getOperand(3);
1483 SDOperand N4 = N->getOperand(4);
1484 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1485 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1486 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1487 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1489 // Determine if the condition we're dealing with is constant
1490 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1491 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1493 // fold select_cc lhs, rhs, x, x, cc -> x
1497 // If we can fold this based on the true/false value, do so.
1498 if (SimplifySelectOps(N, N2, N3))
1501 // fold select_cc into other things, such as min/max/abs
1502 return SimplifySelectCC(N0, N1, N2, N3, CC);
1505 SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1506 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1507 cast<CondCodeSDNode>(N->getOperand(2))->get());
1510 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1511 SDOperand N0 = N->getOperand(0);
1512 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1513 MVT::ValueType VT = N->getValueType(0);
1515 // fold (sext c1) -> c1
1517 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0);
1518 // fold (sext (sext x)) -> (sext x)
1519 if (N0.getOpcode() == ISD::SIGN_EXTEND)
1520 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1521 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
1522 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1524 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
1525 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
1526 DAG.getValueType(N0.getValueType()));
1527 // fold (sext (load x)) -> (sext (truncate (sextload x)))
1528 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1529 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){
1530 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1531 N0.getOperand(1), N0.getOperand(2),
1533 CombineTo(N, ExtLoad);
1534 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1535 ExtLoad.getValue(1));
1539 // fold (sext (sextload x)) -> (sext (truncate (sextload x)))
1540 // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
1541 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1543 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0),
1544 N0.getOperand(1), N0.getOperand(2),
1546 CombineTo(N, ExtLoad);
1547 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1548 ExtLoad.getValue(1));
1555 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1556 SDOperand N0 = N->getOperand(0);
1557 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1558 MVT::ValueType VT = N->getValueType(0);
1560 // fold (zext c1) -> c1
1562 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
1563 // fold (zext (zext x)) -> (zext x)
1564 if (N0.getOpcode() == ISD::ZERO_EXTEND)
1565 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1566 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size.
1567 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
1568 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType())))
1569 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType());
1570 // fold (zext (load x)) -> (zext (truncate (zextload x)))
1571 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() &&
1572 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){
1573 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1574 N0.getOperand(1), N0.getOperand(2),
1576 CombineTo(N, ExtLoad);
1577 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1578 ExtLoad.getValue(1));
1582 // fold (zext (zextload x)) -> (zext (truncate (zextload x)))
1583 // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
1584 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) &&
1586 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0),
1587 N0.getOperand(1), N0.getOperand(2),
1589 CombineTo(N, ExtLoad);
1590 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1591 ExtLoad.getValue(1));
1597 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1598 SDOperand N0 = N->getOperand(0);
1599 SDOperand N1 = N->getOperand(1);
1600 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1601 MVT::ValueType VT = N->getValueType(0);
1602 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1603 unsigned EVTBits = MVT::getSizeInBits(EVT);
1605 // fold (sext_in_reg c1) -> c1
1607 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1608 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1610 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1611 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1612 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1615 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1616 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1617 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1618 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1620 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1621 if (N0.getOpcode() == ISD::AssertSext &&
1622 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1625 // fold (sext_in_reg (sextload x)) -> (sextload x)
1626 if (N0.getOpcode() == ISD::SEXTLOAD &&
1627 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1630 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1631 if (N0.getOpcode() == ISD::SETCC &&
1632 TLI.getSetCCResultContents() ==
1633 TargetLowering::ZeroOrNegativeOneSetCCResult)
1635 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1636 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
1637 return DAG.getZeroExtendInReg(N0, EVT);
1638 // fold (sext_in_reg (srl x)) -> sra x
1639 if (N0.getOpcode() == ISD::SRL &&
1640 N0.getOperand(1).getOpcode() == ISD::Constant &&
1641 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1642 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1645 // fold (sext_inreg (extload x)) -> (sextload x)
1646 if (N0.getOpcode() == ISD::EXTLOAD &&
1647 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1648 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1649 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1650 N0.getOperand(1), N0.getOperand(2),
1652 CombineTo(N, ExtLoad);
1653 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1656 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1657 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() &&
1658 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1659 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1660 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1661 N0.getOperand(1), N0.getOperand(2),
1663 CombineTo(N, ExtLoad);
1664 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1670 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1671 SDOperand N0 = N->getOperand(0);
1672 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1673 MVT::ValueType VT = N->getValueType(0);
1676 if (N0.getValueType() == N->getValueType(0))
1678 // fold (truncate c1) -> c1
1680 return DAG.getNode(ISD::TRUNCATE, VT, N0);
1681 // fold (truncate (truncate x)) -> (truncate x)
1682 if (N0.getOpcode() == ISD::TRUNCATE)
1683 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1684 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1685 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1686 if (N0.getValueType() < VT)
1687 // if the source is smaller than the dest, we still need an extend
1688 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1689 else if (N0.getValueType() > VT)
1690 // if the source is larger than the dest, than we just need the truncate
1691 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1693 // if the source and dest are the same type, we can drop both the extend
1695 return N0.getOperand(0);
1697 // fold (truncate (load x)) -> (smaller load x)
1698 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1699 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1700 "Cannot truncate to larger type!");
1701 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1702 // For big endian targets, we need to add an offset to the pointer to load
1703 // the correct bytes. For little endian systems, we merely need to read
1704 // fewer bytes from the same pointer.
1706 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1707 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1708 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1709 DAG.getConstant(PtrOff, PtrType));
1710 WorkList.push_back(NewPtr.Val);
1711 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1712 WorkList.push_back(N);
1713 CombineTo(N0.Val, Load, Load.getValue(1));
1719 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
1720 SDOperand N0 = N->getOperand(0);
1721 MVT::ValueType VT = N->getValueType(0);
1723 // If the input is a constant, let getNode() fold it.
1724 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
1725 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0);
1726 if (Res.Val != N) return Res;
1729 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2)
1730 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
1732 // fold (conv (load x)) -> (load (conv*)x)
1733 // FIXME: These xforms need to know that the resultant load doesn't need a
1734 // higher alignment than the original!
1735 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) {
1736 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1),
1738 WorkList.push_back(N);
1739 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
1747 SDOperand DAGCombiner::visitFADD(SDNode *N) {
1748 SDOperand N0 = N->getOperand(0);
1749 SDOperand N1 = N->getOperand(1);
1750 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1751 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1752 MVT::ValueType VT = N->getValueType(0);
1754 // fold (fadd c1, c2) -> c1+c2
1756 return DAG.getNode(ISD::FADD, VT, N0, N1);
1757 // canonicalize constant to RHS
1758 if (N0CFP && !N1CFP)
1759 return DAG.getNode(ISD::FADD, VT, N1, N0);
1760 // fold (A + (-B)) -> A-B
1761 if (N1.getOpcode() == ISD::FNEG)
1762 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1763 // fold ((-A) + B) -> B-A
1764 if (N0.getOpcode() == ISD::FNEG)
1765 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1769 SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1770 SDOperand N0 = N->getOperand(0);
1771 SDOperand N1 = N->getOperand(1);
1772 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1773 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1774 MVT::ValueType VT = N->getValueType(0);
1776 // fold (fsub c1, c2) -> c1-c2
1778 return DAG.getNode(ISD::FSUB, VT, N0, N1);
1779 // fold (A-(-B)) -> A+B
1780 if (N1.getOpcode() == ISD::FNEG)
1781 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0));
1785 SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1786 SDOperand N0 = N->getOperand(0);
1787 SDOperand N1 = N->getOperand(1);
1788 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1789 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1790 MVT::ValueType VT = N->getValueType(0);
1792 // fold (fmul c1, c2) -> c1*c2
1794 return DAG.getNode(ISD::FMUL, VT, N0, N1);
1795 // canonicalize constant to RHS
1796 if (N0CFP && !N1CFP)
1797 return DAG.getNode(ISD::FMUL, VT, N1, N0);
1798 // fold (fmul X, 2.0) -> (fadd X, X)
1799 if (N1CFP && N1CFP->isExactlyValue(+2.0))
1800 return DAG.getNode(ISD::FADD, VT, N0, N0);
1804 SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1805 SDOperand N0 = N->getOperand(0);
1806 SDOperand N1 = N->getOperand(1);
1807 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1808 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1809 MVT::ValueType VT = N->getValueType(0);
1811 // fold (fdiv c1, c2) -> c1/c2
1813 return DAG.getNode(ISD::FDIV, VT, N0, N1);
1817 SDOperand DAGCombiner::visitFREM(SDNode *N) {
1818 SDOperand N0 = N->getOperand(0);
1819 SDOperand N1 = N->getOperand(1);
1820 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1821 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
1822 MVT::ValueType VT = N->getValueType(0);
1824 // fold (frem c1, c2) -> fmod(c1,c2)
1826 return DAG.getNode(ISD::FREM, VT, N0, N1);
1831 SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1832 SDOperand N0 = N->getOperand(0);
1833 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1834 MVT::ValueType VT = N->getValueType(0);
1836 // fold (sint_to_fp c1) -> c1fp
1838 return DAG.getNode(ISD::SINT_TO_FP, VT, N0);
1842 SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1843 SDOperand N0 = N->getOperand(0);
1844 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1845 MVT::ValueType VT = N->getValueType(0);
1847 // fold (uint_to_fp c1) -> c1fp
1849 return DAG.getNode(ISD::UINT_TO_FP, VT, N0);
1853 SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1854 SDOperand N0 = N->getOperand(0);
1855 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1856 MVT::ValueType VT = N->getValueType(0);
1858 // fold (fp_to_sint c1fp) -> c1
1860 return DAG.getNode(ISD::FP_TO_SINT, VT, N0);
1864 SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1865 SDOperand N0 = N->getOperand(0);
1866 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1867 MVT::ValueType VT = N->getValueType(0);
1869 // fold (fp_to_uint c1fp) -> c1
1871 return DAG.getNode(ISD::FP_TO_UINT, VT, N0);
1875 SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1876 SDOperand N0 = N->getOperand(0);
1877 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1878 MVT::ValueType VT = N->getValueType(0);
1880 // fold (fp_round c1fp) -> c1fp
1882 return DAG.getNode(ISD::FP_ROUND, VT, N0);
1886 SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1887 SDOperand N0 = N->getOperand(0);
1888 MVT::ValueType VT = N->getValueType(0);
1889 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1890 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1892 // fold (fp_round_inreg c1fp) -> c1fp
1894 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1895 return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1900 SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1901 SDOperand N0 = N->getOperand(0);
1902 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1903 MVT::ValueType VT = N->getValueType(0);
1905 // fold (fp_extend c1fp) -> c1fp
1907 return DAG.getNode(ISD::FP_EXTEND, VT, N0);
1911 SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1912 SDOperand N0 = N->getOperand(0);
1913 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1914 MVT::ValueType VT = N->getValueType(0);
1916 // fold (fneg c1) -> -c1
1918 return DAG.getNode(ISD::FNEG, VT, N0);
1919 // fold (fneg (sub x, y)) -> (sub y, x)
1920 if (N->getOperand(0).getOpcode() == ISD::SUB)
1921 return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0));
1922 // fold (fneg (fneg x)) -> x
1923 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1924 return N->getOperand(0).getOperand(0);
1928 SDOperand DAGCombiner::visitFABS(SDNode *N) {
1929 SDOperand N0 = N->getOperand(0);
1930 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1931 MVT::ValueType VT = N->getValueType(0);
1933 // fold (fabs c1) -> fabs(c1)
1935 return DAG.getNode(ISD::FABS, VT, N0);
1936 // fold (fabs (fabs x)) -> (fabs x)
1937 if (N->getOperand(0).getOpcode() == ISD::FABS)
1938 return N->getOperand(0);
1939 // fold (fabs (fneg x)) -> (fabs x)
1940 if (N->getOperand(0).getOpcode() == ISD::FNEG)
1941 return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0));
1945 SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
1946 SDOperand Chain = N->getOperand(0);
1947 SDOperand N1 = N->getOperand(1);
1948 SDOperand N2 = N->getOperand(2);
1949 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1951 // never taken branch, fold to chain
1952 if (N1C && N1C->isNullValue())
1954 // unconditional branch
1955 if (N1C && N1C->getValue() == 1)
1956 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1957 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
1959 if (N1.getOpcode() == ISD::SETCC &&
1960 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) {
1961 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2),
1962 N1.getOperand(0), N1.getOperand(1), N2);
1967 SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
1968 SDOperand Chain = N->getOperand(0);
1969 SDOperand N1 = N->getOperand(1);
1970 SDOperand N2 = N->getOperand(2);
1971 SDOperand N3 = N->getOperand(3);
1972 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1974 // unconditional branch to true mbb
1975 if (N1C && N1C->getValue() == 1)
1976 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1977 // unconditional branch to false mbb
1978 if (N1C && N1C->isNullValue())
1979 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
1980 // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if
1981 // BRTWOWAY_CC is legal on the target.
1982 if (N1.getOpcode() == ISD::SETCC &&
1983 TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
1984 std::vector<SDOperand> Ops;
1985 Ops.push_back(Chain);
1986 Ops.push_back(N1.getOperand(2));
1987 Ops.push_back(N1.getOperand(0));
1988 Ops.push_back(N1.getOperand(1));
1991 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
1996 // Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
1998 SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
1999 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
2000 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
2002 // Use SimplifySetCC to simplify SETCC's.
2003 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
2004 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
2006 // fold br_cc true, dest -> br dest (unconditional branch)
2007 if (SCCC && SCCC->getValue())
2008 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
2010 // fold br_cc false, dest -> unconditional fall through
2011 if (SCCC && SCCC->isNullValue())
2012 return N->getOperand(0);
2013 // fold to a simpler setcc
2014 if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
2015 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
2016 Simp.getOperand(2), Simp.getOperand(0),
2017 Simp.getOperand(1), N->getOperand(4));
2021 SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
2022 SDOperand Chain = N->getOperand(0);
2023 SDOperand CCN = N->getOperand(1);
2024 SDOperand LHS = N->getOperand(2);
2025 SDOperand RHS = N->getOperand(3);
2026 SDOperand N4 = N->getOperand(4);
2027 SDOperand N5 = N->getOperand(5);
2029 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
2030 cast<CondCodeSDNode>(CCN)->get(), false);
2031 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2033 // fold select_cc lhs, rhs, x, x, cc -> x
2035 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2036 // fold select_cc true, x, y -> x
2037 if (SCCC && SCCC->getValue())
2038 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
2039 // fold select_cc false, x, y -> y
2040 if (SCCC && SCCC->isNullValue())
2041 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
2042 // fold to a simpler setcc
2043 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) {
2044 std::vector<SDOperand> Ops;
2045 Ops.push_back(Chain);
2046 Ops.push_back(SCC.getOperand(2));
2047 Ops.push_back(SCC.getOperand(0));
2048 Ops.push_back(SCC.getOperand(1));
2051 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
2056 SDOperand DAGCombiner::visitLOAD(SDNode *N) {
2057 SDOperand Chain = N->getOperand(0);
2058 SDOperand Ptr = N->getOperand(1);
2059 SDOperand SrcValue = N->getOperand(2);
2061 // If this load is directly stored, replace the load value with the stored
2063 // TODO: Handle store large -> read small portion.
2064 // TODO: Handle TRUNCSTORE/EXTLOAD
2065 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2066 Chain.getOperand(1).getValueType() == N->getValueType(0))
2067 return CombineTo(N, Chain.getOperand(1), Chain);
2072 SDOperand DAGCombiner::visitSTORE(SDNode *N) {
2073 SDOperand Chain = N->getOperand(0);
2074 SDOperand Value = N->getOperand(1);
2075 SDOperand Ptr = N->getOperand(2);
2076 SDOperand SrcValue = N->getOperand(3);
2078 // If this is a store that kills a previous store, remove the previous store.
2079 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
2080 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ &&
2081 // Make sure that these stores are the same value type:
2082 // FIXME: we really care that the second store is >= size of the first.
2083 Value.getValueType() == Chain.getOperand(1).getValueType()) {
2084 // Create a new store of Value that replaces both stores.
2085 SDNode *PrevStore = Chain.Val;
2086 if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
2088 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
2089 PrevStore->getOperand(0), Value, Ptr,
2091 CombineTo(N, NewStore); // Nuke this store.
2092 CombineTo(PrevStore, NewStore); // Nuke the previous store.
2093 return SDOperand(N, 0);
2096 // If this is a store of a bit convert, store the input value.
2097 // FIXME: This needs to know that the resultant store does not need a
2098 // higher alignment than the original.
2099 if (0 && Value.getOpcode() == ISD::BIT_CONVERT)
2100 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0),
2106 SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
2107 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
2109 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
2110 cast<CondCodeSDNode>(N0.getOperand(2))->get());
2111 // If we got a simplified select_cc node back from SimplifySelectCC, then
2112 // break it down into a new SETCC node, and a new SELECT node, and then return
2113 // the SELECT node, since we were called with a SELECT node.
2115 // Check to see if we got a select_cc back (to turn into setcc/select).
2116 // Otherwise, just return whatever node we got back, like fabs.
2117 if (SCC.getOpcode() == ISD::SELECT_CC) {
2118 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
2119 SCC.getOperand(0), SCC.getOperand(1),
2121 WorkList.push_back(SETCC.Val);
2122 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
2123 SCC.getOperand(3), SETCC);
2130 /// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS
2131 /// are the two values being selected between, see if we can simplify the
2134 bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
2137 // If this is a select from two identical things, try to pull the operation
2138 // through the select.
2139 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){
2141 std::cerr << "SELECT: ["; LHS.Val->dump();
2142 std::cerr << "] ["; RHS.Val->dump();
2146 // If this is a load and the token chain is identical, replace the select
2147 // of two loads with a load through a select of the address to load from.
2148 // This triggers in things like "select bool X, 10.0, 123.0" after the FP
2149 // constants have been dropped into the constant pool.
2150 if ((LHS.getOpcode() == ISD::LOAD ||
2151 LHS.getOpcode() == ISD::EXTLOAD ||
2152 LHS.getOpcode() == ISD::ZEXTLOAD ||
2153 LHS.getOpcode() == ISD::SEXTLOAD) &&
2154 // Token chains must be identical.
2155 LHS.getOperand(0) == RHS.getOperand(0) &&
2156 // If this is an EXTLOAD, the VT's must match.
2157 (LHS.getOpcode() == ISD::LOAD ||
2158 LHS.getOperand(3) == RHS.getOperand(3))) {
2159 // FIXME: this conflates two src values, discarding one. This is not
2160 // the right thing to do, but nothing uses srcvalues now. When they do,
2161 // turn SrcValue into a list of locations.
2163 if (TheSelect->getOpcode() == ISD::SELECT)
2164 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(),
2165 TheSelect->getOperand(0), LHS.getOperand(1),
2168 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(),
2169 TheSelect->getOperand(0),
2170 TheSelect->getOperand(1),
2171 LHS.getOperand(1), RHS.getOperand(1),
2172 TheSelect->getOperand(4));
2175 if (LHS.getOpcode() == ISD::LOAD)
2176 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0),
2177 Addr, LHS.getOperand(2));
2179 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0),
2180 LHS.getOperand(0), Addr, LHS.getOperand(2),
2181 cast<VTSDNode>(LHS.getOperand(3))->getVT());
2182 // Users of the select now use the result of the load.
2183 CombineTo(TheSelect, Load);
2185 // Users of the old loads now use the new load's chain. We know the
2186 // old-load value is dead now.
2187 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
2188 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
2196 SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
2197 SDOperand N2, SDOperand N3,
2200 MVT::ValueType VT = N2.getValueType();
2201 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
2202 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
2203 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
2204 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
2206 // Determine if the condition we're dealing with is constant
2207 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
2208 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
2210 // fold select_cc true, x, y -> x
2211 if (SCCC && SCCC->getValue())
2213 // fold select_cc false, x, y -> y
2214 if (SCCC && SCCC->getValue() == 0)
2217 // Check to see if we can simplify the select into an fabs node
2218 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
2219 // Allow either -0.0 or 0.0
2220 if (CFP->getValue() == 0.0) {
2221 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
2222 if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
2223 N0 == N2 && N3.getOpcode() == ISD::FNEG &&
2224 N2 == N3.getOperand(0))
2225 return DAG.getNode(ISD::FABS, VT, N0);
2227 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
2228 if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
2229 N0 == N3 && N2.getOpcode() == ISD::FNEG &&
2230 N2.getOperand(0) == N3)
2231 return DAG.getNode(ISD::FABS, VT, N3);
2235 // Check to see if we can perform the "gzip trick", transforming
2236 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
2237 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
2238 MVT::isInteger(N0.getValueType()) &&
2239 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
2240 MVT::ValueType XType = N0.getValueType();
2241 MVT::ValueType AType = N2.getValueType();
2242 if (XType >= AType) {
2243 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
2244 // single-bit constant.
2245 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
2246 unsigned ShCtV = Log2_64(N2C->getValue());
2247 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
2248 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
2249 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
2250 WorkList.push_back(Shift.Val);
2251 if (XType > AType) {
2252 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2253 WorkList.push_back(Shift.Val);
2255 return DAG.getNode(ISD::AND, AType, Shift, N2);
2257 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2258 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2259 TLI.getShiftAmountTy()));
2260 WorkList.push_back(Shift.Val);
2261 if (XType > AType) {
2262 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
2263 WorkList.push_back(Shift.Val);
2265 return DAG.getNode(ISD::AND, AType, Shift, N2);
2269 // fold select C, 16, 0 -> shl C, 4
2270 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
2271 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
2272 // Get a SetCC of the condition
2273 // FIXME: Should probably make sure that setcc is legal if we ever have a
2274 // target where it isn't.
2275 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2276 WorkList.push_back(SCC.Val);
2277 // cast from setcc result type to select result type
2279 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
2281 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
2282 WorkList.push_back(Temp.Val);
2283 // shl setcc result by log2 n2c
2284 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
2285 DAG.getConstant(Log2_64(N2C->getValue()),
2286 TLI.getShiftAmountTy()));
2289 // Check to see if this is the equivalent of setcc
2290 // FIXME: Turn all of these into setcc if setcc if setcc is legal
2291 // otherwise, go ahead with the folds.
2292 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
2293 MVT::ValueType XType = N0.getValueType();
2294 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
2295 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
2296 if (Res.getValueType() != VT)
2297 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
2301 // seteq X, 0 -> srl (ctlz X, log2(size(X)))
2302 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
2303 TLI.isOperationLegal(ISD::CTLZ, XType)) {
2304 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
2305 return DAG.getNode(ISD::SRL, XType, Ctlz,
2306 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
2307 TLI.getShiftAmountTy()));
2309 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
2310 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
2311 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
2313 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
2314 DAG.getConstant(~0ULL, XType));
2315 return DAG.getNode(ISD::SRL, XType,
2316 DAG.getNode(ISD::AND, XType, NegN0, NotN0),
2317 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2318 TLI.getShiftAmountTy()));
2320 // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
2321 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
2322 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
2323 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2324 TLI.getShiftAmountTy()));
2325 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
2329 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
2330 // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2331 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
2332 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
2333 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
2334 MVT::ValueType XType = N0.getValueType();
2335 if (SubC->isNullValue() && MVT::isInteger(XType)) {
2336 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
2337 DAG.getConstant(MVT::getSizeInBits(XType)-1,
2338 TLI.getShiftAmountTy()));
2339 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
2340 WorkList.push_back(Shift.Val);
2341 WorkList.push_back(Add.Val);
2342 return DAG.getNode(ISD::XOR, XType, Add, Shift);
2350 SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
2351 SDOperand N1, ISD::CondCode Cond,
2352 bool foldBooleans) {
2353 // These setcc operations always fold.
2357 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
2359 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
2362 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
2363 uint64_t C1 = N1C->getValue();
2364 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
2365 uint64_t C0 = N0C->getValue();
2367 // Sign extend the operands if required
2368 if (ISD::isSignedIntSetCC(Cond)) {
2369 C0 = N0C->getSignExtended();
2370 C1 = N1C->getSignExtended();
2374 default: assert(0 && "Unknown integer setcc!");
2375 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2376 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2377 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT);
2378 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT);
2379 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
2380 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
2381 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT);
2382 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT);
2383 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
2384 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
2387 // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
2388 if (N0.getOpcode() == ISD::ZERO_EXTEND) {
2389 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
2391 // If the comparison constant has bits in the upper part, the
2392 // zero-extended value could never match.
2393 if (C1 & (~0ULL << InSize)) {
2394 unsigned VSize = MVT::getSizeInBits(N0.getValueType());
2398 case ISD::SETEQ: return DAG.getConstant(0, VT);
2401 case ISD::SETNE: return DAG.getConstant(1, VT);
2404 // True if the sign bit of C1 is set.
2405 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
2408 // True if the sign bit of C1 isn't set.
2409 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
2415 // Otherwise, we can perform the comparison with the low bits.
2423 return DAG.getSetCC(VT, N0.getOperand(0),
2424 DAG.getConstant(C1, N0.getOperand(0).getValueType()),
2427 break; // todo, be more careful with signed comparisons
2429 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
2430 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
2431 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
2432 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
2433 MVT::ValueType ExtDstTy = N0.getValueType();
2434 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
2436 // If the extended part has any inconsistent bits, it cannot ever
2437 // compare equal. In other words, they have to be all ones or all
2440 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
2441 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
2442 return DAG.getConstant(Cond == ISD::SETNE, VT);
2445 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
2446 if (Op0Ty == ExtSrcTy) {
2447 ZextOp = N0.getOperand(0);
2449 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
2450 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
2451 DAG.getConstant(Imm, Op0Ty));
2453 WorkList.push_back(ZextOp.Val);
2454 // Otherwise, make this a use of a zext.
2455 return DAG.getSetCC(VT, ZextOp,
2456 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
2459 } else if ((N1C->getValue() == 0 || N1C->getValue() == 1) &&
2460 (Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2461 (N0.getOpcode() == ISD::XOR ||
2462 (N0.getOpcode() == ISD::AND &&
2463 N0.getOperand(0).getOpcode() == ISD::XOR &&
2464 N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
2465 isa<ConstantSDNode>(N0.getOperand(1)) &&
2466 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == 1) {
2467 // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We can
2468 // only do this if the top bits are known zero.
2469 if (TLI.MaskedValueIsZero(N1,
2470 MVT::getIntVTBitMask(N0.getValueType())-1)) {
2471 // Okay, get the un-inverted input value.
2473 if (N0.getOpcode() == ISD::XOR)
2474 Val = N0.getOperand(0);
2476 assert(N0.getOpcode() == ISD::AND &&
2477 N0.getOperand(0).getOpcode() == ISD::XOR);
2478 // ((X^1)&1)^1 -> X & 1
2479 Val = DAG.getNode(ISD::AND, N0.getValueType(),
2480 N0.getOperand(0).getOperand(0), N0.getOperand(1));
2482 return DAG.getSetCC(VT, Val, N1,
2483 Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
2487 uint64_t MinVal, MaxVal;
2488 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
2489 if (ISD::isSignedIntSetCC(Cond)) {
2490 MinVal = 1ULL << (OperandBitSize-1);
2491 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined.
2492 MaxVal = ~0ULL >> (65-OperandBitSize);
2497 MaxVal = ~0ULL >> (64-OperandBitSize);
2500 // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2501 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2502 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
2503 --C1; // X >= C0 --> X > (C0-1)
2504 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2505 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2508 if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2509 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
2510 ++C1; // X <= C0 --> X < (C0+1)
2511 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2512 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2515 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2516 return DAG.getConstant(0, VT); // X < MIN --> false
2518 // Canonicalize setgt X, Min --> setne X, Min
2519 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2520 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2521 // Canonicalize setlt X, Max --> setne X, Max
2522 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal)
2523 return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2525 // If we have setult X, 1, turn it into seteq X, 0
2526 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2527 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
2529 // If we have setugt X, Max-1, turn it into seteq X, Max
2530 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2531 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
2534 // If we have "setcc X, C0", check to see if we can shrink the immediate
2537 // SETUGT X, SINTMAX -> SETLT X, 0
2538 if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
2539 C1 == (~0ULL >> (65-OperandBitSize)))
2540 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
2543 // FIXME: Implement the rest of these.
2545 // Fold bit comparisons when we can.
2546 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2547 VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
2548 if (ConstantSDNode *AndRHS =
2549 dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2550 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
2551 // Perform the xform if the AND RHS is a single bit.
2552 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
2553 return DAG.getNode(ISD::SRL, VT, N0,
2554 DAG.getConstant(Log2_64(AndRHS->getValue()),
2555 TLI.getShiftAmountTy()));
2557 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
2558 // (X & 8) == 8 --> (X & 8) >> 3
2559 // Perform the xform if C1 is a single bit.
2560 if ((C1 & (C1-1)) == 0) {
2561 return DAG.getNode(ISD::SRL, VT, N0,
2562 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
2567 } else if (isa<ConstantSDNode>(N0.Val)) {
2568 // Ensure that the constant occurs on the RHS.
2569 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2572 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
2573 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
2574 double C0 = N0C->getValue(), C1 = N1C->getValue();
2577 default: break; // FIXME: Implement the rest of these!
2578 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT);
2579 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT);
2580 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT);
2581 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT);
2582 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT);
2583 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT);
2586 // Ensure that the constant occurs on the RHS.
2587 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2591 // We can always fold X == Y for integer setcc's.
2592 if (MVT::isInteger(N0.getValueType()))
2593 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2594 unsigned UOF = ISD::getUnorderedFlavor(Cond);
2595 if (UOF == 2) // FP operators that are undefined on NaNs.
2596 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2597 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2598 return DAG.getConstant(UOF, VT);
2599 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO
2600 // if it is not already.
2601 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO;
2602 if (NewCond != Cond)
2603 return DAG.getSetCC(VT, N0, N1, NewCond);
2606 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2607 MVT::isInteger(N0.getValueType())) {
2608 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2609 N0.getOpcode() == ISD::XOR) {
2610 // Simplify (X+Y) == (X+Z) --> Y == Z
2611 if (N0.getOpcode() == N1.getOpcode()) {
2612 if (N0.getOperand(0) == N1.getOperand(0))
2613 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2614 if (N0.getOperand(1) == N1.getOperand(1))
2615 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2616 if (isCommutativeBinOp(N0.getOpcode())) {
2617 // If X op Y == Y op X, try other combinations.
2618 if (N0.getOperand(0) == N1.getOperand(1))
2619 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2620 if (N0.getOperand(1) == N1.getOperand(0))
2621 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond);
2625 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2626 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2627 // Turn (X+C1) == C2 --> X == C2-C1
2628 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) {
2629 return DAG.getSetCC(VT, N0.getOperand(0),
2630 DAG.getConstant(RHSC->getValue()-LHSR->getValue(),
2631 N0.getValueType()), Cond);
2634 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.
2635 if (N0.getOpcode() == ISD::XOR)
2636 // If we know that all of the inverted bits are zero, don't bother
2637 // performing the inversion.
2638 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue()))
2639 return DAG.getSetCC(VT, N0.getOperand(0),
2640 DAG.getConstant(LHSR->getValue()^RHSC->getValue(),
2641 N0.getValueType()), Cond);
2644 // Turn (C1-X) == C2 --> X == C1-C2
2645 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
2646 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) {
2647 return DAG.getSetCC(VT, N0.getOperand(1),
2648 DAG.getConstant(SUBC->getValue()-RHSC->getValue(),
2649 N0.getValueType()), Cond);
2654 // Simplify (X+Z) == X --> Z == 0
2655 if (N0.getOperand(0) == N1)
2656 return DAG.getSetCC(VT, N0.getOperand(1),
2657 DAG.getConstant(0, N0.getValueType()), Cond);
2658 if (N0.getOperand(1) == N1) {
2659 if (isCommutativeBinOp(N0.getOpcode()))
2660 return DAG.getSetCC(VT, N0.getOperand(0),
2661 DAG.getConstant(0, N0.getValueType()), Cond);
2663 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2664 // (Z-X) == X --> Z == X<<1
2665 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2667 DAG.getConstant(1,TLI.getShiftAmountTy()));
2668 WorkList.push_back(SH.Val);
2669 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2674 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2675 N1.getOpcode() == ISD::XOR) {
2676 // Simplify X == (X+Z) --> Z == 0
2677 if (N1.getOperand(0) == N0) {
2678 return DAG.getSetCC(VT, N1.getOperand(1),
2679 DAG.getConstant(0, N1.getValueType()), Cond);
2680 } else if (N1.getOperand(1) == N0) {
2681 if (isCommutativeBinOp(N1.getOpcode())) {
2682 return DAG.getSetCC(VT, N1.getOperand(0),
2683 DAG.getConstant(0, N1.getValueType()), Cond);
2685 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2686 // X == (Z-X) --> X<<1 == Z
2687 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2688 DAG.getConstant(1,TLI.getShiftAmountTy()));
2689 WorkList.push_back(SH.Val);
2690 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2696 // Fold away ALL boolean setcc's.
2698 if (N0.getValueType() == MVT::i1 && foldBooleans) {
2700 default: assert(0 && "Unknown integer setcc!");
2701 case ISD::SETEQ: // X == Y -> (X^Y)^1
2702 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2703 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2704 WorkList.push_back(Temp.Val);
2706 case ISD::SETNE: // X != Y --> (X^Y)
2707 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2709 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y
2710 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y
2711 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2712 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2713 WorkList.push_back(Temp.Val);
2715 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X
2716 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X
2717 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2718 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2719 WorkList.push_back(Temp.Val);
2721 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y
2722 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y
2723 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2724 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2725 WorkList.push_back(Temp.Val);
2727 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X
2728 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X
2729 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2730 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2733 if (VT != MVT::i1) {
2734 WorkList.push_back(N0.Val);
2735 // FIXME: If running after legalize, we probably can't do this.
2736 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2741 // Could not fold it.
2745 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
2746 /// return a DAG expression to select that will generate the same value by
2747 /// multiplying by a magic number. See:
2748 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2749 SDOperand DAGCombiner::BuildSDIV(SDNode *N) {
2750 MVT::ValueType VT = N->getValueType(0);
2752 // Check to see if we can do this.
2753 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2754 return SDOperand(); // BuildSDIV only operates on i32 or i64
2755 if (!TLI.isOperationLegal(ISD::MULHS, VT))
2756 return SDOperand(); // Make sure the target supports MULHS.
2758 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended();
2759 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d);
2761 // Multiply the numerator (operand 0) by the magic value
2762 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0),
2763 DAG.getConstant(magics.m, VT));
2764 // If d > 0 and m < 0, add the numerator
2765 if (d > 0 && magics.m < 0) {
2766 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0));
2767 WorkList.push_back(Q.Val);
2769 // If d < 0 and m > 0, subtract the numerator.
2770 if (d < 0 && magics.m > 0) {
2771 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0));
2772 WorkList.push_back(Q.Val);
2774 // Shift right algebraic if shift value is nonzero
2776 Q = DAG.getNode(ISD::SRA, VT, Q,
2777 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2778 WorkList.push_back(Q.Val);
2780 // Extract the sign bit and add it to the quotient
2782 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1,
2783 TLI.getShiftAmountTy()));
2784 WorkList.push_back(T.Val);
2785 return DAG.getNode(ISD::ADD, VT, Q, T);
2788 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
2789 /// return a DAG expression to select that will generate the same value by
2790 /// multiplying by a magic number. See:
2791 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
2792 SDOperand DAGCombiner::BuildUDIV(SDNode *N) {
2793 MVT::ValueType VT = N->getValueType(0);
2795 // Check to see if we can do this.
2796 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64))
2797 return SDOperand(); // BuildUDIV only operates on i32 or i64
2798 if (!TLI.isOperationLegal(ISD::MULHU, VT))
2799 return SDOperand(); // Make sure the target supports MULHU.
2801 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue();
2802 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d);
2804 // Multiply the numerator (operand 0) by the magic value
2805 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0),
2806 DAG.getConstant(magics.m, VT));
2807 WorkList.push_back(Q.Val);
2809 if (magics.a == 0) {
2810 return DAG.getNode(ISD::SRL, VT, Q,
2811 DAG.getConstant(magics.s, TLI.getShiftAmountTy()));
2813 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q);
2814 WorkList.push_back(NPQ.Val);
2815 NPQ = DAG.getNode(ISD::SRL, VT, NPQ,
2816 DAG.getConstant(1, TLI.getShiftAmountTy()));
2817 WorkList.push_back(NPQ.Val);
2818 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q);
2819 WorkList.push_back(NPQ.Val);
2820 return DAG.getNode(ISD::SRL, VT, NPQ,
2821 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy()));
2825 // SelectionDAG::Combine - This is the entry point for the file.
2827 void SelectionDAG::Combine(bool RunningAfterLegalize) {
2828 /// run - This is the main entry point to this class.
2830 DAGCombiner(*this).Run(RunningAfterLegalize);