1 //===-- FastISel.cpp - Implementation of the FastISel class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/CodeGen/Analysis.h"
43 #include "llvm/CodeGen/FastISel.h"
44 #include "llvm/ADT/Optional.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/Analysis/BranchProbabilityInfo.h"
47 #include "llvm/Analysis/Loads.h"
48 #include "llvm/CodeGen/Analysis.h"
49 #include "llvm/CodeGen/FunctionLoweringInfo.h"
50 #include "llvm/CodeGen/MachineFrameInfo.h"
51 #include "llvm/CodeGen/MachineInstrBuilder.h"
52 #include "llvm/CodeGen/MachineModuleInfo.h"
53 #include "llvm/CodeGen/MachineRegisterInfo.h"
54 #include "llvm/CodeGen/StackMaps.h"
55 #include "llvm/IR/DataLayout.h"
56 #include "llvm/IR/DebugInfo.h"
57 #include "llvm/IR/Function.h"
58 #include "llvm/IR/GlobalVariable.h"
59 #include "llvm/IR/Instructions.h"
60 #include "llvm/IR/IntrinsicInst.h"
61 #include "llvm/IR/Operator.h"
62 #include "llvm/Support/Debug.h"
63 #include "llvm/Support/ErrorHandling.h"
64 #include "llvm/Target/TargetInstrInfo.h"
65 #include "llvm/Target/TargetLibraryInfo.h"
66 #include "llvm/Target/TargetLowering.h"
67 #include "llvm/Target/TargetMachine.h"
68 #include "llvm/Target/TargetSubtargetInfo.h"
71 #define DEBUG_TYPE "isel"
73 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
74 "target-independent selector");
75 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
76 "target-specific selector");
77 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
79 void FastISel::ArgListEntry::setAttributes(ImmutableCallSite *CS,
81 IsSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
82 IsZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
83 IsInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
84 IsSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
85 IsNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
86 IsByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
87 IsInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
88 IsReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
89 Alignment = CS->getParamAlignment(AttrIdx);
92 /// Set the current block to which generated machine instructions will be
93 /// appended, and clear the local CSE map.
94 void FastISel::startNewBlock() {
95 LocalValueMap.clear();
97 // Instructions are appended to FuncInfo.MBB. If the basic block already
98 // contains labels or copies, use the last instruction as the last local
100 EmitStartPt = nullptr;
101 if (!FuncInfo.MBB->empty())
102 EmitStartPt = &FuncInfo.MBB->back();
103 LastLocalValue = EmitStartPt;
106 bool FastISel::lowerArguments() {
107 if (!FuncInfo.CanLowerReturn)
108 // Fallback to SDISel argument lowering code to deal with sret pointer
112 if (!fastLowerArguments())
115 // Enter arguments into ValueMap for uses in non-entry BBs.
116 for (Function::const_arg_iterator I = FuncInfo.Fn->arg_begin(),
117 E = FuncInfo.Fn->arg_end();
119 DenseMap<const Value *, unsigned>::iterator VI = LocalValueMap.find(I);
120 assert(VI != LocalValueMap.end() && "Missed an argument?");
121 FuncInfo.ValueMap[I] = VI->second;
126 void FastISel::flushLocalValueMap() {
127 LocalValueMap.clear();
128 LastLocalValue = EmitStartPt;
132 bool FastISel::hasTrivialKill(const Value *V) {
133 // Don't consider constants or arguments to have trivial kills.
134 const Instruction *I = dyn_cast<Instruction>(V);
138 // No-op casts are trivially coalesced by fast-isel.
139 if (const auto *Cast = dyn_cast<CastInst>(I))
140 if (Cast->isNoopCast(DL.getIntPtrType(Cast->getContext())) &&
141 !hasTrivialKill(Cast->getOperand(0)))
144 // Even the value might have only one use in the LLVM IR, it is possible that
145 // FastISel might fold the use into another instruction and now there is more
146 // than one use at the Machine Instruction level.
147 unsigned Reg = lookUpRegForValue(V);
148 if (Reg && !MRI.use_empty(Reg))
151 // GEPs with all zero indices are trivially coalesced by fast-isel.
152 if (const auto *GEP = dyn_cast<GetElementPtrInst>(I))
153 if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0)))
156 // Only instructions with a single use in the same basic block are considered
157 // to have trivial kills.
158 return I->hasOneUse() &&
159 !(I->getOpcode() == Instruction::BitCast ||
160 I->getOpcode() == Instruction::PtrToInt ||
161 I->getOpcode() == Instruction::IntToPtr) &&
162 cast<Instruction>(*I->user_begin())->getParent() == I->getParent();
165 unsigned FastISel::getRegForValue(const Value *V) {
166 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
167 // Don't handle non-simple values in FastISel.
168 if (!RealVT.isSimple())
171 // Ignore illegal types. We must do this before looking up the value
172 // in ValueMap because Arguments are given virtual registers regardless
173 // of whether FastISel can handle them.
174 MVT VT = RealVT.getSimpleVT();
175 if (!TLI.isTypeLegal(VT)) {
176 // Handle integer promotions, though, because they're common and easy.
177 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
178 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
183 // Look up the value to see if we already have a register for it.
184 unsigned Reg = lookUpRegForValue(V);
188 // In bottom-up mode, just create the virtual register which will be used
189 // to hold the value. It will be materialized later.
190 if (isa<Instruction>(V) &&
191 (!isa<AllocaInst>(V) ||
192 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
193 return FuncInfo.InitializeRegForValue(V);
195 SavePoint SaveInsertPt = enterLocalValueArea();
197 // Materialize the value in a register. Emit any instructions in the
199 Reg = materializeRegForValue(V, VT);
201 leaveLocalValueArea(SaveInsertPt);
206 unsigned FastISel::materializeConstant(const Value *V, MVT VT) {
208 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
209 if (CI->getValue().getActiveBits() <= 64)
210 Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
211 } else if (isa<AllocaInst>(V))
212 Reg = fastMaterializeAlloca(cast<AllocaInst>(V));
213 else if (isa<ConstantPointerNull>(V))
214 // Translate this as an integer zero so that it can be
215 // local-CSE'd with actual integer zeros.
216 Reg = getRegForValue(
217 Constant::getNullValue(DL.getIntPtrType(V->getContext())));
218 else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
219 if (CF->isNullValue())
220 Reg = fastMaterializeFloatZero(CF);
222 // Try to emit the constant directly.
223 Reg = fastEmit_f(VT, VT, ISD::ConstantFP, CF);
226 // Try to emit the constant by using an integer constant with a cast.
227 const APFloat &Flt = CF->getValueAPF();
228 EVT IntVT = TLI.getPointerTy();
231 uint32_t IntBitWidth = IntVT.getSizeInBits();
233 (void)Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
234 APFloat::rmTowardZero, &isExact);
236 APInt IntVal(IntBitWidth, x);
238 unsigned IntegerReg =
239 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
241 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg,
245 } else if (const auto *Op = dyn_cast<Operator>(V)) {
246 if (!selectOperator(Op, Op->getOpcode()))
247 if (!isa<Instruction>(Op) ||
248 !fastSelectInstruction(cast<Instruction>(Op)))
250 Reg = lookUpRegForValue(Op);
251 } else if (isa<UndefValue>(V)) {
252 Reg = createResultReg(TLI.getRegClassFor(VT));
253 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
254 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
259 /// Helper for getRegForValue. This function is called when the value isn't
260 /// already available in a register and must be materialized with new
262 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
264 // Give the target-specific code a try first.
265 if (isa<Constant>(V))
266 Reg = fastMaterializeConstant(cast<Constant>(V));
268 // If target-specific code couldn't or didn't want to handle the value, then
269 // give target-independent code a try.
271 Reg = materializeConstant(V, VT);
273 // Don't cache constant materializations in the general ValueMap.
274 // To do so would require tracking what uses they dominate.
276 LocalValueMap[V] = Reg;
277 LastLocalValue = MRI.getVRegDef(Reg);
282 unsigned FastISel::lookUpRegForValue(const Value *V) {
283 // Look up the value to see if we already have a register for it. We
284 // cache values defined by Instructions across blocks, and other values
285 // only locally. This is because Instructions already have the SSA
286 // def-dominates-use requirement enforced.
287 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
288 if (I != FuncInfo.ValueMap.end())
290 return LocalValueMap[V];
293 void FastISel::updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) {
294 if (!isa<Instruction>(I)) {
295 LocalValueMap[I] = Reg;
299 unsigned &AssignedReg = FuncInfo.ValueMap[I];
300 if (AssignedReg == 0)
301 // Use the new register.
303 else if (Reg != AssignedReg) {
304 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
305 for (unsigned i = 0; i < NumRegs; i++)
306 FuncInfo.RegFixups[AssignedReg + i] = Reg + i;
312 std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) {
313 unsigned IdxN = getRegForValue(Idx);
315 // Unhandled operand. Halt "fast" selection and bail.
316 return std::pair<unsigned, bool>(0, false);
318 bool IdxNIsKill = hasTrivialKill(Idx);
320 // If the index is smaller or larger than intptr_t, truncate or extend it.
321 MVT PtrVT = TLI.getPointerTy();
322 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
323 if (IdxVT.bitsLT(PtrVT)) {
324 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN,
327 } else if (IdxVT.bitsGT(PtrVT)) {
329 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN, IdxNIsKill);
332 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
335 void FastISel::recomputeInsertPt() {
336 if (getLastLocalValue()) {
337 FuncInfo.InsertPt = getLastLocalValue();
338 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
341 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
343 // Now skip past any EH_LABELs, which must remain at the beginning.
344 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
345 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
349 void FastISel::removeDeadCode(MachineBasicBlock::iterator I,
350 MachineBasicBlock::iterator E) {
351 assert(I && E && std::distance(I, E) > 0 && "Invalid iterator!");
353 MachineInstr *Dead = &*I;
355 Dead->eraseFromParent();
361 FastISel::SavePoint FastISel::enterLocalValueArea() {
362 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
363 DebugLoc OldDL = DbgLoc;
366 SavePoint SP = {OldInsertPt, OldDL};
370 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
371 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
372 LastLocalValue = std::prev(FuncInfo.InsertPt);
374 // Restore the previous insert position.
375 FuncInfo.InsertPt = OldInsertPt.InsertPt;
376 DbgLoc = OldInsertPt.DL;
379 bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) {
380 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
381 if (VT == MVT::Other || !VT.isSimple())
382 // Unhandled type. Halt "fast" selection and bail.
385 // We only handle legal types. For example, on x86-32 the instruction
386 // selector contains all of the 64-bit instructions from x86-64,
387 // under the assumption that i64 won't be used if the target doesn't
389 if (!TLI.isTypeLegal(VT)) {
390 // MVT::i1 is special. Allow AND, OR, or XOR because they
391 // don't require additional zeroing, which makes them easy.
392 if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
393 ISDOpcode == ISD::XOR))
394 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
399 // Check if the first operand is a constant, and handle it as "ri". At -O0,
400 // we don't have anything that canonicalizes operand order.
401 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
402 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
403 unsigned Op1 = getRegForValue(I->getOperand(1));
406 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
409 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, Op1IsKill,
410 CI->getZExtValue(), VT.getSimpleVT());
414 // We successfully emitted code for the given LLVM Instruction.
415 updateValueMap(I, ResultReg);
419 unsigned Op0 = getRegForValue(I->getOperand(0));
420 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
422 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
424 // Check if the second operand is a constant and handle it appropriately.
425 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
426 uint64_t Imm = CI->getZExtValue();
428 // Transform "sdiv exact X, 8" -> "sra X, 3".
429 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
430 cast<BinaryOperator>(I)->isExact() && isPowerOf2_64(Imm)) {
432 ISDOpcode = ISD::SRA;
435 // Transform "urem x, pow2" -> "and x, pow2-1".
436 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
437 isPowerOf2_64(Imm)) {
439 ISDOpcode = ISD::AND;
442 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
443 Op0IsKill, Imm, VT.getSimpleVT());
447 // We successfully emitted code for the given LLVM Instruction.
448 updateValueMap(I, ResultReg);
452 // Check if the second operand is a constant float.
453 if (const auto *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
454 unsigned ResultReg = fastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
455 ISDOpcode, Op0, Op0IsKill, CF);
457 // We successfully emitted code for the given LLVM Instruction.
458 updateValueMap(I, ResultReg);
463 unsigned Op1 = getRegForValue(I->getOperand(1));
464 if (!Op1) // Unhandled operand. Halt "fast" selection and bail.
466 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
468 // Now we have both operands in registers. Emit the instruction.
469 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
470 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill);
472 // Target-specific code wasn't able to find a machine opcode for
473 // the given ISD opcode and type. Halt "fast" selection and bail.
476 // We successfully emitted code for the given LLVM Instruction.
477 updateValueMap(I, ResultReg);
481 bool FastISel::selectGetElementPtr(const User *I) {
482 unsigned N = getRegForValue(I->getOperand(0));
483 if (!N) // Unhandled operand. Halt "fast" selection and bail.
485 bool NIsKill = hasTrivialKill(I->getOperand(0));
487 // Keep a running tab of the total offset to coalesce multiple N = N + Offset
488 // into a single N = N + TotalOffset.
489 uint64_t TotalOffs = 0;
490 // FIXME: What's a good SWAG number for MaxOffs?
491 uint64_t MaxOffs = 2048;
492 Type *Ty = I->getOperand(0)->getType();
493 MVT VT = TLI.getPointerTy();
494 for (GetElementPtrInst::const_op_iterator OI = I->op_begin() + 1,
497 const Value *Idx = *OI;
498 if (auto *StTy = dyn_cast<StructType>(Ty)) {
499 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
502 TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
503 if (TotalOffs >= MaxOffs) {
504 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
505 if (!N) // Unhandled operand. Halt "fast" selection and bail.
511 Ty = StTy->getElementType(Field);
513 Ty = cast<SequentialType>(Ty)->getElementType();
515 // If this is a constant subscript, handle it quickly.
516 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
521 DL.getTypeAllocSize(Ty) * cast<ConstantInt>(CI)->getSExtValue();
522 if (TotalOffs >= MaxOffs) {
523 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
524 if (!N) // Unhandled operand. Halt "fast" selection and bail.
532 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
533 if (!N) // Unhandled operand. Halt "fast" selection and bail.
539 // N = N + Idx * ElementSize;
540 uint64_t ElementSize = DL.getTypeAllocSize(Ty);
541 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
542 unsigned IdxN = Pair.first;
543 bool IdxNIsKill = Pair.second;
544 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
547 if (ElementSize != 1) {
548 IdxN = fastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
549 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
553 N = fastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
554 if (!N) // Unhandled operand. Halt "fast" selection and bail.
559 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
560 if (!N) // Unhandled operand. Halt "fast" selection and bail.
564 // We successfully emitted code for the given LLVM Instruction.
565 updateValueMap(I, N);
569 bool FastISel::addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
570 const CallInst *CI, unsigned StartIdx) {
571 for (unsigned i = StartIdx, e = CI->getNumArgOperands(); i != e; ++i) {
572 Value *Val = CI->getArgOperand(i);
573 // Check for constants and encode them with a StackMaps::ConstantOp prefix.
574 if (const auto *C = dyn_cast<ConstantInt>(Val)) {
575 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
576 Ops.push_back(MachineOperand::CreateImm(C->getSExtValue()));
577 } else if (isa<ConstantPointerNull>(Val)) {
578 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
579 Ops.push_back(MachineOperand::CreateImm(0));
580 } else if (auto *AI = dyn_cast<AllocaInst>(Val)) {
581 // Values coming from a stack location also require a sepcial encoding,
582 // but that is added later on by the target specific frame index
583 // elimination implementation.
584 auto SI = FuncInfo.StaticAllocaMap.find(AI);
585 if (SI != FuncInfo.StaticAllocaMap.end())
586 Ops.push_back(MachineOperand::CreateFI(SI->second));
590 unsigned Reg = getRegForValue(Val);
593 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
599 bool FastISel::selectStackmap(const CallInst *I) {
600 // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
601 // [live variables...])
602 assert(I->getCalledFunction()->getReturnType()->isVoidTy() &&
603 "Stackmap cannot return a value.");
605 // The stackmap intrinsic only records the live variables (the arguments
606 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
607 // intrinsic, this won't be lowered to a function call. This means we don't
608 // have to worry about calling conventions and target-specific lowering code.
609 // Instead we perform the call lowering right here.
612 // STACKMAP(id, nbytes, ...)
615 SmallVector<MachineOperand, 32> Ops;
617 // Add the <id> and <numBytes> constants.
618 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
619 "Expected a constant integer.");
620 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
621 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
623 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
624 "Expected a constant integer.");
625 const auto *NumBytes =
626 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
627 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
629 // Push live variables for the stack map (skipping the first two arguments
630 // <id> and <numBytes>).
631 if (!addStackMapLiveVars(Ops, I, 2))
634 // We are not adding any register mask info here, because the stackmap doesn't
637 // Add scratch registers as implicit def and early clobber.
638 CallingConv::ID CC = I->getCallingConv();
639 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
640 for (unsigned i = 0; ScratchRegs[i]; ++i)
641 Ops.push_back(MachineOperand::CreateReg(
642 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
643 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
645 // Issue CALLSEQ_START
646 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
647 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
651 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
652 TII.get(TargetOpcode::STACKMAP));
653 for (auto const &MO : Ops)
657 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
658 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
662 // Inform the Frame Information that we have a stackmap in this function.
663 FuncInfo.MF->getFrameInfo()->setHasStackMap();
668 /// \brief Lower an argument list according to the target calling convention.
670 /// This is a helper for lowering intrinsics that follow a target calling
671 /// convention or require stack pointer adjustment. Only a subset of the
672 /// intrinsic's operands need to participate in the calling convention.
673 bool FastISel::lowerCallOperands(const CallInst *CI, unsigned ArgIdx,
674 unsigned NumArgs, const Value *Callee,
675 bool ForceRetVoidTy, CallLoweringInfo &CLI) {
677 Args.reserve(NumArgs);
679 // Populate the argument list.
680 // Attributes for args start at offset 1, after the return attribute.
681 ImmutableCallSite CS(CI);
682 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
683 ArgI != ArgE; ++ArgI) {
684 Value *V = CI->getOperand(ArgI);
686 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
690 Entry.Ty = V->getType();
691 Entry.setAttributes(&CS, AttrI);
692 Args.push_back(Entry);
695 Type *RetTy = ForceRetVoidTy ? Type::getVoidTy(CI->getType()->getContext())
697 CLI.setCallee(CI->getCallingConv(), RetTy, Callee, std::move(Args), NumArgs);
699 return lowerCallTo(CLI);
702 bool FastISel::selectPatchpoint(const CallInst *I) {
703 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
708 // [live variables...])
709 CallingConv::ID CC = I->getCallingConv();
710 bool IsAnyRegCC = CC == CallingConv::AnyReg;
711 bool HasDef = !I->getType()->isVoidTy();
712 Value *Callee = I->getOperand(PatchPointOpers::TargetPos);
714 // Get the real number of arguments participating in the call <numArgs>
715 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos)) &&
716 "Expected a constant integer.");
717 const auto *NumArgsVal =
718 cast<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos));
719 unsigned NumArgs = NumArgsVal->getZExtValue();
721 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
722 // This includes all meta-operands up to but not including CC.
723 unsigned NumMetaOpers = PatchPointOpers::CCPos;
724 assert(I->getNumArgOperands() >= NumMetaOpers + NumArgs &&
725 "Not enough arguments provided to the patchpoint intrinsic");
727 // For AnyRegCC the arguments are lowered later on manually.
728 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
729 CallLoweringInfo CLI;
730 if (!lowerCallOperands(I, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC, CLI))
733 assert(CLI.Call && "No call instruction specified.");
735 SmallVector<MachineOperand, 32> Ops;
737 // Add an explicit result reg if we use the anyreg calling convention.
738 if (IsAnyRegCC && HasDef) {
739 assert(CLI.NumResultRegs == 0 && "Unexpected result register.");
740 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
741 CLI.NumResultRegs = 1;
742 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true));
745 // Add the <id> and <numBytes> constants.
746 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
747 "Expected a constant integer.");
748 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
749 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
751 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
752 "Expected a constant integer.");
753 const auto *NumBytes =
754 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
755 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
757 // Assume that the callee is a constant address or null pointer.
758 // FIXME: handle function symbols in the future.
760 if (const auto *C = dyn_cast<IntToPtrInst>(Callee))
761 CalleeAddr = cast<ConstantInt>(C->getOperand(0))->getZExtValue();
762 else if (const auto *C = dyn_cast<ConstantExpr>(Callee)) {
763 if (C->getOpcode() == Instruction::IntToPtr)
764 CalleeAddr = cast<ConstantInt>(C->getOperand(0))->getZExtValue();
766 llvm_unreachable("Unsupported ConstantExpr.");
767 } else if (isa<ConstantPointerNull>(Callee))
770 llvm_unreachable("Unsupported callee address.");
772 Ops.push_back(MachineOperand::CreateImm(CalleeAddr));
774 // Adjust <numArgs> to account for any arguments that have been passed on
775 // the stack instead.
776 unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size();
777 Ops.push_back(MachineOperand::CreateImm(NumCallRegArgs));
779 // Add the calling convention
780 Ops.push_back(MachineOperand::CreateImm((unsigned)CC));
782 // Add the arguments we omitted previously. The register allocator should
783 // place these in any free register.
785 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) {
786 unsigned Reg = getRegForValue(I->getArgOperand(i));
789 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
793 // Push the arguments from the call instruction.
794 for (auto Reg : CLI.OutRegs)
795 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
797 // Push live variables for the stack map.
798 if (!addStackMapLiveVars(Ops, I, NumMetaOpers + NumArgs))
801 // Push the register mask info.
802 Ops.push_back(MachineOperand::CreateRegMask(TRI.getCallPreservedMask(CC)));
804 // Add scratch registers as implicit def and early clobber.
805 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
806 for (unsigned i = 0; ScratchRegs[i]; ++i)
807 Ops.push_back(MachineOperand::CreateReg(
808 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
809 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
811 // Add implicit defs (return values).
812 for (auto Reg : CLI.InRegs)
813 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/true,
816 // Insert the patchpoint instruction before the call generated by the target.
817 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, CLI.Call, DbgLoc,
818 TII.get(TargetOpcode::PATCHPOINT));
823 MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);
825 // Delete the original call instruction.
826 CLI.Call->eraseFromParent();
828 // Inform the Frame Information that we have a patchpoint in this function.
829 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
831 if (CLI.NumResultRegs)
832 updateValueMap(I, CLI.ResultReg, CLI.NumResultRegs);
836 /// Returns an AttributeSet representing the attributes applied to the return
837 /// value of the given call.
838 static AttributeSet getReturnAttrs(FastISel::CallLoweringInfo &CLI) {
839 SmallVector<Attribute::AttrKind, 2> Attrs;
841 Attrs.push_back(Attribute::SExt);
843 Attrs.push_back(Attribute::ZExt);
845 Attrs.push_back(Attribute::InReg);
847 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
851 bool FastISel::lowerCallTo(const CallInst *CI, const char *SymName,
853 ImmutableCallSite CS(CI);
855 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
856 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
857 Type *RetTy = FTy->getReturnType();
860 Args.reserve(NumArgs);
862 // Populate the argument list.
863 // Attributes for args start at offset 1, after the return attribute.
864 for (unsigned ArgI = 0; ArgI != NumArgs; ++ArgI) {
865 Value *V = CI->getOperand(ArgI);
867 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
871 Entry.Ty = V->getType();
872 Entry.setAttributes(&CS, ArgI + 1);
873 Args.push_back(Entry);
876 CallLoweringInfo CLI;
877 CLI.setCallee(RetTy, FTy, SymName, std::move(Args), CS, NumArgs);
879 return lowerCallTo(CLI);
882 bool FastISel::lowerCallTo(CallLoweringInfo &CLI) {
883 // Handle the incoming return values from the call.
885 SmallVector<EVT, 4> RetTys;
886 ComputeValueVTs(TLI, CLI.RetTy, RetTys);
888 SmallVector<ISD::OutputArg, 4> Outs;
889 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, TLI);
891 bool CanLowerReturn = TLI.CanLowerReturn(
892 CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
894 // FIXME: sret demotion isn't supported yet - bail out.
898 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
900 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT);
901 unsigned NumRegs = TLI.getNumRegisters(CLI.RetTy->getContext(), VT);
902 for (unsigned i = 0; i != NumRegs; ++i) {
903 ISD::InputArg MyFlags;
904 MyFlags.VT = RegisterVT;
906 MyFlags.Used = CLI.IsReturnValueUsed;
908 MyFlags.Flags.setSExt();
910 MyFlags.Flags.setZExt();
912 MyFlags.Flags.setInReg();
913 CLI.Ins.push_back(MyFlags);
917 // Handle all of the outgoing arguments.
919 for (auto &Arg : CLI.getArgs()) {
920 Type *FinalType = Arg.Ty;
922 FinalType = cast<PointerType>(Arg.Ty)->getElementType();
923 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
924 FinalType, CLI.CallConv, CLI.IsVarArg);
926 ISD::ArgFlagsTy Flags;
937 if (Arg.IsInAlloca) {
939 // Set the byval flag for CCAssignFn callbacks that don't know about
940 // inalloca. This way we can know how many bytes we should've allocated
941 // and how many bytes a callee cleanup function will pop. If we port
942 // inalloca to more targets, we'll have to add custom inalloca handling in
943 // the various CC lowering callbacks.
946 if (Arg.IsByVal || Arg.IsInAlloca) {
947 PointerType *Ty = cast<PointerType>(Arg.Ty);
948 Type *ElementTy = Ty->getElementType();
949 unsigned FrameSize = DL.getTypeAllocSize(ElementTy);
950 // For ByVal, alignment should come from FE. BE will guess if this info is
951 // not there, but there are cases it cannot get right.
952 unsigned FrameAlign = Arg.Alignment;
954 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
955 Flags.setByValSize(FrameSize);
956 Flags.setByValAlign(FrameAlign);
961 Flags.setInConsecutiveRegs();
962 unsigned OriginalAlignment = DL.getABITypeAlignment(Arg.Ty);
963 Flags.setOrigAlign(OriginalAlignment);
965 CLI.OutVals.push_back(Arg.Val);
966 CLI.OutFlags.push_back(Flags);
969 if (!fastLowerCall(CLI))
972 // Set all unused physreg defs as dead.
973 assert(CLI.Call && "No call instruction specified.");
974 CLI.Call->setPhysRegsDeadExcept(CLI.InRegs, TRI);
976 if (CLI.NumResultRegs && CLI.CS)
977 updateValueMap(CLI.CS->getInstruction(), CLI.ResultReg, CLI.NumResultRegs);
982 bool FastISel::lowerCall(const CallInst *CI) {
983 ImmutableCallSite CS(CI);
985 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
986 FunctionType *FuncTy = cast<FunctionType>(PT->getElementType());
987 Type *RetTy = FuncTy->getReturnType();
991 Args.reserve(CS.arg_size());
993 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
998 if (V->getType()->isEmptyTy())
1002 Entry.Ty = V->getType();
1004 // Skip the first return-type Attribute to get to params.
1005 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
1006 Args.push_back(Entry);
1009 // Check if target-independent constraints permit a tail call here.
1010 // Target-dependent constraints are checked within fastLowerCall.
1011 bool IsTailCall = CI->isTailCall();
1012 if (IsTailCall && !isInTailCallPosition(CS, TM))
1015 CallLoweringInfo CLI;
1016 CLI.setCallee(RetTy, FuncTy, CI->getCalledValue(), std::move(Args), CS)
1017 .setTailCall(IsTailCall);
1019 return lowerCallTo(CLI);
1022 bool FastISel::selectCall(const User *I) {
1023 const CallInst *Call = cast<CallInst>(I);
1025 // Handle simple inline asms.
1026 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledValue())) {
1027 // If the inline asm has side effects, then make sure that no local value
1028 // lives across by flushing the local value map.
1029 if (IA->hasSideEffects())
1030 flushLocalValueMap();
1032 // Don't attempt to handle constraints.
1033 if (!IA->getConstraintString().empty())
1036 unsigned ExtraInfo = 0;
1037 if (IA->hasSideEffects())
1038 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1039 if (IA->isAlignStack())
1040 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
1042 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1043 TII.get(TargetOpcode::INLINEASM))
1044 .addExternalSymbol(IA->getAsmString().c_str())
1049 MachineModuleInfo &MMI = FuncInfo.MF->getMMI();
1050 ComputeUsesVAFloatArgument(*Call, &MMI);
1052 // Handle intrinsic function calls.
1053 if (const auto *II = dyn_cast<IntrinsicInst>(Call))
1054 return selectIntrinsicCall(II);
1056 // Usually, it does not make sense to initialize a value,
1057 // make an unrelated function call and use the value, because
1058 // it tends to be spilled on the stack. So, we move the pointer
1059 // to the last local value to the beginning of the block, so that
1060 // all the values which have already been materialized,
1061 // appear after the call. It also makes sense to skip intrinsics
1062 // since they tend to be inlined.
1063 flushLocalValueMap();
1065 return lowerCall(Call);
1068 bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
1069 switch (II->getIntrinsicID()) {
1072 // At -O0 we don't care about the lifetime intrinsics.
1073 case Intrinsic::lifetime_start:
1074 case Intrinsic::lifetime_end:
1075 // The donothing intrinsic does, well, nothing.
1076 case Intrinsic::donothing:
1078 case Intrinsic::dbg_declare: {
1079 const DbgDeclareInst *DI = cast<DbgDeclareInst>(II);
1080 DIVariable DIVar(DI->getVariable());
1081 assert((!DIVar || DIVar.isVariable()) &&
1082 "Variable in DbgDeclareInst should be either null or a DIVariable.");
1083 if (!DIVar || !FuncInfo.MF->getMMI().hasDebugInfo()) {
1084 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1088 const Value *Address = DI->getAddress();
1089 if (!Address || isa<UndefValue>(Address)) {
1090 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1094 unsigned Offset = 0;
1095 Optional<MachineOperand> Op;
1096 if (const auto *Arg = dyn_cast<Argument>(Address))
1097 // Some arguments' frame index is recorded during argument lowering.
1098 Offset = FuncInfo.getArgumentFrameIndex(Arg);
1100 Op = MachineOperand::CreateFI(Offset);
1102 if (unsigned Reg = lookUpRegForValue(Address))
1103 Op = MachineOperand::CreateReg(Reg, false);
1105 // If we have a VLA that has a "use" in a metadata node that's then used
1106 // here but it has no other uses, then we have a problem. E.g.,
1108 // int foo (const int *x) {
1113 // If we assign 'a' a vreg and fast isel later on has to use the selection
1114 // DAG isel, it will want to copy the value to the vreg. However, there are
1115 // no uses, which goes counter to what selection DAG isel expects.
1116 if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&
1117 (!isa<AllocaInst>(Address) ||
1118 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
1119 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
1124 Op->setIsDebug(true);
1125 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1126 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0,
1129 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1130 TII.get(TargetOpcode::DBG_VALUE))
1133 .addMetadata(DI->getVariable());
1135 // We can't yet handle anything else here because it would require
1136 // generating code, thus altering codegen because of debug info.
1137 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1141 case Intrinsic::dbg_value: {
1142 // This form of DBG_VALUE is target-independent.
1143 const DbgValueInst *DI = cast<DbgValueInst>(II);
1144 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1145 const Value *V = DI->getValue();
1147 // Currently the optimizer can produce this; insert an undef to
1148 // help debugging. Probably the optimizer should not do this.
1149 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1151 .addImm(DI->getOffset())
1152 .addMetadata(DI->getVariable());
1153 } else if (const auto *CI = dyn_cast<ConstantInt>(V)) {
1154 if (CI->getBitWidth() > 64)
1155 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1157 .addImm(DI->getOffset())
1158 .addMetadata(DI->getVariable());
1160 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1161 .addImm(CI->getZExtValue())
1162 .addImm(DI->getOffset())
1163 .addMetadata(DI->getVariable());
1164 } else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
1165 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1167 .addImm(DI->getOffset())
1168 .addMetadata(DI->getVariable());
1169 } else if (unsigned Reg = lookUpRegForValue(V)) {
1170 // FIXME: This does not handle register-indirect values at offset 0.
1171 bool IsIndirect = DI->getOffset() != 0;
1172 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, IsIndirect, Reg,
1173 DI->getOffset(), DI->getVariable());
1175 // We can't yet handle anything else here because it would require
1176 // generating code, thus altering codegen because of debug info.
1177 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1181 case Intrinsic::objectsize: {
1182 ConstantInt *CI = cast<ConstantInt>(II->getArgOperand(1));
1183 unsigned long long Res = CI->isZero() ? -1ULL : 0;
1184 Constant *ResCI = ConstantInt::get(II->getType(), Res);
1185 unsigned ResultReg = getRegForValue(ResCI);
1188 updateValueMap(II, ResultReg);
1191 case Intrinsic::expect: {
1192 unsigned ResultReg = getRegForValue(II->getArgOperand(0));
1195 updateValueMap(II, ResultReg);
1198 case Intrinsic::experimental_stackmap:
1199 return selectStackmap(II);
1200 case Intrinsic::experimental_patchpoint_void:
1201 case Intrinsic::experimental_patchpoint_i64:
1202 return selectPatchpoint(II);
1205 return fastLowerIntrinsicCall(II);
1208 bool FastISel::selectCast(const User *I, unsigned Opcode) {
1209 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1210 EVT DstVT = TLI.getValueType(I->getType());
1212 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1214 // Unhandled type. Halt "fast" selection and bail.
1217 // Check if the destination type is legal.
1218 if (!TLI.isTypeLegal(DstVT))
1221 // Check if the source operand is legal.
1222 if (!TLI.isTypeLegal(SrcVT))
1225 unsigned InputReg = getRegForValue(I->getOperand(0));
1227 // Unhandled operand. Halt "fast" selection and bail.
1230 bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
1232 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1233 Opcode, InputReg, InputRegIsKill);
1237 updateValueMap(I, ResultReg);
1241 bool FastISel::selectBitCast(const User *I) {
1242 // If the bitcast doesn't change the type, just use the operand value.
1243 if (I->getType() == I->getOperand(0)->getType()) {
1244 unsigned Reg = getRegForValue(I->getOperand(0));
1247 updateValueMap(I, Reg);
1251 // Bitcasts of other values become reg-reg copies or BITCAST operators.
1252 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType());
1253 EVT DstEVT = TLI.getValueType(I->getType());
1254 if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
1255 !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
1256 // Unhandled type. Halt "fast" selection and bail.
1259 MVT SrcVT = SrcEVT.getSimpleVT();
1260 MVT DstVT = DstEVT.getSimpleVT();
1261 unsigned Op0 = getRegForValue(I->getOperand(0));
1262 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
1264 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
1266 // First, try to perform the bitcast by inserting a reg-reg copy.
1267 unsigned ResultReg = 0;
1268 if (SrcVT == DstVT) {
1269 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1270 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
1271 // Don't attempt a cross-class copy. It will likely fail.
1272 if (SrcClass == DstClass) {
1273 ResultReg = createResultReg(DstClass);
1274 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1275 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
1279 // If the reg-reg copy failed, select a BITCAST opcode.
1281 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1286 updateValueMap(I, ResultReg);
1290 bool FastISel::selectInstruction(const Instruction *I) {
1291 // Just before the terminator instruction, insert instructions to
1292 // feed PHI nodes in successor blocks.
1293 if (isa<TerminatorInst>(I))
1294 if (!handlePHINodesInSuccessorBlocks(I->getParent()))
1297 DbgLoc = I->getDebugLoc();
1299 MachineBasicBlock::iterator SavedInsertPt = FuncInfo.InsertPt;
1301 if (const auto *Call = dyn_cast<CallInst>(I)) {
1302 const Function *F = Call->getCalledFunction();
1305 // As a special case, don't handle calls to builtin library functions that
1306 // may be translated directly to target instructions.
1307 if (F && !F->hasLocalLinkage() && F->hasName() &&
1308 LibInfo->getLibFunc(F->getName(), Func) &&
1309 LibInfo->hasOptimizedCodeGen(Func))
1312 // Don't handle Intrinsic::trap if a trap funciton is specified.
1313 if (F && F->getIntrinsicID() == Intrinsic::trap &&
1314 !TM.Options.getTrapFunctionName().empty())
1318 // First, try doing target-independent selection.
1319 if (!SkipTargetIndependentISel) {
1320 if (selectOperator(I, I->getOpcode())) {
1321 ++NumFastIselSuccessIndependent;
1322 DbgLoc = DebugLoc();
1325 // Remove dead code. However, ignore call instructions since we've flushed
1326 // the local value map and recomputed the insert point.
1327 if (!isa<CallInst>(I)) {
1328 recomputeInsertPt();
1329 if (SavedInsertPt != FuncInfo.InsertPt)
1330 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1332 SavedInsertPt = FuncInfo.InsertPt;
1334 // Next, try calling the target to attempt to handle the instruction.
1335 if (fastSelectInstruction(I)) {
1336 ++NumFastIselSuccessTarget;
1337 DbgLoc = DebugLoc();
1340 // Remove dead code. However, ignore call instructions since we've flushed
1341 // the local value map and recomputed the insert point.
1342 if (!isa<CallInst>(I)) {
1343 recomputeInsertPt();
1344 if (SavedInsertPt != FuncInfo.InsertPt)
1345 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1348 DbgLoc = DebugLoc();
1349 // Undo phi node updates, because they will be added again by SelectionDAG.
1350 if (isa<TerminatorInst>(I))
1351 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
1355 /// Emit an unconditional branch to the given block, unless it is the immediate
1356 /// (fall-through) successor, and update the CFG.
1357 void FastISel::fastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DbgLoc) {
1358 if (FuncInfo.MBB->getBasicBlock()->size() > 1 &&
1359 FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
1360 // For more accurate line information if this is the only instruction
1361 // in the block then emit it, otherwise we have the unconditional
1362 // fall-through case, which needs no instructions.
1364 // The unconditional branch case.
1365 TII.InsertBranch(*FuncInfo.MBB, MSucc, nullptr,
1366 SmallVector<MachineOperand, 0>(), DbgLoc);
1368 uint32_t BranchWeight = 0;
1370 BranchWeight = FuncInfo.BPI->getEdgeWeight(FuncInfo.MBB->getBasicBlock(),
1371 MSucc->getBasicBlock());
1372 FuncInfo.MBB->addSuccessor(MSucc, BranchWeight);
1375 /// Emit an FNeg operation.
1376 bool FastISel::selectFNeg(const User *I) {
1377 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
1380 bool OpRegIsKill = hasTrivialKill(I);
1382 // If the target has ISD::FNEG, use it.
1383 EVT VT = TLI.getValueType(I->getType());
1384 unsigned ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1385 OpReg, OpRegIsKill);
1387 updateValueMap(I, ResultReg);
1391 // Bitcast the value to integer, twiddle the sign bit with xor,
1392 // and then bitcast it back to floating-point.
1393 if (VT.getSizeInBits() > 64)
1395 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
1396 if (!TLI.isTypeLegal(IntVT))
1399 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1400 ISD::BITCAST, OpReg, OpRegIsKill);
1404 unsigned IntResultReg = fastEmit_ri_(
1405 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true,
1406 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT());
1410 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
1411 IntResultReg, /*IsKill=*/true);
1415 updateValueMap(I, ResultReg);
1419 bool FastISel::selectExtractValue(const User *U) {
1420 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
1424 // Make sure we only try to handle extracts with a legal result. But also
1425 // allow i1 because it's easy.
1426 EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true);
1427 if (!RealVT.isSimple())
1429 MVT VT = RealVT.getSimpleVT();
1430 if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
1433 const Value *Op0 = EVI->getOperand(0);
1434 Type *AggTy = Op0->getType();
1436 // Get the base result register.
1438 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
1439 if (I != FuncInfo.ValueMap.end())
1440 ResultReg = I->second;
1441 else if (isa<Instruction>(Op0))
1442 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1444 return false; // fast-isel can't handle aggregate constants at the moment
1446 // Get the actual result register, which is an offset from the base register.
1447 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
1449 SmallVector<EVT, 4> AggValueVTs;
1450 ComputeValueVTs(TLI, AggTy, AggValueVTs);
1452 for (unsigned i = 0; i < VTIndex; i++)
1453 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1455 updateValueMap(EVI, ResultReg);
1459 bool FastISel::selectOperator(const User *I, unsigned Opcode) {
1461 case Instruction::Add:
1462 return selectBinaryOp(I, ISD::ADD);
1463 case Instruction::FAdd:
1464 return selectBinaryOp(I, ISD::FADD);
1465 case Instruction::Sub:
1466 return selectBinaryOp(I, ISD::SUB);
1467 case Instruction::FSub:
1468 // FNeg is currently represented in LLVM IR as a special case of FSub.
1469 if (BinaryOperator::isFNeg(I))
1470 return selectFNeg(I);
1471 return selectBinaryOp(I, ISD::FSUB);
1472 case Instruction::Mul:
1473 return selectBinaryOp(I, ISD::MUL);
1474 case Instruction::FMul:
1475 return selectBinaryOp(I, ISD::FMUL);
1476 case Instruction::SDiv:
1477 return selectBinaryOp(I, ISD::SDIV);
1478 case Instruction::UDiv:
1479 return selectBinaryOp(I, ISD::UDIV);
1480 case Instruction::FDiv:
1481 return selectBinaryOp(I, ISD::FDIV);
1482 case Instruction::SRem:
1483 return selectBinaryOp(I, ISD::SREM);
1484 case Instruction::URem:
1485 return selectBinaryOp(I, ISD::UREM);
1486 case Instruction::FRem:
1487 return selectBinaryOp(I, ISD::FREM);
1488 case Instruction::Shl:
1489 return selectBinaryOp(I, ISD::SHL);
1490 case Instruction::LShr:
1491 return selectBinaryOp(I, ISD::SRL);
1492 case Instruction::AShr:
1493 return selectBinaryOp(I, ISD::SRA);
1494 case Instruction::And:
1495 return selectBinaryOp(I, ISD::AND);
1496 case Instruction::Or:
1497 return selectBinaryOp(I, ISD::OR);
1498 case Instruction::Xor:
1499 return selectBinaryOp(I, ISD::XOR);
1501 case Instruction::GetElementPtr:
1502 return selectGetElementPtr(I);
1504 case Instruction::Br: {
1505 const BranchInst *BI = cast<BranchInst>(I);
1507 if (BI->isUnconditional()) {
1508 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
1509 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
1510 fastEmitBranch(MSucc, BI->getDebugLoc());
1514 // Conditional branches are not handed yet.
1515 // Halt "fast" selection and bail.
1519 case Instruction::Unreachable:
1520 if (TM.Options.TrapUnreachable)
1521 return fastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
1525 case Instruction::Alloca:
1526 // FunctionLowering has the static-sized case covered.
1527 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
1530 // Dynamic-sized alloca is not handled yet.
1533 case Instruction::Call:
1534 return selectCall(I);
1536 case Instruction::BitCast:
1537 return selectBitCast(I);
1539 case Instruction::FPToSI:
1540 return selectCast(I, ISD::FP_TO_SINT);
1541 case Instruction::ZExt:
1542 return selectCast(I, ISD::ZERO_EXTEND);
1543 case Instruction::SExt:
1544 return selectCast(I, ISD::SIGN_EXTEND);
1545 case Instruction::Trunc:
1546 return selectCast(I, ISD::TRUNCATE);
1547 case Instruction::SIToFP:
1548 return selectCast(I, ISD::SINT_TO_FP);
1550 case Instruction::IntToPtr: // Deliberate fall-through.
1551 case Instruction::PtrToInt: {
1552 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1553 EVT DstVT = TLI.getValueType(I->getType());
1554 if (DstVT.bitsGT(SrcVT))
1555 return selectCast(I, ISD::ZERO_EXTEND);
1556 if (DstVT.bitsLT(SrcVT))
1557 return selectCast(I, ISD::TRUNCATE);
1558 unsigned Reg = getRegForValue(I->getOperand(0));
1561 updateValueMap(I, Reg);
1565 case Instruction::ExtractValue:
1566 return selectExtractValue(I);
1568 case Instruction::PHI:
1569 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1572 // Unhandled instruction. Halt "fast" selection and bail.
1577 FastISel::FastISel(FunctionLoweringInfo &FuncInfo,
1578 const TargetLibraryInfo *LibInfo,
1579 bool SkipTargetIndependentISel)
1580 : FuncInfo(FuncInfo), MF(FuncInfo.MF), MRI(FuncInfo.MF->getRegInfo()),
1581 MFI(*FuncInfo.MF->getFrameInfo()), MCP(*FuncInfo.MF->getConstantPool()),
1582 TM(FuncInfo.MF->getTarget()), DL(*TM.getSubtargetImpl()->getDataLayout()),
1583 TII(*TM.getSubtargetImpl()->getInstrInfo()),
1584 TLI(*TM.getSubtargetImpl()->getTargetLowering()),
1585 TRI(*TM.getSubtargetImpl()->getRegisterInfo()), LibInfo(LibInfo),
1586 SkipTargetIndependentISel(SkipTargetIndependentISel) {}
1588 FastISel::~FastISel() {}
1590 bool FastISel::fastLowerArguments() { return false; }
1592 bool FastISel::fastLowerCall(CallLoweringInfo & /*CLI*/) { return false; }
1594 bool FastISel::fastLowerIntrinsicCall(const IntrinsicInst * /*II*/) {
1598 unsigned FastISel::fastEmit_(MVT, MVT, unsigned) { return 0; }
1600 unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, unsigned /*Op0*/,
1601 bool /*Op0IsKill*/) {
1605 unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
1606 bool /*Op0IsKill*/, unsigned /*Op1*/,
1607 bool /*Op1IsKill*/) {
1611 unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1615 unsigned FastISel::fastEmit_f(MVT, MVT, unsigned,
1616 const ConstantFP * /*FPImm*/) {
1620 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
1621 bool /*Op0IsKill*/, uint64_t /*Imm*/) {
1625 unsigned FastISel::fastEmit_rf(MVT, MVT, unsigned, unsigned /*Op0*/,
1627 const ConstantFP * /*FPImm*/) {
1631 unsigned FastISel::fastEmit_rri(MVT, MVT, unsigned, unsigned /*Op0*/,
1632 bool /*Op0IsKill*/, unsigned /*Op1*/,
1633 bool /*Op1IsKill*/, uint64_t /*Imm*/) {
1637 /// This method is a wrapper of fastEmit_ri. It first tries to emit an
1638 /// instruction with an immediate operand using fastEmit_ri.
1639 /// If that fails, it materializes the immediate into a register and try
1640 /// fastEmit_rr instead.
1641 unsigned FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
1642 bool Op0IsKill, uint64_t Imm, MVT ImmType) {
1643 // If this is a multiply by a power of two, emit this as a shift left.
1644 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1647 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1648 // div x, 8 -> srl x, 3
1653 // Horrible hack (to be removed), check to make sure shift amounts are
1655 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1656 Imm >= VT.getSizeInBits())
1659 // First check if immediate type is legal. If not, we can't use the ri form.
1660 unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1663 unsigned MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1665 // This is a bit ugly/slow, but failing here means falling out of
1666 // fast-isel, which would be very slow.
1668 IntegerType::get(FuncInfo.Fn->getContext(), VT.getSizeInBits());
1669 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1673 return fastEmit_rr(VT, VT, Opcode, Op0, Op0IsKill, MaterialReg,
1677 unsigned FastISel::createResultReg(const TargetRegisterClass *RC) {
1678 return MRI.createVirtualRegister(RC);
1681 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
1683 if (TargetRegisterInfo::isVirtualRegister(Op)) {
1684 const TargetRegisterClass *RegClass =
1685 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
1686 if (!MRI.constrainRegClass(Op, RegClass)) {
1687 // If it's not legal to COPY between the register classes, something
1688 // has gone very wrong before we got here.
1689 unsigned NewOp = createResultReg(RegClass);
1690 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1691 TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
1698 unsigned FastISel::fastEmitInst_(unsigned MachineInstOpcode,
1699 const TargetRegisterClass *RC) {
1700 unsigned ResultReg = createResultReg(RC);
1701 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1703 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
1707 unsigned FastISel::fastEmitInst_r(unsigned MachineInstOpcode,
1708 const TargetRegisterClass *RC, unsigned Op0,
1710 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1712 unsigned ResultReg = createResultReg(RC);
1713 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1715 if (II.getNumDefs() >= 1)
1716 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1717 .addReg(Op0, getKillRegState(Op0IsKill));
1719 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1720 .addReg(Op0, getKillRegState(Op0IsKill));
1721 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1722 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1728 unsigned FastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1729 const TargetRegisterClass *RC, unsigned Op0,
1730 bool Op0IsKill, unsigned Op1,
1732 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1734 unsigned ResultReg = createResultReg(RC);
1735 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1736 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1738 if (II.getNumDefs() >= 1)
1739 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1740 .addReg(Op0, getKillRegState(Op0IsKill))
1741 .addReg(Op1, getKillRegState(Op1IsKill));
1743 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1744 .addReg(Op0, getKillRegState(Op0IsKill))
1745 .addReg(Op1, getKillRegState(Op1IsKill));
1746 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1747 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1752 unsigned FastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
1753 const TargetRegisterClass *RC, unsigned Op0,
1754 bool Op0IsKill, unsigned Op1,
1755 bool Op1IsKill, unsigned Op2,
1757 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1759 unsigned ResultReg = createResultReg(RC);
1760 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1761 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1762 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
1764 if (II.getNumDefs() >= 1)
1765 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1766 .addReg(Op0, getKillRegState(Op0IsKill))
1767 .addReg(Op1, getKillRegState(Op1IsKill))
1768 .addReg(Op2, getKillRegState(Op2IsKill));
1770 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1771 .addReg(Op0, getKillRegState(Op0IsKill))
1772 .addReg(Op1, getKillRegState(Op1IsKill))
1773 .addReg(Op2, getKillRegState(Op2IsKill));
1774 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1775 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1780 unsigned FastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
1781 const TargetRegisterClass *RC, unsigned Op0,
1782 bool Op0IsKill, uint64_t Imm) {
1783 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1785 unsigned ResultReg = createResultReg(RC);
1786 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1788 if (II.getNumDefs() >= 1)
1789 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1790 .addReg(Op0, getKillRegState(Op0IsKill))
1793 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1794 .addReg(Op0, getKillRegState(Op0IsKill))
1796 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1797 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1802 unsigned FastISel::fastEmitInst_rii(unsigned MachineInstOpcode,
1803 const TargetRegisterClass *RC, unsigned Op0,
1804 bool Op0IsKill, uint64_t Imm1,
1806 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1808 unsigned ResultReg = createResultReg(RC);
1809 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1811 if (II.getNumDefs() >= 1)
1812 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1813 .addReg(Op0, getKillRegState(Op0IsKill))
1817 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1818 .addReg(Op0, getKillRegState(Op0IsKill))
1821 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1822 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1827 unsigned FastISel::fastEmitInst_rf(unsigned MachineInstOpcode,
1828 const TargetRegisterClass *RC, unsigned Op0,
1829 bool Op0IsKill, const ConstantFP *FPImm) {
1830 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1832 unsigned ResultReg = createResultReg(RC);
1833 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1835 if (II.getNumDefs() >= 1)
1836 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1837 .addReg(Op0, getKillRegState(Op0IsKill))
1840 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1841 .addReg(Op0, getKillRegState(Op0IsKill))
1843 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1844 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1849 unsigned FastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
1850 const TargetRegisterClass *RC, unsigned Op0,
1851 bool Op0IsKill, unsigned Op1,
1852 bool Op1IsKill, uint64_t Imm) {
1853 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1855 unsigned ResultReg = createResultReg(RC);
1856 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1857 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1859 if (II.getNumDefs() >= 1)
1860 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1861 .addReg(Op0, getKillRegState(Op0IsKill))
1862 .addReg(Op1, getKillRegState(Op1IsKill))
1865 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1866 .addReg(Op0, getKillRegState(Op0IsKill))
1867 .addReg(Op1, getKillRegState(Op1IsKill))
1869 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1870 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1875 unsigned FastISel::fastEmitInst_rrii(unsigned MachineInstOpcode,
1876 const TargetRegisterClass *RC,
1877 unsigned Op0, bool Op0IsKill, unsigned Op1,
1878 bool Op1IsKill, uint64_t Imm1,
1880 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1882 unsigned ResultReg = createResultReg(RC);
1883 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1884 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1886 if (II.getNumDefs() >= 1)
1887 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1888 .addReg(Op0, getKillRegState(Op0IsKill))
1889 .addReg(Op1, getKillRegState(Op1IsKill))
1893 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1894 .addReg(Op0, getKillRegState(Op0IsKill))
1895 .addReg(Op1, getKillRegState(Op1IsKill))
1898 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1899 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1904 unsigned FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
1905 const TargetRegisterClass *RC, uint64_t Imm) {
1906 unsigned ResultReg = createResultReg(RC);
1907 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1909 if (II.getNumDefs() >= 1)
1910 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1913 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm);
1914 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1915 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1920 unsigned FastISel::fastEmitInst_ii(unsigned MachineInstOpcode,
1921 const TargetRegisterClass *RC, uint64_t Imm1,
1923 unsigned ResultReg = createResultReg(RC);
1924 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1926 if (II.getNumDefs() >= 1)
1927 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1931 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm1)
1933 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1934 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1939 unsigned FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
1940 bool Op0IsKill, uint32_t Idx) {
1941 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1942 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1943 "Cannot yet extract from physregs");
1944 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
1945 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
1946 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
1947 ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);
1951 /// Emit MachineInstrs to compute the value of Op with all but the least
1952 /// significant bit set to zero.
1953 unsigned FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1954 return fastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
1957 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
1958 /// Emit code to ensure constants are copied into registers when needed.
1959 /// Remember the virtual registers that need to be added to the Machine PHI
1960 /// nodes as input. We cannot just directly add them, because expansion
1961 /// might result in multiple MBB's for one BB. As such, the start of the
1962 /// BB might correspond to a different MBB than the end.
1963 bool FastISel::handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
1964 const TerminatorInst *TI = LLVMBB->getTerminator();
1966 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
1967 FuncInfo.OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
1969 // Check successor nodes' PHI nodes that expect a constant to be available
1971 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
1972 const BasicBlock *SuccBB = TI->getSuccessor(succ);
1973 if (!isa<PHINode>(SuccBB->begin()))
1975 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
1977 // If this terminator has multiple identical successors (common for
1978 // switches), only handle each succ once.
1979 if (!SuccsHandled.insert(SuccMBB))
1982 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
1984 // At this point we know that there is a 1-1 correspondence between LLVM PHI
1985 // nodes and Machine PHI nodes, but the incoming operands have not been
1987 for (BasicBlock::const_iterator I = SuccBB->begin();
1988 const auto *PN = dyn_cast<PHINode>(I); ++I) {
1990 // Ignore dead phi's.
1991 if (PN->use_empty())
1994 // Only handle legal types. Two interesting things to note here. First,
1995 // by bailing out early, we may leave behind some dead instructions,
1996 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
1997 // own moves. Second, this check is necessary because FastISel doesn't
1998 // use CreateRegs to create registers, so it always creates
1999 // exactly one register for each non-void instruction.
2000 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
2001 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
2002 // Handle integer promotions, though, because they're common and easy.
2003 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
2004 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT);
2006 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
2011 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
2013 // Set the DebugLoc for the copy. Prefer the location of the operand
2014 // if there is one; use the location of the PHI otherwise.
2015 DbgLoc = PN->getDebugLoc();
2016 if (const auto *Inst = dyn_cast<Instruction>(PHIOp))
2017 DbgLoc = Inst->getDebugLoc();
2019 unsigned Reg = getRegForValue(PHIOp);
2021 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
2024 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
2025 DbgLoc = DebugLoc();
2032 bool FastISel::tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst) {
2033 assert(LI->hasOneUse() &&
2034 "tryToFoldLoad expected a LoadInst with a single use");
2035 // We know that the load has a single use, but don't know what it is. If it
2036 // isn't one of the folded instructions, then we can't succeed here. Handle
2037 // this by scanning the single-use users of the load until we get to FoldInst.
2038 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
2040 const Instruction *TheUser = LI->user_back();
2041 while (TheUser != FoldInst && // Scan up until we find FoldInst.
2042 // Stay in the right block.
2043 TheUser->getParent() == FoldInst->getParent() &&
2044 --MaxUsers) { // Don't scan too far.
2045 // If there are multiple or no uses of this instruction, then bail out.
2046 if (!TheUser->hasOneUse())
2049 TheUser = TheUser->user_back();
2052 // If we didn't find the fold instruction, then we failed to collapse the
2054 if (TheUser != FoldInst)
2057 // Don't try to fold volatile loads. Target has to deal with alignment
2059 if (LI->isVolatile())
2062 // Figure out which vreg this is going into. If there is no assigned vreg yet
2063 // then there actually was no reference to it. Perhaps the load is referenced
2064 // by a dead instruction.
2065 unsigned LoadReg = getRegForValue(LI);
2069 // We can't fold if this vreg has no uses or more than one use. Multiple uses
2070 // may mean that the instruction got lowered to multiple MIs, or the use of
2071 // the loaded value ended up being multiple operands of the result.
2072 if (!MRI.hasOneUse(LoadReg))
2075 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg);
2076 MachineInstr *User = RI->getParent();
2078 // Set the insertion point properly. Folding the load can cause generation of
2079 // other random instructions (like sign extends) for addressing modes; make
2080 // sure they get inserted in a logical place before the new instruction.
2081 FuncInfo.InsertPt = User;
2082 FuncInfo.MBB = User->getParent();
2084 // Ask the target to try folding the load.
2085 return tryToFoldLoadIntoMI(User, RI.getOperandNo(), LI);
2088 bool FastISel::canFoldAddIntoGEP(const User *GEP, const Value *Add) {
2090 if (!isa<AddOperator>(Add))
2092 // Type size needs to match.
2093 if (DL.getTypeSizeInBits(GEP->getType()) !=
2094 DL.getTypeSizeInBits(Add->getType()))
2096 // Must be in the same basic block.
2097 if (isa<Instruction>(Add) &&
2098 FuncInfo.MBBMap[cast<Instruction>(Add)->getParent()] != FuncInfo.MBB)
2100 // Must have a constant operand.
2101 return isa<ConstantInt>(cast<AddOperator>(Add)->getOperand(1));
2105 FastISel::createMachineMemOperandFor(const Instruction *I) const {
2112 if (const auto *LI = dyn_cast<LoadInst>(I)) {
2113 Alignment = LI->getAlignment();
2114 IsVolatile = LI->isVolatile();
2115 Flags = MachineMemOperand::MOLoad;
2116 Ptr = LI->getPointerOperand();
2117 ValTy = LI->getType();
2118 } else if (const auto *SI = dyn_cast<StoreInst>(I)) {
2119 Alignment = SI->getAlignment();
2120 IsVolatile = SI->isVolatile();
2121 Flags = MachineMemOperand::MOStore;
2122 Ptr = SI->getPointerOperand();
2123 ValTy = SI->getValueOperand()->getType();
2127 bool IsNonTemporal = I->getMetadata("nontemporal") != nullptr;
2128 bool IsInvariant = I->getMetadata("invariant.load") != nullptr;
2129 const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range);
2132 I->getAAMetadata(AAInfo);
2134 if (Alignment == 0) // Ensure that codegen never sees alignment 0.
2135 Alignment = DL.getABITypeAlignment(ValTy);
2138 TM.getSubtargetImpl()->getDataLayout()->getTypeStoreSize(ValTy);
2141 Flags |= MachineMemOperand::MOVolatile;
2143 Flags |= MachineMemOperand::MONonTemporal;
2145 Flags |= MachineMemOperand::MOInvariant;
2147 return FuncInfo.MF->getMachineMemOperand(MachinePointerInfo(Ptr), Flags, Size,
2148 Alignment, AAInfo, Ranges);