1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/DwarfWriter.h"
51 #include "llvm/Analysis/DebugInfo.h"
52 #include "llvm/Target/TargetData.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "FunctionLoweringInfo.h"
59 unsigned FastISel::getRegForValue(Value *V) {
60 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
61 // Don't handle non-simple values in FastISel.
62 if (!RealVT.isSimple())
65 // Ignore illegal types. We must do this before looking up the value
66 // in ValueMap because Arguments are given virtual registers regardless
67 // of whether FastISel can handle them.
68 MVT VT = RealVT.getSimpleVT();
69 if (!TLI.isTypeLegal(VT)) {
70 // Promote MVT::i1 to a legal type though, because it's common and easy.
72 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
77 // Look up the value to see if we already have a register for it. We
78 // cache values defined by Instructions across blocks, and other values
79 // only locally. This is because Instructions already have the SSA
80 // def-dominates-use requirement enforced.
81 if (ValueMap.count(V))
83 unsigned Reg = LocalValueMap[V];
87 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
88 if (CI->getValue().getActiveBits() <= 64)
89 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
90 } else if (isa<AllocaInst>(V)) {
91 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
92 } else if (isa<ConstantPointerNull>(V)) {
93 // Translate this as an integer zero so that it can be
94 // local-CSE'd with actual integer zeros.
96 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
97 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
98 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
101 const APFloat &Flt = CF->getValueAPF();
102 EVT IntVT = TLI.getPointerTy();
105 uint32_t IntBitWidth = IntVT.getSizeInBits();
107 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
108 APFloat::rmTowardZero, &isExact);
110 APInt IntVal(IntBitWidth, 2, x);
112 unsigned IntegerReg =
113 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
115 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
118 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
119 if (!SelectOperator(CE, CE->getOpcode())) return 0;
120 Reg = LocalValueMap[CE];
121 } else if (isa<UndefValue>(V)) {
122 Reg = createResultReg(TLI.getRegClassFor(VT));
123 BuildMI(MBB, DL, TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
126 // If target-independent code couldn't handle the value, give target-specific
128 if (!Reg && isa<Constant>(V))
129 Reg = TargetMaterializeConstant(cast<Constant>(V));
131 // Don't cache constant materializations in the general ValueMap.
132 // To do so would require tracking what uses they dominate.
134 LocalValueMap[V] = Reg;
138 unsigned FastISel::lookUpRegForValue(Value *V) {
139 // Look up the value to see if we already have a register for it. We
140 // cache values defined by Instructions across blocks, and other values
141 // only locally. This is because Instructions already have the SSA
142 // def-dominatess-use requirement enforced.
143 if (ValueMap.count(V))
145 return LocalValueMap[V];
148 /// UpdateValueMap - Update the value map to include the new mapping for this
149 /// instruction, or insert an extra copy to get the result in a previous
150 /// determined register.
151 /// NOTE: This is only necessary because we might select a block that uses
152 /// a value before we select the block that defines the value. It might be
153 /// possible to fix this by selecting blocks in reverse postorder.
154 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
155 if (!isa<Instruction>(I)) {
156 LocalValueMap[I] = Reg;
160 unsigned &AssignedReg = ValueMap[I];
161 if (AssignedReg == 0)
163 else if (Reg != AssignedReg) {
164 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
165 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
166 Reg, RegClass, RegClass);
171 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
172 unsigned IdxN = getRegForValue(Idx);
174 // Unhandled operand. Halt "fast" selection and bail.
177 // If the index is smaller or larger than intptr_t, truncate or extend it.
178 MVT PtrVT = TLI.getPointerTy();
179 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
180 if (IdxVT.bitsLT(PtrVT))
181 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
182 else if (IdxVT.bitsGT(PtrVT))
183 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
187 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
188 /// which has an opcode which directly corresponds to the given ISD opcode.
190 bool FastISel::SelectBinaryOp(User *I, unsigned ISDOpcode) {
191 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
192 if (VT == MVT::Other || !VT.isSimple())
193 // Unhandled type. Halt "fast" selection and bail.
196 // We only handle legal types. For example, on x86-32 the instruction
197 // selector contains all of the 64-bit instructions from x86-64,
198 // under the assumption that i64 won't be used if the target doesn't
200 if (!TLI.isTypeLegal(VT)) {
201 // MVT::i1 is special. Allow AND, OR, or XOR because they
202 // don't require additional zeroing, which makes them easy.
204 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
205 ISDOpcode == ISD::XOR))
206 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
211 unsigned Op0 = getRegForValue(I->getOperand(0));
213 // Unhandled operand. Halt "fast" selection and bail.
216 // Check if the second operand is a constant and handle it appropriately.
217 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
218 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
219 ISDOpcode, Op0, CI->getZExtValue());
220 if (ResultReg != 0) {
221 // We successfully emitted code for the given LLVM Instruction.
222 UpdateValueMap(I, ResultReg);
227 // Check if the second operand is a constant float.
228 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
229 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
231 if (ResultReg != 0) {
232 // We successfully emitted code for the given LLVM Instruction.
233 UpdateValueMap(I, ResultReg);
238 unsigned Op1 = getRegForValue(I->getOperand(1));
240 // Unhandled operand. Halt "fast" selection and bail.
243 // Now we have both operands in registers. Emit the instruction.
244 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
245 ISDOpcode, Op0, Op1);
247 // Target-specific code wasn't able to find a machine opcode for
248 // the given ISD opcode and type. Halt "fast" selection and bail.
251 // We successfully emitted code for the given LLVM Instruction.
252 UpdateValueMap(I, ResultReg);
256 bool FastISel::SelectGetElementPtr(User *I) {
257 unsigned N = getRegForValue(I->getOperand(0));
259 // Unhandled operand. Halt "fast" selection and bail.
262 const Type *Ty = I->getOperand(0)->getType();
263 MVT VT = TLI.getPointerTy();
264 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
267 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
268 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
271 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
272 // FIXME: This can be optimized by combining the add with a
274 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
276 // Unhandled operand. Halt "fast" selection and bail.
279 Ty = StTy->getElementType(Field);
281 Ty = cast<SequentialType>(Ty)->getElementType();
283 // If this is a constant subscript, handle it quickly.
284 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
285 if (CI->getZExtValue() == 0) continue;
287 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
288 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
290 // Unhandled operand. Halt "fast" selection and bail.
295 // N = N + Idx * ElementSize;
296 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
297 unsigned IdxN = getRegForGEPIndex(Idx);
299 // Unhandled operand. Halt "fast" selection and bail.
302 if (ElementSize != 1) {
303 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
305 // Unhandled operand. Halt "fast" selection and bail.
308 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
310 // Unhandled operand. Halt "fast" selection and bail.
315 // We successfully emitted code for the given LLVM Instruction.
316 UpdateValueMap(I, N);
320 bool FastISel::SelectCall(User *I) {
321 Function *F = cast<CallInst>(I)->getCalledFunction();
322 if (!F) return false;
324 unsigned IID = F->getIntrinsicID();
327 case Intrinsic::dbg_declare: {
328 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
329 if (!DIDescriptor::ValidDebugInfo(DI->getVariable(), CodeGenOpt::None)||!DW
330 || !DW->ShouldEmitDwarfDebug())
333 Value *Address = DI->getAddress();
336 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
337 // Don't handle byval struct arguments or VLAs, for example.
339 DenseMap<const AllocaInst*, int>::iterator SI =
340 StaticAllocaMap.find(AI);
341 if (SI == StaticAllocaMap.end()) break; // VLAs.
344 if (MDNode *Dbg = DI->getMetadata("dbg"))
345 MMI->setVariableDbgInfo(DI->getVariable(), FI, Dbg);
347 // Building the map above is target independent. Generating DBG_VALUE
348 // inline is target dependent; do this now.
349 (void)TargetSelectInstruction(cast<Instruction>(I));
352 case Intrinsic::dbg_value: {
353 // This requires target support, but right now X86 is the only Fast target.
354 DbgValueInst *DI = cast<DbgValueInst>(I);
355 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
356 Value *V = DI->getValue();
358 // Currently the optimizer can produce this; insert an undef to
359 // help debugging. Probably the optimizer should not do this.
360 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
361 addMetadata(DI->getVariable());
362 } else if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
363 BuildMI(MBB, DL, II).addImm(CI->getZExtValue()).addImm(DI->getOffset()).
364 addMetadata(DI->getVariable());
365 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
366 BuildMI(MBB, DL, II).addFPImm(CF).addImm(DI->getOffset()).
367 addMetadata(DI->getVariable());
368 } else if (unsigned Reg = lookUpRegForValue(V)) {
369 BuildMI(MBB, DL, II).addReg(Reg, RegState::Debug).addImm(DI->getOffset()).
370 addMetadata(DI->getVariable());
372 // We can't yet handle anything else here because it would require
373 // generating code, thus altering codegen because of debug info.
374 // Insert an undef so we can see what we dropped.
375 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
376 addMetadata(DI->getVariable());
380 case Intrinsic::eh_exception: {
381 EVT VT = TLI.getValueType(I->getType());
382 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
384 case TargetLowering::Expand: {
385 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
386 unsigned Reg = TLI.getExceptionAddressRegister();
387 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
388 unsigned ResultReg = createResultReg(RC);
389 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
391 assert(InsertedCopy && "Can't copy address registers!");
392 InsertedCopy = InsertedCopy;
393 UpdateValueMap(I, ResultReg);
399 case Intrinsic::eh_selector: {
400 EVT VT = TLI.getValueType(I->getType());
401 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
403 case TargetLowering::Expand: {
405 if (MBB->isLandingPad())
406 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
409 CatchInfoLost.insert(cast<CallInst>(I));
411 // FIXME: Mark exception selector register as live in. Hack for PR1508.
412 unsigned Reg = TLI.getExceptionSelectorRegister();
413 if (Reg) MBB->addLiveIn(Reg);
416 unsigned Reg = TLI.getExceptionSelectorRegister();
417 EVT SrcVT = TLI.getPointerTy();
418 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
419 unsigned ResultReg = createResultReg(RC);
420 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
422 assert(InsertedCopy && "Can't copy address registers!");
423 InsertedCopy = InsertedCopy;
425 // Cast the register to the type of the selector.
426 if (SrcVT.bitsGT(MVT::i32))
427 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
429 else if (SrcVT.bitsLT(MVT::i32))
430 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
431 ISD::SIGN_EXTEND, ResultReg);
433 // Unhandled operand. Halt "fast" selection and bail.
436 UpdateValueMap(I, ResultReg);
439 getRegForValue(Constant::getNullValue(I->getType()));
440 UpdateValueMap(I, ResultReg);
451 bool FastISel::SelectCast(User *I, unsigned Opcode) {
452 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
453 EVT DstVT = TLI.getValueType(I->getType());
455 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
456 DstVT == MVT::Other || !DstVT.isSimple())
457 // Unhandled type. Halt "fast" selection and bail.
460 // Check if the destination type is legal. Or as a special case,
461 // it may be i1 if we're doing a truncate because that's
462 // easy and somewhat common.
463 if (!TLI.isTypeLegal(DstVT))
464 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
465 // Unhandled type. Halt "fast" selection and bail.
468 // Check if the source operand is legal. Or as a special case,
469 // it may be i1 if we're doing zero-extension because that's
470 // easy and somewhat common.
471 if (!TLI.isTypeLegal(SrcVT))
472 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
473 // Unhandled type. Halt "fast" selection and bail.
476 unsigned InputReg = getRegForValue(I->getOperand(0));
478 // Unhandled operand. Halt "fast" selection and bail.
481 // If the operand is i1, arrange for the high bits in the register to be zero.
482 if (SrcVT == MVT::i1) {
483 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
484 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
488 // If the result is i1, truncate to the target's type for i1 first.
489 if (DstVT == MVT::i1)
490 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
492 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
499 UpdateValueMap(I, ResultReg);
503 bool FastISel::SelectBitCast(User *I) {
504 // If the bitcast doesn't change the type, just use the operand value.
505 if (I->getType() == I->getOperand(0)->getType()) {
506 unsigned Reg = getRegForValue(I->getOperand(0));
509 UpdateValueMap(I, Reg);
513 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
514 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
515 EVT DstVT = TLI.getValueType(I->getType());
517 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
518 DstVT == MVT::Other || !DstVT.isSimple() ||
519 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
520 // Unhandled type. Halt "fast" selection and bail.
523 unsigned Op0 = getRegForValue(I->getOperand(0));
525 // Unhandled operand. Halt "fast" selection and bail.
528 // First, try to perform the bitcast by inserting a reg-reg copy.
529 unsigned ResultReg = 0;
530 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
531 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
532 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
533 ResultReg = createResultReg(DstClass);
535 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
536 Op0, DstClass, SrcClass);
541 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
543 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
544 ISD::BIT_CONVERT, Op0);
549 UpdateValueMap(I, ResultReg);
554 FastISel::SelectInstruction(Instruction *I) {
555 // First, try doing target-independent selection.
556 if (SelectOperator(I, I->getOpcode()))
559 // Next, try calling the target to attempt to handle the instruction.
560 if (TargetSelectInstruction(I))
566 /// FastEmitBranch - Emit an unconditional branch to the given block,
567 /// unless it is the immediate (fall-through) successor, and update
570 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
571 if (MBB->isLayoutSuccessor(MSucc)) {
572 // The unconditional fall-through case, which needs no instructions.
574 // The unconditional branch case.
575 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
577 MBB->addSuccessor(MSucc);
580 /// SelectFNeg - Emit an FNeg operation.
583 FastISel::SelectFNeg(User *I) {
584 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
585 if (OpReg == 0) return false;
587 // If the target has ISD::FNEG, use it.
588 EVT VT = TLI.getValueType(I->getType());
589 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
591 if (ResultReg != 0) {
592 UpdateValueMap(I, ResultReg);
596 // Bitcast the value to integer, twiddle the sign bit with xor,
597 // and then bitcast it back to floating-point.
598 if (VT.getSizeInBits() > 64) return false;
599 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
600 if (!TLI.isTypeLegal(IntVT))
603 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
604 ISD::BIT_CONVERT, OpReg);
608 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
609 UINT64_C(1) << (VT.getSizeInBits()-1),
610 IntVT.getSimpleVT());
611 if (IntResultReg == 0)
614 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
615 ISD::BIT_CONVERT, IntResultReg);
619 UpdateValueMap(I, ResultReg);
624 FastISel::SelectOperator(User *I, unsigned Opcode) {
626 case Instruction::Add:
627 return SelectBinaryOp(I, ISD::ADD);
628 case Instruction::FAdd:
629 return SelectBinaryOp(I, ISD::FADD);
630 case Instruction::Sub:
631 return SelectBinaryOp(I, ISD::SUB);
632 case Instruction::FSub:
633 // FNeg is currently represented in LLVM IR as a special case of FSub.
634 if (BinaryOperator::isFNeg(I))
635 return SelectFNeg(I);
636 return SelectBinaryOp(I, ISD::FSUB);
637 case Instruction::Mul:
638 return SelectBinaryOp(I, ISD::MUL);
639 case Instruction::FMul:
640 return SelectBinaryOp(I, ISD::FMUL);
641 case Instruction::SDiv:
642 return SelectBinaryOp(I, ISD::SDIV);
643 case Instruction::UDiv:
644 return SelectBinaryOp(I, ISD::UDIV);
645 case Instruction::FDiv:
646 return SelectBinaryOp(I, ISD::FDIV);
647 case Instruction::SRem:
648 return SelectBinaryOp(I, ISD::SREM);
649 case Instruction::URem:
650 return SelectBinaryOp(I, ISD::UREM);
651 case Instruction::FRem:
652 return SelectBinaryOp(I, ISD::FREM);
653 case Instruction::Shl:
654 return SelectBinaryOp(I, ISD::SHL);
655 case Instruction::LShr:
656 return SelectBinaryOp(I, ISD::SRL);
657 case Instruction::AShr:
658 return SelectBinaryOp(I, ISD::SRA);
659 case Instruction::And:
660 return SelectBinaryOp(I, ISD::AND);
661 case Instruction::Or:
662 return SelectBinaryOp(I, ISD::OR);
663 case Instruction::Xor:
664 return SelectBinaryOp(I, ISD::XOR);
666 case Instruction::GetElementPtr:
667 return SelectGetElementPtr(I);
669 case Instruction::Br: {
670 BranchInst *BI = cast<BranchInst>(I);
672 if (BI->isUnconditional()) {
673 BasicBlock *LLVMSucc = BI->getSuccessor(0);
674 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
675 FastEmitBranch(MSucc);
679 // Conditional branches are not handed yet.
680 // Halt "fast" selection and bail.
684 case Instruction::Unreachable:
688 case Instruction::PHI:
689 // PHI nodes are already emitted.
692 case Instruction::Alloca:
693 // FunctionLowering has the static-sized case covered.
694 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
697 // Dynamic-sized alloca is not handled yet.
700 case Instruction::Call:
701 return SelectCall(I);
703 case Instruction::BitCast:
704 return SelectBitCast(I);
706 case Instruction::FPToSI:
707 return SelectCast(I, ISD::FP_TO_SINT);
708 case Instruction::ZExt:
709 return SelectCast(I, ISD::ZERO_EXTEND);
710 case Instruction::SExt:
711 return SelectCast(I, ISD::SIGN_EXTEND);
712 case Instruction::Trunc:
713 return SelectCast(I, ISD::TRUNCATE);
714 case Instruction::SIToFP:
715 return SelectCast(I, ISD::SINT_TO_FP);
717 case Instruction::IntToPtr: // Deliberate fall-through.
718 case Instruction::PtrToInt: {
719 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
720 EVT DstVT = TLI.getValueType(I->getType());
721 if (DstVT.bitsGT(SrcVT))
722 return SelectCast(I, ISD::ZERO_EXTEND);
723 if (DstVT.bitsLT(SrcVT))
724 return SelectCast(I, ISD::TRUNCATE);
725 unsigned Reg = getRegForValue(I->getOperand(0));
726 if (Reg == 0) return false;
727 UpdateValueMap(I, Reg);
732 // Unhandled instruction. Halt "fast" selection and bail.
737 FastISel::FastISel(MachineFunction &mf,
738 MachineModuleInfo *mmi,
740 DenseMap<const Value *, unsigned> &vm,
741 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
742 DenseMap<const AllocaInst *, int> &am
744 , SmallSet<Instruction*, 8> &cil
757 MRI(MF.getRegInfo()),
758 MFI(*MF.getFrameInfo()),
759 MCP(*MF.getConstantPool()),
761 TD(*TM.getTargetData()),
762 TII(*TM.getInstrInfo()),
763 TLI(*TM.getTargetLowering()) {
766 FastISel::~FastISel() {}
768 unsigned FastISel::FastEmit_(MVT, MVT,
773 unsigned FastISel::FastEmit_r(MVT, MVT,
774 unsigned, unsigned /*Op0*/) {
778 unsigned FastISel::FastEmit_rr(MVT, MVT,
779 unsigned, unsigned /*Op0*/,
784 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
788 unsigned FastISel::FastEmit_f(MVT, MVT,
789 unsigned, ConstantFP * /*FPImm*/) {
793 unsigned FastISel::FastEmit_ri(MVT, MVT,
794 unsigned, unsigned /*Op0*/,
799 unsigned FastISel::FastEmit_rf(MVT, MVT,
800 unsigned, unsigned /*Op0*/,
801 ConstantFP * /*FPImm*/) {
805 unsigned FastISel::FastEmit_rri(MVT, MVT,
807 unsigned /*Op0*/, unsigned /*Op1*/,
812 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
813 /// to emit an instruction with an immediate operand using FastEmit_ri.
814 /// If that fails, it materializes the immediate into a register and try
815 /// FastEmit_rr instead.
816 unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode,
817 unsigned Op0, uint64_t Imm,
819 // First check if immediate type is legal. If not, we can't use the ri form.
820 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
823 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
824 if (MaterialReg == 0)
826 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
829 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
830 /// to emit an instruction with a floating-point immediate operand using
831 /// FastEmit_rf. If that fails, it materializes the immediate into a register
832 /// and try FastEmit_rr instead.
833 unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode,
834 unsigned Op0, ConstantFP *FPImm,
836 // First check if immediate type is legal. If not, we can't use the rf form.
837 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
841 // Materialize the constant in a register.
842 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
843 if (MaterialReg == 0) {
844 // If the target doesn't have a way to directly enter a floating-point
845 // value into a register, use an alternate approach.
846 // TODO: The current approach only supports floating-point constants
847 // that can be constructed by conversion from integer values. This should
848 // be replaced by code that creates a load from a constant-pool entry,
849 // which will require some target-specific work.
850 const APFloat &Flt = FPImm->getValueAPF();
851 EVT IntVT = TLI.getPointerTy();
854 uint32_t IntBitWidth = IntVT.getSizeInBits();
856 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
857 APFloat::rmTowardZero, &isExact);
860 APInt IntVal(IntBitWidth, 2, x);
862 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
863 ISD::Constant, IntVal.getZExtValue());
866 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
867 ISD::SINT_TO_FP, IntegerReg);
868 if (MaterialReg == 0)
871 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
874 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
875 return MRI.createVirtualRegister(RC);
878 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
879 const TargetRegisterClass* RC) {
880 unsigned ResultReg = createResultReg(RC);
881 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
883 BuildMI(MBB, DL, II, ResultReg);
887 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
888 const TargetRegisterClass *RC,
890 unsigned ResultReg = createResultReg(RC);
891 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
893 if (II.getNumDefs() >= 1)
894 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
896 BuildMI(MBB, DL, II).addReg(Op0);
897 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
898 II.ImplicitDefs[0], RC, RC);
906 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
907 const TargetRegisterClass *RC,
908 unsigned Op0, unsigned Op1) {
909 unsigned ResultReg = createResultReg(RC);
910 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
912 if (II.getNumDefs() >= 1)
913 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
915 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
916 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
917 II.ImplicitDefs[0], RC, RC);
924 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
925 const TargetRegisterClass *RC,
926 unsigned Op0, uint64_t Imm) {
927 unsigned ResultReg = createResultReg(RC);
928 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
930 if (II.getNumDefs() >= 1)
931 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
933 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
934 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
935 II.ImplicitDefs[0], RC, RC);
942 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
943 const TargetRegisterClass *RC,
944 unsigned Op0, ConstantFP *FPImm) {
945 unsigned ResultReg = createResultReg(RC);
946 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
948 if (II.getNumDefs() >= 1)
949 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
951 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
952 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
953 II.ImplicitDefs[0], RC, RC);
960 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
961 const TargetRegisterClass *RC,
962 unsigned Op0, unsigned Op1, uint64_t Imm) {
963 unsigned ResultReg = createResultReg(RC);
964 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
966 if (II.getNumDefs() >= 1)
967 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
969 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
970 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
971 II.ImplicitDefs[0], RC, RC);
978 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
979 const TargetRegisterClass *RC,
981 unsigned ResultReg = createResultReg(RC);
982 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
984 if (II.getNumDefs() >= 1)
985 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
987 BuildMI(MBB, DL, II).addImm(Imm);
988 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
989 II.ImplicitDefs[0], RC, RC);
996 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
997 unsigned Op0, uint32_t Idx) {
998 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
1000 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1001 const TargetInstrDesc &II = TII.get(TargetOpcode::EXTRACT_SUBREG);
1003 if (II.getNumDefs() >= 1)
1004 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
1006 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
1007 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1008 II.ImplicitDefs[0], RC, RC);
1015 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1016 /// with all but the least significant bit set to zero.
1017 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
1018 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);