1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/Target/TargetData.h"
51 #include "llvm/Target/TargetInstrInfo.h"
52 #include "llvm/Target/TargetLowering.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "SelectionDAGBuild.h"
57 unsigned FastISel::getRegForValue(Value *V) {
58 // Look up the value to see if we already have a register for it. We
59 // cache values defined by Instructions across blocks, and other values
60 // only locally. This is because Instructions already have the SSA
61 // def-dominatess-use requirement enforced.
62 if (ValueMap.count(V))
64 unsigned Reg = LocalValueMap[V];
68 MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
70 // Ignore illegal types.
71 if (!TLI.isTypeLegal(VT)) {
72 // Promote MVT::i1 to a legal type though, because it's common and easy.
74 VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
79 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
80 if (CI->getValue().getActiveBits() <= 64)
81 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
82 } else if (isa<AllocaInst>(V)) {
83 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
84 } else if (isa<ConstantPointerNull>(V)) {
85 // Translate this as an integer zero so that it can be
86 // local-CSE'd with actual integer zeros.
87 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType()));
88 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
89 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
92 const APFloat &Flt = CF->getValueAPF();
93 MVT IntVT = TLI.getPointerTy();
96 uint32_t IntBitWidth = IntVT.getSizeInBits();
98 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
99 APFloat::rmTowardZero, &isExact);
101 APInt IntVal(IntBitWidth, 2, x);
103 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal));
105 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
108 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
109 if (!SelectOperator(CE, CE->getOpcode())) return 0;
110 Reg = LocalValueMap[CE];
111 } else if (isa<UndefValue>(V)) {
112 Reg = createResultReg(TLI.getRegClassFor(VT));
113 BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
116 // If target-independent code couldn't handle the value, give target-specific
118 if (!Reg && isa<Constant>(V))
119 Reg = TargetMaterializeConstant(cast<Constant>(V));
121 // Don't cache constant materializations in the general ValueMap.
122 // To do so would require tracking what uses they dominate.
124 LocalValueMap[V] = Reg;
128 unsigned FastISel::lookUpRegForValue(Value *V) {
129 // Look up the value to see if we already have a register for it. We
130 // cache values defined by Instructions across blocks, and other values
131 // only locally. This is because Instructions already have the SSA
132 // def-dominatess-use requirement enforced.
133 if (ValueMap.count(V))
135 return LocalValueMap[V];
138 /// UpdateValueMap - Update the value map to include the new mapping for this
139 /// instruction, or insert an extra copy to get the result in a previous
140 /// determined register.
141 /// NOTE: This is only necessary because we might select a block that uses
142 /// a value before we select the block that defines the value. It might be
143 /// possible to fix this by selecting blocks in reverse postorder.
144 void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
145 if (!isa<Instruction>(I)) {
146 LocalValueMap[I] = Reg;
149 if (!ValueMap.count(I))
152 TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
153 Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
156 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
157 /// which has an opcode which directly corresponds to the given ISD opcode.
159 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
160 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
161 if (VT == MVT::Other || !VT.isSimple())
162 // Unhandled type. Halt "fast" selection and bail.
165 // We only handle legal types. For example, on x86-32 the instruction
166 // selector contains all of the 64-bit instructions from x86-64,
167 // under the assumption that i64 won't be used if the target doesn't
169 if (!TLI.isTypeLegal(VT)) {
170 // MVT::i1 is special. Allow AND, OR, or XOR because they
171 // don't require additional zeroing, which makes them easy.
173 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
174 ISDOpcode == ISD::XOR))
175 VT = TLI.getTypeToTransformTo(VT);
180 unsigned Op0 = getRegForValue(I->getOperand(0));
182 // Unhandled operand. Halt "fast" selection and bail.
185 // Check if the second operand is a constant and handle it appropriately.
186 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
187 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
188 ISDOpcode, Op0, CI->getZExtValue());
189 if (ResultReg != 0) {
190 // We successfully emitted code for the given LLVM Instruction.
191 UpdateValueMap(I, ResultReg);
196 // Check if the second operand is a constant float.
197 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
198 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
200 if (ResultReg != 0) {
201 // We successfully emitted code for the given LLVM Instruction.
202 UpdateValueMap(I, ResultReg);
207 unsigned Op1 = getRegForValue(I->getOperand(1));
209 // Unhandled operand. Halt "fast" selection and bail.
212 // Now we have both operands in registers. Emit the instruction.
213 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
214 ISDOpcode, Op0, Op1);
216 // Target-specific code wasn't able to find a machine opcode for
217 // the given ISD opcode and type. Halt "fast" selection and bail.
220 // We successfully emitted code for the given LLVM Instruction.
221 UpdateValueMap(I, ResultReg);
225 bool FastISel::SelectGetElementPtr(User *I) {
226 unsigned N = getRegForValue(I->getOperand(0));
228 // Unhandled operand. Halt "fast" selection and bail.
231 const Type *Ty = I->getOperand(0)->getType();
232 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
233 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
236 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
237 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
240 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
241 // FIXME: This can be optimized by combining the add with a
243 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
245 // Unhandled operand. Halt "fast" selection and bail.
248 Ty = StTy->getElementType(Field);
250 Ty = cast<SequentialType>(Ty)->getElementType();
252 // If this is a constant subscript, handle it quickly.
253 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
254 if (CI->getZExtValue() == 0) continue;
256 TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
257 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
259 // Unhandled operand. Halt "fast" selection and bail.
264 // N = N + Idx * ElementSize;
265 uint64_t ElementSize = TD.getABITypeSize(Ty);
266 unsigned IdxN = getRegForValue(Idx);
268 // Unhandled operand. Halt "fast" selection and bail.
271 // If the index is smaller or larger than intptr_t, truncate or extend
273 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
274 if (IdxVT.bitsLT(VT))
275 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
276 else if (IdxVT.bitsGT(VT))
277 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
279 // Unhandled operand. Halt "fast" selection and bail.
282 if (ElementSize != 1) {
283 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
285 // Unhandled operand. Halt "fast" selection and bail.
288 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
290 // Unhandled operand. Halt "fast" selection and bail.
295 // We successfully emitted code for the given LLVM Instruction.
296 UpdateValueMap(I, N);
300 bool FastISel::SelectCall(User *I) {
301 Function *F = cast<CallInst>(I)->getCalledFunction();
302 if (!F) return false;
304 unsigned IID = F->getIntrinsicID();
307 case Intrinsic::dbg_stoppoint: {
308 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
309 if (MMI && SPI->getContext() && MMI->Verify(SPI->getContext())) {
310 DebugInfoDesc *DD = MMI->getDescFor(SPI->getContext());
311 assert(DD && "Not a debug information descriptor");
312 const CompileUnitDesc *CompileUnit = cast<CompileUnitDesc>(DD);
313 unsigned SrcFile = MMI->RecordSource(CompileUnit);
314 unsigned Line = SPI->getLine();
315 unsigned Col = SPI->getColumn();
316 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
317 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
318 BuildMI(MBB, II).addImm(ID);
322 case Intrinsic::dbg_region_start: {
323 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
324 if (MMI && RSI->getContext() && MMI->Verify(RSI->getContext())) {
325 unsigned ID = MMI->RecordRegionStart(RSI->getContext());
326 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
327 BuildMI(MBB, II).addImm(ID);
331 case Intrinsic::dbg_region_end: {
332 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
333 if (MMI && REI->getContext() && MMI->Verify(REI->getContext())) {
334 unsigned ID = MMI->RecordRegionEnd(REI->getContext());
335 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
336 BuildMI(MBB, II).addImm(ID);
340 case Intrinsic::dbg_func_start: {
341 if (!MMI) return true;
342 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
343 Value *SP = FSI->getSubprogram();
344 if (SP && MMI->Verify(SP)) {
345 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
346 // what (most?) gdb expects.
347 DebugInfoDesc *DD = MMI->getDescFor(SP);
348 assert(DD && "Not a debug information descriptor");
349 SubprogramDesc *Subprogram = cast<SubprogramDesc>(DD);
350 const CompileUnitDesc *CompileUnit = Subprogram->getFile();
351 unsigned SrcFile = MMI->RecordSource(CompileUnit);
352 // Record the source line but does create a label. It will be emitted
353 // at asm emission time.
354 MMI->RecordSourceLine(Subprogram->getLine(), 0, SrcFile);
358 case Intrinsic::dbg_declare: {
359 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
360 Value *Variable = DI->getVariable();
361 if (MMI && Variable && MMI->Verify(Variable)) {
362 // Determine the address of the declared object.
363 Value *Address = DI->getAddress();
364 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
365 Address = BCI->getOperand(0);
366 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
367 // Don't handle byval struct arguments, for example.
369 DenseMap<const AllocaInst*, int>::iterator SI =
370 StaticAllocaMap.find(AI);
371 assert(SI != StaticAllocaMap.end() && "Invalid dbg.declare!");
374 // Determine the debug globalvariable.
375 GlobalValue *GV = cast<GlobalVariable>(Variable);
377 // Build the DECLARE instruction.
378 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
379 BuildMI(MBB, II).addFrameIndex(FI).addGlobalAddress(GV);
383 case Intrinsic::eh_exception: {
384 MVT VT = TLI.getValueType(I->getType());
385 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
387 case TargetLowering::Expand: {
388 if (!MBB->isLandingPad()) {
389 // FIXME: Mark exception register as live in. Hack for PR1508.
390 unsigned Reg = TLI.getExceptionAddressRegister();
391 if (Reg) MBB->addLiveIn(Reg);
393 unsigned Reg = TLI.getExceptionAddressRegister();
394 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
395 unsigned ResultReg = createResultReg(RC);
396 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
398 assert(InsertedCopy && "Can't copy address registers!");
399 UpdateValueMap(I, ResultReg);
405 case Intrinsic::eh_selector_i32:
406 case Intrinsic::eh_selector_i64: {
407 MVT VT = TLI.getValueType(I->getType());
408 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
410 case TargetLowering::Expand: {
411 MVT VT = (IID == Intrinsic::eh_selector_i32 ?
412 MVT::i32 : MVT::i64);
415 if (MBB->isLandingPad())
416 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
419 CatchInfoLost.insert(cast<CallInst>(I));
421 // FIXME: Mark exception selector register as live in. Hack for PR1508.
422 unsigned Reg = TLI.getExceptionSelectorRegister();
423 if (Reg) MBB->addLiveIn(Reg);
426 unsigned Reg = TLI.getExceptionSelectorRegister();
427 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
428 unsigned ResultReg = createResultReg(RC);
429 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
431 assert(InsertedCopy && "Can't copy address registers!");
432 UpdateValueMap(I, ResultReg);
435 getRegForValue(Constant::getNullValue(I->getType()));
436 UpdateValueMap(I, ResultReg);
447 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
448 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
449 MVT DstVT = TLI.getValueType(I->getType());
451 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
452 DstVT == MVT::Other || !DstVT.isSimple() ||
453 !TLI.isTypeLegal(DstVT))
454 // Unhandled type. Halt "fast" selection and bail.
457 // Check if the source operand is legal. Or as a special case,
458 // it may be i1 if we're doing zero-extension because that's
459 // trivially easy and somewhat common.
460 if (!TLI.isTypeLegal(SrcVT)) {
461 if (SrcVT == MVT::i1 && Opcode == ISD::ZERO_EXTEND)
462 SrcVT = TLI.getTypeToTransformTo(SrcVT);
464 // Unhandled type. Halt "fast" selection and bail.
468 unsigned InputReg = getRegForValue(I->getOperand(0));
470 // Unhandled operand. Halt "fast" selection and bail.
473 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
480 UpdateValueMap(I, ResultReg);
484 bool FastISel::SelectBitCast(User *I) {
485 // If the bitcast doesn't change the type, just use the operand value.
486 if (I->getType() == I->getOperand(0)->getType()) {
487 unsigned Reg = getRegForValue(I->getOperand(0));
490 UpdateValueMap(I, Reg);
494 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
495 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
496 MVT DstVT = TLI.getValueType(I->getType());
498 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
499 DstVT == MVT::Other || !DstVT.isSimple() ||
500 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
501 // Unhandled type. Halt "fast" selection and bail.
504 unsigned Op0 = getRegForValue(I->getOperand(0));
506 // Unhandled operand. Halt "fast" selection and bail.
509 // First, try to perform the bitcast by inserting a reg-reg copy.
510 unsigned ResultReg = 0;
511 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
512 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
513 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
514 ResultReg = createResultReg(DstClass);
516 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
517 Op0, DstClass, SrcClass);
522 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
524 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
525 ISD::BIT_CONVERT, Op0);
530 UpdateValueMap(I, ResultReg);
535 FastISel::SelectInstruction(Instruction *I) {
536 return SelectOperator(I, I->getOpcode());
539 /// FastEmitBranch - Emit an unconditional branch to the given block,
540 /// unless it is the immediate (fall-through) successor, and update
543 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
544 MachineFunction::iterator NextMBB =
545 next(MachineFunction::iterator(MBB));
547 if (MBB->isLayoutSuccessor(MSucc)) {
548 // The unconditional fall-through case, which needs no instructions.
550 // The unconditional branch case.
551 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
553 MBB->addSuccessor(MSucc);
557 FastISel::SelectOperator(User *I, unsigned Opcode) {
559 case Instruction::Add: {
560 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
561 return SelectBinaryOp(I, Opc);
563 case Instruction::Sub: {
564 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
565 return SelectBinaryOp(I, Opc);
567 case Instruction::Mul: {
568 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
569 return SelectBinaryOp(I, Opc);
571 case Instruction::SDiv:
572 return SelectBinaryOp(I, ISD::SDIV);
573 case Instruction::UDiv:
574 return SelectBinaryOp(I, ISD::UDIV);
575 case Instruction::FDiv:
576 return SelectBinaryOp(I, ISD::FDIV);
577 case Instruction::SRem:
578 return SelectBinaryOp(I, ISD::SREM);
579 case Instruction::URem:
580 return SelectBinaryOp(I, ISD::UREM);
581 case Instruction::FRem:
582 return SelectBinaryOp(I, ISD::FREM);
583 case Instruction::Shl:
584 return SelectBinaryOp(I, ISD::SHL);
585 case Instruction::LShr:
586 return SelectBinaryOp(I, ISD::SRL);
587 case Instruction::AShr:
588 return SelectBinaryOp(I, ISD::SRA);
589 case Instruction::And:
590 return SelectBinaryOp(I, ISD::AND);
591 case Instruction::Or:
592 return SelectBinaryOp(I, ISD::OR);
593 case Instruction::Xor:
594 return SelectBinaryOp(I, ISD::XOR);
596 case Instruction::GetElementPtr:
597 return SelectGetElementPtr(I);
599 case Instruction::Br: {
600 BranchInst *BI = cast<BranchInst>(I);
602 if (BI->isUnconditional()) {
603 BasicBlock *LLVMSucc = BI->getSuccessor(0);
604 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
605 FastEmitBranch(MSucc);
609 // Conditional branches are not handed yet.
610 // Halt "fast" selection and bail.
614 case Instruction::Unreachable:
618 case Instruction::PHI:
619 // PHI nodes are already emitted.
622 case Instruction::Alloca:
623 // FunctionLowering has the static-sized case covered.
624 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
627 // Dynamic-sized alloca is not handled yet.
630 case Instruction::Call:
631 return SelectCall(I);
633 case Instruction::BitCast:
634 return SelectBitCast(I);
636 case Instruction::FPToSI:
637 return SelectCast(I, ISD::FP_TO_SINT);
638 case Instruction::ZExt:
639 return SelectCast(I, ISD::ZERO_EXTEND);
640 case Instruction::SExt:
641 return SelectCast(I, ISD::SIGN_EXTEND);
642 case Instruction::Trunc:
643 return SelectCast(I, ISD::TRUNCATE);
644 case Instruction::SIToFP:
645 return SelectCast(I, ISD::SINT_TO_FP);
647 case Instruction::IntToPtr: // Deliberate fall-through.
648 case Instruction::PtrToInt: {
649 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
650 MVT DstVT = TLI.getValueType(I->getType());
651 if (DstVT.bitsGT(SrcVT))
652 return SelectCast(I, ISD::ZERO_EXTEND);
653 if (DstVT.bitsLT(SrcVT))
654 return SelectCast(I, ISD::TRUNCATE);
655 unsigned Reg = getRegForValue(I->getOperand(0));
656 if (Reg == 0) return false;
657 UpdateValueMap(I, Reg);
662 // Unhandled instruction. Halt "fast" selection and bail.
667 FastISel::FastISel(MachineFunction &mf,
668 MachineModuleInfo *mmi,
669 DenseMap<const Value *, unsigned> &vm,
670 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
671 DenseMap<const AllocaInst *, int> &am
673 , SmallSet<Instruction*, 8> &cil
685 MRI(MF.getRegInfo()),
686 MFI(*MF.getFrameInfo()),
687 MCP(*MF.getConstantPool()),
689 TD(*TM.getTargetData()),
690 TII(*TM.getInstrInfo()),
691 TLI(*TM.getTargetLowering()) {
694 FastISel::~FastISel() {}
696 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
701 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
702 ISD::NodeType, unsigned /*Op0*/) {
706 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
707 ISD::NodeType, unsigned /*Op0*/,
712 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
713 ISD::NodeType, uint64_t /*Imm*/) {
717 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
718 ISD::NodeType, ConstantFP * /*FPImm*/) {
722 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
723 ISD::NodeType, unsigned /*Op0*/,
728 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
729 ISD::NodeType, unsigned /*Op0*/,
730 ConstantFP * /*FPImm*/) {
734 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
736 unsigned /*Op0*/, unsigned /*Op1*/,
741 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
742 /// to emit an instruction with an immediate operand using FastEmit_ri.
743 /// If that fails, it materializes the immediate into a register and try
744 /// FastEmit_rr instead.
745 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
746 unsigned Op0, uint64_t Imm,
747 MVT::SimpleValueType ImmType) {
748 // First check if immediate type is legal. If not, we can't use the ri form.
749 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
752 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
753 if (MaterialReg == 0)
755 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
758 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
759 /// to emit an instruction with a floating-point immediate operand using
760 /// FastEmit_rf. If that fails, it materializes the immediate into a register
761 /// and try FastEmit_rr instead.
762 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
763 unsigned Op0, ConstantFP *FPImm,
764 MVT::SimpleValueType ImmType) {
765 // First check if immediate type is legal. If not, we can't use the rf form.
766 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
770 // Materialize the constant in a register.
771 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
772 if (MaterialReg == 0) {
773 // If the target doesn't have a way to directly enter a floating-point
774 // value into a register, use an alternate approach.
775 // TODO: The current approach only supports floating-point constants
776 // that can be constructed by conversion from integer values. This should
777 // be replaced by code that creates a load from a constant-pool entry,
778 // which will require some target-specific work.
779 const APFloat &Flt = FPImm->getValueAPF();
780 MVT IntVT = TLI.getPointerTy();
783 uint32_t IntBitWidth = IntVT.getSizeInBits();
785 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
786 APFloat::rmTowardZero, &isExact);
789 APInt IntVal(IntBitWidth, 2, x);
791 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
792 ISD::Constant, IntVal.getZExtValue());
795 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
796 ISD::SINT_TO_FP, IntegerReg);
797 if (MaterialReg == 0)
800 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
803 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
804 return MRI.createVirtualRegister(RC);
807 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
808 const TargetRegisterClass* RC) {
809 unsigned ResultReg = createResultReg(RC);
810 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
812 BuildMI(MBB, II, ResultReg);
816 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
817 const TargetRegisterClass *RC,
819 unsigned ResultReg = createResultReg(RC);
820 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
822 if (II.getNumDefs() >= 1)
823 BuildMI(MBB, II, ResultReg).addReg(Op0);
825 BuildMI(MBB, II).addReg(Op0);
826 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
827 II.ImplicitDefs[0], RC, RC);
835 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
836 const TargetRegisterClass *RC,
837 unsigned Op0, unsigned Op1) {
838 unsigned ResultReg = createResultReg(RC);
839 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
841 if (II.getNumDefs() >= 1)
842 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
844 BuildMI(MBB, II).addReg(Op0).addReg(Op1);
845 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
846 II.ImplicitDefs[0], RC, RC);
853 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
854 const TargetRegisterClass *RC,
855 unsigned Op0, uint64_t Imm) {
856 unsigned ResultReg = createResultReg(RC);
857 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
859 if (II.getNumDefs() >= 1)
860 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
862 BuildMI(MBB, II).addReg(Op0).addImm(Imm);
863 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
864 II.ImplicitDefs[0], RC, RC);
871 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
872 const TargetRegisterClass *RC,
873 unsigned Op0, ConstantFP *FPImm) {
874 unsigned ResultReg = createResultReg(RC);
875 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
877 if (II.getNumDefs() >= 1)
878 BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
880 BuildMI(MBB, II).addReg(Op0).addFPImm(FPImm);
881 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
882 II.ImplicitDefs[0], RC, RC);
889 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
890 const TargetRegisterClass *RC,
891 unsigned Op0, unsigned Op1, uint64_t Imm) {
892 unsigned ResultReg = createResultReg(RC);
893 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
895 if (II.getNumDefs() >= 1)
896 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
898 BuildMI(MBB, II).addReg(Op0).addReg(Op1).addImm(Imm);
899 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
900 II.ImplicitDefs[0], RC, RC);
907 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
908 const TargetRegisterClass *RC,
910 unsigned ResultReg = createResultReg(RC);
911 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
913 if (II.getNumDefs() >= 1)
914 BuildMI(MBB, II, ResultReg).addImm(Imm);
916 BuildMI(MBB, II).addImm(Imm);
917 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
918 II.ImplicitDefs[0], RC, RC);
925 unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
926 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
927 const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
929 unsigned ResultReg = createResultReg(SRC);
930 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
932 if (II.getNumDefs() >= 1)
933 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
935 BuildMI(MBB, II).addReg(Op0).addImm(Idx);
936 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
937 II.ImplicitDefs[0], RC, RC);