1 //===-- FastISel.cpp - Implementation of the FastISel class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/CodeGen/FastISel.h"
43 #include "llvm/ADT/Optional.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Analysis/BranchProbabilityInfo.h"
46 #include "llvm/Analysis/Loads.h"
47 #include "llvm/CodeGen/Analysis.h"
48 #include "llvm/CodeGen/FunctionLoweringInfo.h"
49 #include "llvm/CodeGen/MachineFrameInfo.h"
50 #include "llvm/CodeGen/MachineInstrBuilder.h"
51 #include "llvm/CodeGen/MachineModuleInfo.h"
52 #include "llvm/CodeGen/MachineRegisterInfo.h"
53 #include "llvm/CodeGen/StackMaps.h"
54 #include "llvm/IR/DataLayout.h"
55 #include "llvm/IR/DebugInfo.h"
56 #include "llvm/IR/Function.h"
57 #include "llvm/IR/GlobalVariable.h"
58 #include "llvm/IR/Instructions.h"
59 #include "llvm/IR/IntrinsicInst.h"
60 #include "llvm/IR/Operator.h"
61 #include "llvm/Support/Debug.h"
62 #include "llvm/Support/ErrorHandling.h"
63 #include "llvm/Target/TargetInstrInfo.h"
64 #include "llvm/Target/TargetLibraryInfo.h"
65 #include "llvm/Target/TargetLowering.h"
66 #include "llvm/Target/TargetMachine.h"
69 #define DEBUG_TYPE "isel"
71 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
72 "target-independent selector");
73 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
74 "target-specific selector");
75 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
77 /// startNewBlock - Set the current block to which generated machine
78 /// instructions will be appended, and clear the local CSE map.
80 void FastISel::startNewBlock() {
81 LocalValueMap.clear();
83 // Instructions are appended to FuncInfo.MBB. If the basic block already
84 // contains labels or copies, use the last instruction as the last local
86 EmitStartPt = nullptr;
87 if (!FuncInfo.MBB->empty())
88 EmitStartPt = &FuncInfo.MBB->back();
89 LastLocalValue = EmitStartPt;
92 bool FastISel::LowerArguments() {
93 if (!FuncInfo.CanLowerReturn)
94 // Fallback to SDISel argument lowering code to deal with sret pointer
98 if (!FastLowerArguments())
101 // Enter arguments into ValueMap for uses in non-entry BBs.
102 for (Function::const_arg_iterator I = FuncInfo.Fn->arg_begin(),
103 E = FuncInfo.Fn->arg_end(); I != E; ++I) {
104 DenseMap<const Value *, unsigned>::iterator VI = LocalValueMap.find(I);
105 assert(VI != LocalValueMap.end() && "Missed an argument?");
106 FuncInfo.ValueMap[I] = VI->second;
111 void FastISel::flushLocalValueMap() {
112 LocalValueMap.clear();
113 LastLocalValue = EmitStartPt;
117 bool FastISel::hasTrivialKill(const Value *V) const {
118 // Don't consider constants or arguments to have trivial kills.
119 const Instruction *I = dyn_cast<Instruction>(V);
123 // No-op casts are trivially coalesced by fast-isel.
124 if (const CastInst *Cast = dyn_cast<CastInst>(I))
125 if (Cast->isNoopCast(DL.getIntPtrType(Cast->getContext())) &&
126 !hasTrivialKill(Cast->getOperand(0)))
129 // GEPs with all zero indices are trivially coalesced by fast-isel.
130 if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(I))
131 if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0)))
134 // Only instructions with a single use in the same basic block are considered
135 // to have trivial kills.
136 return I->hasOneUse() &&
137 !(I->getOpcode() == Instruction::BitCast ||
138 I->getOpcode() == Instruction::PtrToInt ||
139 I->getOpcode() == Instruction::IntToPtr) &&
140 cast<Instruction>(*I->user_begin())->getParent() == I->getParent();
143 unsigned FastISel::getRegForValue(const Value *V) {
144 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
145 // Don't handle non-simple values in FastISel.
146 if (!RealVT.isSimple())
149 // Ignore illegal types. We must do this before looking up the value
150 // in ValueMap because Arguments are given virtual registers regardless
151 // of whether FastISel can handle them.
152 MVT VT = RealVT.getSimpleVT();
153 if (!TLI.isTypeLegal(VT)) {
154 // Handle integer promotions, though, because they're common and easy.
155 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
156 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
161 // Look up the value to see if we already have a register for it.
162 unsigned Reg = lookUpRegForValue(V);
166 // In bottom-up mode, just create the virtual register which will be used
167 // to hold the value. It will be materialized later.
168 if (isa<Instruction>(V) &&
169 (!isa<AllocaInst>(V) ||
170 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
171 return FuncInfo.InitializeRegForValue(V);
173 SavePoint SaveInsertPt = enterLocalValueArea();
175 // Materialize the value in a register. Emit any instructions in the
177 Reg = materializeRegForValue(V, VT);
179 leaveLocalValueArea(SaveInsertPt);
184 /// materializeRegForValue - Helper for getRegForValue. This function is
185 /// called when the value isn't already available in a register and must
186 /// be materialized with new instructions.
187 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
190 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
191 if (CI->getValue().getActiveBits() <= 64)
192 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
193 } else if (isa<AllocaInst>(V)) {
194 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
195 } else if (isa<ConstantPointerNull>(V)) {
196 // Translate this as an integer zero so that it can be
197 // local-CSE'd with actual integer zeros.
199 getRegForValue(Constant::getNullValue(DL.getIntPtrType(V->getContext())));
200 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
201 if (CF->isNullValue()) {
202 Reg = TargetMaterializeFloatZero(CF);
204 // Try to emit the constant directly.
205 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
209 // Try to emit the constant by using an integer constant with a cast.
210 const APFloat &Flt = CF->getValueAPF();
211 EVT IntVT = TLI.getPointerTy();
214 uint32_t IntBitWidth = IntVT.getSizeInBits();
216 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
217 APFloat::rmTowardZero, &isExact);
219 APInt IntVal(IntBitWidth, x);
221 unsigned IntegerReg =
222 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
224 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
225 IntegerReg, /*Kill=*/false);
228 } else if (const Operator *Op = dyn_cast<Operator>(V)) {
229 if (!SelectOperator(Op, Op->getOpcode()))
230 if (!isa<Instruction>(Op) ||
231 !TargetSelectInstruction(cast<Instruction>(Op)))
233 Reg = lookUpRegForValue(Op);
234 } else if (isa<UndefValue>(V)) {
235 Reg = createResultReg(TLI.getRegClassFor(VT));
236 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
237 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
240 // If target-independent code couldn't handle the value, give target-specific
242 if (!Reg && isa<Constant>(V))
243 Reg = TargetMaterializeConstant(cast<Constant>(V));
245 // Don't cache constant materializations in the general ValueMap.
246 // To do so would require tracking what uses they dominate.
248 LocalValueMap[V] = Reg;
249 LastLocalValue = MRI.getVRegDef(Reg);
254 unsigned FastISel::lookUpRegForValue(const Value *V) {
255 // Look up the value to see if we already have a register for it. We
256 // cache values defined by Instructions across blocks, and other values
257 // only locally. This is because Instructions already have the SSA
258 // def-dominates-use requirement enforced.
259 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
260 if (I != FuncInfo.ValueMap.end())
262 return LocalValueMap[V];
265 /// UpdateValueMap - Update the value map to include the new mapping for this
266 /// instruction, or insert an extra copy to get the result in a previous
267 /// determined register.
268 /// NOTE: This is only necessary because we might select a block that uses
269 /// a value before we select the block that defines the value. It might be
270 /// possible to fix this by selecting blocks in reverse postorder.
271 void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) {
272 if (!isa<Instruction>(I)) {
273 LocalValueMap[I] = Reg;
277 unsigned &AssignedReg = FuncInfo.ValueMap[I];
278 if (AssignedReg == 0)
279 // Use the new register.
281 else if (Reg != AssignedReg) {
282 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
283 for (unsigned i = 0; i < NumRegs; i++)
284 FuncInfo.RegFixups[AssignedReg+i] = Reg+i;
290 std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) {
291 unsigned IdxN = getRegForValue(Idx);
293 // Unhandled operand. Halt "fast" selection and bail.
294 return std::pair<unsigned, bool>(0, false);
296 bool IdxNIsKill = hasTrivialKill(Idx);
298 // If the index is smaller or larger than intptr_t, truncate or extend it.
299 MVT PtrVT = TLI.getPointerTy();
300 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
301 if (IdxVT.bitsLT(PtrVT)) {
302 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND,
306 else if (IdxVT.bitsGT(PtrVT)) {
307 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE,
311 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
314 void FastISel::recomputeInsertPt() {
315 if (getLastLocalValue()) {
316 FuncInfo.InsertPt = getLastLocalValue();
317 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
320 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
322 // Now skip past any EH_LABELs, which must remain at the beginning.
323 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
324 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
328 void FastISel::removeDeadCode(MachineBasicBlock::iterator I,
329 MachineBasicBlock::iterator E) {
330 assert (I && E && std::distance(I, E) > 0 && "Invalid iterator!");
332 MachineInstr *Dead = &*I;
334 Dead->eraseFromParent();
340 FastISel::SavePoint FastISel::enterLocalValueArea() {
341 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
342 DebugLoc OldDL = DbgLoc;
345 SavePoint SP = { OldInsertPt, OldDL };
349 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
350 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
351 LastLocalValue = std::prev(FuncInfo.InsertPt);
353 // Restore the previous insert position.
354 FuncInfo.InsertPt = OldInsertPt.InsertPt;
355 DbgLoc = OldInsertPt.DL;
358 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
359 /// which has an opcode which directly corresponds to the given ISD opcode.
361 bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) {
362 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
363 if (VT == MVT::Other || !VT.isSimple())
364 // Unhandled type. Halt "fast" selection and bail.
367 // We only handle legal types. For example, on x86-32 the instruction
368 // selector contains all of the 64-bit instructions from x86-64,
369 // under the assumption that i64 won't be used if the target doesn't
371 if (!TLI.isTypeLegal(VT)) {
372 // MVT::i1 is special. Allow AND, OR, or XOR because they
373 // don't require additional zeroing, which makes them easy.
375 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
376 ISDOpcode == ISD::XOR))
377 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
382 // Check if the first operand is a constant, and handle it as "ri". At -O0,
383 // we don't have anything that canonicalizes operand order.
384 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
385 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
386 unsigned Op1 = getRegForValue(I->getOperand(1));
387 if (Op1 == 0) return false;
389 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
391 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
392 Op1IsKill, CI->getZExtValue(),
394 if (ResultReg == 0) return false;
396 // We successfully emitted code for the given LLVM Instruction.
397 UpdateValueMap(I, ResultReg);
402 unsigned Op0 = getRegForValue(I->getOperand(0));
403 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail.
406 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
408 // Check if the second operand is a constant and handle it appropriately.
409 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
410 uint64_t Imm = CI->getZExtValue();
412 // Transform "sdiv exact X, 8" -> "sra X, 3".
413 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
414 cast<BinaryOperator>(I)->isExact() &&
415 isPowerOf2_64(Imm)) {
417 ISDOpcode = ISD::SRA;
420 // Transform "urem x, pow2" -> "and x, pow2-1".
421 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
422 isPowerOf2_64(Imm)) {
424 ISDOpcode = ISD::AND;
427 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
428 Op0IsKill, Imm, VT.getSimpleVT());
429 if (ResultReg == 0) return false;
431 // We successfully emitted code for the given LLVM Instruction.
432 UpdateValueMap(I, ResultReg);
436 // Check if the second operand is a constant float.
437 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
438 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
439 ISDOpcode, Op0, Op0IsKill, CF);
440 if (ResultReg != 0) {
441 // We successfully emitted code for the given LLVM Instruction.
442 UpdateValueMap(I, ResultReg);
447 unsigned Op1 = getRegForValue(I->getOperand(1));
449 // Unhandled operand. Halt "fast" selection and bail.
452 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
454 // Now we have both operands in registers. Emit the instruction.
455 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
460 // Target-specific code wasn't able to find a machine opcode for
461 // the given ISD opcode and type. Halt "fast" selection and bail.
464 // We successfully emitted code for the given LLVM Instruction.
465 UpdateValueMap(I, ResultReg);
469 bool FastISel::SelectGetElementPtr(const User *I) {
470 unsigned N = getRegForValue(I->getOperand(0));
472 // Unhandled operand. Halt "fast" selection and bail.
475 bool NIsKill = hasTrivialKill(I->getOperand(0));
477 // Keep a running tab of the total offset to coalesce multiple N = N + Offset
478 // into a single N = N + TotalOffset.
479 uint64_t TotalOffs = 0;
480 // FIXME: What's a good SWAG number for MaxOffs?
481 uint64_t MaxOffs = 2048;
482 Type *Ty = I->getOperand(0)->getType();
483 MVT VT = TLI.getPointerTy();
484 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1,
485 E = I->op_end(); OI != E; ++OI) {
486 const Value *Idx = *OI;
487 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
488 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
491 TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
492 if (TotalOffs >= MaxOffs) {
493 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
495 // Unhandled operand. Halt "fast" selection and bail.
501 Ty = StTy->getElementType(Field);
503 Ty = cast<SequentialType>(Ty)->getElementType();
505 // If this is a constant subscript, handle it quickly.
506 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
507 if (CI->isZero()) continue;
510 DL.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
511 if (TotalOffs >= MaxOffs) {
512 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
514 // Unhandled operand. Halt "fast" selection and bail.
522 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
524 // Unhandled operand. Halt "fast" selection and bail.
530 // N = N + Idx * ElementSize;
531 uint64_t ElementSize = DL.getTypeAllocSize(Ty);
532 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
533 unsigned IdxN = Pair.first;
534 bool IdxNIsKill = Pair.second;
536 // Unhandled operand. Halt "fast" selection and bail.
539 if (ElementSize != 1) {
540 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
542 // Unhandled operand. Halt "fast" selection and bail.
546 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
548 // Unhandled operand. Halt "fast" selection and bail.
553 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
555 // Unhandled operand. Halt "fast" selection and bail.
559 // We successfully emitted code for the given LLVM Instruction.
560 UpdateValueMap(I, N);
564 /// \brief Add a stackmap or patchpoint intrinsic call's live variable operands
565 /// to a stackmap or patchpoint machine instruction.
566 bool FastISel::addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
567 const CallInst *CI, unsigned StartIdx) {
568 for (unsigned i = StartIdx, e = CI->getNumArgOperands(); i != e; ++i) {
569 Value *Val = CI->getArgOperand(i);
570 // Check for constants and encode them with a StackMaps::ConstantOp prefix.
571 if (auto *C = dyn_cast<ConstantInt>(Val)) {
572 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
573 Ops.push_back(MachineOperand::CreateImm(C->getSExtValue()));
574 } else if (isa<ConstantPointerNull>(Val)) {
575 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
576 Ops.push_back(MachineOperand::CreateImm(0));
577 } else if (auto *AI = dyn_cast<AllocaInst>(Val)) {
578 // Values coming from a stack location also require a sepcial encoding,
579 // but that is added later on by the target specific frame index
580 // elimination implementation.
581 auto SI = FuncInfo.StaticAllocaMap.find(AI);
582 if (SI != FuncInfo.StaticAllocaMap.end())
583 Ops.push_back(MachineOperand::CreateFI(SI->second));
587 unsigned Reg = getRegForValue(Val);
590 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
597 bool FastISel::SelectStackmap(const CallInst *I) {
598 // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
599 // [live variables...])
600 assert(I->getCalledFunction()->getReturnType()->isVoidTy() &&
601 "Stackmap cannot return a value.");
603 // The stackmap intrinsic only records the live variables (the arguments
604 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
605 // intrinsic, this won't be lowered to a function call. This means we don't
606 // have to worry about calling conventions and target-specific lowering code.
607 // Instead we perform the call lowering right here.
610 // STACKMAP(id, nbytes, ...)
613 SmallVector<MachineOperand, 32> Ops;
615 // Add the <id> and <numBytes> constants.
616 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
617 "Expected a constant integer.");
618 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
619 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
621 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
622 "Expected a constant integer.");
623 const auto *NumBytes =
624 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
625 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
627 // Push live variables for the stack map (skipping the first two arguments
628 // <id> and <numBytes>).
629 if (!addStackMapLiveVars(Ops, I, 2))
632 // We are not adding any register mask info here, because the stackmap doesn't
635 // Add scratch registers as implicit def and early clobber.
636 CallingConv::ID CC = I->getCallingConv();
637 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
638 for (unsigned i = 0; ScratchRegs[i]; ++i)
639 Ops.push_back(MachineOperand::CreateReg(
640 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
641 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
643 // Issue CALLSEQ_START
644 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
645 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
649 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
650 TII.get(TargetOpcode::STACKMAP));
651 for (auto const &MO : Ops)
655 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
656 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
657 .addImm(0).addImm(0);
659 // Inform the Frame Information that we have a stackmap in this function.
660 FuncInfo.MF->getFrameInfo()->setHasStackMap();
665 bool FastISel::SelectCall(const User *I) {
666 const CallInst *Call = cast<CallInst>(I);
668 // Handle simple inline asms.
669 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledValue())) {
670 // Don't attempt to handle constraints.
671 if (!IA->getConstraintString().empty())
674 unsigned ExtraInfo = 0;
675 if (IA->hasSideEffects())
676 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
677 if (IA->isAlignStack())
678 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
680 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
681 TII.get(TargetOpcode::INLINEASM))
682 .addExternalSymbol(IA->getAsmString().c_str())
687 MachineModuleInfo &MMI = FuncInfo.MF->getMMI();
688 ComputeUsesVAFloatArgument(*Call, &MMI);
690 const Function *F = Call->getCalledFunction();
691 if (!F) return false;
693 // Handle selected intrinsic function calls.
694 switch (F->getIntrinsicID()) {
696 // At -O0 we don't care about the lifetime intrinsics.
697 case Intrinsic::lifetime_start:
698 case Intrinsic::lifetime_end:
699 // The donothing intrinsic does, well, nothing.
700 case Intrinsic::donothing:
703 case Intrinsic::dbg_declare: {
704 const DbgDeclareInst *DI = cast<DbgDeclareInst>(Call);
705 DIVariable DIVar(DI->getVariable());
706 assert((!DIVar || DIVar.isVariable()) &&
707 "Variable in DbgDeclareInst should be either null or a DIVariable.");
709 !FuncInfo.MF->getMMI().hasDebugInfo()) {
710 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
714 const Value *Address = DI->getAddress();
715 if (!Address || isa<UndefValue>(Address)) {
716 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
721 Optional<MachineOperand> Op;
722 if (const Argument *Arg = dyn_cast<Argument>(Address))
723 // Some arguments' frame index is recorded during argument lowering.
724 Offset = FuncInfo.getArgumentFrameIndex(Arg);
726 Op = MachineOperand::CreateFI(Offset);
728 if (unsigned Reg = lookUpRegForValue(Address))
729 Op = MachineOperand::CreateReg(Reg, false);
731 // If we have a VLA that has a "use" in a metadata node that's then used
732 // here but it has no other uses, then we have a problem. E.g.,
734 // int foo (const int *x) {
739 // If we assign 'a' a vreg and fast isel later on has to use the selection
740 // DAG isel, it will want to copy the value to the vreg. However, there are
741 // no uses, which goes counter to what selection DAG isel expects.
742 if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&
743 (!isa<AllocaInst>(Address) ||
744 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
745 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
750 Op->setIsDebug(true);
751 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
752 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0,
755 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
756 TII.get(TargetOpcode::DBG_VALUE))
759 .addMetadata(DI->getVariable());
761 // We can't yet handle anything else here because it would require
762 // generating code, thus altering codegen because of debug info.
763 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
767 case Intrinsic::dbg_value: {
768 // This form of DBG_VALUE is target-independent.
769 const DbgValueInst *DI = cast<DbgValueInst>(Call);
770 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
771 const Value *V = DI->getValue();
773 // Currently the optimizer can produce this; insert an undef to
774 // help debugging. Probably the optimizer should not do this.
775 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
776 .addReg(0U).addImm(DI->getOffset())
777 .addMetadata(DI->getVariable());
778 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
779 if (CI->getBitWidth() > 64)
780 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
781 .addCImm(CI).addImm(DI->getOffset())
782 .addMetadata(DI->getVariable());
784 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
785 .addImm(CI->getZExtValue()).addImm(DI->getOffset())
786 .addMetadata(DI->getVariable());
787 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
788 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
789 .addFPImm(CF).addImm(DI->getOffset())
790 .addMetadata(DI->getVariable());
791 } else if (unsigned Reg = lookUpRegForValue(V)) {
792 // FIXME: This does not handle register-indirect values at offset 0.
793 bool IsIndirect = DI->getOffset() != 0;
794 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, IsIndirect,
795 Reg, DI->getOffset(), DI->getVariable());
797 // We can't yet handle anything else here because it would require
798 // generating code, thus altering codegen because of debug info.
799 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
803 case Intrinsic::objectsize: {
804 ConstantInt *CI = cast<ConstantInt>(Call->getArgOperand(1));
805 unsigned long long Res = CI->isZero() ? -1ULL : 0;
806 Constant *ResCI = ConstantInt::get(Call->getType(), Res);
807 unsigned ResultReg = getRegForValue(ResCI);
810 UpdateValueMap(Call, ResultReg);
813 case Intrinsic::expect: {
814 unsigned ResultReg = getRegForValue(Call->getArgOperand(0));
817 UpdateValueMap(Call, ResultReg);
820 case Intrinsic::experimental_stackmap:
821 return SelectStackmap(Call);
824 // Usually, it does not make sense to initialize a value,
825 // make an unrelated function call and use the value, because
826 // it tends to be spilled on the stack. So, we move the pointer
827 // to the last local value to the beginning of the block, so that
828 // all the values which have already been materialized,
829 // appear after the call. It also makes sense to skip intrinsics
830 // since they tend to be inlined.
831 if (!isa<IntrinsicInst>(Call))
832 flushLocalValueMap();
834 // An arbitrary call. Bail.
838 bool FastISel::SelectCast(const User *I, unsigned Opcode) {
839 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
840 EVT DstVT = TLI.getValueType(I->getType());
842 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
843 DstVT == MVT::Other || !DstVT.isSimple())
844 // Unhandled type. Halt "fast" selection and bail.
847 // Check if the destination type is legal.
848 if (!TLI.isTypeLegal(DstVT))
851 // Check if the source operand is legal.
852 if (!TLI.isTypeLegal(SrcVT))
855 unsigned InputReg = getRegForValue(I->getOperand(0));
857 // Unhandled operand. Halt "fast" selection and bail.
860 bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
862 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
865 InputReg, InputRegIsKill);
869 UpdateValueMap(I, ResultReg);
873 bool FastISel::SelectBitCast(const User *I) {
874 // If the bitcast doesn't change the type, just use the operand value.
875 if (I->getType() == I->getOperand(0)->getType()) {
876 unsigned Reg = getRegForValue(I->getOperand(0));
879 UpdateValueMap(I, Reg);
883 // Bitcasts of other values become reg-reg copies or BITCAST operators.
884 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType());
885 EVT DstEVT = TLI.getValueType(I->getType());
886 if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
887 !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
888 // Unhandled type. Halt "fast" selection and bail.
891 MVT SrcVT = SrcEVT.getSimpleVT();
892 MVT DstVT = DstEVT.getSimpleVT();
893 unsigned Op0 = getRegForValue(I->getOperand(0));
895 // Unhandled operand. Halt "fast" selection and bail.
898 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
900 // First, try to perform the bitcast by inserting a reg-reg copy.
901 unsigned ResultReg = 0;
902 if (SrcVT == DstVT) {
903 const TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
904 const TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
905 // Don't attempt a cross-class copy. It will likely fail.
906 if (SrcClass == DstClass) {
907 ResultReg = createResultReg(DstClass);
908 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
909 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
913 // If the reg-reg copy failed, select a BITCAST opcode.
915 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
920 UpdateValueMap(I, ResultReg);
925 FastISel::SelectInstruction(const Instruction *I) {
926 // Just before the terminator instruction, insert instructions to
927 // feed PHI nodes in successor blocks.
928 if (isa<TerminatorInst>(I))
929 if (!HandlePHINodesInSuccessorBlocks(I->getParent()))
932 DbgLoc = I->getDebugLoc();
934 MachineBasicBlock::iterator SavedInsertPt = FuncInfo.InsertPt;
936 if (const CallInst *Call = dyn_cast<CallInst>(I)) {
937 const Function *F = Call->getCalledFunction();
940 // As a special case, don't handle calls to builtin library functions that
941 // may be translated directly to target instructions.
942 if (F && !F->hasLocalLinkage() && F->hasName() &&
943 LibInfo->getLibFunc(F->getName(), Func) &&
944 LibInfo->hasOptimizedCodeGen(Func))
947 // Don't handle Intrinsic::trap if a trap funciton is specified.
948 if (F && F->getIntrinsicID() == Intrinsic::trap &&
949 !TM.Options.getTrapFunctionName().empty())
953 // First, try doing target-independent selection.
954 if (SelectOperator(I, I->getOpcode())) {
955 ++NumFastIselSuccessIndependent;
959 // Remove dead code. However, ignore call instructions since we've flushed
960 // the local value map and recomputed the insert point.
961 if (!isa<CallInst>(I)) {
963 if (SavedInsertPt != FuncInfo.InsertPt)
964 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
967 // Next, try calling the target to attempt to handle the instruction.
968 SavedInsertPt = FuncInfo.InsertPt;
969 if (TargetSelectInstruction(I)) {
970 ++NumFastIselSuccessTarget;
974 // Check for dead code and remove as necessary.
976 if (SavedInsertPt != FuncInfo.InsertPt)
977 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
983 /// FastEmitBranch - Emit an unconditional branch to the given block,
984 /// unless it is the immediate (fall-through) successor, and update
987 FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DbgLoc) {
988 if (FuncInfo.MBB->getBasicBlock()->size() > 1 &&
989 FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
990 // For more accurate line information if this is the only instruction
991 // in the block then emit it, otherwise we have the unconditional
992 // fall-through case, which needs no instructions.
994 // The unconditional branch case.
995 TII.InsertBranch(*FuncInfo.MBB, MSucc, nullptr,
996 SmallVector<MachineOperand, 0>(), DbgLoc);
998 uint32_t BranchWeight = 0;
1000 BranchWeight = FuncInfo.BPI->getEdgeWeight(FuncInfo.MBB->getBasicBlock(),
1001 MSucc->getBasicBlock());
1002 FuncInfo.MBB->addSuccessor(MSucc, BranchWeight);
1005 /// SelectFNeg - Emit an FNeg operation.
1008 FastISel::SelectFNeg(const User *I) {
1009 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
1010 if (OpReg == 0) return false;
1012 bool OpRegIsKill = hasTrivialKill(I);
1014 // If the target has ISD::FNEG, use it.
1015 EVT VT = TLI.getValueType(I->getType());
1016 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
1017 ISD::FNEG, OpReg, OpRegIsKill);
1018 if (ResultReg != 0) {
1019 UpdateValueMap(I, ResultReg);
1023 // Bitcast the value to integer, twiddle the sign bit with xor,
1024 // and then bitcast it back to floating-point.
1025 if (VT.getSizeInBits() > 64) return false;
1026 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
1027 if (!TLI.isTypeLegal(IntVT))
1030 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1031 ISD::BITCAST, OpReg, OpRegIsKill);
1035 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR,
1036 IntReg, /*Kill=*/true,
1037 UINT64_C(1) << (VT.getSizeInBits()-1),
1038 IntVT.getSimpleVT());
1039 if (IntResultReg == 0)
1042 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
1043 ISD::BITCAST, IntResultReg, /*Kill=*/true);
1047 UpdateValueMap(I, ResultReg);
1052 FastISel::SelectExtractValue(const User *U) {
1053 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
1057 // Make sure we only try to handle extracts with a legal result. But also
1058 // allow i1 because it's easy.
1059 EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true);
1060 if (!RealVT.isSimple())
1062 MVT VT = RealVT.getSimpleVT();
1063 if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
1066 const Value *Op0 = EVI->getOperand(0);
1067 Type *AggTy = Op0->getType();
1069 // Get the base result register.
1071 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
1072 if (I != FuncInfo.ValueMap.end())
1073 ResultReg = I->second;
1074 else if (isa<Instruction>(Op0))
1075 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1077 return false; // fast-isel can't handle aggregate constants at the moment
1079 // Get the actual result register, which is an offset from the base register.
1080 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
1082 SmallVector<EVT, 4> AggValueVTs;
1083 ComputeValueVTs(TLI, AggTy, AggValueVTs);
1085 for (unsigned i = 0; i < VTIndex; i++)
1086 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1088 UpdateValueMap(EVI, ResultReg);
1093 FastISel::SelectOperator(const User *I, unsigned Opcode) {
1095 case Instruction::Add:
1096 return SelectBinaryOp(I, ISD::ADD);
1097 case Instruction::FAdd:
1098 return SelectBinaryOp(I, ISD::FADD);
1099 case Instruction::Sub:
1100 return SelectBinaryOp(I, ISD::SUB);
1101 case Instruction::FSub:
1102 // FNeg is currently represented in LLVM IR as a special case of FSub.
1103 if (BinaryOperator::isFNeg(I))
1104 return SelectFNeg(I);
1105 return SelectBinaryOp(I, ISD::FSUB);
1106 case Instruction::Mul:
1107 return SelectBinaryOp(I, ISD::MUL);
1108 case Instruction::FMul:
1109 return SelectBinaryOp(I, ISD::FMUL);
1110 case Instruction::SDiv:
1111 return SelectBinaryOp(I, ISD::SDIV);
1112 case Instruction::UDiv:
1113 return SelectBinaryOp(I, ISD::UDIV);
1114 case Instruction::FDiv:
1115 return SelectBinaryOp(I, ISD::FDIV);
1116 case Instruction::SRem:
1117 return SelectBinaryOp(I, ISD::SREM);
1118 case Instruction::URem:
1119 return SelectBinaryOp(I, ISD::UREM);
1120 case Instruction::FRem:
1121 return SelectBinaryOp(I, ISD::FREM);
1122 case Instruction::Shl:
1123 return SelectBinaryOp(I, ISD::SHL);
1124 case Instruction::LShr:
1125 return SelectBinaryOp(I, ISD::SRL);
1126 case Instruction::AShr:
1127 return SelectBinaryOp(I, ISD::SRA);
1128 case Instruction::And:
1129 return SelectBinaryOp(I, ISD::AND);
1130 case Instruction::Or:
1131 return SelectBinaryOp(I, ISD::OR);
1132 case Instruction::Xor:
1133 return SelectBinaryOp(I, ISD::XOR);
1135 case Instruction::GetElementPtr:
1136 return SelectGetElementPtr(I);
1138 case Instruction::Br: {
1139 const BranchInst *BI = cast<BranchInst>(I);
1141 if (BI->isUnconditional()) {
1142 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
1143 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
1144 FastEmitBranch(MSucc, BI->getDebugLoc());
1148 // Conditional branches are not handed yet.
1149 // Halt "fast" selection and bail.
1153 case Instruction::Unreachable:
1154 if (TM.Options.TrapUnreachable)
1155 return FastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
1159 case Instruction::Alloca:
1160 // FunctionLowering has the static-sized case covered.
1161 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
1164 // Dynamic-sized alloca is not handled yet.
1167 case Instruction::Call:
1168 return SelectCall(I);
1170 case Instruction::BitCast:
1171 return SelectBitCast(I);
1173 case Instruction::FPToSI:
1174 return SelectCast(I, ISD::FP_TO_SINT);
1175 case Instruction::ZExt:
1176 return SelectCast(I, ISD::ZERO_EXTEND);
1177 case Instruction::SExt:
1178 return SelectCast(I, ISD::SIGN_EXTEND);
1179 case Instruction::Trunc:
1180 return SelectCast(I, ISD::TRUNCATE);
1181 case Instruction::SIToFP:
1182 return SelectCast(I, ISD::SINT_TO_FP);
1184 case Instruction::IntToPtr: // Deliberate fall-through.
1185 case Instruction::PtrToInt: {
1186 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1187 EVT DstVT = TLI.getValueType(I->getType());
1188 if (DstVT.bitsGT(SrcVT))
1189 return SelectCast(I, ISD::ZERO_EXTEND);
1190 if (DstVT.bitsLT(SrcVT))
1191 return SelectCast(I, ISD::TRUNCATE);
1192 unsigned Reg = getRegForValue(I->getOperand(0));
1193 if (Reg == 0) return false;
1194 UpdateValueMap(I, Reg);
1198 case Instruction::ExtractValue:
1199 return SelectExtractValue(I);
1201 case Instruction::PHI:
1202 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1205 // Unhandled instruction. Halt "fast" selection and bail.
1210 FastISel::FastISel(FunctionLoweringInfo &funcInfo,
1211 const TargetLibraryInfo *libInfo)
1212 : FuncInfo(funcInfo),
1214 MRI(FuncInfo.MF->getRegInfo()),
1215 MFI(*FuncInfo.MF->getFrameInfo()),
1216 MCP(*FuncInfo.MF->getConstantPool()),
1217 TM(FuncInfo.MF->getTarget()),
1218 DL(*TM.getDataLayout()),
1219 TII(*TM.getInstrInfo()),
1220 TLI(*TM.getTargetLowering()),
1221 TRI(*TM.getRegisterInfo()),
1225 FastISel::~FastISel() {}
1227 bool FastISel::FastLowerArguments() {
1231 unsigned FastISel::FastEmit_(MVT, MVT,
1236 unsigned FastISel::FastEmit_r(MVT, MVT,
1238 unsigned /*Op0*/, bool /*Op0IsKill*/) {
1242 unsigned FastISel::FastEmit_rr(MVT, MVT,
1244 unsigned /*Op0*/, bool /*Op0IsKill*/,
1245 unsigned /*Op1*/, bool /*Op1IsKill*/) {
1249 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1253 unsigned FastISel::FastEmit_f(MVT, MVT,
1254 unsigned, const ConstantFP * /*FPImm*/) {
1258 unsigned FastISel::FastEmit_ri(MVT, MVT,
1260 unsigned /*Op0*/, bool /*Op0IsKill*/,
1265 unsigned FastISel::FastEmit_rf(MVT, MVT,
1267 unsigned /*Op0*/, bool /*Op0IsKill*/,
1268 const ConstantFP * /*FPImm*/) {
1272 unsigned FastISel::FastEmit_rri(MVT, MVT,
1274 unsigned /*Op0*/, bool /*Op0IsKill*/,
1275 unsigned /*Op1*/, bool /*Op1IsKill*/,
1280 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
1281 /// to emit an instruction with an immediate operand using FastEmit_ri.
1282 /// If that fails, it materializes the immediate into a register and try
1283 /// FastEmit_rr instead.
1284 unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode,
1285 unsigned Op0, bool Op0IsKill,
1286 uint64_t Imm, MVT ImmType) {
1287 // If this is a multiply by a power of two, emit this as a shift left.
1288 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1291 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1292 // div x, 8 -> srl x, 3
1297 // Horrible hack (to be removed), check to make sure shift amounts are
1299 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1300 Imm >= VT.getSizeInBits())
1303 // First check if immediate type is legal. If not, we can't use the ri form.
1304 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1307 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1308 if (MaterialReg == 0) {
1309 // This is a bit ugly/slow, but failing here means falling out of
1310 // fast-isel, which would be very slow.
1311 IntegerType *ITy = IntegerType::get(FuncInfo.Fn->getContext(),
1312 VT.getSizeInBits());
1313 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1314 assert (MaterialReg != 0 && "Unable to materialize imm.");
1315 if (MaterialReg == 0) return 0;
1317 return FastEmit_rr(VT, VT, Opcode,
1319 MaterialReg, /*Kill=*/true);
1322 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
1323 return MRI.createVirtualRegister(RC);
1326 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II,
1327 unsigned Op, unsigned OpNum) {
1328 if (TargetRegisterInfo::isVirtualRegister(Op)) {
1329 const TargetRegisterClass *RegClass =
1330 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
1331 if (!MRI.constrainRegClass(Op, RegClass)) {
1332 // If it's not legal to COPY between the register classes, something
1333 // has gone very wrong before we got here.
1334 unsigned NewOp = createResultReg(RegClass);
1335 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1336 TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
1343 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
1344 const TargetRegisterClass* RC) {
1345 unsigned ResultReg = createResultReg(RC);
1346 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1348 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
1352 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
1353 const TargetRegisterClass *RC,
1354 unsigned Op0, bool Op0IsKill) {
1355 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1357 unsigned ResultReg = createResultReg(RC);
1358 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1360 if (II.getNumDefs() >= 1)
1361 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1362 .addReg(Op0, Op0IsKill * RegState::Kill);
1364 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1365 .addReg(Op0, Op0IsKill * RegState::Kill);
1366 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1367 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1373 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
1374 const TargetRegisterClass *RC,
1375 unsigned Op0, bool Op0IsKill,
1376 unsigned Op1, bool Op1IsKill) {
1377 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1379 unsigned ResultReg = createResultReg(RC);
1380 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1381 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1383 if (II.getNumDefs() >= 1)
1384 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1385 .addReg(Op0, Op0IsKill * RegState::Kill)
1386 .addReg(Op1, Op1IsKill * RegState::Kill);
1388 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1389 .addReg(Op0, Op0IsKill * RegState::Kill)
1390 .addReg(Op1, Op1IsKill * RegState::Kill);
1391 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1392 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1397 unsigned FastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
1398 const TargetRegisterClass *RC,
1399 unsigned Op0, bool Op0IsKill,
1400 unsigned Op1, bool Op1IsKill,
1401 unsigned Op2, bool Op2IsKill) {
1402 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1404 unsigned ResultReg = createResultReg(RC);
1405 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1406 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1407 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
1409 if (II.getNumDefs() >= 1)
1410 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1411 .addReg(Op0, Op0IsKill * RegState::Kill)
1412 .addReg(Op1, Op1IsKill * RegState::Kill)
1413 .addReg(Op2, Op2IsKill * RegState::Kill);
1415 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1416 .addReg(Op0, Op0IsKill * RegState::Kill)
1417 .addReg(Op1, Op1IsKill * RegState::Kill)
1418 .addReg(Op2, Op2IsKill * RegState::Kill);
1419 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1420 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1425 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
1426 const TargetRegisterClass *RC,
1427 unsigned Op0, bool Op0IsKill,
1429 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1431 unsigned ResultReg = createResultReg(RC);
1432 RC = TII.getRegClass(II, II.getNumDefs(), &TRI, *FuncInfo.MF);
1433 MRI.constrainRegClass(Op0, RC);
1435 if (II.getNumDefs() >= 1)
1436 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1437 .addReg(Op0, Op0IsKill * RegState::Kill)
1440 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1441 .addReg(Op0, Op0IsKill * RegState::Kill)
1443 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1444 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1449 unsigned FastISel::FastEmitInst_rii(unsigned MachineInstOpcode,
1450 const TargetRegisterClass *RC,
1451 unsigned Op0, bool Op0IsKill,
1452 uint64_t Imm1, uint64_t Imm2) {
1453 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1455 unsigned ResultReg = createResultReg(RC);
1456 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1458 if (II.getNumDefs() >= 1)
1459 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1460 .addReg(Op0, Op0IsKill * RegState::Kill)
1464 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1465 .addReg(Op0, Op0IsKill * RegState::Kill)
1468 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1469 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1474 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
1475 const TargetRegisterClass *RC,
1476 unsigned Op0, bool Op0IsKill,
1477 const ConstantFP *FPImm) {
1478 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1480 unsigned ResultReg = createResultReg(RC);
1481 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1483 if (II.getNumDefs() >= 1)
1484 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1485 .addReg(Op0, Op0IsKill * RegState::Kill)
1488 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1489 .addReg(Op0, Op0IsKill * RegState::Kill)
1491 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1492 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1497 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
1498 const TargetRegisterClass *RC,
1499 unsigned Op0, bool Op0IsKill,
1500 unsigned Op1, bool Op1IsKill,
1502 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1504 unsigned ResultReg = createResultReg(RC);
1505 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1506 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1508 if (II.getNumDefs() >= 1)
1509 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1510 .addReg(Op0, Op0IsKill * RegState::Kill)
1511 .addReg(Op1, Op1IsKill * RegState::Kill)
1514 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1515 .addReg(Op0, Op0IsKill * RegState::Kill)
1516 .addReg(Op1, Op1IsKill * RegState::Kill)
1518 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1519 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1524 unsigned FastISel::FastEmitInst_rrii(unsigned MachineInstOpcode,
1525 const TargetRegisterClass *RC,
1526 unsigned Op0, bool Op0IsKill,
1527 unsigned Op1, bool Op1IsKill,
1528 uint64_t Imm1, uint64_t Imm2) {
1529 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1531 unsigned ResultReg = createResultReg(RC);
1532 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1533 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1535 if (II.getNumDefs() >= 1)
1536 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1537 .addReg(Op0, Op0IsKill * RegState::Kill)
1538 .addReg(Op1, Op1IsKill * RegState::Kill)
1539 .addImm(Imm1).addImm(Imm2);
1541 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1542 .addReg(Op0, Op0IsKill * RegState::Kill)
1543 .addReg(Op1, Op1IsKill * RegState::Kill)
1544 .addImm(Imm1).addImm(Imm2);
1545 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1546 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1551 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
1552 const TargetRegisterClass *RC,
1554 unsigned ResultReg = createResultReg(RC);
1555 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1557 if (II.getNumDefs() >= 1)
1558 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg).addImm(Imm);
1560 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm);
1561 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1562 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1567 unsigned FastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
1568 const TargetRegisterClass *RC,
1569 uint64_t Imm1, uint64_t Imm2) {
1570 unsigned ResultReg = createResultReg(RC);
1571 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1573 if (II.getNumDefs() >= 1)
1574 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1575 .addImm(Imm1).addImm(Imm2);
1577 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm1).addImm(Imm2);
1578 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1579 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1584 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
1585 unsigned Op0, bool Op0IsKill,
1587 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1588 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1589 "Cannot yet extract from physregs");
1590 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
1591 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
1592 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
1593 DbgLoc, TII.get(TargetOpcode::COPY), ResultReg)
1594 .addReg(Op0, getKillRegState(Op0IsKill), Idx);
1598 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1599 /// with all but the least significant bit set to zero.
1600 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1601 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
1604 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
1605 /// Emit code to ensure constants are copied into registers when needed.
1606 /// Remember the virtual registers that need to be added to the Machine PHI
1607 /// nodes as input. We cannot just directly add them, because expansion
1608 /// might result in multiple MBB's for one BB. As such, the start of the
1609 /// BB might correspond to a different MBB than the end.
1610 bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
1611 const TerminatorInst *TI = LLVMBB->getTerminator();
1613 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
1614 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
1616 // Check successor nodes' PHI nodes that expect a constant to be available
1618 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
1619 const BasicBlock *SuccBB = TI->getSuccessor(succ);
1620 if (!isa<PHINode>(SuccBB->begin())) continue;
1621 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
1623 // If this terminator has multiple identical successors (common for
1624 // switches), only handle each succ once.
1625 if (!SuccsHandled.insert(SuccMBB)) continue;
1627 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
1629 // At this point we know that there is a 1-1 correspondence between LLVM PHI
1630 // nodes and Machine PHI nodes, but the incoming operands have not been
1632 for (BasicBlock::const_iterator I = SuccBB->begin();
1633 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
1635 // Ignore dead phi's.
1636 if (PN->use_empty()) continue;
1638 // Only handle legal types. Two interesting things to note here. First,
1639 // by bailing out early, we may leave behind some dead instructions,
1640 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
1641 // own moves. Second, this check is necessary because FastISel doesn't
1642 // use CreateRegs to create registers, so it always creates
1643 // exactly one register for each non-void instruction.
1644 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
1645 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
1646 // Handle integer promotions, though, because they're common and easy.
1647 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
1648 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT);
1650 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
1655 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
1657 // Set the DebugLoc for the copy. Prefer the location of the operand
1658 // if there is one; use the location of the PHI otherwise.
1659 DbgLoc = PN->getDebugLoc();
1660 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp))
1661 DbgLoc = Inst->getDebugLoc();
1663 unsigned Reg = getRegForValue(PHIOp);
1665 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
1668 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
1669 DbgLoc = DebugLoc();
1676 bool FastISel::tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst) {
1677 assert(LI->hasOneUse() &&
1678 "tryToFoldLoad expected a LoadInst with a single use");
1679 // We know that the load has a single use, but don't know what it is. If it
1680 // isn't one of the folded instructions, then we can't succeed here. Handle
1681 // this by scanning the single-use users of the load until we get to FoldInst.
1682 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
1684 const Instruction *TheUser = LI->user_back();
1685 while (TheUser != FoldInst && // Scan up until we find FoldInst.
1686 // Stay in the right block.
1687 TheUser->getParent() == FoldInst->getParent() &&
1688 --MaxUsers) { // Don't scan too far.
1689 // If there are multiple or no uses of this instruction, then bail out.
1690 if (!TheUser->hasOneUse())
1693 TheUser = TheUser->user_back();
1696 // If we didn't find the fold instruction, then we failed to collapse the
1698 if (TheUser != FoldInst)
1701 // Don't try to fold volatile loads. Target has to deal with alignment
1703 if (LI->isVolatile())
1706 // Figure out which vreg this is going into. If there is no assigned vreg yet
1707 // then there actually was no reference to it. Perhaps the load is referenced
1708 // by a dead instruction.
1709 unsigned LoadReg = getRegForValue(LI);
1713 // We can't fold if this vreg has no uses or more than one use. Multiple uses
1714 // may mean that the instruction got lowered to multiple MIs, or the use of
1715 // the loaded value ended up being multiple operands of the result.
1716 if (!MRI.hasOneUse(LoadReg))
1719 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg);
1720 MachineInstr *User = RI->getParent();
1722 // Set the insertion point properly. Folding the load can cause generation of
1723 // other random instructions (like sign extends) for addressing modes; make
1724 // sure they get inserted in a logical place before the new instruction.
1725 FuncInfo.InsertPt = User;
1726 FuncInfo.MBB = User->getParent();
1728 // Ask the target to try folding the load.
1729 return tryToFoldLoadIntoMI(User, RI.getOperandNo(), LI);
1732 bool FastISel::canFoldAddIntoGEP(const User *GEP, const Value *Add) {
1734 if (!isa<AddOperator>(Add))
1736 // Type size needs to match.
1737 if (DL.getTypeSizeInBits(GEP->getType()) !=
1738 DL.getTypeSizeInBits(Add->getType()))
1740 // Must be in the same basic block.
1741 if (isa<Instruction>(Add) &&
1742 FuncInfo.MBBMap[cast<Instruction>(Add)->getParent()] != FuncInfo.MBB)
1744 // Must have a constant operand.
1745 return isa<ConstantInt>(cast<AddOperator>(Add)->getOperand(1));
1749 FastISel::createMachineMemOperandFor(const Instruction *I) const {
1756 if (const auto *LI = dyn_cast<LoadInst>(I)) {
1757 Alignment = LI->getAlignment();
1758 IsVolatile = LI->isVolatile();
1759 Flags = MachineMemOperand::MOLoad;
1760 Ptr = LI->getPointerOperand();
1761 ValTy = LI->getType();
1762 } else if (const auto *SI = dyn_cast<StoreInst>(I)) {
1763 Alignment = SI->getAlignment();
1764 IsVolatile = SI->isVolatile();
1765 Flags = MachineMemOperand::MOStore;
1766 Ptr = SI->getPointerOperand();
1767 ValTy = SI->getValueOperand()->getType();
1772 bool IsNonTemporal = I->getMetadata("nontemporal") != nullptr;
1773 bool IsInvariant = I->getMetadata("invariant.load") != nullptr;
1774 const MDNode *TBAAInfo = I->getMetadata(LLVMContext::MD_tbaa);
1775 const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range);
1777 if (Alignment == 0) // Ensure that codegen never sees alignment 0.
1778 Alignment = DL.getABITypeAlignment(ValTy);
1780 unsigned Size = TM.getDataLayout()->getTypeStoreSize(ValTy);
1783 Flags |= MachineMemOperand::MOVolatile;
1785 Flags |= MachineMemOperand::MONonTemporal;
1787 Flags |= MachineMemOperand::MOInvariant;
1789 return FuncInfo.MF->getMachineMemOperand(MachinePointerInfo(Ptr), Flags, Size,
1790 Alignment, TBAAInfo, Ranges);