1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/LLVMContext.h"
47 #include "llvm/CodeGen/FastISel.h"
48 #include "llvm/CodeGen/MachineInstrBuilder.h"
49 #include "llvm/CodeGen/MachineModuleInfo.h"
50 #include "llvm/CodeGen/MachineRegisterInfo.h"
51 #include "llvm/CodeGen/DwarfWriter.h"
52 #include "llvm/Analysis/DebugInfo.h"
53 #include "llvm/Target/TargetData.h"
54 #include "llvm/Target/TargetInstrInfo.h"
55 #include "llvm/Target/TargetLowering.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "SelectionDAGBuilder.h"
58 #include "FunctionLoweringInfo.h"
61 unsigned FastISel::getRegForValue(Value *V) {
62 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
63 // Don't handle non-simple values in FastISel.
64 if (!RealVT.isSimple())
67 // Ignore illegal types. We must do this before looking up the value
68 // in ValueMap because Arguments are given virtual registers regardless
69 // of whether FastISel can handle them.
70 MVT VT = RealVT.getSimpleVT();
71 if (!TLI.isTypeLegal(VT)) {
72 // Promote MVT::i1 to a legal type though, because it's common and easy.
74 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
79 // Look up the value to see if we already have a register for it. We
80 // cache values defined by Instructions across blocks, and other values
81 // only locally. This is because Instructions already have the SSA
82 // def-dominatess-use requirement enforced.
83 if (ValueMap.count(V))
85 unsigned Reg = LocalValueMap[V];
89 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
90 if (CI->getValue().getActiveBits() <= 64)
91 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
92 } else if (isa<AllocaInst>(V)) {
93 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
94 } else if (isa<ConstantPointerNull>(V)) {
95 // Translate this as an integer zero so that it can be
96 // local-CSE'd with actual integer zeros.
98 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
99 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
100 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
103 const APFloat &Flt = CF->getValueAPF();
104 EVT IntVT = TLI.getPointerTy();
107 uint32_t IntBitWidth = IntVT.getSizeInBits();
109 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
110 APFloat::rmTowardZero, &isExact);
112 APInt IntVal(IntBitWidth, 2, x);
114 unsigned IntegerReg =
115 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
117 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
120 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
121 if (!SelectOperator(CE, CE->getOpcode())) return 0;
122 Reg = LocalValueMap[CE];
123 } else if (isa<UndefValue>(V)) {
124 Reg = createResultReg(TLI.getRegClassFor(VT));
125 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
128 // If target-independent code couldn't handle the value, give target-specific
130 if (!Reg && isa<Constant>(V))
131 Reg = TargetMaterializeConstant(cast<Constant>(V));
133 // Don't cache constant materializations in the general ValueMap.
134 // To do so would require tracking what uses they dominate.
136 LocalValueMap[V] = Reg;
140 unsigned FastISel::lookUpRegForValue(Value *V) {
141 // Look up the value to see if we already have a register for it. We
142 // cache values defined by Instructions across blocks, and other values
143 // only locally. This is because Instructions already have the SSA
144 // def-dominatess-use requirement enforced.
145 if (ValueMap.count(V))
147 return LocalValueMap[V];
150 /// UpdateValueMap - Update the value map to include the new mapping for this
151 /// instruction, or insert an extra copy to get the result in a previous
152 /// determined register.
153 /// NOTE: This is only necessary because we might select a block that uses
154 /// a value before we select the block that defines the value. It might be
155 /// possible to fix this by selecting blocks in reverse postorder.
156 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
157 if (!isa<Instruction>(I)) {
158 LocalValueMap[I] = Reg;
162 unsigned &AssignedReg = ValueMap[I];
163 if (AssignedReg == 0)
165 else if (Reg != AssignedReg) {
166 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
167 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
168 Reg, RegClass, RegClass);
173 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
174 unsigned IdxN = getRegForValue(Idx);
176 // Unhandled operand. Halt "fast" selection and bail.
179 // If the index is smaller or larger than intptr_t, truncate or extend it.
180 MVT PtrVT = TLI.getPointerTy();
181 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
182 if (IdxVT.bitsLT(PtrVT))
183 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
184 else if (IdxVT.bitsGT(PtrVT))
185 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
189 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
190 /// which has an opcode which directly corresponds to the given ISD opcode.
192 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
193 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
194 if (VT == MVT::Other || !VT.isSimple())
195 // Unhandled type. Halt "fast" selection and bail.
198 // We only handle legal types. For example, on x86-32 the instruction
199 // selector contains all of the 64-bit instructions from x86-64,
200 // under the assumption that i64 won't be used if the target doesn't
202 if (!TLI.isTypeLegal(VT)) {
203 // MVT::i1 is special. Allow AND, OR, or XOR because they
204 // don't require additional zeroing, which makes them easy.
206 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
207 ISDOpcode == ISD::XOR))
208 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
213 unsigned Op0 = getRegForValue(I->getOperand(0));
215 // Unhandled operand. Halt "fast" selection and bail.
218 // Check if the second operand is a constant and handle it appropriately.
219 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
220 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
221 ISDOpcode, Op0, CI->getZExtValue());
222 if (ResultReg != 0) {
223 // We successfully emitted code for the given LLVM Instruction.
224 UpdateValueMap(I, ResultReg);
229 // Check if the second operand is a constant float.
230 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
231 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
233 if (ResultReg != 0) {
234 // We successfully emitted code for the given LLVM Instruction.
235 UpdateValueMap(I, ResultReg);
240 unsigned Op1 = getRegForValue(I->getOperand(1));
242 // Unhandled operand. Halt "fast" selection and bail.
245 // Now we have both operands in registers. Emit the instruction.
246 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
247 ISDOpcode, Op0, Op1);
249 // Target-specific code wasn't able to find a machine opcode for
250 // the given ISD opcode and type. Halt "fast" selection and bail.
253 // We successfully emitted code for the given LLVM Instruction.
254 UpdateValueMap(I, ResultReg);
258 bool FastISel::SelectGetElementPtr(User *I) {
259 unsigned N = getRegForValue(I->getOperand(0));
261 // Unhandled operand. Halt "fast" selection and bail.
264 const Type *Ty = I->getOperand(0)->getType();
265 MVT VT = TLI.getPointerTy();
266 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
269 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
270 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
273 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
274 // FIXME: This can be optimized by combining the add with a
276 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
278 // Unhandled operand. Halt "fast" selection and bail.
281 Ty = StTy->getElementType(Field);
283 Ty = cast<SequentialType>(Ty)->getElementType();
285 // If this is a constant subscript, handle it quickly.
286 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
287 if (CI->getZExtValue() == 0) continue;
289 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
290 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
292 // Unhandled operand. Halt "fast" selection and bail.
297 // N = N + Idx * ElementSize;
298 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
299 unsigned IdxN = getRegForGEPIndex(Idx);
301 // Unhandled operand. Halt "fast" selection and bail.
304 if (ElementSize != 1) {
305 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
307 // Unhandled operand. Halt "fast" selection and bail.
310 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
312 // Unhandled operand. Halt "fast" selection and bail.
317 // We successfully emitted code for the given LLVM Instruction.
318 UpdateValueMap(I, N);
322 bool FastISel::SelectCall(User *I) {
323 Function *F = cast<CallInst>(I)->getCalledFunction();
324 if (!F) return false;
326 unsigned IID = F->getIntrinsicID();
329 case Intrinsic::dbg_stoppoint:
330 case Intrinsic::dbg_region_start:
331 case Intrinsic::dbg_region_end:
332 case Intrinsic::dbg_func_start:
333 // FIXME - Remove this instructions once the dust settles.
335 case Intrinsic::dbg_declare: {
336 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
337 if (!isValidDebugInfoIntrinsic(*DI, CodeGenOpt::None) || !DW
338 || !DW->ShouldEmitDwarfDebug())
341 Value *Address = DI->getAddress();
342 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
343 Address = BCI->getOperand(0);
344 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
345 // Don't handle byval struct arguments or VLAs, for example.
347 DenseMap<const AllocaInst*, int>::iterator SI =
348 StaticAllocaMap.find(AI);
349 if (SI == StaticAllocaMap.end()) break; // VLAs.
352 MetadataContext &TheMetadata =
353 DI->getParent()->getContext().getMetadata();
354 unsigned MDDbgKind = TheMetadata.getMDKind("dbg");
355 MDNode *Dbg = TheMetadata.getMD(MDDbgKind, DI);
356 MMI->setVariableDbgInfo(DI->getVariable(), FI, Dbg);
360 case Intrinsic::eh_exception: {
361 EVT VT = TLI.getValueType(I->getType());
362 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
364 case TargetLowering::Expand: {
365 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
366 unsigned Reg = TLI.getExceptionAddressRegister();
367 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
368 unsigned ResultReg = createResultReg(RC);
369 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
371 assert(InsertedCopy && "Can't copy address registers!");
372 InsertedCopy = InsertedCopy;
373 UpdateValueMap(I, ResultReg);
379 case Intrinsic::eh_selector: {
380 EVT VT = TLI.getValueType(I->getType());
381 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
383 case TargetLowering::Expand: {
385 if (MBB->isLandingPad())
386 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
389 CatchInfoLost.insert(cast<CallInst>(I));
391 // FIXME: Mark exception selector register as live in. Hack for PR1508.
392 unsigned Reg = TLI.getExceptionSelectorRegister();
393 if (Reg) MBB->addLiveIn(Reg);
396 unsigned Reg = TLI.getExceptionSelectorRegister();
397 EVT SrcVT = TLI.getPointerTy();
398 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
399 unsigned ResultReg = createResultReg(RC);
400 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
402 assert(InsertedCopy && "Can't copy address registers!");
403 InsertedCopy = InsertedCopy;
405 // Cast the register to the type of the selector.
406 if (SrcVT.bitsGT(MVT::i32))
407 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
409 else if (SrcVT.bitsLT(MVT::i32))
410 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
411 ISD::SIGN_EXTEND, ResultReg);
413 // Unhandled operand. Halt "fast" selection and bail.
416 UpdateValueMap(I, ResultReg);
419 getRegForValue(Constant::getNullValue(I->getType()));
420 UpdateValueMap(I, ResultReg);
431 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
432 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
433 EVT DstVT = TLI.getValueType(I->getType());
435 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
436 DstVT == MVT::Other || !DstVT.isSimple())
437 // Unhandled type. Halt "fast" selection and bail.
440 // Check if the destination type is legal. Or as a special case,
441 // it may be i1 if we're doing a truncate because that's
442 // easy and somewhat common.
443 if (!TLI.isTypeLegal(DstVT))
444 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
445 // Unhandled type. Halt "fast" selection and bail.
448 // Check if the source operand is legal. Or as a special case,
449 // it may be i1 if we're doing zero-extension because that's
450 // easy and somewhat common.
451 if (!TLI.isTypeLegal(SrcVT))
452 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
453 // Unhandled type. Halt "fast" selection and bail.
456 unsigned InputReg = getRegForValue(I->getOperand(0));
458 // Unhandled operand. Halt "fast" selection and bail.
461 // If the operand is i1, arrange for the high bits in the register to be zero.
462 if (SrcVT == MVT::i1) {
463 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
464 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
468 // If the result is i1, truncate to the target's type for i1 first.
469 if (DstVT == MVT::i1)
470 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
472 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
479 UpdateValueMap(I, ResultReg);
483 bool FastISel::SelectBitCast(User *I) {
484 // If the bitcast doesn't change the type, just use the operand value.
485 if (I->getType() == I->getOperand(0)->getType()) {
486 unsigned Reg = getRegForValue(I->getOperand(0));
489 UpdateValueMap(I, Reg);
493 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
494 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
495 EVT DstVT = TLI.getValueType(I->getType());
497 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
498 DstVT == MVT::Other || !DstVT.isSimple() ||
499 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
500 // Unhandled type. Halt "fast" selection and bail.
503 unsigned Op0 = getRegForValue(I->getOperand(0));
505 // Unhandled operand. Halt "fast" selection and bail.
508 // First, try to perform the bitcast by inserting a reg-reg copy.
509 unsigned ResultReg = 0;
510 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
511 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
512 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
513 ResultReg = createResultReg(DstClass);
515 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
516 Op0, DstClass, SrcClass);
521 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
523 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
524 ISD::BIT_CONVERT, Op0);
529 UpdateValueMap(I, ResultReg);
534 FastISel::SelectInstruction(Instruction *I) {
535 // First, try doing target-independent selection.
536 if (SelectOperator(I, I->getOpcode()))
539 // Next, try calling the target to attempt to handle the instruction.
540 if (TargetSelectInstruction(I))
546 /// FastEmitBranch - Emit an unconditional branch to the given block,
547 /// unless it is the immediate (fall-through) successor, and update
550 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
551 MachineFunction::iterator NextMBB =
552 llvm::next(MachineFunction::iterator(MBB));
554 if (MBB->isLayoutSuccessor(MSucc)) {
555 // The unconditional fall-through case, which needs no instructions.
557 // The unconditional branch case.
558 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
560 MBB->addSuccessor(MSucc);
563 /// SelectFNeg - Emit an FNeg operation.
566 FastISel::SelectFNeg(User *I) {
567 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
568 if (OpReg == 0) return false;
570 // If the target has ISD::FNEG, use it.
571 EVT VT = TLI.getValueType(I->getType());
572 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
574 if (ResultReg != 0) {
575 UpdateValueMap(I, ResultReg);
579 // Bitcast the value to integer, twiddle the sign bit with xor,
580 // and then bitcast it back to floating-point.
581 if (VT.getSizeInBits() > 64) return false;
582 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
583 if (!TLI.isTypeLegal(IntVT))
586 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
587 ISD::BIT_CONVERT, OpReg);
591 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
592 UINT64_C(1) << (VT.getSizeInBits()-1),
593 IntVT.getSimpleVT());
594 if (IntResultReg == 0)
597 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
598 ISD::BIT_CONVERT, IntResultReg);
602 UpdateValueMap(I, ResultReg);
607 FastISel::SelectOperator(User *I, unsigned Opcode) {
609 case Instruction::Add:
610 return SelectBinaryOp(I, ISD::ADD);
611 case Instruction::FAdd:
612 return SelectBinaryOp(I, ISD::FADD);
613 case Instruction::Sub:
614 return SelectBinaryOp(I, ISD::SUB);
615 case Instruction::FSub:
616 // FNeg is currently represented in LLVM IR as a special case of FSub.
617 if (BinaryOperator::isFNeg(I))
618 return SelectFNeg(I);
619 return SelectBinaryOp(I, ISD::FSUB);
620 case Instruction::Mul:
621 return SelectBinaryOp(I, ISD::MUL);
622 case Instruction::FMul:
623 return SelectBinaryOp(I, ISD::FMUL);
624 case Instruction::SDiv:
625 return SelectBinaryOp(I, ISD::SDIV);
626 case Instruction::UDiv:
627 return SelectBinaryOp(I, ISD::UDIV);
628 case Instruction::FDiv:
629 return SelectBinaryOp(I, ISD::FDIV);
630 case Instruction::SRem:
631 return SelectBinaryOp(I, ISD::SREM);
632 case Instruction::URem:
633 return SelectBinaryOp(I, ISD::UREM);
634 case Instruction::FRem:
635 return SelectBinaryOp(I, ISD::FREM);
636 case Instruction::Shl:
637 return SelectBinaryOp(I, ISD::SHL);
638 case Instruction::LShr:
639 return SelectBinaryOp(I, ISD::SRL);
640 case Instruction::AShr:
641 return SelectBinaryOp(I, ISD::SRA);
642 case Instruction::And:
643 return SelectBinaryOp(I, ISD::AND);
644 case Instruction::Or:
645 return SelectBinaryOp(I, ISD::OR);
646 case Instruction::Xor:
647 return SelectBinaryOp(I, ISD::XOR);
649 case Instruction::GetElementPtr:
650 return SelectGetElementPtr(I);
652 case Instruction::Br: {
653 BranchInst *BI = cast<BranchInst>(I);
655 if (BI->isUnconditional()) {
656 BasicBlock *LLVMSucc = BI->getSuccessor(0);
657 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
658 FastEmitBranch(MSucc);
662 // Conditional branches are not handed yet.
663 // Halt "fast" selection and bail.
667 case Instruction::Unreachable:
671 case Instruction::PHI:
672 // PHI nodes are already emitted.
675 case Instruction::Alloca:
676 // FunctionLowering has the static-sized case covered.
677 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
680 // Dynamic-sized alloca is not handled yet.
683 case Instruction::Call:
684 return SelectCall(I);
686 case Instruction::BitCast:
687 return SelectBitCast(I);
689 case Instruction::FPToSI:
690 return SelectCast(I, ISD::FP_TO_SINT);
691 case Instruction::ZExt:
692 return SelectCast(I, ISD::ZERO_EXTEND);
693 case Instruction::SExt:
694 return SelectCast(I, ISD::SIGN_EXTEND);
695 case Instruction::Trunc:
696 return SelectCast(I, ISD::TRUNCATE);
697 case Instruction::SIToFP:
698 return SelectCast(I, ISD::SINT_TO_FP);
700 case Instruction::IntToPtr: // Deliberate fall-through.
701 case Instruction::PtrToInt: {
702 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
703 EVT DstVT = TLI.getValueType(I->getType());
704 if (DstVT.bitsGT(SrcVT))
705 return SelectCast(I, ISD::ZERO_EXTEND);
706 if (DstVT.bitsLT(SrcVT))
707 return SelectCast(I, ISD::TRUNCATE);
708 unsigned Reg = getRegForValue(I->getOperand(0));
709 if (Reg == 0) return false;
710 UpdateValueMap(I, Reg);
715 // Unhandled instruction. Halt "fast" selection and bail.
720 FastISel::FastISel(MachineFunction &mf,
721 MachineModuleInfo *mmi,
723 DenseMap<const Value *, unsigned> &vm,
724 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
725 DenseMap<const AllocaInst *, int> &am
727 , SmallSet<Instruction*, 8> &cil
740 MRI(MF.getRegInfo()),
741 MFI(*MF.getFrameInfo()),
742 MCP(*MF.getConstantPool()),
744 TD(*TM.getTargetData()),
745 TII(*TM.getInstrInfo()),
746 TLI(*TM.getTargetLowering()) {
749 FastISel::~FastISel() {}
751 unsigned FastISel::FastEmit_(MVT, MVT,
756 unsigned FastISel::FastEmit_r(MVT, MVT,
757 ISD::NodeType, unsigned /*Op0*/) {
761 unsigned FastISel::FastEmit_rr(MVT, MVT,
762 ISD::NodeType, unsigned /*Op0*/,
767 unsigned FastISel::FastEmit_i(MVT, MVT, ISD::NodeType, uint64_t /*Imm*/) {
771 unsigned FastISel::FastEmit_f(MVT, MVT,
772 ISD::NodeType, ConstantFP * /*FPImm*/) {
776 unsigned FastISel::FastEmit_ri(MVT, MVT,
777 ISD::NodeType, unsigned /*Op0*/,
782 unsigned FastISel::FastEmit_rf(MVT, MVT,
783 ISD::NodeType, unsigned /*Op0*/,
784 ConstantFP * /*FPImm*/) {
788 unsigned FastISel::FastEmit_rri(MVT, MVT,
790 unsigned /*Op0*/, unsigned /*Op1*/,
795 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
796 /// to emit an instruction with an immediate operand using FastEmit_ri.
797 /// If that fails, it materializes the immediate into a register and try
798 /// FastEmit_rr instead.
799 unsigned FastISel::FastEmit_ri_(MVT VT, ISD::NodeType Opcode,
800 unsigned Op0, uint64_t Imm,
802 // First check if immediate type is legal. If not, we can't use the ri form.
803 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
806 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
807 if (MaterialReg == 0)
809 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
812 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
813 /// to emit an instruction with a floating-point immediate operand using
814 /// FastEmit_rf. If that fails, it materializes the immediate into a register
815 /// and try FastEmit_rr instead.
816 unsigned FastISel::FastEmit_rf_(MVT VT, ISD::NodeType Opcode,
817 unsigned Op0, ConstantFP *FPImm,
819 // First check if immediate type is legal. If not, we can't use the rf form.
820 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
824 // Materialize the constant in a register.
825 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
826 if (MaterialReg == 0) {
827 // If the target doesn't have a way to directly enter a floating-point
828 // value into a register, use an alternate approach.
829 // TODO: The current approach only supports floating-point constants
830 // that can be constructed by conversion from integer values. This should
831 // be replaced by code that creates a load from a constant-pool entry,
832 // which will require some target-specific work.
833 const APFloat &Flt = FPImm->getValueAPF();
834 EVT IntVT = TLI.getPointerTy();
837 uint32_t IntBitWidth = IntVT.getSizeInBits();
839 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
840 APFloat::rmTowardZero, &isExact);
843 APInt IntVal(IntBitWidth, 2, x);
845 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
846 ISD::Constant, IntVal.getZExtValue());
849 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
850 ISD::SINT_TO_FP, IntegerReg);
851 if (MaterialReg == 0)
854 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
857 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
858 return MRI.createVirtualRegister(RC);
861 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
862 const TargetRegisterClass* RC) {
863 unsigned ResultReg = createResultReg(RC);
864 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
866 BuildMI(MBB, DL, II, ResultReg);
870 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
871 const TargetRegisterClass *RC,
873 unsigned ResultReg = createResultReg(RC);
874 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
876 if (II.getNumDefs() >= 1)
877 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
879 BuildMI(MBB, DL, II).addReg(Op0);
880 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
881 II.ImplicitDefs[0], RC, RC);
889 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
890 const TargetRegisterClass *RC,
891 unsigned Op0, unsigned Op1) {
892 unsigned ResultReg = createResultReg(RC);
893 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
895 if (II.getNumDefs() >= 1)
896 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
898 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
899 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
900 II.ImplicitDefs[0], RC, RC);
907 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
908 const TargetRegisterClass *RC,
909 unsigned Op0, uint64_t Imm) {
910 unsigned ResultReg = createResultReg(RC);
911 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
913 if (II.getNumDefs() >= 1)
914 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
916 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
917 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
918 II.ImplicitDefs[0], RC, RC);
925 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
926 const TargetRegisterClass *RC,
927 unsigned Op0, ConstantFP *FPImm) {
928 unsigned ResultReg = createResultReg(RC);
929 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
931 if (II.getNumDefs() >= 1)
932 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
934 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
935 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
936 II.ImplicitDefs[0], RC, RC);
943 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
944 const TargetRegisterClass *RC,
945 unsigned Op0, unsigned Op1, uint64_t Imm) {
946 unsigned ResultReg = createResultReg(RC);
947 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
949 if (II.getNumDefs() >= 1)
950 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
952 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
953 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
954 II.ImplicitDefs[0], RC, RC);
961 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
962 const TargetRegisterClass *RC,
964 unsigned ResultReg = createResultReg(RC);
965 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
967 if (II.getNumDefs() >= 1)
968 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
970 BuildMI(MBB, DL, II).addImm(Imm);
971 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
972 II.ImplicitDefs[0], RC, RC);
979 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
980 unsigned Op0, uint32_t Idx) {
981 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
983 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
984 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
986 if (II.getNumDefs() >= 1)
987 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
989 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
990 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
991 II.ImplicitDefs[0], RC, RC);
998 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
999 /// with all but the least significant bit set to zero.
1000 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
1001 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);