1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/DwarfWriter.h"
51 #include "llvm/Analysis/DebugInfo.h"
52 #include "llvm/Target/TargetData.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "SelectionDAGBuilder.h"
57 #include "FunctionLoweringInfo.h"
60 unsigned FastISel::getRegForValue(Value *V) {
61 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
62 // Don't handle non-simple values in FastISel.
63 if (!RealVT.isSimple())
66 // Ignore illegal types. We must do this before looking up the value
67 // in ValueMap because Arguments are given virtual registers regardless
68 // of whether FastISel can handle them.
69 MVT VT = RealVT.getSimpleVT();
70 if (!TLI.isTypeLegal(VT)) {
71 // Promote MVT::i1 to a legal type though, because it's common and easy.
73 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
78 // Look up the value to see if we already have a register for it. We
79 // cache values defined by Instructions across blocks, and other values
80 // only locally. This is because Instructions already have the SSA
81 // def-dominates-use requirement enforced.
82 if (ValueMap.count(V))
84 unsigned Reg = LocalValueMap[V];
88 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
89 if (CI->getValue().getActiveBits() <= 64)
90 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
91 } else if (isa<AllocaInst>(V)) {
92 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
93 } else if (isa<ConstantPointerNull>(V)) {
94 // Translate this as an integer zero so that it can be
95 // local-CSE'd with actual integer zeros.
97 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
98 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
99 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
102 const APFloat &Flt = CF->getValueAPF();
103 EVT IntVT = TLI.getPointerTy();
106 uint32_t IntBitWidth = IntVT.getSizeInBits();
108 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
109 APFloat::rmTowardZero, &isExact);
111 APInt IntVal(IntBitWidth, 2, x);
113 unsigned IntegerReg =
114 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
116 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
119 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
120 if (!SelectOperator(CE, CE->getOpcode())) return 0;
121 Reg = LocalValueMap[CE];
122 } else if (isa<UndefValue>(V)) {
123 Reg = createResultReg(TLI.getRegClassFor(VT));
124 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
127 // If target-independent code couldn't handle the value, give target-specific
129 if (!Reg && isa<Constant>(V))
130 Reg = TargetMaterializeConstant(cast<Constant>(V));
132 // Don't cache constant materializations in the general ValueMap.
133 // To do so would require tracking what uses they dominate.
135 LocalValueMap[V] = Reg;
139 unsigned FastISel::lookUpRegForValue(Value *V) {
140 // Look up the value to see if we already have a register for it. We
141 // cache values defined by Instructions across blocks, and other values
142 // only locally. This is because Instructions already have the SSA
143 // def-dominatess-use requirement enforced.
144 if (ValueMap.count(V))
146 return LocalValueMap[V];
149 /// UpdateValueMap - Update the value map to include the new mapping for this
150 /// instruction, or insert an extra copy to get the result in a previous
151 /// determined register.
152 /// NOTE: This is only necessary because we might select a block that uses
153 /// a value before we select the block that defines the value. It might be
154 /// possible to fix this by selecting blocks in reverse postorder.
155 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
156 if (!isa<Instruction>(I)) {
157 LocalValueMap[I] = Reg;
161 unsigned &AssignedReg = ValueMap[I];
162 if (AssignedReg == 0)
164 else if (Reg != AssignedReg) {
165 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
166 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
167 Reg, RegClass, RegClass);
172 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
173 unsigned IdxN = getRegForValue(Idx);
175 // Unhandled operand. Halt "fast" selection and bail.
178 // If the index is smaller or larger than intptr_t, truncate or extend it.
179 MVT PtrVT = TLI.getPointerTy();
180 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
181 if (IdxVT.bitsLT(PtrVT))
182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
183 else if (IdxVT.bitsGT(PtrVT))
184 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
188 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
189 /// which has an opcode which directly corresponds to the given ISD opcode.
191 bool FastISel::SelectBinaryOp(User *I, unsigned ISDOpcode) {
192 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
193 if (VT == MVT::Other || !VT.isSimple())
194 // Unhandled type. Halt "fast" selection and bail.
197 // We only handle legal types. For example, on x86-32 the instruction
198 // selector contains all of the 64-bit instructions from x86-64,
199 // under the assumption that i64 won't be used if the target doesn't
201 if (!TLI.isTypeLegal(VT)) {
202 // MVT::i1 is special. Allow AND, OR, or XOR because they
203 // don't require additional zeroing, which makes them easy.
205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
206 ISDOpcode == ISD::XOR))
207 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
212 unsigned Op0 = getRegForValue(I->getOperand(0));
214 // Unhandled operand. Halt "fast" selection and bail.
217 // Check if the second operand is a constant and handle it appropriately.
218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
220 ISDOpcode, Op0, CI->getZExtValue());
221 if (ResultReg != 0) {
222 // We successfully emitted code for the given LLVM Instruction.
223 UpdateValueMap(I, ResultReg);
228 // Check if the second operand is a constant float.
229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
232 if (ResultReg != 0) {
233 // We successfully emitted code for the given LLVM Instruction.
234 UpdateValueMap(I, ResultReg);
239 unsigned Op1 = getRegForValue(I->getOperand(1));
241 // Unhandled operand. Halt "fast" selection and bail.
244 // Now we have both operands in registers. Emit the instruction.
245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
246 ISDOpcode, Op0, Op1);
248 // Target-specific code wasn't able to find a machine opcode for
249 // the given ISD opcode and type. Halt "fast" selection and bail.
252 // We successfully emitted code for the given LLVM Instruction.
253 UpdateValueMap(I, ResultReg);
257 bool FastISel::SelectGetElementPtr(User *I) {
258 unsigned N = getRegForValue(I->getOperand(0));
260 // Unhandled operand. Halt "fast" selection and bail.
263 const Type *Ty = I->getOperand(0)->getType();
264 MVT VT = TLI.getPointerTy();
265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
273 // FIXME: This can be optimized by combining the add with a
275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
277 // Unhandled operand. Halt "fast" selection and bail.
280 Ty = StTy->getElementType(Field);
282 Ty = cast<SequentialType>(Ty)->getElementType();
284 // If this is a constant subscript, handle it quickly.
285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
286 if (CI->getZExtValue() == 0) continue;
288 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
291 // Unhandled operand. Halt "fast" selection and bail.
296 // N = N + Idx * ElementSize;
297 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
298 unsigned IdxN = getRegForGEPIndex(Idx);
300 // Unhandled operand. Halt "fast" selection and bail.
303 if (ElementSize != 1) {
304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
306 // Unhandled operand. Halt "fast" selection and bail.
309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
311 // Unhandled operand. Halt "fast" selection and bail.
316 // We successfully emitted code for the given LLVM Instruction.
317 UpdateValueMap(I, N);
321 bool FastISel::SelectCall(User *I) {
322 Function *F = cast<CallInst>(I)->getCalledFunction();
323 if (!F) return false;
325 unsigned IID = F->getIntrinsicID();
328 case Intrinsic::dbg_declare: {
329 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
330 if (!DIDescriptor::ValidDebugInfo(DI->getVariable(), CodeGenOpt::None)||!DW
331 || !DW->ShouldEmitDwarfDebug())
334 Value *Address = DI->getAddress();
337 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
338 // Don't handle byval struct arguments or VLAs, for example.
340 DenseMap<const AllocaInst*, int>::iterator SI =
341 StaticAllocaMap.find(AI);
342 if (SI == StaticAllocaMap.end()) break; // VLAs.
345 if (MDNode *Dbg = DI->getMetadata("dbg"))
346 MMI->setVariableDbgInfo(DI->getVariable(), FI, Dbg);
348 // Building the map above is target independent. Generating DEBUG_VALUE
349 // inline is target dependent; do this now.
350 (void)TargetSelectInstruction(cast<Instruction>(I));
353 case Intrinsic::eh_exception: {
354 EVT VT = TLI.getValueType(I->getType());
355 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
357 case TargetLowering::Expand: {
358 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
359 unsigned Reg = TLI.getExceptionAddressRegister();
360 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
361 unsigned ResultReg = createResultReg(RC);
362 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
364 assert(InsertedCopy && "Can't copy address registers!");
365 InsertedCopy = InsertedCopy;
366 UpdateValueMap(I, ResultReg);
372 case Intrinsic::eh_selector: {
373 EVT VT = TLI.getValueType(I->getType());
374 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
376 case TargetLowering::Expand: {
378 if (MBB->isLandingPad())
379 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
382 CatchInfoLost.insert(cast<CallInst>(I));
384 // FIXME: Mark exception selector register as live in. Hack for PR1508.
385 unsigned Reg = TLI.getExceptionSelectorRegister();
386 if (Reg) MBB->addLiveIn(Reg);
389 unsigned Reg = TLI.getExceptionSelectorRegister();
390 EVT SrcVT = TLI.getPointerTy();
391 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
392 unsigned ResultReg = createResultReg(RC);
393 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
395 assert(InsertedCopy && "Can't copy address registers!");
396 InsertedCopy = InsertedCopy;
398 // Cast the register to the type of the selector.
399 if (SrcVT.bitsGT(MVT::i32))
400 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
402 else if (SrcVT.bitsLT(MVT::i32))
403 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
404 ISD::SIGN_EXTEND, ResultReg);
406 // Unhandled operand. Halt "fast" selection and bail.
409 UpdateValueMap(I, ResultReg);
412 getRegForValue(Constant::getNullValue(I->getType()));
413 UpdateValueMap(I, ResultReg);
424 bool FastISel::SelectCast(User *I, unsigned Opcode) {
425 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
426 EVT DstVT = TLI.getValueType(I->getType());
428 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
429 DstVT == MVT::Other || !DstVT.isSimple())
430 // Unhandled type. Halt "fast" selection and bail.
433 // Check if the destination type is legal. Or as a special case,
434 // it may be i1 if we're doing a truncate because that's
435 // easy and somewhat common.
436 if (!TLI.isTypeLegal(DstVT))
437 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
438 // Unhandled type. Halt "fast" selection and bail.
441 // Check if the source operand is legal. Or as a special case,
442 // it may be i1 if we're doing zero-extension because that's
443 // easy and somewhat common.
444 if (!TLI.isTypeLegal(SrcVT))
445 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
446 // Unhandled type. Halt "fast" selection and bail.
449 unsigned InputReg = getRegForValue(I->getOperand(0));
451 // Unhandled operand. Halt "fast" selection and bail.
454 // If the operand is i1, arrange for the high bits in the register to be zero.
455 if (SrcVT == MVT::i1) {
456 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
457 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
461 // If the result is i1, truncate to the target's type for i1 first.
462 if (DstVT == MVT::i1)
463 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
465 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
472 UpdateValueMap(I, ResultReg);
476 bool FastISel::SelectBitCast(User *I) {
477 // If the bitcast doesn't change the type, just use the operand value.
478 if (I->getType() == I->getOperand(0)->getType()) {
479 unsigned Reg = getRegForValue(I->getOperand(0));
482 UpdateValueMap(I, Reg);
486 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
487 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
488 EVT DstVT = TLI.getValueType(I->getType());
490 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
491 DstVT == MVT::Other || !DstVT.isSimple() ||
492 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
493 // Unhandled type. Halt "fast" selection and bail.
496 unsigned Op0 = getRegForValue(I->getOperand(0));
498 // Unhandled operand. Halt "fast" selection and bail.
501 // First, try to perform the bitcast by inserting a reg-reg copy.
502 unsigned ResultReg = 0;
503 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
504 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
505 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
506 ResultReg = createResultReg(DstClass);
508 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
509 Op0, DstClass, SrcClass);
514 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
516 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
517 ISD::BIT_CONVERT, Op0);
522 UpdateValueMap(I, ResultReg);
527 FastISel::SelectInstruction(Instruction *I) {
528 // First, try doing target-independent selection.
529 if (SelectOperator(I, I->getOpcode()))
532 // Next, try calling the target to attempt to handle the instruction.
533 if (TargetSelectInstruction(I))
539 /// FastEmitBranch - Emit an unconditional branch to the given block,
540 /// unless it is the immediate (fall-through) successor, and update
543 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
544 if (MBB->isLayoutSuccessor(MSucc)) {
545 // The unconditional fall-through case, which needs no instructions.
547 // The unconditional branch case.
548 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
550 MBB->addSuccessor(MSucc);
553 /// SelectFNeg - Emit an FNeg operation.
556 FastISel::SelectFNeg(User *I) {
557 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
558 if (OpReg == 0) return false;
560 // If the target has ISD::FNEG, use it.
561 EVT VT = TLI.getValueType(I->getType());
562 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
564 if (ResultReg != 0) {
565 UpdateValueMap(I, ResultReg);
569 // Bitcast the value to integer, twiddle the sign bit with xor,
570 // and then bitcast it back to floating-point.
571 if (VT.getSizeInBits() > 64) return false;
572 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
573 if (!TLI.isTypeLegal(IntVT))
576 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
577 ISD::BIT_CONVERT, OpReg);
581 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
582 UINT64_C(1) << (VT.getSizeInBits()-1),
583 IntVT.getSimpleVT());
584 if (IntResultReg == 0)
587 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
588 ISD::BIT_CONVERT, IntResultReg);
592 UpdateValueMap(I, ResultReg);
597 FastISel::SelectOperator(User *I, unsigned Opcode) {
599 case Instruction::Add:
600 return SelectBinaryOp(I, ISD::ADD);
601 case Instruction::FAdd:
602 return SelectBinaryOp(I, ISD::FADD);
603 case Instruction::Sub:
604 return SelectBinaryOp(I, ISD::SUB);
605 case Instruction::FSub:
606 // FNeg is currently represented in LLVM IR as a special case of FSub.
607 if (BinaryOperator::isFNeg(I))
608 return SelectFNeg(I);
609 return SelectBinaryOp(I, ISD::FSUB);
610 case Instruction::Mul:
611 return SelectBinaryOp(I, ISD::MUL);
612 case Instruction::FMul:
613 return SelectBinaryOp(I, ISD::FMUL);
614 case Instruction::SDiv:
615 return SelectBinaryOp(I, ISD::SDIV);
616 case Instruction::UDiv:
617 return SelectBinaryOp(I, ISD::UDIV);
618 case Instruction::FDiv:
619 return SelectBinaryOp(I, ISD::FDIV);
620 case Instruction::SRem:
621 return SelectBinaryOp(I, ISD::SREM);
622 case Instruction::URem:
623 return SelectBinaryOp(I, ISD::UREM);
624 case Instruction::FRem:
625 return SelectBinaryOp(I, ISD::FREM);
626 case Instruction::Shl:
627 return SelectBinaryOp(I, ISD::SHL);
628 case Instruction::LShr:
629 return SelectBinaryOp(I, ISD::SRL);
630 case Instruction::AShr:
631 return SelectBinaryOp(I, ISD::SRA);
632 case Instruction::And:
633 return SelectBinaryOp(I, ISD::AND);
634 case Instruction::Or:
635 return SelectBinaryOp(I, ISD::OR);
636 case Instruction::Xor:
637 return SelectBinaryOp(I, ISD::XOR);
639 case Instruction::GetElementPtr:
640 return SelectGetElementPtr(I);
642 case Instruction::Br: {
643 BranchInst *BI = cast<BranchInst>(I);
645 if (BI->isUnconditional()) {
646 BasicBlock *LLVMSucc = BI->getSuccessor(0);
647 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
648 FastEmitBranch(MSucc);
652 // Conditional branches are not handed yet.
653 // Halt "fast" selection and bail.
657 case Instruction::Unreachable:
661 case Instruction::PHI:
662 // PHI nodes are already emitted.
665 case Instruction::Alloca:
666 // FunctionLowering has the static-sized case covered.
667 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
670 // Dynamic-sized alloca is not handled yet.
673 case Instruction::Call:
674 return SelectCall(I);
676 case Instruction::BitCast:
677 return SelectBitCast(I);
679 case Instruction::FPToSI:
680 return SelectCast(I, ISD::FP_TO_SINT);
681 case Instruction::ZExt:
682 return SelectCast(I, ISD::ZERO_EXTEND);
683 case Instruction::SExt:
684 return SelectCast(I, ISD::SIGN_EXTEND);
685 case Instruction::Trunc:
686 return SelectCast(I, ISD::TRUNCATE);
687 case Instruction::SIToFP:
688 return SelectCast(I, ISD::SINT_TO_FP);
690 case Instruction::IntToPtr: // Deliberate fall-through.
691 case Instruction::PtrToInt: {
692 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
693 EVT DstVT = TLI.getValueType(I->getType());
694 if (DstVT.bitsGT(SrcVT))
695 return SelectCast(I, ISD::ZERO_EXTEND);
696 if (DstVT.bitsLT(SrcVT))
697 return SelectCast(I, ISD::TRUNCATE);
698 unsigned Reg = getRegForValue(I->getOperand(0));
699 if (Reg == 0) return false;
700 UpdateValueMap(I, Reg);
705 // Unhandled instruction. Halt "fast" selection and bail.
710 FastISel::FastISel(MachineFunction &mf,
711 MachineModuleInfo *mmi,
713 DenseMap<const Value *, unsigned> &vm,
714 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
715 DenseMap<const AllocaInst *, int> &am
717 , SmallSet<Instruction*, 8> &cil
730 MRI(MF.getRegInfo()),
731 MFI(*MF.getFrameInfo()),
732 MCP(*MF.getConstantPool()),
734 TD(*TM.getTargetData()),
735 TII(*TM.getInstrInfo()),
736 TLI(*TM.getTargetLowering()) {
739 FastISel::~FastISel() {}
741 unsigned FastISel::FastEmit_(MVT, MVT,
746 unsigned FastISel::FastEmit_r(MVT, MVT,
747 unsigned, unsigned /*Op0*/) {
751 unsigned FastISel::FastEmit_rr(MVT, MVT,
752 unsigned, unsigned /*Op0*/,
757 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
761 unsigned FastISel::FastEmit_f(MVT, MVT,
762 unsigned, ConstantFP * /*FPImm*/) {
766 unsigned FastISel::FastEmit_ri(MVT, MVT,
767 unsigned, unsigned /*Op0*/,
772 unsigned FastISel::FastEmit_rf(MVT, MVT,
773 unsigned, unsigned /*Op0*/,
774 ConstantFP * /*FPImm*/) {
778 unsigned FastISel::FastEmit_rri(MVT, MVT,
780 unsigned /*Op0*/, unsigned /*Op1*/,
785 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
786 /// to emit an instruction with an immediate operand using FastEmit_ri.
787 /// If that fails, it materializes the immediate into a register and try
788 /// FastEmit_rr instead.
789 unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode,
790 unsigned Op0, uint64_t Imm,
792 // First check if immediate type is legal. If not, we can't use the ri form.
793 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
796 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
797 if (MaterialReg == 0)
799 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
802 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
803 /// to emit an instruction with a floating-point immediate operand using
804 /// FastEmit_rf. If that fails, it materializes the immediate into a register
805 /// and try FastEmit_rr instead.
806 unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode,
807 unsigned Op0, ConstantFP *FPImm,
809 // First check if immediate type is legal. If not, we can't use the rf form.
810 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
814 // Materialize the constant in a register.
815 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
816 if (MaterialReg == 0) {
817 // If the target doesn't have a way to directly enter a floating-point
818 // value into a register, use an alternate approach.
819 // TODO: The current approach only supports floating-point constants
820 // that can be constructed by conversion from integer values. This should
821 // be replaced by code that creates a load from a constant-pool entry,
822 // which will require some target-specific work.
823 const APFloat &Flt = FPImm->getValueAPF();
824 EVT IntVT = TLI.getPointerTy();
827 uint32_t IntBitWidth = IntVT.getSizeInBits();
829 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
830 APFloat::rmTowardZero, &isExact);
833 APInt IntVal(IntBitWidth, 2, x);
835 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
836 ISD::Constant, IntVal.getZExtValue());
839 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
840 ISD::SINT_TO_FP, IntegerReg);
841 if (MaterialReg == 0)
844 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
847 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
848 return MRI.createVirtualRegister(RC);
851 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
852 const TargetRegisterClass* RC) {
853 unsigned ResultReg = createResultReg(RC);
854 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
856 BuildMI(MBB, DL, II, ResultReg);
860 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
861 const TargetRegisterClass *RC,
863 unsigned ResultReg = createResultReg(RC);
864 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
866 if (II.getNumDefs() >= 1)
867 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
869 BuildMI(MBB, DL, II).addReg(Op0);
870 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
871 II.ImplicitDefs[0], RC, RC);
879 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
880 const TargetRegisterClass *RC,
881 unsigned Op0, unsigned Op1) {
882 unsigned ResultReg = createResultReg(RC);
883 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
885 if (II.getNumDefs() >= 1)
886 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
888 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
889 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
890 II.ImplicitDefs[0], RC, RC);
897 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
898 const TargetRegisterClass *RC,
899 unsigned Op0, uint64_t Imm) {
900 unsigned ResultReg = createResultReg(RC);
901 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
903 if (II.getNumDefs() >= 1)
904 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
906 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
907 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
908 II.ImplicitDefs[0], RC, RC);
915 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
916 const TargetRegisterClass *RC,
917 unsigned Op0, ConstantFP *FPImm) {
918 unsigned ResultReg = createResultReg(RC);
919 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
921 if (II.getNumDefs() >= 1)
922 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
924 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
925 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
926 II.ImplicitDefs[0], RC, RC);
933 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
934 const TargetRegisterClass *RC,
935 unsigned Op0, unsigned Op1, uint64_t Imm) {
936 unsigned ResultReg = createResultReg(RC);
937 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
939 if (II.getNumDefs() >= 1)
940 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
942 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
943 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
944 II.ImplicitDefs[0], RC, RC);
951 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
952 const TargetRegisterClass *RC,
954 unsigned ResultReg = createResultReg(RC);
955 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
957 if (II.getNumDefs() >= 1)
958 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
960 BuildMI(MBB, DL, II).addImm(Imm);
961 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
962 II.ImplicitDefs[0], RC, RC);
969 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
970 unsigned Op0, uint32_t Idx) {
971 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
973 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
974 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
976 if (II.getNumDefs() >= 1)
977 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
979 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
980 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
981 II.ImplicitDefs[0], RC, RC);
988 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
989 /// with all but the least significant bit set to zero.
990 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
991 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);