1 //===-- FastISel.cpp - Implementation of the FastISel class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/CodeGen/Analysis.h"
43 #include "llvm/CodeGen/FastISel.h"
44 #include "llvm/ADT/Optional.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/Analysis/BranchProbabilityInfo.h"
47 #include "llvm/Analysis/Loads.h"
48 #include "llvm/CodeGen/Analysis.h"
49 #include "llvm/CodeGen/FunctionLoweringInfo.h"
50 #include "llvm/CodeGen/MachineFrameInfo.h"
51 #include "llvm/CodeGen/MachineInstrBuilder.h"
52 #include "llvm/CodeGen/MachineModuleInfo.h"
53 #include "llvm/CodeGen/MachineRegisterInfo.h"
54 #include "llvm/CodeGen/StackMaps.h"
55 #include "llvm/IR/DataLayout.h"
56 #include "llvm/IR/DebugInfo.h"
57 #include "llvm/IR/Function.h"
58 #include "llvm/IR/GlobalVariable.h"
59 #include "llvm/IR/Instructions.h"
60 #include "llvm/IR/IntrinsicInst.h"
61 #include "llvm/IR/Operator.h"
62 #include "llvm/Support/Debug.h"
63 #include "llvm/Support/ErrorHandling.h"
64 #include "llvm/Target/TargetInstrInfo.h"
65 #include "llvm/Target/TargetLibraryInfo.h"
66 #include "llvm/Target/TargetLowering.h"
67 #include "llvm/Target/TargetMachine.h"
68 #include "llvm/Target/TargetSubtargetInfo.h"
71 #define DEBUG_TYPE "isel"
73 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
74 "target-independent selector");
75 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
76 "target-specific selector");
77 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
79 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
80 /// and called function attributes.
81 void FastISel::ArgListEntry::setAttributes(ImmutableCallSite *CS,
83 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
84 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
85 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
86 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
87 isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
88 isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
89 isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
90 isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
91 Alignment = CS->getParamAlignment(AttrIdx);
94 /// startNewBlock - Set the current block to which generated machine
95 /// instructions will be appended, and clear the local CSE map.
97 void FastISel::startNewBlock() {
98 LocalValueMap.clear();
100 // Instructions are appended to FuncInfo.MBB. If the basic block already
101 // contains labels or copies, use the last instruction as the last local
103 EmitStartPt = nullptr;
104 if (!FuncInfo.MBB->empty())
105 EmitStartPt = &FuncInfo.MBB->back();
106 LastLocalValue = EmitStartPt;
109 bool FastISel::LowerArguments() {
110 if (!FuncInfo.CanLowerReturn)
111 // Fallback to SDISel argument lowering code to deal with sret pointer
115 if (!FastLowerArguments())
118 // Enter arguments into ValueMap for uses in non-entry BBs.
119 for (Function::const_arg_iterator I = FuncInfo.Fn->arg_begin(),
120 E = FuncInfo.Fn->arg_end(); I != E; ++I) {
121 DenseMap<const Value *, unsigned>::iterator VI = LocalValueMap.find(I);
122 assert(VI != LocalValueMap.end() && "Missed an argument?");
123 FuncInfo.ValueMap[I] = VI->second;
128 void FastISel::flushLocalValueMap() {
129 LocalValueMap.clear();
130 LastLocalValue = EmitStartPt;
134 bool FastISel::hasTrivialKill(const Value *V) const {
135 // Don't consider constants or arguments to have trivial kills.
136 const Instruction *I = dyn_cast<Instruction>(V);
140 // No-op casts are trivially coalesced by fast-isel.
141 if (const CastInst *Cast = dyn_cast<CastInst>(I))
142 if (Cast->isNoopCast(DL.getIntPtrType(Cast->getContext())) &&
143 !hasTrivialKill(Cast->getOperand(0)))
146 // GEPs with all zero indices are trivially coalesced by fast-isel.
147 if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(I))
148 if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0)))
151 // Only instructions with a single use in the same basic block are considered
152 // to have trivial kills.
153 return I->hasOneUse() &&
154 !(I->getOpcode() == Instruction::BitCast ||
155 I->getOpcode() == Instruction::PtrToInt ||
156 I->getOpcode() == Instruction::IntToPtr) &&
157 cast<Instruction>(*I->user_begin())->getParent() == I->getParent();
160 unsigned FastISel::getRegForValue(const Value *V) {
161 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
162 // Don't handle non-simple values in FastISel.
163 if (!RealVT.isSimple())
166 // Ignore illegal types. We must do this before looking up the value
167 // in ValueMap because Arguments are given virtual registers regardless
168 // of whether FastISel can handle them.
169 MVT VT = RealVT.getSimpleVT();
170 if (!TLI.isTypeLegal(VT)) {
171 // Handle integer promotions, though, because they're common and easy.
172 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
173 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
178 // Look up the value to see if we already have a register for it.
179 unsigned Reg = lookUpRegForValue(V);
183 // In bottom-up mode, just create the virtual register which will be used
184 // to hold the value. It will be materialized later.
185 if (isa<Instruction>(V) &&
186 (!isa<AllocaInst>(V) ||
187 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
188 return FuncInfo.InitializeRegForValue(V);
190 SavePoint SaveInsertPt = enterLocalValueArea();
192 // Materialize the value in a register. Emit any instructions in the
194 Reg = materializeRegForValue(V, VT);
196 leaveLocalValueArea(SaveInsertPt);
201 /// materializeRegForValue - Helper for getRegForValue. This function is
202 /// called when the value isn't already available in a register and must
203 /// be materialized with new instructions.
204 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
207 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
208 if (CI->getValue().getActiveBits() <= 64)
209 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
210 } else if (isa<AllocaInst>(V)) {
211 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
212 } else if (isa<ConstantPointerNull>(V)) {
213 // Translate this as an integer zero so that it can be
214 // local-CSE'd with actual integer zeros.
216 getRegForValue(Constant::getNullValue(DL.getIntPtrType(V->getContext())));
217 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
218 if (CF->isNullValue()) {
219 Reg = TargetMaterializeFloatZero(CF);
221 // Try to emit the constant directly.
222 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
226 // Try to emit the constant by using an integer constant with a cast.
227 const APFloat &Flt = CF->getValueAPF();
228 EVT IntVT = TLI.getPointerTy();
231 uint32_t IntBitWidth = IntVT.getSizeInBits();
233 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
234 APFloat::rmTowardZero, &isExact);
236 APInt IntVal(IntBitWidth, x);
238 unsigned IntegerReg =
239 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
241 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
242 IntegerReg, /*Kill=*/false);
245 } else if (const Operator *Op = dyn_cast<Operator>(V)) {
246 if (!SelectOperator(Op, Op->getOpcode()))
247 if (!isa<Instruction>(Op) ||
248 !TargetSelectInstruction(cast<Instruction>(Op)))
250 Reg = lookUpRegForValue(Op);
251 } else if (isa<UndefValue>(V)) {
252 Reg = createResultReg(TLI.getRegClassFor(VT));
253 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
254 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
257 // If target-independent code couldn't handle the value, give target-specific
259 if (!Reg && isa<Constant>(V))
260 Reg = TargetMaterializeConstant(cast<Constant>(V));
262 // Don't cache constant materializations in the general ValueMap.
263 // To do so would require tracking what uses they dominate.
265 LocalValueMap[V] = Reg;
266 LastLocalValue = MRI.getVRegDef(Reg);
271 unsigned FastISel::lookUpRegForValue(const Value *V) {
272 // Look up the value to see if we already have a register for it. We
273 // cache values defined by Instructions across blocks, and other values
274 // only locally. This is because Instructions already have the SSA
275 // def-dominates-use requirement enforced.
276 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
277 if (I != FuncInfo.ValueMap.end())
279 return LocalValueMap[V];
282 /// UpdateValueMap - Update the value map to include the new mapping for this
283 /// instruction, or insert an extra copy to get the result in a previous
284 /// determined register.
285 /// NOTE: This is only necessary because we might select a block that uses
286 /// a value before we select the block that defines the value. It might be
287 /// possible to fix this by selecting blocks in reverse postorder.
288 void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) {
289 if (!isa<Instruction>(I)) {
290 LocalValueMap[I] = Reg;
294 unsigned &AssignedReg = FuncInfo.ValueMap[I];
295 if (AssignedReg == 0)
296 // Use the new register.
298 else if (Reg != AssignedReg) {
299 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
300 for (unsigned i = 0; i < NumRegs; i++)
301 FuncInfo.RegFixups[AssignedReg+i] = Reg+i;
307 std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) {
308 unsigned IdxN = getRegForValue(Idx);
310 // Unhandled operand. Halt "fast" selection and bail.
311 return std::pair<unsigned, bool>(0, false);
313 bool IdxNIsKill = hasTrivialKill(Idx);
315 // If the index is smaller or larger than intptr_t, truncate or extend it.
316 MVT PtrVT = TLI.getPointerTy();
317 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
318 if (IdxVT.bitsLT(PtrVT)) {
319 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND,
323 else if (IdxVT.bitsGT(PtrVT)) {
324 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE,
328 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
331 void FastISel::recomputeInsertPt() {
332 if (getLastLocalValue()) {
333 FuncInfo.InsertPt = getLastLocalValue();
334 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
337 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
339 // Now skip past any EH_LABELs, which must remain at the beginning.
340 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
341 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
345 void FastISel::removeDeadCode(MachineBasicBlock::iterator I,
346 MachineBasicBlock::iterator E) {
347 assert (I && E && std::distance(I, E) > 0 && "Invalid iterator!");
349 MachineInstr *Dead = &*I;
351 Dead->eraseFromParent();
357 FastISel::SavePoint FastISel::enterLocalValueArea() {
358 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
359 DebugLoc OldDL = DbgLoc;
362 SavePoint SP = { OldInsertPt, OldDL };
366 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
367 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
368 LastLocalValue = std::prev(FuncInfo.InsertPt);
370 // Restore the previous insert position.
371 FuncInfo.InsertPt = OldInsertPt.InsertPt;
372 DbgLoc = OldInsertPt.DL;
375 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
376 /// which has an opcode which directly corresponds to the given ISD opcode.
378 bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) {
379 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
380 if (VT == MVT::Other || !VT.isSimple())
381 // Unhandled type. Halt "fast" selection and bail.
384 // We only handle legal types. For example, on x86-32 the instruction
385 // selector contains all of the 64-bit instructions from x86-64,
386 // under the assumption that i64 won't be used if the target doesn't
388 if (!TLI.isTypeLegal(VT)) {
389 // MVT::i1 is special. Allow AND, OR, or XOR because they
390 // don't require additional zeroing, which makes them easy.
392 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
393 ISDOpcode == ISD::XOR))
394 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
399 // Check if the first operand is a constant, and handle it as "ri". At -O0,
400 // we don't have anything that canonicalizes operand order.
401 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
402 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
403 unsigned Op1 = getRegForValue(I->getOperand(1));
404 if (Op1 == 0) return false;
406 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
408 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
409 Op1IsKill, CI->getZExtValue(),
411 if (ResultReg == 0) return false;
413 // We successfully emitted code for the given LLVM Instruction.
414 UpdateValueMap(I, ResultReg);
419 unsigned Op0 = getRegForValue(I->getOperand(0));
420 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail.
423 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
425 // Check if the second operand is a constant and handle it appropriately.
426 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
427 uint64_t Imm = CI->getZExtValue();
429 // Transform "sdiv exact X, 8" -> "sra X, 3".
430 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
431 cast<BinaryOperator>(I)->isExact() &&
432 isPowerOf2_64(Imm)) {
434 ISDOpcode = ISD::SRA;
437 // Transform "urem x, pow2" -> "and x, pow2-1".
438 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
439 isPowerOf2_64(Imm)) {
441 ISDOpcode = ISD::AND;
444 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
445 Op0IsKill, Imm, VT.getSimpleVT());
446 if (ResultReg == 0) return false;
448 // We successfully emitted code for the given LLVM Instruction.
449 UpdateValueMap(I, ResultReg);
453 // Check if the second operand is a constant float.
454 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
455 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
456 ISDOpcode, Op0, Op0IsKill, CF);
457 if (ResultReg != 0) {
458 // We successfully emitted code for the given LLVM Instruction.
459 UpdateValueMap(I, ResultReg);
464 unsigned Op1 = getRegForValue(I->getOperand(1));
466 // Unhandled operand. Halt "fast" selection and bail.
469 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
471 // Now we have both operands in registers. Emit the instruction.
472 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
477 // Target-specific code wasn't able to find a machine opcode for
478 // the given ISD opcode and type. Halt "fast" selection and bail.
481 // We successfully emitted code for the given LLVM Instruction.
482 UpdateValueMap(I, ResultReg);
486 bool FastISel::SelectGetElementPtr(const User *I) {
487 unsigned N = getRegForValue(I->getOperand(0));
489 // Unhandled operand. Halt "fast" selection and bail.
492 bool NIsKill = hasTrivialKill(I->getOperand(0));
494 // Keep a running tab of the total offset to coalesce multiple N = N + Offset
495 // into a single N = N + TotalOffset.
496 uint64_t TotalOffs = 0;
497 // FIXME: What's a good SWAG number for MaxOffs?
498 uint64_t MaxOffs = 2048;
499 Type *Ty = I->getOperand(0)->getType();
500 MVT VT = TLI.getPointerTy();
501 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1,
502 E = I->op_end(); OI != E; ++OI) {
503 const Value *Idx = *OI;
504 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
505 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
508 TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
509 if (TotalOffs >= MaxOffs) {
510 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
512 // Unhandled operand. Halt "fast" selection and bail.
518 Ty = StTy->getElementType(Field);
520 Ty = cast<SequentialType>(Ty)->getElementType();
522 // If this is a constant subscript, handle it quickly.
523 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
524 if (CI->isZero()) continue;
527 DL.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
528 if (TotalOffs >= MaxOffs) {
529 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
531 // Unhandled operand. Halt "fast" selection and bail.
539 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
541 // Unhandled operand. Halt "fast" selection and bail.
547 // N = N + Idx * ElementSize;
548 uint64_t ElementSize = DL.getTypeAllocSize(Ty);
549 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
550 unsigned IdxN = Pair.first;
551 bool IdxNIsKill = Pair.second;
553 // Unhandled operand. Halt "fast" selection and bail.
556 if (ElementSize != 1) {
557 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
559 // Unhandled operand. Halt "fast" selection and bail.
563 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
565 // Unhandled operand. Halt "fast" selection and bail.
570 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
572 // Unhandled operand. Halt "fast" selection and bail.
576 // We successfully emitted code for the given LLVM Instruction.
577 UpdateValueMap(I, N);
581 /// \brief Add a stackmap or patchpoint intrinsic call's live variable operands
582 /// to a stackmap or patchpoint machine instruction.
583 bool FastISel::addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
584 const CallInst *CI, unsigned StartIdx) {
585 for (unsigned i = StartIdx, e = CI->getNumArgOperands(); i != e; ++i) {
586 Value *Val = CI->getArgOperand(i);
587 // Check for constants and encode them with a StackMaps::ConstantOp prefix.
588 if (auto *C = dyn_cast<ConstantInt>(Val)) {
589 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
590 Ops.push_back(MachineOperand::CreateImm(C->getSExtValue()));
591 } else if (isa<ConstantPointerNull>(Val)) {
592 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
593 Ops.push_back(MachineOperand::CreateImm(0));
594 } else if (auto *AI = dyn_cast<AllocaInst>(Val)) {
595 // Values coming from a stack location also require a sepcial encoding,
596 // but that is added later on by the target specific frame index
597 // elimination implementation.
598 auto SI = FuncInfo.StaticAllocaMap.find(AI);
599 if (SI != FuncInfo.StaticAllocaMap.end())
600 Ops.push_back(MachineOperand::CreateFI(SI->second));
604 unsigned Reg = getRegForValue(Val);
607 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
614 bool FastISel::SelectStackmap(const CallInst *I) {
615 // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
616 // [live variables...])
617 assert(I->getCalledFunction()->getReturnType()->isVoidTy() &&
618 "Stackmap cannot return a value.");
620 // The stackmap intrinsic only records the live variables (the arguments
621 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
622 // intrinsic, this won't be lowered to a function call. This means we don't
623 // have to worry about calling conventions and target-specific lowering code.
624 // Instead we perform the call lowering right here.
627 // STACKMAP(id, nbytes, ...)
630 SmallVector<MachineOperand, 32> Ops;
632 // Add the <id> and <numBytes> constants.
633 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
634 "Expected a constant integer.");
635 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
636 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
638 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
639 "Expected a constant integer.");
640 const auto *NumBytes =
641 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
642 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
644 // Push live variables for the stack map (skipping the first two arguments
645 // <id> and <numBytes>).
646 if (!addStackMapLiveVars(Ops, I, 2))
649 // We are not adding any register mask info here, because the stackmap doesn't
652 // Add scratch registers as implicit def and early clobber.
653 CallingConv::ID CC = I->getCallingConv();
654 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
655 for (unsigned i = 0; ScratchRegs[i]; ++i)
656 Ops.push_back(MachineOperand::CreateReg(
657 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
658 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
660 // Issue CALLSEQ_START
661 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
662 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
666 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
667 TII.get(TargetOpcode::STACKMAP));
668 for (auto const &MO : Ops)
672 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
673 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
674 .addImm(0).addImm(0);
676 // Inform the Frame Information that we have a stackmap in this function.
677 FuncInfo.MF->getFrameInfo()->setHasStackMap();
682 /// \brief Lower an argument list according to the target calling convention.
684 /// This is a helper for lowering intrinsics that follow a target calling
685 /// convention or require stack pointer adjustment. Only a subset of the
686 /// intrinsic's operands need to participate in the calling convention.
687 bool FastISel::lowerCallOperands(const CallInst *CI, unsigned ArgIdx,
688 unsigned NumArgs, const Value *Callee,
689 bool ForceRetVoidTy, CallLoweringInfo &CLI) {
691 Args.reserve(NumArgs);
693 // Populate the argument list.
694 // Attributes for args start at offset 1, after the return attribute.
695 ImmutableCallSite CS(CI);
696 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
697 ArgI != ArgE; ++ArgI) {
698 Value *V = CI->getOperand(ArgI);
700 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
704 Entry.Ty = V->getType();
705 Entry.setAttributes(&CS, AttrI);
706 Args.push_back(Entry);
709 Type *RetTy = ForceRetVoidTy ? Type::getVoidTy(CI->getType()->getContext())
711 CLI.setCallee(CI->getCallingConv(), RetTy, Callee, std::move(Args), NumArgs);
713 return LowerCallTo(CLI);
716 bool FastISel::SelectPatchpoint(const CallInst *I) {
717 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
722 // [live variables...])
723 CallingConv::ID CC = I->getCallingConv();
724 bool IsAnyRegCC = CC == CallingConv::AnyReg;
725 bool HasDef = !I->getType()->isVoidTy();
726 Value *Callee = I->getOperand(PatchPointOpers::TargetPos);
728 // Get the real number of arguments participating in the call <numArgs>
729 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos)) &&
730 "Expected a constant integer.");
731 const auto *NumArgsVal =
732 cast<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos));
733 unsigned NumArgs = NumArgsVal->getZExtValue();
735 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
736 // This includes all meta-operands up to but not including CC.
737 unsigned NumMetaOpers = PatchPointOpers::CCPos;
738 assert(I->getNumArgOperands() >= NumMetaOpers + NumArgs &&
739 "Not enough arguments provided to the patchpoint intrinsic");
741 // For AnyRegCC the arguments are lowered later on manually.
742 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
743 CallLoweringInfo CLI;
744 if (!lowerCallOperands(I, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC, CLI))
747 assert(CLI.Call && "No call instruction specified.");
749 SmallVector<MachineOperand, 32> Ops;
751 // Add an explicit result reg if we use the anyreg calling convention.
752 if (IsAnyRegCC && HasDef) {
753 assert(CLI.NumResultRegs == 0 && "Unexpected result register.");
754 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
755 CLI.NumResultRegs = 1;
756 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true));
759 // Add the <id> and <numBytes> constants.
760 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
761 "Expected a constant integer.");
762 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
763 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
765 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
766 "Expected a constant integer.");
767 const auto *NumBytes =
768 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
769 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
771 // Assume that the callee is a constant address or null pointer.
772 // FIXME: handle function symbols in the future.
774 if (const auto *C = dyn_cast<IntToPtrInst>(Callee))
775 CalleeAddr = cast<ConstantInt>(C->getOperand(0))->getZExtValue();
776 else if (const auto *C = dyn_cast<ConstantExpr>(Callee)) {
777 if (C->getOpcode() == Instruction::IntToPtr)
778 CalleeAddr = cast<ConstantInt>(C->getOperand(0))->getZExtValue();
780 llvm_unreachable("Unsupported ConstantExpr.");
781 } else if (isa<ConstantPointerNull>(Callee))
784 llvm_unreachable("Unsupported callee address.");
786 Ops.push_back(MachineOperand::CreateImm(CalleeAddr));
788 // Adjust <numArgs> to account for any arguments that have been passed on
789 // the stack instead.
790 unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size();
791 Ops.push_back(MachineOperand::CreateImm(NumCallRegArgs));
793 // Add the calling convention
794 Ops.push_back(MachineOperand::CreateImm((unsigned)CC));
796 // Add the arguments we omitted previously. The register allocator should
797 // place these in any free register.
799 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) {
800 unsigned Reg = getRegForValue(I->getArgOperand(i));
803 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
807 // Push the arguments from the call instruction.
808 for (auto Reg : CLI.OutRegs)
809 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
811 // Push live variables for the stack map.
812 if (!addStackMapLiveVars(Ops, I, NumMetaOpers + NumArgs))
815 // Push the register mask info.
816 Ops.push_back(MachineOperand::CreateRegMask(TRI.getCallPreservedMask(CC)));
818 // Add scratch registers as implicit def and early clobber.
819 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
820 for (unsigned i = 0; ScratchRegs[i]; ++i)
821 Ops.push_back(MachineOperand::CreateReg(
822 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
823 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
825 // Add implicit defs (return values).
826 for (auto Reg : CLI.InRegs)
827 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/true,
830 // Insert the patchpoint instruction before the call generated by the target.
831 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, CLI.Call, DbgLoc,
832 TII.get(TargetOpcode::PATCHPOINT));
837 MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);
839 // Delete the original call instruction.
840 CLI.Call->eraseFromParent();
842 // Inform the Frame Information that we have a patchpoint in this function.
843 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
845 if (CLI.NumResultRegs)
846 UpdateValueMap(I, CLI.ResultReg, CLI.NumResultRegs);
850 /// Returns an AttributeSet representing the attributes applied to the return
851 /// value of the given call.
852 static AttributeSet getReturnAttrs(FastISel::CallLoweringInfo &CLI) {
853 SmallVector<Attribute::AttrKind, 2> Attrs;
855 Attrs.push_back(Attribute::SExt);
857 Attrs.push_back(Attribute::ZExt);
859 Attrs.push_back(Attribute::InReg);
861 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
865 bool FastISel::LowerCallTo(const CallInst *CI, const char *SymName,
867 ImmutableCallSite CS(CI);
869 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
870 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
871 Type *RetTy = FTy->getReturnType();
874 Args.reserve(NumArgs);
876 // Populate the argument list.
877 // Attributes for args start at offset 1, after the return attribute.
878 for (unsigned ArgI = 0; ArgI != NumArgs; ++ArgI) {
879 Value *V = CI->getOperand(ArgI);
881 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
885 Entry.Ty = V->getType();
886 Entry.setAttributes(&CS, ArgI + 1);
887 Args.push_back(Entry);
890 CallLoweringInfo CLI;
891 CLI.setCallee(RetTy, FTy, SymName, std::move(Args), CS, NumArgs);
893 return LowerCallTo(CLI);
896 bool FastISel::LowerCallTo(CallLoweringInfo &CLI) {
897 // Handle the incoming return values from the call.
899 SmallVector<EVT, 4> RetTys;
900 ComputeValueVTs(TLI, CLI.RetTy, RetTys);
902 SmallVector<ISD::OutputArg, 4> Outs;
903 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, TLI);
905 bool CanLowerReturn = TLI.CanLowerReturn(CLI.CallConv, *FuncInfo.MF,
907 CLI.RetTy->getContext());
909 // FIXME: sret demotion isn't supported yet - bail out.
913 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
915 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT);
916 unsigned NumRegs = TLI.getNumRegisters(CLI.RetTy->getContext(), VT);
917 for (unsigned i = 0; i != NumRegs; ++i) {
918 ISD::InputArg MyFlags;
919 MyFlags.VT = RegisterVT;
921 MyFlags.Used = CLI.IsReturnValueUsed;
923 MyFlags.Flags.setSExt();
925 MyFlags.Flags.setZExt();
927 MyFlags.Flags.setInReg();
928 CLI.Ins.push_back(MyFlags);
932 // Handle all of the outgoing arguments.
934 for (auto &Arg : CLI.getArgs()) {
935 Type *FinalType = Arg.Ty;
937 FinalType = cast<PointerType>(Arg.Ty)->getElementType();
938 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
939 FinalType, CLI.CallConv, CLI.IsVarArg);
941 ISD::ArgFlagsTy Flags;
952 if (Arg.isInAlloca) {
954 // Set the byval flag for CCAssignFn callbacks that don't know about
955 // inalloca. This way we can know how many bytes we should've allocated
956 // and how many bytes a callee cleanup function will pop. If we port
957 // inalloca to more targets, we'll have to add custom inalloca handling in
958 // the various CC lowering callbacks.
961 if (Arg.isByVal || Arg.isInAlloca) {
962 PointerType *Ty = cast<PointerType>(Arg.Ty);
963 Type *ElementTy = Ty->getElementType();
964 unsigned FrameSize = DL.getTypeAllocSize(ElementTy);
965 // For ByVal, alignment should come from FE. BE will guess if this info is
966 // not there, but there are cases it cannot get right.
967 unsigned FrameAlign = Arg.Alignment;
969 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
970 Flags.setByValSize(FrameSize);
971 Flags.setByValAlign(FrameAlign);
976 Flags.setInConsecutiveRegs();
977 unsigned OriginalAlignment = DL.getABITypeAlignment(Arg.Ty);
978 Flags.setOrigAlign(OriginalAlignment);
980 CLI.OutVals.push_back(Arg.Val);
981 CLI.OutFlags.push_back(Flags);
984 if (!FastLowerCall(CLI))
987 // Set all unused physreg defs as dead.
988 assert(CLI.Call && "No call instruction specified.");
989 CLI.Call->setPhysRegsDeadExcept(CLI.InRegs, TRI);
991 if (CLI.NumResultRegs && CLI.CS)
992 UpdateValueMap(CLI.CS->getInstruction(), CLI.ResultReg, CLI.NumResultRegs);
997 bool FastISel::LowerCall(const CallInst *CI) {
998 ImmutableCallSite CS(CI);
1000 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1001 FunctionType *FuncTy = cast<FunctionType>(PT->getElementType());
1002 Type *RetTy = FuncTy->getReturnType();
1006 Args.reserve(CS.arg_size());
1008 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1013 if (V->getType()->isEmptyTy())
1017 Entry.Ty = V->getType();
1019 // Skip the first return-type Attribute to get to params.
1020 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
1021 Args.push_back(Entry);
1024 // Check if target-independent constraints permit a tail call here.
1025 // Target-dependent constraints are checked within FastLowerCall.
1026 bool IsTailCall = CI->isTailCall();
1027 if (IsTailCall && !isInTailCallPosition(CS, TM))
1030 CallLoweringInfo CLI;
1031 CLI.setCallee(RetTy, FuncTy, CI->getCalledValue(), std::move(Args), CS)
1032 .setTailCall(IsTailCall);
1034 return LowerCallTo(CLI);
1037 bool FastISel::SelectCall(const User *I) {
1038 const CallInst *Call = cast<CallInst>(I);
1040 // Handle simple inline asms.
1041 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledValue())) {
1042 // If the inline asm has side effects, then make sure that no local value
1043 // lives across by flushing the local value map.
1044 if (IA->hasSideEffects())
1045 flushLocalValueMap();
1047 // Don't attempt to handle constraints.
1048 if (!IA->getConstraintString().empty())
1051 unsigned ExtraInfo = 0;
1052 if (IA->hasSideEffects())
1053 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1054 if (IA->isAlignStack())
1055 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
1057 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1058 TII.get(TargetOpcode::INLINEASM))
1059 .addExternalSymbol(IA->getAsmString().c_str())
1064 MachineModuleInfo &MMI = FuncInfo.MF->getMMI();
1065 ComputeUsesVAFloatArgument(*Call, &MMI);
1067 // Handle intrinsic function calls.
1068 if (const auto *II = dyn_cast<IntrinsicInst>(Call))
1069 return SelectIntrinsicCall(II);
1071 // Usually, it does not make sense to initialize a value,
1072 // make an unrelated function call and use the value, because
1073 // it tends to be spilled on the stack. So, we move the pointer
1074 // to the last local value to the beginning of the block, so that
1075 // all the values which have already been materialized,
1076 // appear after the call. It also makes sense to skip intrinsics
1077 // since they tend to be inlined.
1078 flushLocalValueMap();
1080 return LowerCall(Call);
1083 bool FastISel::SelectIntrinsicCall(const IntrinsicInst *II) {
1084 switch (II->getIntrinsicID()) {
1086 // At -O0 we don't care about the lifetime intrinsics.
1087 case Intrinsic::lifetime_start:
1088 case Intrinsic::lifetime_end:
1089 // The donothing intrinsic does, well, nothing.
1090 case Intrinsic::donothing:
1092 case Intrinsic::dbg_declare: {
1093 const DbgDeclareInst *DI = cast<DbgDeclareInst>(II);
1094 DIVariable DIVar(DI->getVariable());
1095 assert((!DIVar || DIVar.isVariable()) &&
1096 "Variable in DbgDeclareInst should be either null or a DIVariable.");
1097 if (!DIVar || !FuncInfo.MF->getMMI().hasDebugInfo()) {
1098 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1102 const Value *Address = DI->getAddress();
1103 if (!Address || isa<UndefValue>(Address)) {
1104 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1108 unsigned Offset = 0;
1109 Optional<MachineOperand> Op;
1110 if (const Argument *Arg = dyn_cast<Argument>(Address))
1111 // Some arguments' frame index is recorded during argument lowering.
1112 Offset = FuncInfo.getArgumentFrameIndex(Arg);
1114 Op = MachineOperand::CreateFI(Offset);
1116 if (unsigned Reg = lookUpRegForValue(Address))
1117 Op = MachineOperand::CreateReg(Reg, false);
1119 // If we have a VLA that has a "use" in a metadata node that's then used
1120 // here but it has no other uses, then we have a problem. E.g.,
1122 // int foo (const int *x) {
1127 // If we assign 'a' a vreg and fast isel later on has to use the selection
1128 // DAG isel, it will want to copy the value to the vreg. However, there are
1129 // no uses, which goes counter to what selection DAG isel expects.
1130 if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&
1131 (!isa<AllocaInst>(Address) ||
1132 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
1133 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
1138 Op->setIsDebug(true);
1139 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1140 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0,
1143 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1144 TII.get(TargetOpcode::DBG_VALUE))
1147 .addMetadata(DI->getVariable());
1149 // We can't yet handle anything else here because it would require
1150 // generating code, thus altering codegen because of debug info.
1151 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1155 case Intrinsic::dbg_value: {
1156 // This form of DBG_VALUE is target-independent.
1157 const DbgValueInst *DI = cast<DbgValueInst>(II);
1158 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1159 const Value *V = DI->getValue();
1161 // Currently the optimizer can produce this; insert an undef to
1162 // help debugging. Probably the optimizer should not do this.
1163 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1164 .addReg(0U).addImm(DI->getOffset())
1165 .addMetadata(DI->getVariable());
1166 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
1167 if (CI->getBitWidth() > 64)
1168 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1169 .addCImm(CI).addImm(DI->getOffset())
1170 .addMetadata(DI->getVariable());
1172 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1173 .addImm(CI->getZExtValue()).addImm(DI->getOffset())
1174 .addMetadata(DI->getVariable());
1175 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
1176 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1177 .addFPImm(CF).addImm(DI->getOffset())
1178 .addMetadata(DI->getVariable());
1179 } else if (unsigned Reg = lookUpRegForValue(V)) {
1180 // FIXME: This does not handle register-indirect values at offset 0.
1181 bool IsIndirect = DI->getOffset() != 0;
1182 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, IsIndirect,
1183 Reg, DI->getOffset(), DI->getVariable());
1185 // We can't yet handle anything else here because it would require
1186 // generating code, thus altering codegen because of debug info.
1187 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1191 case Intrinsic::objectsize: {
1192 ConstantInt *CI = cast<ConstantInt>(II->getArgOperand(1));
1193 unsigned long long Res = CI->isZero() ? -1ULL : 0;
1194 Constant *ResCI = ConstantInt::get(II->getType(), Res);
1195 unsigned ResultReg = getRegForValue(ResCI);
1198 UpdateValueMap(II, ResultReg);
1201 case Intrinsic::expect: {
1202 unsigned ResultReg = getRegForValue(II->getArgOperand(0));
1205 UpdateValueMap(II, ResultReg);
1208 case Intrinsic::experimental_stackmap:
1209 return SelectStackmap(II);
1210 case Intrinsic::experimental_patchpoint_void:
1211 case Intrinsic::experimental_patchpoint_i64:
1212 return SelectPatchpoint(II);
1215 return FastLowerIntrinsicCall(II);
1218 bool FastISel::SelectCast(const User *I, unsigned Opcode) {
1219 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1220 EVT DstVT = TLI.getValueType(I->getType());
1222 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
1223 DstVT == MVT::Other || !DstVT.isSimple())
1224 // Unhandled type. Halt "fast" selection and bail.
1227 // Check if the destination type is legal.
1228 if (!TLI.isTypeLegal(DstVT))
1231 // Check if the source operand is legal.
1232 if (!TLI.isTypeLegal(SrcVT))
1235 unsigned InputReg = getRegForValue(I->getOperand(0));
1237 // Unhandled operand. Halt "fast" selection and bail.
1240 bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
1242 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
1243 DstVT.getSimpleVT(),
1245 InputReg, InputRegIsKill);
1249 UpdateValueMap(I, ResultReg);
1253 bool FastISel::SelectBitCast(const User *I) {
1254 // If the bitcast doesn't change the type, just use the operand value.
1255 if (I->getType() == I->getOperand(0)->getType()) {
1256 unsigned Reg = getRegForValue(I->getOperand(0));
1259 UpdateValueMap(I, Reg);
1263 // Bitcasts of other values become reg-reg copies or BITCAST operators.
1264 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType());
1265 EVT DstEVT = TLI.getValueType(I->getType());
1266 if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
1267 !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
1268 // Unhandled type. Halt "fast" selection and bail.
1271 MVT SrcVT = SrcEVT.getSimpleVT();
1272 MVT DstVT = DstEVT.getSimpleVT();
1273 unsigned Op0 = getRegForValue(I->getOperand(0));
1275 // Unhandled operand. Halt "fast" selection and bail.
1278 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
1280 // First, try to perform the bitcast by inserting a reg-reg copy.
1281 unsigned ResultReg = 0;
1282 if (SrcVT == DstVT) {
1283 const TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
1284 const TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
1285 // Don't attempt a cross-class copy. It will likely fail.
1286 if (SrcClass == DstClass) {
1287 ResultReg = createResultReg(DstClass);
1288 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1289 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
1293 // If the reg-reg copy failed, select a BITCAST opcode.
1295 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1300 UpdateValueMap(I, ResultReg);
1305 FastISel::SelectInstruction(const Instruction *I) {
1306 // Just before the terminator instruction, insert instructions to
1307 // feed PHI nodes in successor blocks.
1308 if (isa<TerminatorInst>(I))
1309 if (!HandlePHINodesInSuccessorBlocks(I->getParent()))
1312 DbgLoc = I->getDebugLoc();
1314 MachineBasicBlock::iterator SavedInsertPt = FuncInfo.InsertPt;
1316 if (const CallInst *Call = dyn_cast<CallInst>(I)) {
1317 const Function *F = Call->getCalledFunction();
1320 // As a special case, don't handle calls to builtin library functions that
1321 // may be translated directly to target instructions.
1322 if (F && !F->hasLocalLinkage() && F->hasName() &&
1323 LibInfo->getLibFunc(F->getName(), Func) &&
1324 LibInfo->hasOptimizedCodeGen(Func))
1327 // Don't handle Intrinsic::trap if a trap funciton is specified.
1328 if (F && F->getIntrinsicID() == Intrinsic::trap &&
1329 !TM.Options.getTrapFunctionName().empty())
1333 // First, try doing target-independent selection.
1334 if (SelectOperator(I, I->getOpcode())) {
1335 ++NumFastIselSuccessIndependent;
1336 DbgLoc = DebugLoc();
1339 // Remove dead code. However, ignore call instructions since we've flushed
1340 // the local value map and recomputed the insert point.
1341 if (!isa<CallInst>(I)) {
1342 recomputeInsertPt();
1343 if (SavedInsertPt != FuncInfo.InsertPt)
1344 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1347 // Next, try calling the target to attempt to handle the instruction.
1348 SavedInsertPt = FuncInfo.InsertPt;
1349 if (TargetSelectInstruction(I)) {
1350 ++NumFastIselSuccessTarget;
1351 DbgLoc = DebugLoc();
1354 // Check for dead code and remove as necessary.
1355 recomputeInsertPt();
1356 if (SavedInsertPt != FuncInfo.InsertPt)
1357 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1359 DbgLoc = DebugLoc();
1363 /// FastEmitBranch - Emit an unconditional branch to the given block,
1364 /// unless it is the immediate (fall-through) successor, and update
1367 FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DbgLoc) {
1368 if (FuncInfo.MBB->getBasicBlock()->size() > 1 &&
1369 FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
1370 // For more accurate line information if this is the only instruction
1371 // in the block then emit it, otherwise we have the unconditional
1372 // fall-through case, which needs no instructions.
1374 // The unconditional branch case.
1375 TII.InsertBranch(*FuncInfo.MBB, MSucc, nullptr,
1376 SmallVector<MachineOperand, 0>(), DbgLoc);
1378 uint32_t BranchWeight = 0;
1380 BranchWeight = FuncInfo.BPI->getEdgeWeight(FuncInfo.MBB->getBasicBlock(),
1381 MSucc->getBasicBlock());
1382 FuncInfo.MBB->addSuccessor(MSucc, BranchWeight);
1385 /// SelectFNeg - Emit an FNeg operation.
1388 FastISel::SelectFNeg(const User *I) {
1389 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
1390 if (OpReg == 0) return false;
1392 bool OpRegIsKill = hasTrivialKill(I);
1394 // If the target has ISD::FNEG, use it.
1395 EVT VT = TLI.getValueType(I->getType());
1396 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
1397 ISD::FNEG, OpReg, OpRegIsKill);
1398 if (ResultReg != 0) {
1399 UpdateValueMap(I, ResultReg);
1403 // Bitcast the value to integer, twiddle the sign bit with xor,
1404 // and then bitcast it back to floating-point.
1405 if (VT.getSizeInBits() > 64) return false;
1406 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
1407 if (!TLI.isTypeLegal(IntVT))
1410 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1411 ISD::BITCAST, OpReg, OpRegIsKill);
1415 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR,
1416 IntReg, /*Kill=*/true,
1417 UINT64_C(1) << (VT.getSizeInBits()-1),
1418 IntVT.getSimpleVT());
1419 if (IntResultReg == 0)
1422 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
1423 ISD::BITCAST, IntResultReg, /*Kill=*/true);
1427 UpdateValueMap(I, ResultReg);
1432 FastISel::SelectExtractValue(const User *U) {
1433 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
1437 // Make sure we only try to handle extracts with a legal result. But also
1438 // allow i1 because it's easy.
1439 EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true);
1440 if (!RealVT.isSimple())
1442 MVT VT = RealVT.getSimpleVT();
1443 if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
1446 const Value *Op0 = EVI->getOperand(0);
1447 Type *AggTy = Op0->getType();
1449 // Get the base result register.
1451 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
1452 if (I != FuncInfo.ValueMap.end())
1453 ResultReg = I->second;
1454 else if (isa<Instruction>(Op0))
1455 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1457 return false; // fast-isel can't handle aggregate constants at the moment
1459 // Get the actual result register, which is an offset from the base register.
1460 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
1462 SmallVector<EVT, 4> AggValueVTs;
1463 ComputeValueVTs(TLI, AggTy, AggValueVTs);
1465 for (unsigned i = 0; i < VTIndex; i++)
1466 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1468 UpdateValueMap(EVI, ResultReg);
1473 FastISel::SelectOperator(const User *I, unsigned Opcode) {
1475 case Instruction::Add:
1476 return SelectBinaryOp(I, ISD::ADD);
1477 case Instruction::FAdd:
1478 return SelectBinaryOp(I, ISD::FADD);
1479 case Instruction::Sub:
1480 return SelectBinaryOp(I, ISD::SUB);
1481 case Instruction::FSub:
1482 // FNeg is currently represented in LLVM IR as a special case of FSub.
1483 if (BinaryOperator::isFNeg(I))
1484 return SelectFNeg(I);
1485 return SelectBinaryOp(I, ISD::FSUB);
1486 case Instruction::Mul:
1487 return SelectBinaryOp(I, ISD::MUL);
1488 case Instruction::FMul:
1489 return SelectBinaryOp(I, ISD::FMUL);
1490 case Instruction::SDiv:
1491 return SelectBinaryOp(I, ISD::SDIV);
1492 case Instruction::UDiv:
1493 return SelectBinaryOp(I, ISD::UDIV);
1494 case Instruction::FDiv:
1495 return SelectBinaryOp(I, ISD::FDIV);
1496 case Instruction::SRem:
1497 return SelectBinaryOp(I, ISD::SREM);
1498 case Instruction::URem:
1499 return SelectBinaryOp(I, ISD::UREM);
1500 case Instruction::FRem:
1501 return SelectBinaryOp(I, ISD::FREM);
1502 case Instruction::Shl:
1503 return SelectBinaryOp(I, ISD::SHL);
1504 case Instruction::LShr:
1505 return SelectBinaryOp(I, ISD::SRL);
1506 case Instruction::AShr:
1507 return SelectBinaryOp(I, ISD::SRA);
1508 case Instruction::And:
1509 return SelectBinaryOp(I, ISD::AND);
1510 case Instruction::Or:
1511 return SelectBinaryOp(I, ISD::OR);
1512 case Instruction::Xor:
1513 return SelectBinaryOp(I, ISD::XOR);
1515 case Instruction::GetElementPtr:
1516 return SelectGetElementPtr(I);
1518 case Instruction::Br: {
1519 const BranchInst *BI = cast<BranchInst>(I);
1521 if (BI->isUnconditional()) {
1522 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
1523 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
1524 FastEmitBranch(MSucc, BI->getDebugLoc());
1528 // Conditional branches are not handed yet.
1529 // Halt "fast" selection and bail.
1533 case Instruction::Unreachable:
1534 if (TM.Options.TrapUnreachable)
1535 return FastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
1539 case Instruction::Alloca:
1540 // FunctionLowering has the static-sized case covered.
1541 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
1544 // Dynamic-sized alloca is not handled yet.
1547 case Instruction::Call:
1548 return SelectCall(I);
1550 case Instruction::BitCast:
1551 return SelectBitCast(I);
1553 case Instruction::FPToSI:
1554 return SelectCast(I, ISD::FP_TO_SINT);
1555 case Instruction::ZExt:
1556 return SelectCast(I, ISD::ZERO_EXTEND);
1557 case Instruction::SExt:
1558 return SelectCast(I, ISD::SIGN_EXTEND);
1559 case Instruction::Trunc:
1560 return SelectCast(I, ISD::TRUNCATE);
1561 case Instruction::SIToFP:
1562 return SelectCast(I, ISD::SINT_TO_FP);
1564 case Instruction::IntToPtr: // Deliberate fall-through.
1565 case Instruction::PtrToInt: {
1566 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1567 EVT DstVT = TLI.getValueType(I->getType());
1568 if (DstVT.bitsGT(SrcVT))
1569 return SelectCast(I, ISD::ZERO_EXTEND);
1570 if (DstVT.bitsLT(SrcVT))
1571 return SelectCast(I, ISD::TRUNCATE);
1572 unsigned Reg = getRegForValue(I->getOperand(0));
1573 if (Reg == 0) return false;
1574 UpdateValueMap(I, Reg);
1578 case Instruction::ExtractValue:
1579 return SelectExtractValue(I);
1581 case Instruction::PHI:
1582 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1585 // Unhandled instruction. Halt "fast" selection and bail.
1590 FastISel::FastISel(FunctionLoweringInfo &funcInfo,
1591 const TargetLibraryInfo *libInfo)
1592 : FuncInfo(funcInfo), MF(funcInfo.MF), MRI(FuncInfo.MF->getRegInfo()),
1593 MFI(*FuncInfo.MF->getFrameInfo()), MCP(*FuncInfo.MF->getConstantPool()),
1594 TM(FuncInfo.MF->getTarget()), DL(*TM.getSubtargetImpl()->getDataLayout()),
1595 TII(*TM.getSubtargetImpl()->getInstrInfo()),
1596 TLI(*TM.getSubtargetImpl()->getTargetLowering()),
1597 TRI(*TM.getSubtargetImpl()->getRegisterInfo()), LibInfo(libInfo) {}
1599 FastISel::~FastISel() {}
1601 bool FastISel::FastLowerArguments() {
1605 bool FastISel::FastLowerCall(CallLoweringInfo &/*CLI*/) {
1609 bool FastISel::FastLowerIntrinsicCall(const IntrinsicInst * /*II*/) {
1613 unsigned FastISel::FastEmit_(MVT, MVT,
1618 unsigned FastISel::FastEmit_r(MVT, MVT,
1620 unsigned /*Op0*/, bool /*Op0IsKill*/) {
1624 unsigned FastISel::FastEmit_rr(MVT, MVT,
1626 unsigned /*Op0*/, bool /*Op0IsKill*/,
1627 unsigned /*Op1*/, bool /*Op1IsKill*/) {
1631 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1635 unsigned FastISel::FastEmit_f(MVT, MVT,
1636 unsigned, const ConstantFP * /*FPImm*/) {
1640 unsigned FastISel::FastEmit_ri(MVT, MVT,
1642 unsigned /*Op0*/, bool /*Op0IsKill*/,
1647 unsigned FastISel::FastEmit_rf(MVT, MVT,
1649 unsigned /*Op0*/, bool /*Op0IsKill*/,
1650 const ConstantFP * /*FPImm*/) {
1654 unsigned FastISel::FastEmit_rri(MVT, MVT,
1656 unsigned /*Op0*/, bool /*Op0IsKill*/,
1657 unsigned /*Op1*/, bool /*Op1IsKill*/,
1662 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
1663 /// to emit an instruction with an immediate operand using FastEmit_ri.
1664 /// If that fails, it materializes the immediate into a register and try
1665 /// FastEmit_rr instead.
1666 unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode,
1667 unsigned Op0, bool Op0IsKill,
1668 uint64_t Imm, MVT ImmType) {
1669 // If this is a multiply by a power of two, emit this as a shift left.
1670 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1673 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1674 // div x, 8 -> srl x, 3
1679 // Horrible hack (to be removed), check to make sure shift amounts are
1681 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1682 Imm >= VT.getSizeInBits())
1685 // First check if immediate type is legal. If not, we can't use the ri form.
1686 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1689 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1690 if (MaterialReg == 0) {
1691 // This is a bit ugly/slow, but failing here means falling out of
1692 // fast-isel, which would be very slow.
1693 IntegerType *ITy = IntegerType::get(FuncInfo.Fn->getContext(),
1694 VT.getSizeInBits());
1695 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1696 if (MaterialReg == 0) return 0;
1698 return FastEmit_rr(VT, VT, Opcode,
1700 MaterialReg, /*Kill=*/true);
1703 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
1704 return MRI.createVirtualRegister(RC);
1707 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II,
1708 unsigned Op, unsigned OpNum) {
1709 if (TargetRegisterInfo::isVirtualRegister(Op)) {
1710 const TargetRegisterClass *RegClass =
1711 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
1712 if (!MRI.constrainRegClass(Op, RegClass)) {
1713 // If it's not legal to COPY between the register classes, something
1714 // has gone very wrong before we got here.
1715 unsigned NewOp = createResultReg(RegClass);
1716 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1717 TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
1724 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
1725 const TargetRegisterClass* RC) {
1726 unsigned ResultReg = createResultReg(RC);
1727 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1729 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
1733 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
1734 const TargetRegisterClass *RC,
1735 unsigned Op0, bool Op0IsKill) {
1736 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1738 unsigned ResultReg = createResultReg(RC);
1739 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1741 if (II.getNumDefs() >= 1)
1742 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1743 .addReg(Op0, Op0IsKill * RegState::Kill);
1745 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1746 .addReg(Op0, Op0IsKill * RegState::Kill);
1747 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1748 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1754 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
1755 const TargetRegisterClass *RC,
1756 unsigned Op0, bool Op0IsKill,
1757 unsigned Op1, bool Op1IsKill) {
1758 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1760 unsigned ResultReg = createResultReg(RC);
1761 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1762 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1764 if (II.getNumDefs() >= 1)
1765 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1766 .addReg(Op0, Op0IsKill * RegState::Kill)
1767 .addReg(Op1, Op1IsKill * RegState::Kill);
1769 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1770 .addReg(Op0, Op0IsKill * RegState::Kill)
1771 .addReg(Op1, Op1IsKill * RegState::Kill);
1772 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1773 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1778 unsigned FastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
1779 const TargetRegisterClass *RC,
1780 unsigned Op0, bool Op0IsKill,
1781 unsigned Op1, bool Op1IsKill,
1782 unsigned Op2, bool Op2IsKill) {
1783 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1785 unsigned ResultReg = createResultReg(RC);
1786 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1787 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1788 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
1790 if (II.getNumDefs() >= 1)
1791 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1792 .addReg(Op0, Op0IsKill * RegState::Kill)
1793 .addReg(Op1, Op1IsKill * RegState::Kill)
1794 .addReg(Op2, Op2IsKill * RegState::Kill);
1796 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1797 .addReg(Op0, Op0IsKill * RegState::Kill)
1798 .addReg(Op1, Op1IsKill * RegState::Kill)
1799 .addReg(Op2, Op2IsKill * RegState::Kill);
1800 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1801 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1806 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
1807 const TargetRegisterClass *RC,
1808 unsigned Op0, bool Op0IsKill,
1810 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1812 unsigned ResultReg = createResultReg(RC);
1813 RC = TII.getRegClass(II, II.getNumDefs(), &TRI, *FuncInfo.MF);
1814 MRI.constrainRegClass(Op0, RC);
1816 if (II.getNumDefs() >= 1)
1817 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1818 .addReg(Op0, Op0IsKill * RegState::Kill)
1821 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1822 .addReg(Op0, Op0IsKill * RegState::Kill)
1824 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1825 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1830 unsigned FastISel::FastEmitInst_rii(unsigned MachineInstOpcode,
1831 const TargetRegisterClass *RC,
1832 unsigned Op0, bool Op0IsKill,
1833 uint64_t Imm1, uint64_t Imm2) {
1834 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1836 unsigned ResultReg = createResultReg(RC);
1837 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1839 if (II.getNumDefs() >= 1)
1840 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1841 .addReg(Op0, Op0IsKill * RegState::Kill)
1845 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1846 .addReg(Op0, Op0IsKill * RegState::Kill)
1849 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1850 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1855 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
1856 const TargetRegisterClass *RC,
1857 unsigned Op0, bool Op0IsKill,
1858 const ConstantFP *FPImm) {
1859 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1861 unsigned ResultReg = createResultReg(RC);
1862 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1864 if (II.getNumDefs() >= 1)
1865 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1866 .addReg(Op0, Op0IsKill * RegState::Kill)
1869 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1870 .addReg(Op0, Op0IsKill * RegState::Kill)
1872 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1873 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1878 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
1879 const TargetRegisterClass *RC,
1880 unsigned Op0, bool Op0IsKill,
1881 unsigned Op1, bool Op1IsKill,
1883 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1885 unsigned ResultReg = createResultReg(RC);
1886 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1887 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1889 if (II.getNumDefs() >= 1)
1890 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1891 .addReg(Op0, Op0IsKill * RegState::Kill)
1892 .addReg(Op1, Op1IsKill * RegState::Kill)
1895 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1896 .addReg(Op0, Op0IsKill * RegState::Kill)
1897 .addReg(Op1, Op1IsKill * RegState::Kill)
1899 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1900 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1905 unsigned FastISel::FastEmitInst_rrii(unsigned MachineInstOpcode,
1906 const TargetRegisterClass *RC,
1907 unsigned Op0, bool Op0IsKill,
1908 unsigned Op1, bool Op1IsKill,
1909 uint64_t Imm1, uint64_t Imm2) {
1910 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1912 unsigned ResultReg = createResultReg(RC);
1913 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1914 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1916 if (II.getNumDefs() >= 1)
1917 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1918 .addReg(Op0, Op0IsKill * RegState::Kill)
1919 .addReg(Op1, Op1IsKill * RegState::Kill)
1920 .addImm(Imm1).addImm(Imm2);
1922 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1923 .addReg(Op0, Op0IsKill * RegState::Kill)
1924 .addReg(Op1, Op1IsKill * RegState::Kill)
1925 .addImm(Imm1).addImm(Imm2);
1926 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1927 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1932 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
1933 const TargetRegisterClass *RC,
1935 unsigned ResultReg = createResultReg(RC);
1936 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1938 if (II.getNumDefs() >= 1)
1939 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg).addImm(Imm);
1941 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm);
1942 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1943 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1948 unsigned FastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
1949 const TargetRegisterClass *RC,
1950 uint64_t Imm1, uint64_t Imm2) {
1951 unsigned ResultReg = createResultReg(RC);
1952 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1954 if (II.getNumDefs() >= 1)
1955 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1956 .addImm(Imm1).addImm(Imm2);
1958 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm1).addImm(Imm2);
1959 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1960 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1965 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
1966 unsigned Op0, bool Op0IsKill,
1968 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1969 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1970 "Cannot yet extract from physregs");
1971 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
1972 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
1973 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
1974 DbgLoc, TII.get(TargetOpcode::COPY), ResultReg)
1975 .addReg(Op0, getKillRegState(Op0IsKill), Idx);
1979 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1980 /// with all but the least significant bit set to zero.
1981 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1982 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
1985 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
1986 /// Emit code to ensure constants are copied into registers when needed.
1987 /// Remember the virtual registers that need to be added to the Machine PHI
1988 /// nodes as input. We cannot just directly add them, because expansion
1989 /// might result in multiple MBB's for one BB. As such, the start of the
1990 /// BB might correspond to a different MBB than the end.
1991 bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
1992 const TerminatorInst *TI = LLVMBB->getTerminator();
1994 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
1995 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
1997 // Check successor nodes' PHI nodes that expect a constant to be available
1999 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
2000 const BasicBlock *SuccBB = TI->getSuccessor(succ);
2001 if (!isa<PHINode>(SuccBB->begin())) continue;
2002 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
2004 // If this terminator has multiple identical successors (common for
2005 // switches), only handle each succ once.
2006 if (!SuccsHandled.insert(SuccMBB)) continue;
2008 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
2010 // At this point we know that there is a 1-1 correspondence between LLVM PHI
2011 // nodes and Machine PHI nodes, but the incoming operands have not been
2013 for (BasicBlock::const_iterator I = SuccBB->begin();
2014 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
2016 // Ignore dead phi's.
2017 if (PN->use_empty()) continue;
2019 // Only handle legal types. Two interesting things to note here. First,
2020 // by bailing out early, we may leave behind some dead instructions,
2021 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
2022 // own moves. Second, this check is necessary because FastISel doesn't
2023 // use CreateRegs to create registers, so it always creates
2024 // exactly one register for each non-void instruction.
2025 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
2026 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
2027 // Handle integer promotions, though, because they're common and easy.
2028 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
2029 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT);
2031 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
2036 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
2038 // Set the DebugLoc for the copy. Prefer the location of the operand
2039 // if there is one; use the location of the PHI otherwise.
2040 DbgLoc = PN->getDebugLoc();
2041 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp))
2042 DbgLoc = Inst->getDebugLoc();
2044 unsigned Reg = getRegForValue(PHIOp);
2046 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
2049 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
2050 DbgLoc = DebugLoc();
2057 bool FastISel::tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst) {
2058 assert(LI->hasOneUse() &&
2059 "tryToFoldLoad expected a LoadInst with a single use");
2060 // We know that the load has a single use, but don't know what it is. If it
2061 // isn't one of the folded instructions, then we can't succeed here. Handle
2062 // this by scanning the single-use users of the load until we get to FoldInst.
2063 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
2065 const Instruction *TheUser = LI->user_back();
2066 while (TheUser != FoldInst && // Scan up until we find FoldInst.
2067 // Stay in the right block.
2068 TheUser->getParent() == FoldInst->getParent() &&
2069 --MaxUsers) { // Don't scan too far.
2070 // If there are multiple or no uses of this instruction, then bail out.
2071 if (!TheUser->hasOneUse())
2074 TheUser = TheUser->user_back();
2077 // If we didn't find the fold instruction, then we failed to collapse the
2079 if (TheUser != FoldInst)
2082 // Don't try to fold volatile loads. Target has to deal with alignment
2084 if (LI->isVolatile())
2087 // Figure out which vreg this is going into. If there is no assigned vreg yet
2088 // then there actually was no reference to it. Perhaps the load is referenced
2089 // by a dead instruction.
2090 unsigned LoadReg = getRegForValue(LI);
2094 // We can't fold if this vreg has no uses or more than one use. Multiple uses
2095 // may mean that the instruction got lowered to multiple MIs, or the use of
2096 // the loaded value ended up being multiple operands of the result.
2097 if (!MRI.hasOneUse(LoadReg))
2100 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg);
2101 MachineInstr *User = RI->getParent();
2103 // Set the insertion point properly. Folding the load can cause generation of
2104 // other random instructions (like sign extends) for addressing modes; make
2105 // sure they get inserted in a logical place before the new instruction.
2106 FuncInfo.InsertPt = User;
2107 FuncInfo.MBB = User->getParent();
2109 // Ask the target to try folding the load.
2110 return tryToFoldLoadIntoMI(User, RI.getOperandNo(), LI);
2113 bool FastISel::canFoldAddIntoGEP(const User *GEP, const Value *Add) {
2115 if (!isa<AddOperator>(Add))
2117 // Type size needs to match.
2118 if (DL.getTypeSizeInBits(GEP->getType()) !=
2119 DL.getTypeSizeInBits(Add->getType()))
2121 // Must be in the same basic block.
2122 if (isa<Instruction>(Add) &&
2123 FuncInfo.MBBMap[cast<Instruction>(Add)->getParent()] != FuncInfo.MBB)
2125 // Must have a constant operand.
2126 return isa<ConstantInt>(cast<AddOperator>(Add)->getOperand(1));
2130 FastISel::createMachineMemOperandFor(const Instruction *I) const {
2137 if (const auto *LI = dyn_cast<LoadInst>(I)) {
2138 Alignment = LI->getAlignment();
2139 IsVolatile = LI->isVolatile();
2140 Flags = MachineMemOperand::MOLoad;
2141 Ptr = LI->getPointerOperand();
2142 ValTy = LI->getType();
2143 } else if (const auto *SI = dyn_cast<StoreInst>(I)) {
2144 Alignment = SI->getAlignment();
2145 IsVolatile = SI->isVolatile();
2146 Flags = MachineMemOperand::MOStore;
2147 Ptr = SI->getPointerOperand();
2148 ValTy = SI->getValueOperand()->getType();
2153 bool IsNonTemporal = I->getMetadata("nontemporal") != nullptr;
2154 bool IsInvariant = I->getMetadata("invariant.load") != nullptr;
2155 const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range);
2158 I->getAAMetadata(AAInfo);
2160 if (Alignment == 0) // Ensure that codegen never sees alignment 0.
2161 Alignment = DL.getABITypeAlignment(ValTy);
2164 TM.getSubtargetImpl()->getDataLayout()->getTypeStoreSize(ValTy);
2167 Flags |= MachineMemOperand::MOVolatile;
2169 Flags |= MachineMemOperand::MONonTemporal;
2171 Flags |= MachineMemOperand::MOInvariant;
2173 return FuncInfo.MF->getMachineMemOperand(MachinePointerInfo(Ptr), Flags, Size,
2174 Alignment, AAInfo, Ranges);