1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/DebugLoc.h"
51 #include "llvm/CodeGen/DwarfWriter.h"
52 #include "llvm/Analysis/DebugInfo.h"
53 #include "llvm/Target/TargetData.h"
54 #include "llvm/Target/TargetInstrInfo.h"
55 #include "llvm/Target/TargetLowering.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "SelectionDAGBuild.h"
60 unsigned FastISel::getRegForValue(Value *V) {
61 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
62 // Don't handle non-simple values in FastISel.
63 if (!RealVT.isSimple())
66 // Ignore illegal types. We must do this before looking up the value
67 // in ValueMap because Arguments are given virtual registers regardless
68 // of whether FastISel can handle them.
69 MVT::SimpleValueType VT = RealVT.getSimpleVT();
70 if (!TLI.isTypeLegal(VT)) {
71 // Promote MVT::i1 to a legal type though, because it's common and easy.
73 VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
78 // Look up the value to see if we already have a register for it. We
79 // cache values defined by Instructions across blocks, and other values
80 // only locally. This is because Instructions already have the SSA
81 // def-dominatess-use requirement enforced.
82 if (ValueMap.count(V))
84 unsigned Reg = LocalValueMap[V];
88 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
89 if (CI->getValue().getActiveBits() <= 64)
90 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
91 } else if (isa<AllocaInst>(V)) {
92 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
93 } else if (isa<ConstantPointerNull>(V)) {
94 // Translate this as an integer zero so that it can be
95 // local-CSE'd with actual integer zeros.
96 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType()));
97 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
98 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
101 const APFloat &Flt = CF->getValueAPF();
102 MVT IntVT = TLI.getPointerTy();
105 uint32_t IntBitWidth = IntVT.getSizeInBits();
107 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
108 APFloat::rmTowardZero, &isExact);
110 APInt IntVal(IntBitWidth, 2, x);
112 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal));
114 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
117 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
118 if (!SelectOperator(CE, CE->getOpcode())) return 0;
119 Reg = LocalValueMap[CE];
120 } else if (isa<UndefValue>(V)) {
121 Reg = createResultReg(TLI.getRegClassFor(VT));
122 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
125 // If target-independent code couldn't handle the value, give target-specific
127 if (!Reg && isa<Constant>(V))
128 Reg = TargetMaterializeConstant(cast<Constant>(V));
130 // Don't cache constant materializations in the general ValueMap.
131 // To do so would require tracking what uses they dominate.
133 LocalValueMap[V] = Reg;
137 unsigned FastISel::lookUpRegForValue(Value *V) {
138 // Look up the value to see if we already have a register for it. We
139 // cache values defined by Instructions across blocks, and other values
140 // only locally. This is because Instructions already have the SSA
141 // def-dominatess-use requirement enforced.
142 if (ValueMap.count(V))
144 return LocalValueMap[V];
147 /// UpdateValueMap - Update the value map to include the new mapping for this
148 /// instruction, or insert an extra copy to get the result in a previous
149 /// determined register.
150 /// NOTE: This is only necessary because we might select a block that uses
151 /// a value before we select the block that defines the value. It might be
152 /// possible to fix this by selecting blocks in reverse postorder.
153 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
154 if (!isa<Instruction>(I)) {
155 LocalValueMap[I] = Reg;
159 unsigned &AssignedReg = ValueMap[I];
160 if (AssignedReg == 0)
162 else if (Reg != AssignedReg) {
163 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
164 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
165 Reg, RegClass, RegClass);
170 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
171 unsigned IdxN = getRegForValue(Idx);
173 // Unhandled operand. Halt "fast" selection and bail.
176 // If the index is smaller or larger than intptr_t, truncate or extend it.
177 MVT PtrVT = TLI.getPointerTy();
178 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
179 if (IdxVT.bitsLT(PtrVT))
180 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
181 ISD::SIGN_EXTEND, IdxN);
182 else if (IdxVT.bitsGT(PtrVT))
183 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
184 ISD::TRUNCATE, IdxN);
188 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
189 /// which has an opcode which directly corresponds to the given ISD opcode.
191 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
192 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
193 if (VT == MVT::Other || !VT.isSimple())
194 // Unhandled type. Halt "fast" selection and bail.
197 // We only handle legal types. For example, on x86-32 the instruction
198 // selector contains all of the 64-bit instructions from x86-64,
199 // under the assumption that i64 won't be used if the target doesn't
201 if (!TLI.isTypeLegal(VT)) {
202 // MVT::i1 is special. Allow AND, OR, or XOR because they
203 // don't require additional zeroing, which makes them easy.
205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
206 ISDOpcode == ISD::XOR))
207 VT = TLI.getTypeToTransformTo(VT);
212 unsigned Op0 = getRegForValue(I->getOperand(0));
214 // Unhandled operand. Halt "fast" selection and bail.
217 // Check if the second operand is a constant and handle it appropriately.
218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
220 ISDOpcode, Op0, CI->getZExtValue());
221 if (ResultReg != 0) {
222 // We successfully emitted code for the given LLVM Instruction.
223 UpdateValueMap(I, ResultReg);
228 // Check if the second operand is a constant float.
229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
232 if (ResultReg != 0) {
233 // We successfully emitted code for the given LLVM Instruction.
234 UpdateValueMap(I, ResultReg);
239 unsigned Op1 = getRegForValue(I->getOperand(1));
241 // Unhandled operand. Halt "fast" selection and bail.
244 // Now we have both operands in registers. Emit the instruction.
245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
246 ISDOpcode, Op0, Op1);
248 // Target-specific code wasn't able to find a machine opcode for
249 // the given ISD opcode and type. Halt "fast" selection and bail.
252 // We successfully emitted code for the given LLVM Instruction.
253 UpdateValueMap(I, ResultReg);
257 bool FastISel::SelectGetElementPtr(User *I) {
258 unsigned N = getRegForValue(I->getOperand(0));
260 // Unhandled operand. Halt "fast" selection and bail.
263 const Type *Ty = I->getOperand(0)->getType();
264 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
273 // FIXME: This can be optimized by combining the add with a
275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
277 // Unhandled operand. Halt "fast" selection and bail.
280 Ty = StTy->getElementType(Field);
282 Ty = cast<SequentialType>(Ty)->getElementType();
284 // If this is a constant subscript, handle it quickly.
285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
286 if (CI->getZExtValue() == 0) continue;
288 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
291 // Unhandled operand. Halt "fast" selection and bail.
296 // N = N + Idx * ElementSize;
297 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
298 unsigned IdxN = getRegForGEPIndex(Idx);
300 // Unhandled operand. Halt "fast" selection and bail.
303 if (ElementSize != 1) {
304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
306 // Unhandled operand. Halt "fast" selection and bail.
309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
311 // Unhandled operand. Halt "fast" selection and bail.
316 // We successfully emitted code for the given LLVM Instruction.
317 UpdateValueMap(I, N);
321 bool FastISel::SelectCall(User *I) {
322 Function *F = cast<CallInst>(I)->getCalledFunction();
323 if (!F) return false;
325 unsigned IID = F->getIntrinsicID();
328 case Intrinsic::dbg_stoppoint: {
329 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
330 if (DIDescriptor::ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) {
331 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
332 unsigned Line = SPI->getLine();
333 unsigned Col = SPI->getColumn();
334 unsigned Idx = MF.getOrCreateDebugLocID(CU.getGV(), Line, Col);
335 setCurDebugLoc(DebugLoc::get(Idx));
339 case Intrinsic::dbg_region_start: {
340 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
341 if (DIDescriptor::ValidDebugInfo(RSI->getContext(), CodeGenOpt::None) &&
342 DW && DW->ShouldEmitDwarfDebug()) {
344 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
345 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
346 BuildMI(MBB, DL, II).addImm(ID);
350 case Intrinsic::dbg_region_end: {
351 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
352 if (DIDescriptor::ValidDebugInfo(REI->getContext(), CodeGenOpt::None) &&
353 DW && DW->ShouldEmitDwarfDebug()) {
355 DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
356 if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
357 // This is end of an inlined function.
358 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
359 ID = DW->RecordInlinedFnEnd(Subprogram);
361 // Returned ID is 0 if this is unbalanced "end of inlined
362 // scope". This could happen if optimizer eats dbg intrinsics
363 // or "beginning of inlined scope" is not recoginized due to
364 // missing location info. In such cases, do ignore this region.end.
365 BuildMI(MBB, DL, II).addImm(ID);
367 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
368 ID = DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext()));
369 BuildMI(MBB, DL, II).addImm(ID);
374 case Intrinsic::dbg_func_start: {
375 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
376 Value *SP = FSI->getSubprogram();
377 if (!DIDescriptor::ValidDebugInfo(SP, CodeGenOpt::None))
380 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
381 // (most?) gdb expects.
382 DebugLoc PrevLoc = DL;
383 DISubprogram Subprogram(cast<GlobalVariable>(SP));
384 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
386 if (!Subprogram.describes(MF.getFunction())) {
387 // This is a beginning of an inlined function.
389 // If llvm.dbg.func.start is seen in a new block before any
390 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
391 // FIXME : Why DebugLoc is reset at the beginning of each block ?
392 if (PrevLoc.isUnknown())
394 // Record the source line.
395 unsigned Line = Subprogram.getLineNumber();
396 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(
397 CompileUnit.getGV(), Line, 0)));
399 if (DW && DW->ShouldEmitDwarfDebug()) {
400 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
401 unsigned LabelID = DW->RecordInlinedFnStart(Subprogram,
402 DICompileUnit(PrevLocTpl.CompileUnit),
405 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
406 BuildMI(MBB, DL, II).addImm(LabelID);
409 // Record the source line.
410 unsigned Line = Subprogram.getLineNumber();
411 MF.setDefaultDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(
412 CompileUnit.getGV(), Line, 0)));
413 if (DW && DW->ShouldEmitDwarfDebug()) {
414 // llvm.dbg.func_start also defines beginning of function scope.
415 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
421 case Intrinsic::dbg_declare: {
422 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
423 Value *Variable = DI->getVariable();
424 if (DIDescriptor::ValidDebugInfo(Variable, CodeGenOpt::None) &&
425 DW && DW->ShouldEmitDwarfDebug()) {
426 // Determine the address of the declared object.
427 Value *Address = DI->getAddress();
428 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
429 Address = BCI->getOperand(0);
430 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
431 // Don't handle byval struct arguments or VLAs, for example.
433 DenseMap<const AllocaInst*, int>::iterator SI =
434 StaticAllocaMap.find(AI);
435 if (SI == StaticAllocaMap.end()) break; // VLAs.
438 // Determine the debug globalvariable.
439 GlobalValue *GV = cast<GlobalVariable>(Variable);
441 // Build the DECLARE instruction.
442 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
443 MachineInstr *DeclareMI
444 = BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV);
445 DIVariable DV(cast<GlobalVariable>(GV));
447 // This is a local variable
448 DW->RecordVariableScope(DV, DeclareMI);
453 case Intrinsic::eh_exception: {
454 MVT VT = TLI.getValueType(I->getType());
455 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
457 case TargetLowering::Expand: {
458 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
459 unsigned Reg = TLI.getExceptionAddressRegister();
460 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
461 unsigned ResultReg = createResultReg(RC);
462 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
464 assert(InsertedCopy && "Can't copy address registers!");
465 InsertedCopy = InsertedCopy;
466 UpdateValueMap(I, ResultReg);
472 case Intrinsic::eh_selector_i32:
473 case Intrinsic::eh_selector_i64: {
474 MVT VT = TLI.getValueType(I->getType());
475 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
477 case TargetLowering::Expand: {
478 MVT VT = (IID == Intrinsic::eh_selector_i32 ?
479 MVT::i32 : MVT::i64);
482 if (MBB->isLandingPad())
483 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
486 CatchInfoLost.insert(cast<CallInst>(I));
488 // FIXME: Mark exception selector register as live in. Hack for PR1508.
489 unsigned Reg = TLI.getExceptionSelectorRegister();
490 if (Reg) MBB->addLiveIn(Reg);
493 unsigned Reg = TLI.getExceptionSelectorRegister();
494 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
495 unsigned ResultReg = createResultReg(RC);
496 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
498 assert(InsertedCopy && "Can't copy address registers!");
499 InsertedCopy = InsertedCopy;
500 UpdateValueMap(I, ResultReg);
503 getRegForValue(Constant::getNullValue(I->getType()));
504 UpdateValueMap(I, ResultReg);
515 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
516 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
517 MVT DstVT = TLI.getValueType(I->getType());
519 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
520 DstVT == MVT::Other || !DstVT.isSimple())
521 // Unhandled type. Halt "fast" selection and bail.
524 // Check if the destination type is legal. Or as a special case,
525 // it may be i1 if we're doing a truncate because that's
526 // easy and somewhat common.
527 if (!TLI.isTypeLegal(DstVT))
528 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
529 // Unhandled type. Halt "fast" selection and bail.
532 // Check if the source operand is legal. Or as a special case,
533 // it may be i1 if we're doing zero-extension because that's
534 // easy and somewhat common.
535 if (!TLI.isTypeLegal(SrcVT))
536 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
537 // Unhandled type. Halt "fast" selection and bail.
540 unsigned InputReg = getRegForValue(I->getOperand(0));
542 // Unhandled operand. Halt "fast" selection and bail.
545 // If the operand is i1, arrange for the high bits in the register to be zero.
546 if (SrcVT == MVT::i1) {
547 SrcVT = TLI.getTypeToTransformTo(SrcVT);
548 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
552 // If the result is i1, truncate to the target's type for i1 first.
553 if (DstVT == MVT::i1)
554 DstVT = TLI.getTypeToTransformTo(DstVT);
556 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
563 UpdateValueMap(I, ResultReg);
567 bool FastISel::SelectBitCast(User *I) {
568 // If the bitcast doesn't change the type, just use the operand value.
569 if (I->getType() == I->getOperand(0)->getType()) {
570 unsigned Reg = getRegForValue(I->getOperand(0));
573 UpdateValueMap(I, Reg);
577 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
578 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
579 MVT DstVT = TLI.getValueType(I->getType());
581 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
582 DstVT == MVT::Other || !DstVT.isSimple() ||
583 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
584 // Unhandled type. Halt "fast" selection and bail.
587 unsigned Op0 = getRegForValue(I->getOperand(0));
589 // Unhandled operand. Halt "fast" selection and bail.
592 // First, try to perform the bitcast by inserting a reg-reg copy.
593 unsigned ResultReg = 0;
594 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
595 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
596 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
597 ResultReg = createResultReg(DstClass);
599 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
600 Op0, DstClass, SrcClass);
605 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
607 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
608 ISD::BIT_CONVERT, Op0);
613 UpdateValueMap(I, ResultReg);
618 FastISel::SelectInstruction(Instruction *I) {
619 return SelectOperator(I, I->getOpcode());
622 /// FastEmitBranch - Emit an unconditional branch to the given block,
623 /// unless it is the immediate (fall-through) successor, and update
626 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
627 MachineFunction::iterator NextMBB =
628 next(MachineFunction::iterator(MBB));
630 if (MBB->isLayoutSuccessor(MSucc)) {
631 // The unconditional fall-through case, which needs no instructions.
633 // The unconditional branch case.
634 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
636 MBB->addSuccessor(MSucc);
640 FastISel::SelectOperator(User *I, unsigned Opcode) {
642 case Instruction::Add: {
643 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
644 return SelectBinaryOp(I, Opc);
646 case Instruction::Sub: {
647 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
648 return SelectBinaryOp(I, Opc);
650 case Instruction::Mul: {
651 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
652 return SelectBinaryOp(I, Opc);
654 case Instruction::SDiv:
655 return SelectBinaryOp(I, ISD::SDIV);
656 case Instruction::UDiv:
657 return SelectBinaryOp(I, ISD::UDIV);
658 case Instruction::FDiv:
659 return SelectBinaryOp(I, ISD::FDIV);
660 case Instruction::SRem:
661 return SelectBinaryOp(I, ISD::SREM);
662 case Instruction::URem:
663 return SelectBinaryOp(I, ISD::UREM);
664 case Instruction::FRem:
665 return SelectBinaryOp(I, ISD::FREM);
666 case Instruction::Shl:
667 return SelectBinaryOp(I, ISD::SHL);
668 case Instruction::LShr:
669 return SelectBinaryOp(I, ISD::SRL);
670 case Instruction::AShr:
671 return SelectBinaryOp(I, ISD::SRA);
672 case Instruction::And:
673 return SelectBinaryOp(I, ISD::AND);
674 case Instruction::Or:
675 return SelectBinaryOp(I, ISD::OR);
676 case Instruction::Xor:
677 return SelectBinaryOp(I, ISD::XOR);
679 case Instruction::GetElementPtr:
680 return SelectGetElementPtr(I);
682 case Instruction::Br: {
683 BranchInst *BI = cast<BranchInst>(I);
685 if (BI->isUnconditional()) {
686 BasicBlock *LLVMSucc = BI->getSuccessor(0);
687 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
688 FastEmitBranch(MSucc);
692 // Conditional branches are not handed yet.
693 // Halt "fast" selection and bail.
697 case Instruction::Unreachable:
701 case Instruction::PHI:
702 // PHI nodes are already emitted.
705 case Instruction::Alloca:
706 // FunctionLowering has the static-sized case covered.
707 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
710 // Dynamic-sized alloca is not handled yet.
713 case Instruction::Call:
714 return SelectCall(I);
716 case Instruction::BitCast:
717 return SelectBitCast(I);
719 case Instruction::FPToSI:
720 return SelectCast(I, ISD::FP_TO_SINT);
721 case Instruction::ZExt:
722 return SelectCast(I, ISD::ZERO_EXTEND);
723 case Instruction::SExt:
724 return SelectCast(I, ISD::SIGN_EXTEND);
725 case Instruction::Trunc:
726 return SelectCast(I, ISD::TRUNCATE);
727 case Instruction::SIToFP:
728 return SelectCast(I, ISD::SINT_TO_FP);
730 case Instruction::IntToPtr: // Deliberate fall-through.
731 case Instruction::PtrToInt: {
732 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
733 MVT DstVT = TLI.getValueType(I->getType());
734 if (DstVT.bitsGT(SrcVT))
735 return SelectCast(I, ISD::ZERO_EXTEND);
736 if (DstVT.bitsLT(SrcVT))
737 return SelectCast(I, ISD::TRUNCATE);
738 unsigned Reg = getRegForValue(I->getOperand(0));
739 if (Reg == 0) return false;
740 UpdateValueMap(I, Reg);
745 // Unhandled instruction. Halt "fast" selection and bail.
750 FastISel::FastISel(MachineFunction &mf,
751 MachineModuleInfo *mmi,
753 DenseMap<const Value *, unsigned> &vm,
754 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
755 DenseMap<const AllocaInst *, int> &am
757 , SmallSet<Instruction*, 8> &cil
770 MRI(MF.getRegInfo()),
771 MFI(*MF.getFrameInfo()),
772 MCP(*MF.getConstantPool()),
774 TD(*TM.getTargetData()),
775 TII(*TM.getInstrInfo()),
776 TLI(*TM.getTargetLowering()) {
779 FastISel::~FastISel() {}
781 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
786 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
787 ISD::NodeType, unsigned /*Op0*/) {
791 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
792 ISD::NodeType, unsigned /*Op0*/,
797 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
798 ISD::NodeType, uint64_t /*Imm*/) {
802 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
803 ISD::NodeType, ConstantFP * /*FPImm*/) {
807 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
808 ISD::NodeType, unsigned /*Op0*/,
813 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
814 ISD::NodeType, unsigned /*Op0*/,
815 ConstantFP * /*FPImm*/) {
819 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
821 unsigned /*Op0*/, unsigned /*Op1*/,
826 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
827 /// to emit an instruction with an immediate operand using FastEmit_ri.
828 /// If that fails, it materializes the immediate into a register and try
829 /// FastEmit_rr instead.
830 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
831 unsigned Op0, uint64_t Imm,
832 MVT::SimpleValueType ImmType) {
833 // First check if immediate type is legal. If not, we can't use the ri form.
834 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
837 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
838 if (MaterialReg == 0)
840 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
843 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
844 /// to emit an instruction with a floating-point immediate operand using
845 /// FastEmit_rf. If that fails, it materializes the immediate into a register
846 /// and try FastEmit_rr instead.
847 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
848 unsigned Op0, ConstantFP *FPImm,
849 MVT::SimpleValueType ImmType) {
850 // First check if immediate type is legal. If not, we can't use the rf form.
851 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
855 // Materialize the constant in a register.
856 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
857 if (MaterialReg == 0) {
858 // If the target doesn't have a way to directly enter a floating-point
859 // value into a register, use an alternate approach.
860 // TODO: The current approach only supports floating-point constants
861 // that can be constructed by conversion from integer values. This should
862 // be replaced by code that creates a load from a constant-pool entry,
863 // which will require some target-specific work.
864 const APFloat &Flt = FPImm->getValueAPF();
865 MVT IntVT = TLI.getPointerTy();
868 uint32_t IntBitWidth = IntVT.getSizeInBits();
870 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
871 APFloat::rmTowardZero, &isExact);
874 APInt IntVal(IntBitWidth, 2, x);
876 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
877 ISD::Constant, IntVal.getZExtValue());
880 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
881 ISD::SINT_TO_FP, IntegerReg);
882 if (MaterialReg == 0)
885 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
888 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
889 return MRI.createVirtualRegister(RC);
892 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
893 const TargetRegisterClass* RC) {
894 unsigned ResultReg = createResultReg(RC);
895 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
897 BuildMI(MBB, DL, II, ResultReg);
901 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
902 const TargetRegisterClass *RC,
904 unsigned ResultReg = createResultReg(RC);
905 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
907 if (II.getNumDefs() >= 1)
908 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
910 BuildMI(MBB, DL, II).addReg(Op0);
911 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
912 II.ImplicitDefs[0], RC, RC);
920 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
921 const TargetRegisterClass *RC,
922 unsigned Op0, unsigned Op1) {
923 unsigned ResultReg = createResultReg(RC);
924 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
926 if (II.getNumDefs() >= 1)
927 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
929 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
930 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
931 II.ImplicitDefs[0], RC, RC);
938 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
939 const TargetRegisterClass *RC,
940 unsigned Op0, uint64_t Imm) {
941 unsigned ResultReg = createResultReg(RC);
942 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
944 if (II.getNumDefs() >= 1)
945 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
947 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
948 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
949 II.ImplicitDefs[0], RC, RC);
956 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
957 const TargetRegisterClass *RC,
958 unsigned Op0, ConstantFP *FPImm) {
959 unsigned ResultReg = createResultReg(RC);
960 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
962 if (II.getNumDefs() >= 1)
963 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
965 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
966 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
967 II.ImplicitDefs[0], RC, RC);
974 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
975 const TargetRegisterClass *RC,
976 unsigned Op0, unsigned Op1, uint64_t Imm) {
977 unsigned ResultReg = createResultReg(RC);
978 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
980 if (II.getNumDefs() >= 1)
981 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
983 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
984 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
985 II.ImplicitDefs[0], RC, RC);
992 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
993 const TargetRegisterClass *RC,
995 unsigned ResultReg = createResultReg(RC);
996 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
998 if (II.getNumDefs() >= 1)
999 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
1001 BuildMI(MBB, DL, II).addImm(Imm);
1002 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1003 II.ImplicitDefs[0], RC, RC);
1010 unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
1011 unsigned Op0, uint32_t Idx) {
1012 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
1014 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1015 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
1017 if (II.getNumDefs() >= 1)
1018 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
1020 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
1021 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1022 II.ImplicitDefs[0], RC, RC);
1029 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1030 /// with all but the least significant bit set to zero.
1031 unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
1032 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);