1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/DwarfWriter.h"
51 #include "llvm/Analysis/DebugInfo.h"
52 #include "llvm/Target/TargetData.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "SelectionDAGBuild.h"
59 unsigned FastISel::getRegForValue(Value *V) {
60 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
61 // Don't handle non-simple values in FastISel.
62 if (!RealVT.isSimple())
65 // Ignore illegal types. We must do this before looking up the value
66 // in ValueMap because Arguments are given virtual registers regardless
67 // of whether FastISel can handle them.
68 MVT::SimpleValueType VT = RealVT.getSimpleVT();
69 if (!TLI.isTypeLegal(VT)) {
70 // Promote MVT::i1 to a legal type though, because it's common and easy.
72 VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
77 // Look up the value to see if we already have a register for it. We
78 // cache values defined by Instructions across blocks, and other values
79 // only locally. This is because Instructions already have the SSA
80 // def-dominatess-use requirement enforced.
81 if (ValueMap.count(V))
83 unsigned Reg = LocalValueMap[V];
87 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
88 if (CI->getValue().getActiveBits() <= 64)
89 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
90 } else if (isa<AllocaInst>(V)) {
91 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
92 } else if (isa<ConstantPointerNull>(V)) {
93 // Translate this as an integer zero so that it can be
94 // local-CSE'd with actual integer zeros.
95 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType()));
96 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
97 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
100 const APFloat &Flt = CF->getValueAPF();
101 MVT IntVT = TLI.getPointerTy();
104 uint32_t IntBitWidth = IntVT.getSizeInBits();
106 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
107 APFloat::rmTowardZero, &isExact);
109 APInt IntVal(IntBitWidth, 2, x);
111 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal));
113 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
116 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
117 if (!SelectOperator(CE, CE->getOpcode())) return 0;
118 Reg = LocalValueMap[CE];
119 } else if (isa<UndefValue>(V)) {
120 Reg = createResultReg(TLI.getRegClassFor(VT));
121 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
124 // If target-independent code couldn't handle the value, give target-specific
126 if (!Reg && isa<Constant>(V))
127 Reg = TargetMaterializeConstant(cast<Constant>(V));
129 // Don't cache constant materializations in the general ValueMap.
130 // To do so would require tracking what uses they dominate.
132 LocalValueMap[V] = Reg;
136 unsigned FastISel::lookUpRegForValue(Value *V) {
137 // Look up the value to see if we already have a register for it. We
138 // cache values defined by Instructions across blocks, and other values
139 // only locally. This is because Instructions already have the SSA
140 // def-dominatess-use requirement enforced.
141 if (ValueMap.count(V))
143 return LocalValueMap[V];
146 /// UpdateValueMap - Update the value map to include the new mapping for this
147 /// instruction, or insert an extra copy to get the result in a previous
148 /// determined register.
149 /// NOTE: This is only necessary because we might select a block that uses
150 /// a value before we select the block that defines the value. It might be
151 /// possible to fix this by selecting blocks in reverse postorder.
152 void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
153 if (!isa<Instruction>(I)) {
154 LocalValueMap[I] = Reg;
157 if (!ValueMap.count(I))
160 TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
161 Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
164 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
165 unsigned IdxN = getRegForValue(Idx);
167 // Unhandled operand. Halt "fast" selection and bail.
170 // If the index is smaller or larger than intptr_t, truncate or extend it.
171 MVT PtrVT = TLI.getPointerTy();
172 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
173 if (IdxVT.bitsLT(PtrVT))
174 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
175 ISD::SIGN_EXTEND, IdxN);
176 else if (IdxVT.bitsGT(PtrVT))
177 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
178 ISD::TRUNCATE, IdxN);
182 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
183 /// which has an opcode which directly corresponds to the given ISD opcode.
185 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
186 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
187 if (VT == MVT::Other || !VT.isSimple())
188 // Unhandled type. Halt "fast" selection and bail.
191 // We only handle legal types. For example, on x86-32 the instruction
192 // selector contains all of the 64-bit instructions from x86-64,
193 // under the assumption that i64 won't be used if the target doesn't
195 if (!TLI.isTypeLegal(VT)) {
196 // MVT::i1 is special. Allow AND, OR, or XOR because they
197 // don't require additional zeroing, which makes them easy.
199 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
200 ISDOpcode == ISD::XOR))
201 VT = TLI.getTypeToTransformTo(VT);
206 unsigned Op0 = getRegForValue(I->getOperand(0));
208 // Unhandled operand. Halt "fast" selection and bail.
211 // Check if the second operand is a constant and handle it appropriately.
212 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
213 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
214 ISDOpcode, Op0, CI->getZExtValue());
215 if (ResultReg != 0) {
216 // We successfully emitted code for the given LLVM Instruction.
217 UpdateValueMap(I, ResultReg);
222 // Check if the second operand is a constant float.
223 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
224 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
226 if (ResultReg != 0) {
227 // We successfully emitted code for the given LLVM Instruction.
228 UpdateValueMap(I, ResultReg);
233 unsigned Op1 = getRegForValue(I->getOperand(1));
235 // Unhandled operand. Halt "fast" selection and bail.
238 // Now we have both operands in registers. Emit the instruction.
239 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
240 ISDOpcode, Op0, Op1);
242 // Target-specific code wasn't able to find a machine opcode for
243 // the given ISD opcode and type. Halt "fast" selection and bail.
246 // We successfully emitted code for the given LLVM Instruction.
247 UpdateValueMap(I, ResultReg);
251 bool FastISel::SelectGetElementPtr(User *I) {
252 unsigned N = getRegForValue(I->getOperand(0));
254 // Unhandled operand. Halt "fast" selection and bail.
257 const Type *Ty = I->getOperand(0)->getType();
258 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
259 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
262 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
263 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
266 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
267 // FIXME: This can be optimized by combining the add with a
269 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
271 // Unhandled operand. Halt "fast" selection and bail.
274 Ty = StTy->getElementType(Field);
276 Ty = cast<SequentialType>(Ty)->getElementType();
278 // If this is a constant subscript, handle it quickly.
279 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
280 if (CI->getZExtValue() == 0) continue;
282 TD.getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
283 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
285 // Unhandled operand. Halt "fast" selection and bail.
290 // N = N + Idx * ElementSize;
291 uint64_t ElementSize = TD.getTypePaddedSize(Ty);
292 unsigned IdxN = getRegForGEPIndex(Idx);
294 // Unhandled operand. Halt "fast" selection and bail.
297 if (ElementSize != 1) {
298 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
300 // Unhandled operand. Halt "fast" selection and bail.
303 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
305 // Unhandled operand. Halt "fast" selection and bail.
310 // We successfully emitted code for the given LLVM Instruction.
311 UpdateValueMap(I, N);
315 bool FastISel::SelectCall(User *I) {
316 Function *F = cast<CallInst>(I)->getCalledFunction();
317 if (!F) return false;
319 unsigned IID = F->getIntrinsicID();
322 case Intrinsic::dbg_stoppoint: {
323 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
324 if (DW && DW->ValidDebugInfo(SPI->getContext())) {
325 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
327 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
329 unsigned Line = SPI->getLine();
330 unsigned Col = SPI->getColumn();
331 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
332 unsigned Idx = MF.getOrCreateDebugLocID(SrcFile, Line, Col);
333 setCurDebugLoc(DebugLoc::get(Idx));
334 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
335 BuildMI(MBB, DL, II).addImm(ID);
339 case Intrinsic::dbg_region_start: {
340 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
341 if (DW && DW->ValidDebugInfo(RSI->getContext())) {
343 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
344 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
345 BuildMI(MBB, DL, II).addImm(ID);
349 case Intrinsic::dbg_region_end: {
350 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
351 if (DW && DW->ValidDebugInfo(REI->getContext())) {
353 DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext()));
354 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
355 BuildMI(MBB, DL, II).addImm(ID);
359 case Intrinsic::dbg_func_start: {
360 if (!DW) return true;
361 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
362 Value *SP = FSI->getSubprogram();
364 if (DW->ValidDebugInfo(SP)) {
365 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
366 // (most?) gdb expects.
367 DISubprogram Subprogram(cast<GlobalVariable>(SP));
368 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
370 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(Dir),
371 CompileUnit.getFilename(FN));
373 // Record the source line.
374 unsigned Line = Subprogram.getLineNumber();
375 DW->RecordSourceLine(Line, 0, SrcFile);
376 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
378 // llvm.dbg.func_start also defines beginning of function scope.
379 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
384 case Intrinsic::dbg_declare: {
385 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
386 Value *Variable = DI->getVariable();
387 if (DW && DW->ValidDebugInfo(Variable)) {
388 // Determine the address of the declared object.
389 Value *Address = DI->getAddress();
390 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
391 Address = BCI->getOperand(0);
392 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
393 // Don't handle byval struct arguments or VLAs, for example.
395 DenseMap<const AllocaInst*, int>::iterator SI =
396 StaticAllocaMap.find(AI);
397 if (SI == StaticAllocaMap.end()) break; // VLAs.
400 // Determine the debug globalvariable.
401 GlobalValue *GV = cast<GlobalVariable>(Variable);
403 // Build the DECLARE instruction.
404 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
405 BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV);
409 case Intrinsic::eh_exception: {
410 MVT VT = TLI.getValueType(I->getType());
411 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
413 case TargetLowering::Expand: {
414 if (!MBB->isLandingPad()) {
415 // FIXME: Mark exception register as live in. Hack for PR1508.
416 unsigned Reg = TLI.getExceptionAddressRegister();
417 if (Reg) MBB->addLiveIn(Reg);
419 unsigned Reg = TLI.getExceptionAddressRegister();
420 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
421 unsigned ResultReg = createResultReg(RC);
422 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
424 assert(InsertedCopy && "Can't copy address registers!");
425 InsertedCopy = InsertedCopy;
426 UpdateValueMap(I, ResultReg);
432 case Intrinsic::eh_selector_i32:
433 case Intrinsic::eh_selector_i64: {
434 MVT VT = TLI.getValueType(I->getType());
435 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
437 case TargetLowering::Expand: {
438 MVT VT = (IID == Intrinsic::eh_selector_i32 ?
439 MVT::i32 : MVT::i64);
442 if (MBB->isLandingPad())
443 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
446 CatchInfoLost.insert(cast<CallInst>(I));
448 // FIXME: Mark exception selector register as live in. Hack for PR1508.
449 unsigned Reg = TLI.getExceptionSelectorRegister();
450 if (Reg) MBB->addLiveIn(Reg);
453 unsigned Reg = TLI.getExceptionSelectorRegister();
454 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
455 unsigned ResultReg = createResultReg(RC);
456 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
458 assert(InsertedCopy && "Can't copy address registers!");
459 InsertedCopy = InsertedCopy;
460 UpdateValueMap(I, ResultReg);
463 getRegForValue(Constant::getNullValue(I->getType()));
464 UpdateValueMap(I, ResultReg);
475 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
476 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
477 MVT DstVT = TLI.getValueType(I->getType());
479 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
480 DstVT == MVT::Other || !DstVT.isSimple())
481 // Unhandled type. Halt "fast" selection and bail.
484 // Check if the destination type is legal. Or as a special case,
485 // it may be i1 if we're doing a truncate because that's
486 // easy and somewhat common.
487 if (!TLI.isTypeLegal(DstVT))
488 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
489 // Unhandled type. Halt "fast" selection and bail.
492 // Check if the source operand is legal. Or as a special case,
493 // it may be i1 if we're doing zero-extension because that's
494 // easy and somewhat common.
495 if (!TLI.isTypeLegal(SrcVT))
496 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
497 // Unhandled type. Halt "fast" selection and bail.
500 unsigned InputReg = getRegForValue(I->getOperand(0));
502 // Unhandled operand. Halt "fast" selection and bail.
505 // If the operand is i1, arrange for the high bits in the register to be zero.
506 if (SrcVT == MVT::i1) {
507 SrcVT = TLI.getTypeToTransformTo(SrcVT);
508 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
512 // If the result is i1, truncate to the target's type for i1 first.
513 if (DstVT == MVT::i1)
514 DstVT = TLI.getTypeToTransformTo(DstVT);
516 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
523 UpdateValueMap(I, ResultReg);
527 bool FastISel::SelectBitCast(User *I) {
528 // If the bitcast doesn't change the type, just use the operand value.
529 if (I->getType() == I->getOperand(0)->getType()) {
530 unsigned Reg = getRegForValue(I->getOperand(0));
533 UpdateValueMap(I, Reg);
537 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
538 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
539 MVT DstVT = TLI.getValueType(I->getType());
541 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
542 DstVT == MVT::Other || !DstVT.isSimple() ||
543 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
544 // Unhandled type. Halt "fast" selection and bail.
547 unsigned Op0 = getRegForValue(I->getOperand(0));
549 // Unhandled operand. Halt "fast" selection and bail.
552 // First, try to perform the bitcast by inserting a reg-reg copy.
553 unsigned ResultReg = 0;
554 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
555 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
556 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
557 ResultReg = createResultReg(DstClass);
559 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
560 Op0, DstClass, SrcClass);
565 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
567 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
568 ISD::BIT_CONVERT, Op0);
573 UpdateValueMap(I, ResultReg);
578 FastISel::SelectInstruction(Instruction *I) {
579 return SelectOperator(I, I->getOpcode());
582 /// FastEmitBranch - Emit an unconditional branch to the given block,
583 /// unless it is the immediate (fall-through) successor, and update
586 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
587 MachineFunction::iterator NextMBB =
588 next(MachineFunction::iterator(MBB));
590 if (MBB->isLayoutSuccessor(MSucc)) {
591 // The unconditional fall-through case, which needs no instructions.
593 // The unconditional branch case.
594 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
596 MBB->addSuccessor(MSucc);
600 FastISel::SelectOperator(User *I, unsigned Opcode) {
602 case Instruction::Add: {
603 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
604 return SelectBinaryOp(I, Opc);
606 case Instruction::Sub: {
607 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
608 return SelectBinaryOp(I, Opc);
610 case Instruction::Mul: {
611 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
612 return SelectBinaryOp(I, Opc);
614 case Instruction::SDiv:
615 return SelectBinaryOp(I, ISD::SDIV);
616 case Instruction::UDiv:
617 return SelectBinaryOp(I, ISD::UDIV);
618 case Instruction::FDiv:
619 return SelectBinaryOp(I, ISD::FDIV);
620 case Instruction::SRem:
621 return SelectBinaryOp(I, ISD::SREM);
622 case Instruction::URem:
623 return SelectBinaryOp(I, ISD::UREM);
624 case Instruction::FRem:
625 return SelectBinaryOp(I, ISD::FREM);
626 case Instruction::Shl:
627 return SelectBinaryOp(I, ISD::SHL);
628 case Instruction::LShr:
629 return SelectBinaryOp(I, ISD::SRL);
630 case Instruction::AShr:
631 return SelectBinaryOp(I, ISD::SRA);
632 case Instruction::And:
633 return SelectBinaryOp(I, ISD::AND);
634 case Instruction::Or:
635 return SelectBinaryOp(I, ISD::OR);
636 case Instruction::Xor:
637 return SelectBinaryOp(I, ISD::XOR);
639 case Instruction::GetElementPtr:
640 return SelectGetElementPtr(I);
642 case Instruction::Br: {
643 BranchInst *BI = cast<BranchInst>(I);
645 if (BI->isUnconditional()) {
646 BasicBlock *LLVMSucc = BI->getSuccessor(0);
647 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
648 FastEmitBranch(MSucc);
652 // Conditional branches are not handed yet.
653 // Halt "fast" selection and bail.
657 case Instruction::Unreachable:
661 case Instruction::PHI:
662 // PHI nodes are already emitted.
665 case Instruction::Alloca:
666 // FunctionLowering has the static-sized case covered.
667 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
670 // Dynamic-sized alloca is not handled yet.
673 case Instruction::Call:
674 return SelectCall(I);
676 case Instruction::BitCast:
677 return SelectBitCast(I);
679 case Instruction::FPToSI:
680 return SelectCast(I, ISD::FP_TO_SINT);
681 case Instruction::ZExt:
682 return SelectCast(I, ISD::ZERO_EXTEND);
683 case Instruction::SExt:
684 return SelectCast(I, ISD::SIGN_EXTEND);
685 case Instruction::Trunc:
686 return SelectCast(I, ISD::TRUNCATE);
687 case Instruction::SIToFP:
688 return SelectCast(I, ISD::SINT_TO_FP);
690 case Instruction::IntToPtr: // Deliberate fall-through.
691 case Instruction::PtrToInt: {
692 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
693 MVT DstVT = TLI.getValueType(I->getType());
694 if (DstVT.bitsGT(SrcVT))
695 return SelectCast(I, ISD::ZERO_EXTEND);
696 if (DstVT.bitsLT(SrcVT))
697 return SelectCast(I, ISD::TRUNCATE);
698 unsigned Reg = getRegForValue(I->getOperand(0));
699 if (Reg == 0) return false;
700 UpdateValueMap(I, Reg);
705 // Unhandled instruction. Halt "fast" selection and bail.
710 FastISel::FastISel(MachineFunction &mf,
711 MachineModuleInfo *mmi,
713 DenseMap<const Value *, unsigned> &vm,
714 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
715 DenseMap<const AllocaInst *, int> &am
717 , SmallSet<Instruction*, 8> &cil
730 MRI(MF.getRegInfo()),
731 MFI(*MF.getFrameInfo()),
732 MCP(*MF.getConstantPool()),
734 TD(*TM.getTargetData()),
735 TII(*TM.getInstrInfo()),
736 TLI(*TM.getTargetLowering()) {
739 FastISel::~FastISel() {}
741 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
746 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
747 ISD::NodeType, unsigned /*Op0*/) {
751 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
752 ISD::NodeType, unsigned /*Op0*/,
757 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
758 ISD::NodeType, uint64_t /*Imm*/) {
762 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
763 ISD::NodeType, ConstantFP * /*FPImm*/) {
767 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
768 ISD::NodeType, unsigned /*Op0*/,
773 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
774 ISD::NodeType, unsigned /*Op0*/,
775 ConstantFP * /*FPImm*/) {
779 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
781 unsigned /*Op0*/, unsigned /*Op1*/,
786 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
787 /// to emit an instruction with an immediate operand using FastEmit_ri.
788 /// If that fails, it materializes the immediate into a register and try
789 /// FastEmit_rr instead.
790 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
791 unsigned Op0, uint64_t Imm,
792 MVT::SimpleValueType ImmType) {
793 // First check if immediate type is legal. If not, we can't use the ri form.
794 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
797 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
798 if (MaterialReg == 0)
800 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
803 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
804 /// to emit an instruction with a floating-point immediate operand using
805 /// FastEmit_rf. If that fails, it materializes the immediate into a register
806 /// and try FastEmit_rr instead.
807 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
808 unsigned Op0, ConstantFP *FPImm,
809 MVT::SimpleValueType ImmType) {
810 // First check if immediate type is legal. If not, we can't use the rf form.
811 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
815 // Materialize the constant in a register.
816 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
817 if (MaterialReg == 0) {
818 // If the target doesn't have a way to directly enter a floating-point
819 // value into a register, use an alternate approach.
820 // TODO: The current approach only supports floating-point constants
821 // that can be constructed by conversion from integer values. This should
822 // be replaced by code that creates a load from a constant-pool entry,
823 // which will require some target-specific work.
824 const APFloat &Flt = FPImm->getValueAPF();
825 MVT IntVT = TLI.getPointerTy();
828 uint32_t IntBitWidth = IntVT.getSizeInBits();
830 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
831 APFloat::rmTowardZero, &isExact);
834 APInt IntVal(IntBitWidth, 2, x);
836 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
837 ISD::Constant, IntVal.getZExtValue());
840 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
841 ISD::SINT_TO_FP, IntegerReg);
842 if (MaterialReg == 0)
845 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
848 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
849 return MRI.createVirtualRegister(RC);
852 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
853 const TargetRegisterClass* RC) {
854 unsigned ResultReg = createResultReg(RC);
855 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
857 BuildMI(MBB, DL, II, ResultReg);
861 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
862 const TargetRegisterClass *RC,
864 unsigned ResultReg = createResultReg(RC);
865 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
867 if (II.getNumDefs() >= 1)
868 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
870 BuildMI(MBB, DL, II).addReg(Op0);
871 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
872 II.ImplicitDefs[0], RC, RC);
880 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
881 const TargetRegisterClass *RC,
882 unsigned Op0, unsigned Op1) {
883 unsigned ResultReg = createResultReg(RC);
884 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
886 if (II.getNumDefs() >= 1)
887 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
889 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
890 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
891 II.ImplicitDefs[0], RC, RC);
898 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
899 const TargetRegisterClass *RC,
900 unsigned Op0, uint64_t Imm) {
901 unsigned ResultReg = createResultReg(RC);
902 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
904 if (II.getNumDefs() >= 1)
905 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
907 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
908 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
909 II.ImplicitDefs[0], RC, RC);
916 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
917 const TargetRegisterClass *RC,
918 unsigned Op0, ConstantFP *FPImm) {
919 unsigned ResultReg = createResultReg(RC);
920 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
922 if (II.getNumDefs() >= 1)
923 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
925 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
926 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
927 II.ImplicitDefs[0], RC, RC);
934 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
935 const TargetRegisterClass *RC,
936 unsigned Op0, unsigned Op1, uint64_t Imm) {
937 unsigned ResultReg = createResultReg(RC);
938 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
940 if (II.getNumDefs() >= 1)
941 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
943 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
944 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
945 II.ImplicitDefs[0], RC, RC);
952 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
953 const TargetRegisterClass *RC,
955 unsigned ResultReg = createResultReg(RC);
956 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
958 if (II.getNumDefs() >= 1)
959 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
961 BuildMI(MBB, DL, II).addImm(Imm);
962 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
963 II.ImplicitDefs[0], RC, RC);
970 unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
971 unsigned Op0, uint32_t Idx) {
972 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
974 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
975 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
977 if (II.getNumDefs() >= 1)
978 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
980 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
981 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
982 II.ImplicitDefs[0], RC, RC);
989 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
990 /// with all but the least significant bit set to zero.
991 unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
992 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);