1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/DwarfWriter.h"
51 #include "llvm/Analysis/DebugInfo.h"
52 #include "llvm/Target/TargetData.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "SelectionDAGBuild.h"
59 unsigned FastISel::getRegForValue(Value *V) {
60 MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
62 // Ignore illegal types. We must do this before looking up the value
63 // in ValueMap because Arguments are given virtual registers regardless
64 // of whether FastISel can handle them.
65 if (!TLI.isTypeLegal(VT)) {
66 // Promote MVT::i1 to a legal type though, because it's common and easy.
68 VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
73 // Look up the value to see if we already have a register for it. We
74 // cache values defined by Instructions across blocks, and other values
75 // only locally. This is because Instructions already have the SSA
76 // def-dominatess-use requirement enforced.
77 if (ValueMap.count(V))
79 unsigned Reg = LocalValueMap[V];
83 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
84 if (CI->getValue().getActiveBits() <= 64)
85 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
86 } else if (isa<AllocaInst>(V)) {
87 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
88 } else if (isa<ConstantPointerNull>(V)) {
89 // Translate this as an integer zero so that it can be
90 // local-CSE'd with actual integer zeros.
91 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType()));
92 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
93 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
96 const APFloat &Flt = CF->getValueAPF();
97 MVT IntVT = TLI.getPointerTy();
100 uint32_t IntBitWidth = IntVT.getSizeInBits();
102 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
103 APFloat::rmTowardZero, &isExact);
105 APInt IntVal(IntBitWidth, 2, x);
107 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal));
109 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
112 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
113 if (!SelectOperator(CE, CE->getOpcode())) return 0;
114 Reg = LocalValueMap[CE];
115 } else if (isa<UndefValue>(V)) {
116 Reg = createResultReg(TLI.getRegClassFor(VT));
117 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
120 // If target-independent code couldn't handle the value, give target-specific
122 if (!Reg && isa<Constant>(V))
123 Reg = TargetMaterializeConstant(cast<Constant>(V));
125 // Don't cache constant materializations in the general ValueMap.
126 // To do so would require tracking what uses they dominate.
128 LocalValueMap[V] = Reg;
132 unsigned FastISel::lookUpRegForValue(Value *V) {
133 // Look up the value to see if we already have a register for it. We
134 // cache values defined by Instructions across blocks, and other values
135 // only locally. This is because Instructions already have the SSA
136 // def-dominatess-use requirement enforced.
137 if (ValueMap.count(V))
139 return LocalValueMap[V];
142 /// UpdateValueMap - Update the value map to include the new mapping for this
143 /// instruction, or insert an extra copy to get the result in a previous
144 /// determined register.
145 /// NOTE: This is only necessary because we might select a block that uses
146 /// a value before we select the block that defines the value. It might be
147 /// possible to fix this by selecting blocks in reverse postorder.
148 void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
149 if (!isa<Instruction>(I)) {
150 LocalValueMap[I] = Reg;
153 if (!ValueMap.count(I))
156 TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
157 Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
160 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
161 unsigned IdxN = getRegForValue(Idx);
163 // Unhandled operand. Halt "fast" selection and bail.
166 // If the index is smaller or larger than intptr_t, truncate or extend it.
167 MVT PtrVT = TLI.getPointerTy();
168 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
169 if (IdxVT.bitsLT(PtrVT))
170 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
171 ISD::SIGN_EXTEND, IdxN);
172 else if (IdxVT.bitsGT(PtrVT))
173 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
174 ISD::TRUNCATE, IdxN);
178 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
179 /// which has an opcode which directly corresponds to the given ISD opcode.
181 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
182 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
183 if (VT == MVT::Other || !VT.isSimple())
184 // Unhandled type. Halt "fast" selection and bail.
187 // We only handle legal types. For example, on x86-32 the instruction
188 // selector contains all of the 64-bit instructions from x86-64,
189 // under the assumption that i64 won't be used if the target doesn't
191 if (!TLI.isTypeLegal(VT)) {
192 // MVT::i1 is special. Allow AND, OR, or XOR because they
193 // don't require additional zeroing, which makes them easy.
195 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
196 ISDOpcode == ISD::XOR))
197 VT = TLI.getTypeToTransformTo(VT);
202 unsigned Op0 = getRegForValue(I->getOperand(0));
204 // Unhandled operand. Halt "fast" selection and bail.
207 // Check if the second operand is a constant and handle it appropriately.
208 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
209 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
210 ISDOpcode, Op0, CI->getZExtValue());
211 if (ResultReg != 0) {
212 // We successfully emitted code for the given LLVM Instruction.
213 UpdateValueMap(I, ResultReg);
218 // Check if the second operand is a constant float.
219 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
220 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
222 if (ResultReg != 0) {
223 // We successfully emitted code for the given LLVM Instruction.
224 UpdateValueMap(I, ResultReg);
229 unsigned Op1 = getRegForValue(I->getOperand(1));
231 // Unhandled operand. Halt "fast" selection and bail.
234 // Now we have both operands in registers. Emit the instruction.
235 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
236 ISDOpcode, Op0, Op1);
238 // Target-specific code wasn't able to find a machine opcode for
239 // the given ISD opcode and type. Halt "fast" selection and bail.
242 // We successfully emitted code for the given LLVM Instruction.
243 UpdateValueMap(I, ResultReg);
247 bool FastISel::SelectGetElementPtr(User *I) {
248 unsigned N = getRegForValue(I->getOperand(0));
250 // Unhandled operand. Halt "fast" selection and bail.
253 const Type *Ty = I->getOperand(0)->getType();
254 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
255 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
258 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
259 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
262 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
263 // FIXME: This can be optimized by combining the add with a
265 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
267 // Unhandled operand. Halt "fast" selection and bail.
270 Ty = StTy->getElementType(Field);
272 Ty = cast<SequentialType>(Ty)->getElementType();
274 // If this is a constant subscript, handle it quickly.
275 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
276 if (CI->getZExtValue() == 0) continue;
278 TD.getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
279 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
281 // Unhandled operand. Halt "fast" selection and bail.
286 // N = N + Idx * ElementSize;
287 uint64_t ElementSize = TD.getTypePaddedSize(Ty);
288 unsigned IdxN = getRegForGEPIndex(Idx);
290 // Unhandled operand. Halt "fast" selection and bail.
293 if (ElementSize != 1) {
294 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
296 // Unhandled operand. Halt "fast" selection and bail.
299 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
301 // Unhandled operand. Halt "fast" selection and bail.
306 // We successfully emitted code for the given LLVM Instruction.
307 UpdateValueMap(I, N);
311 bool FastISel::SelectCall(User *I) {
312 Function *F = cast<CallInst>(I)->getCalledFunction();
313 if (!F) return false;
315 unsigned IID = F->getIntrinsicID();
318 case Intrinsic::dbg_stoppoint: {
319 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
320 if (DW && DW->ValidDebugInfo(SPI->getContext())) {
321 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
322 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(),
324 unsigned Line = SPI->getLine();
325 unsigned Col = SPI->getColumn();
326 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
327 unsigned Idx = MF.getOrCreateDebugLocID(SrcFile, Line, Col);
328 setCurDebugLoc(DebugLoc::get(Idx));
329 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
330 BuildMI(MBB, DL, II).addImm(ID);
334 case Intrinsic::dbg_region_start: {
335 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
336 if (DW && DW->ValidDebugInfo(RSI->getContext())) {
338 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
339 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
340 BuildMI(MBB, DL, II).addImm(ID);
344 case Intrinsic::dbg_region_end: {
345 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
346 if (DW && DW->ValidDebugInfo(REI->getContext())) {
348 DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext()));
349 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
350 BuildMI(MBB, DL, II).addImm(ID);
354 case Intrinsic::dbg_func_start: {
355 if (!DW) return true;
356 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
357 Value *SP = FSI->getSubprogram();
359 if (DW->ValidDebugInfo(SP)) {
360 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
361 // (most?) gdb expects.
362 DISubprogram Subprogram(cast<GlobalVariable>(SP));
363 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
364 unsigned SrcFile = DW->getOrCreateSourceID(CompileUnit.getDirectory(),
365 CompileUnit.getFilename());
367 // Record the source line but does not create a label for the normal
368 // function start. It will be emitted at asm emission time. However,
369 // create a label if this is a beginning of inlined function.
370 unsigned Line = Subprogram.getLineNumber();
371 unsigned LabelID = DW->RecordSourceLine(Line, 0, SrcFile);
372 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(SrcFile, Line, 0)));
374 if (DW->getRecordSourceLineCount() != 1) {
375 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
376 BuildMI(MBB, DL, II).addImm(LabelID);
382 case Intrinsic::dbg_declare: {
383 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
384 Value *Variable = DI->getVariable();
385 if (DW && DW->ValidDebugInfo(Variable)) {
386 // Determine the address of the declared object.
387 Value *Address = DI->getAddress();
388 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
389 Address = BCI->getOperand(0);
390 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
391 // Don't handle byval struct arguments or VLAs, for example.
393 DenseMap<const AllocaInst*, int>::iterator SI =
394 StaticAllocaMap.find(AI);
395 if (SI == StaticAllocaMap.end()) break; // VLAs.
398 // Determine the debug globalvariable.
399 GlobalValue *GV = cast<GlobalVariable>(Variable);
401 // Build the DECLARE instruction.
402 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
403 BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV);
407 case Intrinsic::eh_exception: {
408 MVT VT = TLI.getValueType(I->getType());
409 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
411 case TargetLowering::Expand: {
412 if (!MBB->isLandingPad()) {
413 // FIXME: Mark exception register as live in. Hack for PR1508.
414 unsigned Reg = TLI.getExceptionAddressRegister();
415 if (Reg) MBB->addLiveIn(Reg);
417 unsigned Reg = TLI.getExceptionAddressRegister();
418 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
419 unsigned ResultReg = createResultReg(RC);
420 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
422 assert(InsertedCopy && "Can't copy address registers!");
423 InsertedCopy = InsertedCopy;
424 UpdateValueMap(I, ResultReg);
430 case Intrinsic::eh_selector_i32:
431 case Intrinsic::eh_selector_i64: {
432 MVT VT = TLI.getValueType(I->getType());
433 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
435 case TargetLowering::Expand: {
436 MVT VT = (IID == Intrinsic::eh_selector_i32 ?
437 MVT::i32 : MVT::i64);
440 if (MBB->isLandingPad())
441 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
444 CatchInfoLost.insert(cast<CallInst>(I));
446 // FIXME: Mark exception selector register as live in. Hack for PR1508.
447 unsigned Reg = TLI.getExceptionSelectorRegister();
448 if (Reg) MBB->addLiveIn(Reg);
451 unsigned Reg = TLI.getExceptionSelectorRegister();
452 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
453 unsigned ResultReg = createResultReg(RC);
454 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
456 assert(InsertedCopy && "Can't copy address registers!");
457 InsertedCopy = InsertedCopy;
458 UpdateValueMap(I, ResultReg);
461 getRegForValue(Constant::getNullValue(I->getType()));
462 UpdateValueMap(I, ResultReg);
473 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
474 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
475 MVT DstVT = TLI.getValueType(I->getType());
477 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
478 DstVT == MVT::Other || !DstVT.isSimple() ||
479 !TLI.isTypeLegal(DstVT))
480 // Unhandled type. Halt "fast" selection and bail.
483 // Check if the source operand is legal. Or as a special case,
484 // it may be i1 if we're doing zero-extension because that's
485 // trivially easy and somewhat common.
486 if (!TLI.isTypeLegal(SrcVT)) {
487 if (SrcVT == MVT::i1 && Opcode == ISD::ZERO_EXTEND)
488 SrcVT = TLI.getTypeToTransformTo(SrcVT);
490 // Unhandled type. Halt "fast" selection and bail.
494 unsigned InputReg = getRegForValue(I->getOperand(0));
496 // Unhandled operand. Halt "fast" selection and bail.
499 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
506 UpdateValueMap(I, ResultReg);
510 bool FastISel::SelectBitCast(User *I) {
511 // If the bitcast doesn't change the type, just use the operand value.
512 if (I->getType() == I->getOperand(0)->getType()) {
513 unsigned Reg = getRegForValue(I->getOperand(0));
516 UpdateValueMap(I, Reg);
520 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
521 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
522 MVT DstVT = TLI.getValueType(I->getType());
524 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
525 DstVT == MVT::Other || !DstVT.isSimple() ||
526 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
527 // Unhandled type. Halt "fast" selection and bail.
530 unsigned Op0 = getRegForValue(I->getOperand(0));
532 // Unhandled operand. Halt "fast" selection and bail.
535 // First, try to perform the bitcast by inserting a reg-reg copy.
536 unsigned ResultReg = 0;
537 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
538 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
539 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
540 ResultReg = createResultReg(DstClass);
542 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
543 Op0, DstClass, SrcClass);
548 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
550 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
551 ISD::BIT_CONVERT, Op0);
556 UpdateValueMap(I, ResultReg);
561 FastISel::SelectInstruction(Instruction *I) {
562 return SelectOperator(I, I->getOpcode());
565 /// FastEmitBranch - Emit an unconditional branch to the given block,
566 /// unless it is the immediate (fall-through) successor, and update
569 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
570 MachineFunction::iterator NextMBB =
571 next(MachineFunction::iterator(MBB));
573 if (MBB->isLayoutSuccessor(MSucc)) {
574 // The unconditional fall-through case, which needs no instructions.
576 // The unconditional branch case.
577 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
579 MBB->addSuccessor(MSucc);
583 FastISel::SelectOperator(User *I, unsigned Opcode) {
585 case Instruction::Add: {
586 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
587 return SelectBinaryOp(I, Opc);
589 case Instruction::Sub: {
590 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
591 return SelectBinaryOp(I, Opc);
593 case Instruction::Mul: {
594 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
595 return SelectBinaryOp(I, Opc);
597 case Instruction::SDiv:
598 return SelectBinaryOp(I, ISD::SDIV);
599 case Instruction::UDiv:
600 return SelectBinaryOp(I, ISD::UDIV);
601 case Instruction::FDiv:
602 return SelectBinaryOp(I, ISD::FDIV);
603 case Instruction::SRem:
604 return SelectBinaryOp(I, ISD::SREM);
605 case Instruction::URem:
606 return SelectBinaryOp(I, ISD::UREM);
607 case Instruction::FRem:
608 return SelectBinaryOp(I, ISD::FREM);
609 case Instruction::Shl:
610 return SelectBinaryOp(I, ISD::SHL);
611 case Instruction::LShr:
612 return SelectBinaryOp(I, ISD::SRL);
613 case Instruction::AShr:
614 return SelectBinaryOp(I, ISD::SRA);
615 case Instruction::And:
616 return SelectBinaryOp(I, ISD::AND);
617 case Instruction::Or:
618 return SelectBinaryOp(I, ISD::OR);
619 case Instruction::Xor:
620 return SelectBinaryOp(I, ISD::XOR);
622 case Instruction::GetElementPtr:
623 return SelectGetElementPtr(I);
625 case Instruction::Br: {
626 BranchInst *BI = cast<BranchInst>(I);
628 if (BI->isUnconditional()) {
629 BasicBlock *LLVMSucc = BI->getSuccessor(0);
630 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
631 FastEmitBranch(MSucc);
635 // Conditional branches are not handed yet.
636 // Halt "fast" selection and bail.
640 case Instruction::Unreachable:
644 case Instruction::PHI:
645 // PHI nodes are already emitted.
648 case Instruction::Alloca:
649 // FunctionLowering has the static-sized case covered.
650 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
653 // Dynamic-sized alloca is not handled yet.
656 case Instruction::Call:
657 return SelectCall(I);
659 case Instruction::BitCast:
660 return SelectBitCast(I);
662 case Instruction::FPToSI:
663 return SelectCast(I, ISD::FP_TO_SINT);
664 case Instruction::ZExt:
665 return SelectCast(I, ISD::ZERO_EXTEND);
666 case Instruction::SExt:
667 return SelectCast(I, ISD::SIGN_EXTEND);
668 case Instruction::Trunc:
669 return SelectCast(I, ISD::TRUNCATE);
670 case Instruction::SIToFP:
671 return SelectCast(I, ISD::SINT_TO_FP);
673 case Instruction::IntToPtr: // Deliberate fall-through.
674 case Instruction::PtrToInt: {
675 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
676 MVT DstVT = TLI.getValueType(I->getType());
677 if (DstVT.bitsGT(SrcVT))
678 return SelectCast(I, ISD::ZERO_EXTEND);
679 if (DstVT.bitsLT(SrcVT))
680 return SelectCast(I, ISD::TRUNCATE);
681 unsigned Reg = getRegForValue(I->getOperand(0));
682 if (Reg == 0) return false;
683 UpdateValueMap(I, Reg);
688 // Unhandled instruction. Halt "fast" selection and bail.
693 FastISel::FastISel(MachineFunction &mf,
694 MachineModuleInfo *mmi,
696 DenseMap<const Value *, unsigned> &vm,
697 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
698 DenseMap<const AllocaInst *, int> &am
700 , SmallSet<Instruction*, 8> &cil
713 MRI(MF.getRegInfo()),
714 MFI(*MF.getFrameInfo()),
715 MCP(*MF.getConstantPool()),
717 TD(*TM.getTargetData()),
718 TII(*TM.getInstrInfo()),
719 TLI(*TM.getTargetLowering()) {
722 FastISel::~FastISel() {}
724 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
729 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
730 ISD::NodeType, unsigned /*Op0*/) {
734 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
735 ISD::NodeType, unsigned /*Op0*/,
740 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
741 ISD::NodeType, uint64_t /*Imm*/) {
745 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
746 ISD::NodeType, ConstantFP * /*FPImm*/) {
750 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
751 ISD::NodeType, unsigned /*Op0*/,
756 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
757 ISD::NodeType, unsigned /*Op0*/,
758 ConstantFP * /*FPImm*/) {
762 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
764 unsigned /*Op0*/, unsigned /*Op1*/,
769 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
770 /// to emit an instruction with an immediate operand using FastEmit_ri.
771 /// If that fails, it materializes the immediate into a register and try
772 /// FastEmit_rr instead.
773 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
774 unsigned Op0, uint64_t Imm,
775 MVT::SimpleValueType ImmType) {
776 // First check if immediate type is legal. If not, we can't use the ri form.
777 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
780 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
781 if (MaterialReg == 0)
783 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
786 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
787 /// to emit an instruction with a floating-point immediate operand using
788 /// FastEmit_rf. If that fails, it materializes the immediate into a register
789 /// and try FastEmit_rr instead.
790 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
791 unsigned Op0, ConstantFP *FPImm,
792 MVT::SimpleValueType ImmType) {
793 // First check if immediate type is legal. If not, we can't use the rf form.
794 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
798 // Materialize the constant in a register.
799 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
800 if (MaterialReg == 0) {
801 // If the target doesn't have a way to directly enter a floating-point
802 // value into a register, use an alternate approach.
803 // TODO: The current approach only supports floating-point constants
804 // that can be constructed by conversion from integer values. This should
805 // be replaced by code that creates a load from a constant-pool entry,
806 // which will require some target-specific work.
807 const APFloat &Flt = FPImm->getValueAPF();
808 MVT IntVT = TLI.getPointerTy();
811 uint32_t IntBitWidth = IntVT.getSizeInBits();
813 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
814 APFloat::rmTowardZero, &isExact);
817 APInt IntVal(IntBitWidth, 2, x);
819 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
820 ISD::Constant, IntVal.getZExtValue());
823 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
824 ISD::SINT_TO_FP, IntegerReg);
825 if (MaterialReg == 0)
828 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
831 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
832 return MRI.createVirtualRegister(RC);
835 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
836 const TargetRegisterClass* RC) {
837 unsigned ResultReg = createResultReg(RC);
838 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
840 BuildMI(MBB, DL, II, ResultReg);
844 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
845 const TargetRegisterClass *RC,
847 unsigned ResultReg = createResultReg(RC);
848 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
850 if (II.getNumDefs() >= 1)
851 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
853 BuildMI(MBB, DL, II).addReg(Op0);
854 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
855 II.ImplicitDefs[0], RC, RC);
863 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
864 const TargetRegisterClass *RC,
865 unsigned Op0, unsigned Op1) {
866 unsigned ResultReg = createResultReg(RC);
867 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
869 if (II.getNumDefs() >= 1)
870 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
872 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
873 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
874 II.ImplicitDefs[0], RC, RC);
881 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
882 const TargetRegisterClass *RC,
883 unsigned Op0, uint64_t Imm) {
884 unsigned ResultReg = createResultReg(RC);
885 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
887 if (II.getNumDefs() >= 1)
888 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
890 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
891 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
892 II.ImplicitDefs[0], RC, RC);
899 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
900 const TargetRegisterClass *RC,
901 unsigned Op0, ConstantFP *FPImm) {
902 unsigned ResultReg = createResultReg(RC);
903 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
905 if (II.getNumDefs() >= 1)
906 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
908 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
909 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
910 II.ImplicitDefs[0], RC, RC);
917 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
918 const TargetRegisterClass *RC,
919 unsigned Op0, unsigned Op1, uint64_t Imm) {
920 unsigned ResultReg = createResultReg(RC);
921 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
923 if (II.getNumDefs() >= 1)
924 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
926 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
927 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
928 II.ImplicitDefs[0], RC, RC);
935 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
936 const TargetRegisterClass *RC,
938 unsigned ResultReg = createResultReg(RC);
939 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
941 if (II.getNumDefs() >= 1)
942 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
944 BuildMI(MBB, DL, II).addImm(Imm);
945 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
946 II.ImplicitDefs[0], RC, RC);
953 unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
954 unsigned Op0, uint32_t Idx) {
955 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
957 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
958 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
960 if (II.getNumDefs() >= 1)
961 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
963 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
964 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
965 II.ImplicitDefs[0], RC, RC);