1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/Analysis/DebugInfo.h"
51 #include "llvm/Target/TargetData.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "FunctionLoweringInfo.h"
58 unsigned FastISel::getRegForValue(Value *V) {
59 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
60 // Don't handle non-simple values in FastISel.
61 if (!RealVT.isSimple())
64 // Ignore illegal types. We must do this before looking up the value
65 // in ValueMap because Arguments are given virtual registers regardless
66 // of whether FastISel can handle them.
67 MVT VT = RealVT.getSimpleVT();
68 if (!TLI.isTypeLegal(VT)) {
69 // Promote MVT::i1 to a legal type though, because it's common and easy.
71 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
76 // Look up the value to see if we already have a register for it. We
77 // cache values defined by Instructions across blocks, and other values
78 // only locally. This is because Instructions already have the SSA
79 // def-dominates-use requirement enforced.
80 if (ValueMap.count(V))
82 unsigned Reg = LocalValueMap[V];
86 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
87 if (CI->getValue().getActiveBits() <= 64)
88 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
89 } else if (isa<AllocaInst>(V)) {
90 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
91 } else if (isa<ConstantPointerNull>(V)) {
92 // Translate this as an integer zero so that it can be
93 // local-CSE'd with actual integer zeros.
95 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
96 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
97 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
100 const APFloat &Flt = CF->getValueAPF();
101 EVT IntVT = TLI.getPointerTy();
104 uint32_t IntBitWidth = IntVT.getSizeInBits();
106 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
107 APFloat::rmTowardZero, &isExact);
109 APInt IntVal(IntBitWidth, 2, x);
111 unsigned IntegerReg =
112 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
114 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
117 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
118 if (!SelectOperator(CE, CE->getOpcode())) return 0;
119 Reg = LocalValueMap[CE];
120 } else if (isa<UndefValue>(V)) {
121 Reg = createResultReg(TLI.getRegClassFor(VT));
122 BuildMI(MBB, DL, TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
125 // If target-independent code couldn't handle the value, give target-specific
127 if (!Reg && isa<Constant>(V))
128 Reg = TargetMaterializeConstant(cast<Constant>(V));
130 // Don't cache constant materializations in the general ValueMap.
131 // To do so would require tracking what uses they dominate.
133 LocalValueMap[V] = Reg;
137 unsigned FastISel::lookUpRegForValue(Value *V) {
138 // Look up the value to see if we already have a register for it. We
139 // cache values defined by Instructions across blocks, and other values
140 // only locally. This is because Instructions already have the SSA
141 // def-dominatess-use requirement enforced.
142 if (ValueMap.count(V))
144 return LocalValueMap[V];
147 /// UpdateValueMap - Update the value map to include the new mapping for this
148 /// instruction, or insert an extra copy to get the result in a previous
149 /// determined register.
150 /// NOTE: This is only necessary because we might select a block that uses
151 /// a value before we select the block that defines the value. It might be
152 /// possible to fix this by selecting blocks in reverse postorder.
153 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
154 if (!isa<Instruction>(I)) {
155 LocalValueMap[I] = Reg;
159 unsigned &AssignedReg = ValueMap[I];
160 if (AssignedReg == 0)
162 else if (Reg != AssignedReg) {
163 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
164 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
165 Reg, RegClass, RegClass);
170 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
171 unsigned IdxN = getRegForValue(Idx);
173 // Unhandled operand. Halt "fast" selection and bail.
176 // If the index is smaller or larger than intptr_t, truncate or extend it.
177 MVT PtrVT = TLI.getPointerTy();
178 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
179 if (IdxVT.bitsLT(PtrVT))
180 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
181 else if (IdxVT.bitsGT(PtrVT))
182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
186 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
187 /// which has an opcode which directly corresponds to the given ISD opcode.
189 bool FastISel::SelectBinaryOp(User *I, unsigned ISDOpcode) {
190 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
191 if (VT == MVT::Other || !VT.isSimple())
192 // Unhandled type. Halt "fast" selection and bail.
195 // We only handle legal types. For example, on x86-32 the instruction
196 // selector contains all of the 64-bit instructions from x86-64,
197 // under the assumption that i64 won't be used if the target doesn't
199 if (!TLI.isTypeLegal(VT)) {
200 // MVT::i1 is special. Allow AND, OR, or XOR because they
201 // don't require additional zeroing, which makes them easy.
203 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
204 ISDOpcode == ISD::XOR))
205 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
210 unsigned Op0 = getRegForValue(I->getOperand(0));
212 // Unhandled operand. Halt "fast" selection and bail.
215 // Check if the second operand is a constant and handle it appropriately.
216 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
217 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
218 ISDOpcode, Op0, CI->getZExtValue());
219 if (ResultReg != 0) {
220 // We successfully emitted code for the given LLVM Instruction.
221 UpdateValueMap(I, ResultReg);
226 // Check if the second operand is a constant float.
227 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
228 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
230 if (ResultReg != 0) {
231 // We successfully emitted code for the given LLVM Instruction.
232 UpdateValueMap(I, ResultReg);
237 unsigned Op1 = getRegForValue(I->getOperand(1));
239 // Unhandled operand. Halt "fast" selection and bail.
242 // Now we have both operands in registers. Emit the instruction.
243 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
244 ISDOpcode, Op0, Op1);
246 // Target-specific code wasn't able to find a machine opcode for
247 // the given ISD opcode and type. Halt "fast" selection and bail.
250 // We successfully emitted code for the given LLVM Instruction.
251 UpdateValueMap(I, ResultReg);
255 bool FastISel::SelectGetElementPtr(User *I) {
256 unsigned N = getRegForValue(I->getOperand(0));
258 // Unhandled operand. Halt "fast" selection and bail.
261 const Type *Ty = I->getOperand(0)->getType();
262 MVT VT = TLI.getPointerTy();
263 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
266 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
267 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
270 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
271 // FIXME: This can be optimized by combining the add with a
273 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
275 // Unhandled operand. Halt "fast" selection and bail.
278 Ty = StTy->getElementType(Field);
280 Ty = cast<SequentialType>(Ty)->getElementType();
282 // If this is a constant subscript, handle it quickly.
283 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
284 if (CI->getZExtValue() == 0) continue;
286 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
287 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
289 // Unhandled operand. Halt "fast" selection and bail.
294 // N = N + Idx * ElementSize;
295 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
296 unsigned IdxN = getRegForGEPIndex(Idx);
298 // Unhandled operand. Halt "fast" selection and bail.
301 if (ElementSize != 1) {
302 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
304 // Unhandled operand. Halt "fast" selection and bail.
307 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
309 // Unhandled operand. Halt "fast" selection and bail.
314 // We successfully emitted code for the given LLVM Instruction.
315 UpdateValueMap(I, N);
319 bool FastISel::SelectCall(User *I) {
320 Function *F = cast<CallInst>(I)->getCalledFunction();
321 if (!F) return false;
323 unsigned IID = F->getIntrinsicID();
326 case Intrinsic::dbg_declare: {
327 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
328 if (!DIDescriptor::ValidDebugInfo(DI->getVariable(), CodeGenOpt::None) ||
329 !MF.getMMI().hasDebugInfo())
332 Value *Address = DI->getAddress();
335 if (isa<UndefValue>(Address))
337 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
338 // Don't handle byval struct arguments or VLAs, for example.
340 DenseMap<const AllocaInst*, int>::iterator SI =
341 StaticAllocaMap.find(AI);
342 if (SI == StaticAllocaMap.end()) break; // VLAs.
344 if (!DI->getDebugLoc().isUnknown())
345 MF.getMMI().setVariableDbgInfo(DI->getVariable(), FI, DI->getDebugLoc());
347 // Building the map above is target independent. Generating DBG_VALUE
348 // inline is target dependent; do this now.
349 (void)TargetSelectInstruction(cast<Instruction>(I));
352 case Intrinsic::dbg_value: {
353 // This form of DBG_VALUE is target-independent.
354 DbgValueInst *DI = cast<DbgValueInst>(I);
355 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
356 Value *V = DI->getValue();
358 // Currently the optimizer can produce this; insert an undef to
359 // help debugging. Probably the optimizer should not do this.
360 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
361 addMetadata(DI->getVariable());
362 } else if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
363 BuildMI(MBB, DL, II).addImm(CI->getZExtValue()).addImm(DI->getOffset()).
364 addMetadata(DI->getVariable());
365 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
366 BuildMI(MBB, DL, II).addFPImm(CF).addImm(DI->getOffset()).
367 addMetadata(DI->getVariable());
368 } else if (unsigned Reg = lookUpRegForValue(V)) {
369 BuildMI(MBB, DL, II).addReg(Reg, RegState::Debug).addImm(DI->getOffset()).
370 addMetadata(DI->getVariable());
372 // We can't yet handle anything else here because it would require
373 // generating code, thus altering codegen because of debug info.
374 // Insert an undef so we can see what we dropped.
375 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
376 addMetadata(DI->getVariable());
380 case Intrinsic::eh_exception: {
381 EVT VT = TLI.getValueType(I->getType());
382 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
384 case TargetLowering::Expand: {
385 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
386 unsigned Reg = TLI.getExceptionAddressRegister();
387 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
388 unsigned ResultReg = createResultReg(RC);
389 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
391 assert(InsertedCopy && "Can't copy address registers!");
392 InsertedCopy = InsertedCopy;
393 UpdateValueMap(I, ResultReg);
399 case Intrinsic::eh_selector: {
400 EVT VT = TLI.getValueType(I->getType());
401 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
403 case TargetLowering::Expand: {
404 if (MBB->isLandingPad())
405 AddCatchInfo(*cast<CallInst>(I), &MF.getMMI(), MBB);
408 CatchInfoLost.insert(cast<CallInst>(I));
410 // FIXME: Mark exception selector register as live in. Hack for PR1508.
411 unsigned Reg = TLI.getExceptionSelectorRegister();
412 if (Reg) MBB->addLiveIn(Reg);
415 unsigned Reg = TLI.getExceptionSelectorRegister();
416 EVT SrcVT = TLI.getPointerTy();
417 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
418 unsigned ResultReg = createResultReg(RC);
419 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
421 assert(InsertedCopy && "Can't copy address registers!");
422 InsertedCopy = InsertedCopy;
424 // Cast the register to the type of the selector.
425 if (SrcVT.bitsGT(MVT::i32))
426 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
428 else if (SrcVT.bitsLT(MVT::i32))
429 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
430 ISD::SIGN_EXTEND, ResultReg);
432 // Unhandled operand. Halt "fast" selection and bail.
435 UpdateValueMap(I, ResultReg);
446 bool FastISel::SelectCast(User *I, unsigned Opcode) {
447 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
448 EVT DstVT = TLI.getValueType(I->getType());
450 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
451 DstVT == MVT::Other || !DstVT.isSimple())
452 // Unhandled type. Halt "fast" selection and bail.
455 // Check if the destination type is legal. Or as a special case,
456 // it may be i1 if we're doing a truncate because that's
457 // easy and somewhat common.
458 if (!TLI.isTypeLegal(DstVT))
459 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
460 // Unhandled type. Halt "fast" selection and bail.
463 // Check if the source operand is legal. Or as a special case,
464 // it may be i1 if we're doing zero-extension because that's
465 // easy and somewhat common.
466 if (!TLI.isTypeLegal(SrcVT))
467 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
468 // Unhandled type. Halt "fast" selection and bail.
471 unsigned InputReg = getRegForValue(I->getOperand(0));
473 // Unhandled operand. Halt "fast" selection and bail.
476 // If the operand is i1, arrange for the high bits in the register to be zero.
477 if (SrcVT == MVT::i1) {
478 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
479 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
483 // If the result is i1, truncate to the target's type for i1 first.
484 if (DstVT == MVT::i1)
485 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
487 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
494 UpdateValueMap(I, ResultReg);
498 bool FastISel::SelectBitCast(User *I) {
499 // If the bitcast doesn't change the type, just use the operand value.
500 if (I->getType() == I->getOperand(0)->getType()) {
501 unsigned Reg = getRegForValue(I->getOperand(0));
504 UpdateValueMap(I, Reg);
508 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
509 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
510 EVT DstVT = TLI.getValueType(I->getType());
512 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
513 DstVT == MVT::Other || !DstVT.isSimple() ||
514 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
515 // Unhandled type. Halt "fast" selection and bail.
518 unsigned Op0 = getRegForValue(I->getOperand(0));
520 // Unhandled operand. Halt "fast" selection and bail.
523 // First, try to perform the bitcast by inserting a reg-reg copy.
524 unsigned ResultReg = 0;
525 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
526 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
527 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
528 ResultReg = createResultReg(DstClass);
530 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
531 Op0, DstClass, SrcClass);
536 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
538 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
539 ISD::BIT_CONVERT, Op0);
544 UpdateValueMap(I, ResultReg);
549 FastISel::SelectInstruction(Instruction *I) {
550 // First, try doing target-independent selection.
551 if (SelectOperator(I, I->getOpcode()))
554 // Next, try calling the target to attempt to handle the instruction.
555 if (TargetSelectInstruction(I))
561 /// FastEmitBranch - Emit an unconditional branch to the given block,
562 /// unless it is the immediate (fall-through) successor, and update
565 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
566 if (MBB->isLayoutSuccessor(MSucc)) {
567 // The unconditional fall-through case, which needs no instructions.
569 // The unconditional branch case.
570 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
572 MBB->addSuccessor(MSucc);
575 /// SelectFNeg - Emit an FNeg operation.
578 FastISel::SelectFNeg(User *I) {
579 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
580 if (OpReg == 0) return false;
582 // If the target has ISD::FNEG, use it.
583 EVT VT = TLI.getValueType(I->getType());
584 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
586 if (ResultReg != 0) {
587 UpdateValueMap(I, ResultReg);
591 // Bitcast the value to integer, twiddle the sign bit with xor,
592 // and then bitcast it back to floating-point.
593 if (VT.getSizeInBits() > 64) return false;
594 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
595 if (!TLI.isTypeLegal(IntVT))
598 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
599 ISD::BIT_CONVERT, OpReg);
603 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
604 UINT64_C(1) << (VT.getSizeInBits()-1),
605 IntVT.getSimpleVT());
606 if (IntResultReg == 0)
609 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
610 ISD::BIT_CONVERT, IntResultReg);
614 UpdateValueMap(I, ResultReg);
619 FastISel::SelectOperator(User *I, unsigned Opcode) {
621 case Instruction::Add:
622 return SelectBinaryOp(I, ISD::ADD);
623 case Instruction::FAdd:
624 return SelectBinaryOp(I, ISD::FADD);
625 case Instruction::Sub:
626 return SelectBinaryOp(I, ISD::SUB);
627 case Instruction::FSub:
628 // FNeg is currently represented in LLVM IR as a special case of FSub.
629 if (BinaryOperator::isFNeg(I))
630 return SelectFNeg(I);
631 return SelectBinaryOp(I, ISD::FSUB);
632 case Instruction::Mul:
633 return SelectBinaryOp(I, ISD::MUL);
634 case Instruction::FMul:
635 return SelectBinaryOp(I, ISD::FMUL);
636 case Instruction::SDiv:
637 return SelectBinaryOp(I, ISD::SDIV);
638 case Instruction::UDiv:
639 return SelectBinaryOp(I, ISD::UDIV);
640 case Instruction::FDiv:
641 return SelectBinaryOp(I, ISD::FDIV);
642 case Instruction::SRem:
643 return SelectBinaryOp(I, ISD::SREM);
644 case Instruction::URem:
645 return SelectBinaryOp(I, ISD::UREM);
646 case Instruction::FRem:
647 return SelectBinaryOp(I, ISD::FREM);
648 case Instruction::Shl:
649 return SelectBinaryOp(I, ISD::SHL);
650 case Instruction::LShr:
651 return SelectBinaryOp(I, ISD::SRL);
652 case Instruction::AShr:
653 return SelectBinaryOp(I, ISD::SRA);
654 case Instruction::And:
655 return SelectBinaryOp(I, ISD::AND);
656 case Instruction::Or:
657 return SelectBinaryOp(I, ISD::OR);
658 case Instruction::Xor:
659 return SelectBinaryOp(I, ISD::XOR);
661 case Instruction::GetElementPtr:
662 return SelectGetElementPtr(I);
664 case Instruction::Br: {
665 BranchInst *BI = cast<BranchInst>(I);
667 if (BI->isUnconditional()) {
668 BasicBlock *LLVMSucc = BI->getSuccessor(0);
669 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
670 FastEmitBranch(MSucc);
674 // Conditional branches are not handed yet.
675 // Halt "fast" selection and bail.
679 case Instruction::Unreachable:
683 case Instruction::PHI:
684 // PHI nodes are already emitted.
687 case Instruction::Alloca:
688 // FunctionLowering has the static-sized case covered.
689 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
692 // Dynamic-sized alloca is not handled yet.
695 case Instruction::Call:
696 return SelectCall(I);
698 case Instruction::BitCast:
699 return SelectBitCast(I);
701 case Instruction::FPToSI:
702 return SelectCast(I, ISD::FP_TO_SINT);
703 case Instruction::ZExt:
704 return SelectCast(I, ISD::ZERO_EXTEND);
705 case Instruction::SExt:
706 return SelectCast(I, ISD::SIGN_EXTEND);
707 case Instruction::Trunc:
708 return SelectCast(I, ISD::TRUNCATE);
709 case Instruction::SIToFP:
710 return SelectCast(I, ISD::SINT_TO_FP);
712 case Instruction::IntToPtr: // Deliberate fall-through.
713 case Instruction::PtrToInt: {
714 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
715 EVT DstVT = TLI.getValueType(I->getType());
716 if (DstVT.bitsGT(SrcVT))
717 return SelectCast(I, ISD::ZERO_EXTEND);
718 if (DstVT.bitsLT(SrcVT))
719 return SelectCast(I, ISD::TRUNCATE);
720 unsigned Reg = getRegForValue(I->getOperand(0));
721 if (Reg == 0) return false;
722 UpdateValueMap(I, Reg);
727 // Unhandled instruction. Halt "fast" selection and bail.
732 FastISel::FastISel(MachineFunction &mf,
733 DenseMap<const Value *, unsigned> &vm,
734 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
735 DenseMap<const AllocaInst *, int> &am
737 , SmallSet<Instruction*, 8> &cil
748 MRI(MF.getRegInfo()),
749 MFI(*MF.getFrameInfo()),
750 MCP(*MF.getConstantPool()),
752 TD(*TM.getTargetData()),
753 TII(*TM.getInstrInfo()),
754 TLI(*TM.getTargetLowering()) {
757 FastISel::~FastISel() {}
759 unsigned FastISel::FastEmit_(MVT, MVT,
764 unsigned FastISel::FastEmit_r(MVT, MVT,
765 unsigned, unsigned /*Op0*/) {
769 unsigned FastISel::FastEmit_rr(MVT, MVT,
770 unsigned, unsigned /*Op0*/,
775 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
779 unsigned FastISel::FastEmit_f(MVT, MVT,
780 unsigned, ConstantFP * /*FPImm*/) {
784 unsigned FastISel::FastEmit_ri(MVT, MVT,
785 unsigned, unsigned /*Op0*/,
790 unsigned FastISel::FastEmit_rf(MVT, MVT,
791 unsigned, unsigned /*Op0*/,
792 ConstantFP * /*FPImm*/) {
796 unsigned FastISel::FastEmit_rri(MVT, MVT,
798 unsigned /*Op0*/, unsigned /*Op1*/,
803 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
804 /// to emit an instruction with an immediate operand using FastEmit_ri.
805 /// If that fails, it materializes the immediate into a register and try
806 /// FastEmit_rr instead.
807 unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode,
808 unsigned Op0, uint64_t Imm,
810 // First check if immediate type is legal. If not, we can't use the ri form.
811 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
814 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
815 if (MaterialReg == 0)
817 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
820 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
821 /// to emit an instruction with a floating-point immediate operand using
822 /// FastEmit_rf. If that fails, it materializes the immediate into a register
823 /// and try FastEmit_rr instead.
824 unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode,
825 unsigned Op0, ConstantFP *FPImm,
827 // First check if immediate type is legal. If not, we can't use the rf form.
828 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
832 // Materialize the constant in a register.
833 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
834 if (MaterialReg == 0) {
835 // If the target doesn't have a way to directly enter a floating-point
836 // value into a register, use an alternate approach.
837 // TODO: The current approach only supports floating-point constants
838 // that can be constructed by conversion from integer values. This should
839 // be replaced by code that creates a load from a constant-pool entry,
840 // which will require some target-specific work.
841 const APFloat &Flt = FPImm->getValueAPF();
842 EVT IntVT = TLI.getPointerTy();
845 uint32_t IntBitWidth = IntVT.getSizeInBits();
847 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
848 APFloat::rmTowardZero, &isExact);
851 APInt IntVal(IntBitWidth, 2, x);
853 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
854 ISD::Constant, IntVal.getZExtValue());
857 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
858 ISD::SINT_TO_FP, IntegerReg);
859 if (MaterialReg == 0)
862 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
865 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
866 return MRI.createVirtualRegister(RC);
869 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
870 const TargetRegisterClass* RC) {
871 unsigned ResultReg = createResultReg(RC);
872 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
874 BuildMI(MBB, DL, II, ResultReg);
878 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
879 const TargetRegisterClass *RC,
881 unsigned ResultReg = createResultReg(RC);
882 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
884 if (II.getNumDefs() >= 1)
885 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
887 BuildMI(MBB, DL, II).addReg(Op0);
888 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
889 II.ImplicitDefs[0], RC, RC);
897 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
898 const TargetRegisterClass *RC,
899 unsigned Op0, unsigned Op1) {
900 unsigned ResultReg = createResultReg(RC);
901 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
903 if (II.getNumDefs() >= 1)
904 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
906 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
907 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
908 II.ImplicitDefs[0], RC, RC);
915 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
916 const TargetRegisterClass *RC,
917 unsigned Op0, uint64_t Imm) {
918 unsigned ResultReg = createResultReg(RC);
919 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
921 if (II.getNumDefs() >= 1)
922 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
924 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
925 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
926 II.ImplicitDefs[0], RC, RC);
933 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
934 const TargetRegisterClass *RC,
935 unsigned Op0, ConstantFP *FPImm) {
936 unsigned ResultReg = createResultReg(RC);
937 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
939 if (II.getNumDefs() >= 1)
940 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
942 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
943 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
944 II.ImplicitDefs[0], RC, RC);
951 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
952 const TargetRegisterClass *RC,
953 unsigned Op0, unsigned Op1, uint64_t Imm) {
954 unsigned ResultReg = createResultReg(RC);
955 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
957 if (II.getNumDefs() >= 1)
958 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
960 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
961 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
962 II.ImplicitDefs[0], RC, RC);
969 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
970 const TargetRegisterClass *RC,
972 unsigned ResultReg = createResultReg(RC);
973 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
975 if (II.getNumDefs() >= 1)
976 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
978 BuildMI(MBB, DL, II).addImm(Imm);
979 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
980 II.ImplicitDefs[0], RC, RC);
987 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
988 unsigned Op0, uint32_t Idx) {
989 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
991 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
992 const TargetInstrDesc &II = TII.get(TargetOpcode::EXTRACT_SUBREG);
994 if (II.getNumDefs() >= 1)
995 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
997 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
998 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
999 II.ImplicitDefs[0], RC, RC);
1006 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1007 /// with all but the least significant bit set to zero.
1008 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
1009 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);