1 //===-- FastISel.cpp - Implementation of the FastISel class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #define DEBUG_TYPE "isel"
43 #include "llvm/Function.h"
44 #include "llvm/GlobalVariable.h"
45 #include "llvm/Instructions.h"
46 #include "llvm/IntrinsicInst.h"
47 #include "llvm/Operator.h"
48 #include "llvm/CodeGen/Analysis.h"
49 #include "llvm/CodeGen/FastISel.h"
50 #include "llvm/CodeGen/FunctionLoweringInfo.h"
51 #include "llvm/CodeGen/MachineInstrBuilder.h"
52 #include "llvm/CodeGen/MachineModuleInfo.h"
53 #include "llvm/CodeGen/MachineRegisterInfo.h"
54 #include "llvm/Analysis/DebugInfo.h"
55 #include "llvm/Analysis/Loads.h"
56 #include "llvm/Target/TargetData.h"
57 #include "llvm/Target/TargetInstrInfo.h"
58 #include "llvm/Target/TargetLowering.h"
59 #include "llvm/Target/TargetMachine.h"
60 #include "llvm/Support/ErrorHandling.h"
61 #include "llvm/Support/Debug.h"
62 #include "llvm/ADT/Statistic.h"
65 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
66 "target-independent selector");
67 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
68 "target-specific selector");
69 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
71 /// startNewBlock - Set the current block to which generated machine
72 /// instructions will be appended, and clear the local CSE map.
74 void FastISel::startNewBlock() {
75 LocalValueMap.clear();
79 // Advance the emit start point past any EH_LABEL instructions.
80 MachineBasicBlock::iterator
81 I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end();
82 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) {
86 LastLocalValue = EmitStartPt;
89 void FastISel::flushLocalValueMap() {
90 LocalValueMap.clear();
91 LastLocalValue = EmitStartPt;
95 bool FastISel::hasTrivialKill(const Value *V) const {
96 // Don't consider constants or arguments to have trivial kills.
97 const Instruction *I = dyn_cast<Instruction>(V);
101 // No-op casts are trivially coalesced by fast-isel.
102 if (const CastInst *Cast = dyn_cast<CastInst>(I))
103 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) &&
104 !hasTrivialKill(Cast->getOperand(0)))
107 // GEPs with all zero indices are trivially coalesced by fast-isel.
108 if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(I))
109 if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0)))
112 // Only instructions with a single use in the same basic block are considered
113 // to have trivial kills.
114 return I->hasOneUse() &&
115 !(I->getOpcode() == Instruction::BitCast ||
116 I->getOpcode() == Instruction::PtrToInt ||
117 I->getOpcode() == Instruction::IntToPtr) &&
118 cast<Instruction>(*I->use_begin())->getParent() == I->getParent();
121 unsigned FastISel::getRegForValue(const Value *V) {
122 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
123 // Don't handle non-simple values in FastISel.
124 if (!RealVT.isSimple())
127 // Ignore illegal types. We must do this before looking up the value
128 // in ValueMap because Arguments are given virtual registers regardless
129 // of whether FastISel can handle them.
130 MVT VT = RealVT.getSimpleVT();
131 if (!TLI.isTypeLegal(VT)) {
132 // Handle integer promotions, though, because they're common and easy.
133 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
134 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
139 // Look up the value to see if we already have a register for it.
140 unsigned Reg = lookUpRegForValue(V);
144 // In bottom-up mode, just create the virtual register which will be used
145 // to hold the value. It will be materialized later.
146 if (isa<Instruction>(V) &&
147 (!isa<AllocaInst>(V) ||
148 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
149 return FuncInfo.InitializeRegForValue(V);
151 SavePoint SaveInsertPt = enterLocalValueArea();
153 // Materialize the value in a register. Emit any instructions in the
155 Reg = materializeRegForValue(V, VT);
157 leaveLocalValueArea(SaveInsertPt);
162 /// materializeRegForValue - Helper for getRegForValue. This function is
163 /// called when the value isn't already available in a register and must
164 /// be materialized with new instructions.
165 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
168 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
169 if (CI->getValue().getActiveBits() <= 64)
170 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
171 } else if (isa<AllocaInst>(V)) {
172 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
173 } else if (isa<ConstantPointerNull>(V)) {
174 // Translate this as an integer zero so that it can be
175 // local-CSE'd with actual integer zeros.
177 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
178 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
179 if (CF->isNullValue()) {
180 Reg = TargetMaterializeFloatZero(CF);
182 // Try to emit the constant directly.
183 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
187 // Try to emit the constant by using an integer constant with a cast.
188 const APFloat &Flt = CF->getValueAPF();
189 EVT IntVT = TLI.getPointerTy();
192 uint32_t IntBitWidth = IntVT.getSizeInBits();
194 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
195 APFloat::rmTowardZero, &isExact);
197 APInt IntVal(IntBitWidth, x);
199 unsigned IntegerReg =
200 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
202 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
203 IntegerReg, /*Kill=*/false);
206 } else if (const Operator *Op = dyn_cast<Operator>(V)) {
207 if (!SelectOperator(Op, Op->getOpcode()))
208 if (!isa<Instruction>(Op) ||
209 !TargetSelectInstruction(cast<Instruction>(Op)))
211 Reg = lookUpRegForValue(Op);
212 } else if (isa<UndefValue>(V)) {
213 Reg = createResultReg(TLI.getRegClassFor(VT));
214 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
215 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
218 // If target-independent code couldn't handle the value, give target-specific
220 if (!Reg && isa<Constant>(V))
221 Reg = TargetMaterializeConstant(cast<Constant>(V));
223 // Don't cache constant materializations in the general ValueMap.
224 // To do so would require tracking what uses they dominate.
226 LocalValueMap[V] = Reg;
227 LastLocalValue = MRI.getVRegDef(Reg);
232 unsigned FastISel::lookUpRegForValue(const Value *V) {
233 // Look up the value to see if we already have a register for it. We
234 // cache values defined by Instructions across blocks, and other values
235 // only locally. This is because Instructions already have the SSA
236 // def-dominates-use requirement enforced.
237 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
238 if (I != FuncInfo.ValueMap.end())
240 return LocalValueMap[V];
243 /// UpdateValueMap - Update the value map to include the new mapping for this
244 /// instruction, or insert an extra copy to get the result in a previous
245 /// determined register.
246 /// NOTE: This is only necessary because we might select a block that uses
247 /// a value before we select the block that defines the value. It might be
248 /// possible to fix this by selecting blocks in reverse postorder.
249 void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) {
250 if (!isa<Instruction>(I)) {
251 LocalValueMap[I] = Reg;
255 unsigned &AssignedReg = FuncInfo.ValueMap[I];
256 if (AssignedReg == 0)
257 // Use the new register.
259 else if (Reg != AssignedReg) {
260 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
261 for (unsigned i = 0; i < NumRegs; i++)
262 FuncInfo.RegFixups[AssignedReg+i] = Reg+i;
268 std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) {
269 unsigned IdxN = getRegForValue(Idx);
271 // Unhandled operand. Halt "fast" selection and bail.
272 return std::pair<unsigned, bool>(0, false);
274 bool IdxNIsKill = hasTrivialKill(Idx);
276 // If the index is smaller or larger than intptr_t, truncate or extend it.
277 MVT PtrVT = TLI.getPointerTy();
278 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
279 if (IdxVT.bitsLT(PtrVT)) {
280 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND,
284 else if (IdxVT.bitsGT(PtrVT)) {
285 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE,
289 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
292 void FastISel::recomputeInsertPt() {
293 if (getLastLocalValue()) {
294 FuncInfo.InsertPt = getLastLocalValue();
295 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
298 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
300 // Now skip past any EH_LABELs, which must remain at the beginning.
301 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
302 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
306 void FastISel::removeDeadCode(MachineBasicBlock::iterator I,
307 MachineBasicBlock::iterator E) {
308 assert (I && E && std::distance(I, E) > 0 && "Invalid iterator!");
310 MachineInstr *Dead = &*I;
312 Dead->eraseFromParent();
318 FastISel::SavePoint FastISel::enterLocalValueArea() {
319 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
323 SavePoint SP = { OldInsertPt, OldDL };
327 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
328 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
329 LastLocalValue = llvm::prior(FuncInfo.InsertPt);
331 // Restore the previous insert position.
332 FuncInfo.InsertPt = OldInsertPt.InsertPt;
336 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
337 /// which has an opcode which directly corresponds to the given ISD opcode.
339 bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) {
340 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
341 if (VT == MVT::Other || !VT.isSimple())
342 // Unhandled type. Halt "fast" selection and bail.
345 // We only handle legal types. For example, on x86-32 the instruction
346 // selector contains all of the 64-bit instructions from x86-64,
347 // under the assumption that i64 won't be used if the target doesn't
349 if (!TLI.isTypeLegal(VT)) {
350 // MVT::i1 is special. Allow AND, OR, or XOR because they
351 // don't require additional zeroing, which makes them easy.
353 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
354 ISDOpcode == ISD::XOR))
355 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
360 // Check if the first operand is a constant, and handle it as "ri". At -O0,
361 // we don't have anything that canonicalizes operand order.
362 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
363 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
364 unsigned Op1 = getRegForValue(I->getOperand(1));
365 if (Op1 == 0) return false;
367 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
369 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
370 Op1IsKill, CI->getZExtValue(),
372 if (ResultReg == 0) return false;
374 // We successfully emitted code for the given LLVM Instruction.
375 UpdateValueMap(I, ResultReg);
380 unsigned Op0 = getRegForValue(I->getOperand(0));
381 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail.
384 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
386 // Check if the second operand is a constant and handle it appropriately.
387 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
388 uint64_t Imm = CI->getZExtValue();
390 // Transform "sdiv exact X, 8" -> "sra X, 3".
391 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
392 cast<BinaryOperator>(I)->isExact() &&
393 isPowerOf2_64(Imm)) {
395 ISDOpcode = ISD::SRA;
398 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
399 Op0IsKill, Imm, VT.getSimpleVT());
400 if (ResultReg == 0) return false;
402 // We successfully emitted code for the given LLVM Instruction.
403 UpdateValueMap(I, ResultReg);
407 // Check if the second operand is a constant float.
408 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
409 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
410 ISDOpcode, Op0, Op0IsKill, CF);
411 if (ResultReg != 0) {
412 // We successfully emitted code for the given LLVM Instruction.
413 UpdateValueMap(I, ResultReg);
418 unsigned Op1 = getRegForValue(I->getOperand(1));
420 // Unhandled operand. Halt "fast" selection and bail.
423 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
425 // Now we have both operands in registers. Emit the instruction.
426 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
431 // Target-specific code wasn't able to find a machine opcode for
432 // the given ISD opcode and type. Halt "fast" selection and bail.
435 // We successfully emitted code for the given LLVM Instruction.
436 UpdateValueMap(I, ResultReg);
440 bool FastISel::SelectGetElementPtr(const User *I) {
441 unsigned N = getRegForValue(I->getOperand(0));
443 // Unhandled operand. Halt "fast" selection and bail.
446 bool NIsKill = hasTrivialKill(I->getOperand(0));
448 // Keep a running tab of the total offset to coalesce multiple N = N + Offset
449 // into a single N = N + TotalOffset.
450 uint64_t TotalOffs = 0;
451 // FIXME: What's a good SWAG number for MaxOffs?
452 uint64_t MaxOffs = 2048;
453 Type *Ty = I->getOperand(0)->getType();
454 MVT VT = TLI.getPointerTy();
455 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1,
456 E = I->op_end(); OI != E; ++OI) {
457 const Value *Idx = *OI;
458 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
459 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
462 TotalOffs += TD.getStructLayout(StTy)->getElementOffset(Field);
463 if (TotalOffs >= MaxOffs) {
464 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
466 // Unhandled operand. Halt "fast" selection and bail.
472 Ty = StTy->getElementType(Field);
474 Ty = cast<SequentialType>(Ty)->getElementType();
476 // If this is a constant subscript, handle it quickly.
477 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
478 if (CI->isZero()) continue;
481 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
482 if (TotalOffs >= MaxOffs) {
483 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
485 // Unhandled operand. Halt "fast" selection and bail.
493 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
495 // Unhandled operand. Halt "fast" selection and bail.
501 // N = N + Idx * ElementSize;
502 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
503 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
504 unsigned IdxN = Pair.first;
505 bool IdxNIsKill = Pair.second;
507 // Unhandled operand. Halt "fast" selection and bail.
510 if (ElementSize != 1) {
511 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
513 // Unhandled operand. Halt "fast" selection and bail.
517 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
519 // Unhandled operand. Halt "fast" selection and bail.
524 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
526 // Unhandled operand. Halt "fast" selection and bail.
530 // We successfully emitted code for the given LLVM Instruction.
531 UpdateValueMap(I, N);
535 bool FastISel::SelectCall(const User *I) {
536 const CallInst *Call = cast<CallInst>(I);
538 // Handle simple inline asms.
539 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledValue())) {
540 // Don't attempt to handle constraints.
541 if (!IA->getConstraintString().empty())
544 unsigned ExtraInfo = 0;
545 if (IA->hasSideEffects())
546 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
547 if (IA->isAlignStack())
548 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
550 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
551 TII.get(TargetOpcode::INLINEASM))
552 .addExternalSymbol(IA->getAsmString().c_str())
557 MachineModuleInfo &MMI = FuncInfo.MF->getMMI();
558 ComputeUsesVAFloatArgument(*Call, &MMI);
560 const Function *F = Call->getCalledFunction();
561 if (!F) return false;
563 // Handle selected intrinsic function calls.
564 switch (F->getIntrinsicID()) {
566 // At -O0 we don't care about the lifetime intrinsics.
567 case Intrinsic::lifetime_start:
568 case Intrinsic::lifetime_end:
570 case Intrinsic::dbg_declare: {
571 const DbgDeclareInst *DI = cast<DbgDeclareInst>(Call);
572 if (!DIVariable(DI->getVariable()).Verify() ||
573 !FuncInfo.MF->getMMI().hasDebugInfo()) {
574 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
578 const Value *Address = DI->getAddress();
579 if (!Address || isa<UndefValue>(Address)) {
580 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
586 if (const Argument *Arg = dyn_cast<Argument>(Address)) {
587 // Some arguments' frame index is recorded during argument lowering.
588 Offset = FuncInfo.getArgumentFrameIndex(Arg);
590 Reg = TRI.getFrameRegister(*FuncInfo.MF);
593 Reg = getRegForValue(Address);
596 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
597 TII.get(TargetOpcode::DBG_VALUE))
598 .addReg(Reg, RegState::Debug).addImm(Offset)
599 .addMetadata(DI->getVariable());
601 // We can't yet handle anything else here because it would require
602 // generating code, thus altering codegen because of debug info.
603 DEBUG(dbgs() << "Dropping debug info for " << DI);
606 case Intrinsic::dbg_value: {
607 // This form of DBG_VALUE is target-independent.
608 const DbgValueInst *DI = cast<DbgValueInst>(Call);
609 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
610 const Value *V = DI->getValue();
612 // Currently the optimizer can produce this; insert an undef to
613 // help debugging. Probably the optimizer should not do this.
614 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
615 .addReg(0U).addImm(DI->getOffset())
616 .addMetadata(DI->getVariable());
617 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
618 if (CI->getBitWidth() > 64)
619 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
620 .addCImm(CI).addImm(DI->getOffset())
621 .addMetadata(DI->getVariable());
623 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
624 .addImm(CI->getZExtValue()).addImm(DI->getOffset())
625 .addMetadata(DI->getVariable());
626 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
627 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
628 .addFPImm(CF).addImm(DI->getOffset())
629 .addMetadata(DI->getVariable());
630 } else if (unsigned Reg = lookUpRegForValue(V)) {
631 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
632 .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
633 .addMetadata(DI->getVariable());
635 // We can't yet handle anything else here because it would require
636 // generating code, thus altering codegen because of debug info.
637 DEBUG(dbgs() << "Dropping debug info for " << DI);
641 case Intrinsic::objectsize: {
642 ConstantInt *CI = cast<ConstantInt>(Call->getArgOperand(1));
643 unsigned long long Res = CI->isZero() ? -1ULL : 0;
644 Constant *ResCI = ConstantInt::get(Call->getType(), Res);
645 unsigned ResultReg = getRegForValue(ResCI);
648 UpdateValueMap(Call, ResultReg);
653 // Usually, it does not make sense to initialize a value,
654 // make an unrelated function call and use the value, because
655 // it tends to be spilled on the stack. So, we move the pointer
656 // to the last local value to the beginning of the block, so that
657 // all the values which have already been materialized,
658 // appear after the call. It also makes sense to skip intrinsics
659 // since they tend to be inlined.
660 if (!isa<IntrinsicInst>(F))
661 flushLocalValueMap();
663 // An arbitrary call. Bail.
667 bool FastISel::SelectCast(const User *I, unsigned Opcode) {
668 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
669 EVT DstVT = TLI.getValueType(I->getType());
671 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
672 DstVT == MVT::Other || !DstVT.isSimple())
673 // Unhandled type. Halt "fast" selection and bail.
676 // Check if the destination type is legal.
677 if (!TLI.isTypeLegal(DstVT))
680 // Check if the source operand is legal.
681 if (!TLI.isTypeLegal(SrcVT))
684 unsigned InputReg = getRegForValue(I->getOperand(0));
686 // Unhandled operand. Halt "fast" selection and bail.
689 bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
691 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
694 InputReg, InputRegIsKill);
698 UpdateValueMap(I, ResultReg);
702 bool FastISel::SelectBitCast(const User *I) {
703 // If the bitcast doesn't change the type, just use the operand value.
704 if (I->getType() == I->getOperand(0)->getType()) {
705 unsigned Reg = getRegForValue(I->getOperand(0));
708 UpdateValueMap(I, Reg);
712 // Bitcasts of other values become reg-reg copies or BITCAST operators.
713 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
714 EVT DstVT = TLI.getValueType(I->getType());
716 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
717 DstVT == MVT::Other || !DstVT.isSimple() ||
718 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
719 // Unhandled type. Halt "fast" selection and bail.
722 unsigned Op0 = getRegForValue(I->getOperand(0));
724 // Unhandled operand. Halt "fast" selection and bail.
727 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
729 // First, try to perform the bitcast by inserting a reg-reg copy.
730 unsigned ResultReg = 0;
731 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
732 const TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
733 const TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
734 // Don't attempt a cross-class copy. It will likely fail.
735 if (SrcClass == DstClass) {
736 ResultReg = createResultReg(DstClass);
737 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
738 ResultReg).addReg(Op0);
742 // If the reg-reg copy failed, select a BITCAST opcode.
744 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
745 ISD::BITCAST, Op0, Op0IsKill);
750 UpdateValueMap(I, ResultReg);
755 FastISel::SelectInstruction(const Instruction *I) {
756 // Just before the terminator instruction, insert instructions to
757 // feed PHI nodes in successor blocks.
758 if (isa<TerminatorInst>(I))
759 if (!HandlePHINodesInSuccessorBlocks(I->getParent()))
762 DL = I->getDebugLoc();
764 MachineBasicBlock::iterator SavedInsertPt = FuncInfo.InsertPt;
766 // First, try doing target-independent selection.
767 if (SelectOperator(I, I->getOpcode())) {
768 ++NumFastIselSuccessIndependent;
772 // Remove dead code. However, ignore call instructions since we've flushed
773 // the local value map and recomputed the insert point.
774 if (!isa<CallInst>(I)) {
776 if (SavedInsertPt != FuncInfo.InsertPt)
777 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
780 // Next, try calling the target to attempt to handle the instruction.
781 SavedInsertPt = FuncInfo.InsertPt;
782 if (TargetSelectInstruction(I)) {
783 ++NumFastIselSuccessTarget;
787 // Check for dead code and remove as necessary.
789 if (SavedInsertPt != FuncInfo.InsertPt)
790 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
796 /// FastEmitBranch - Emit an unconditional branch to the given block,
797 /// unless it is the immediate (fall-through) successor, and update
800 FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) {
801 if (FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
802 // The unconditional fall-through case, which needs no instructions.
804 // The unconditional branch case.
805 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL,
806 SmallVector<MachineOperand, 0>(), DL);
808 FuncInfo.MBB->addSuccessor(MSucc);
811 /// SelectFNeg - Emit an FNeg operation.
814 FastISel::SelectFNeg(const User *I) {
815 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
816 if (OpReg == 0) return false;
818 bool OpRegIsKill = hasTrivialKill(I);
820 // If the target has ISD::FNEG, use it.
821 EVT VT = TLI.getValueType(I->getType());
822 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
823 ISD::FNEG, OpReg, OpRegIsKill);
824 if (ResultReg != 0) {
825 UpdateValueMap(I, ResultReg);
829 // Bitcast the value to integer, twiddle the sign bit with xor,
830 // and then bitcast it back to floating-point.
831 if (VT.getSizeInBits() > 64) return false;
832 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
833 if (!TLI.isTypeLegal(IntVT))
836 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
837 ISD::BITCAST, OpReg, OpRegIsKill);
841 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR,
842 IntReg, /*Kill=*/true,
843 UINT64_C(1) << (VT.getSizeInBits()-1),
844 IntVT.getSimpleVT());
845 if (IntResultReg == 0)
848 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
849 ISD::BITCAST, IntResultReg, /*Kill=*/true);
853 UpdateValueMap(I, ResultReg);
858 FastISel::SelectExtractValue(const User *U) {
859 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
863 // Make sure we only try to handle extracts with a legal result. But also
864 // allow i1 because it's easy.
865 EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true);
866 if (!RealVT.isSimple())
868 MVT VT = RealVT.getSimpleVT();
869 if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
872 const Value *Op0 = EVI->getOperand(0);
873 Type *AggTy = Op0->getType();
875 // Get the base result register.
877 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
878 if (I != FuncInfo.ValueMap.end())
879 ResultReg = I->second;
880 else if (isa<Instruction>(Op0))
881 ResultReg = FuncInfo.InitializeRegForValue(Op0);
883 return false; // fast-isel can't handle aggregate constants at the moment
885 // Get the actual result register, which is an offset from the base register.
886 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
888 SmallVector<EVT, 4> AggValueVTs;
889 ComputeValueVTs(TLI, AggTy, AggValueVTs);
891 for (unsigned i = 0; i < VTIndex; i++)
892 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
894 UpdateValueMap(EVI, ResultReg);
899 FastISel::SelectOperator(const User *I, unsigned Opcode) {
901 case Instruction::Add:
902 return SelectBinaryOp(I, ISD::ADD);
903 case Instruction::FAdd:
904 return SelectBinaryOp(I, ISD::FADD);
905 case Instruction::Sub:
906 return SelectBinaryOp(I, ISD::SUB);
907 case Instruction::FSub:
908 // FNeg is currently represented in LLVM IR as a special case of FSub.
909 if (BinaryOperator::isFNeg(I))
910 return SelectFNeg(I);
911 return SelectBinaryOp(I, ISD::FSUB);
912 case Instruction::Mul:
913 return SelectBinaryOp(I, ISD::MUL);
914 case Instruction::FMul:
915 return SelectBinaryOp(I, ISD::FMUL);
916 case Instruction::SDiv:
917 return SelectBinaryOp(I, ISD::SDIV);
918 case Instruction::UDiv:
919 return SelectBinaryOp(I, ISD::UDIV);
920 case Instruction::FDiv:
921 return SelectBinaryOp(I, ISD::FDIV);
922 case Instruction::SRem:
923 return SelectBinaryOp(I, ISD::SREM);
924 case Instruction::URem:
925 return SelectBinaryOp(I, ISD::UREM);
926 case Instruction::FRem:
927 return SelectBinaryOp(I, ISD::FREM);
928 case Instruction::Shl:
929 return SelectBinaryOp(I, ISD::SHL);
930 case Instruction::LShr:
931 return SelectBinaryOp(I, ISD::SRL);
932 case Instruction::AShr:
933 return SelectBinaryOp(I, ISD::SRA);
934 case Instruction::And:
935 return SelectBinaryOp(I, ISD::AND);
936 case Instruction::Or:
937 return SelectBinaryOp(I, ISD::OR);
938 case Instruction::Xor:
939 return SelectBinaryOp(I, ISD::XOR);
941 case Instruction::GetElementPtr:
942 return SelectGetElementPtr(I);
944 case Instruction::Br: {
945 const BranchInst *BI = cast<BranchInst>(I);
947 if (BI->isUnconditional()) {
948 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
949 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
950 FastEmitBranch(MSucc, BI->getDebugLoc());
954 // Conditional branches are not handed yet.
955 // Halt "fast" selection and bail.
959 case Instruction::Unreachable:
963 case Instruction::Alloca:
964 // FunctionLowering has the static-sized case covered.
965 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
968 // Dynamic-sized alloca is not handled yet.
971 case Instruction::Call:
972 return SelectCall(I);
974 case Instruction::BitCast:
975 return SelectBitCast(I);
977 case Instruction::FPToSI:
978 return SelectCast(I, ISD::FP_TO_SINT);
979 case Instruction::ZExt:
980 return SelectCast(I, ISD::ZERO_EXTEND);
981 case Instruction::SExt:
982 return SelectCast(I, ISD::SIGN_EXTEND);
983 case Instruction::Trunc:
984 return SelectCast(I, ISD::TRUNCATE);
985 case Instruction::SIToFP:
986 return SelectCast(I, ISD::SINT_TO_FP);
988 case Instruction::IntToPtr: // Deliberate fall-through.
989 case Instruction::PtrToInt: {
990 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
991 EVT DstVT = TLI.getValueType(I->getType());
992 if (DstVT.bitsGT(SrcVT))
993 return SelectCast(I, ISD::ZERO_EXTEND);
994 if (DstVT.bitsLT(SrcVT))
995 return SelectCast(I, ISD::TRUNCATE);
996 unsigned Reg = getRegForValue(I->getOperand(0));
997 if (Reg == 0) return false;
998 UpdateValueMap(I, Reg);
1002 case Instruction::ExtractValue:
1003 return SelectExtractValue(I);
1005 case Instruction::PHI:
1006 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1009 // Unhandled instruction. Halt "fast" selection and bail.
1014 FastISel::FastISel(FunctionLoweringInfo &funcInfo)
1015 : FuncInfo(funcInfo),
1016 MRI(FuncInfo.MF->getRegInfo()),
1017 MFI(*FuncInfo.MF->getFrameInfo()),
1018 MCP(*FuncInfo.MF->getConstantPool()),
1019 TM(FuncInfo.MF->getTarget()),
1020 TD(*TM.getTargetData()),
1021 TII(*TM.getInstrInfo()),
1022 TLI(*TM.getTargetLowering()),
1023 TRI(*TM.getRegisterInfo()) {
1026 FastISel::~FastISel() {}
1028 unsigned FastISel::FastEmit_(MVT, MVT,
1033 unsigned FastISel::FastEmit_r(MVT, MVT,
1035 unsigned /*Op0*/, bool /*Op0IsKill*/) {
1039 unsigned FastISel::FastEmit_rr(MVT, MVT,
1041 unsigned /*Op0*/, bool /*Op0IsKill*/,
1042 unsigned /*Op1*/, bool /*Op1IsKill*/) {
1046 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1050 unsigned FastISel::FastEmit_f(MVT, MVT,
1051 unsigned, const ConstantFP * /*FPImm*/) {
1055 unsigned FastISel::FastEmit_ri(MVT, MVT,
1057 unsigned /*Op0*/, bool /*Op0IsKill*/,
1062 unsigned FastISel::FastEmit_rf(MVT, MVT,
1064 unsigned /*Op0*/, bool /*Op0IsKill*/,
1065 const ConstantFP * /*FPImm*/) {
1069 unsigned FastISel::FastEmit_rri(MVT, MVT,
1071 unsigned /*Op0*/, bool /*Op0IsKill*/,
1072 unsigned /*Op1*/, bool /*Op1IsKill*/,
1077 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
1078 /// to emit an instruction with an immediate operand using FastEmit_ri.
1079 /// If that fails, it materializes the immediate into a register and try
1080 /// FastEmit_rr instead.
1081 unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode,
1082 unsigned Op0, bool Op0IsKill,
1083 uint64_t Imm, MVT ImmType) {
1084 // If this is a multiply by a power of two, emit this as a shift left.
1085 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1088 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1089 // div x, 8 -> srl x, 3
1094 // Horrible hack (to be removed), check to make sure shift amounts are
1096 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1097 Imm >= VT.getSizeInBits())
1100 // First check if immediate type is legal. If not, we can't use the ri form.
1101 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1104 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1105 if (MaterialReg == 0) {
1106 // This is a bit ugly/slow, but failing here means falling out of
1107 // fast-isel, which would be very slow.
1108 IntegerType *ITy = IntegerType::get(FuncInfo.Fn->getContext(),
1109 VT.getSizeInBits());
1110 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1112 return FastEmit_rr(VT, VT, Opcode,
1114 MaterialReg, /*Kill=*/true);
1117 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
1118 return MRI.createVirtualRegister(RC);
1121 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
1122 const TargetRegisterClass* RC) {
1123 unsigned ResultReg = createResultReg(RC);
1124 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1126 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg);
1130 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
1131 const TargetRegisterClass *RC,
1132 unsigned Op0, bool Op0IsKill) {
1133 unsigned ResultReg = createResultReg(RC);
1134 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1136 if (II.getNumDefs() >= 1)
1137 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1138 .addReg(Op0, Op0IsKill * RegState::Kill);
1140 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1141 .addReg(Op0, Op0IsKill * RegState::Kill);
1142 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1143 ResultReg).addReg(II.ImplicitDefs[0]);
1149 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
1150 const TargetRegisterClass *RC,
1151 unsigned Op0, bool Op0IsKill,
1152 unsigned Op1, bool Op1IsKill) {
1153 unsigned ResultReg = createResultReg(RC);
1154 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1156 if (II.getNumDefs() >= 1)
1157 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1158 .addReg(Op0, Op0IsKill * RegState::Kill)
1159 .addReg(Op1, Op1IsKill * RegState::Kill);
1161 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1162 .addReg(Op0, Op0IsKill * RegState::Kill)
1163 .addReg(Op1, Op1IsKill * RegState::Kill);
1164 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1165 ResultReg).addReg(II.ImplicitDefs[0]);
1170 unsigned FastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
1171 const TargetRegisterClass *RC,
1172 unsigned Op0, bool Op0IsKill,
1173 unsigned Op1, bool Op1IsKill,
1174 unsigned Op2, bool Op2IsKill) {
1175 unsigned ResultReg = createResultReg(RC);
1176 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1178 if (II.getNumDefs() >= 1)
1179 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1180 .addReg(Op0, Op0IsKill * RegState::Kill)
1181 .addReg(Op1, Op1IsKill * RegState::Kill)
1182 .addReg(Op2, Op2IsKill * RegState::Kill);
1184 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1185 .addReg(Op0, Op0IsKill * RegState::Kill)
1186 .addReg(Op1, Op1IsKill * RegState::Kill)
1187 .addReg(Op2, Op2IsKill * RegState::Kill);
1188 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1189 ResultReg).addReg(II.ImplicitDefs[0]);
1194 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
1195 const TargetRegisterClass *RC,
1196 unsigned Op0, bool Op0IsKill,
1198 unsigned ResultReg = createResultReg(RC);
1199 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1201 if (II.getNumDefs() >= 1)
1202 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1203 .addReg(Op0, Op0IsKill * RegState::Kill)
1206 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1207 .addReg(Op0, Op0IsKill * RegState::Kill)
1209 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1210 ResultReg).addReg(II.ImplicitDefs[0]);
1215 unsigned FastISel::FastEmitInst_rii(unsigned MachineInstOpcode,
1216 const TargetRegisterClass *RC,
1217 unsigned Op0, bool Op0IsKill,
1218 uint64_t Imm1, uint64_t Imm2) {
1219 unsigned ResultReg = createResultReg(RC);
1220 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1222 if (II.getNumDefs() >= 1)
1223 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1224 .addReg(Op0, Op0IsKill * RegState::Kill)
1228 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1229 .addReg(Op0, Op0IsKill * RegState::Kill)
1232 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1233 ResultReg).addReg(II.ImplicitDefs[0]);
1238 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
1239 const TargetRegisterClass *RC,
1240 unsigned Op0, bool Op0IsKill,
1241 const ConstantFP *FPImm) {
1242 unsigned ResultReg = createResultReg(RC);
1243 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1245 if (II.getNumDefs() >= 1)
1246 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1247 .addReg(Op0, Op0IsKill * RegState::Kill)
1250 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1251 .addReg(Op0, Op0IsKill * RegState::Kill)
1253 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1254 ResultReg).addReg(II.ImplicitDefs[0]);
1259 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
1260 const TargetRegisterClass *RC,
1261 unsigned Op0, bool Op0IsKill,
1262 unsigned Op1, bool Op1IsKill,
1264 unsigned ResultReg = createResultReg(RC);
1265 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1267 if (II.getNumDefs() >= 1)
1268 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1269 .addReg(Op0, Op0IsKill * RegState::Kill)
1270 .addReg(Op1, Op1IsKill * RegState::Kill)
1273 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1274 .addReg(Op0, Op0IsKill * RegState::Kill)
1275 .addReg(Op1, Op1IsKill * RegState::Kill)
1277 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1278 ResultReg).addReg(II.ImplicitDefs[0]);
1283 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
1284 const TargetRegisterClass *RC,
1286 unsigned ResultReg = createResultReg(RC);
1287 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1289 if (II.getNumDefs() >= 1)
1290 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm);
1292 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm);
1293 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1294 ResultReg).addReg(II.ImplicitDefs[0]);
1299 unsigned FastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
1300 const TargetRegisterClass *RC,
1301 uint64_t Imm1, uint64_t Imm2) {
1302 unsigned ResultReg = createResultReg(RC);
1303 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1305 if (II.getNumDefs() >= 1)
1306 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1307 .addImm(Imm1).addImm(Imm2);
1309 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm1).addImm(Imm2);
1310 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1311 ResultReg).addReg(II.ImplicitDefs[0]);
1316 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
1317 unsigned Op0, bool Op0IsKill,
1319 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1320 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1321 "Cannot yet extract from physregs");
1322 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
1323 DL, TII.get(TargetOpcode::COPY), ResultReg)
1324 .addReg(Op0, getKillRegState(Op0IsKill), Idx);
1328 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1329 /// with all but the least significant bit set to zero.
1330 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1331 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
1334 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
1335 /// Emit code to ensure constants are copied into registers when needed.
1336 /// Remember the virtual registers that need to be added to the Machine PHI
1337 /// nodes as input. We cannot just directly add them, because expansion
1338 /// might result in multiple MBB's for one BB. As such, the start of the
1339 /// BB might correspond to a different MBB than the end.
1340 bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
1341 const TerminatorInst *TI = LLVMBB->getTerminator();
1343 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
1344 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
1346 // Check successor nodes' PHI nodes that expect a constant to be available
1348 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
1349 const BasicBlock *SuccBB = TI->getSuccessor(succ);
1350 if (!isa<PHINode>(SuccBB->begin())) continue;
1351 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
1353 // If this terminator has multiple identical successors (common for
1354 // switches), only handle each succ once.
1355 if (!SuccsHandled.insert(SuccMBB)) continue;
1357 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
1359 // At this point we know that there is a 1-1 correspondence between LLVM PHI
1360 // nodes and Machine PHI nodes, but the incoming operands have not been
1362 for (BasicBlock::const_iterator I = SuccBB->begin();
1363 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
1365 // Ignore dead phi's.
1366 if (PN->use_empty()) continue;
1368 // Only handle legal types. Two interesting things to note here. First,
1369 // by bailing out early, we may leave behind some dead instructions,
1370 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
1371 // own moves. Second, this check is necessary because FastISel doesn't
1372 // use CreateRegs to create registers, so it always creates
1373 // exactly one register for each non-void instruction.
1374 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
1375 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
1376 // Handle integer promotions, though, because they're common and easy.
1377 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
1378 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT);
1380 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
1385 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
1387 // Set the DebugLoc for the copy. Prefer the location of the operand
1388 // if there is one; use the location of the PHI otherwise.
1389 DL = PN->getDebugLoc();
1390 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp))
1391 DL = Inst->getDebugLoc();
1393 unsigned Reg = getRegForValue(PHIOp);
1395 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
1398 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));