1 //===-- FastISel.cpp - Implementation of the FastISel class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/CodeGen/Analysis.h"
43 #include "llvm/CodeGen/FastISel.h"
44 #include "llvm/ADT/Optional.h"
45 #include "llvm/ADT/Statistic.h"
46 #include "llvm/Analysis/BranchProbabilityInfo.h"
47 #include "llvm/Analysis/Loads.h"
48 #include "llvm/CodeGen/Analysis.h"
49 #include "llvm/CodeGen/FunctionLoweringInfo.h"
50 #include "llvm/CodeGen/MachineFrameInfo.h"
51 #include "llvm/CodeGen/MachineInstrBuilder.h"
52 #include "llvm/CodeGen/MachineModuleInfo.h"
53 #include "llvm/CodeGen/MachineRegisterInfo.h"
54 #include "llvm/CodeGen/StackMaps.h"
55 #include "llvm/IR/DataLayout.h"
56 #include "llvm/IR/DebugInfo.h"
57 #include "llvm/IR/Function.h"
58 #include "llvm/IR/GlobalVariable.h"
59 #include "llvm/IR/Instructions.h"
60 #include "llvm/IR/IntrinsicInst.h"
61 #include "llvm/IR/Operator.h"
62 #include "llvm/Support/Debug.h"
63 #include "llvm/Support/ErrorHandling.h"
64 #include "llvm/Target/TargetInstrInfo.h"
65 #include "llvm/Target/TargetLibraryInfo.h"
66 #include "llvm/Target/TargetLowering.h"
67 #include "llvm/Target/TargetMachine.h"
68 #include "llvm/Target/TargetSubtargetInfo.h"
71 #define DEBUG_TYPE "isel"
73 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
74 "target-independent selector");
75 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
76 "target-specific selector");
77 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
79 /// \brief Set CallLoweringInfo attribute flags based on a call instruction
80 /// and called function attributes.
81 void FastISel::ArgListEntry::setAttributes(ImmutableCallSite *CS,
83 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
84 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
85 isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
86 isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
87 isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
88 isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
89 isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
90 isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
91 Alignment = CS->getParamAlignment(AttrIdx);
94 /// startNewBlock - Set the current block to which generated machine
95 /// instructions will be appended, and clear the local CSE map.
97 void FastISel::startNewBlock() {
98 LocalValueMap.clear();
100 // Instructions are appended to FuncInfo.MBB. If the basic block already
101 // contains labels or copies, use the last instruction as the last local
103 EmitStartPt = nullptr;
104 if (!FuncInfo.MBB->empty())
105 EmitStartPt = &FuncInfo.MBB->back();
106 LastLocalValue = EmitStartPt;
109 bool FastISel::LowerArguments() {
110 if (!FuncInfo.CanLowerReturn)
111 // Fallback to SDISel argument lowering code to deal with sret pointer
115 if (!FastLowerArguments())
118 // Enter arguments into ValueMap for uses in non-entry BBs.
119 for (Function::const_arg_iterator I = FuncInfo.Fn->arg_begin(),
120 E = FuncInfo.Fn->arg_end(); I != E; ++I) {
121 DenseMap<const Value *, unsigned>::iterator VI = LocalValueMap.find(I);
122 assert(VI != LocalValueMap.end() && "Missed an argument?");
123 FuncInfo.ValueMap[I] = VI->second;
128 void FastISel::flushLocalValueMap() {
129 LocalValueMap.clear();
130 LastLocalValue = EmitStartPt;
134 bool FastISel::hasTrivialKill(const Value *V) const {
135 // Don't consider constants or arguments to have trivial kills.
136 const Instruction *I = dyn_cast<Instruction>(V);
140 // No-op casts are trivially coalesced by fast-isel.
141 if (const CastInst *Cast = dyn_cast<CastInst>(I))
142 if (Cast->isNoopCast(DL.getIntPtrType(Cast->getContext())) &&
143 !hasTrivialKill(Cast->getOperand(0)))
146 // GEPs with all zero indices are trivially coalesced by fast-isel.
147 if (const GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(I))
148 if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0)))
151 // Only instructions with a single use in the same basic block are considered
152 // to have trivial kills.
153 return I->hasOneUse() &&
154 !(I->getOpcode() == Instruction::BitCast ||
155 I->getOpcode() == Instruction::PtrToInt ||
156 I->getOpcode() == Instruction::IntToPtr) &&
157 cast<Instruction>(*I->user_begin())->getParent() == I->getParent();
160 unsigned FastISel::getRegForValue(const Value *V) {
161 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
162 // Don't handle non-simple values in FastISel.
163 if (!RealVT.isSimple())
166 // Ignore illegal types. We must do this before looking up the value
167 // in ValueMap because Arguments are given virtual registers regardless
168 // of whether FastISel can handle them.
169 MVT VT = RealVT.getSimpleVT();
170 if (!TLI.isTypeLegal(VT)) {
171 // Handle integer promotions, though, because they're common and easy.
172 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
173 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
178 // Look up the value to see if we already have a register for it.
179 unsigned Reg = lookUpRegForValue(V);
183 // In bottom-up mode, just create the virtual register which will be used
184 // to hold the value. It will be materialized later.
185 if (isa<Instruction>(V) &&
186 (!isa<AllocaInst>(V) ||
187 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
188 return FuncInfo.InitializeRegForValue(V);
190 SavePoint SaveInsertPt = enterLocalValueArea();
192 // Materialize the value in a register. Emit any instructions in the
194 Reg = materializeRegForValue(V, VT);
196 leaveLocalValueArea(SaveInsertPt);
201 unsigned FastISel::MaterializeConstant(const Value *V, MVT VT) {
203 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
204 if (CI->getValue().getActiveBits() <= 64)
205 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
206 } else if (isa<AllocaInst>(V))
207 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
208 else if (isa<ConstantPointerNull>(V))
209 // Translate this as an integer zero so that it can be
210 // local-CSE'd with actual integer zeros.
212 getRegForValue(Constant::getNullValue(DL.getIntPtrType(V->getContext())));
213 else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
214 if (CF->isNullValue())
215 Reg = TargetMaterializeFloatZero(CF);
217 // Try to emit the constant directly.
218 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
221 // Try to emit the constant by using an integer constant with a cast.
222 const APFloat &Flt = CF->getValueAPF();
223 EVT IntVT = TLI.getPointerTy();
226 uint32_t IntBitWidth = IntVT.getSizeInBits();
228 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
229 APFloat::rmTowardZero, &isExact);
231 APInt IntVal(IntBitWidth, x);
233 unsigned IntegerReg =
234 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
236 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
237 IntegerReg, /*Kill=*/false);
240 } else if (const Operator *Op = dyn_cast<Operator>(V)) {
241 if (!SelectOperator(Op, Op->getOpcode()))
242 if (!isa<Instruction>(Op) ||
243 !TargetSelectInstruction(cast<Instruction>(Op)))
245 Reg = lookUpRegForValue(Op);
246 } else if (isa<UndefValue>(V)) {
247 Reg = createResultReg(TLI.getRegClassFor(VT));
248 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
249 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
254 /// materializeRegForValue - Helper for getRegForValue. This function is
255 /// called when the value isn't already available in a register and must
256 /// be materialized with new instructions.
257 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
259 // Give the target-specific code a try first.
260 if (isa<Constant>(V))
261 Reg = TargetMaterializeConstant(cast<Constant>(V));
263 // If target-specific code couldn't or didn't want to handle the value, then
264 // give target-independent code a try.
266 Reg = MaterializeConstant(V, VT);
268 // Don't cache constant materializations in the general ValueMap.
269 // To do so would require tracking what uses they dominate.
271 LocalValueMap[V] = Reg;
272 LastLocalValue = MRI.getVRegDef(Reg);
277 unsigned FastISel::lookUpRegForValue(const Value *V) {
278 // Look up the value to see if we already have a register for it. We
279 // cache values defined by Instructions across blocks, and other values
280 // only locally. This is because Instructions already have the SSA
281 // def-dominates-use requirement enforced.
282 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
283 if (I != FuncInfo.ValueMap.end())
285 return LocalValueMap[V];
288 /// UpdateValueMap - Update the value map to include the new mapping for this
289 /// instruction, or insert an extra copy to get the result in a previous
290 /// determined register.
291 /// NOTE: This is only necessary because we might select a block that uses
292 /// a value before we select the block that defines the value. It might be
293 /// possible to fix this by selecting blocks in reverse postorder.
294 void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) {
295 if (!isa<Instruction>(I)) {
296 LocalValueMap[I] = Reg;
300 unsigned &AssignedReg = FuncInfo.ValueMap[I];
301 if (AssignedReg == 0)
302 // Use the new register.
304 else if (Reg != AssignedReg) {
305 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
306 for (unsigned i = 0; i < NumRegs; i++)
307 FuncInfo.RegFixups[AssignedReg+i] = Reg+i;
313 std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) {
314 unsigned IdxN = getRegForValue(Idx);
316 // Unhandled operand. Halt "fast" selection and bail.
317 return std::pair<unsigned, bool>(0, false);
319 bool IdxNIsKill = hasTrivialKill(Idx);
321 // If the index is smaller or larger than intptr_t, truncate or extend it.
322 MVT PtrVT = TLI.getPointerTy();
323 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
324 if (IdxVT.bitsLT(PtrVT)) {
325 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND,
329 else if (IdxVT.bitsGT(PtrVT)) {
330 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE,
334 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
337 void FastISel::recomputeInsertPt() {
338 if (getLastLocalValue()) {
339 FuncInfo.InsertPt = getLastLocalValue();
340 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
343 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
345 // Now skip past any EH_LABELs, which must remain at the beginning.
346 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
347 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
351 void FastISel::removeDeadCode(MachineBasicBlock::iterator I,
352 MachineBasicBlock::iterator E) {
353 assert (I && E && std::distance(I, E) > 0 && "Invalid iterator!");
355 MachineInstr *Dead = &*I;
357 Dead->eraseFromParent();
363 FastISel::SavePoint FastISel::enterLocalValueArea() {
364 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
365 DebugLoc OldDL = DbgLoc;
368 SavePoint SP = { OldInsertPt, OldDL };
372 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
373 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
374 LastLocalValue = std::prev(FuncInfo.InsertPt);
376 // Restore the previous insert position.
377 FuncInfo.InsertPt = OldInsertPt.InsertPt;
378 DbgLoc = OldInsertPt.DL;
381 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
382 /// which has an opcode which directly corresponds to the given ISD opcode.
384 bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) {
385 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
386 if (VT == MVT::Other || !VT.isSimple())
387 // Unhandled type. Halt "fast" selection and bail.
390 // We only handle legal types. For example, on x86-32 the instruction
391 // selector contains all of the 64-bit instructions from x86-64,
392 // under the assumption that i64 won't be used if the target doesn't
394 if (!TLI.isTypeLegal(VT)) {
395 // MVT::i1 is special. Allow AND, OR, or XOR because they
396 // don't require additional zeroing, which makes them easy.
398 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
399 ISDOpcode == ISD::XOR))
400 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
405 // Check if the first operand is a constant, and handle it as "ri". At -O0,
406 // we don't have anything that canonicalizes operand order.
407 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
408 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
409 unsigned Op1 = getRegForValue(I->getOperand(1));
410 if (Op1 == 0) return false;
412 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
414 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
415 Op1IsKill, CI->getZExtValue(),
417 if (ResultReg == 0) return false;
419 // We successfully emitted code for the given LLVM Instruction.
420 UpdateValueMap(I, ResultReg);
425 unsigned Op0 = getRegForValue(I->getOperand(0));
426 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail.
429 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
431 // Check if the second operand is a constant and handle it appropriately.
432 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
433 uint64_t Imm = CI->getZExtValue();
435 // Transform "sdiv exact X, 8" -> "sra X, 3".
436 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
437 cast<BinaryOperator>(I)->isExact() &&
438 isPowerOf2_64(Imm)) {
440 ISDOpcode = ISD::SRA;
443 // Transform "urem x, pow2" -> "and x, pow2-1".
444 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
445 isPowerOf2_64(Imm)) {
447 ISDOpcode = ISD::AND;
450 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
451 Op0IsKill, Imm, VT.getSimpleVT());
452 if (ResultReg == 0) return false;
454 // We successfully emitted code for the given LLVM Instruction.
455 UpdateValueMap(I, ResultReg);
459 // Check if the second operand is a constant float.
460 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
461 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
462 ISDOpcode, Op0, Op0IsKill, CF);
463 if (ResultReg != 0) {
464 // We successfully emitted code for the given LLVM Instruction.
465 UpdateValueMap(I, ResultReg);
470 unsigned Op1 = getRegForValue(I->getOperand(1));
472 // Unhandled operand. Halt "fast" selection and bail.
475 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
477 // Now we have both operands in registers. Emit the instruction.
478 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
483 // Target-specific code wasn't able to find a machine opcode for
484 // the given ISD opcode and type. Halt "fast" selection and bail.
487 // We successfully emitted code for the given LLVM Instruction.
488 UpdateValueMap(I, ResultReg);
492 bool FastISel::SelectGetElementPtr(const User *I) {
493 unsigned N = getRegForValue(I->getOperand(0));
495 // Unhandled operand. Halt "fast" selection and bail.
498 bool NIsKill = hasTrivialKill(I->getOperand(0));
500 // Keep a running tab of the total offset to coalesce multiple N = N + Offset
501 // into a single N = N + TotalOffset.
502 uint64_t TotalOffs = 0;
503 // FIXME: What's a good SWAG number for MaxOffs?
504 uint64_t MaxOffs = 2048;
505 Type *Ty = I->getOperand(0)->getType();
506 MVT VT = TLI.getPointerTy();
507 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1,
508 E = I->op_end(); OI != E; ++OI) {
509 const Value *Idx = *OI;
510 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
511 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
514 TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
515 if (TotalOffs >= MaxOffs) {
516 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
518 // Unhandled operand. Halt "fast" selection and bail.
524 Ty = StTy->getElementType(Field);
526 Ty = cast<SequentialType>(Ty)->getElementType();
528 // If this is a constant subscript, handle it quickly.
529 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
530 if (CI->isZero()) continue;
533 DL.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
534 if (TotalOffs >= MaxOffs) {
535 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
537 // Unhandled operand. Halt "fast" selection and bail.
545 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
547 // Unhandled operand. Halt "fast" selection and bail.
553 // N = N + Idx * ElementSize;
554 uint64_t ElementSize = DL.getTypeAllocSize(Ty);
555 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
556 unsigned IdxN = Pair.first;
557 bool IdxNIsKill = Pair.second;
559 // Unhandled operand. Halt "fast" selection and bail.
562 if (ElementSize != 1) {
563 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
565 // Unhandled operand. Halt "fast" selection and bail.
569 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
571 // Unhandled operand. Halt "fast" selection and bail.
576 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
578 // Unhandled operand. Halt "fast" selection and bail.
582 // We successfully emitted code for the given LLVM Instruction.
583 UpdateValueMap(I, N);
587 /// \brief Add a stackmap or patchpoint intrinsic call's live variable operands
588 /// to a stackmap or patchpoint machine instruction.
589 bool FastISel::addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
590 const CallInst *CI, unsigned StartIdx) {
591 for (unsigned i = StartIdx, e = CI->getNumArgOperands(); i != e; ++i) {
592 Value *Val = CI->getArgOperand(i);
593 // Check for constants and encode them with a StackMaps::ConstantOp prefix.
594 if (auto *C = dyn_cast<ConstantInt>(Val)) {
595 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
596 Ops.push_back(MachineOperand::CreateImm(C->getSExtValue()));
597 } else if (isa<ConstantPointerNull>(Val)) {
598 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
599 Ops.push_back(MachineOperand::CreateImm(0));
600 } else if (auto *AI = dyn_cast<AllocaInst>(Val)) {
601 // Values coming from a stack location also require a sepcial encoding,
602 // but that is added later on by the target specific frame index
603 // elimination implementation.
604 auto SI = FuncInfo.StaticAllocaMap.find(AI);
605 if (SI != FuncInfo.StaticAllocaMap.end())
606 Ops.push_back(MachineOperand::CreateFI(SI->second));
610 unsigned Reg = getRegForValue(Val);
613 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
620 bool FastISel::SelectStackmap(const CallInst *I) {
621 // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
622 // [live variables...])
623 assert(I->getCalledFunction()->getReturnType()->isVoidTy() &&
624 "Stackmap cannot return a value.");
626 // The stackmap intrinsic only records the live variables (the arguments
627 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
628 // intrinsic, this won't be lowered to a function call. This means we don't
629 // have to worry about calling conventions and target-specific lowering code.
630 // Instead we perform the call lowering right here.
633 // STACKMAP(id, nbytes, ...)
636 SmallVector<MachineOperand, 32> Ops;
638 // Add the <id> and <numBytes> constants.
639 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
640 "Expected a constant integer.");
641 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
642 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
644 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
645 "Expected a constant integer.");
646 const auto *NumBytes =
647 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
648 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
650 // Push live variables for the stack map (skipping the first two arguments
651 // <id> and <numBytes>).
652 if (!addStackMapLiveVars(Ops, I, 2))
655 // We are not adding any register mask info here, because the stackmap doesn't
658 // Add scratch registers as implicit def and early clobber.
659 CallingConv::ID CC = I->getCallingConv();
660 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
661 for (unsigned i = 0; ScratchRegs[i]; ++i)
662 Ops.push_back(MachineOperand::CreateReg(
663 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
664 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
666 // Issue CALLSEQ_START
667 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
668 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown))
672 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
673 TII.get(TargetOpcode::STACKMAP));
674 for (auto const &MO : Ops)
678 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
679 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
680 .addImm(0).addImm(0);
682 // Inform the Frame Information that we have a stackmap in this function.
683 FuncInfo.MF->getFrameInfo()->setHasStackMap();
688 /// \brief Lower an argument list according to the target calling convention.
690 /// This is a helper for lowering intrinsics that follow a target calling
691 /// convention or require stack pointer adjustment. Only a subset of the
692 /// intrinsic's operands need to participate in the calling convention.
693 bool FastISel::lowerCallOperands(const CallInst *CI, unsigned ArgIdx,
694 unsigned NumArgs, const Value *Callee,
695 bool ForceRetVoidTy, CallLoweringInfo &CLI) {
697 Args.reserve(NumArgs);
699 // Populate the argument list.
700 // Attributes for args start at offset 1, after the return attribute.
701 ImmutableCallSite CS(CI);
702 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
703 ArgI != ArgE; ++ArgI) {
704 Value *V = CI->getOperand(ArgI);
706 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
710 Entry.Ty = V->getType();
711 Entry.setAttributes(&CS, AttrI);
712 Args.push_back(Entry);
715 Type *RetTy = ForceRetVoidTy ? Type::getVoidTy(CI->getType()->getContext())
717 CLI.setCallee(CI->getCallingConv(), RetTy, Callee, std::move(Args), NumArgs);
719 return LowerCallTo(CLI);
722 bool FastISel::SelectPatchpoint(const CallInst *I) {
723 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
728 // [live variables...])
729 CallingConv::ID CC = I->getCallingConv();
730 bool IsAnyRegCC = CC == CallingConv::AnyReg;
731 bool HasDef = !I->getType()->isVoidTy();
732 Value *Callee = I->getOperand(PatchPointOpers::TargetPos);
734 // Get the real number of arguments participating in the call <numArgs>
735 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos)) &&
736 "Expected a constant integer.");
737 const auto *NumArgsVal =
738 cast<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos));
739 unsigned NumArgs = NumArgsVal->getZExtValue();
741 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
742 // This includes all meta-operands up to but not including CC.
743 unsigned NumMetaOpers = PatchPointOpers::CCPos;
744 assert(I->getNumArgOperands() >= NumMetaOpers + NumArgs &&
745 "Not enough arguments provided to the patchpoint intrinsic");
747 // For AnyRegCC the arguments are lowered later on manually.
748 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
749 CallLoweringInfo CLI;
750 if (!lowerCallOperands(I, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC, CLI))
753 assert(CLI.Call && "No call instruction specified.");
755 SmallVector<MachineOperand, 32> Ops;
757 // Add an explicit result reg if we use the anyreg calling convention.
758 if (IsAnyRegCC && HasDef) {
759 assert(CLI.NumResultRegs == 0 && "Unexpected result register.");
760 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
761 CLI.NumResultRegs = 1;
762 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true));
765 // Add the <id> and <numBytes> constants.
766 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
767 "Expected a constant integer.");
768 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
769 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
771 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
772 "Expected a constant integer.");
773 const auto *NumBytes =
774 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
775 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
777 // Assume that the callee is a constant address or null pointer.
778 // FIXME: handle function symbols in the future.
780 if (const auto *C = dyn_cast<IntToPtrInst>(Callee))
781 CalleeAddr = cast<ConstantInt>(C->getOperand(0))->getZExtValue();
782 else if (const auto *C = dyn_cast<ConstantExpr>(Callee)) {
783 if (C->getOpcode() == Instruction::IntToPtr)
784 CalleeAddr = cast<ConstantInt>(C->getOperand(0))->getZExtValue();
786 llvm_unreachable("Unsupported ConstantExpr.");
787 } else if (isa<ConstantPointerNull>(Callee))
790 llvm_unreachable("Unsupported callee address.");
792 Ops.push_back(MachineOperand::CreateImm(CalleeAddr));
794 // Adjust <numArgs> to account for any arguments that have been passed on
795 // the stack instead.
796 unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size();
797 Ops.push_back(MachineOperand::CreateImm(NumCallRegArgs));
799 // Add the calling convention
800 Ops.push_back(MachineOperand::CreateImm((unsigned)CC));
802 // Add the arguments we omitted previously. The register allocator should
803 // place these in any free register.
805 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) {
806 unsigned Reg = getRegForValue(I->getArgOperand(i));
809 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
813 // Push the arguments from the call instruction.
814 for (auto Reg : CLI.OutRegs)
815 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
817 // Push live variables for the stack map.
818 if (!addStackMapLiveVars(Ops, I, NumMetaOpers + NumArgs))
821 // Push the register mask info.
822 Ops.push_back(MachineOperand::CreateRegMask(TRI.getCallPreservedMask(CC)));
824 // Add scratch registers as implicit def and early clobber.
825 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
826 for (unsigned i = 0; ScratchRegs[i]; ++i)
827 Ops.push_back(MachineOperand::CreateReg(
828 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
829 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
831 // Add implicit defs (return values).
832 for (auto Reg : CLI.InRegs)
833 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/true,
836 // Insert the patchpoint instruction before the call generated by the target.
837 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, CLI.Call, DbgLoc,
838 TII.get(TargetOpcode::PATCHPOINT));
843 MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);
845 // Delete the original call instruction.
846 CLI.Call->eraseFromParent();
848 // Inform the Frame Information that we have a patchpoint in this function.
849 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
851 if (CLI.NumResultRegs)
852 UpdateValueMap(I, CLI.ResultReg, CLI.NumResultRegs);
856 /// Returns an AttributeSet representing the attributes applied to the return
857 /// value of the given call.
858 static AttributeSet getReturnAttrs(FastISel::CallLoweringInfo &CLI) {
859 SmallVector<Attribute::AttrKind, 2> Attrs;
861 Attrs.push_back(Attribute::SExt);
863 Attrs.push_back(Attribute::ZExt);
865 Attrs.push_back(Attribute::InReg);
867 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
871 bool FastISel::LowerCallTo(const CallInst *CI, const char *SymName,
873 ImmutableCallSite CS(CI);
875 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
876 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
877 Type *RetTy = FTy->getReturnType();
880 Args.reserve(NumArgs);
882 // Populate the argument list.
883 // Attributes for args start at offset 1, after the return attribute.
884 for (unsigned ArgI = 0; ArgI != NumArgs; ++ArgI) {
885 Value *V = CI->getOperand(ArgI);
887 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
891 Entry.Ty = V->getType();
892 Entry.setAttributes(&CS, ArgI + 1);
893 Args.push_back(Entry);
896 CallLoweringInfo CLI;
897 CLI.setCallee(RetTy, FTy, SymName, std::move(Args), CS, NumArgs);
899 return LowerCallTo(CLI);
902 bool FastISel::LowerCallTo(CallLoweringInfo &CLI) {
903 // Handle the incoming return values from the call.
905 SmallVector<EVT, 4> RetTys;
906 ComputeValueVTs(TLI, CLI.RetTy, RetTys);
908 SmallVector<ISD::OutputArg, 4> Outs;
909 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, TLI);
911 bool CanLowerReturn = TLI.CanLowerReturn(CLI.CallConv, *FuncInfo.MF,
913 CLI.RetTy->getContext());
915 // FIXME: sret demotion isn't supported yet - bail out.
919 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
921 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT);
922 unsigned NumRegs = TLI.getNumRegisters(CLI.RetTy->getContext(), VT);
923 for (unsigned i = 0; i != NumRegs; ++i) {
924 ISD::InputArg MyFlags;
925 MyFlags.VT = RegisterVT;
927 MyFlags.Used = CLI.IsReturnValueUsed;
929 MyFlags.Flags.setSExt();
931 MyFlags.Flags.setZExt();
933 MyFlags.Flags.setInReg();
934 CLI.Ins.push_back(MyFlags);
938 // Handle all of the outgoing arguments.
940 for (auto &Arg : CLI.getArgs()) {
941 Type *FinalType = Arg.Ty;
943 FinalType = cast<PointerType>(Arg.Ty)->getElementType();
944 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
945 FinalType, CLI.CallConv, CLI.IsVarArg);
947 ISD::ArgFlagsTy Flags;
958 if (Arg.isInAlloca) {
960 // Set the byval flag for CCAssignFn callbacks that don't know about
961 // inalloca. This way we can know how many bytes we should've allocated
962 // and how many bytes a callee cleanup function will pop. If we port
963 // inalloca to more targets, we'll have to add custom inalloca handling in
964 // the various CC lowering callbacks.
967 if (Arg.isByVal || Arg.isInAlloca) {
968 PointerType *Ty = cast<PointerType>(Arg.Ty);
969 Type *ElementTy = Ty->getElementType();
970 unsigned FrameSize = DL.getTypeAllocSize(ElementTy);
971 // For ByVal, alignment should come from FE. BE will guess if this info is
972 // not there, but there are cases it cannot get right.
973 unsigned FrameAlign = Arg.Alignment;
975 FrameAlign = TLI.getByValTypeAlignment(ElementTy);
976 Flags.setByValSize(FrameSize);
977 Flags.setByValAlign(FrameAlign);
982 Flags.setInConsecutiveRegs();
983 unsigned OriginalAlignment = DL.getABITypeAlignment(Arg.Ty);
984 Flags.setOrigAlign(OriginalAlignment);
986 CLI.OutVals.push_back(Arg.Val);
987 CLI.OutFlags.push_back(Flags);
990 if (!FastLowerCall(CLI))
993 // Set all unused physreg defs as dead.
994 assert(CLI.Call && "No call instruction specified.");
995 CLI.Call->setPhysRegsDeadExcept(CLI.InRegs, TRI);
997 if (CLI.NumResultRegs && CLI.CS)
998 UpdateValueMap(CLI.CS->getInstruction(), CLI.ResultReg, CLI.NumResultRegs);
1003 bool FastISel::LowerCall(const CallInst *CI) {
1004 ImmutableCallSite CS(CI);
1006 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1007 FunctionType *FuncTy = cast<FunctionType>(PT->getElementType());
1008 Type *RetTy = FuncTy->getReturnType();
1012 Args.reserve(CS.arg_size());
1014 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1019 if (V->getType()->isEmptyTy())
1023 Entry.Ty = V->getType();
1025 // Skip the first return-type Attribute to get to params.
1026 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
1027 Args.push_back(Entry);
1030 // Check if target-independent constraints permit a tail call here.
1031 // Target-dependent constraints are checked within FastLowerCall.
1032 bool IsTailCall = CI->isTailCall();
1033 if (IsTailCall && !isInTailCallPosition(CS, TM))
1036 CallLoweringInfo CLI;
1037 CLI.setCallee(RetTy, FuncTy, CI->getCalledValue(), std::move(Args), CS)
1038 .setTailCall(IsTailCall);
1040 return LowerCallTo(CLI);
1043 bool FastISel::SelectCall(const User *I) {
1044 const CallInst *Call = cast<CallInst>(I);
1046 // Handle simple inline asms.
1047 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledValue())) {
1048 // If the inline asm has side effects, then make sure that no local value
1049 // lives across by flushing the local value map.
1050 if (IA->hasSideEffects())
1051 flushLocalValueMap();
1053 // Don't attempt to handle constraints.
1054 if (!IA->getConstraintString().empty())
1057 unsigned ExtraInfo = 0;
1058 if (IA->hasSideEffects())
1059 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1060 if (IA->isAlignStack())
1061 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
1063 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1064 TII.get(TargetOpcode::INLINEASM))
1065 .addExternalSymbol(IA->getAsmString().c_str())
1070 MachineModuleInfo &MMI = FuncInfo.MF->getMMI();
1071 ComputeUsesVAFloatArgument(*Call, &MMI);
1073 // Handle intrinsic function calls.
1074 if (const auto *II = dyn_cast<IntrinsicInst>(Call))
1075 return SelectIntrinsicCall(II);
1077 // Usually, it does not make sense to initialize a value,
1078 // make an unrelated function call and use the value, because
1079 // it tends to be spilled on the stack. So, we move the pointer
1080 // to the last local value to the beginning of the block, so that
1081 // all the values which have already been materialized,
1082 // appear after the call. It also makes sense to skip intrinsics
1083 // since they tend to be inlined.
1084 flushLocalValueMap();
1086 return LowerCall(Call);
1089 bool FastISel::SelectIntrinsicCall(const IntrinsicInst *II) {
1090 switch (II->getIntrinsicID()) {
1092 // At -O0 we don't care about the lifetime intrinsics.
1093 case Intrinsic::lifetime_start:
1094 case Intrinsic::lifetime_end:
1095 // The donothing intrinsic does, well, nothing.
1096 case Intrinsic::donothing:
1098 case Intrinsic::dbg_declare: {
1099 const DbgDeclareInst *DI = cast<DbgDeclareInst>(II);
1100 DIVariable DIVar(DI->getVariable());
1101 assert((!DIVar || DIVar.isVariable()) &&
1102 "Variable in DbgDeclareInst should be either null or a DIVariable.");
1103 if (!DIVar || !FuncInfo.MF->getMMI().hasDebugInfo()) {
1104 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1108 const Value *Address = DI->getAddress();
1109 if (!Address || isa<UndefValue>(Address)) {
1110 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1114 unsigned Offset = 0;
1115 Optional<MachineOperand> Op;
1116 if (const Argument *Arg = dyn_cast<Argument>(Address))
1117 // Some arguments' frame index is recorded during argument lowering.
1118 Offset = FuncInfo.getArgumentFrameIndex(Arg);
1120 Op = MachineOperand::CreateFI(Offset);
1122 if (unsigned Reg = lookUpRegForValue(Address))
1123 Op = MachineOperand::CreateReg(Reg, false);
1125 // If we have a VLA that has a "use" in a metadata node that's then used
1126 // here but it has no other uses, then we have a problem. E.g.,
1128 // int foo (const int *x) {
1133 // If we assign 'a' a vreg and fast isel later on has to use the selection
1134 // DAG isel, it will want to copy the value to the vreg. However, there are
1135 // no uses, which goes counter to what selection DAG isel expects.
1136 if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&
1137 (!isa<AllocaInst>(Address) ||
1138 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
1139 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
1144 Op->setIsDebug(true);
1145 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1146 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0,
1149 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1150 TII.get(TargetOpcode::DBG_VALUE))
1153 .addMetadata(DI->getVariable());
1155 // We can't yet handle anything else here because it would require
1156 // generating code, thus altering codegen because of debug info.
1157 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1161 case Intrinsic::dbg_value: {
1162 // This form of DBG_VALUE is target-independent.
1163 const DbgValueInst *DI = cast<DbgValueInst>(II);
1164 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1165 const Value *V = DI->getValue();
1167 // Currently the optimizer can produce this; insert an undef to
1168 // help debugging. Probably the optimizer should not do this.
1169 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1170 .addReg(0U).addImm(DI->getOffset())
1171 .addMetadata(DI->getVariable());
1172 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
1173 if (CI->getBitWidth() > 64)
1174 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1175 .addCImm(CI).addImm(DI->getOffset())
1176 .addMetadata(DI->getVariable());
1178 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1179 .addImm(CI->getZExtValue()).addImm(DI->getOffset())
1180 .addMetadata(DI->getVariable());
1181 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
1182 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1183 .addFPImm(CF).addImm(DI->getOffset())
1184 .addMetadata(DI->getVariable());
1185 } else if (unsigned Reg = lookUpRegForValue(V)) {
1186 // FIXME: This does not handle register-indirect values at offset 0.
1187 bool IsIndirect = DI->getOffset() != 0;
1188 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, IsIndirect,
1189 Reg, DI->getOffset(), DI->getVariable());
1191 // We can't yet handle anything else here because it would require
1192 // generating code, thus altering codegen because of debug info.
1193 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1197 case Intrinsic::objectsize: {
1198 ConstantInt *CI = cast<ConstantInt>(II->getArgOperand(1));
1199 unsigned long long Res = CI->isZero() ? -1ULL : 0;
1200 Constant *ResCI = ConstantInt::get(II->getType(), Res);
1201 unsigned ResultReg = getRegForValue(ResCI);
1204 UpdateValueMap(II, ResultReg);
1207 case Intrinsic::expect: {
1208 unsigned ResultReg = getRegForValue(II->getArgOperand(0));
1211 UpdateValueMap(II, ResultReg);
1214 case Intrinsic::experimental_stackmap:
1215 return SelectStackmap(II);
1216 case Intrinsic::experimental_patchpoint_void:
1217 case Intrinsic::experimental_patchpoint_i64:
1218 return SelectPatchpoint(II);
1221 return FastLowerIntrinsicCall(II);
1224 bool FastISel::SelectCast(const User *I, unsigned Opcode) {
1225 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1226 EVT DstVT = TLI.getValueType(I->getType());
1228 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
1229 DstVT == MVT::Other || !DstVT.isSimple())
1230 // Unhandled type. Halt "fast" selection and bail.
1233 // Check if the destination type is legal.
1234 if (!TLI.isTypeLegal(DstVT))
1237 // Check if the source operand is legal.
1238 if (!TLI.isTypeLegal(SrcVT))
1241 unsigned InputReg = getRegForValue(I->getOperand(0));
1243 // Unhandled operand. Halt "fast" selection and bail.
1246 bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
1248 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
1249 DstVT.getSimpleVT(),
1251 InputReg, InputRegIsKill);
1255 UpdateValueMap(I, ResultReg);
1259 bool FastISel::SelectBitCast(const User *I) {
1260 // If the bitcast doesn't change the type, just use the operand value.
1261 if (I->getType() == I->getOperand(0)->getType()) {
1262 unsigned Reg = getRegForValue(I->getOperand(0));
1265 UpdateValueMap(I, Reg);
1269 // Bitcasts of other values become reg-reg copies or BITCAST operators.
1270 EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType());
1271 EVT DstEVT = TLI.getValueType(I->getType());
1272 if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
1273 !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
1274 // Unhandled type. Halt "fast" selection and bail.
1277 MVT SrcVT = SrcEVT.getSimpleVT();
1278 MVT DstVT = DstEVT.getSimpleVT();
1279 unsigned Op0 = getRegForValue(I->getOperand(0));
1281 // Unhandled operand. Halt "fast" selection and bail.
1284 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
1286 // First, try to perform the bitcast by inserting a reg-reg copy.
1287 unsigned ResultReg = 0;
1288 if (SrcVT == DstVT) {
1289 const TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
1290 const TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
1291 // Don't attempt a cross-class copy. It will likely fail.
1292 if (SrcClass == DstClass) {
1293 ResultReg = createResultReg(DstClass);
1294 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1295 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
1299 // If the reg-reg copy failed, select a BITCAST opcode.
1301 ResultReg = FastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1306 UpdateValueMap(I, ResultReg);
1311 FastISel::SelectInstruction(const Instruction *I) {
1312 // Just before the terminator instruction, insert instructions to
1313 // feed PHI nodes in successor blocks.
1314 if (isa<TerminatorInst>(I))
1315 if (!HandlePHINodesInSuccessorBlocks(I->getParent()))
1318 DbgLoc = I->getDebugLoc();
1320 MachineBasicBlock::iterator SavedInsertPt = FuncInfo.InsertPt;
1322 if (const CallInst *Call = dyn_cast<CallInst>(I)) {
1323 const Function *F = Call->getCalledFunction();
1326 // As a special case, don't handle calls to builtin library functions that
1327 // may be translated directly to target instructions.
1328 if (F && !F->hasLocalLinkage() && F->hasName() &&
1329 LibInfo->getLibFunc(F->getName(), Func) &&
1330 LibInfo->hasOptimizedCodeGen(Func))
1333 // Don't handle Intrinsic::trap if a trap funciton is specified.
1334 if (F && F->getIntrinsicID() == Intrinsic::trap &&
1335 !TM.Options.getTrapFunctionName().empty())
1339 // First, try doing target-independent selection.
1340 if (SelectOperator(I, I->getOpcode())) {
1341 ++NumFastIselSuccessIndependent;
1342 DbgLoc = DebugLoc();
1345 // Remove dead code. However, ignore call instructions since we've flushed
1346 // the local value map and recomputed the insert point.
1347 if (!isa<CallInst>(I)) {
1348 recomputeInsertPt();
1349 if (SavedInsertPt != FuncInfo.InsertPt)
1350 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1353 // Next, try calling the target to attempt to handle the instruction.
1354 SavedInsertPt = FuncInfo.InsertPt;
1355 if (TargetSelectInstruction(I)) {
1356 ++NumFastIselSuccessTarget;
1357 DbgLoc = DebugLoc();
1360 // Check for dead code and remove as necessary.
1361 recomputeInsertPt();
1362 if (SavedInsertPt != FuncInfo.InsertPt)
1363 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1365 DbgLoc = DebugLoc();
1369 /// FastEmitBranch - Emit an unconditional branch to the given block,
1370 /// unless it is the immediate (fall-through) successor, and update
1373 FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DbgLoc) {
1374 if (FuncInfo.MBB->getBasicBlock()->size() > 1 &&
1375 FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
1376 // For more accurate line information if this is the only instruction
1377 // in the block then emit it, otherwise we have the unconditional
1378 // fall-through case, which needs no instructions.
1380 // The unconditional branch case.
1381 TII.InsertBranch(*FuncInfo.MBB, MSucc, nullptr,
1382 SmallVector<MachineOperand, 0>(), DbgLoc);
1384 uint32_t BranchWeight = 0;
1386 BranchWeight = FuncInfo.BPI->getEdgeWeight(FuncInfo.MBB->getBasicBlock(),
1387 MSucc->getBasicBlock());
1388 FuncInfo.MBB->addSuccessor(MSucc, BranchWeight);
1391 /// SelectFNeg - Emit an FNeg operation.
1394 FastISel::SelectFNeg(const User *I) {
1395 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
1396 if (OpReg == 0) return false;
1398 bool OpRegIsKill = hasTrivialKill(I);
1400 // If the target has ISD::FNEG, use it.
1401 EVT VT = TLI.getValueType(I->getType());
1402 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
1403 ISD::FNEG, OpReg, OpRegIsKill);
1404 if (ResultReg != 0) {
1405 UpdateValueMap(I, ResultReg);
1409 // Bitcast the value to integer, twiddle the sign bit with xor,
1410 // and then bitcast it back to floating-point.
1411 if (VT.getSizeInBits() > 64) return false;
1412 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
1413 if (!TLI.isTypeLegal(IntVT))
1416 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1417 ISD::BITCAST, OpReg, OpRegIsKill);
1421 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR,
1422 IntReg, /*Kill=*/true,
1423 UINT64_C(1) << (VT.getSizeInBits()-1),
1424 IntVT.getSimpleVT());
1425 if (IntResultReg == 0)
1428 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
1429 ISD::BITCAST, IntResultReg, /*Kill=*/true);
1433 UpdateValueMap(I, ResultReg);
1438 FastISel::SelectExtractValue(const User *U) {
1439 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
1443 // Make sure we only try to handle extracts with a legal result. But also
1444 // allow i1 because it's easy.
1445 EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true);
1446 if (!RealVT.isSimple())
1448 MVT VT = RealVT.getSimpleVT();
1449 if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
1452 const Value *Op0 = EVI->getOperand(0);
1453 Type *AggTy = Op0->getType();
1455 // Get the base result register.
1457 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
1458 if (I != FuncInfo.ValueMap.end())
1459 ResultReg = I->second;
1460 else if (isa<Instruction>(Op0))
1461 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1463 return false; // fast-isel can't handle aggregate constants at the moment
1465 // Get the actual result register, which is an offset from the base register.
1466 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
1468 SmallVector<EVT, 4> AggValueVTs;
1469 ComputeValueVTs(TLI, AggTy, AggValueVTs);
1471 for (unsigned i = 0; i < VTIndex; i++)
1472 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1474 UpdateValueMap(EVI, ResultReg);
1479 FastISel::SelectOperator(const User *I, unsigned Opcode) {
1481 case Instruction::Add:
1482 return SelectBinaryOp(I, ISD::ADD);
1483 case Instruction::FAdd:
1484 return SelectBinaryOp(I, ISD::FADD);
1485 case Instruction::Sub:
1486 return SelectBinaryOp(I, ISD::SUB);
1487 case Instruction::FSub:
1488 // FNeg is currently represented in LLVM IR as a special case of FSub.
1489 if (BinaryOperator::isFNeg(I))
1490 return SelectFNeg(I);
1491 return SelectBinaryOp(I, ISD::FSUB);
1492 case Instruction::Mul:
1493 return SelectBinaryOp(I, ISD::MUL);
1494 case Instruction::FMul:
1495 return SelectBinaryOp(I, ISD::FMUL);
1496 case Instruction::SDiv:
1497 return SelectBinaryOp(I, ISD::SDIV);
1498 case Instruction::UDiv:
1499 return SelectBinaryOp(I, ISD::UDIV);
1500 case Instruction::FDiv:
1501 return SelectBinaryOp(I, ISD::FDIV);
1502 case Instruction::SRem:
1503 return SelectBinaryOp(I, ISD::SREM);
1504 case Instruction::URem:
1505 return SelectBinaryOp(I, ISD::UREM);
1506 case Instruction::FRem:
1507 return SelectBinaryOp(I, ISD::FREM);
1508 case Instruction::Shl:
1509 return SelectBinaryOp(I, ISD::SHL);
1510 case Instruction::LShr:
1511 return SelectBinaryOp(I, ISD::SRL);
1512 case Instruction::AShr:
1513 return SelectBinaryOp(I, ISD::SRA);
1514 case Instruction::And:
1515 return SelectBinaryOp(I, ISD::AND);
1516 case Instruction::Or:
1517 return SelectBinaryOp(I, ISD::OR);
1518 case Instruction::Xor:
1519 return SelectBinaryOp(I, ISD::XOR);
1521 case Instruction::GetElementPtr:
1522 return SelectGetElementPtr(I);
1524 case Instruction::Br: {
1525 const BranchInst *BI = cast<BranchInst>(I);
1527 if (BI->isUnconditional()) {
1528 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
1529 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
1530 FastEmitBranch(MSucc, BI->getDebugLoc());
1534 // Conditional branches are not handed yet.
1535 // Halt "fast" selection and bail.
1539 case Instruction::Unreachable:
1540 if (TM.Options.TrapUnreachable)
1541 return FastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
1545 case Instruction::Alloca:
1546 // FunctionLowering has the static-sized case covered.
1547 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
1550 // Dynamic-sized alloca is not handled yet.
1553 case Instruction::Call:
1554 return SelectCall(I);
1556 case Instruction::BitCast:
1557 return SelectBitCast(I);
1559 case Instruction::FPToSI:
1560 return SelectCast(I, ISD::FP_TO_SINT);
1561 case Instruction::ZExt:
1562 return SelectCast(I, ISD::ZERO_EXTEND);
1563 case Instruction::SExt:
1564 return SelectCast(I, ISD::SIGN_EXTEND);
1565 case Instruction::Trunc:
1566 return SelectCast(I, ISD::TRUNCATE);
1567 case Instruction::SIToFP:
1568 return SelectCast(I, ISD::SINT_TO_FP);
1570 case Instruction::IntToPtr: // Deliberate fall-through.
1571 case Instruction::PtrToInt: {
1572 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
1573 EVT DstVT = TLI.getValueType(I->getType());
1574 if (DstVT.bitsGT(SrcVT))
1575 return SelectCast(I, ISD::ZERO_EXTEND);
1576 if (DstVT.bitsLT(SrcVT))
1577 return SelectCast(I, ISD::TRUNCATE);
1578 unsigned Reg = getRegForValue(I->getOperand(0));
1579 if (Reg == 0) return false;
1580 UpdateValueMap(I, Reg);
1584 case Instruction::ExtractValue:
1585 return SelectExtractValue(I);
1587 case Instruction::PHI:
1588 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1591 // Unhandled instruction. Halt "fast" selection and bail.
1596 FastISel::FastISel(FunctionLoweringInfo &funcInfo,
1597 const TargetLibraryInfo *libInfo)
1598 : FuncInfo(funcInfo), MF(funcInfo.MF), MRI(FuncInfo.MF->getRegInfo()),
1599 MFI(*FuncInfo.MF->getFrameInfo()), MCP(*FuncInfo.MF->getConstantPool()),
1600 TM(FuncInfo.MF->getTarget()), DL(*TM.getSubtargetImpl()->getDataLayout()),
1601 TII(*TM.getSubtargetImpl()->getInstrInfo()),
1602 TLI(*TM.getSubtargetImpl()->getTargetLowering()),
1603 TRI(*TM.getSubtargetImpl()->getRegisterInfo()), LibInfo(libInfo) {}
1605 FastISel::~FastISel() {}
1607 bool FastISel::FastLowerArguments() {
1611 bool FastISel::FastLowerCall(CallLoweringInfo &/*CLI*/) {
1615 bool FastISel::FastLowerIntrinsicCall(const IntrinsicInst * /*II*/) {
1619 unsigned FastISel::FastEmit_(MVT, MVT,
1624 unsigned FastISel::FastEmit_r(MVT, MVT,
1626 unsigned /*Op0*/, bool /*Op0IsKill*/) {
1630 unsigned FastISel::FastEmit_rr(MVT, MVT,
1632 unsigned /*Op0*/, bool /*Op0IsKill*/,
1633 unsigned /*Op1*/, bool /*Op1IsKill*/) {
1637 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1641 unsigned FastISel::FastEmit_f(MVT, MVT,
1642 unsigned, const ConstantFP * /*FPImm*/) {
1646 unsigned FastISel::FastEmit_ri(MVT, MVT,
1648 unsigned /*Op0*/, bool /*Op0IsKill*/,
1653 unsigned FastISel::FastEmit_rf(MVT, MVT,
1655 unsigned /*Op0*/, bool /*Op0IsKill*/,
1656 const ConstantFP * /*FPImm*/) {
1660 unsigned FastISel::FastEmit_rri(MVT, MVT,
1662 unsigned /*Op0*/, bool /*Op0IsKill*/,
1663 unsigned /*Op1*/, bool /*Op1IsKill*/,
1668 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
1669 /// to emit an instruction with an immediate operand using FastEmit_ri.
1670 /// If that fails, it materializes the immediate into a register and try
1671 /// FastEmit_rr instead.
1672 unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode,
1673 unsigned Op0, bool Op0IsKill,
1674 uint64_t Imm, MVT ImmType) {
1675 // If this is a multiply by a power of two, emit this as a shift left.
1676 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1679 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1680 // div x, 8 -> srl x, 3
1685 // Horrible hack (to be removed), check to make sure shift amounts are
1687 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1688 Imm >= VT.getSizeInBits())
1691 // First check if immediate type is legal. If not, we can't use the ri form.
1692 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1695 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1696 if (MaterialReg == 0) {
1697 // This is a bit ugly/slow, but failing here means falling out of
1698 // fast-isel, which would be very slow.
1699 IntegerType *ITy = IntegerType::get(FuncInfo.Fn->getContext(),
1700 VT.getSizeInBits());
1701 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1702 if (MaterialReg == 0) return 0;
1704 return FastEmit_rr(VT, VT, Opcode,
1706 MaterialReg, /*Kill=*/true);
1709 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
1710 return MRI.createVirtualRegister(RC);
1713 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II,
1714 unsigned Op, unsigned OpNum) {
1715 if (TargetRegisterInfo::isVirtualRegister(Op)) {
1716 const TargetRegisterClass *RegClass =
1717 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
1718 if (!MRI.constrainRegClass(Op, RegClass)) {
1719 // If it's not legal to COPY between the register classes, something
1720 // has gone very wrong before we got here.
1721 unsigned NewOp = createResultReg(RegClass);
1722 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1723 TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
1730 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
1731 const TargetRegisterClass* RC) {
1732 unsigned ResultReg = createResultReg(RC);
1733 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1735 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
1739 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
1740 const TargetRegisterClass *RC,
1741 unsigned Op0, bool Op0IsKill) {
1742 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1744 unsigned ResultReg = createResultReg(RC);
1745 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1747 if (II.getNumDefs() >= 1)
1748 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1749 .addReg(Op0, Op0IsKill * RegState::Kill);
1751 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1752 .addReg(Op0, Op0IsKill * RegState::Kill);
1753 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1754 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1760 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
1761 const TargetRegisterClass *RC,
1762 unsigned Op0, bool Op0IsKill,
1763 unsigned Op1, bool Op1IsKill) {
1764 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1766 unsigned ResultReg = createResultReg(RC);
1767 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1768 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1770 if (II.getNumDefs() >= 1)
1771 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1772 .addReg(Op0, Op0IsKill * RegState::Kill)
1773 .addReg(Op1, Op1IsKill * RegState::Kill);
1775 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1776 .addReg(Op0, Op0IsKill * RegState::Kill)
1777 .addReg(Op1, Op1IsKill * RegState::Kill);
1778 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1779 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1784 unsigned FastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
1785 const TargetRegisterClass *RC,
1786 unsigned Op0, bool Op0IsKill,
1787 unsigned Op1, bool Op1IsKill,
1788 unsigned Op2, bool Op2IsKill) {
1789 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1791 unsigned ResultReg = createResultReg(RC);
1792 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1793 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1794 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
1796 if (II.getNumDefs() >= 1)
1797 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1798 .addReg(Op0, Op0IsKill * RegState::Kill)
1799 .addReg(Op1, Op1IsKill * RegState::Kill)
1800 .addReg(Op2, Op2IsKill * RegState::Kill);
1802 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1803 .addReg(Op0, Op0IsKill * RegState::Kill)
1804 .addReg(Op1, Op1IsKill * RegState::Kill)
1805 .addReg(Op2, Op2IsKill * RegState::Kill);
1806 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1807 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1812 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
1813 const TargetRegisterClass *RC,
1814 unsigned Op0, bool Op0IsKill,
1816 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1818 unsigned ResultReg = createResultReg(RC);
1819 RC = TII.getRegClass(II, II.getNumDefs(), &TRI, *FuncInfo.MF);
1820 MRI.constrainRegClass(Op0, RC);
1822 if (II.getNumDefs() >= 1)
1823 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1824 .addReg(Op0, Op0IsKill * RegState::Kill)
1827 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1828 .addReg(Op0, Op0IsKill * RegState::Kill)
1830 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1831 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1836 unsigned FastISel::FastEmitInst_rii(unsigned MachineInstOpcode,
1837 const TargetRegisterClass *RC,
1838 unsigned Op0, bool Op0IsKill,
1839 uint64_t Imm1, uint64_t Imm2) {
1840 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1842 unsigned ResultReg = createResultReg(RC);
1843 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1845 if (II.getNumDefs() >= 1)
1846 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1847 .addReg(Op0, Op0IsKill * RegState::Kill)
1851 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1852 .addReg(Op0, Op0IsKill * RegState::Kill)
1855 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1856 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1861 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
1862 const TargetRegisterClass *RC,
1863 unsigned Op0, bool Op0IsKill,
1864 const ConstantFP *FPImm) {
1865 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1867 unsigned ResultReg = createResultReg(RC);
1868 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1870 if (II.getNumDefs() >= 1)
1871 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1872 .addReg(Op0, Op0IsKill * RegState::Kill)
1875 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1876 .addReg(Op0, Op0IsKill * RegState::Kill)
1878 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1879 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1884 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
1885 const TargetRegisterClass *RC,
1886 unsigned Op0, bool Op0IsKill,
1887 unsigned Op1, bool Op1IsKill,
1889 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1891 unsigned ResultReg = createResultReg(RC);
1892 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1893 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1895 if (II.getNumDefs() >= 1)
1896 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1897 .addReg(Op0, Op0IsKill * RegState::Kill)
1898 .addReg(Op1, Op1IsKill * RegState::Kill)
1901 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1902 .addReg(Op0, Op0IsKill * RegState::Kill)
1903 .addReg(Op1, Op1IsKill * RegState::Kill)
1905 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1906 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1911 unsigned FastISel::FastEmitInst_rrii(unsigned MachineInstOpcode,
1912 const TargetRegisterClass *RC,
1913 unsigned Op0, bool Op0IsKill,
1914 unsigned Op1, bool Op1IsKill,
1915 uint64_t Imm1, uint64_t Imm2) {
1916 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1918 unsigned ResultReg = createResultReg(RC);
1919 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1920 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1922 if (II.getNumDefs() >= 1)
1923 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1924 .addReg(Op0, Op0IsKill * RegState::Kill)
1925 .addReg(Op1, Op1IsKill * RegState::Kill)
1926 .addImm(Imm1).addImm(Imm2);
1928 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1929 .addReg(Op0, Op0IsKill * RegState::Kill)
1930 .addReg(Op1, Op1IsKill * RegState::Kill)
1931 .addImm(Imm1).addImm(Imm2);
1932 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1933 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1938 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
1939 const TargetRegisterClass *RC,
1941 unsigned ResultReg = createResultReg(RC);
1942 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1944 if (II.getNumDefs() >= 1)
1945 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg).addImm(Imm);
1947 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm);
1948 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1949 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1954 unsigned FastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
1955 const TargetRegisterClass *RC,
1956 uint64_t Imm1, uint64_t Imm2) {
1957 unsigned ResultReg = createResultReg(RC);
1958 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1960 if (II.getNumDefs() >= 1)
1961 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1962 .addImm(Imm1).addImm(Imm2);
1964 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm1).addImm(Imm2);
1965 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1966 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1971 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
1972 unsigned Op0, bool Op0IsKill,
1974 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1975 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1976 "Cannot yet extract from physregs");
1977 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
1978 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
1979 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
1980 DbgLoc, TII.get(TargetOpcode::COPY), ResultReg)
1981 .addReg(Op0, getKillRegState(Op0IsKill), Idx);
1985 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1986 /// with all but the least significant bit set to zero.
1987 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1988 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
1991 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
1992 /// Emit code to ensure constants are copied into registers when needed.
1993 /// Remember the virtual registers that need to be added to the Machine PHI
1994 /// nodes as input. We cannot just directly add them, because expansion
1995 /// might result in multiple MBB's for one BB. As such, the start of the
1996 /// BB might correspond to a different MBB than the end.
1997 bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
1998 const TerminatorInst *TI = LLVMBB->getTerminator();
2000 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
2001 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
2003 // Check successor nodes' PHI nodes that expect a constant to be available
2005 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
2006 const BasicBlock *SuccBB = TI->getSuccessor(succ);
2007 if (!isa<PHINode>(SuccBB->begin())) continue;
2008 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
2010 // If this terminator has multiple identical successors (common for
2011 // switches), only handle each succ once.
2012 if (!SuccsHandled.insert(SuccMBB)) continue;
2014 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
2016 // At this point we know that there is a 1-1 correspondence between LLVM PHI
2017 // nodes and Machine PHI nodes, but the incoming operands have not been
2019 for (BasicBlock::const_iterator I = SuccBB->begin();
2020 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
2022 // Ignore dead phi's.
2023 if (PN->use_empty()) continue;
2025 // Only handle legal types. Two interesting things to note here. First,
2026 // by bailing out early, we may leave behind some dead instructions,
2027 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
2028 // own moves. Second, this check is necessary because FastISel doesn't
2029 // use CreateRegs to create registers, so it always creates
2030 // exactly one register for each non-void instruction.
2031 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
2032 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
2033 // Handle integer promotions, though, because they're common and easy.
2034 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
2035 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT);
2037 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
2042 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
2044 // Set the DebugLoc for the copy. Prefer the location of the operand
2045 // if there is one; use the location of the PHI otherwise.
2046 DbgLoc = PN->getDebugLoc();
2047 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp))
2048 DbgLoc = Inst->getDebugLoc();
2050 unsigned Reg = getRegForValue(PHIOp);
2052 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
2055 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
2056 DbgLoc = DebugLoc();
2063 bool FastISel::tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst) {
2064 assert(LI->hasOneUse() &&
2065 "tryToFoldLoad expected a LoadInst with a single use");
2066 // We know that the load has a single use, but don't know what it is. If it
2067 // isn't one of the folded instructions, then we can't succeed here. Handle
2068 // this by scanning the single-use users of the load until we get to FoldInst.
2069 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
2071 const Instruction *TheUser = LI->user_back();
2072 while (TheUser != FoldInst && // Scan up until we find FoldInst.
2073 // Stay in the right block.
2074 TheUser->getParent() == FoldInst->getParent() &&
2075 --MaxUsers) { // Don't scan too far.
2076 // If there are multiple or no uses of this instruction, then bail out.
2077 if (!TheUser->hasOneUse())
2080 TheUser = TheUser->user_back();
2083 // If we didn't find the fold instruction, then we failed to collapse the
2085 if (TheUser != FoldInst)
2088 // Don't try to fold volatile loads. Target has to deal with alignment
2090 if (LI->isVolatile())
2093 // Figure out which vreg this is going into. If there is no assigned vreg yet
2094 // then there actually was no reference to it. Perhaps the load is referenced
2095 // by a dead instruction.
2096 unsigned LoadReg = getRegForValue(LI);
2100 // We can't fold if this vreg has no uses or more than one use. Multiple uses
2101 // may mean that the instruction got lowered to multiple MIs, or the use of
2102 // the loaded value ended up being multiple operands of the result.
2103 if (!MRI.hasOneUse(LoadReg))
2106 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg);
2107 MachineInstr *User = RI->getParent();
2109 // Set the insertion point properly. Folding the load can cause generation of
2110 // other random instructions (like sign extends) for addressing modes; make
2111 // sure they get inserted in a logical place before the new instruction.
2112 FuncInfo.InsertPt = User;
2113 FuncInfo.MBB = User->getParent();
2115 // Ask the target to try folding the load.
2116 return tryToFoldLoadIntoMI(User, RI.getOperandNo(), LI);
2119 bool FastISel::canFoldAddIntoGEP(const User *GEP, const Value *Add) {
2121 if (!isa<AddOperator>(Add))
2123 // Type size needs to match.
2124 if (DL.getTypeSizeInBits(GEP->getType()) !=
2125 DL.getTypeSizeInBits(Add->getType()))
2127 // Must be in the same basic block.
2128 if (isa<Instruction>(Add) &&
2129 FuncInfo.MBBMap[cast<Instruction>(Add)->getParent()] != FuncInfo.MBB)
2131 // Must have a constant operand.
2132 return isa<ConstantInt>(cast<AddOperator>(Add)->getOperand(1));
2136 FastISel::createMachineMemOperandFor(const Instruction *I) const {
2143 if (const auto *LI = dyn_cast<LoadInst>(I)) {
2144 Alignment = LI->getAlignment();
2145 IsVolatile = LI->isVolatile();
2146 Flags = MachineMemOperand::MOLoad;
2147 Ptr = LI->getPointerOperand();
2148 ValTy = LI->getType();
2149 } else if (const auto *SI = dyn_cast<StoreInst>(I)) {
2150 Alignment = SI->getAlignment();
2151 IsVolatile = SI->isVolatile();
2152 Flags = MachineMemOperand::MOStore;
2153 Ptr = SI->getPointerOperand();
2154 ValTy = SI->getValueOperand()->getType();
2159 bool IsNonTemporal = I->getMetadata("nontemporal") != nullptr;
2160 bool IsInvariant = I->getMetadata("invariant.load") != nullptr;
2161 const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range);
2164 I->getAAMetadata(AAInfo);
2166 if (Alignment == 0) // Ensure that codegen never sees alignment 0.
2167 Alignment = DL.getABITypeAlignment(ValTy);
2170 TM.getSubtargetImpl()->getDataLayout()->getTypeStoreSize(ValTy);
2173 Flags |= MachineMemOperand::MOVolatile;
2175 Flags |= MachineMemOperand::MONonTemporal;
2177 Flags |= MachineMemOperand::MOInvariant;
2179 return FuncInfo.MF->getMachineMemOperand(MachinePointerInfo(Ptr), Flags, Size,
2180 Alignment, AAInfo, Ranges);