1 //===-- FastISel.cpp - Implementation of the FastISel class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/Operator.h"
47 #include "llvm/CodeGen/Analysis.h"
48 #include "llvm/CodeGen/FastISel.h"
49 #include "llvm/CodeGen/FunctionLoweringInfo.h"
50 #include "llvm/CodeGen/MachineInstrBuilder.h"
51 #include "llvm/CodeGen/MachineModuleInfo.h"
52 #include "llvm/CodeGen/MachineRegisterInfo.h"
53 #include "llvm/Analysis/DebugInfo.h"
54 #include "llvm/Analysis/Loads.h"
55 #include "llvm/Target/TargetData.h"
56 #include "llvm/Target/TargetInstrInfo.h"
57 #include "llvm/Target/TargetLowering.h"
58 #include "llvm/Target/TargetMachine.h"
59 #include "llvm/Support/ErrorHandling.h"
60 #include "llvm/Support/Debug.h"
63 /// startNewBlock - Set the current block to which generated machine
64 /// instructions will be appended, and clear the local CSE map.
66 void FastISel::startNewBlock() {
67 LocalValueMap.clear();
71 // Advance the emit start point past any EH_LABEL instructions.
72 MachineBasicBlock::iterator
73 I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end();
74 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) {
78 LastLocalValue = EmitStartPt;
81 void FastISel::flushLocalValueMap() {
82 LocalValueMap.clear();
83 LastLocalValue = EmitStartPt;
87 bool FastISel::hasTrivialKill(const Value *V) const {
88 // Don't consider constants or arguments to have trivial kills.
89 const Instruction *I = dyn_cast<Instruction>(V);
93 // No-op casts are trivially coalesced by fast-isel.
94 if (const CastInst *Cast = dyn_cast<CastInst>(I))
95 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) &&
96 !hasTrivialKill(Cast->getOperand(0)))
99 // Only instructions with a single use in the same basic block are considered
100 // to have trivial kills.
101 return I->hasOneUse() &&
102 !(I->getOpcode() == Instruction::BitCast ||
103 I->getOpcode() == Instruction::PtrToInt ||
104 I->getOpcode() == Instruction::IntToPtr) &&
105 cast<Instruction>(*I->use_begin())->getParent() == I->getParent();
108 unsigned FastISel::getRegForValue(const Value *V) {
109 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
110 // Don't handle non-simple values in FastISel.
111 if (!RealVT.isSimple())
114 // Ignore illegal types. We must do this before looking up the value
115 // in ValueMap because Arguments are given virtual registers regardless
116 // of whether FastISel can handle them.
117 MVT VT = RealVT.getSimpleVT();
118 if (!TLI.isTypeLegal(VT)) {
119 // Handle integer promotions, though, because they're common and easy.
120 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
121 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
126 // Look up the value to see if we already have a register for it. We
127 // cache values defined by Instructions across blocks, and other values
128 // only locally. This is because Instructions already have the SSA
129 // def-dominates-use requirement enforced.
130 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
131 if (I != FuncInfo.ValueMap.end())
134 unsigned Reg = LocalValueMap[V];
138 // In bottom-up mode, just create the virtual register which will be used
139 // to hold the value. It will be materialized later.
140 if (isa<Instruction>(V) &&
141 (!isa<AllocaInst>(V) ||
142 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
143 return FuncInfo.InitializeRegForValue(V);
145 SavePoint SaveInsertPt = enterLocalValueArea();
147 // Materialize the value in a register. Emit any instructions in the
149 Reg = materializeRegForValue(V, VT);
151 leaveLocalValueArea(SaveInsertPt);
156 /// materializeRegForValue - Helper for getRegForValue. This function is
157 /// called when the value isn't already available in a register and must
158 /// be materialized with new instructions.
159 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
162 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
163 if (CI->getValue().getActiveBits() <= 64)
164 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
165 } else if (isa<AllocaInst>(V)) {
166 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
167 } else if (isa<ConstantPointerNull>(V)) {
168 // Translate this as an integer zero so that it can be
169 // local-CSE'd with actual integer zeros.
171 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
172 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
173 if (CF->isNullValue()) {
174 Reg = TargetMaterializeFloatZero(CF);
176 // Try to emit the constant directly.
177 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
181 // Try to emit the constant by using an integer constant with a cast.
182 const APFloat &Flt = CF->getValueAPF();
183 EVT IntVT = TLI.getPointerTy();
186 uint32_t IntBitWidth = IntVT.getSizeInBits();
188 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
189 APFloat::rmTowardZero, &isExact);
191 APInt IntVal(IntBitWidth, x);
193 unsigned IntegerReg =
194 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
196 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
197 IntegerReg, /*Kill=*/false);
200 } else if (const Operator *Op = dyn_cast<Operator>(V)) {
201 if (!SelectOperator(Op, Op->getOpcode()))
202 if (!isa<Instruction>(Op) ||
203 !TargetSelectInstruction(cast<Instruction>(Op)))
205 Reg = lookUpRegForValue(Op);
206 } else if (isa<UndefValue>(V)) {
207 Reg = createResultReg(TLI.getRegClassFor(VT));
208 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
209 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
212 // If target-independent code couldn't handle the value, give target-specific
214 if (!Reg && isa<Constant>(V))
215 Reg = TargetMaterializeConstant(cast<Constant>(V));
217 // Don't cache constant materializations in the general ValueMap.
218 // To do so would require tracking what uses they dominate.
220 LocalValueMap[V] = Reg;
221 LastLocalValue = MRI.getVRegDef(Reg);
226 unsigned FastISel::lookUpRegForValue(const Value *V) {
227 // Look up the value to see if we already have a register for it. We
228 // cache values defined by Instructions across blocks, and other values
229 // only locally. This is because Instructions already have the SSA
230 // def-dominates-use requirement enforced.
231 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
232 if (I != FuncInfo.ValueMap.end())
234 return LocalValueMap[V];
237 /// UpdateValueMap - Update the value map to include the new mapping for this
238 /// instruction, or insert an extra copy to get the result in a previous
239 /// determined register.
240 /// NOTE: This is only necessary because we might select a block that uses
241 /// a value before we select the block that defines the value. It might be
242 /// possible to fix this by selecting blocks in reverse postorder.
243 void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) {
244 if (!isa<Instruction>(I)) {
245 LocalValueMap[I] = Reg;
249 unsigned &AssignedReg = FuncInfo.ValueMap[I];
250 if (AssignedReg == 0)
251 // Use the new register.
253 else if (Reg != AssignedReg) {
254 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
255 for (unsigned i = 0; i < NumRegs; i++)
256 FuncInfo.RegFixups[AssignedReg+i] = Reg+i;
262 std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) {
263 unsigned IdxN = getRegForValue(Idx);
265 // Unhandled operand. Halt "fast" selection and bail.
266 return std::pair<unsigned, bool>(0, false);
268 bool IdxNIsKill = hasTrivialKill(Idx);
270 // If the index is smaller or larger than intptr_t, truncate or extend it.
271 MVT PtrVT = TLI.getPointerTy();
272 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
273 if (IdxVT.bitsLT(PtrVT)) {
274 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND,
278 else if (IdxVT.bitsGT(PtrVT)) {
279 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE,
283 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
286 void FastISel::recomputeInsertPt() {
287 if (getLastLocalValue()) {
288 FuncInfo.InsertPt = getLastLocalValue();
289 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
292 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
294 // Now skip past any EH_LABELs, which must remain at the beginning.
295 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
296 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
300 FastISel::SavePoint FastISel::enterLocalValueArea() {
301 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
305 SavePoint SP = { OldInsertPt, OldDL };
309 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
310 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
311 LastLocalValue = llvm::prior(FuncInfo.InsertPt);
313 // Restore the previous insert position.
314 FuncInfo.InsertPt = OldInsertPt.InsertPt;
318 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
319 /// which has an opcode which directly corresponds to the given ISD opcode.
321 bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) {
322 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
323 if (VT == MVT::Other || !VT.isSimple())
324 // Unhandled type. Halt "fast" selection and bail.
327 // We only handle legal types. For example, on x86-32 the instruction
328 // selector contains all of the 64-bit instructions from x86-64,
329 // under the assumption that i64 won't be used if the target doesn't
331 if (!TLI.isTypeLegal(VT)) {
332 // MVT::i1 is special. Allow AND, OR, or XOR because they
333 // don't require additional zeroing, which makes them easy.
335 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
336 ISDOpcode == ISD::XOR))
337 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
342 // Check if the first operand is a constant, and handle it as "ri". At -O0,
343 // we don't have anything that canonicalizes operand order.
344 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
345 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
346 unsigned Op1 = getRegForValue(I->getOperand(1));
347 if (Op1 == 0) return false;
349 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
351 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1,
352 Op1IsKill, CI->getZExtValue(),
354 if (ResultReg == 0) return false;
356 // We successfully emitted code for the given LLVM Instruction.
357 UpdateValueMap(I, ResultReg);
362 unsigned Op0 = getRegForValue(I->getOperand(0));
363 if (Op0 == 0) // Unhandled operand. Halt "fast" selection and bail.
366 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
368 // Check if the second operand is a constant and handle it appropriately.
369 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
370 uint64_t Imm = CI->getZExtValue();
372 // Transform "sdiv exact X, 8" -> "sra X, 3".
373 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
374 cast<BinaryOperator>(I)->isExact() &&
375 isPowerOf2_64(Imm)) {
377 ISDOpcode = ISD::SRA;
380 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
381 Op0IsKill, Imm, VT.getSimpleVT());
382 if (ResultReg == 0) return false;
384 // We successfully emitted code for the given LLVM Instruction.
385 UpdateValueMap(I, ResultReg);
389 // Check if the second operand is a constant float.
390 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
391 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
392 ISDOpcode, Op0, Op0IsKill, CF);
393 if (ResultReg != 0) {
394 // We successfully emitted code for the given LLVM Instruction.
395 UpdateValueMap(I, ResultReg);
400 unsigned Op1 = getRegForValue(I->getOperand(1));
402 // Unhandled operand. Halt "fast" selection and bail.
405 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
407 // Now we have both operands in registers. Emit the instruction.
408 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
413 // Target-specific code wasn't able to find a machine opcode for
414 // the given ISD opcode and type. Halt "fast" selection and bail.
417 // We successfully emitted code for the given LLVM Instruction.
418 UpdateValueMap(I, ResultReg);
422 bool FastISel::SelectGetElementPtr(const User *I) {
423 unsigned N = getRegForValue(I->getOperand(0));
425 // Unhandled operand. Halt "fast" selection and bail.
428 bool NIsKill = hasTrivialKill(I->getOperand(0));
430 Type *Ty = I->getOperand(0)->getType();
431 MVT VT = TLI.getPointerTy();
432 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1,
433 E = I->op_end(); OI != E; ++OI) {
434 const Value *Idx = *OI;
435 if (StructType *StTy = dyn_cast<StructType>(Ty)) {
436 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
439 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
440 // FIXME: This can be optimized by combining the add with a
442 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT);
444 // Unhandled operand. Halt "fast" selection and bail.
448 Ty = StTy->getElementType(Field);
450 Ty = cast<SequentialType>(Ty)->getElementType();
452 // If this is a constant subscript, handle it quickly.
453 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
454 if (CI->isZero()) continue;
456 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
457 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT);
459 // Unhandled operand. Halt "fast" selection and bail.
465 // N = N + Idx * ElementSize;
466 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
467 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
468 unsigned IdxN = Pair.first;
469 bool IdxNIsKill = Pair.second;
471 // Unhandled operand. Halt "fast" selection and bail.
474 if (ElementSize != 1) {
475 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
477 // Unhandled operand. Halt "fast" selection and bail.
481 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
483 // Unhandled operand. Halt "fast" selection and bail.
488 // We successfully emitted code for the given LLVM Instruction.
489 UpdateValueMap(I, N);
493 bool FastISel::SelectCall(const User *I) {
494 const CallInst *Call = cast<CallInst>(I);
496 // Handle simple inline asms.
497 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getArgOperand(0))) {
498 // Don't attempt to handle constraints.
499 if (!IA->getConstraintString().empty())
502 unsigned ExtraInfo = 0;
503 if (IA->hasSideEffects())
504 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
505 if (IA->isAlignStack())
506 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
508 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
509 TII.get(TargetOpcode::INLINEASM))
510 .addExternalSymbol(IA->getAsmString().c_str())
515 const Function *F = Call->getCalledFunction();
516 if (!F) return false;
518 // Handle selected intrinsic function calls.
519 switch (F->getIntrinsicID()) {
521 case Intrinsic::dbg_declare: {
522 const DbgDeclareInst *DI = cast<DbgDeclareInst>(Call);
523 if (!DIVariable(DI->getVariable()).Verify() ||
524 !FuncInfo.MF->getMMI().hasDebugInfo())
527 const Value *Address = DI->getAddress();
528 if (!Address || isa<UndefValue>(Address) || isa<AllocaInst>(Address))
533 if (const Argument *Arg = dyn_cast<Argument>(Address)) {
534 // Some arguments' frame index is recorded during argument lowering.
535 Offset = FuncInfo.getArgumentFrameIndex(Arg);
537 Reg = TRI.getFrameRegister(*FuncInfo.MF);
540 Reg = getRegForValue(Address);
543 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
544 TII.get(TargetOpcode::DBG_VALUE))
545 .addReg(Reg, RegState::Debug).addImm(Offset)
546 .addMetadata(DI->getVariable());
549 case Intrinsic::dbg_value: {
550 // This form of DBG_VALUE is target-independent.
551 const DbgValueInst *DI = cast<DbgValueInst>(Call);
552 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
553 const Value *V = DI->getValue();
555 // Currently the optimizer can produce this; insert an undef to
556 // help debugging. Probably the optimizer should not do this.
557 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
558 .addReg(0U).addImm(DI->getOffset())
559 .addMetadata(DI->getVariable());
560 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
561 if (CI->getBitWidth() > 64)
562 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
563 .addCImm(CI).addImm(DI->getOffset())
564 .addMetadata(DI->getVariable());
566 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
567 .addImm(CI->getZExtValue()).addImm(DI->getOffset())
568 .addMetadata(DI->getVariable());
569 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
570 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
571 .addFPImm(CF).addImm(DI->getOffset())
572 .addMetadata(DI->getVariable());
573 } else if (unsigned Reg = lookUpRegForValue(V)) {
574 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
575 .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
576 .addMetadata(DI->getVariable());
578 // We can't yet handle anything else here because it would require
579 // generating code, thus altering codegen because of debug info.
580 DEBUG(dbgs() << "Dropping debug info for " << DI);
584 case Intrinsic::eh_exception: {
585 EVT VT = TLI.getValueType(Call->getType());
586 if (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)!=TargetLowering::Expand)
589 assert(FuncInfo.MBB->isLandingPad() &&
590 "Call to eh.exception not in landing pad!");
591 unsigned Reg = TLI.getExceptionAddressRegister();
592 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
593 unsigned ResultReg = createResultReg(RC);
594 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
595 ResultReg).addReg(Reg);
596 UpdateValueMap(Call, ResultReg);
599 case Intrinsic::eh_selector: {
600 EVT VT = TLI.getValueType(Call->getType());
601 if (TLI.getOperationAction(ISD::EHSELECTION, VT) != TargetLowering::Expand)
603 if (FuncInfo.MBB->isLandingPad())
604 AddCatchInfo(*Call, &FuncInfo.MF->getMMI(), FuncInfo.MBB);
607 FuncInfo.CatchInfoLost.insert(Call);
609 // FIXME: Mark exception selector register as live in. Hack for PR1508.
610 unsigned Reg = TLI.getExceptionSelectorRegister();
611 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
614 unsigned Reg = TLI.getExceptionSelectorRegister();
615 EVT SrcVT = TLI.getPointerTy();
616 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
617 unsigned ResultReg = createResultReg(RC);
618 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
619 ResultReg).addReg(Reg);
621 bool ResultRegIsKill = hasTrivialKill(Call);
623 // Cast the register to the type of the selector.
624 if (SrcVT.bitsGT(MVT::i32))
625 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
626 ResultReg, ResultRegIsKill);
627 else if (SrcVT.bitsLT(MVT::i32))
628 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
629 ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill);
631 // Unhandled operand. Halt "fast" selection and bail.
634 UpdateValueMap(Call, ResultReg);
638 case Intrinsic::objectsize: {
639 ConstantInt *CI = cast<ConstantInt>(Call->getArgOperand(1));
640 unsigned long long Res = CI->isZero() ? -1ULL : 0;
641 Constant *ResCI = ConstantInt::get(Call->getType(), Res);
642 unsigned ResultReg = getRegForValue(ResCI);
645 UpdateValueMap(Call, ResultReg);
650 // Usually, it does not make sense to initialize a value,
651 // make an unrelated function call and use the value, because
652 // it tends to be spilled on the stack. So, we move the pointer
653 // to the last local value to the beginning of the block, so that
654 // all the values which have already been materialized,
655 // appear after the call. It also makes sense to skip intrinsics
656 // since they tend to be inlined.
657 if (!isa<IntrinsicInst>(F))
658 flushLocalValueMap();
660 // An arbitrary call. Bail.
664 bool FastISel::SelectCast(const User *I, unsigned Opcode) {
665 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
666 EVT DstVT = TLI.getValueType(I->getType());
668 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
669 DstVT == MVT::Other || !DstVT.isSimple())
670 // Unhandled type. Halt "fast" selection and bail.
673 // Check if the destination type is legal.
674 if (!TLI.isTypeLegal(DstVT))
677 // Check if the source operand is legal.
678 if (!TLI.isTypeLegal(SrcVT))
681 unsigned InputReg = getRegForValue(I->getOperand(0));
683 // Unhandled operand. Halt "fast" selection and bail.
686 bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
688 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
691 InputReg, InputRegIsKill);
695 UpdateValueMap(I, ResultReg);
699 bool FastISel::SelectBitCast(const User *I) {
700 // If the bitcast doesn't change the type, just use the operand value.
701 if (I->getType() == I->getOperand(0)->getType()) {
702 unsigned Reg = getRegForValue(I->getOperand(0));
705 UpdateValueMap(I, Reg);
709 // Bitcasts of other values become reg-reg copies or BITCAST operators.
710 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
711 EVT DstVT = TLI.getValueType(I->getType());
713 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
714 DstVT == MVT::Other || !DstVT.isSimple() ||
715 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
716 // Unhandled type. Halt "fast" selection and bail.
719 unsigned Op0 = getRegForValue(I->getOperand(0));
721 // Unhandled operand. Halt "fast" selection and bail.
724 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
726 // First, try to perform the bitcast by inserting a reg-reg copy.
727 unsigned ResultReg = 0;
728 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
729 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
730 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
731 // Don't attempt a cross-class copy. It will likely fail.
732 if (SrcClass == DstClass) {
733 ResultReg = createResultReg(DstClass);
734 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
735 ResultReg).addReg(Op0);
739 // If the reg-reg copy failed, select a BITCAST opcode.
741 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
742 ISD::BITCAST, Op0, Op0IsKill);
747 UpdateValueMap(I, ResultReg);
752 FastISel::SelectInstruction(const Instruction *I) {
753 // Just before the terminator instruction, insert instructions to
754 // feed PHI nodes in successor blocks.
755 if (isa<TerminatorInst>(I))
756 if (!HandlePHINodesInSuccessorBlocks(I->getParent()))
759 DL = I->getDebugLoc();
761 // First, try doing target-independent selection.
762 if (SelectOperator(I, I->getOpcode())) {
767 // Next, try calling the target to attempt to handle the instruction.
768 if (TargetSelectInstruction(I)) {
777 /// FastEmitBranch - Emit an unconditional branch to the given block,
778 /// unless it is the immediate (fall-through) successor, and update
781 FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) {
782 if (FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
783 // The unconditional fall-through case, which needs no instructions.
785 // The unconditional branch case.
786 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL,
787 SmallVector<MachineOperand, 0>(), DL);
789 FuncInfo.MBB->addSuccessor(MSucc);
792 /// SelectFNeg - Emit an FNeg operation.
795 FastISel::SelectFNeg(const User *I) {
796 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
797 if (OpReg == 0) return false;
799 bool OpRegIsKill = hasTrivialKill(I);
801 // If the target has ISD::FNEG, use it.
802 EVT VT = TLI.getValueType(I->getType());
803 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
804 ISD::FNEG, OpReg, OpRegIsKill);
805 if (ResultReg != 0) {
806 UpdateValueMap(I, ResultReg);
810 // Bitcast the value to integer, twiddle the sign bit with xor,
811 // and then bitcast it back to floating-point.
812 if (VT.getSizeInBits() > 64) return false;
813 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
814 if (!TLI.isTypeLegal(IntVT))
817 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
818 ISD::BITCAST, OpReg, OpRegIsKill);
822 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR,
823 IntReg, /*Kill=*/true,
824 UINT64_C(1) << (VT.getSizeInBits()-1),
825 IntVT.getSimpleVT());
826 if (IntResultReg == 0)
829 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
830 ISD::BITCAST, IntResultReg, /*Kill=*/true);
834 UpdateValueMap(I, ResultReg);
839 FastISel::SelectExtractValue(const User *U) {
840 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
844 // Make sure we only try to handle extracts with a legal result. But also
845 // allow i1 because it's easy.
846 EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true);
847 if (!RealVT.isSimple())
849 MVT VT = RealVT.getSimpleVT();
850 if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
853 const Value *Op0 = EVI->getOperand(0);
854 Type *AggTy = Op0->getType();
856 // Get the base result register.
858 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
859 if (I != FuncInfo.ValueMap.end())
860 ResultReg = I->second;
861 else if (isa<Instruction>(Op0))
862 ResultReg = FuncInfo.InitializeRegForValue(Op0);
864 return false; // fast-isel can't handle aggregate constants at the moment
866 // Get the actual result register, which is an offset from the base register.
867 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
869 SmallVector<EVT, 4> AggValueVTs;
870 ComputeValueVTs(TLI, AggTy, AggValueVTs);
872 for (unsigned i = 0; i < VTIndex; i++)
873 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
875 UpdateValueMap(EVI, ResultReg);
880 FastISel::SelectOperator(const User *I, unsigned Opcode) {
882 case Instruction::Add:
883 return SelectBinaryOp(I, ISD::ADD);
884 case Instruction::FAdd:
885 return SelectBinaryOp(I, ISD::FADD);
886 case Instruction::Sub:
887 return SelectBinaryOp(I, ISD::SUB);
888 case Instruction::FSub:
889 // FNeg is currently represented in LLVM IR as a special case of FSub.
890 if (BinaryOperator::isFNeg(I))
891 return SelectFNeg(I);
892 return SelectBinaryOp(I, ISD::FSUB);
893 case Instruction::Mul:
894 return SelectBinaryOp(I, ISD::MUL);
895 case Instruction::FMul:
896 return SelectBinaryOp(I, ISD::FMUL);
897 case Instruction::SDiv:
898 return SelectBinaryOp(I, ISD::SDIV);
899 case Instruction::UDiv:
900 return SelectBinaryOp(I, ISD::UDIV);
901 case Instruction::FDiv:
902 return SelectBinaryOp(I, ISD::FDIV);
903 case Instruction::SRem:
904 return SelectBinaryOp(I, ISD::SREM);
905 case Instruction::URem:
906 return SelectBinaryOp(I, ISD::UREM);
907 case Instruction::FRem:
908 return SelectBinaryOp(I, ISD::FREM);
909 case Instruction::Shl:
910 return SelectBinaryOp(I, ISD::SHL);
911 case Instruction::LShr:
912 return SelectBinaryOp(I, ISD::SRL);
913 case Instruction::AShr:
914 return SelectBinaryOp(I, ISD::SRA);
915 case Instruction::And:
916 return SelectBinaryOp(I, ISD::AND);
917 case Instruction::Or:
918 return SelectBinaryOp(I, ISD::OR);
919 case Instruction::Xor:
920 return SelectBinaryOp(I, ISD::XOR);
922 case Instruction::GetElementPtr:
923 return SelectGetElementPtr(I);
925 case Instruction::Br: {
926 const BranchInst *BI = cast<BranchInst>(I);
928 if (BI->isUnconditional()) {
929 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
930 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
931 FastEmitBranch(MSucc, BI->getDebugLoc());
935 // Conditional branches are not handed yet.
936 // Halt "fast" selection and bail.
940 case Instruction::Unreachable:
944 case Instruction::Alloca:
945 // FunctionLowering has the static-sized case covered.
946 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
949 // Dynamic-sized alloca is not handled yet.
952 case Instruction::Call:
953 return SelectCall(I);
955 case Instruction::BitCast:
956 return SelectBitCast(I);
958 case Instruction::FPToSI:
959 return SelectCast(I, ISD::FP_TO_SINT);
960 case Instruction::ZExt:
961 return SelectCast(I, ISD::ZERO_EXTEND);
962 case Instruction::SExt:
963 return SelectCast(I, ISD::SIGN_EXTEND);
964 case Instruction::Trunc:
965 return SelectCast(I, ISD::TRUNCATE);
966 case Instruction::SIToFP:
967 return SelectCast(I, ISD::SINT_TO_FP);
969 case Instruction::IntToPtr: // Deliberate fall-through.
970 case Instruction::PtrToInt: {
971 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
972 EVT DstVT = TLI.getValueType(I->getType());
973 if (DstVT.bitsGT(SrcVT))
974 return SelectCast(I, ISD::ZERO_EXTEND);
975 if (DstVT.bitsLT(SrcVT))
976 return SelectCast(I, ISD::TRUNCATE);
977 unsigned Reg = getRegForValue(I->getOperand(0));
978 if (Reg == 0) return false;
979 UpdateValueMap(I, Reg);
983 case Instruction::ExtractValue:
984 return SelectExtractValue(I);
986 case Instruction::PHI:
987 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
990 // Unhandled instruction. Halt "fast" selection and bail.
995 FastISel::FastISel(FunctionLoweringInfo &funcInfo)
996 : FuncInfo(funcInfo),
997 MRI(FuncInfo.MF->getRegInfo()),
998 MFI(*FuncInfo.MF->getFrameInfo()),
999 MCP(*FuncInfo.MF->getConstantPool()),
1000 TM(FuncInfo.MF->getTarget()),
1001 TD(*TM.getTargetData()),
1002 TII(*TM.getInstrInfo()),
1003 TLI(*TM.getTargetLowering()),
1004 TRI(*TM.getRegisterInfo()) {
1007 FastISel::~FastISel() {}
1009 unsigned FastISel::FastEmit_(MVT, MVT,
1014 unsigned FastISel::FastEmit_r(MVT, MVT,
1016 unsigned /*Op0*/, bool /*Op0IsKill*/) {
1020 unsigned FastISel::FastEmit_rr(MVT, MVT,
1022 unsigned /*Op0*/, bool /*Op0IsKill*/,
1023 unsigned /*Op1*/, bool /*Op1IsKill*/) {
1027 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1031 unsigned FastISel::FastEmit_f(MVT, MVT,
1032 unsigned, const ConstantFP * /*FPImm*/) {
1036 unsigned FastISel::FastEmit_ri(MVT, MVT,
1038 unsigned /*Op0*/, bool /*Op0IsKill*/,
1043 unsigned FastISel::FastEmit_rf(MVT, MVT,
1045 unsigned /*Op0*/, bool /*Op0IsKill*/,
1046 const ConstantFP * /*FPImm*/) {
1050 unsigned FastISel::FastEmit_rri(MVT, MVT,
1052 unsigned /*Op0*/, bool /*Op0IsKill*/,
1053 unsigned /*Op1*/, bool /*Op1IsKill*/,
1058 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
1059 /// to emit an instruction with an immediate operand using FastEmit_ri.
1060 /// If that fails, it materializes the immediate into a register and try
1061 /// FastEmit_rr instead.
1062 unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode,
1063 unsigned Op0, bool Op0IsKill,
1064 uint64_t Imm, MVT ImmType) {
1065 // If this is a multiply by a power of two, emit this as a shift left.
1066 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1069 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1070 // div x, 8 -> srl x, 3
1075 // Horrible hack (to be removed), check to make sure shift amounts are
1077 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1078 Imm >= VT.getSizeInBits())
1081 // First check if immediate type is legal. If not, we can't use the ri form.
1082 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1085 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1086 if (MaterialReg == 0) {
1087 // This is a bit ugly/slow, but failing here means falling out of
1088 // fast-isel, which would be very slow.
1089 IntegerType *ITy = IntegerType::get(FuncInfo.Fn->getContext(),
1090 VT.getSizeInBits());
1091 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1093 return FastEmit_rr(VT, VT, Opcode,
1095 MaterialReg, /*Kill=*/true);
1098 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
1099 return MRI.createVirtualRegister(RC);
1102 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
1103 const TargetRegisterClass* RC) {
1104 unsigned ResultReg = createResultReg(RC);
1105 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1107 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg);
1111 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
1112 const TargetRegisterClass *RC,
1113 unsigned Op0, bool Op0IsKill) {
1114 unsigned ResultReg = createResultReg(RC);
1115 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1117 if (II.getNumDefs() >= 1)
1118 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1119 .addReg(Op0, Op0IsKill * RegState::Kill);
1121 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1122 .addReg(Op0, Op0IsKill * RegState::Kill);
1123 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1124 ResultReg).addReg(II.ImplicitDefs[0]);
1130 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
1131 const TargetRegisterClass *RC,
1132 unsigned Op0, bool Op0IsKill,
1133 unsigned Op1, bool Op1IsKill) {
1134 unsigned ResultReg = createResultReg(RC);
1135 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1137 if (II.getNumDefs() >= 1)
1138 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1139 .addReg(Op0, Op0IsKill * RegState::Kill)
1140 .addReg(Op1, Op1IsKill * RegState::Kill);
1142 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1143 .addReg(Op0, Op0IsKill * RegState::Kill)
1144 .addReg(Op1, Op1IsKill * RegState::Kill);
1145 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1146 ResultReg).addReg(II.ImplicitDefs[0]);
1151 unsigned FastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
1152 const TargetRegisterClass *RC,
1153 unsigned Op0, bool Op0IsKill,
1154 unsigned Op1, bool Op1IsKill,
1155 unsigned Op2, bool Op2IsKill) {
1156 unsigned ResultReg = createResultReg(RC);
1157 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1159 if (II.getNumDefs() >= 1)
1160 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1161 .addReg(Op0, Op0IsKill * RegState::Kill)
1162 .addReg(Op1, Op1IsKill * RegState::Kill)
1163 .addReg(Op2, Op2IsKill * RegState::Kill);
1165 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1166 .addReg(Op0, Op0IsKill * RegState::Kill)
1167 .addReg(Op1, Op1IsKill * RegState::Kill)
1168 .addReg(Op2, Op2IsKill * RegState::Kill);
1169 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1170 ResultReg).addReg(II.ImplicitDefs[0]);
1175 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
1176 const TargetRegisterClass *RC,
1177 unsigned Op0, bool Op0IsKill,
1179 unsigned ResultReg = createResultReg(RC);
1180 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1182 if (II.getNumDefs() >= 1)
1183 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1184 .addReg(Op0, Op0IsKill * RegState::Kill)
1187 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1188 .addReg(Op0, Op0IsKill * RegState::Kill)
1190 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1191 ResultReg).addReg(II.ImplicitDefs[0]);
1196 unsigned FastISel::FastEmitInst_rii(unsigned MachineInstOpcode,
1197 const TargetRegisterClass *RC,
1198 unsigned Op0, bool Op0IsKill,
1199 uint64_t Imm1, uint64_t Imm2) {
1200 unsigned ResultReg = createResultReg(RC);
1201 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1203 if (II.getNumDefs() >= 1)
1204 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1205 .addReg(Op0, Op0IsKill * RegState::Kill)
1209 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1210 .addReg(Op0, Op0IsKill * RegState::Kill)
1213 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1214 ResultReg).addReg(II.ImplicitDefs[0]);
1219 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
1220 const TargetRegisterClass *RC,
1221 unsigned Op0, bool Op0IsKill,
1222 const ConstantFP *FPImm) {
1223 unsigned ResultReg = createResultReg(RC);
1224 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1226 if (II.getNumDefs() >= 1)
1227 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1228 .addReg(Op0, Op0IsKill * RegState::Kill)
1231 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1232 .addReg(Op0, Op0IsKill * RegState::Kill)
1234 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1235 ResultReg).addReg(II.ImplicitDefs[0]);
1240 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
1241 const TargetRegisterClass *RC,
1242 unsigned Op0, bool Op0IsKill,
1243 unsigned Op1, bool Op1IsKill,
1245 unsigned ResultReg = createResultReg(RC);
1246 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1248 if (II.getNumDefs() >= 1)
1249 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1250 .addReg(Op0, Op0IsKill * RegState::Kill)
1251 .addReg(Op1, Op1IsKill * RegState::Kill)
1254 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1255 .addReg(Op0, Op0IsKill * RegState::Kill)
1256 .addReg(Op1, Op1IsKill * RegState::Kill)
1258 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1259 ResultReg).addReg(II.ImplicitDefs[0]);
1264 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
1265 const TargetRegisterClass *RC,
1267 unsigned ResultReg = createResultReg(RC);
1268 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1270 if (II.getNumDefs() >= 1)
1271 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm);
1273 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm);
1274 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1275 ResultReg).addReg(II.ImplicitDefs[0]);
1280 unsigned FastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
1281 const TargetRegisterClass *RC,
1282 uint64_t Imm1, uint64_t Imm2) {
1283 unsigned ResultReg = createResultReg(RC);
1284 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1286 if (II.getNumDefs() >= 1)
1287 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1288 .addImm(Imm1).addImm(Imm2);
1290 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm1).addImm(Imm2);
1291 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1292 ResultReg).addReg(II.ImplicitDefs[0]);
1297 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
1298 unsigned Op0, bool Op0IsKill,
1300 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1301 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1302 "Cannot yet extract from physregs");
1303 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
1304 DL, TII.get(TargetOpcode::COPY), ResultReg)
1305 .addReg(Op0, getKillRegState(Op0IsKill), Idx);
1309 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1310 /// with all but the least significant bit set to zero.
1311 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1312 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
1315 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
1316 /// Emit code to ensure constants are copied into registers when needed.
1317 /// Remember the virtual registers that need to be added to the Machine PHI
1318 /// nodes as input. We cannot just directly add them, because expansion
1319 /// might result in multiple MBB's for one BB. As such, the start of the
1320 /// BB might correspond to a different MBB than the end.
1321 bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
1322 const TerminatorInst *TI = LLVMBB->getTerminator();
1324 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
1325 unsigned OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
1327 // Check successor nodes' PHI nodes that expect a constant to be available
1329 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
1330 const BasicBlock *SuccBB = TI->getSuccessor(succ);
1331 if (!isa<PHINode>(SuccBB->begin())) continue;
1332 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
1334 // If this terminator has multiple identical successors (common for
1335 // switches), only handle each succ once.
1336 if (!SuccsHandled.insert(SuccMBB)) continue;
1338 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
1340 // At this point we know that there is a 1-1 correspondence between LLVM PHI
1341 // nodes and Machine PHI nodes, but the incoming operands have not been
1343 for (BasicBlock::const_iterator I = SuccBB->begin();
1344 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
1346 // Ignore dead phi's.
1347 if (PN->use_empty()) continue;
1349 // Only handle legal types. Two interesting things to note here. First,
1350 // by bailing out early, we may leave behind some dead instructions,
1351 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
1352 // own moves. Second, this check is necessary because FastISel doesn't
1353 // use CreateRegs to create registers, so it always creates
1354 // exactly one register for each non-void instruction.
1355 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
1356 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
1359 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT);
1361 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
1366 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
1368 // Set the DebugLoc for the copy. Prefer the location of the operand
1369 // if there is one; use the location of the PHI otherwise.
1370 DL = PN->getDebugLoc();
1371 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp))
1372 DL = Inst->getDebugLoc();
1374 unsigned Reg = getRegForValue(PHIOp);
1376 FuncInfo.PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
1379 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));