1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Instructions.h"
15 #include "llvm/CodeGen/FastISel.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetMachine.h"
24 unsigned FastISel::getRegForValue(Value *V) {
25 // Look up the value to see if we already have a register for it. We
26 // cache values defined by Instructions across blocks, and other values
27 // only locally. This is because Instructions already have the SSA
28 // def-dominatess-use requirement enforced.
29 if (ValueMap.count(V))
31 unsigned Reg = LocalValueMap[V];
35 MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
36 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
37 if (CI->getValue().getActiveBits() > 64)
39 // Don't cache constant materializations. To do so would require
40 // tracking what uses they dominate.
41 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
42 } else if (isa<ConstantPointerNull>(V)) {
43 Reg = FastEmit_i(VT, VT, ISD::Constant, 0);
44 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
45 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
48 const APFloat &Flt = CF->getValueAPF();
49 MVT IntVT = TLI.getPointerTy();
52 uint32_t IntBitWidth = IntVT.getSizeInBits();
53 if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
54 APFloat::rmTowardZero) != APFloat::opOK)
56 APInt IntVal(IntBitWidth, 2, x);
58 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
59 ISD::Constant, IntVal.getZExtValue());
62 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
66 } else if (isa<UndefValue>(V)) {
67 Reg = createResultReg(TLI.getRegClassFor(VT));
68 BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
73 LocalValueMap[V] = Reg;
77 /// UpdateValueMap - Update the value map to include the new mapping for this
78 /// instruction, or insert an extra copy to get the result in a previous
79 /// determined register.
80 /// NOTE: This is only necessary because we might select a block that uses
81 /// a value before we select the block that defines the value. It might be
82 /// possible to fix this by selecting blocks in reverse postorder.
83 void FastISel::UpdateValueMap(Instruction* I, unsigned Reg) {
84 if (!ValueMap.count(I))
87 TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
88 Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
91 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
92 /// which has an opcode which directly corresponds to the given ISD opcode.
94 bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode) {
95 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
96 if (VT == MVT::Other || !VT.isSimple())
97 // Unhandled type. Halt "fast" selection and bail.
99 // We only handle legal types. For example, on x86-32 the instruction
100 // selector contains all of the 64-bit instructions from x86-64,
101 // under the assumption that i64 won't be used if the target doesn't
103 if (!TLI.isTypeLegal(VT))
106 unsigned Op0 = getRegForValue(I->getOperand(0));
108 // Unhandled operand. Halt "fast" selection and bail.
111 // Check if the second operand is a constant and handle it appropriately.
112 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
113 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
114 ISDOpcode, Op0, CI->getZExtValue());
115 if (ResultReg != 0) {
116 // We successfully emitted code for the given LLVM Instruction.
117 UpdateValueMap(I, ResultReg);
122 // Check if the second operand is a constant float.
123 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
124 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
126 if (ResultReg != 0) {
127 // We successfully emitted code for the given LLVM Instruction.
128 UpdateValueMap(I, ResultReg);
133 unsigned Op1 = getRegForValue(I->getOperand(1));
135 // Unhandled operand. Halt "fast" selection and bail.
138 // Now we have both operands in registers. Emit the instruction.
139 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
140 ISDOpcode, Op0, Op1);
142 // Target-specific code wasn't able to find a machine opcode for
143 // the given ISD opcode and type. Halt "fast" selection and bail.
146 // We successfully emitted code for the given LLVM Instruction.
147 UpdateValueMap(I, ResultReg);
151 bool FastISel::SelectGetElementPtr(Instruction *I) {
152 unsigned N = getRegForValue(I->getOperand(0));
154 // Unhandled operand. Halt "fast" selection and bail.
157 const Type *Ty = I->getOperand(0)->getType();
158 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
159 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
162 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
163 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
166 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
167 // FIXME: This can be optimized by combining the add with a
169 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
171 // Unhandled operand. Halt "fast" selection and bail.
174 Ty = StTy->getElementType(Field);
176 Ty = cast<SequentialType>(Ty)->getElementType();
178 // If this is a constant subscript, handle it quickly.
179 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
180 if (CI->getZExtValue() == 0) continue;
182 TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
183 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
185 // Unhandled operand. Halt "fast" selection and bail.
190 // N = N + Idx * ElementSize;
191 uint64_t ElementSize = TD.getABITypeSize(Ty);
192 unsigned IdxN = getRegForValue(Idx);
194 // Unhandled operand. Halt "fast" selection and bail.
197 // If the index is smaller or larger than intptr_t, truncate or extend
199 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
200 if (IdxVT.bitsLT(VT))
201 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
202 else if (IdxVT.bitsGT(VT))
203 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
205 // Unhandled operand. Halt "fast" selection and bail.
208 if (ElementSize != 1) {
209 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
211 // Unhandled operand. Halt "fast" selection and bail.
214 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
216 // Unhandled operand. Halt "fast" selection and bail.
221 // We successfully emitted code for the given LLVM Instruction.
222 UpdateValueMap(I, N);
226 bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode) {
227 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
228 MVT DstVT = TLI.getValueType(I->getType());
230 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
231 DstVT == MVT::Other || !DstVT.isSimple() ||
232 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
233 // Unhandled type. Halt "fast" selection and bail.
236 unsigned InputReg = getRegForValue(I->getOperand(0));
238 // Unhandled operand. Halt "fast" selection and bail.
241 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
248 UpdateValueMap(I, ResultReg);
252 bool FastISel::SelectBitCast(Instruction *I) {
253 // If the bitcast doesn't change the type, just use the operand value.
254 if (I->getType() == I->getOperand(0)->getType()) {
255 unsigned Reg = getRegForValue(I->getOperand(0));
258 UpdateValueMap(I, Reg);
262 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
263 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
264 MVT DstVT = TLI.getValueType(I->getType());
266 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
267 DstVT == MVT::Other || !DstVT.isSimple() ||
268 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
269 // Unhandled type. Halt "fast" selection and bail.
272 unsigned Op0 = getRegForValue(I->getOperand(0));
274 // Unhandled operand. Halt "fast" selection and bail.
277 // First, try to perform the bitcast by inserting a reg-reg copy.
278 unsigned ResultReg = 0;
279 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
280 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
281 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
282 ResultReg = createResultReg(DstClass);
284 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
285 Op0, DstClass, SrcClass);
290 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
292 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
293 ISD::BIT_CONVERT, Op0);
298 UpdateValueMap(I, ResultReg);
303 FastISel::SelectInstruction(Instruction *I) {
304 switch (I->getOpcode()) {
305 case Instruction::Add: {
306 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
307 return SelectBinaryOp(I, Opc);
309 case Instruction::Sub: {
310 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
311 return SelectBinaryOp(I, Opc);
313 case Instruction::Mul: {
314 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
315 return SelectBinaryOp(I, Opc);
317 case Instruction::SDiv:
318 return SelectBinaryOp(I, ISD::SDIV);
319 case Instruction::UDiv:
320 return SelectBinaryOp(I, ISD::UDIV);
321 case Instruction::FDiv:
322 return SelectBinaryOp(I, ISD::FDIV);
323 case Instruction::SRem:
324 return SelectBinaryOp(I, ISD::SREM);
325 case Instruction::URem:
326 return SelectBinaryOp(I, ISD::UREM);
327 case Instruction::FRem:
328 return SelectBinaryOp(I, ISD::FREM);
329 case Instruction::Shl:
330 return SelectBinaryOp(I, ISD::SHL);
331 case Instruction::LShr:
332 return SelectBinaryOp(I, ISD::SRL);
333 case Instruction::AShr:
334 return SelectBinaryOp(I, ISD::SRA);
335 case Instruction::And:
336 return SelectBinaryOp(I, ISD::AND);
337 case Instruction::Or:
338 return SelectBinaryOp(I, ISD::OR);
339 case Instruction::Xor:
340 return SelectBinaryOp(I, ISD::XOR);
342 case Instruction::GetElementPtr:
343 return SelectGetElementPtr(I);
345 case Instruction::Br: {
346 BranchInst *BI = cast<BranchInst>(I);
348 if (BI->isUnconditional()) {
349 MachineFunction::iterator NextMBB =
350 next(MachineFunction::iterator(MBB));
351 BasicBlock *LLVMSucc = BI->getSuccessor(0);
352 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
354 if (NextMBB != MF.end() && MSucc == NextMBB) {
355 // The unconditional fall-through case, which needs no instructions.
357 // The unconditional branch case.
358 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
360 MBB->addSuccessor(MSucc);
364 // Conditional branches are not handed yet.
365 // Halt "fast" selection and bail.
369 case Instruction::PHI:
370 // PHI nodes are already emitted.
373 case Instruction::BitCast:
374 return SelectBitCast(I);
376 case Instruction::FPToSI:
377 return SelectCast(I, ISD::FP_TO_SINT);
378 case Instruction::ZExt:
379 return SelectCast(I, ISD::ZERO_EXTEND);
380 case Instruction::SExt:
381 return SelectCast(I, ISD::SIGN_EXTEND);
382 case Instruction::Trunc:
383 return SelectCast(I, ISD::TRUNCATE);
384 case Instruction::SIToFP:
385 return SelectCast(I, ISD::SINT_TO_FP);
387 case Instruction::IntToPtr: // Deliberate fall-through.
388 case Instruction::PtrToInt: {
389 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
390 MVT DstVT = TLI.getValueType(I->getType());
391 if (DstVT.bitsGT(SrcVT))
392 return SelectCast(I, ISD::ZERO_EXTEND);
393 if (DstVT.bitsLT(SrcVT))
394 return SelectCast(I, ISD::TRUNCATE);
395 unsigned Reg = getRegForValue(I->getOperand(0));
396 if (Reg == 0) return false;
397 UpdateValueMap(I, Reg);
402 // Unhandled instruction. Halt "fast" selection and bail.
407 FastISel::FastISel(MachineFunction &mf,
408 DenseMap<const Value *, unsigned> &vm,
409 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm)
414 MRI(MF.getRegInfo()),
416 TD(*TM.getTargetData()),
417 TII(*TM.getInstrInfo()),
418 TLI(*TM.getTargetLowering()) {
421 FastISel::~FastISel() {}
423 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
428 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
429 ISD::NodeType, unsigned /*Op0*/) {
433 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
434 ISD::NodeType, unsigned /*Op0*/,
439 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
440 ISD::NodeType, uint64_t /*Imm*/) {
444 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
445 ISD::NodeType, ConstantFP * /*FPImm*/) {
449 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
450 ISD::NodeType, unsigned /*Op0*/,
455 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
456 ISD::NodeType, unsigned /*Op0*/,
457 ConstantFP * /*FPImm*/) {
461 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
463 unsigned /*Op0*/, unsigned /*Op1*/,
468 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
469 /// to emit an instruction with an immediate operand using FastEmit_ri.
470 /// If that fails, it materializes the immediate into a register and try
471 /// FastEmit_rr instead.
472 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
473 unsigned Op0, uint64_t Imm,
474 MVT::SimpleValueType ImmType) {
475 // First check if immediate type is legal. If not, we can't use the ri form.
476 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
479 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
480 if (MaterialReg == 0)
482 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
485 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
486 /// to emit an instruction with a floating-point immediate operand using
487 /// FastEmit_rf. If that fails, it materializes the immediate into a register
488 /// and try FastEmit_rr instead.
489 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
490 unsigned Op0, ConstantFP *FPImm,
491 MVT::SimpleValueType ImmType) {
492 // First check if immediate type is legal. If not, we can't use the rf form.
493 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
497 // Materialize the constant in a register.
498 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
499 if (MaterialReg == 0) {
500 // If the target doesn't have a way to directly enter a floating-point
501 // value into a register, use an alternate approach.
502 // TODO: The current approach only supports floating-point constants
503 // that can be constructed by conversion from integer values. This should
504 // be replaced by code that creates a load from a constant-pool entry,
505 // which will require some target-specific work.
506 const APFloat &Flt = FPImm->getValueAPF();
507 MVT IntVT = TLI.getPointerTy();
510 uint32_t IntBitWidth = IntVT.getSizeInBits();
511 if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
512 APFloat::rmTowardZero) != APFloat::opOK)
514 APInt IntVal(IntBitWidth, 2, x);
516 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
517 ISD::Constant, IntVal.getZExtValue());
520 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
521 ISD::SINT_TO_FP, IntegerReg);
522 if (MaterialReg == 0)
525 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
528 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
529 return MRI.createVirtualRegister(RC);
532 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
533 const TargetRegisterClass* RC) {
534 unsigned ResultReg = createResultReg(RC);
535 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
537 BuildMI(MBB, II, ResultReg);
541 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
542 const TargetRegisterClass *RC,
544 unsigned ResultReg = createResultReg(RC);
545 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
547 BuildMI(MBB, II, ResultReg).addReg(Op0);
551 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
552 const TargetRegisterClass *RC,
553 unsigned Op0, unsigned Op1) {
554 unsigned ResultReg = createResultReg(RC);
555 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
557 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
561 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
562 const TargetRegisterClass *RC,
563 unsigned Op0, uint64_t Imm) {
564 unsigned ResultReg = createResultReg(RC);
565 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
567 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
571 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
572 const TargetRegisterClass *RC,
573 unsigned Op0, ConstantFP *FPImm) {
574 unsigned ResultReg = createResultReg(RC);
575 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
577 BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
581 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
582 const TargetRegisterClass *RC,
583 unsigned Op0, unsigned Op1, uint64_t Imm) {
584 unsigned ResultReg = createResultReg(RC);
585 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
587 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
591 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
592 const TargetRegisterClass *RC,
594 unsigned ResultReg = createResultReg(RC);
595 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
597 BuildMI(MBB, II, ResultReg).addImm(Imm);
601 unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
602 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
603 const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
605 unsigned ResultReg = createResultReg(SRC);
606 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
608 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);