1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/DwarfWriter.h"
51 #include "llvm/Analysis/DebugInfo.h"
52 #include "llvm/Target/TargetData.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "SelectionDAGBuild.h"
59 unsigned FastISel::getRegForValue(Value *V) {
60 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
61 // Don't handle non-simple values in FastISel.
62 if (!RealVT.isSimple())
65 // Ignore illegal types. We must do this before looking up the value
66 // in ValueMap because Arguments are given virtual registers regardless
67 // of whether FastISel can handle them.
68 MVT::SimpleValueType VT = RealVT.getSimpleVT();
69 if (!TLI.isTypeLegal(VT)) {
70 // Promote MVT::i1 to a legal type though, because it's common and easy.
72 VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
77 // Look up the value to see if we already have a register for it. We
78 // cache values defined by Instructions across blocks, and other values
79 // only locally. This is because Instructions already have the SSA
80 // def-dominatess-use requirement enforced.
81 if (ValueMap.count(V))
83 unsigned Reg = LocalValueMap[V];
87 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
88 if (CI->getValue().getActiveBits() <= 64)
89 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
90 } else if (isa<AllocaInst>(V)) {
91 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
92 } else if (isa<ConstantPointerNull>(V)) {
93 // Translate this as an integer zero so that it can be
94 // local-CSE'd with actual integer zeros.
95 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType()));
96 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
97 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
100 const APFloat &Flt = CF->getValueAPF();
101 MVT IntVT = TLI.getPointerTy();
104 uint32_t IntBitWidth = IntVT.getSizeInBits();
106 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
107 APFloat::rmTowardZero, &isExact);
109 APInt IntVal(IntBitWidth, 2, x);
111 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal));
113 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
116 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
117 if (!SelectOperator(CE, CE->getOpcode())) return 0;
118 Reg = LocalValueMap[CE];
119 } else if (isa<UndefValue>(V)) {
120 Reg = createResultReg(TLI.getRegClassFor(VT));
121 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
124 // If target-independent code couldn't handle the value, give target-specific
126 if (!Reg && isa<Constant>(V))
127 Reg = TargetMaterializeConstant(cast<Constant>(V));
129 // Don't cache constant materializations in the general ValueMap.
130 // To do so would require tracking what uses they dominate.
132 LocalValueMap[V] = Reg;
136 unsigned FastISel::lookUpRegForValue(Value *V) {
137 // Look up the value to see if we already have a register for it. We
138 // cache values defined by Instructions across blocks, and other values
139 // only locally. This is because Instructions already have the SSA
140 // def-dominatess-use requirement enforced.
141 if (ValueMap.count(V))
143 return LocalValueMap[V];
146 /// UpdateValueMap - Update the value map to include the new mapping for this
147 /// instruction, or insert an extra copy to get the result in a previous
148 /// determined register.
149 /// NOTE: This is only necessary because we might select a block that uses
150 /// a value before we select the block that defines the value. It might be
151 /// possible to fix this by selecting blocks in reverse postorder.
152 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
153 if (!isa<Instruction>(I)) {
154 LocalValueMap[I] = Reg;
158 unsigned &AssignedReg = ValueMap[I];
159 if (AssignedReg == 0)
161 else if (Reg != AssignedReg) {
162 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
163 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
164 Reg, RegClass, RegClass);
169 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
170 unsigned IdxN = getRegForValue(Idx);
172 // Unhandled operand. Halt "fast" selection and bail.
175 // If the index is smaller or larger than intptr_t, truncate or extend it.
176 MVT PtrVT = TLI.getPointerTy();
177 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
178 if (IdxVT.bitsLT(PtrVT))
179 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
180 ISD::SIGN_EXTEND, IdxN);
181 else if (IdxVT.bitsGT(PtrVT))
182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
183 ISD::TRUNCATE, IdxN);
187 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
188 /// which has an opcode which directly corresponds to the given ISD opcode.
190 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
191 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
192 if (VT == MVT::Other || !VT.isSimple())
193 // Unhandled type. Halt "fast" selection and bail.
196 // We only handle legal types. For example, on x86-32 the instruction
197 // selector contains all of the 64-bit instructions from x86-64,
198 // under the assumption that i64 won't be used if the target doesn't
200 if (!TLI.isTypeLegal(VT)) {
201 // MVT::i1 is special. Allow AND, OR, or XOR because they
202 // don't require additional zeroing, which makes them easy.
204 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
205 ISDOpcode == ISD::XOR))
206 VT = TLI.getTypeToTransformTo(VT);
211 unsigned Op0 = getRegForValue(I->getOperand(0));
213 // Unhandled operand. Halt "fast" selection and bail.
216 // Check if the second operand is a constant and handle it appropriately.
217 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
218 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
219 ISDOpcode, Op0, CI->getZExtValue());
220 if (ResultReg != 0) {
221 // We successfully emitted code for the given LLVM Instruction.
222 UpdateValueMap(I, ResultReg);
227 // Check if the second operand is a constant float.
228 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
229 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
231 if (ResultReg != 0) {
232 // We successfully emitted code for the given LLVM Instruction.
233 UpdateValueMap(I, ResultReg);
238 unsigned Op1 = getRegForValue(I->getOperand(1));
240 // Unhandled operand. Halt "fast" selection and bail.
243 // Now we have both operands in registers. Emit the instruction.
244 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
245 ISDOpcode, Op0, Op1);
247 // Target-specific code wasn't able to find a machine opcode for
248 // the given ISD opcode and type. Halt "fast" selection and bail.
251 // We successfully emitted code for the given LLVM Instruction.
252 UpdateValueMap(I, ResultReg);
256 bool FastISel::SelectGetElementPtr(User *I) {
257 unsigned N = getRegForValue(I->getOperand(0));
259 // Unhandled operand. Halt "fast" selection and bail.
262 const Type *Ty = I->getOperand(0)->getType();
263 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
264 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
267 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
268 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
271 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
272 // FIXME: This can be optimized by combining the add with a
274 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
276 // Unhandled operand. Halt "fast" selection and bail.
279 Ty = StTy->getElementType(Field);
281 Ty = cast<SequentialType>(Ty)->getElementType();
283 // If this is a constant subscript, handle it quickly.
284 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
285 if (CI->getZExtValue() == 0) continue;
287 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
288 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
290 // Unhandled operand. Halt "fast" selection and bail.
295 // N = N + Idx * ElementSize;
296 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
297 unsigned IdxN = getRegForGEPIndex(Idx);
299 // Unhandled operand. Halt "fast" selection and bail.
302 if (ElementSize != 1) {
303 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
305 // Unhandled operand. Halt "fast" selection and bail.
308 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
310 // Unhandled operand. Halt "fast" selection and bail.
315 // We successfully emitted code for the given LLVM Instruction.
316 UpdateValueMap(I, N);
320 bool FastISel::SelectCall(User *I) {
321 Function *F = cast<CallInst>(I)->getCalledFunction();
322 if (!F) return false;
324 unsigned IID = F->getIntrinsicID();
327 case Intrinsic::dbg_stoppoint: {
328 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
329 if (DIDescriptor::ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) {
330 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
331 unsigned Line = SPI->getLine();
332 unsigned Col = SPI->getColumn();
333 unsigned Idx = MF.getOrCreateDebugLocID(CU.getGV(), Line, Col);
334 setCurDebugLoc(DebugLoc::get(Idx));
338 case Intrinsic::dbg_region_start: {
339 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
340 if (DIDescriptor::ValidDebugInfo(RSI->getContext(), CodeGenOpt::None) &&
341 DW && DW->ShouldEmitDwarfDebug()) {
343 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
344 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
345 BuildMI(MBB, DL, II).addImm(ID);
349 case Intrinsic::dbg_region_end: {
350 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
351 if (DIDescriptor::ValidDebugInfo(REI->getContext(), CodeGenOpt::None) &&
352 DW && DW->ShouldEmitDwarfDebug()) {
354 DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
355 if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
356 // This is end of an inlined function.
357 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
358 ID = DW->RecordInlinedFnEnd(Subprogram);
360 // Returned ID is 0 if this is unbalanced "end of inlined
361 // scope". This could happen if optimizer eats dbg intrinsics
362 // or "beginning of inlined scope" is not recoginized due to
363 // missing location info. In such cases, ignore this region.end.
364 BuildMI(MBB, DL, II).addImm(ID);
366 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
367 ID = DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext()));
368 BuildMI(MBB, DL, II).addImm(ID);
373 case Intrinsic::dbg_func_start: {
374 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
375 Value *SP = FSI->getSubprogram();
376 if (!DIDescriptor::ValidDebugInfo(SP, CodeGenOpt::None))
379 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
380 // (most?) gdb expects.
381 DebugLoc PrevLoc = DL;
382 DISubprogram Subprogram(cast<GlobalVariable>(SP));
383 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
385 if (!Subprogram.describes(MF.getFunction())) {
386 // This is a beginning of an inlined function.
388 // If llvm.dbg.func.start is seen in a new block before any
389 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
390 // FIXME : Why DebugLoc is reset at the beginning of each block ?
391 if (PrevLoc.isUnknown())
393 // Record the source line.
394 unsigned Line = Subprogram.getLineNumber();
395 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(
396 CompileUnit.getGV(), Line, 0)));
398 if (DW && DW->ShouldEmitDwarfDebug()) {
399 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
400 unsigned LabelID = DW->RecordInlinedFnStart(Subprogram,
401 DICompileUnit(PrevLocTpl.CompileUnit),
404 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
405 BuildMI(MBB, DL, II).addImm(LabelID);
408 // Record the source line.
409 unsigned Line = Subprogram.getLineNumber();
410 MF.setDefaultDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(
411 CompileUnit.getGV(), Line, 0)));
412 if (DW && DW->ShouldEmitDwarfDebug()) {
413 // llvm.dbg.func_start also defines beginning of function scope.
414 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
420 case Intrinsic::dbg_declare: {
421 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
422 Value *Variable = DI->getVariable();
423 if (DIDescriptor::ValidDebugInfo(Variable, CodeGenOpt::None) &&
424 DW && DW->ShouldEmitDwarfDebug()) {
425 // Determine the address of the declared object.
426 Value *Address = DI->getAddress();
427 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
428 Address = BCI->getOperand(0);
429 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
430 // Don't handle byval struct arguments or VLAs, for example.
432 DenseMap<const AllocaInst*, int>::iterator SI =
433 StaticAllocaMap.find(AI);
434 if (SI == StaticAllocaMap.end()) break; // VLAs.
437 // Determine the debug globalvariable.
438 GlobalValue *GV = cast<GlobalVariable>(Variable);
440 // Build the DECLARE instruction.
441 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
442 MachineInstr *DeclareMI
443 = BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV);
444 DIVariable DV(cast<GlobalVariable>(GV));
446 // This is a local variable
447 DW->RecordVariableScope(DV, DeclareMI);
452 case Intrinsic::eh_exception: {
453 MVT VT = TLI.getValueType(I->getType());
454 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
456 case TargetLowering::Expand: {
457 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
458 unsigned Reg = TLI.getExceptionAddressRegister();
459 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
460 unsigned ResultReg = createResultReg(RC);
461 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
463 assert(InsertedCopy && "Can't copy address registers!");
464 InsertedCopy = InsertedCopy;
465 UpdateValueMap(I, ResultReg);
471 case Intrinsic::eh_selector_i32:
472 case Intrinsic::eh_selector_i64: {
473 MVT VT = TLI.getValueType(I->getType());
474 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
476 case TargetLowering::Expand: {
477 MVT VT = (IID == Intrinsic::eh_selector_i32 ?
478 MVT::i32 : MVT::i64);
481 if (MBB->isLandingPad())
482 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
485 CatchInfoLost.insert(cast<CallInst>(I));
487 // FIXME: Mark exception selector register as live in. Hack for PR1508.
488 unsigned Reg = TLI.getExceptionSelectorRegister();
489 if (Reg) MBB->addLiveIn(Reg);
492 unsigned Reg = TLI.getExceptionSelectorRegister();
493 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
494 unsigned ResultReg = createResultReg(RC);
495 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
497 assert(InsertedCopy && "Can't copy address registers!");
498 InsertedCopy = InsertedCopy;
499 UpdateValueMap(I, ResultReg);
502 getRegForValue(Constant::getNullValue(I->getType()));
503 UpdateValueMap(I, ResultReg);
514 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
515 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
516 MVT DstVT = TLI.getValueType(I->getType());
518 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
519 DstVT == MVT::Other || !DstVT.isSimple())
520 // Unhandled type. Halt "fast" selection and bail.
523 // Check if the destination type is legal. Or as a special case,
524 // it may be i1 if we're doing a truncate because that's
525 // easy and somewhat common.
526 if (!TLI.isTypeLegal(DstVT))
527 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
528 // Unhandled type. Halt "fast" selection and bail.
531 // Check if the source operand is legal. Or as a special case,
532 // it may be i1 if we're doing zero-extension because that's
533 // easy and somewhat common.
534 if (!TLI.isTypeLegal(SrcVT))
535 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
536 // Unhandled type. Halt "fast" selection and bail.
539 unsigned InputReg = getRegForValue(I->getOperand(0));
541 // Unhandled operand. Halt "fast" selection and bail.
544 // If the operand is i1, arrange for the high bits in the register to be zero.
545 if (SrcVT == MVT::i1) {
546 SrcVT = TLI.getTypeToTransformTo(SrcVT);
547 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
551 // If the result is i1, truncate to the target's type for i1 first.
552 if (DstVT == MVT::i1)
553 DstVT = TLI.getTypeToTransformTo(DstVT);
555 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
562 UpdateValueMap(I, ResultReg);
566 bool FastISel::SelectBitCast(User *I) {
567 // If the bitcast doesn't change the type, just use the operand value.
568 if (I->getType() == I->getOperand(0)->getType()) {
569 unsigned Reg = getRegForValue(I->getOperand(0));
572 UpdateValueMap(I, Reg);
576 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
577 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
578 MVT DstVT = TLI.getValueType(I->getType());
580 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
581 DstVT == MVT::Other || !DstVT.isSimple() ||
582 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
583 // Unhandled type. Halt "fast" selection and bail.
586 unsigned Op0 = getRegForValue(I->getOperand(0));
588 // Unhandled operand. Halt "fast" selection and bail.
591 // First, try to perform the bitcast by inserting a reg-reg copy.
592 unsigned ResultReg = 0;
593 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
594 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
595 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
596 ResultReg = createResultReg(DstClass);
598 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
599 Op0, DstClass, SrcClass);
604 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
606 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
607 ISD::BIT_CONVERT, Op0);
612 UpdateValueMap(I, ResultReg);
617 FastISel::SelectInstruction(Instruction *I) {
618 return SelectOperator(I, I->getOpcode());
621 /// FastEmitBranch - Emit an unconditional branch to the given block,
622 /// unless it is the immediate (fall-through) successor, and update
625 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
626 MachineFunction::iterator NextMBB =
627 next(MachineFunction::iterator(MBB));
629 if (MBB->isLayoutSuccessor(MSucc)) {
630 // The unconditional fall-through case, which needs no instructions.
632 // The unconditional branch case.
633 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
635 MBB->addSuccessor(MSucc);
639 FastISel::SelectOperator(User *I, unsigned Opcode) {
641 case Instruction::Add:
642 return SelectBinaryOp(I, ISD::ADD);
643 case Instruction::FAdd:
644 return SelectBinaryOp(I, ISD::FADD);
645 case Instruction::Sub:
646 return SelectBinaryOp(I, ISD::SUB);
647 case Instruction::FSub:
648 return SelectBinaryOp(I, ISD::FSUB);
649 case Instruction::Mul:
650 return SelectBinaryOp(I, ISD::MUL);
651 case Instruction::FMul:
652 return SelectBinaryOp(I, ISD::FMUL);
653 case Instruction::SDiv:
654 return SelectBinaryOp(I, ISD::SDIV);
655 case Instruction::UDiv:
656 return SelectBinaryOp(I, ISD::UDIV);
657 case Instruction::FDiv:
658 return SelectBinaryOp(I, ISD::FDIV);
659 case Instruction::SRem:
660 return SelectBinaryOp(I, ISD::SREM);
661 case Instruction::URem:
662 return SelectBinaryOp(I, ISD::UREM);
663 case Instruction::FRem:
664 return SelectBinaryOp(I, ISD::FREM);
665 case Instruction::Shl:
666 return SelectBinaryOp(I, ISD::SHL);
667 case Instruction::LShr:
668 return SelectBinaryOp(I, ISD::SRL);
669 case Instruction::AShr:
670 return SelectBinaryOp(I, ISD::SRA);
671 case Instruction::And:
672 return SelectBinaryOp(I, ISD::AND);
673 case Instruction::Or:
674 return SelectBinaryOp(I, ISD::OR);
675 case Instruction::Xor:
676 return SelectBinaryOp(I, ISD::XOR);
678 case Instruction::GetElementPtr:
679 return SelectGetElementPtr(I);
681 case Instruction::Br: {
682 BranchInst *BI = cast<BranchInst>(I);
684 if (BI->isUnconditional()) {
685 BasicBlock *LLVMSucc = BI->getSuccessor(0);
686 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
687 FastEmitBranch(MSucc);
691 // Conditional branches are not handed yet.
692 // Halt "fast" selection and bail.
696 case Instruction::Unreachable:
700 case Instruction::PHI:
701 // PHI nodes are already emitted.
704 case Instruction::Alloca:
705 // FunctionLowering has the static-sized case covered.
706 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
709 // Dynamic-sized alloca is not handled yet.
712 case Instruction::Call:
713 return SelectCall(I);
715 case Instruction::BitCast:
716 return SelectBitCast(I);
718 case Instruction::FPToSI:
719 return SelectCast(I, ISD::FP_TO_SINT);
720 case Instruction::ZExt:
721 return SelectCast(I, ISD::ZERO_EXTEND);
722 case Instruction::SExt:
723 return SelectCast(I, ISD::SIGN_EXTEND);
724 case Instruction::Trunc:
725 return SelectCast(I, ISD::TRUNCATE);
726 case Instruction::SIToFP:
727 return SelectCast(I, ISD::SINT_TO_FP);
729 case Instruction::IntToPtr: // Deliberate fall-through.
730 case Instruction::PtrToInt: {
731 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
732 MVT DstVT = TLI.getValueType(I->getType());
733 if (DstVT.bitsGT(SrcVT))
734 return SelectCast(I, ISD::ZERO_EXTEND);
735 if (DstVT.bitsLT(SrcVT))
736 return SelectCast(I, ISD::TRUNCATE);
737 unsigned Reg = getRegForValue(I->getOperand(0));
738 if (Reg == 0) return false;
739 UpdateValueMap(I, Reg);
744 // Unhandled instruction. Halt "fast" selection and bail.
749 FastISel::FastISel(MachineFunction &mf,
750 MachineModuleInfo *mmi,
752 DenseMap<const Value *, unsigned> &vm,
753 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
754 DenseMap<const AllocaInst *, int> &am
756 , SmallSet<Instruction*, 8> &cil
769 MRI(MF.getRegInfo()),
770 MFI(*MF.getFrameInfo()),
771 MCP(*MF.getConstantPool()),
773 TD(*TM.getTargetData()),
774 TII(*TM.getInstrInfo()),
775 TLI(*TM.getTargetLowering()) {
778 FastISel::~FastISel() {}
780 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
785 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
786 ISD::NodeType, unsigned /*Op0*/) {
790 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
791 ISD::NodeType, unsigned /*Op0*/,
796 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
797 ISD::NodeType, uint64_t /*Imm*/) {
801 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
802 ISD::NodeType, ConstantFP * /*FPImm*/) {
806 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
807 ISD::NodeType, unsigned /*Op0*/,
812 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
813 ISD::NodeType, unsigned /*Op0*/,
814 ConstantFP * /*FPImm*/) {
818 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
820 unsigned /*Op0*/, unsigned /*Op1*/,
825 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
826 /// to emit an instruction with an immediate operand using FastEmit_ri.
827 /// If that fails, it materializes the immediate into a register and try
828 /// FastEmit_rr instead.
829 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
830 unsigned Op0, uint64_t Imm,
831 MVT::SimpleValueType ImmType) {
832 // First check if immediate type is legal. If not, we can't use the ri form.
833 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
836 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
837 if (MaterialReg == 0)
839 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
842 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
843 /// to emit an instruction with a floating-point immediate operand using
844 /// FastEmit_rf. If that fails, it materializes the immediate into a register
845 /// and try FastEmit_rr instead.
846 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
847 unsigned Op0, ConstantFP *FPImm,
848 MVT::SimpleValueType ImmType) {
849 // First check if immediate type is legal. If not, we can't use the rf form.
850 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
854 // Materialize the constant in a register.
855 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
856 if (MaterialReg == 0) {
857 // If the target doesn't have a way to directly enter a floating-point
858 // value into a register, use an alternate approach.
859 // TODO: The current approach only supports floating-point constants
860 // that can be constructed by conversion from integer values. This should
861 // be replaced by code that creates a load from a constant-pool entry,
862 // which will require some target-specific work.
863 const APFloat &Flt = FPImm->getValueAPF();
864 MVT IntVT = TLI.getPointerTy();
867 uint32_t IntBitWidth = IntVT.getSizeInBits();
869 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
870 APFloat::rmTowardZero, &isExact);
873 APInt IntVal(IntBitWidth, 2, x);
875 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
876 ISD::Constant, IntVal.getZExtValue());
879 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
880 ISD::SINT_TO_FP, IntegerReg);
881 if (MaterialReg == 0)
884 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
887 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
888 return MRI.createVirtualRegister(RC);
891 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
892 const TargetRegisterClass* RC) {
893 unsigned ResultReg = createResultReg(RC);
894 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
896 BuildMI(MBB, DL, II, ResultReg);
900 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
901 const TargetRegisterClass *RC,
903 unsigned ResultReg = createResultReg(RC);
904 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
906 if (II.getNumDefs() >= 1)
907 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
909 BuildMI(MBB, DL, II).addReg(Op0);
910 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
911 II.ImplicitDefs[0], RC, RC);
919 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
920 const TargetRegisterClass *RC,
921 unsigned Op0, unsigned Op1) {
922 unsigned ResultReg = createResultReg(RC);
923 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
925 if (II.getNumDefs() >= 1)
926 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
928 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
929 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
930 II.ImplicitDefs[0], RC, RC);
937 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
938 const TargetRegisterClass *RC,
939 unsigned Op0, uint64_t Imm) {
940 unsigned ResultReg = createResultReg(RC);
941 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
943 if (II.getNumDefs() >= 1)
944 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
946 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
947 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
948 II.ImplicitDefs[0], RC, RC);
955 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
956 const TargetRegisterClass *RC,
957 unsigned Op0, ConstantFP *FPImm) {
958 unsigned ResultReg = createResultReg(RC);
959 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
961 if (II.getNumDefs() >= 1)
962 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
964 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
965 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
966 II.ImplicitDefs[0], RC, RC);
973 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
974 const TargetRegisterClass *RC,
975 unsigned Op0, unsigned Op1, uint64_t Imm) {
976 unsigned ResultReg = createResultReg(RC);
977 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
979 if (II.getNumDefs() >= 1)
980 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
982 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
983 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
984 II.ImplicitDefs[0], RC, RC);
991 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
992 const TargetRegisterClass *RC,
994 unsigned ResultReg = createResultReg(RC);
995 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
997 if (II.getNumDefs() >= 1)
998 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
1000 BuildMI(MBB, DL, II).addImm(Imm);
1001 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1002 II.ImplicitDefs[0], RC, RC);
1009 unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
1010 unsigned Op0, uint32_t Idx) {
1011 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
1013 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1014 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
1016 if (II.getNumDefs() >= 1)
1017 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
1019 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
1020 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1021 II.ImplicitDefs[0], RC, RC);
1028 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1029 /// with all but the least significant bit set to zero.
1030 unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
1031 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);