1 //===-- FastISel.cpp - Implementation of the FastISel class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/Analysis/DebugInfo.h"
51 #include "llvm/Target/TargetData.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetLowering.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include "llvm/Support/ErrorHandling.h"
56 #include "FunctionLoweringInfo.h"
59 bool FastISel::hasTrivialKill(const Value *V) const {
60 // Don't consider constants or arguments to have trivial kills.
61 const Instruction *I = dyn_cast<Instruction>(V);
65 // No-op casts are trivially coalesced by fast-isel.
66 if (const CastInst *Cast = dyn_cast<CastInst>(I))
67 if (Cast->isNoopCast(TD.getIntPtrType(Cast->getContext())) &&
68 !hasTrivialKill(Cast->getOperand(0)))
71 // Only instructions with a single use in the same basic block are considered
72 // to have trivial kills.
73 return I->hasOneUse() &&
74 !(I->getOpcode() == Instruction::BitCast ||
75 I->getOpcode() == Instruction::PtrToInt ||
76 I->getOpcode() == Instruction::IntToPtr) &&
77 cast<Instruction>(I->use_begin())->getParent() == I->getParent();
80 unsigned FastISel::getRegForValue(const Value *V) {
81 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
82 // Don't handle non-simple values in FastISel.
83 if (!RealVT.isSimple())
86 // Ignore illegal types. We must do this before looking up the value
87 // in ValueMap because Arguments are given virtual registers regardless
88 // of whether FastISel can handle them.
89 MVT VT = RealVT.getSimpleVT();
90 if (!TLI.isTypeLegal(VT)) {
91 // Promote MVT::i1 to a legal type though, because it's common and easy.
93 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
98 // Look up the value to see if we already have a register for it. We
99 // cache values defined by Instructions across blocks, and other values
100 // only locally. This is because Instructions already have the SSA
101 // def-dominates-use requirement enforced.
102 DenseMap<const Value *, unsigned>::iterator I = ValueMap.find(V);
103 if (I != ValueMap.end())
105 unsigned Reg = LocalValueMap[V];
109 // In bottom-up mode, just create the virtual register which will be used
110 // to hold the value. It will be materialized later.
112 Reg = createResultReg(TLI.getRegClassFor(VT));
113 if (isa<Instruction>(V))
116 LocalValueMap[V] = Reg;
120 return materializeRegForValue(V, VT);
123 /// materializeRegForValue - Helper for getRegForVale. This function is
124 /// called when the value isn't already available in a register and must
125 /// be materialized with new instructions.
126 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
129 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
130 if (CI->getValue().getActiveBits() <= 64)
131 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
132 } else if (isa<AllocaInst>(V)) {
133 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
134 } else if (isa<ConstantPointerNull>(V)) {
135 // Translate this as an integer zero so that it can be
136 // local-CSE'd with actual integer zeros.
138 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
139 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
140 // Try to emit the constant directly.
141 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
144 // Try to emit the constant by using an integer constant with a cast.
145 const APFloat &Flt = CF->getValueAPF();
146 EVT IntVT = TLI.getPointerTy();
149 uint32_t IntBitWidth = IntVT.getSizeInBits();
151 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
152 APFloat::rmTowardZero, &isExact);
154 APInt IntVal(IntBitWidth, 2, x);
156 unsigned IntegerReg =
157 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
159 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP,
160 IntegerReg, /*Kill=*/false);
163 } else if (const Operator *Op = dyn_cast<Operator>(V)) {
164 if (!SelectOperator(Op, Op->getOpcode())) return 0;
165 Reg = LocalValueMap[Op];
166 } else if (isa<UndefValue>(V)) {
167 Reg = createResultReg(TLI.getRegClassFor(VT));
168 BuildMI(MBB, DL, TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
171 // If target-independent code couldn't handle the value, give target-specific
173 if (!Reg && isa<Constant>(V))
174 Reg = TargetMaterializeConstant(cast<Constant>(V));
176 // Don't cache constant materializations in the general ValueMap.
177 // To do so would require tracking what uses they dominate.
179 LocalValueMap[V] = Reg;
183 unsigned FastISel::lookUpRegForValue(const Value *V) {
184 // Look up the value to see if we already have a register for it. We
185 // cache values defined by Instructions across blocks, and other values
186 // only locally. This is because Instructions already have the SSA
187 // def-dominates-use requirement enforced.
188 if (ValueMap.count(V))
190 return LocalValueMap[V];
193 /// UpdateValueMap - Update the value map to include the new mapping for this
194 /// instruction, or insert an extra copy to get the result in a previous
195 /// determined register.
196 /// NOTE: This is only necessary because we might select a block that uses
197 /// a value before we select the block that defines the value. It might be
198 /// possible to fix this by selecting blocks in reverse postorder.
199 unsigned FastISel::UpdateValueMap(const Value *I, unsigned Reg) {
200 if (!isa<Instruction>(I)) {
201 LocalValueMap[I] = Reg;
205 unsigned &AssignedReg = ValueMap[I];
206 if (AssignedReg == 0)
208 else if (Reg != AssignedReg) {
209 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
210 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
211 Reg, RegClass, RegClass, DL);
216 std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) {
217 unsigned IdxN = getRegForValue(Idx);
219 // Unhandled operand. Halt "fast" selection and bail.
220 return std::pair<unsigned, bool>(0, false);
222 bool IdxNIsKill = hasTrivialKill(Idx);
224 // If the index is smaller or larger than intptr_t, truncate or extend it.
225 MVT PtrVT = TLI.getPointerTy();
226 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
227 if (IdxVT.bitsLT(PtrVT)) {
228 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND,
232 else if (IdxVT.bitsGT(PtrVT)) {
233 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE,
237 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
240 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
241 /// which has an opcode which directly corresponds to the given ISD opcode.
243 bool FastISel::SelectBinaryOp(const User *I, unsigned ISDOpcode) {
244 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
245 if (VT == MVT::Other || !VT.isSimple())
246 // Unhandled type. Halt "fast" selection and bail.
249 // We only handle legal types. For example, on x86-32 the instruction
250 // selector contains all of the 64-bit instructions from x86-64,
251 // under the assumption that i64 won't be used if the target doesn't
253 if (!TLI.isTypeLegal(VT)) {
254 // MVT::i1 is special. Allow AND, OR, or XOR because they
255 // don't require additional zeroing, which makes them easy.
257 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
258 ISDOpcode == ISD::XOR))
259 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
264 unsigned Op0 = getRegForValue(I->getOperand(0));
266 // Unhandled operand. Halt "fast" selection and bail.
269 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
271 // Check if the second operand is a constant and handle it appropriately.
272 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
273 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
274 ISDOpcode, Op0, Op0IsKill,
276 if (ResultReg != 0) {
277 // We successfully emitted code for the given LLVM Instruction.
278 UpdateValueMap(I, ResultReg);
283 // Check if the second operand is a constant float.
284 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
285 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
286 ISDOpcode, Op0, Op0IsKill, CF);
287 if (ResultReg != 0) {
288 // We successfully emitted code for the given LLVM Instruction.
289 UpdateValueMap(I, ResultReg);
294 unsigned Op1 = getRegForValue(I->getOperand(1));
296 // Unhandled operand. Halt "fast" selection and bail.
299 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
301 // Now we have both operands in registers. Emit the instruction.
302 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
307 // Target-specific code wasn't able to find a machine opcode for
308 // the given ISD opcode and type. Halt "fast" selection and bail.
311 // We successfully emitted code for the given LLVM Instruction.
312 UpdateValueMap(I, ResultReg);
316 bool FastISel::SelectGetElementPtr(const User *I) {
317 unsigned N = getRegForValue(I->getOperand(0));
319 // Unhandled operand. Halt "fast" selection and bail.
322 bool NIsKill = hasTrivialKill(I->getOperand(0));
324 const Type *Ty = I->getOperand(0)->getType();
325 MVT VT = TLI.getPointerTy();
326 for (GetElementPtrInst::const_op_iterator OI = I->op_begin()+1,
327 E = I->op_end(); OI != E; ++OI) {
328 const Value *Idx = *OI;
329 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
330 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
333 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
334 // FIXME: This can be optimized by combining the add with a
336 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT);
338 // Unhandled operand. Halt "fast" selection and bail.
342 Ty = StTy->getElementType(Field);
344 Ty = cast<SequentialType>(Ty)->getElementType();
346 // If this is a constant subscript, handle it quickly.
347 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
348 if (CI->getZExtValue() == 0) continue;
350 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
351 N = FastEmit_ri_(VT, ISD::ADD, N, NIsKill, Offs, VT);
353 // Unhandled operand. Halt "fast" selection and bail.
359 // N = N + Idx * ElementSize;
360 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
361 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
362 unsigned IdxN = Pair.first;
363 bool IdxNIsKill = Pair.second;
365 // Unhandled operand. Halt "fast" selection and bail.
368 if (ElementSize != 1) {
369 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
371 // Unhandled operand. Halt "fast" selection and bail.
375 N = FastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
377 // Unhandled operand. Halt "fast" selection and bail.
382 // We successfully emitted code for the given LLVM Instruction.
383 UpdateValueMap(I, N);
387 bool FastISel::SelectCall(const User *I) {
388 const Function *F = cast<CallInst>(I)->getCalledFunction();
389 if (!F) return false;
391 // Handle selected intrinsic function calls.
392 unsigned IID = F->getIntrinsicID();
395 case Intrinsic::dbg_declare: {
396 const DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
397 if (!DIVariable(DI->getVariable()).Verify() ||
398 !MF.getMMI().hasDebugInfo())
401 const Value *Address = DI->getAddress();
404 if (isa<UndefValue>(Address))
406 const AllocaInst *AI = dyn_cast<AllocaInst>(Address);
407 // Don't handle byval struct arguments or VLAs, for example.
408 // Note that if we have a byval struct argument, fast ISel is turned off;
409 // those are handled in SelectionDAGBuilder.
411 DenseMap<const AllocaInst*, int>::iterator SI =
412 StaticAllocaMap.find(AI);
413 if (SI == StaticAllocaMap.end()) break; // VLAs.
415 if (!DI->getDebugLoc().isUnknown())
416 MF.getMMI().setVariableDbgInfo(DI->getVariable(), FI, DI->getDebugLoc());
418 // Building the map above is target independent. Generating DBG_VALUE
419 // inline is target dependent; do this now.
420 (void)TargetSelectInstruction(cast<Instruction>(I));
423 case Intrinsic::dbg_value: {
424 // This form of DBG_VALUE is target-independent.
425 const DbgValueInst *DI = cast<DbgValueInst>(I);
426 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
427 const Value *V = DI->getValue();
429 // Currently the optimizer can produce this; insert an undef to
430 // help debugging. Probably the optimizer should not do this.
431 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
432 addMetadata(DI->getVariable());
433 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
434 BuildMI(MBB, DL, II).addImm(CI->getZExtValue()).addImm(DI->getOffset()).
435 addMetadata(DI->getVariable());
436 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
437 BuildMI(MBB, DL, II).addFPImm(CF).addImm(DI->getOffset()).
438 addMetadata(DI->getVariable());
439 } else if (unsigned Reg = lookUpRegForValue(V)) {
440 BuildMI(MBB, DL, II).addReg(Reg, RegState::Debug).addImm(DI->getOffset()).
441 addMetadata(DI->getVariable());
443 // We can't yet handle anything else here because it would require
444 // generating code, thus altering codegen because of debug info.
445 // Insert an undef so we can see what we dropped.
446 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
447 addMetadata(DI->getVariable());
451 case Intrinsic::eh_exception: {
452 EVT VT = TLI.getValueType(I->getType());
453 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
455 case TargetLowering::Expand: {
456 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
457 unsigned Reg = TLI.getExceptionAddressRegister();
458 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
459 unsigned ResultReg = createResultReg(RC);
460 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
462 assert(InsertedCopy && "Can't copy address registers!");
463 InsertedCopy = InsertedCopy;
464 UpdateValueMap(I, ResultReg);
470 case Intrinsic::eh_selector: {
471 EVT VT = TLI.getValueType(I->getType());
472 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
474 case TargetLowering::Expand: {
475 if (MBB->isLandingPad())
476 AddCatchInfo(*cast<CallInst>(I), &MF.getMMI(), MBB);
479 CatchInfoLost.insert(cast<CallInst>(I));
481 // FIXME: Mark exception selector register as live in. Hack for PR1508.
482 unsigned Reg = TLI.getExceptionSelectorRegister();
483 if (Reg) MBB->addLiveIn(Reg);
486 unsigned Reg = TLI.getExceptionSelectorRegister();
487 EVT SrcVT = TLI.getPointerTy();
488 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
489 unsigned ResultReg = createResultReg(RC);
490 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
492 assert(InsertedCopy && "Can't copy address registers!");
493 InsertedCopy = InsertedCopy;
495 bool ResultRegIsKill = hasTrivialKill(I);
497 // Cast the register to the type of the selector.
498 if (SrcVT.bitsGT(MVT::i32))
499 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
500 ResultReg, ResultRegIsKill);
501 else if (SrcVT.bitsLT(MVT::i32))
502 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
503 ISD::SIGN_EXTEND, ResultReg, ResultRegIsKill);
505 // Unhandled operand. Halt "fast" selection and bail.
508 UpdateValueMap(I, ResultReg);
517 // An arbitrary call. Bail.
521 bool FastISel::SelectCast(const User *I, unsigned Opcode) {
522 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
523 EVT DstVT = TLI.getValueType(I->getType());
525 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
526 DstVT == MVT::Other || !DstVT.isSimple())
527 // Unhandled type. Halt "fast" selection and bail.
530 // Check if the destination type is legal. Or as a special case,
531 // it may be i1 if we're doing a truncate because that's
532 // easy and somewhat common.
533 if (!TLI.isTypeLegal(DstVT))
534 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
535 // Unhandled type. Halt "fast" selection and bail.
538 // Check if the source operand is legal. Or as a special case,
539 // it may be i1 if we're doing zero-extension because that's
540 // easy and somewhat common.
541 if (!TLI.isTypeLegal(SrcVT))
542 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
543 // Unhandled type. Halt "fast" selection and bail.
546 unsigned InputReg = getRegForValue(I->getOperand(0));
548 // Unhandled operand. Halt "fast" selection and bail.
551 bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
553 // If the operand is i1, arrange for the high bits in the register to be zero.
554 if (SrcVT == MVT::i1) {
555 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
556 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg, InputRegIsKill);
559 InputRegIsKill = true;
561 // If the result is i1, truncate to the target's type for i1 first.
562 if (DstVT == MVT::i1)
563 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
565 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
568 InputReg, InputRegIsKill);
572 UpdateValueMap(I, ResultReg);
576 bool FastISel::SelectBitCast(const User *I) {
577 // If the bitcast doesn't change the type, just use the operand value.
578 if (I->getType() == I->getOperand(0)->getType()) {
579 unsigned Reg = getRegForValue(I->getOperand(0));
582 UpdateValueMap(I, Reg);
586 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
587 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
588 EVT DstVT = TLI.getValueType(I->getType());
590 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
591 DstVT == MVT::Other || !DstVT.isSimple() ||
592 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
593 // Unhandled type. Halt "fast" selection and bail.
596 unsigned Op0 = getRegForValue(I->getOperand(0));
598 // Unhandled operand. Halt "fast" selection and bail.
601 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
603 // First, try to perform the bitcast by inserting a reg-reg copy.
604 unsigned ResultReg = 0;
605 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
606 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
607 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
608 ResultReg = createResultReg(DstClass);
610 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
611 Op0, DstClass, SrcClass, DL);
616 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
618 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
619 ISD::BIT_CONVERT, Op0, Op0IsKill);
624 UpdateValueMap(I, ResultReg);
629 FastISel::SelectInstruction(const Instruction *I) {
630 // Just before the terminator instruction, insert instructions to
631 // feed PHI nodes in successor blocks.
632 if (isa<TerminatorInst>(I))
633 if (!HandlePHINodesInSuccessorBlocks(I->getParent()))
636 DL = I->getDebugLoc();
638 // First, try doing target-independent selection.
639 if (SelectOperator(I, I->getOpcode())) {
644 // Next, try calling the target to attempt to handle the instruction.
645 if (TargetSelectInstruction(I)) {
654 /// FastEmitBranch - Emit an unconditional branch to the given block,
655 /// unless it is the immediate (fall-through) successor, and update
658 FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) {
659 if (MBB->isLayoutSuccessor(MSucc)) {
660 // The unconditional fall-through case, which needs no instructions.
662 // The unconditional branch case.
663 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>(), DL);
665 MBB->addSuccessor(MSucc);
668 /// SelectFNeg - Emit an FNeg operation.
671 FastISel::SelectFNeg(const User *I) {
672 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
673 if (OpReg == 0) return false;
675 bool OpRegIsKill = hasTrivialKill(I);
677 // If the target has ISD::FNEG, use it.
678 EVT VT = TLI.getValueType(I->getType());
679 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
680 ISD::FNEG, OpReg, OpRegIsKill);
681 if (ResultReg != 0) {
682 UpdateValueMap(I, ResultReg);
686 // Bitcast the value to integer, twiddle the sign bit with xor,
687 // and then bitcast it back to floating-point.
688 if (VT.getSizeInBits() > 64) return false;
689 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
690 if (!TLI.isTypeLegal(IntVT))
693 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
694 ISD::BIT_CONVERT, OpReg, OpRegIsKill);
698 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR,
699 IntReg, /*Kill=*/true,
700 UINT64_C(1) << (VT.getSizeInBits()-1),
701 IntVT.getSimpleVT());
702 if (IntResultReg == 0)
705 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
706 ISD::BIT_CONVERT, IntResultReg, /*Kill=*/true);
710 UpdateValueMap(I, ResultReg);
715 FastISel::SelectOperator(const User *I, unsigned Opcode) {
717 case Instruction::Add:
718 return SelectBinaryOp(I, ISD::ADD);
719 case Instruction::FAdd:
720 return SelectBinaryOp(I, ISD::FADD);
721 case Instruction::Sub:
722 return SelectBinaryOp(I, ISD::SUB);
723 case Instruction::FSub:
724 // FNeg is currently represented in LLVM IR as a special case of FSub.
725 if (BinaryOperator::isFNeg(I))
726 return SelectFNeg(I);
727 return SelectBinaryOp(I, ISD::FSUB);
728 case Instruction::Mul:
729 return SelectBinaryOp(I, ISD::MUL);
730 case Instruction::FMul:
731 return SelectBinaryOp(I, ISD::FMUL);
732 case Instruction::SDiv:
733 return SelectBinaryOp(I, ISD::SDIV);
734 case Instruction::UDiv:
735 return SelectBinaryOp(I, ISD::UDIV);
736 case Instruction::FDiv:
737 return SelectBinaryOp(I, ISD::FDIV);
738 case Instruction::SRem:
739 return SelectBinaryOp(I, ISD::SREM);
740 case Instruction::URem:
741 return SelectBinaryOp(I, ISD::UREM);
742 case Instruction::FRem:
743 return SelectBinaryOp(I, ISD::FREM);
744 case Instruction::Shl:
745 return SelectBinaryOp(I, ISD::SHL);
746 case Instruction::LShr:
747 return SelectBinaryOp(I, ISD::SRL);
748 case Instruction::AShr:
749 return SelectBinaryOp(I, ISD::SRA);
750 case Instruction::And:
751 return SelectBinaryOp(I, ISD::AND);
752 case Instruction::Or:
753 return SelectBinaryOp(I, ISD::OR);
754 case Instruction::Xor:
755 return SelectBinaryOp(I, ISD::XOR);
757 case Instruction::GetElementPtr:
758 return SelectGetElementPtr(I);
760 case Instruction::Br: {
761 const BranchInst *BI = cast<BranchInst>(I);
763 if (BI->isUnconditional()) {
764 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
765 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
766 FastEmitBranch(MSucc, BI->getDebugLoc());
770 // Conditional branches are not handed yet.
771 // Halt "fast" selection and bail.
775 case Instruction::Unreachable:
779 case Instruction::Alloca:
780 // FunctionLowering has the static-sized case covered.
781 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
784 // Dynamic-sized alloca is not handled yet.
787 case Instruction::Call:
788 return SelectCall(I);
790 case Instruction::BitCast:
791 return SelectBitCast(I);
793 case Instruction::FPToSI:
794 return SelectCast(I, ISD::FP_TO_SINT);
795 case Instruction::ZExt:
796 return SelectCast(I, ISD::ZERO_EXTEND);
797 case Instruction::SExt:
798 return SelectCast(I, ISD::SIGN_EXTEND);
799 case Instruction::Trunc:
800 return SelectCast(I, ISD::TRUNCATE);
801 case Instruction::SIToFP:
802 return SelectCast(I, ISD::SINT_TO_FP);
804 case Instruction::IntToPtr: // Deliberate fall-through.
805 case Instruction::PtrToInt: {
806 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
807 EVT DstVT = TLI.getValueType(I->getType());
808 if (DstVT.bitsGT(SrcVT))
809 return SelectCast(I, ISD::ZERO_EXTEND);
810 if (DstVT.bitsLT(SrcVT))
811 return SelectCast(I, ISD::TRUNCATE);
812 unsigned Reg = getRegForValue(I->getOperand(0));
813 if (Reg == 0) return false;
814 UpdateValueMap(I, Reg);
818 case Instruction::PHI:
819 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
822 // Unhandled instruction. Halt "fast" selection and bail.
827 FastISel::FastISel(MachineFunction &mf,
828 DenseMap<const Value *, unsigned> &vm,
829 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
830 DenseMap<const AllocaInst *, int> &am,
831 std::vector<std::pair<MachineInstr*, unsigned> > &pn
833 , SmallSet<const Instruction *, 8> &cil
840 PHINodesToUpdate(pn),
845 MRI(MF.getRegInfo()),
846 MFI(*MF.getFrameInfo()),
847 MCP(*MF.getConstantPool()),
849 TD(*TM.getTargetData()),
850 TII(*TM.getInstrInfo()),
851 TLI(*TM.getTargetLowering()),
855 FastISel::~FastISel() {}
857 unsigned FastISel::FastEmit_(MVT, MVT,
862 unsigned FastISel::FastEmit_r(MVT, MVT,
864 unsigned /*Op0*/, bool /*Op0IsKill*/) {
868 unsigned FastISel::FastEmit_rr(MVT, MVT,
870 unsigned /*Op0*/, bool /*Op0IsKill*/,
871 unsigned /*Op1*/, bool /*Op1IsKill*/) {
875 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
879 unsigned FastISel::FastEmit_f(MVT, MVT,
880 unsigned, const ConstantFP * /*FPImm*/) {
884 unsigned FastISel::FastEmit_ri(MVT, MVT,
886 unsigned /*Op0*/, bool /*Op0IsKill*/,
891 unsigned FastISel::FastEmit_rf(MVT, MVT,
893 unsigned /*Op0*/, bool /*Op0IsKill*/,
894 const ConstantFP * /*FPImm*/) {
898 unsigned FastISel::FastEmit_rri(MVT, MVT,
900 unsigned /*Op0*/, bool /*Op0IsKill*/,
901 unsigned /*Op1*/, bool /*Op1IsKill*/,
906 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
907 /// to emit an instruction with an immediate operand using FastEmit_ri.
908 /// If that fails, it materializes the immediate into a register and try
909 /// FastEmit_rr instead.
910 unsigned FastISel::FastEmit_ri_(MVT VT, unsigned Opcode,
911 unsigned Op0, bool Op0IsKill,
912 uint64_t Imm, MVT ImmType) {
913 // First check if immediate type is legal. If not, we can't use the ri form.
914 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
917 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
918 if (MaterialReg == 0)
920 return FastEmit_rr(VT, VT, Opcode,
922 MaterialReg, /*Kill=*/true);
925 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
926 /// to emit an instruction with a floating-point immediate operand using
927 /// FastEmit_rf. If that fails, it materializes the immediate into a register
928 /// and try FastEmit_rr instead.
929 unsigned FastISel::FastEmit_rf_(MVT VT, unsigned Opcode,
930 unsigned Op0, bool Op0IsKill,
931 const ConstantFP *FPImm, MVT ImmType) {
932 // First check if immediate type is legal. If not, we can't use the rf form.
933 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, Op0IsKill, FPImm);
937 // Materialize the constant in a register.
938 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
939 if (MaterialReg == 0) {
940 // If the target doesn't have a way to directly enter a floating-point
941 // value into a register, use an alternate approach.
942 // TODO: The current approach only supports floating-point constants
943 // that can be constructed by conversion from integer values. This should
944 // be replaced by code that creates a load from a constant-pool entry,
945 // which will require some target-specific work.
946 const APFloat &Flt = FPImm->getValueAPF();
947 EVT IntVT = TLI.getPointerTy();
950 uint32_t IntBitWidth = IntVT.getSizeInBits();
952 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
953 APFloat::rmTowardZero, &isExact);
956 APInt IntVal(IntBitWidth, 2, x);
958 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
959 ISD::Constant, IntVal.getZExtValue());
962 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
963 ISD::SINT_TO_FP, IntegerReg, /*Kill=*/true);
964 if (MaterialReg == 0)
967 return FastEmit_rr(VT, VT, Opcode,
969 MaterialReg, /*Kill=*/true);
972 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
973 return MRI.createVirtualRegister(RC);
976 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
977 const TargetRegisterClass* RC) {
978 unsigned ResultReg = createResultReg(RC);
979 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
981 BuildMI(MBB, DL, II, ResultReg);
985 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
986 const TargetRegisterClass *RC,
987 unsigned Op0, bool Op0IsKill) {
988 unsigned ResultReg = createResultReg(RC);
989 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
991 if (II.getNumDefs() >= 1)
992 BuildMI(MBB, DL, II, ResultReg).addReg(Op0, Op0IsKill * RegState::Kill);
994 BuildMI(MBB, DL, II).addReg(Op0, Op0IsKill * RegState::Kill);
995 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
996 II.ImplicitDefs[0], RC, RC, DL);
1004 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
1005 const TargetRegisterClass *RC,
1006 unsigned Op0, bool Op0IsKill,
1007 unsigned Op1, bool Op1IsKill) {
1008 unsigned ResultReg = createResultReg(RC);
1009 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1011 if (II.getNumDefs() >= 1)
1012 BuildMI(MBB, DL, II, ResultReg)
1013 .addReg(Op0, Op0IsKill * RegState::Kill)
1014 .addReg(Op1, Op1IsKill * RegState::Kill);
1016 BuildMI(MBB, DL, II)
1017 .addReg(Op0, Op0IsKill * RegState::Kill)
1018 .addReg(Op1, Op1IsKill * RegState::Kill);
1019 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1020 II.ImplicitDefs[0], RC, RC, DL);
1027 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
1028 const TargetRegisterClass *RC,
1029 unsigned Op0, bool Op0IsKill,
1031 unsigned ResultReg = createResultReg(RC);
1032 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1034 if (II.getNumDefs() >= 1)
1035 BuildMI(MBB, DL, II, ResultReg)
1036 .addReg(Op0, Op0IsKill * RegState::Kill)
1039 BuildMI(MBB, DL, II)
1040 .addReg(Op0, Op0IsKill * RegState::Kill)
1042 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1043 II.ImplicitDefs[0], RC, RC, DL);
1050 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
1051 const TargetRegisterClass *RC,
1052 unsigned Op0, bool Op0IsKill,
1053 const ConstantFP *FPImm) {
1054 unsigned ResultReg = createResultReg(RC);
1055 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1057 if (II.getNumDefs() >= 1)
1058 BuildMI(MBB, DL, II, ResultReg)
1059 .addReg(Op0, Op0IsKill * RegState::Kill)
1062 BuildMI(MBB, DL, II)
1063 .addReg(Op0, Op0IsKill * RegState::Kill)
1065 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1066 II.ImplicitDefs[0], RC, RC, DL);
1073 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
1074 const TargetRegisterClass *RC,
1075 unsigned Op0, bool Op0IsKill,
1076 unsigned Op1, bool Op1IsKill,
1078 unsigned ResultReg = createResultReg(RC);
1079 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1081 if (II.getNumDefs() >= 1)
1082 BuildMI(MBB, DL, II, ResultReg)
1083 .addReg(Op0, Op0IsKill * RegState::Kill)
1084 .addReg(Op1, Op1IsKill * RegState::Kill)
1087 BuildMI(MBB, DL, II)
1088 .addReg(Op0, Op0IsKill * RegState::Kill)
1089 .addReg(Op1, Op1IsKill * RegState::Kill)
1091 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1092 II.ImplicitDefs[0], RC, RC, DL);
1099 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
1100 const TargetRegisterClass *RC,
1102 unsigned ResultReg = createResultReg(RC);
1103 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1105 if (II.getNumDefs() >= 1)
1106 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
1108 BuildMI(MBB, DL, II).addImm(Imm);
1109 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1110 II.ImplicitDefs[0], RC, RC, DL);
1117 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
1118 unsigned Op0, bool Op0IsKill,
1120 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
1122 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1123 const TargetInstrDesc &II = TII.get(TargetOpcode::EXTRACT_SUBREG);
1125 if (II.getNumDefs() >= 1)
1126 BuildMI(MBB, DL, II, ResultReg)
1127 .addReg(Op0, Op0IsKill * RegState::Kill)
1130 BuildMI(MBB, DL, II)
1131 .addReg(Op0, Op0IsKill * RegState::Kill)
1133 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1134 II.ImplicitDefs[0], RC, RC, DL);
1141 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1142 /// with all but the least significant bit set to zero.
1143 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1144 return FastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
1147 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
1148 /// Emit code to ensure constants are copied into registers when needed.
1149 /// Remember the virtual registers that need to be added to the Machine PHI
1150 /// nodes as input. We cannot just directly add them, because expansion
1151 /// might result in multiple MBB's for one BB. As such, the start of the
1152 /// BB might correspond to a different MBB than the end.
1153 bool FastISel::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
1154 const TerminatorInst *TI = LLVMBB->getTerminator();
1156 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
1157 unsigned OrigNumPHINodesToUpdate = PHINodesToUpdate.size();
1159 // Check successor nodes' PHI nodes that expect a constant to be available
1161 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
1162 const BasicBlock *SuccBB = TI->getSuccessor(succ);
1163 if (!isa<PHINode>(SuccBB->begin())) continue;
1164 MachineBasicBlock *SuccMBB = MBBMap[SuccBB];
1166 // If this terminator has multiple identical successors (common for
1167 // switches), only handle each succ once.
1168 if (!SuccsHandled.insert(SuccMBB)) continue;
1170 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
1172 // At this point we know that there is a 1-1 correspondence between LLVM PHI
1173 // nodes and Machine PHI nodes, but the incoming operands have not been
1175 for (BasicBlock::const_iterator I = SuccBB->begin();
1176 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
1178 // Ignore dead phi's.
1179 if (PN->use_empty()) continue;
1181 // Only handle legal types. Two interesting things to note here. First,
1182 // by bailing out early, we may leave behind some dead instructions,
1183 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
1184 // own moves. Second, this check is necessary becuase FastISel doesn't
1185 // use CreateRegForValue to create registers, so it always creates
1186 // exactly one register for each non-void instruction.
1187 EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
1188 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
1191 VT = TLI.getTypeToTransformTo(LLVMBB->getContext(), VT);
1193 PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
1198 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
1200 // Set the DebugLoc for the copy. Prefer the location of the operand
1201 // if there is one; use the location of the PHI otherwise.
1202 DL = PN->getDebugLoc();
1203 if (const Instruction *Inst = dyn_cast<Instruction>(PHIOp))
1204 DL = Inst->getDebugLoc();
1206 unsigned Reg = getRegForValue(PHIOp);
1208 PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
1211 PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));