1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/LLVMContext.h"
47 #include "llvm/CodeGen/FastISel.h"
48 #include "llvm/CodeGen/MachineInstrBuilder.h"
49 #include "llvm/CodeGen/MachineModuleInfo.h"
50 #include "llvm/CodeGen/MachineRegisterInfo.h"
51 #include "llvm/CodeGen/DwarfWriter.h"
52 #include "llvm/Analysis/DebugInfo.h"
53 #include "llvm/Target/TargetData.h"
54 #include "llvm/Target/TargetInstrInfo.h"
55 #include "llvm/Target/TargetLowering.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "SelectionDAGBuild.h"
60 unsigned FastISel::getRegForValue(Value *V) {
61 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
62 // Don't handle non-simple values in FastISel.
63 if (!RealVT.isSimple())
66 // Ignore illegal types. We must do this before looking up the value
67 // in ValueMap because Arguments are given virtual registers regardless
68 // of whether FastISel can handle them.
69 MVT VT = RealVT.getSimpleVT();
70 if (!TLI.isTypeLegal(VT)) {
71 // Promote MVT::i1 to a legal type though, because it's common and easy.
73 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
78 // Look up the value to see if we already have a register for it. We
79 // cache values defined by Instructions across blocks, and other values
80 // only locally. This is because Instructions already have the SSA
81 // def-dominatess-use requirement enforced.
82 if (ValueMap.count(V))
84 unsigned Reg = LocalValueMap[V];
88 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
89 if (CI->getValue().getActiveBits() <= 64)
90 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
91 } else if (isa<AllocaInst>(V)) {
92 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
93 } else if (isa<ConstantPointerNull>(V)) {
94 // Translate this as an integer zero so that it can be
95 // local-CSE'd with actual integer zeros.
97 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
98 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
99 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
102 const APFloat &Flt = CF->getValueAPF();
103 EVT IntVT = TLI.getPointerTy();
106 uint32_t IntBitWidth = IntVT.getSizeInBits();
108 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
109 APFloat::rmTowardZero, &isExact);
111 APInt IntVal(IntBitWidth, 2, x);
113 unsigned IntegerReg =
114 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
116 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
119 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
120 if (!SelectOperator(CE, CE->getOpcode())) return 0;
121 Reg = LocalValueMap[CE];
122 } else if (isa<UndefValue>(V)) {
123 Reg = createResultReg(TLI.getRegClassFor(VT));
124 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
127 // If target-independent code couldn't handle the value, give target-specific
129 if (!Reg && isa<Constant>(V))
130 Reg = TargetMaterializeConstant(cast<Constant>(V));
132 // Don't cache constant materializations in the general ValueMap.
133 // To do so would require tracking what uses they dominate.
135 LocalValueMap[V] = Reg;
139 unsigned FastISel::lookUpRegForValue(Value *V) {
140 // Look up the value to see if we already have a register for it. We
141 // cache values defined by Instructions across blocks, and other values
142 // only locally. This is because Instructions already have the SSA
143 // def-dominatess-use requirement enforced.
144 if (ValueMap.count(V))
146 return LocalValueMap[V];
149 /// UpdateValueMap - Update the value map to include the new mapping for this
150 /// instruction, or insert an extra copy to get the result in a previous
151 /// determined register.
152 /// NOTE: This is only necessary because we might select a block that uses
153 /// a value before we select the block that defines the value. It might be
154 /// possible to fix this by selecting blocks in reverse postorder.
155 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
156 if (!isa<Instruction>(I)) {
157 LocalValueMap[I] = Reg;
161 unsigned &AssignedReg = ValueMap[I];
162 if (AssignedReg == 0)
164 else if (Reg != AssignedReg) {
165 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
166 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
167 Reg, RegClass, RegClass);
172 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
173 unsigned IdxN = getRegForValue(Idx);
175 // Unhandled operand. Halt "fast" selection and bail.
178 // If the index is smaller or larger than intptr_t, truncate or extend it.
179 MVT PtrVT = TLI.getPointerTy();
180 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
181 if (IdxVT.bitsLT(PtrVT))
182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
183 else if (IdxVT.bitsGT(PtrVT))
184 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
188 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
189 /// which has an opcode which directly corresponds to the given ISD opcode.
191 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
192 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
193 if (VT == MVT::Other || !VT.isSimple())
194 // Unhandled type. Halt "fast" selection and bail.
197 // We only handle legal types. For example, on x86-32 the instruction
198 // selector contains all of the 64-bit instructions from x86-64,
199 // under the assumption that i64 won't be used if the target doesn't
201 if (!TLI.isTypeLegal(VT)) {
202 // MVT::i1 is special. Allow AND, OR, or XOR because they
203 // don't require additional zeroing, which makes them easy.
205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
206 ISDOpcode == ISD::XOR))
207 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
212 unsigned Op0 = getRegForValue(I->getOperand(0));
214 // Unhandled operand. Halt "fast" selection and bail.
217 // Check if the second operand is a constant and handle it appropriately.
218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
220 ISDOpcode, Op0, CI->getZExtValue());
221 if (ResultReg != 0) {
222 // We successfully emitted code for the given LLVM Instruction.
223 UpdateValueMap(I, ResultReg);
228 // Check if the second operand is a constant float.
229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
232 if (ResultReg != 0) {
233 // We successfully emitted code for the given LLVM Instruction.
234 UpdateValueMap(I, ResultReg);
239 unsigned Op1 = getRegForValue(I->getOperand(1));
241 // Unhandled operand. Halt "fast" selection and bail.
244 // Now we have both operands in registers. Emit the instruction.
245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
246 ISDOpcode, Op0, Op1);
248 // Target-specific code wasn't able to find a machine opcode for
249 // the given ISD opcode and type. Halt "fast" selection and bail.
252 // We successfully emitted code for the given LLVM Instruction.
253 UpdateValueMap(I, ResultReg);
257 bool FastISel::SelectGetElementPtr(User *I) {
258 unsigned N = getRegForValue(I->getOperand(0));
260 // Unhandled operand. Halt "fast" selection and bail.
263 const Type *Ty = I->getOperand(0)->getType();
264 MVT VT = TLI.getPointerTy();
265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
273 // FIXME: This can be optimized by combining the add with a
275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
277 // Unhandled operand. Halt "fast" selection and bail.
280 Ty = StTy->getElementType(Field);
282 Ty = cast<SequentialType>(Ty)->getElementType();
284 // If this is a constant subscript, handle it quickly.
285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
286 if (CI->getZExtValue() == 0) continue;
288 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
291 // Unhandled operand. Halt "fast" selection and bail.
296 // N = N + Idx * ElementSize;
297 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
298 unsigned IdxN = getRegForGEPIndex(Idx);
300 // Unhandled operand. Halt "fast" selection and bail.
303 if (ElementSize != 1) {
304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
306 // Unhandled operand. Halt "fast" selection and bail.
309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
311 // Unhandled operand. Halt "fast" selection and bail.
316 // We successfully emitted code for the given LLVM Instruction.
317 UpdateValueMap(I, N);
321 bool FastISel::SelectCall(User *I) {
322 Function *F = cast<CallInst>(I)->getCalledFunction();
323 if (!F) return false;
325 unsigned IID = F->getIntrinsicID();
328 case Intrinsic::dbg_stoppoint:
329 case Intrinsic::dbg_region_start:
330 case Intrinsic::dbg_region_end:
331 case Intrinsic::dbg_func_start:
332 // FIXME - Remove this instructions once the dust settles.
334 case Intrinsic::dbg_declare: {
335 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
336 if (!isValidDebugInfoIntrinsic(*DI, CodeGenOpt::None) || !DW
337 || !DW->ShouldEmitDwarfDebug())
340 Value *Address = DI->getAddress();
341 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
342 Address = BCI->getOperand(0);
343 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
344 // Don't handle byval struct arguments or VLAs, for example.
346 DenseMap<const AllocaInst*, int>::iterator SI =
347 StaticAllocaMap.find(AI);
348 if (SI == StaticAllocaMap.end()) break; // VLAs.
351 MetadataContext &TheMetadata =
352 DI->getParent()->getContext().getMetadata();
353 unsigned MDDbgKind = TheMetadata.getMDKind("dbg");
354 MDNode *Dbg = TheMetadata.getMD(MDDbgKind, DI);
355 MMI->setVariableDbgInfo(DI->getVariable(), FI, Dbg);
359 case Intrinsic::eh_exception: {
360 EVT VT = TLI.getValueType(I->getType());
361 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
363 case TargetLowering::Expand: {
364 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
365 unsigned Reg = TLI.getExceptionAddressRegister();
366 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
367 unsigned ResultReg = createResultReg(RC);
368 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
370 assert(InsertedCopy && "Can't copy address registers!");
371 InsertedCopy = InsertedCopy;
372 UpdateValueMap(I, ResultReg);
378 case Intrinsic::eh_selector: {
379 EVT VT = TLI.getValueType(I->getType());
380 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
382 case TargetLowering::Expand: {
384 if (MBB->isLandingPad())
385 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
388 CatchInfoLost.insert(cast<CallInst>(I));
390 // FIXME: Mark exception selector register as live in. Hack for PR1508.
391 unsigned Reg = TLI.getExceptionSelectorRegister();
392 if (Reg) MBB->addLiveIn(Reg);
395 unsigned Reg = TLI.getExceptionSelectorRegister();
396 EVT SrcVT = TLI.getPointerTy();
397 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
398 unsigned ResultReg = createResultReg(RC);
399 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
401 assert(InsertedCopy && "Can't copy address registers!");
402 InsertedCopy = InsertedCopy;
404 // Cast the register to the type of the selector.
405 if (SrcVT.bitsGT(MVT::i32))
406 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32, ISD::TRUNCATE,
408 else if (SrcVT.bitsLT(MVT::i32))
409 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), MVT::i32,
410 ISD::SIGN_EXTEND, ResultReg);
412 // Unhandled operand. Halt "fast" selection and bail.
415 UpdateValueMap(I, ResultReg);
418 getRegForValue(Constant::getNullValue(I->getType()));
419 UpdateValueMap(I, ResultReg);
430 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
431 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
432 EVT DstVT = TLI.getValueType(I->getType());
434 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
435 DstVT == MVT::Other || !DstVT.isSimple())
436 // Unhandled type. Halt "fast" selection and bail.
439 // Check if the destination type is legal. Or as a special case,
440 // it may be i1 if we're doing a truncate because that's
441 // easy and somewhat common.
442 if (!TLI.isTypeLegal(DstVT))
443 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
444 // Unhandled type. Halt "fast" selection and bail.
447 // Check if the source operand is legal. Or as a special case,
448 // it may be i1 if we're doing zero-extension because that's
449 // easy and somewhat common.
450 if (!TLI.isTypeLegal(SrcVT))
451 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
452 // Unhandled type. Halt "fast" selection and bail.
455 unsigned InputReg = getRegForValue(I->getOperand(0));
457 // Unhandled operand. Halt "fast" selection and bail.
460 // If the operand is i1, arrange for the high bits in the register to be zero.
461 if (SrcVT == MVT::i1) {
462 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
463 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
467 // If the result is i1, truncate to the target's type for i1 first.
468 if (DstVT == MVT::i1)
469 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
471 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
478 UpdateValueMap(I, ResultReg);
482 bool FastISel::SelectBitCast(User *I) {
483 // If the bitcast doesn't change the type, just use the operand value.
484 if (I->getType() == I->getOperand(0)->getType()) {
485 unsigned Reg = getRegForValue(I->getOperand(0));
488 UpdateValueMap(I, Reg);
492 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
493 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
494 EVT DstVT = TLI.getValueType(I->getType());
496 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
497 DstVT == MVT::Other || !DstVT.isSimple() ||
498 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
499 // Unhandled type. Halt "fast" selection and bail.
502 unsigned Op0 = getRegForValue(I->getOperand(0));
504 // Unhandled operand. Halt "fast" selection and bail.
507 // First, try to perform the bitcast by inserting a reg-reg copy.
508 unsigned ResultReg = 0;
509 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
510 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
511 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
512 ResultReg = createResultReg(DstClass);
514 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
515 Op0, DstClass, SrcClass);
520 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
522 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
523 ISD::BIT_CONVERT, Op0);
528 UpdateValueMap(I, ResultReg);
533 FastISel::SelectInstruction(Instruction *I) {
534 return SelectOperator(I, I->getOpcode());
537 /// FastEmitBranch - Emit an unconditional branch to the given block,
538 /// unless it is the immediate (fall-through) successor, and update
541 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
542 MachineFunction::iterator NextMBB =
543 next(MachineFunction::iterator(MBB));
545 if (MBB->isLayoutSuccessor(MSucc)) {
546 // The unconditional fall-through case, which needs no instructions.
548 // The unconditional branch case.
549 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
551 MBB->addSuccessor(MSucc);
554 /// SelectFNeg - Emit an FNeg operation.
557 FastISel::SelectFNeg(User *I) {
558 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
559 if (OpReg == 0) return false;
561 // If the target has ISD::FNEG, use it.
562 EVT VT = TLI.getValueType(I->getType());
563 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
565 if (ResultReg != 0) {
566 UpdateValueMap(I, ResultReg);
570 // Bitcast the value to integer, twiddle the sign bit with xor,
571 // and then bitcast it back to floating-point.
572 if (VT.getSizeInBits() > 64) return false;
573 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
574 if (!TLI.isTypeLegal(IntVT))
577 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
578 ISD::BIT_CONVERT, OpReg);
582 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
583 UINT64_C(1) << (VT.getSizeInBits()-1),
584 IntVT.getSimpleVT());
585 if (IntResultReg == 0)
588 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
589 ISD::BIT_CONVERT, IntResultReg);
593 UpdateValueMap(I, ResultReg);
598 FastISel::SelectOperator(User *I, unsigned Opcode) {
600 case Instruction::Add:
601 return SelectBinaryOp(I, ISD::ADD);
602 case Instruction::FAdd:
603 return SelectBinaryOp(I, ISD::FADD);
604 case Instruction::Sub:
605 return SelectBinaryOp(I, ISD::SUB);
606 case Instruction::FSub:
607 // FNeg is currently represented in LLVM IR as a special case of FSub.
608 if (BinaryOperator::isFNeg(I))
609 return SelectFNeg(I);
610 return SelectBinaryOp(I, ISD::FSUB);
611 case Instruction::Mul:
612 return SelectBinaryOp(I, ISD::MUL);
613 case Instruction::FMul:
614 return SelectBinaryOp(I, ISD::FMUL);
615 case Instruction::SDiv:
616 return SelectBinaryOp(I, ISD::SDIV);
617 case Instruction::UDiv:
618 return SelectBinaryOp(I, ISD::UDIV);
619 case Instruction::FDiv:
620 return SelectBinaryOp(I, ISD::FDIV);
621 case Instruction::SRem:
622 return SelectBinaryOp(I, ISD::SREM);
623 case Instruction::URem:
624 return SelectBinaryOp(I, ISD::UREM);
625 case Instruction::FRem:
626 return SelectBinaryOp(I, ISD::FREM);
627 case Instruction::Shl:
628 return SelectBinaryOp(I, ISD::SHL);
629 case Instruction::LShr:
630 return SelectBinaryOp(I, ISD::SRL);
631 case Instruction::AShr:
632 return SelectBinaryOp(I, ISD::SRA);
633 case Instruction::And:
634 return SelectBinaryOp(I, ISD::AND);
635 case Instruction::Or:
636 return SelectBinaryOp(I, ISD::OR);
637 case Instruction::Xor:
638 return SelectBinaryOp(I, ISD::XOR);
640 case Instruction::GetElementPtr:
641 return SelectGetElementPtr(I);
643 case Instruction::Br: {
644 BranchInst *BI = cast<BranchInst>(I);
646 if (BI->isUnconditional()) {
647 BasicBlock *LLVMSucc = BI->getSuccessor(0);
648 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
649 FastEmitBranch(MSucc);
653 // Conditional branches are not handed yet.
654 // Halt "fast" selection and bail.
658 case Instruction::Unreachable:
662 case Instruction::PHI:
663 // PHI nodes are already emitted.
666 case Instruction::Alloca:
667 // FunctionLowering has the static-sized case covered.
668 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
671 // Dynamic-sized alloca is not handled yet.
674 case Instruction::Call:
675 return SelectCall(I);
677 case Instruction::BitCast:
678 return SelectBitCast(I);
680 case Instruction::FPToSI:
681 return SelectCast(I, ISD::FP_TO_SINT);
682 case Instruction::ZExt:
683 return SelectCast(I, ISD::ZERO_EXTEND);
684 case Instruction::SExt:
685 return SelectCast(I, ISD::SIGN_EXTEND);
686 case Instruction::Trunc:
687 return SelectCast(I, ISD::TRUNCATE);
688 case Instruction::SIToFP:
689 return SelectCast(I, ISD::SINT_TO_FP);
691 case Instruction::IntToPtr: // Deliberate fall-through.
692 case Instruction::PtrToInt: {
693 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
694 EVT DstVT = TLI.getValueType(I->getType());
695 if (DstVT.bitsGT(SrcVT))
696 return SelectCast(I, ISD::ZERO_EXTEND);
697 if (DstVT.bitsLT(SrcVT))
698 return SelectCast(I, ISD::TRUNCATE);
699 unsigned Reg = getRegForValue(I->getOperand(0));
700 if (Reg == 0) return false;
701 UpdateValueMap(I, Reg);
706 // Unhandled instruction. Halt "fast" selection and bail.
711 FastISel::FastISel(MachineFunction &mf,
712 MachineModuleInfo *mmi,
714 DenseMap<const Value *, unsigned> &vm,
715 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
716 DenseMap<const AllocaInst *, int> &am
718 , SmallSet<Instruction*, 8> &cil
731 MRI(MF.getRegInfo()),
732 MFI(*MF.getFrameInfo()),
733 MCP(*MF.getConstantPool()),
735 TD(*TM.getTargetData()),
736 TII(*TM.getInstrInfo()),
737 TLI(*TM.getTargetLowering()) {
740 FastISel::~FastISel() {}
742 unsigned FastISel::FastEmit_(MVT, MVT,
747 unsigned FastISel::FastEmit_r(MVT, MVT,
748 ISD::NodeType, unsigned /*Op0*/) {
752 unsigned FastISel::FastEmit_rr(MVT, MVT,
753 ISD::NodeType, unsigned /*Op0*/,
758 unsigned FastISel::FastEmit_i(MVT, MVT, ISD::NodeType, uint64_t /*Imm*/) {
762 unsigned FastISel::FastEmit_f(MVT, MVT,
763 ISD::NodeType, ConstantFP * /*FPImm*/) {
767 unsigned FastISel::FastEmit_ri(MVT, MVT,
768 ISD::NodeType, unsigned /*Op0*/,
773 unsigned FastISel::FastEmit_rf(MVT, MVT,
774 ISD::NodeType, unsigned /*Op0*/,
775 ConstantFP * /*FPImm*/) {
779 unsigned FastISel::FastEmit_rri(MVT, MVT,
781 unsigned /*Op0*/, unsigned /*Op1*/,
786 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
787 /// to emit an instruction with an immediate operand using FastEmit_ri.
788 /// If that fails, it materializes the immediate into a register and try
789 /// FastEmit_rr instead.
790 unsigned FastISel::FastEmit_ri_(MVT VT, ISD::NodeType Opcode,
791 unsigned Op0, uint64_t Imm,
793 // First check if immediate type is legal. If not, we can't use the ri form.
794 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
797 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
798 if (MaterialReg == 0)
800 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
803 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
804 /// to emit an instruction with a floating-point immediate operand using
805 /// FastEmit_rf. If that fails, it materializes the immediate into a register
806 /// and try FastEmit_rr instead.
807 unsigned FastISel::FastEmit_rf_(MVT VT, ISD::NodeType Opcode,
808 unsigned Op0, ConstantFP *FPImm,
810 // First check if immediate type is legal. If not, we can't use the rf form.
811 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
815 // Materialize the constant in a register.
816 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
817 if (MaterialReg == 0) {
818 // If the target doesn't have a way to directly enter a floating-point
819 // value into a register, use an alternate approach.
820 // TODO: The current approach only supports floating-point constants
821 // that can be constructed by conversion from integer values. This should
822 // be replaced by code that creates a load from a constant-pool entry,
823 // which will require some target-specific work.
824 const APFloat &Flt = FPImm->getValueAPF();
825 EVT IntVT = TLI.getPointerTy();
828 uint32_t IntBitWidth = IntVT.getSizeInBits();
830 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
831 APFloat::rmTowardZero, &isExact);
834 APInt IntVal(IntBitWidth, 2, x);
836 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
837 ISD::Constant, IntVal.getZExtValue());
840 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
841 ISD::SINT_TO_FP, IntegerReg);
842 if (MaterialReg == 0)
845 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
848 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
849 return MRI.createVirtualRegister(RC);
852 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
853 const TargetRegisterClass* RC) {
854 unsigned ResultReg = createResultReg(RC);
855 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
857 BuildMI(MBB, DL, II, ResultReg);
861 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
862 const TargetRegisterClass *RC,
864 unsigned ResultReg = createResultReg(RC);
865 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
867 if (II.getNumDefs() >= 1)
868 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
870 BuildMI(MBB, DL, II).addReg(Op0);
871 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
872 II.ImplicitDefs[0], RC, RC);
880 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
881 const TargetRegisterClass *RC,
882 unsigned Op0, unsigned Op1) {
883 unsigned ResultReg = createResultReg(RC);
884 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
886 if (II.getNumDefs() >= 1)
887 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
889 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
890 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
891 II.ImplicitDefs[0], RC, RC);
898 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
899 const TargetRegisterClass *RC,
900 unsigned Op0, uint64_t Imm) {
901 unsigned ResultReg = createResultReg(RC);
902 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
904 if (II.getNumDefs() >= 1)
905 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
907 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
908 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
909 II.ImplicitDefs[0], RC, RC);
916 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
917 const TargetRegisterClass *RC,
918 unsigned Op0, ConstantFP *FPImm) {
919 unsigned ResultReg = createResultReg(RC);
920 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
922 if (II.getNumDefs() >= 1)
923 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
925 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
926 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
927 II.ImplicitDefs[0], RC, RC);
934 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
935 const TargetRegisterClass *RC,
936 unsigned Op0, unsigned Op1, uint64_t Imm) {
937 unsigned ResultReg = createResultReg(RC);
938 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
940 if (II.getNumDefs() >= 1)
941 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
943 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
944 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
945 II.ImplicitDefs[0], RC, RC);
952 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
953 const TargetRegisterClass *RC,
955 unsigned ResultReg = createResultReg(RC);
956 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
958 if (II.getNumDefs() >= 1)
959 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
961 BuildMI(MBB, DL, II).addImm(Imm);
962 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
963 II.ImplicitDefs[0], RC, RC);
970 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
971 unsigned Op0, uint32_t Idx) {
972 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
974 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
975 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
977 if (II.getNumDefs() >= 1)
978 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
980 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
981 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
982 II.ImplicitDefs[0], RC, RC);
989 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
990 /// with all but the least significant bit set to zero.
991 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
992 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);