1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Instructions.h"
15 #include "llvm/CodeGen/FastISel.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetInstrInfo.h"
21 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
22 /// which has an opcode which directly corresponds to the given ISD opcode.
24 bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
25 DenseMap<const Value*, unsigned> &ValueMap) {
26 unsigned Op0 = ValueMap[I->getOperand(0)];
27 unsigned Op1 = ValueMap[I->getOperand(1)];
28 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
29 if (VT == MVT::Other || !VT.isSimple())
30 // Unhandled type. Halt "fast" selection and bail.
33 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), ISDOpcode, Op0, Op1);
35 // Target-specific code wasn't able to find a machine opcode for
36 // the given ISD opcode and type. Halt "fast" selection and bail.
39 // We successfully emitted code for the given LLVM Instruction.
40 ValueMap[I] = ResultReg;
44 bool FastISel::SelectGetElementPtr(Instruction *I,
45 DenseMap<const Value*, unsigned> &ValueMap) {
51 FastISel::SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
52 DenseMap<const Value*, unsigned> &ValueMap) {
53 BasicBlock::iterator I = Begin;
55 for (; I != End; ++I) {
56 switch (I->getOpcode()) {
57 case Instruction::Add: {
58 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
59 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
61 case Instruction::Sub: {
62 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
63 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
65 case Instruction::Mul: {
66 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
67 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
69 case Instruction::SDiv:
70 if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
71 case Instruction::UDiv:
72 if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
73 case Instruction::FDiv:
74 if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
75 case Instruction::SRem:
76 if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
77 case Instruction::URem:
78 if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
79 case Instruction::FRem:
80 if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
81 case Instruction::Shl:
82 if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
83 case Instruction::LShr:
84 if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
85 case Instruction::AShr:
86 if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
87 case Instruction::And:
88 if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
90 if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
91 case Instruction::Xor:
92 if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
94 case Instruction::GetElementPtr:
95 if (!SelectGetElementPtr(I, ValueMap)) return I;
98 case Instruction::Br: {
99 BranchInst *BI = cast<BranchInst>(I);
101 // For now, check for and handle just the most trivial case: an
102 // unconditional fall-through branch.
103 if (BI->isUnconditional() &&
104 next(MachineFunction::iterator(MBB))->getBasicBlock() ==
105 BI->getSuccessor(0)) {
106 MBB->addSuccessor(next(MachineFunction::iterator(MBB)));
110 // Something more complicated. Halt "fast" selection and bail.
114 // Unhandled instruction. Halt "fast" selection and bail.
122 FastISel::~FastISel() {}
124 unsigned FastISel::FastEmit_(MVT::SimpleValueType, ISD::NodeType) {
128 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, ISD::NodeType,
133 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, ISD::NodeType,
134 unsigned /*Op0*/, unsigned /*Op0*/) {
138 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
139 const TargetRegisterClass* RC) {
140 MachineRegisterInfo &MRI = MF->getRegInfo();
141 const TargetInstrDesc &II = TII->get(MachineInstOpcode);
142 unsigned ResultReg = MRI.createVirtualRegister(RC);
144 MachineInstr *MI = BuildMI(*MF, II, ResultReg);
150 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
151 const TargetRegisterClass *RC,
153 MachineRegisterInfo &MRI = MF->getRegInfo();
154 const TargetInstrDesc &II = TII->get(MachineInstOpcode);
155 unsigned ResultReg = MRI.createVirtualRegister(RC);
157 MachineInstr *MI = BuildMI(*MF, II, ResultReg);
158 MI->addOperand(MachineOperand::CreateReg(Op0, false));
164 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
165 const TargetRegisterClass *RC,
166 unsigned Op0, unsigned Op1) {
167 MachineRegisterInfo &MRI = MF->getRegInfo();
168 const TargetInstrDesc &II = TII->get(MachineInstOpcode);
169 unsigned ResultReg = MRI.createVirtualRegister(RC);
171 MachineInstr *MI = BuildMI(*MF, II, ResultReg);
172 MI->addOperand(MachineOperand::CreateReg(Op0, false));
173 MI->addOperand(MachineOperand::CreateReg(Op1, false));