1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/DwarfWriter.h"
51 #include "llvm/Analysis/DebugInfo.h"
52 #include "llvm/Target/TargetData.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "SelectionDAGBuild.h"
59 unsigned FastISel::getRegForValue(Value *V) {
60 MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
62 // Ignore illegal types. We must do this before looking up the value
63 // in ValueMap because Arguments are given virtual registers regardless
64 // of whether FastISel can handle them.
65 if (!TLI.isTypeLegal(VT)) {
66 // Promote MVT::i1 to a legal type though, because it's common and easy.
68 VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
73 // Look up the value to see if we already have a register for it. We
74 // cache values defined by Instructions across blocks, and other values
75 // only locally. This is because Instructions already have the SSA
76 // def-dominatess-use requirement enforced.
77 if (ValueMap.count(V))
79 unsigned Reg = LocalValueMap[V];
83 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
84 if (CI->getValue().getActiveBits() <= 64)
85 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
86 } else if (isa<AllocaInst>(V)) {
87 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
88 } else if (isa<ConstantPointerNull>(V)) {
89 // Translate this as an integer zero so that it can be
90 // local-CSE'd with actual integer zeros.
91 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType()));
92 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
93 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
96 const APFloat &Flt = CF->getValueAPF();
97 MVT IntVT = TLI.getPointerTy();
100 uint32_t IntBitWidth = IntVT.getSizeInBits();
102 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
103 APFloat::rmTowardZero, &isExact);
105 APInt IntVal(IntBitWidth, 2, x);
107 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal));
109 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
112 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
113 if (!SelectOperator(CE, CE->getOpcode())) return 0;
114 Reg = LocalValueMap[CE];
115 } else if (isa<UndefValue>(V)) {
116 Reg = createResultReg(TLI.getRegClassFor(VT));
117 BuildMI(MBB, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
120 // If target-independent code couldn't handle the value, give target-specific
122 if (!Reg && isa<Constant>(V))
123 Reg = TargetMaterializeConstant(cast<Constant>(V));
125 // Don't cache constant materializations in the general ValueMap.
126 // To do so would require tracking what uses they dominate.
128 LocalValueMap[V] = Reg;
132 unsigned FastISel::lookUpRegForValue(Value *V) {
133 // Look up the value to see if we already have a register for it. We
134 // cache values defined by Instructions across blocks, and other values
135 // only locally. This is because Instructions already have the SSA
136 // def-dominatess-use requirement enforced.
137 if (ValueMap.count(V))
139 return LocalValueMap[V];
142 /// UpdateValueMap - Update the value map to include the new mapping for this
143 /// instruction, or insert an extra copy to get the result in a previous
144 /// determined register.
145 /// NOTE: This is only necessary because we might select a block that uses
146 /// a value before we select the block that defines the value. It might be
147 /// possible to fix this by selecting blocks in reverse postorder.
148 void FastISel::UpdateValueMap(Value* I, unsigned Reg) {
149 if (!isa<Instruction>(I)) {
150 LocalValueMap[I] = Reg;
153 if (!ValueMap.count(I))
156 TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
157 Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
160 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
161 unsigned IdxN = getRegForValue(Idx);
163 // Unhandled operand. Halt "fast" selection and bail.
166 // If the index is smaller or larger than intptr_t, truncate or extend it.
167 MVT PtrVT = TLI.getPointerTy();
168 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
169 if (IdxVT.bitsLT(PtrVT))
170 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
171 ISD::SIGN_EXTEND, IdxN);
172 else if (IdxVT.bitsGT(PtrVT))
173 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
174 ISD::TRUNCATE, IdxN);
178 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
179 /// which has an opcode which directly corresponds to the given ISD opcode.
181 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
182 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
183 if (VT == MVT::Other || !VT.isSimple())
184 // Unhandled type. Halt "fast" selection and bail.
187 // We only handle legal types. For example, on x86-32 the instruction
188 // selector contains all of the 64-bit instructions from x86-64,
189 // under the assumption that i64 won't be used if the target doesn't
191 if (!TLI.isTypeLegal(VT)) {
192 // MVT::i1 is special. Allow AND, OR, or XOR because they
193 // don't require additional zeroing, which makes them easy.
195 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
196 ISDOpcode == ISD::XOR))
197 VT = TLI.getTypeToTransformTo(VT);
202 unsigned Op0 = getRegForValue(I->getOperand(0));
204 // Unhandled operand. Halt "fast" selection and bail.
207 // Check if the second operand is a constant and handle it appropriately.
208 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
209 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
210 ISDOpcode, Op0, CI->getZExtValue());
211 if (ResultReg != 0) {
212 // We successfully emitted code for the given LLVM Instruction.
213 UpdateValueMap(I, ResultReg);
218 // Check if the second operand is a constant float.
219 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
220 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
222 if (ResultReg != 0) {
223 // We successfully emitted code for the given LLVM Instruction.
224 UpdateValueMap(I, ResultReg);
229 unsigned Op1 = getRegForValue(I->getOperand(1));
231 // Unhandled operand. Halt "fast" selection and bail.
234 // Now we have both operands in registers. Emit the instruction.
235 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
236 ISDOpcode, Op0, Op1);
238 // Target-specific code wasn't able to find a machine opcode for
239 // the given ISD opcode and type. Halt "fast" selection and bail.
242 // We successfully emitted code for the given LLVM Instruction.
243 UpdateValueMap(I, ResultReg);
247 bool FastISel::SelectGetElementPtr(User *I) {
248 unsigned N = getRegForValue(I->getOperand(0));
250 // Unhandled operand. Halt "fast" selection and bail.
253 const Type *Ty = I->getOperand(0)->getType();
254 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
255 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
258 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
259 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
262 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
263 // FIXME: This can be optimized by combining the add with a
265 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
267 // Unhandled operand. Halt "fast" selection and bail.
270 Ty = StTy->getElementType(Field);
272 Ty = cast<SequentialType>(Ty)->getElementType();
274 // If this is a constant subscript, handle it quickly.
275 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
276 if (CI->getZExtValue() == 0) continue;
278 TD.getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
279 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
281 // Unhandled operand. Halt "fast" selection and bail.
286 // N = N + Idx * ElementSize;
287 uint64_t ElementSize = TD.getTypePaddedSize(Ty);
288 unsigned IdxN = getRegForGEPIndex(Idx);
290 // Unhandled operand. Halt "fast" selection and bail.
293 if (ElementSize != 1) {
294 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
296 // Unhandled operand. Halt "fast" selection and bail.
299 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
301 // Unhandled operand. Halt "fast" selection and bail.
306 // We successfully emitted code for the given LLVM Instruction.
307 UpdateValueMap(I, N);
311 bool FastISel::SelectCall(User *I) {
312 Function *F = cast<CallInst>(I)->getCalledFunction();
313 if (!F) return false;
315 unsigned IID = F->getIntrinsicID();
318 case Intrinsic::dbg_stoppoint: {
319 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
320 if (DW && SPI->getContext()) {
321 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
322 unsigned SrcFile = DW->RecordSource(CU.getDirectory(),
324 unsigned Line = SPI->getLine();
325 unsigned Col = SPI->getColumn();
326 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
327 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
328 BuildMI(MBB, II).addImm(ID);
332 case Intrinsic::dbg_region_start: {
333 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
334 if (DW && RSI->getContext()) {
336 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
337 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
338 BuildMI(MBB, II).addImm(ID);
342 case Intrinsic::dbg_region_end: {
343 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
344 if (DW && REI->getContext()) {
346 DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext()));
347 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
348 BuildMI(MBB, II).addImm(ID);
352 case Intrinsic::dbg_func_start: {
353 if (!DW) return true;
354 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
355 Value *SP = FSI->getSubprogram();
357 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is
358 // what (most?) gdb expects.
359 DISubprogram Subprogram(cast<GlobalVariable>(SP));
360 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
361 unsigned SrcFile = DW->RecordSource(CompileUnit.getDirectory(),
362 CompileUnit.getFilename());
363 // Record the source line but does not create a label for the normal
364 // function start. It will be emitted at asm emission time. However,
365 // create a label if this is a beginning of inlined function.
367 DW->RecordSourceLine(Subprogram.getLineNumber(), 0, SrcFile);
368 if (DW->getRecordSourceLineCount() != 1) {
369 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
370 BuildMI(MBB, II).addImm(LabelID);
375 case Intrinsic::dbg_declare: {
376 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
377 Value *Variable = DI->getVariable();
378 if (DW && Variable) {
379 // Determine the address of the declared object.
380 Value *Address = DI->getAddress();
381 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
382 Address = BCI->getOperand(0);
383 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
384 // Don't handle byval struct arguments, for example.
386 DenseMap<const AllocaInst*, int>::iterator SI =
387 StaticAllocaMap.find(AI);
388 assert(SI != StaticAllocaMap.end() && "Invalid dbg.declare!");
391 // Determine the debug globalvariable.
392 GlobalValue *GV = cast<GlobalVariable>(Variable);
394 // Build the DECLARE instruction.
395 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
396 BuildMI(MBB, II).addFrameIndex(FI).addGlobalAddress(GV);
400 case Intrinsic::eh_exception: {
401 MVT VT = TLI.getValueType(I->getType());
402 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
404 case TargetLowering::Expand: {
405 if (!MBB->isLandingPad()) {
406 // FIXME: Mark exception register as live in. Hack for PR1508.
407 unsigned Reg = TLI.getExceptionAddressRegister();
408 if (Reg) MBB->addLiveIn(Reg);
410 unsigned Reg = TLI.getExceptionAddressRegister();
411 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
412 unsigned ResultReg = createResultReg(RC);
413 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
415 assert(InsertedCopy && "Can't copy address registers!");
416 InsertedCopy = InsertedCopy;
417 UpdateValueMap(I, ResultReg);
423 case Intrinsic::eh_selector_i32:
424 case Intrinsic::eh_selector_i64: {
425 MVT VT = TLI.getValueType(I->getType());
426 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
428 case TargetLowering::Expand: {
429 MVT VT = (IID == Intrinsic::eh_selector_i32 ?
430 MVT::i32 : MVT::i64);
433 if (MBB->isLandingPad())
434 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
437 CatchInfoLost.insert(cast<CallInst>(I));
439 // FIXME: Mark exception selector register as live in. Hack for PR1508.
440 unsigned Reg = TLI.getExceptionSelectorRegister();
441 if (Reg) MBB->addLiveIn(Reg);
444 unsigned Reg = TLI.getExceptionSelectorRegister();
445 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
446 unsigned ResultReg = createResultReg(RC);
447 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
449 assert(InsertedCopy && "Can't copy address registers!");
450 InsertedCopy = InsertedCopy;
451 UpdateValueMap(I, ResultReg);
454 getRegForValue(Constant::getNullValue(I->getType()));
455 UpdateValueMap(I, ResultReg);
466 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
467 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
468 MVT DstVT = TLI.getValueType(I->getType());
470 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
471 DstVT == MVT::Other || !DstVT.isSimple() ||
472 !TLI.isTypeLegal(DstVT))
473 // Unhandled type. Halt "fast" selection and bail.
476 // Check if the source operand is legal. Or as a special case,
477 // it may be i1 if we're doing zero-extension because that's
478 // trivially easy and somewhat common.
479 if (!TLI.isTypeLegal(SrcVT)) {
480 if (SrcVT == MVT::i1 && Opcode == ISD::ZERO_EXTEND)
481 SrcVT = TLI.getTypeToTransformTo(SrcVT);
483 // Unhandled type. Halt "fast" selection and bail.
487 unsigned InputReg = getRegForValue(I->getOperand(0));
489 // Unhandled operand. Halt "fast" selection and bail.
492 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
499 UpdateValueMap(I, ResultReg);
503 bool FastISel::SelectBitCast(User *I) {
504 // If the bitcast doesn't change the type, just use the operand value.
505 if (I->getType() == I->getOperand(0)->getType()) {
506 unsigned Reg = getRegForValue(I->getOperand(0));
509 UpdateValueMap(I, Reg);
513 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
514 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
515 MVT DstVT = TLI.getValueType(I->getType());
517 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
518 DstVT == MVT::Other || !DstVT.isSimple() ||
519 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
520 // Unhandled type. Halt "fast" selection and bail.
523 unsigned Op0 = getRegForValue(I->getOperand(0));
525 // Unhandled operand. Halt "fast" selection and bail.
528 // First, try to perform the bitcast by inserting a reg-reg copy.
529 unsigned ResultReg = 0;
530 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
531 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
532 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
533 ResultReg = createResultReg(DstClass);
535 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
536 Op0, DstClass, SrcClass);
541 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
543 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
544 ISD::BIT_CONVERT, Op0);
549 UpdateValueMap(I, ResultReg);
554 FastISel::SelectInstruction(Instruction *I) {
555 return SelectOperator(I, I->getOpcode());
558 /// FastEmitBranch - Emit an unconditional branch to the given block,
559 /// unless it is the immediate (fall-through) successor, and update
562 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
563 MachineFunction::iterator NextMBB =
564 next(MachineFunction::iterator(MBB));
566 if (MBB->isLayoutSuccessor(MSucc)) {
567 // The unconditional fall-through case, which needs no instructions.
569 // The unconditional branch case.
570 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
572 MBB->addSuccessor(MSucc);
576 FastISel::SelectOperator(User *I, unsigned Opcode) {
578 case Instruction::Add: {
579 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
580 return SelectBinaryOp(I, Opc);
582 case Instruction::Sub: {
583 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
584 return SelectBinaryOp(I, Opc);
586 case Instruction::Mul: {
587 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
588 return SelectBinaryOp(I, Opc);
590 case Instruction::SDiv:
591 return SelectBinaryOp(I, ISD::SDIV);
592 case Instruction::UDiv:
593 return SelectBinaryOp(I, ISD::UDIV);
594 case Instruction::FDiv:
595 return SelectBinaryOp(I, ISD::FDIV);
596 case Instruction::SRem:
597 return SelectBinaryOp(I, ISD::SREM);
598 case Instruction::URem:
599 return SelectBinaryOp(I, ISD::UREM);
600 case Instruction::FRem:
601 return SelectBinaryOp(I, ISD::FREM);
602 case Instruction::Shl:
603 return SelectBinaryOp(I, ISD::SHL);
604 case Instruction::LShr:
605 return SelectBinaryOp(I, ISD::SRL);
606 case Instruction::AShr:
607 return SelectBinaryOp(I, ISD::SRA);
608 case Instruction::And:
609 return SelectBinaryOp(I, ISD::AND);
610 case Instruction::Or:
611 return SelectBinaryOp(I, ISD::OR);
612 case Instruction::Xor:
613 return SelectBinaryOp(I, ISD::XOR);
615 case Instruction::GetElementPtr:
616 return SelectGetElementPtr(I);
618 case Instruction::Br: {
619 BranchInst *BI = cast<BranchInst>(I);
621 if (BI->isUnconditional()) {
622 BasicBlock *LLVMSucc = BI->getSuccessor(0);
623 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
624 FastEmitBranch(MSucc);
628 // Conditional branches are not handed yet.
629 // Halt "fast" selection and bail.
633 case Instruction::Unreachable:
637 case Instruction::PHI:
638 // PHI nodes are already emitted.
641 case Instruction::Alloca:
642 // FunctionLowering has the static-sized case covered.
643 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
646 // Dynamic-sized alloca is not handled yet.
649 case Instruction::Call:
650 return SelectCall(I);
652 case Instruction::BitCast:
653 return SelectBitCast(I);
655 case Instruction::FPToSI:
656 return SelectCast(I, ISD::FP_TO_SINT);
657 case Instruction::ZExt:
658 return SelectCast(I, ISD::ZERO_EXTEND);
659 case Instruction::SExt:
660 return SelectCast(I, ISD::SIGN_EXTEND);
661 case Instruction::Trunc:
662 return SelectCast(I, ISD::TRUNCATE);
663 case Instruction::SIToFP:
664 return SelectCast(I, ISD::SINT_TO_FP);
666 case Instruction::IntToPtr: // Deliberate fall-through.
667 case Instruction::PtrToInt: {
668 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
669 MVT DstVT = TLI.getValueType(I->getType());
670 if (DstVT.bitsGT(SrcVT))
671 return SelectCast(I, ISD::ZERO_EXTEND);
672 if (DstVT.bitsLT(SrcVT))
673 return SelectCast(I, ISD::TRUNCATE);
674 unsigned Reg = getRegForValue(I->getOperand(0));
675 if (Reg == 0) return false;
676 UpdateValueMap(I, Reg);
681 // Unhandled instruction. Halt "fast" selection and bail.
686 FastISel::FastISel(MachineFunction &mf,
687 MachineModuleInfo *mmi,
689 DenseMap<const Value *, unsigned> &vm,
690 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
691 DenseMap<const AllocaInst *, int> &am
693 , SmallSet<Instruction*, 8> &cil
706 MRI(MF.getRegInfo()),
707 MFI(*MF.getFrameInfo()),
708 MCP(*MF.getConstantPool()),
710 TD(*TM.getTargetData()),
711 TII(*TM.getInstrInfo()),
712 TLI(*TM.getTargetLowering()) {
715 FastISel::~FastISel() {}
717 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
722 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
723 ISD::NodeType, unsigned /*Op0*/) {
727 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
728 ISD::NodeType, unsigned /*Op0*/,
733 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
734 ISD::NodeType, uint64_t /*Imm*/) {
738 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
739 ISD::NodeType, ConstantFP * /*FPImm*/) {
743 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
744 ISD::NodeType, unsigned /*Op0*/,
749 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
750 ISD::NodeType, unsigned /*Op0*/,
751 ConstantFP * /*FPImm*/) {
755 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
757 unsigned /*Op0*/, unsigned /*Op1*/,
762 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
763 /// to emit an instruction with an immediate operand using FastEmit_ri.
764 /// If that fails, it materializes the immediate into a register and try
765 /// FastEmit_rr instead.
766 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
767 unsigned Op0, uint64_t Imm,
768 MVT::SimpleValueType ImmType) {
769 // First check if immediate type is legal. If not, we can't use the ri form.
770 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
773 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
774 if (MaterialReg == 0)
776 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
779 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
780 /// to emit an instruction with a floating-point immediate operand using
781 /// FastEmit_rf. If that fails, it materializes the immediate into a register
782 /// and try FastEmit_rr instead.
783 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
784 unsigned Op0, ConstantFP *FPImm,
785 MVT::SimpleValueType ImmType) {
786 // First check if immediate type is legal. If not, we can't use the rf form.
787 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
791 // Materialize the constant in a register.
792 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
793 if (MaterialReg == 0) {
794 // If the target doesn't have a way to directly enter a floating-point
795 // value into a register, use an alternate approach.
796 // TODO: The current approach only supports floating-point constants
797 // that can be constructed by conversion from integer values. This should
798 // be replaced by code that creates a load from a constant-pool entry,
799 // which will require some target-specific work.
800 const APFloat &Flt = FPImm->getValueAPF();
801 MVT IntVT = TLI.getPointerTy();
804 uint32_t IntBitWidth = IntVT.getSizeInBits();
806 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
807 APFloat::rmTowardZero, &isExact);
810 APInt IntVal(IntBitWidth, 2, x);
812 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
813 ISD::Constant, IntVal.getZExtValue());
816 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
817 ISD::SINT_TO_FP, IntegerReg);
818 if (MaterialReg == 0)
821 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
824 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
825 return MRI.createVirtualRegister(RC);
828 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
829 const TargetRegisterClass* RC) {
830 unsigned ResultReg = createResultReg(RC);
831 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
833 BuildMI(MBB, II, ResultReg);
837 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
838 const TargetRegisterClass *RC,
840 unsigned ResultReg = createResultReg(RC);
841 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
843 if (II.getNumDefs() >= 1)
844 BuildMI(MBB, II, ResultReg).addReg(Op0);
846 BuildMI(MBB, II).addReg(Op0);
847 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
848 II.ImplicitDefs[0], RC, RC);
856 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
857 const TargetRegisterClass *RC,
858 unsigned Op0, unsigned Op1) {
859 unsigned ResultReg = createResultReg(RC);
860 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
862 if (II.getNumDefs() >= 1)
863 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
865 BuildMI(MBB, II).addReg(Op0).addReg(Op1);
866 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
867 II.ImplicitDefs[0], RC, RC);
874 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
875 const TargetRegisterClass *RC,
876 unsigned Op0, uint64_t Imm) {
877 unsigned ResultReg = createResultReg(RC);
878 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
880 if (II.getNumDefs() >= 1)
881 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
883 BuildMI(MBB, II).addReg(Op0).addImm(Imm);
884 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
885 II.ImplicitDefs[0], RC, RC);
892 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
893 const TargetRegisterClass *RC,
894 unsigned Op0, ConstantFP *FPImm) {
895 unsigned ResultReg = createResultReg(RC);
896 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
898 if (II.getNumDefs() >= 1)
899 BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
901 BuildMI(MBB, II).addReg(Op0).addFPImm(FPImm);
902 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
903 II.ImplicitDefs[0], RC, RC);
910 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
911 const TargetRegisterClass *RC,
912 unsigned Op0, unsigned Op1, uint64_t Imm) {
913 unsigned ResultReg = createResultReg(RC);
914 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
916 if (II.getNumDefs() >= 1)
917 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
919 BuildMI(MBB, II).addReg(Op0).addReg(Op1).addImm(Imm);
920 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
921 II.ImplicitDefs[0], RC, RC);
928 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
929 const TargetRegisterClass *RC,
931 unsigned ResultReg = createResultReg(RC);
932 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
934 if (II.getNumDefs() >= 1)
935 BuildMI(MBB, II, ResultReg).addImm(Imm);
937 BuildMI(MBB, II).addImm(Imm);
938 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
939 II.ImplicitDefs[0], RC, RC);
946 unsigned FastISel::FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx) {
947 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
948 const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
950 unsigned ResultReg = createResultReg(SRC);
951 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
953 if (II.getNumDefs() >= 1)
954 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Idx);
956 BuildMI(MBB, II).addReg(Op0).addImm(Idx);
957 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
958 II.ImplicitDefs[0], RC, RC);