1 //===-- FastISel.cpp - Implementation of the FastISel class ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/CodeGen/Analysis.h"
43 #include "llvm/ADT/Optional.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Analysis/BranchProbabilityInfo.h"
46 #include "llvm/Analysis/Loads.h"
47 #include "llvm/Analysis/TargetLibraryInfo.h"
48 #include "llvm/CodeGen/Analysis.h"
49 #include "llvm/CodeGen/FastISel.h"
50 #include "llvm/CodeGen/FunctionLoweringInfo.h"
51 #include "llvm/CodeGen/MachineFrameInfo.h"
52 #include "llvm/CodeGen/MachineInstrBuilder.h"
53 #include "llvm/CodeGen/MachineModuleInfo.h"
54 #include "llvm/CodeGen/MachineRegisterInfo.h"
55 #include "llvm/CodeGen/StackMaps.h"
56 #include "llvm/IR/DataLayout.h"
57 #include "llvm/IR/DebugInfo.h"
58 #include "llvm/IR/Function.h"
59 #include "llvm/IR/GlobalVariable.h"
60 #include "llvm/IR/Instructions.h"
61 #include "llvm/IR/IntrinsicInst.h"
62 #include "llvm/IR/Mangler.h"
63 #include "llvm/IR/Operator.h"
64 #include "llvm/Support/Debug.h"
65 #include "llvm/Support/ErrorHandling.h"
66 #include "llvm/Support/raw_ostream.h"
67 #include "llvm/Target/TargetInstrInfo.h"
68 #include "llvm/Target/TargetLowering.h"
69 #include "llvm/Target/TargetMachine.h"
70 #include "llvm/Target/TargetSubtargetInfo.h"
73 #define DEBUG_TYPE "isel"
75 STATISTIC(NumFastIselSuccessIndependent, "Number of insts selected by "
76 "target-independent selector");
77 STATISTIC(NumFastIselSuccessTarget, "Number of insts selected by "
78 "target-specific selector");
79 STATISTIC(NumFastIselDead, "Number of dead insts removed on failure");
81 void FastISel::ArgListEntry::setAttributes(ImmutableCallSite *CS,
83 IsSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt);
84 IsZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
85 IsInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg);
86 IsSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet);
87 IsNest = CS->paramHasAttr(AttrIdx, Attribute::Nest);
88 IsByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal);
89 IsInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca);
90 IsReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned);
91 Alignment = CS->getParamAlignment(AttrIdx);
94 /// Set the current block to which generated machine instructions will be
95 /// appended, and clear the local CSE map.
96 void FastISel::startNewBlock() {
97 LocalValueMap.clear();
99 // Instructions are appended to FuncInfo.MBB. If the basic block already
100 // contains labels or copies, use the last instruction as the last local
102 EmitStartPt = nullptr;
103 if (!FuncInfo.MBB->empty())
104 EmitStartPt = &FuncInfo.MBB->back();
105 LastLocalValue = EmitStartPt;
108 bool FastISel::lowerArguments() {
109 if (!FuncInfo.CanLowerReturn)
110 // Fallback to SDISel argument lowering code to deal with sret pointer
114 if (!fastLowerArguments())
117 // Enter arguments into ValueMap for uses in non-entry BBs.
118 for (Function::const_arg_iterator I = FuncInfo.Fn->arg_begin(),
119 E = FuncInfo.Fn->arg_end();
121 DenseMap<const Value *, unsigned>::iterator VI = LocalValueMap.find(I);
122 assert(VI != LocalValueMap.end() && "Missed an argument?");
123 FuncInfo.ValueMap[I] = VI->second;
128 void FastISel::flushLocalValueMap() {
129 LocalValueMap.clear();
130 LastLocalValue = EmitStartPt;
132 SavedInsertPt = FuncInfo.InsertPt;
135 bool FastISel::hasTrivialKill(const Value *V) {
136 // Don't consider constants or arguments to have trivial kills.
137 const Instruction *I = dyn_cast<Instruction>(V);
141 // No-op casts are trivially coalesced by fast-isel.
142 if (const auto *Cast = dyn_cast<CastInst>(I))
143 if (Cast->isNoopCast(DL.getIntPtrType(Cast->getContext())) &&
144 !hasTrivialKill(Cast->getOperand(0)))
147 // Even the value might have only one use in the LLVM IR, it is possible that
148 // FastISel might fold the use into another instruction and now there is more
149 // than one use at the Machine Instruction level.
150 unsigned Reg = lookUpRegForValue(V);
151 if (Reg && !MRI.use_empty(Reg))
154 // GEPs with all zero indices are trivially coalesced by fast-isel.
155 if (const auto *GEP = dyn_cast<GetElementPtrInst>(I))
156 if (GEP->hasAllZeroIndices() && !hasTrivialKill(GEP->getOperand(0)))
159 // Only instructions with a single use in the same basic block are considered
160 // to have trivial kills.
161 return I->hasOneUse() &&
162 !(I->getOpcode() == Instruction::BitCast ||
163 I->getOpcode() == Instruction::PtrToInt ||
164 I->getOpcode() == Instruction::IntToPtr) &&
165 cast<Instruction>(*I->user_begin())->getParent() == I->getParent();
168 unsigned FastISel::getRegForValue(const Value *V) {
169 EVT RealVT = TLI.getValueType(DL, V->getType(), /*AllowUnknown=*/true);
170 // Don't handle non-simple values in FastISel.
171 if (!RealVT.isSimple())
174 // Ignore illegal types. We must do this before looking up the value
175 // in ValueMap because Arguments are given virtual registers regardless
176 // of whether FastISel can handle them.
177 MVT VT = RealVT.getSimpleVT();
178 if (!TLI.isTypeLegal(VT)) {
179 // Handle integer promotions, though, because they're common and easy.
180 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
181 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
186 // Look up the value to see if we already have a register for it.
187 unsigned Reg = lookUpRegForValue(V);
191 // In bottom-up mode, just create the virtual register which will be used
192 // to hold the value. It will be materialized later.
193 if (isa<Instruction>(V) &&
194 (!isa<AllocaInst>(V) ||
195 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(V))))
196 return FuncInfo.InitializeRegForValue(V);
198 SavePoint SaveInsertPt = enterLocalValueArea();
200 // Materialize the value in a register. Emit any instructions in the
202 Reg = materializeRegForValue(V, VT);
204 leaveLocalValueArea(SaveInsertPt);
209 unsigned FastISel::materializeConstant(const Value *V, MVT VT) {
211 if (const auto *CI = dyn_cast<ConstantInt>(V)) {
212 if (CI->getValue().getActiveBits() <= 64)
213 Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
214 } else if (isa<AllocaInst>(V))
215 Reg = fastMaterializeAlloca(cast<AllocaInst>(V));
216 else if (isa<ConstantPointerNull>(V))
217 // Translate this as an integer zero so that it can be
218 // local-CSE'd with actual integer zeros.
219 Reg = getRegForValue(
220 Constant::getNullValue(DL.getIntPtrType(V->getContext())));
221 else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
222 if (CF->isNullValue())
223 Reg = fastMaterializeFloatZero(CF);
225 // Try to emit the constant directly.
226 Reg = fastEmit_f(VT, VT, ISD::ConstantFP, CF);
229 // Try to emit the constant by using an integer constant with a cast.
230 const APFloat &Flt = CF->getValueAPF();
231 EVT IntVT = TLI.getPointerTy(DL);
234 uint32_t IntBitWidth = IntVT.getSizeInBits();
236 (void)Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
237 APFloat::rmTowardZero, &isExact);
239 APInt IntVal(IntBitWidth, x);
241 unsigned IntegerReg =
242 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
244 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg,
248 } else if (const auto *Op = dyn_cast<Operator>(V)) {
249 if (!selectOperator(Op, Op->getOpcode()))
250 if (!isa<Instruction>(Op) ||
251 !fastSelectInstruction(cast<Instruction>(Op)))
253 Reg = lookUpRegForValue(Op);
254 } else if (isa<UndefValue>(V)) {
255 Reg = createResultReg(TLI.getRegClassFor(VT));
256 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
257 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
262 /// Helper for getRegForValue. This function is called when the value isn't
263 /// already available in a register and must be materialized with new
265 unsigned FastISel::materializeRegForValue(const Value *V, MVT VT) {
267 // Give the target-specific code a try first.
268 if (isa<Constant>(V))
269 Reg = fastMaterializeConstant(cast<Constant>(V));
271 // If target-specific code couldn't or didn't want to handle the value, then
272 // give target-independent code a try.
274 Reg = materializeConstant(V, VT);
276 // Don't cache constant materializations in the general ValueMap.
277 // To do so would require tracking what uses they dominate.
279 LocalValueMap[V] = Reg;
280 LastLocalValue = MRI.getVRegDef(Reg);
285 unsigned FastISel::lookUpRegForValue(const Value *V) {
286 // Look up the value to see if we already have a register for it. We
287 // cache values defined by Instructions across blocks, and other values
288 // only locally. This is because Instructions already have the SSA
289 // def-dominates-use requirement enforced.
290 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(V);
291 if (I != FuncInfo.ValueMap.end())
293 return LocalValueMap[V];
296 void FastISel::updateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) {
297 if (!isa<Instruction>(I)) {
298 LocalValueMap[I] = Reg;
302 unsigned &AssignedReg = FuncInfo.ValueMap[I];
303 if (AssignedReg == 0)
304 // Use the new register.
306 else if (Reg != AssignedReg) {
307 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
308 for (unsigned i = 0; i < NumRegs; i++)
309 FuncInfo.RegFixups[AssignedReg + i] = Reg + i;
315 std::pair<unsigned, bool> FastISel::getRegForGEPIndex(const Value *Idx) {
316 unsigned IdxN = getRegForValue(Idx);
318 // Unhandled operand. Halt "fast" selection and bail.
319 return std::pair<unsigned, bool>(0, false);
321 bool IdxNIsKill = hasTrivialKill(Idx);
323 // If the index is smaller or larger than intptr_t, truncate or extend it.
324 MVT PtrVT = TLI.getPointerTy(DL);
325 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
326 if (IdxVT.bitsLT(PtrVT)) {
327 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN,
330 } else if (IdxVT.bitsGT(PtrVT)) {
332 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN, IdxNIsKill);
335 return std::pair<unsigned, bool>(IdxN, IdxNIsKill);
338 void FastISel::recomputeInsertPt() {
339 if (getLastLocalValue()) {
340 FuncInfo.InsertPt = getLastLocalValue();
341 FuncInfo.MBB = FuncInfo.InsertPt->getParent();
344 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
346 // Now skip past any EH_LABELs, which must remain at the beginning.
347 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
348 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
352 void FastISel::removeDeadCode(MachineBasicBlock::iterator I,
353 MachineBasicBlock::iterator E) {
354 assert(I && E && std::distance(I, E) > 0 && "Invalid iterator!");
356 MachineInstr *Dead = &*I;
358 Dead->eraseFromParent();
364 FastISel::SavePoint FastISel::enterLocalValueArea() {
365 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
366 DebugLoc OldDL = DbgLoc;
369 SavePoint SP = {OldInsertPt, OldDL};
373 void FastISel::leaveLocalValueArea(SavePoint OldInsertPt) {
374 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
375 LastLocalValue = std::prev(FuncInfo.InsertPt);
377 // Restore the previous insert position.
378 FuncInfo.InsertPt = OldInsertPt.InsertPt;
379 DbgLoc = OldInsertPt.DL;
382 bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) {
383 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
384 if (VT == MVT::Other || !VT.isSimple())
385 // Unhandled type. Halt "fast" selection and bail.
388 // We only handle legal types. For example, on x86-32 the instruction
389 // selector contains all of the 64-bit instructions from x86-64,
390 // under the assumption that i64 won't be used if the target doesn't
392 if (!TLI.isTypeLegal(VT)) {
393 // MVT::i1 is special. Allow AND, OR, or XOR because they
394 // don't require additional zeroing, which makes them easy.
395 if (VT == MVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
396 ISDOpcode == ISD::XOR))
397 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
402 // Check if the first operand is a constant, and handle it as "ri". At -O0,
403 // we don't have anything that canonicalizes operand order.
404 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
405 if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
406 unsigned Op1 = getRegForValue(I->getOperand(1));
409 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
412 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, Op1IsKill,
413 CI->getZExtValue(), VT.getSimpleVT());
417 // We successfully emitted code for the given LLVM Instruction.
418 updateValueMap(I, ResultReg);
422 unsigned Op0 = getRegForValue(I->getOperand(0));
423 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
425 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
427 // Check if the second operand is a constant and handle it appropriately.
428 if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
429 uint64_t Imm = CI->getSExtValue();
431 // Transform "sdiv exact X, 8" -> "sra X, 3".
432 if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
433 cast<BinaryOperator>(I)->isExact() && isPowerOf2_64(Imm)) {
435 ISDOpcode = ISD::SRA;
438 // Transform "urem x, pow2" -> "and x, pow2-1".
439 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
440 isPowerOf2_64(Imm)) {
442 ISDOpcode = ISD::AND;
445 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
446 Op0IsKill, Imm, VT.getSimpleVT());
450 // We successfully emitted code for the given LLVM Instruction.
451 updateValueMap(I, ResultReg);
455 // Check if the second operand is a constant float.
456 if (const auto *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
457 unsigned ResultReg = fastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
458 ISDOpcode, Op0, Op0IsKill, CF);
460 // We successfully emitted code for the given LLVM Instruction.
461 updateValueMap(I, ResultReg);
466 unsigned Op1 = getRegForValue(I->getOperand(1));
467 if (!Op1) // Unhandled operand. Halt "fast" selection and bail.
469 bool Op1IsKill = hasTrivialKill(I->getOperand(1));
471 // Now we have both operands in registers. Emit the instruction.
472 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
473 ISDOpcode, Op0, Op0IsKill, Op1, Op1IsKill);
475 // Target-specific code wasn't able to find a machine opcode for
476 // the given ISD opcode and type. Halt "fast" selection and bail.
479 // We successfully emitted code for the given LLVM Instruction.
480 updateValueMap(I, ResultReg);
484 bool FastISel::selectGetElementPtr(const User *I) {
485 unsigned N = getRegForValue(I->getOperand(0));
486 if (!N) // Unhandled operand. Halt "fast" selection and bail.
488 bool NIsKill = hasTrivialKill(I->getOperand(0));
490 // Keep a running tab of the total offset to coalesce multiple N = N + Offset
491 // into a single N = N + TotalOffset.
492 uint64_t TotalOffs = 0;
493 // FIXME: What's a good SWAG number for MaxOffs?
494 uint64_t MaxOffs = 2048;
495 Type *Ty = I->getOperand(0)->getType();
496 MVT VT = TLI.getPointerTy(DL);
497 for (GetElementPtrInst::const_op_iterator OI = I->op_begin() + 1,
500 const Value *Idx = *OI;
501 if (auto *StTy = dyn_cast<StructType>(Ty)) {
502 uint64_t Field = cast<ConstantInt>(Idx)->getZExtValue();
505 TotalOffs += DL.getStructLayout(StTy)->getElementOffset(Field);
506 if (TotalOffs >= MaxOffs) {
507 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
508 if (!N) // Unhandled operand. Halt "fast" selection and bail.
514 Ty = StTy->getElementType(Field);
516 Ty = cast<SequentialType>(Ty)->getElementType();
518 // If this is a constant subscript, handle it quickly.
519 if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
523 uint64_t IdxN = CI->getValue().sextOrTrunc(64).getSExtValue();
524 TotalOffs += DL.getTypeAllocSize(Ty) * IdxN;
525 if (TotalOffs >= MaxOffs) {
526 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
527 if (!N) // Unhandled operand. Halt "fast" selection and bail.
535 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
536 if (!N) // Unhandled operand. Halt "fast" selection and bail.
542 // N = N + Idx * ElementSize;
543 uint64_t ElementSize = DL.getTypeAllocSize(Ty);
544 std::pair<unsigned, bool> Pair = getRegForGEPIndex(Idx);
545 unsigned IdxN = Pair.first;
546 bool IdxNIsKill = Pair.second;
547 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
550 if (ElementSize != 1) {
551 IdxN = fastEmit_ri_(VT, ISD::MUL, IdxN, IdxNIsKill, ElementSize, VT);
552 if (!IdxN) // Unhandled operand. Halt "fast" selection and bail.
556 N = fastEmit_rr(VT, VT, ISD::ADD, N, NIsKill, IdxN, IdxNIsKill);
557 if (!N) // Unhandled operand. Halt "fast" selection and bail.
562 N = fastEmit_ri_(VT, ISD::ADD, N, NIsKill, TotalOffs, VT);
563 if (!N) // Unhandled operand. Halt "fast" selection and bail.
567 // We successfully emitted code for the given LLVM Instruction.
568 updateValueMap(I, N);
572 bool FastISel::addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
573 const CallInst *CI, unsigned StartIdx) {
574 for (unsigned i = StartIdx, e = CI->getNumArgOperands(); i != e; ++i) {
575 Value *Val = CI->getArgOperand(i);
576 // Check for constants and encode them with a StackMaps::ConstantOp prefix.
577 if (const auto *C = dyn_cast<ConstantInt>(Val)) {
578 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
579 Ops.push_back(MachineOperand::CreateImm(C->getSExtValue()));
580 } else if (isa<ConstantPointerNull>(Val)) {
581 Ops.push_back(MachineOperand::CreateImm(StackMaps::ConstantOp));
582 Ops.push_back(MachineOperand::CreateImm(0));
583 } else if (auto *AI = dyn_cast<AllocaInst>(Val)) {
584 // Values coming from a stack location also require a sepcial encoding,
585 // but that is added later on by the target specific frame index
586 // elimination implementation.
587 auto SI = FuncInfo.StaticAllocaMap.find(AI);
588 if (SI != FuncInfo.StaticAllocaMap.end())
589 Ops.push_back(MachineOperand::CreateFI(SI->second));
593 unsigned Reg = getRegForValue(Val);
596 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
602 bool FastISel::selectStackmap(const CallInst *I) {
603 // void @llvm.experimental.stackmap(i64 <id>, i32 <numShadowBytes>,
604 // [live variables...])
605 assert(I->getCalledFunction()->getReturnType()->isVoidTy() &&
606 "Stackmap cannot return a value.");
608 // The stackmap intrinsic only records the live variables (the arguments
609 // passed to it) and emits NOPS (if requested). Unlike the patchpoint
610 // intrinsic, this won't be lowered to a function call. This means we don't
611 // have to worry about calling conventions and target-specific lowering code.
612 // Instead we perform the call lowering right here.
614 // CALLSEQ_START(0...)
615 // STACKMAP(id, nbytes, ...)
618 SmallVector<MachineOperand, 32> Ops;
620 // Add the <id> and <numBytes> constants.
621 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
622 "Expected a constant integer.");
623 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
624 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
626 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
627 "Expected a constant integer.");
628 const auto *NumBytes =
629 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
630 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
632 // Push live variables for the stack map (skipping the first two arguments
633 // <id> and <numBytes>).
634 if (!addStackMapLiveVars(Ops, I, 2))
637 // We are not adding any register mask info here, because the stackmap doesn't
640 // Add scratch registers as implicit def and early clobber.
641 CallingConv::ID CC = I->getCallingConv();
642 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
643 for (unsigned i = 0; ScratchRegs[i]; ++i)
644 Ops.push_back(MachineOperand::CreateReg(
645 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
646 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
648 // Issue CALLSEQ_START
649 unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
651 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown));
652 const MCInstrDesc &MCID = Builder.getInstr()->getDesc();
653 for (unsigned I = 0, E = MCID.getNumOperands(); I < E; ++I)
657 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
658 TII.get(TargetOpcode::STACKMAP));
659 for (auto const &MO : Ops)
663 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
664 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp))
668 // Inform the Frame Information that we have a stackmap in this function.
669 FuncInfo.MF->getFrameInfo()->setHasStackMap();
674 /// \brief Lower an argument list according to the target calling convention.
676 /// This is a helper for lowering intrinsics that follow a target calling
677 /// convention or require stack pointer adjustment. Only a subset of the
678 /// intrinsic's operands need to participate in the calling convention.
679 bool FastISel::lowerCallOperands(const CallInst *CI, unsigned ArgIdx,
680 unsigned NumArgs, const Value *Callee,
681 bool ForceRetVoidTy, CallLoweringInfo &CLI) {
683 Args.reserve(NumArgs);
685 // Populate the argument list.
686 // Attributes for args start at offset 1, after the return attribute.
687 ImmutableCallSite CS(CI);
688 for (unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs, AttrI = ArgIdx + 1;
689 ArgI != ArgE; ++ArgI) {
690 Value *V = CI->getOperand(ArgI);
692 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
696 Entry.Ty = V->getType();
697 Entry.setAttributes(&CS, AttrI);
698 Args.push_back(Entry);
701 Type *RetTy = ForceRetVoidTy ? Type::getVoidTy(CI->getType()->getContext())
703 CLI.setCallee(CI->getCallingConv(), RetTy, Callee, std::move(Args), NumArgs);
705 return lowerCallTo(CLI);
708 FastISel::CallLoweringInfo &FastISel::CallLoweringInfo::setCallee(
709 const DataLayout &DL, MCContext &Ctx, CallingConv::ID CC, Type *ResultTy,
710 const char *Target, ArgListTy &&ArgsList, unsigned FixedArgs) {
711 SmallString<32> MangledName;
712 Mangler::getNameWithPrefix(MangledName, Target, DL);
713 MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);
714 return setCallee(CC, ResultTy, Sym, std::move(ArgsList), FixedArgs);
717 bool FastISel::selectPatchpoint(const CallInst *I) {
718 // void|i64 @llvm.experimental.patchpoint.void|i64(i64 <id>,
723 // [live variables...])
724 CallingConv::ID CC = I->getCallingConv();
725 bool IsAnyRegCC = CC == CallingConv::AnyReg;
726 bool HasDef = !I->getType()->isVoidTy();
727 Value *Callee = I->getOperand(PatchPointOpers::TargetPos)->stripPointerCasts();
729 // Get the real number of arguments participating in the call <numArgs>
730 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos)) &&
731 "Expected a constant integer.");
732 const auto *NumArgsVal =
733 cast<ConstantInt>(I->getOperand(PatchPointOpers::NArgPos));
734 unsigned NumArgs = NumArgsVal->getZExtValue();
736 // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
737 // This includes all meta-operands up to but not including CC.
738 unsigned NumMetaOpers = PatchPointOpers::CCPos;
739 assert(I->getNumArgOperands() >= NumMetaOpers + NumArgs &&
740 "Not enough arguments provided to the patchpoint intrinsic");
742 // For AnyRegCC the arguments are lowered later on manually.
743 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
744 CallLoweringInfo CLI;
745 CLI.setIsPatchPoint();
746 if (!lowerCallOperands(I, NumMetaOpers, NumCallArgs, Callee, IsAnyRegCC, CLI))
749 assert(CLI.Call && "No call instruction specified.");
751 SmallVector<MachineOperand, 32> Ops;
753 // Add an explicit result reg if we use the anyreg calling convention.
754 if (IsAnyRegCC && HasDef) {
755 assert(CLI.NumResultRegs == 0 && "Unexpected result register.");
756 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
757 CLI.NumResultRegs = 1;
758 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true));
761 // Add the <id> and <numBytes> constants.
762 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
763 "Expected a constant integer.");
764 const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
765 Ops.push_back(MachineOperand::CreateImm(ID->getZExtValue()));
767 assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos)) &&
768 "Expected a constant integer.");
769 const auto *NumBytes =
770 cast<ConstantInt>(I->getOperand(PatchPointOpers::NBytesPos));
771 Ops.push_back(MachineOperand::CreateImm(NumBytes->getZExtValue()));
773 // Add the call target.
774 if (const auto *C = dyn_cast<IntToPtrInst>(Callee)) {
775 uint64_t CalleeConstAddr =
776 cast<ConstantInt>(C->getOperand(0))->getZExtValue();
777 Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
778 } else if (const auto *C = dyn_cast<ConstantExpr>(Callee)) {
779 if (C->getOpcode() == Instruction::IntToPtr) {
780 uint64_t CalleeConstAddr =
781 cast<ConstantInt>(C->getOperand(0))->getZExtValue();
782 Ops.push_back(MachineOperand::CreateImm(CalleeConstAddr));
784 llvm_unreachable("Unsupported ConstantExpr.");
785 } else if (const auto *GV = dyn_cast<GlobalValue>(Callee)) {
786 Ops.push_back(MachineOperand::CreateGA(GV, 0));
787 } else if (isa<ConstantPointerNull>(Callee))
788 Ops.push_back(MachineOperand::CreateImm(0));
790 llvm_unreachable("Unsupported callee address.");
792 // Adjust <numArgs> to account for any arguments that have been passed on
793 // the stack instead.
794 unsigned NumCallRegArgs = IsAnyRegCC ? NumArgs : CLI.OutRegs.size();
795 Ops.push_back(MachineOperand::CreateImm(NumCallRegArgs));
797 // Add the calling convention
798 Ops.push_back(MachineOperand::CreateImm((unsigned)CC));
800 // Add the arguments we omitted previously. The register allocator should
801 // place these in any free register.
803 for (unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i != e; ++i) {
804 unsigned Reg = getRegForValue(I->getArgOperand(i));
807 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
811 // Push the arguments from the call instruction.
812 for (auto Reg : CLI.OutRegs)
813 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false));
815 // Push live variables for the stack map.
816 if (!addStackMapLiveVars(Ops, I, NumMetaOpers + NumArgs))
819 // Push the register mask info.
820 Ops.push_back(MachineOperand::CreateRegMask(
821 TRI.getCallPreservedMask(*FuncInfo.MF, CC)));
823 // Add scratch registers as implicit def and early clobber.
824 const MCPhysReg *ScratchRegs = TLI.getScratchRegisters(CC);
825 for (unsigned i = 0; ScratchRegs[i]; ++i)
826 Ops.push_back(MachineOperand::CreateReg(
827 ScratchRegs[i], /*IsDef=*/true, /*IsImp=*/true, /*IsKill=*/false,
828 /*IsDead=*/false, /*IsUndef=*/false, /*IsEarlyClobber=*/true));
830 // Add implicit defs (return values).
831 for (auto Reg : CLI.InRegs)
832 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/true,
835 // Insert the patchpoint instruction before the call generated by the target.
836 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, CLI.Call, DbgLoc,
837 TII.get(TargetOpcode::PATCHPOINT));
842 MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);
844 // Delete the original call instruction.
845 CLI.Call->eraseFromParent();
847 // Inform the Frame Information that we have a patchpoint in this function.
848 FuncInfo.MF->getFrameInfo()->setHasPatchPoint();
850 if (CLI.NumResultRegs)
851 updateValueMap(I, CLI.ResultReg, CLI.NumResultRegs);
855 /// Returns an AttributeSet representing the attributes applied to the return
856 /// value of the given call.
857 static AttributeSet getReturnAttrs(FastISel::CallLoweringInfo &CLI) {
858 SmallVector<Attribute::AttrKind, 2> Attrs;
860 Attrs.push_back(Attribute::SExt);
862 Attrs.push_back(Attribute::ZExt);
864 Attrs.push_back(Attribute::InReg);
866 return AttributeSet::get(CLI.RetTy->getContext(), AttributeSet::ReturnIndex,
870 bool FastISel::lowerCallTo(const CallInst *CI, const char *SymName,
872 MCContext &Ctx = MF->getContext();
873 SmallString<32> MangledName;
874 Mangler::getNameWithPrefix(MangledName, SymName, DL);
875 MCSymbol *Sym = Ctx.getOrCreateSymbol(MangledName);
876 return lowerCallTo(CI, Sym, NumArgs);
879 bool FastISel::lowerCallTo(const CallInst *CI, MCSymbol *Symbol,
881 ImmutableCallSite CS(CI);
883 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
884 FunctionType *FTy = cast<FunctionType>(PT->getElementType());
885 Type *RetTy = FTy->getReturnType();
888 Args.reserve(NumArgs);
890 // Populate the argument list.
891 // Attributes for args start at offset 1, after the return attribute.
892 for (unsigned ArgI = 0; ArgI != NumArgs; ++ArgI) {
893 Value *V = CI->getOperand(ArgI);
895 assert(!V->getType()->isEmptyTy() && "Empty type passed to intrinsic.");
899 Entry.Ty = V->getType();
900 Entry.setAttributes(&CS, ArgI + 1);
901 Args.push_back(Entry);
904 CallLoweringInfo CLI;
905 CLI.setCallee(RetTy, FTy, Symbol, std::move(Args), CS, NumArgs);
907 return lowerCallTo(CLI);
910 bool FastISel::lowerCallTo(CallLoweringInfo &CLI) {
911 // Handle the incoming return values from the call.
913 SmallVector<EVT, 4> RetTys;
914 ComputeValueVTs(TLI, DL, CLI.RetTy, RetTys);
916 SmallVector<ISD::OutputArg, 4> Outs;
917 GetReturnInfo(CLI.RetTy, getReturnAttrs(CLI), Outs, TLI, DL);
919 bool CanLowerReturn = TLI.CanLowerReturn(
920 CLI.CallConv, *FuncInfo.MF, CLI.IsVarArg, Outs, CLI.RetTy->getContext());
922 // FIXME: sret demotion isn't supported yet - bail out.
926 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
928 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT);
929 unsigned NumRegs = TLI.getNumRegisters(CLI.RetTy->getContext(), VT);
930 for (unsigned i = 0; i != NumRegs; ++i) {
931 ISD::InputArg MyFlags;
932 MyFlags.VT = RegisterVT;
934 MyFlags.Used = CLI.IsReturnValueUsed;
936 MyFlags.Flags.setSExt();
938 MyFlags.Flags.setZExt();
940 MyFlags.Flags.setInReg();
941 CLI.Ins.push_back(MyFlags);
945 // Handle all of the outgoing arguments.
947 for (auto &Arg : CLI.getArgs()) {
948 Type *FinalType = Arg.Ty;
950 FinalType = cast<PointerType>(Arg.Ty)->getElementType();
951 bool NeedsRegBlock = TLI.functionArgumentNeedsConsecutiveRegisters(
952 FinalType, CLI.CallConv, CLI.IsVarArg);
954 ISD::ArgFlagsTy Flags;
965 if (Arg.IsInAlloca) {
967 // Set the byval flag for CCAssignFn callbacks that don't know about
968 // inalloca. This way we can know how many bytes we should've allocated
969 // and how many bytes a callee cleanup function will pop. If we port
970 // inalloca to more targets, we'll have to add custom inalloca handling in
971 // the various CC lowering callbacks.
974 if (Arg.IsByVal || Arg.IsInAlloca) {
975 PointerType *Ty = cast<PointerType>(Arg.Ty);
976 Type *ElementTy = Ty->getElementType();
977 unsigned FrameSize = DL.getTypeAllocSize(ElementTy);
978 // For ByVal, alignment should come from FE. BE will guess if this info is
979 // not there, but there are cases it cannot get right.
980 unsigned FrameAlign = Arg.Alignment;
982 FrameAlign = TLI.getByValTypeAlignment(ElementTy, DL);
983 Flags.setByValSize(FrameSize);
984 Flags.setByValAlign(FrameAlign);
989 Flags.setInConsecutiveRegs();
990 unsigned OriginalAlignment = DL.getABITypeAlignment(Arg.Ty);
991 Flags.setOrigAlign(OriginalAlignment);
993 CLI.OutVals.push_back(Arg.Val);
994 CLI.OutFlags.push_back(Flags);
997 if (!fastLowerCall(CLI))
1000 // Set all unused physreg defs as dead.
1001 assert(CLI.Call && "No call instruction specified.");
1002 CLI.Call->setPhysRegsDeadExcept(CLI.InRegs, TRI);
1004 if (CLI.NumResultRegs && CLI.CS)
1005 updateValueMap(CLI.CS->getInstruction(), CLI.ResultReg, CLI.NumResultRegs);
1010 bool FastISel::lowerCall(const CallInst *CI) {
1011 ImmutableCallSite CS(CI);
1013 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1014 FunctionType *FuncTy = cast<FunctionType>(PT->getElementType());
1015 Type *RetTy = FuncTy->getReturnType();
1019 Args.reserve(CS.arg_size());
1021 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1026 if (V->getType()->isEmptyTy())
1030 Entry.Ty = V->getType();
1032 // Skip the first return-type Attribute to get to params.
1033 Entry.setAttributes(&CS, i - CS.arg_begin() + 1);
1034 Args.push_back(Entry);
1037 // Check if target-independent constraints permit a tail call here.
1038 // Target-dependent constraints are checked within fastLowerCall.
1039 bool IsTailCall = CI->isTailCall();
1040 if (IsTailCall && !isInTailCallPosition(CS, TM))
1043 CallLoweringInfo CLI;
1044 CLI.setCallee(RetTy, FuncTy, CI->getCalledValue(), std::move(Args), CS)
1045 .setTailCall(IsTailCall);
1047 return lowerCallTo(CLI);
1050 bool FastISel::selectCall(const User *I) {
1051 const CallInst *Call = cast<CallInst>(I);
1053 // Handle simple inline asms.
1054 if (const InlineAsm *IA = dyn_cast<InlineAsm>(Call->getCalledValue())) {
1055 // If the inline asm has side effects, then make sure that no local value
1056 // lives across by flushing the local value map.
1057 if (IA->hasSideEffects())
1058 flushLocalValueMap();
1060 // Don't attempt to handle constraints.
1061 if (!IA->getConstraintString().empty())
1064 unsigned ExtraInfo = 0;
1065 if (IA->hasSideEffects())
1066 ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1067 if (IA->isAlignStack())
1068 ExtraInfo |= InlineAsm::Extra_IsAlignStack;
1070 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1071 TII.get(TargetOpcode::INLINEASM))
1072 .addExternalSymbol(IA->getAsmString().c_str())
1077 MachineModuleInfo &MMI = FuncInfo.MF->getMMI();
1078 ComputeUsesVAFloatArgument(*Call, &MMI);
1080 // Handle intrinsic function calls.
1081 if (const auto *II = dyn_cast<IntrinsicInst>(Call))
1082 return selectIntrinsicCall(II);
1084 // Usually, it does not make sense to initialize a value,
1085 // make an unrelated function call and use the value, because
1086 // it tends to be spilled on the stack. So, we move the pointer
1087 // to the last local value to the beginning of the block, so that
1088 // all the values which have already been materialized,
1089 // appear after the call. It also makes sense to skip intrinsics
1090 // since they tend to be inlined.
1091 flushLocalValueMap();
1093 return lowerCall(Call);
1096 bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
1097 switch (II->getIntrinsicID()) {
1100 // At -O0 we don't care about the lifetime intrinsics.
1101 case Intrinsic::lifetime_start:
1102 case Intrinsic::lifetime_end:
1103 // The donothing intrinsic does, well, nothing.
1104 case Intrinsic::donothing:
1106 case Intrinsic::eh_actions: {
1107 unsigned ResultReg = getRegForValue(UndefValue::get(II->getType()));
1110 updateValueMap(II, ResultReg);
1113 case Intrinsic::dbg_declare: {
1114 const DbgDeclareInst *DI = cast<DbgDeclareInst>(II);
1115 assert(DI->getVariable() && "Missing variable");
1116 if (!FuncInfo.MF->getMMI().hasDebugInfo()) {
1117 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1121 const Value *Address = DI->getAddress();
1122 if (!Address || isa<UndefValue>(Address)) {
1123 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1127 unsigned Offset = 0;
1128 Optional<MachineOperand> Op;
1129 if (const auto *Arg = dyn_cast<Argument>(Address))
1130 // Some arguments' frame index is recorded during argument lowering.
1131 Offset = FuncInfo.getArgumentFrameIndex(Arg);
1133 Op = MachineOperand::CreateFI(Offset);
1135 if (unsigned Reg = lookUpRegForValue(Address))
1136 Op = MachineOperand::CreateReg(Reg, false);
1138 // If we have a VLA that has a "use" in a metadata node that's then used
1139 // here but it has no other uses, then we have a problem. E.g.,
1141 // int foo (const int *x) {
1146 // If we assign 'a' a vreg and fast isel later on has to use the selection
1147 // DAG isel, it will want to copy the value to the vreg. However, there are
1148 // no uses, which goes counter to what selection DAG isel expects.
1149 if (!Op && !Address->use_empty() && isa<Instruction>(Address) &&
1150 (!isa<AllocaInst>(Address) ||
1151 !FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(Address))))
1152 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address),
1156 assert(DI->getVariable()->isValidLocationForIntrinsic(DbgLoc) &&
1157 "Expected inlined-at fields to agree");
1159 Op->setIsDebug(true);
1160 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1161 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0,
1162 DI->getVariable(), DI->getExpression());
1164 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1165 TII.get(TargetOpcode::DBG_VALUE))
1168 .addMetadata(DI->getVariable())
1169 .addMetadata(DI->getExpression());
1171 // We can't yet handle anything else here because it would require
1172 // generating code, thus altering codegen because of debug info.
1173 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1177 case Intrinsic::dbg_value: {
1178 // This form of DBG_VALUE is target-independent.
1179 const DbgValueInst *DI = cast<DbgValueInst>(II);
1180 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
1181 const Value *V = DI->getValue();
1182 assert(DI->getVariable()->isValidLocationForIntrinsic(DbgLoc) &&
1183 "Expected inlined-at fields to agree");
1185 // Currently the optimizer can produce this; insert an undef to
1186 // help debugging. Probably the optimizer should not do this.
1187 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1189 .addImm(DI->getOffset())
1190 .addMetadata(DI->getVariable())
1191 .addMetadata(DI->getExpression());
1192 } else if (const auto *CI = dyn_cast<ConstantInt>(V)) {
1193 if (CI->getBitWidth() > 64)
1194 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1196 .addImm(DI->getOffset())
1197 .addMetadata(DI->getVariable())
1198 .addMetadata(DI->getExpression());
1200 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1201 .addImm(CI->getZExtValue())
1202 .addImm(DI->getOffset())
1203 .addMetadata(DI->getVariable())
1204 .addMetadata(DI->getExpression());
1205 } else if (const auto *CF = dyn_cast<ConstantFP>(V)) {
1206 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1208 .addImm(DI->getOffset())
1209 .addMetadata(DI->getVariable())
1210 .addMetadata(DI->getExpression());
1211 } else if (unsigned Reg = lookUpRegForValue(V)) {
1212 // FIXME: This does not handle register-indirect values at offset 0.
1213 bool IsIndirect = DI->getOffset() != 0;
1214 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, IsIndirect, Reg,
1215 DI->getOffset(), DI->getVariable(), DI->getExpression());
1217 // We can't yet handle anything else here because it would require
1218 // generating code, thus altering codegen because of debug info.
1219 DEBUG(dbgs() << "Dropping debug info for " << *DI << "\n");
1223 case Intrinsic::objectsize: {
1224 ConstantInt *CI = cast<ConstantInt>(II->getArgOperand(1));
1225 unsigned long long Res = CI->isZero() ? -1ULL : 0;
1226 Constant *ResCI = ConstantInt::get(II->getType(), Res);
1227 unsigned ResultReg = getRegForValue(ResCI);
1230 updateValueMap(II, ResultReg);
1233 case Intrinsic::expect: {
1234 unsigned ResultReg = getRegForValue(II->getArgOperand(0));
1237 updateValueMap(II, ResultReg);
1240 case Intrinsic::experimental_stackmap:
1241 return selectStackmap(II);
1242 case Intrinsic::experimental_patchpoint_void:
1243 case Intrinsic::experimental_patchpoint_i64:
1244 return selectPatchpoint(II);
1247 return fastLowerIntrinsicCall(II);
1250 bool FastISel::selectCast(const User *I, unsigned Opcode) {
1251 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1252 EVT DstVT = TLI.getValueType(DL, I->getType());
1254 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other ||
1256 // Unhandled type. Halt "fast" selection and bail.
1259 // Check if the destination type is legal.
1260 if (!TLI.isTypeLegal(DstVT))
1263 // Check if the source operand is legal.
1264 if (!TLI.isTypeLegal(SrcVT))
1267 unsigned InputReg = getRegForValue(I->getOperand(0));
1269 // Unhandled operand. Halt "fast" selection and bail.
1272 bool InputRegIsKill = hasTrivialKill(I->getOperand(0));
1274 unsigned ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
1275 Opcode, InputReg, InputRegIsKill);
1279 updateValueMap(I, ResultReg);
1283 bool FastISel::selectBitCast(const User *I) {
1284 // If the bitcast doesn't change the type, just use the operand value.
1285 if (I->getType() == I->getOperand(0)->getType()) {
1286 unsigned Reg = getRegForValue(I->getOperand(0));
1289 updateValueMap(I, Reg);
1293 // Bitcasts of other values become reg-reg copies or BITCAST operators.
1294 EVT SrcEVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1295 EVT DstEVT = TLI.getValueType(DL, I->getType());
1296 if (SrcEVT == MVT::Other || DstEVT == MVT::Other ||
1297 !TLI.isTypeLegal(SrcEVT) || !TLI.isTypeLegal(DstEVT))
1298 // Unhandled type. Halt "fast" selection and bail.
1301 MVT SrcVT = SrcEVT.getSimpleVT();
1302 MVT DstVT = DstEVT.getSimpleVT();
1303 unsigned Op0 = getRegForValue(I->getOperand(0));
1304 if (!Op0) // Unhandled operand. Halt "fast" selection and bail.
1306 bool Op0IsKill = hasTrivialKill(I->getOperand(0));
1308 // First, try to perform the bitcast by inserting a reg-reg copy.
1309 unsigned ResultReg = 0;
1310 if (SrcVT == DstVT) {
1311 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1312 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
1313 // Don't attempt a cross-class copy. It will likely fail.
1314 if (SrcClass == DstClass) {
1315 ResultReg = createResultReg(DstClass);
1316 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1317 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
1321 // If the reg-reg copy failed, select a BITCAST opcode.
1323 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0, Op0IsKill);
1328 updateValueMap(I, ResultReg);
1332 bool FastISel::selectInstruction(const Instruction *I) {
1333 // Just before the terminator instruction, insert instructions to
1334 // feed PHI nodes in successor blocks.
1335 if (isa<TerminatorInst>(I))
1336 if (!handlePHINodesInSuccessorBlocks(I->getParent()))
1339 DbgLoc = I->getDebugLoc();
1341 SavedInsertPt = FuncInfo.InsertPt;
1343 if (const auto *Call = dyn_cast<CallInst>(I)) {
1344 const Function *F = Call->getCalledFunction();
1347 // As a special case, don't handle calls to builtin library functions that
1348 // may be translated directly to target instructions.
1349 if (F && !F->hasLocalLinkage() && F->hasName() &&
1350 LibInfo->getLibFunc(F->getName(), Func) &&
1351 LibInfo->hasOptimizedCodeGen(Func))
1354 // Don't handle Intrinsic::trap if a trap funciton is specified.
1355 if (F && F->getIntrinsicID() == Intrinsic::trap &&
1356 Call->hasFnAttr("trap-func-name"))
1360 // First, try doing target-independent selection.
1361 if (!SkipTargetIndependentISel) {
1362 if (selectOperator(I, I->getOpcode())) {
1363 ++NumFastIselSuccessIndependent;
1364 DbgLoc = DebugLoc();
1367 // Remove dead code.
1368 recomputeInsertPt();
1369 if (SavedInsertPt != FuncInfo.InsertPt)
1370 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1371 SavedInsertPt = FuncInfo.InsertPt;
1373 // Next, try calling the target to attempt to handle the instruction.
1374 if (fastSelectInstruction(I)) {
1375 ++NumFastIselSuccessTarget;
1376 DbgLoc = DebugLoc();
1379 // Remove dead code.
1380 recomputeInsertPt();
1381 if (SavedInsertPt != FuncInfo.InsertPt)
1382 removeDeadCode(FuncInfo.InsertPt, SavedInsertPt);
1384 DbgLoc = DebugLoc();
1385 // Undo phi node updates, because they will be added again by SelectionDAG.
1386 if (isa<TerminatorInst>(I))
1387 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
1391 /// Emit an unconditional branch to the given block, unless it is the immediate
1392 /// (fall-through) successor, and update the CFG.
1393 void FastISel::fastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DbgLoc) {
1394 if (FuncInfo.MBB->getBasicBlock()->size() > 1 &&
1395 FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
1396 // For more accurate line information if this is the only instruction
1397 // in the block then emit it, otherwise we have the unconditional
1398 // fall-through case, which needs no instructions.
1400 // The unconditional branch case.
1401 TII.InsertBranch(*FuncInfo.MBB, MSucc, nullptr,
1402 SmallVector<MachineOperand, 0>(), DbgLoc);
1404 uint32_t BranchWeight = 0;
1406 BranchWeight = FuncInfo.BPI->getEdgeWeight(FuncInfo.MBB->getBasicBlock(),
1407 MSucc->getBasicBlock());
1408 FuncInfo.MBB->addSuccessor(MSucc, BranchWeight);
1411 /// Emit an FNeg operation.
1412 bool FastISel::selectFNeg(const User *I) {
1413 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
1416 bool OpRegIsKill = hasTrivialKill(I);
1418 // If the target has ISD::FNEG, use it.
1419 EVT VT = TLI.getValueType(DL, I->getType());
1420 unsigned ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG,
1421 OpReg, OpRegIsKill);
1423 updateValueMap(I, ResultReg);
1427 // Bitcast the value to integer, twiddle the sign bit with xor,
1428 // and then bitcast it back to floating-point.
1429 if (VT.getSizeInBits() > 64)
1431 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
1432 if (!TLI.isTypeLegal(IntVT))
1435 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
1436 ISD::BITCAST, OpReg, OpRegIsKill);
1440 unsigned IntResultReg = fastEmit_ri_(
1441 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true,
1442 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT());
1446 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST,
1447 IntResultReg, /*IsKill=*/true);
1451 updateValueMap(I, ResultReg);
1455 bool FastISel::selectExtractValue(const User *U) {
1456 const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(U);
1460 // Make sure we only try to handle extracts with a legal result. But also
1461 // allow i1 because it's easy.
1462 EVT RealVT = TLI.getValueType(DL, EVI->getType(), /*AllowUnknown=*/true);
1463 if (!RealVT.isSimple())
1465 MVT VT = RealVT.getSimpleVT();
1466 if (!TLI.isTypeLegal(VT) && VT != MVT::i1)
1469 const Value *Op0 = EVI->getOperand(0);
1470 Type *AggTy = Op0->getType();
1472 // Get the base result register.
1474 DenseMap<const Value *, unsigned>::iterator I = FuncInfo.ValueMap.find(Op0);
1475 if (I != FuncInfo.ValueMap.end())
1476 ResultReg = I->second;
1477 else if (isa<Instruction>(Op0))
1478 ResultReg = FuncInfo.InitializeRegForValue(Op0);
1480 return false; // fast-isel can't handle aggregate constants at the moment
1482 // Get the actual result register, which is an offset from the base register.
1483 unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->getIndices());
1485 SmallVector<EVT, 4> AggValueVTs;
1486 ComputeValueVTs(TLI, DL, AggTy, AggValueVTs);
1488 for (unsigned i = 0; i < VTIndex; i++)
1489 ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]);
1491 updateValueMap(EVI, ResultReg);
1495 bool FastISel::selectOperator(const User *I, unsigned Opcode) {
1497 case Instruction::Add:
1498 return selectBinaryOp(I, ISD::ADD);
1499 case Instruction::FAdd:
1500 return selectBinaryOp(I, ISD::FADD);
1501 case Instruction::Sub:
1502 return selectBinaryOp(I, ISD::SUB);
1503 case Instruction::FSub:
1504 // FNeg is currently represented in LLVM IR as a special case of FSub.
1505 if (BinaryOperator::isFNeg(I))
1506 return selectFNeg(I);
1507 return selectBinaryOp(I, ISD::FSUB);
1508 case Instruction::Mul:
1509 return selectBinaryOp(I, ISD::MUL);
1510 case Instruction::FMul:
1511 return selectBinaryOp(I, ISD::FMUL);
1512 case Instruction::SDiv:
1513 return selectBinaryOp(I, ISD::SDIV);
1514 case Instruction::UDiv:
1515 return selectBinaryOp(I, ISD::UDIV);
1516 case Instruction::FDiv:
1517 return selectBinaryOp(I, ISD::FDIV);
1518 case Instruction::SRem:
1519 return selectBinaryOp(I, ISD::SREM);
1520 case Instruction::URem:
1521 return selectBinaryOp(I, ISD::UREM);
1522 case Instruction::FRem:
1523 return selectBinaryOp(I, ISD::FREM);
1524 case Instruction::Shl:
1525 return selectBinaryOp(I, ISD::SHL);
1526 case Instruction::LShr:
1527 return selectBinaryOp(I, ISD::SRL);
1528 case Instruction::AShr:
1529 return selectBinaryOp(I, ISD::SRA);
1530 case Instruction::And:
1531 return selectBinaryOp(I, ISD::AND);
1532 case Instruction::Or:
1533 return selectBinaryOp(I, ISD::OR);
1534 case Instruction::Xor:
1535 return selectBinaryOp(I, ISD::XOR);
1537 case Instruction::GetElementPtr:
1538 return selectGetElementPtr(I);
1540 case Instruction::Br: {
1541 const BranchInst *BI = cast<BranchInst>(I);
1543 if (BI->isUnconditional()) {
1544 const BasicBlock *LLVMSucc = BI->getSuccessor(0);
1545 MachineBasicBlock *MSucc = FuncInfo.MBBMap[LLVMSucc];
1546 fastEmitBranch(MSucc, BI->getDebugLoc());
1550 // Conditional branches are not handed yet.
1551 // Halt "fast" selection and bail.
1555 case Instruction::Unreachable:
1556 if (TM.Options.TrapUnreachable)
1557 return fastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
1561 case Instruction::Alloca:
1562 // FunctionLowering has the static-sized case covered.
1563 if (FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(I)))
1566 // Dynamic-sized alloca is not handled yet.
1569 case Instruction::Call:
1570 return selectCall(I);
1572 case Instruction::BitCast:
1573 return selectBitCast(I);
1575 case Instruction::FPToSI:
1576 return selectCast(I, ISD::FP_TO_SINT);
1577 case Instruction::ZExt:
1578 return selectCast(I, ISD::ZERO_EXTEND);
1579 case Instruction::SExt:
1580 return selectCast(I, ISD::SIGN_EXTEND);
1581 case Instruction::Trunc:
1582 return selectCast(I, ISD::TRUNCATE);
1583 case Instruction::SIToFP:
1584 return selectCast(I, ISD::SINT_TO_FP);
1586 case Instruction::IntToPtr: // Deliberate fall-through.
1587 case Instruction::PtrToInt: {
1588 EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType());
1589 EVT DstVT = TLI.getValueType(DL, I->getType());
1590 if (DstVT.bitsGT(SrcVT))
1591 return selectCast(I, ISD::ZERO_EXTEND);
1592 if (DstVT.bitsLT(SrcVT))
1593 return selectCast(I, ISD::TRUNCATE);
1594 unsigned Reg = getRegForValue(I->getOperand(0));
1597 updateValueMap(I, Reg);
1601 case Instruction::ExtractValue:
1602 return selectExtractValue(I);
1604 case Instruction::PHI:
1605 llvm_unreachable("FastISel shouldn't visit PHI nodes!");
1608 // Unhandled instruction. Halt "fast" selection and bail.
1613 FastISel::FastISel(FunctionLoweringInfo &FuncInfo,
1614 const TargetLibraryInfo *LibInfo,
1615 bool SkipTargetIndependentISel)
1616 : FuncInfo(FuncInfo), MF(FuncInfo.MF), MRI(FuncInfo.MF->getRegInfo()),
1617 MFI(*FuncInfo.MF->getFrameInfo()), MCP(*FuncInfo.MF->getConstantPool()),
1618 TM(FuncInfo.MF->getTarget()), DL(MF->getDataLayout()),
1619 TII(*MF->getSubtarget().getInstrInfo()),
1620 TLI(*MF->getSubtarget().getTargetLowering()),
1621 TRI(*MF->getSubtarget().getRegisterInfo()), LibInfo(LibInfo),
1622 SkipTargetIndependentISel(SkipTargetIndependentISel) {}
1624 FastISel::~FastISel() {}
1626 bool FastISel::fastLowerArguments() { return false; }
1628 bool FastISel::fastLowerCall(CallLoweringInfo & /*CLI*/) { return false; }
1630 bool FastISel::fastLowerIntrinsicCall(const IntrinsicInst * /*II*/) {
1634 unsigned FastISel::fastEmit_(MVT, MVT, unsigned) { return 0; }
1636 unsigned FastISel::fastEmit_r(MVT, MVT, unsigned, unsigned /*Op0*/,
1637 bool /*Op0IsKill*/) {
1641 unsigned FastISel::fastEmit_rr(MVT, MVT, unsigned, unsigned /*Op0*/,
1642 bool /*Op0IsKill*/, unsigned /*Op1*/,
1643 bool /*Op1IsKill*/) {
1647 unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1651 unsigned FastISel::fastEmit_f(MVT, MVT, unsigned,
1652 const ConstantFP * /*FPImm*/) {
1656 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
1657 bool /*Op0IsKill*/, uint64_t /*Imm*/) {
1661 unsigned FastISel::fastEmit_rf(MVT, MVT, unsigned, unsigned /*Op0*/,
1663 const ConstantFP * /*FPImm*/) {
1667 unsigned FastISel::fastEmit_rri(MVT, MVT, unsigned, unsigned /*Op0*/,
1668 bool /*Op0IsKill*/, unsigned /*Op1*/,
1669 bool /*Op1IsKill*/, uint64_t /*Imm*/) {
1673 /// This method is a wrapper of fastEmit_ri. It first tries to emit an
1674 /// instruction with an immediate operand using fastEmit_ri.
1675 /// If that fails, it materializes the immediate into a register and try
1676 /// fastEmit_rr instead.
1677 unsigned FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
1678 bool Op0IsKill, uint64_t Imm, MVT ImmType) {
1679 // If this is a multiply by a power of two, emit this as a shift left.
1680 if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
1683 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) {
1684 // div x, 8 -> srl x, 3
1689 // Horrible hack (to be removed), check to make sure shift amounts are
1691 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
1692 Imm >= VT.getSizeInBits())
1695 // First check if immediate type is legal. If not, we can't use the ri form.
1696 unsigned ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Op0IsKill, Imm);
1699 unsigned MaterialReg = fastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
1700 bool IsImmKill = true;
1702 // This is a bit ugly/slow, but failing here means falling out of
1703 // fast-isel, which would be very slow.
1705 IntegerType::get(FuncInfo.Fn->getContext(), VT.getSizeInBits());
1706 MaterialReg = getRegForValue(ConstantInt::get(ITy, Imm));
1709 // FIXME: If the materialized register here has no uses yet then this
1710 // will be the first use and we should be able to mark it as killed.
1711 // However, the local value area for materialising constant expressions
1712 // grows down, not up, which means that any constant expressions we generate
1713 // later which also use 'Imm' could be after this instruction and therefore
1717 return fastEmit_rr(VT, VT, Opcode, Op0, Op0IsKill, MaterialReg, IsImmKill);
1720 unsigned FastISel::createResultReg(const TargetRegisterClass *RC) {
1721 return MRI.createVirtualRegister(RC);
1724 unsigned FastISel::constrainOperandRegClass(const MCInstrDesc &II, unsigned Op,
1726 if (TargetRegisterInfo::isVirtualRegister(Op)) {
1727 const TargetRegisterClass *RegClass =
1728 TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
1729 if (!MRI.constrainRegClass(Op, RegClass)) {
1730 // If it's not legal to COPY between the register classes, something
1731 // has gone very wrong before we got here.
1732 unsigned NewOp = createResultReg(RegClass);
1733 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1734 TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
1741 unsigned FastISel::fastEmitInst_(unsigned MachineInstOpcode,
1742 const TargetRegisterClass *RC) {
1743 unsigned ResultReg = createResultReg(RC);
1744 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1746 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
1750 unsigned FastISel::fastEmitInst_r(unsigned MachineInstOpcode,
1751 const TargetRegisterClass *RC, unsigned Op0,
1753 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1755 unsigned ResultReg = createResultReg(RC);
1756 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1758 if (II.getNumDefs() >= 1)
1759 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1760 .addReg(Op0, getKillRegState(Op0IsKill));
1762 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1763 .addReg(Op0, getKillRegState(Op0IsKill));
1764 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1765 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1771 unsigned FastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1772 const TargetRegisterClass *RC, unsigned Op0,
1773 bool Op0IsKill, unsigned Op1,
1775 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1777 unsigned ResultReg = createResultReg(RC);
1778 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1779 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1781 if (II.getNumDefs() >= 1)
1782 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1783 .addReg(Op0, getKillRegState(Op0IsKill))
1784 .addReg(Op1, getKillRegState(Op1IsKill));
1786 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1787 .addReg(Op0, getKillRegState(Op0IsKill))
1788 .addReg(Op1, getKillRegState(Op1IsKill));
1789 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1790 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1795 unsigned FastISel::fastEmitInst_rrr(unsigned MachineInstOpcode,
1796 const TargetRegisterClass *RC, unsigned Op0,
1797 bool Op0IsKill, unsigned Op1,
1798 bool Op1IsKill, unsigned Op2,
1800 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1802 unsigned ResultReg = createResultReg(RC);
1803 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1804 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1805 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2);
1807 if (II.getNumDefs() >= 1)
1808 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1809 .addReg(Op0, getKillRegState(Op0IsKill))
1810 .addReg(Op1, getKillRegState(Op1IsKill))
1811 .addReg(Op2, getKillRegState(Op2IsKill));
1813 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1814 .addReg(Op0, getKillRegState(Op0IsKill))
1815 .addReg(Op1, getKillRegState(Op1IsKill))
1816 .addReg(Op2, getKillRegState(Op2IsKill));
1817 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1818 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1823 unsigned FastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
1824 const TargetRegisterClass *RC, unsigned Op0,
1825 bool Op0IsKill, uint64_t Imm) {
1826 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1828 unsigned ResultReg = createResultReg(RC);
1829 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1831 if (II.getNumDefs() >= 1)
1832 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1833 .addReg(Op0, getKillRegState(Op0IsKill))
1836 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1837 .addReg(Op0, getKillRegState(Op0IsKill))
1839 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1840 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1845 unsigned FastISel::fastEmitInst_rii(unsigned MachineInstOpcode,
1846 const TargetRegisterClass *RC, unsigned Op0,
1847 bool Op0IsKill, uint64_t Imm1,
1849 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1851 unsigned ResultReg = createResultReg(RC);
1852 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1854 if (II.getNumDefs() >= 1)
1855 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1856 .addReg(Op0, getKillRegState(Op0IsKill))
1860 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1861 .addReg(Op0, getKillRegState(Op0IsKill))
1864 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1865 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1870 unsigned FastISel::fastEmitInst_rf(unsigned MachineInstOpcode,
1871 const TargetRegisterClass *RC, unsigned Op0,
1872 bool Op0IsKill, const ConstantFP *FPImm) {
1873 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1875 unsigned ResultReg = createResultReg(RC);
1876 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1878 if (II.getNumDefs() >= 1)
1879 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1880 .addReg(Op0, getKillRegState(Op0IsKill))
1883 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1884 .addReg(Op0, getKillRegState(Op0IsKill))
1886 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1887 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1892 unsigned FastISel::fastEmitInst_rri(unsigned MachineInstOpcode,
1893 const TargetRegisterClass *RC, unsigned Op0,
1894 bool Op0IsKill, unsigned Op1,
1895 bool Op1IsKill, uint64_t Imm) {
1896 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1898 unsigned ResultReg = createResultReg(RC);
1899 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1900 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1902 if (II.getNumDefs() >= 1)
1903 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1904 .addReg(Op0, getKillRegState(Op0IsKill))
1905 .addReg(Op1, getKillRegState(Op1IsKill))
1908 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1909 .addReg(Op0, getKillRegState(Op0IsKill))
1910 .addReg(Op1, getKillRegState(Op1IsKill))
1912 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1913 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1918 unsigned FastISel::fastEmitInst_rrii(unsigned MachineInstOpcode,
1919 const TargetRegisterClass *RC,
1920 unsigned Op0, bool Op0IsKill, unsigned Op1,
1921 bool Op1IsKill, uint64_t Imm1,
1923 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1925 unsigned ResultReg = createResultReg(RC);
1926 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1927 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1929 if (II.getNumDefs() >= 1)
1930 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1931 .addReg(Op0, getKillRegState(Op0IsKill))
1932 .addReg(Op1, getKillRegState(Op1IsKill))
1936 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II)
1937 .addReg(Op0, getKillRegState(Op0IsKill))
1938 .addReg(Op1, getKillRegState(Op1IsKill))
1941 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1942 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1947 unsigned FastISel::fastEmitInst_i(unsigned MachineInstOpcode,
1948 const TargetRegisterClass *RC, uint64_t Imm) {
1949 unsigned ResultReg = createResultReg(RC);
1950 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1952 if (II.getNumDefs() >= 1)
1953 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1956 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm);
1957 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1958 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1963 unsigned FastISel::fastEmitInst_ii(unsigned MachineInstOpcode,
1964 const TargetRegisterClass *RC, uint64_t Imm1,
1966 unsigned ResultReg = createResultReg(RC);
1967 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1969 if (II.getNumDefs() >= 1)
1970 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1974 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addImm(Imm1)
1976 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1977 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
1982 unsigned FastISel::fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0,
1983 bool Op0IsKill, uint32_t Idx) {
1984 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1985 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
1986 "Cannot yet extract from physregs");
1987 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
1988 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
1989 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
1990 ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);
1994 /// Emit MachineInstrs to compute the value of Op with all but the least
1995 /// significant bit set to zero.
1996 unsigned FastISel::fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill) {
1997 return fastEmit_ri(VT, VT, ISD::AND, Op0, Op0IsKill, 1);
2000 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
2001 /// Emit code to ensure constants are copied into registers when needed.
2002 /// Remember the virtual registers that need to be added to the Machine PHI
2003 /// nodes as input. We cannot just directly add them, because expansion
2004 /// might result in multiple MBB's for one BB. As such, the start of the
2005 /// BB might correspond to a different MBB than the end.
2006 bool FastISel::handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) {
2007 const TerminatorInst *TI = LLVMBB->getTerminator();
2009 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled;
2010 FuncInfo.OrigNumPHINodesToUpdate = FuncInfo.PHINodesToUpdate.size();
2012 // Check successor nodes' PHI nodes that expect a constant to be available
2014 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) {
2015 const BasicBlock *SuccBB = TI->getSuccessor(succ);
2016 if (!isa<PHINode>(SuccBB->begin()))
2018 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB];
2020 // If this terminator has multiple identical successors (common for
2021 // switches), only handle each succ once.
2022 if (!SuccsHandled.insert(SuccMBB).second)
2025 MachineBasicBlock::iterator MBBI = SuccMBB->begin();
2027 // At this point we know that there is a 1-1 correspondence between LLVM PHI
2028 // nodes and Machine PHI nodes, but the incoming operands have not been
2030 for (BasicBlock::const_iterator I = SuccBB->begin();
2031 const auto *PN = dyn_cast<PHINode>(I); ++I) {
2033 // Ignore dead phi's.
2034 if (PN->use_empty())
2037 // Only handle legal types. Two interesting things to note here. First,
2038 // by bailing out early, we may leave behind some dead instructions,
2039 // since SelectionDAG's HandlePHINodesInSuccessorBlocks will insert its
2040 // own moves. Second, this check is necessary because FastISel doesn't
2041 // use CreateRegs to create registers, so it always creates
2042 // exactly one register for each non-void instruction.
2043 EVT VT = TLI.getValueType(DL, PN->getType(), /*AllowUnknown=*/true);
2044 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
2045 // Handle integer promotions, though, because they're common and easy.
2046 if (!(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) {
2047 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
2052 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB);
2054 // Set the DebugLoc for the copy. Prefer the location of the operand
2055 // if there is one; use the location of the PHI otherwise.
2056 DbgLoc = PN->getDebugLoc();
2057 if (const auto *Inst = dyn_cast<Instruction>(PHIOp))
2058 DbgLoc = Inst->getDebugLoc();
2060 unsigned Reg = getRegForValue(PHIOp);
2062 FuncInfo.PHINodesToUpdate.resize(FuncInfo.OrigNumPHINodesToUpdate);
2065 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg));
2066 DbgLoc = DebugLoc();
2073 bool FastISel::tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst) {
2074 assert(LI->hasOneUse() &&
2075 "tryToFoldLoad expected a LoadInst with a single use");
2076 // We know that the load has a single use, but don't know what it is. If it
2077 // isn't one of the folded instructions, then we can't succeed here. Handle
2078 // this by scanning the single-use users of the load until we get to FoldInst.
2079 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs.
2081 const Instruction *TheUser = LI->user_back();
2082 while (TheUser != FoldInst && // Scan up until we find FoldInst.
2083 // Stay in the right block.
2084 TheUser->getParent() == FoldInst->getParent() &&
2085 --MaxUsers) { // Don't scan too far.
2086 // If there are multiple or no uses of this instruction, then bail out.
2087 if (!TheUser->hasOneUse())
2090 TheUser = TheUser->user_back();
2093 // If we didn't find the fold instruction, then we failed to collapse the
2095 if (TheUser != FoldInst)
2098 // Don't try to fold volatile loads. Target has to deal with alignment
2100 if (LI->isVolatile())
2103 // Figure out which vreg this is going into. If there is no assigned vreg yet
2104 // then there actually was no reference to it. Perhaps the load is referenced
2105 // by a dead instruction.
2106 unsigned LoadReg = getRegForValue(LI);
2110 // We can't fold if this vreg has no uses or more than one use. Multiple uses
2111 // may mean that the instruction got lowered to multiple MIs, or the use of
2112 // the loaded value ended up being multiple operands of the result.
2113 if (!MRI.hasOneUse(LoadReg))
2116 MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(LoadReg);
2117 MachineInstr *User = RI->getParent();
2119 // Set the insertion point properly. Folding the load can cause generation of
2120 // other random instructions (like sign extends) for addressing modes; make
2121 // sure they get inserted in a logical place before the new instruction.
2122 FuncInfo.InsertPt = User;
2123 FuncInfo.MBB = User->getParent();
2125 // Ask the target to try folding the load.
2126 return tryToFoldLoadIntoMI(User, RI.getOperandNo(), LI);
2129 bool FastISel::canFoldAddIntoGEP(const User *GEP, const Value *Add) {
2131 if (!isa<AddOperator>(Add))
2133 // Type size needs to match.
2134 if (DL.getTypeSizeInBits(GEP->getType()) !=
2135 DL.getTypeSizeInBits(Add->getType()))
2137 // Must be in the same basic block.
2138 if (isa<Instruction>(Add) &&
2139 FuncInfo.MBBMap[cast<Instruction>(Add)->getParent()] != FuncInfo.MBB)
2141 // Must have a constant operand.
2142 return isa<ConstantInt>(cast<AddOperator>(Add)->getOperand(1));
2146 FastISel::createMachineMemOperandFor(const Instruction *I) const {
2153 if (const auto *LI = dyn_cast<LoadInst>(I)) {
2154 Alignment = LI->getAlignment();
2155 IsVolatile = LI->isVolatile();
2156 Flags = MachineMemOperand::MOLoad;
2157 Ptr = LI->getPointerOperand();
2158 ValTy = LI->getType();
2159 } else if (const auto *SI = dyn_cast<StoreInst>(I)) {
2160 Alignment = SI->getAlignment();
2161 IsVolatile = SI->isVolatile();
2162 Flags = MachineMemOperand::MOStore;
2163 Ptr = SI->getPointerOperand();
2164 ValTy = SI->getValueOperand()->getType();
2168 bool IsNonTemporal = I->getMetadata(LLVMContext::MD_nontemporal) != nullptr;
2169 bool IsInvariant = I->getMetadata(LLVMContext::MD_invariant_load) != nullptr;
2170 const MDNode *Ranges = I->getMetadata(LLVMContext::MD_range);
2173 I->getAAMetadata(AAInfo);
2175 if (Alignment == 0) // Ensure that codegen never sees alignment 0.
2176 Alignment = DL.getABITypeAlignment(ValTy);
2178 unsigned Size = DL.getTypeStoreSize(ValTy);
2181 Flags |= MachineMemOperand::MOVolatile;
2183 Flags |= MachineMemOperand::MONonTemporal;
2185 Flags |= MachineMemOperand::MOInvariant;
2187 return FuncInfo.MF->getMachineMemOperand(MachinePointerInfo(Ptr), Flags, Size,
2188 Alignment, AAInfo, Ranges);
2191 CmpInst::Predicate FastISel::optimizeCmpPredicate(const CmpInst *CI) const {
2192 // If both operands are the same, then try to optimize or fold the cmp.
2193 CmpInst::Predicate Predicate = CI->getPredicate();
2194 if (CI->getOperand(0) != CI->getOperand(1))
2197 switch (Predicate) {
2198 default: llvm_unreachable("Invalid predicate!");
2199 case CmpInst::FCMP_FALSE: Predicate = CmpInst::FCMP_FALSE; break;
2200 case CmpInst::FCMP_OEQ: Predicate = CmpInst::FCMP_ORD; break;
2201 case CmpInst::FCMP_OGT: Predicate = CmpInst::FCMP_FALSE; break;
2202 case CmpInst::FCMP_OGE: Predicate = CmpInst::FCMP_ORD; break;
2203 case CmpInst::FCMP_OLT: Predicate = CmpInst::FCMP_FALSE; break;
2204 case CmpInst::FCMP_OLE: Predicate = CmpInst::FCMP_ORD; break;
2205 case CmpInst::FCMP_ONE: Predicate = CmpInst::FCMP_FALSE; break;
2206 case CmpInst::FCMP_ORD: Predicate = CmpInst::FCMP_ORD; break;
2207 case CmpInst::FCMP_UNO: Predicate = CmpInst::FCMP_UNO; break;
2208 case CmpInst::FCMP_UEQ: Predicate = CmpInst::FCMP_TRUE; break;
2209 case CmpInst::FCMP_UGT: Predicate = CmpInst::FCMP_UNO; break;
2210 case CmpInst::FCMP_UGE: Predicate = CmpInst::FCMP_TRUE; break;
2211 case CmpInst::FCMP_ULT: Predicate = CmpInst::FCMP_UNO; break;
2212 case CmpInst::FCMP_ULE: Predicate = CmpInst::FCMP_TRUE; break;
2213 case CmpInst::FCMP_UNE: Predicate = CmpInst::FCMP_UNO; break;
2214 case CmpInst::FCMP_TRUE: Predicate = CmpInst::FCMP_TRUE; break;
2216 case CmpInst::ICMP_EQ: Predicate = CmpInst::FCMP_TRUE; break;
2217 case CmpInst::ICMP_NE: Predicate = CmpInst::FCMP_FALSE; break;
2218 case CmpInst::ICMP_UGT: Predicate = CmpInst::FCMP_FALSE; break;
2219 case CmpInst::ICMP_UGE: Predicate = CmpInst::FCMP_TRUE; break;
2220 case CmpInst::ICMP_ULT: Predicate = CmpInst::FCMP_FALSE; break;
2221 case CmpInst::ICMP_ULE: Predicate = CmpInst::FCMP_TRUE; break;
2222 case CmpInst::ICMP_SGT: Predicate = CmpInst::FCMP_FALSE; break;
2223 case CmpInst::ICMP_SGE: Predicate = CmpInst::FCMP_TRUE; break;
2224 case CmpInst::ICMP_SLT: Predicate = CmpInst::FCMP_FALSE; break;
2225 case CmpInst::ICMP_SLE: Predicate = CmpInst::FCMP_TRUE; break;