1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Instructions.h"
15 #include "llvm/CodeGen/FastISel.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetMachine.h"
24 unsigned FastISel::getRegForValue(Value *V, DenseMap<const Value*, unsigned> &ValueMap) {
25 unsigned &Reg = ValueMap[V];
29 MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
30 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
31 if (CI->getValue().getActiveBits() > 64)
33 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
34 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
35 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
38 const APFloat &Flt = CF->getValueAPF();
39 MVT IntVT = TLI.getPointerTy();
42 uint32_t IntBitWidth = IntVT.getSizeInBits();
43 if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
44 APFloat::rmTowardZero) != APFloat::opOK)
46 APInt IntVal(IntBitWidth, 2, x);
48 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
49 ISD::Constant, IntVal.getZExtValue());
52 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
61 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
62 /// which has an opcode which directly corresponds to the given ISD opcode.
64 bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
65 DenseMap<const Value*, unsigned> &ValueMap) {
66 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
67 if (VT == MVT::Other || !VT.isSimple())
68 // Unhandled type. Halt "fast" selection and bail.
70 // We only handle legal types. For example, on x86-32 the instruction
71 // selector contains all of the 64-bit instructions from x86-64,
72 // under the assumption that i64 won't be used if the target doesn't
74 if (!TLI.isTypeLegal(VT))
77 unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
79 // Unhandled operand. Halt "fast" selection and bail.
82 // Check if the second operand is a constant and handle it appropriately.
83 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
84 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
85 ISDOpcode, Op0, CI->getZExtValue());
87 // We successfully emitted code for the given LLVM Instruction.
88 ValueMap[I] = ResultReg;
93 // Check if the second operand is a constant float.
94 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
95 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
98 // We successfully emitted code for the given LLVM Instruction.
99 ValueMap[I] = ResultReg;
104 unsigned Op1 = getRegForValue(I->getOperand(1), ValueMap);
106 // Unhandled operand. Halt "fast" selection and bail.
109 // Now we have both operands in registers. Emit the instruction.
110 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
111 ISDOpcode, Op0, Op1);
113 // Target-specific code wasn't able to find a machine opcode for
114 // the given ISD opcode and type. Halt "fast" selection and bail.
117 // We successfully emitted code for the given LLVM Instruction.
118 ValueMap[I] = ResultReg;
122 bool FastISel::SelectGetElementPtr(Instruction *I,
123 DenseMap<const Value*, unsigned> &ValueMap) {
124 unsigned N = getRegForValue(I->getOperand(0), ValueMap);
126 // Unhandled operand. Halt "fast" selection and bail.
129 const Type *Ty = I->getOperand(0)->getType();
130 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
131 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
134 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
135 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
138 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
139 // FIXME: This can be optimized by combining the add with a
141 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
143 // Unhandled operand. Halt "fast" selection and bail.
146 Ty = StTy->getElementType(Field);
148 Ty = cast<SequentialType>(Ty)->getElementType();
150 // If this is a constant subscript, handle it quickly.
151 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
152 if (CI->getZExtValue() == 0) continue;
154 TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
155 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
157 // Unhandled operand. Halt "fast" selection and bail.
162 // N = N + Idx * ElementSize;
163 uint64_t ElementSize = TD.getABITypeSize(Ty);
164 unsigned IdxN = getRegForValue(Idx, ValueMap);
166 // Unhandled operand. Halt "fast" selection and bail.
169 // If the index is smaller or larger than intptr_t, truncate or extend
171 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
172 if (IdxVT.bitsLT(VT))
173 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
174 else if (IdxVT.bitsGT(VT))
175 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
177 // Unhandled operand. Halt "fast" selection and bail.
180 if (ElementSize != 1) {
181 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
183 // Unhandled operand. Halt "fast" selection and bail.
186 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
188 // Unhandled operand. Halt "fast" selection and bail.
193 // We successfully emitted code for the given LLVM Instruction.
198 bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode,
199 DenseMap<const Value*, unsigned> &ValueMap) {
200 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
201 MVT DstVT = TLI.getValueType(I->getType());
203 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
204 DstVT == MVT::Other || !DstVT.isSimple() ||
205 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
206 // Unhandled type. Halt "fast" selection and bail.
209 unsigned InputReg = getRegForValue(I->getOperand(0), ValueMap);
211 // Unhandled operand. Halt "fast" selection and bail.
214 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
221 ValueMap[I] = ResultReg;
225 bool FastISel::SelectBitCast(Instruction *I,
226 DenseMap<const Value*, unsigned> &ValueMap) {
227 // If the bitcast doesn't change the type, just use the operand value.
228 if (I->getType() == I->getOperand(0)->getType()) {
229 unsigned Reg = getRegForValue(I->getOperand(0), ValueMap);
236 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
237 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
238 MVT DstVT = TLI.getValueType(I->getType());
240 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
241 DstVT == MVT::Other || !DstVT.isSimple() ||
242 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
243 // Unhandled type. Halt "fast" selection and bail.
246 unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
248 // Unhandled operand. Halt "fast" selection and bail.
251 // First, try to perform the bitcast by inserting a reg-reg copy.
252 unsigned ResultReg = 0;
253 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
254 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
255 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
256 ResultReg = createResultReg(DstClass);
258 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
259 Op0, DstClass, SrcClass);
264 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
266 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
267 ISD::BIT_CONVERT, Op0);
272 ValueMap[I] = ResultReg;
277 FastISel::SelectInstructions(BasicBlock::iterator Begin,
278 BasicBlock::iterator End,
279 DenseMap<const Value*, unsigned> &ValueMap,
280 DenseMap<const BasicBlock*,
281 MachineBasicBlock *> &MBBMap,
282 MachineBasicBlock *mbb) {
284 BasicBlock::iterator I = Begin;
286 for (; I != End; ++I) {
287 switch (I->getOpcode()) {
288 case Instruction::Add: {
289 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
290 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
292 case Instruction::Sub: {
293 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
294 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
296 case Instruction::Mul: {
297 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
298 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
300 case Instruction::SDiv:
301 if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
302 case Instruction::UDiv:
303 if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
304 case Instruction::FDiv:
305 if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
306 case Instruction::SRem:
307 if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
308 case Instruction::URem:
309 if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
310 case Instruction::FRem:
311 if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
312 case Instruction::Shl:
313 if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
314 case Instruction::LShr:
315 if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
316 case Instruction::AShr:
317 if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
318 case Instruction::And:
319 if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
320 case Instruction::Or:
321 if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
322 case Instruction::Xor:
323 if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
325 case Instruction::GetElementPtr:
326 if (!SelectGetElementPtr(I, ValueMap)) return I;
329 case Instruction::Br: {
330 BranchInst *BI = cast<BranchInst>(I);
332 if (BI->isUnconditional()) {
333 MachineFunction::iterator NextMBB =
334 next(MachineFunction::iterator(MBB));
335 BasicBlock *LLVMSucc = BI->getSuccessor(0);
336 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
338 if (NextMBB != MF.end() && MSucc == NextMBB) {
339 // The unconditional fall-through case, which needs no instructions.
341 // The unconditional branch case.
342 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
344 MBB->addSuccessor(MSucc);
348 // Conditional branches are not handed yet.
349 // Halt "fast" selection and bail.
353 case Instruction::PHI:
354 // PHI nodes are already emitted.
357 case Instruction::BitCast:
358 if (!SelectBitCast(I, ValueMap)) return I; break;
360 case Instruction::FPToSI:
361 if (!SelectCast(I, ISD::FP_TO_SINT, ValueMap)) return I;
363 case Instruction::ZExt:
364 if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
366 case Instruction::SExt:
367 if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
369 case Instruction::SIToFP:
370 if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
373 case Instruction::IntToPtr: // Deliberate fall-through.
374 case Instruction::PtrToInt: {
375 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
376 MVT DstVT = TLI.getValueType(I->getType());
377 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
378 if (ValueMap[I->getOperand(0)]) {
379 ValueMap[I] = ValueMap[I->getOperand(0)];
384 } else if (DstVT.bitsGT(SrcVT)) {
385 if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
388 // TODO: Handle SrcVT > DstVT, where truncation is needed.
394 // Unhandled instruction. Halt "fast" selection and bail.
402 FastISel::FastISel(MachineFunction &mf)
404 MRI(mf.getRegInfo()),
406 TD(*TM.getTargetData()),
407 TII(*TM.getInstrInfo()),
408 TLI(*TM.getTargetLowering()) {
411 FastISel::~FastISel() {}
413 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, ISD::NodeType) {
417 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
418 ISD::NodeType, unsigned /*Op0*/) {
422 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
423 ISD::NodeType, unsigned /*Op0*/,
428 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
429 ISD::NodeType, uint64_t /*Imm*/) {
433 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
434 ISD::NodeType, ConstantFP * /*FPImm*/) {
438 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
439 ISD::NodeType, unsigned /*Op0*/,
444 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
445 ISD::NodeType, unsigned /*Op0*/,
446 ConstantFP * /*FPImm*/) {
450 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
452 unsigned /*Op0*/, unsigned /*Op1*/,
457 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
458 /// to emit an instruction with an immediate operand using FastEmit_ri.
459 /// If that fails, it materializes the immediate into a register and try
460 /// FastEmit_rr instead.
461 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
462 unsigned Op0, uint64_t Imm,
463 MVT::SimpleValueType ImmType) {
464 // First check if immediate type is legal. If not, we can't use the ri form.
465 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
468 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
469 if (MaterialReg == 0)
471 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
474 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
475 /// to emit an instruction with a floating-point immediate operand using
476 /// FastEmit_rf. If that fails, it materializes the immediate into a register
477 /// and try FastEmit_rr instead.
478 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
479 unsigned Op0, ConstantFP *FPImm,
480 MVT::SimpleValueType ImmType) {
481 // First check if immediate type is legal. If not, we can't use the rf form.
482 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
486 // Materialize the constant in a register.
487 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
488 if (MaterialReg == 0) {
489 // If the target doesn't have a way to directly enter a floating-point
490 // value into a register, use an alternate approach.
491 // TODO: The current approach only supports floating-point constants
492 // that can be constructed by conversion from integer values. This should
493 // be replaced by code that creates a load from a constant-pool entry,
494 // which will require some target-specific work.
495 const APFloat &Flt = FPImm->getValueAPF();
496 MVT IntVT = TLI.getPointerTy();
499 uint32_t IntBitWidth = IntVT.getSizeInBits();
500 if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
501 APFloat::rmTowardZero) != APFloat::opOK)
503 APInt IntVal(IntBitWidth, 2, x);
505 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
506 ISD::Constant, IntVal.getZExtValue());
509 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
510 ISD::SINT_TO_FP, IntegerReg);
511 if (MaterialReg == 0)
514 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
517 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
518 return MRI.createVirtualRegister(RC);
521 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
522 const TargetRegisterClass* RC) {
523 unsigned ResultReg = createResultReg(RC);
524 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
526 BuildMI(MBB, II, ResultReg);
530 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
531 const TargetRegisterClass *RC,
533 unsigned ResultReg = createResultReg(RC);
534 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
536 BuildMI(MBB, II, ResultReg).addReg(Op0);
540 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
541 const TargetRegisterClass *RC,
542 unsigned Op0, unsigned Op1) {
543 unsigned ResultReg = createResultReg(RC);
544 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
546 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
550 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
551 const TargetRegisterClass *RC,
552 unsigned Op0, uint64_t Imm) {
553 unsigned ResultReg = createResultReg(RC);
554 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
556 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
560 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
561 const TargetRegisterClass *RC,
562 unsigned Op0, ConstantFP *FPImm) {
563 unsigned ResultReg = createResultReg(RC);
564 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
566 BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
570 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
571 const TargetRegisterClass *RC,
572 unsigned Op0, unsigned Op1, uint64_t Imm) {
573 unsigned ResultReg = createResultReg(RC);
574 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
576 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
580 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
581 const TargetRegisterClass *RC,
583 unsigned ResultReg = createResultReg(RC);
584 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
586 BuildMI(MBB, II, ResultReg).addImm(Imm);
590 unsigned FastISel::FastEmitInst_extractsubreg(const TargetRegisterClass *RC,
591 unsigned Op0, uint32_t Idx) {
592 const TargetRegisterClass* SRC = *(RC->subregclasses_begin()+Idx-1);
594 unsigned ResultReg = createResultReg(SRC);
595 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
597 BuildMI(MBB, II, ResultReg).addReg(Op0);