1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Instructions.h"
15 #include "llvm/CodeGen/FastISel.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetMachine.h"
24 unsigned FastISel::getRegForValue(Value *V, DenseMap<const Value*, unsigned> &ValueMap) {
25 unsigned &Reg = ValueMap[V];
29 MVT::SimpleValueType VT = TLI.getValueType(V->getType()).getSimpleVT();
30 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
31 if (CI->getValue().getActiveBits() > 64)
33 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
34 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
35 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
38 const APFloat &Flt = CF->getValueAPF();
39 MVT IntVT = TLI.getPointerTy();
42 uint32_t IntBitWidth = IntVT.getSizeInBits();
43 if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
44 APFloat::rmTowardZero) != APFloat::opOK)
46 APInt IntVal(IntBitWidth, 2, x);
48 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
49 ISD::Constant, IntVal.getZExtValue());
52 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
61 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
62 /// which has an opcode which directly corresponds to the given ISD opcode.
64 bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
65 DenseMap<const Value*, unsigned> &ValueMap) {
66 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
67 if (VT == MVT::Other || !VT.isSimple())
68 // Unhandled type. Halt "fast" selection and bail.
70 // We only handle legal types. For example, on x86-32 the instruction
71 // selector contains all of the 64-bit instructions from x86-64,
72 // under the assumption that i64 won't be used if the target doesn't
74 if (!TLI.isTypeLegal(VT))
77 unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
79 // Unhandled operand. Halt "fast" selection and bail.
82 // Check if the second operand is a constant and handle it appropriately.
83 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
84 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
85 ISDOpcode, Op0, CI->getZExtValue());
87 // We successfully emitted code for the given LLVM Instruction.
88 ValueMap[I] = ResultReg;
93 // Check if the second operand is a constant float.
94 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
95 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
98 // We successfully emitted code for the given LLVM Instruction.
99 ValueMap[I] = ResultReg;
104 unsigned Op1 = getRegForValue(I->getOperand(1), ValueMap);
106 // Unhandled operand. Halt "fast" selection and bail.
109 // Now we have both operands in registers. Emit the instruction.
110 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
111 ISDOpcode, Op0, Op1);
113 // Target-specific code wasn't able to find a machine opcode for
114 // the given ISD opcode and type. Halt "fast" selection and bail.
117 // We successfully emitted code for the given LLVM Instruction.
118 ValueMap[I] = ResultReg;
122 bool FastISel::SelectGetElementPtr(Instruction *I,
123 DenseMap<const Value*, unsigned> &ValueMap) {
124 unsigned N = getRegForValue(I->getOperand(0), ValueMap);
126 // Unhandled operand. Halt "fast" selection and bail.
129 const Type *Ty = I->getOperand(0)->getType();
130 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
131 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
134 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
135 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
138 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
139 // FIXME: This can be optimized by combining the add with a
141 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
143 // Unhandled operand. Halt "fast" selection and bail.
146 Ty = StTy->getElementType(Field);
148 Ty = cast<SequentialType>(Ty)->getElementType();
150 // If this is a constant subscript, handle it quickly.
151 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
152 if (CI->getZExtValue() == 0) continue;
154 TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
155 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
157 // Unhandled operand. Halt "fast" selection and bail.
162 // N = N + Idx * ElementSize;
163 uint64_t ElementSize = TD.getABITypeSize(Ty);
164 unsigned IdxN = getRegForValue(Idx, ValueMap);
166 // Unhandled operand. Halt "fast" selection and bail.
169 // If the index is smaller or larger than intptr_t, truncate or extend
171 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
172 if (IdxVT.bitsLT(VT))
173 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
174 else if (IdxVT.bitsGT(VT))
175 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
177 // Unhandled operand. Halt "fast" selection and bail.
180 if (ElementSize != 1) {
181 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
183 // Unhandled operand. Halt "fast" selection and bail.
186 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
188 // Unhandled operand. Halt "fast" selection and bail.
193 // We successfully emitted code for the given LLVM Instruction.
198 bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode,
199 DenseMap<const Value*, unsigned> &ValueMap) {
200 MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
201 MVT DstVT = MVT::getMVT(I->getType());
203 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
204 DstVT == MVT::Other || !DstVT.isSimple() ||
205 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
206 // Unhandled type. Halt "fast" selection and bail.
209 unsigned InputReg = getRegForValue(I->getOperand(0), ValueMap);
211 // Unhandled operand. Halt "fast" selection and bail.
214 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
221 ValueMap[I] = ResultReg;
225 bool FastISel::SelectBitCast(Instruction *I,
226 DenseMap<const Value*, unsigned> &ValueMap) {
227 // If the bitcast doesn't change the type, just use the operand value.
228 if (I->getType() == I->getOperand(0)->getType()) {
229 ValueMap[I] = getRegForValue(I->getOperand(0), ValueMap);
233 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
234 MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
235 MVT DstVT = MVT::getMVT(I->getType());
237 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
238 DstVT == MVT::Other || !DstVT.isSimple() ||
239 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
240 // Unhandled type. Halt "fast" selection and bail.
243 unsigned Op0 = getRegForValue(I->getOperand(0), ValueMap);
245 // Unhandled operand. Halt "fast" selection and bail.
248 // First, try to perform the bitcast by inserting a reg-reg copy.
249 unsigned ResultReg = 0;
250 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
251 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
252 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
253 ResultReg = createResultReg(DstClass);
255 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
256 Op0, DstClass, SrcClass);
261 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
263 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
264 ISD::BIT_CONVERT, Op0);
269 ValueMap[I] = ResultReg;
274 FastISel::SelectInstructions(BasicBlock::iterator Begin,
275 BasicBlock::iterator End,
276 DenseMap<const Value*, unsigned> &ValueMap,
277 DenseMap<const BasicBlock*,
278 MachineBasicBlock *> &MBBMap,
279 MachineBasicBlock *mbb) {
281 BasicBlock::iterator I = Begin;
283 for (; I != End; ++I) {
284 switch (I->getOpcode()) {
285 case Instruction::Add: {
286 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
287 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
289 case Instruction::Sub: {
290 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
291 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
293 case Instruction::Mul: {
294 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
295 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
297 case Instruction::SDiv:
298 if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
299 case Instruction::UDiv:
300 if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
301 case Instruction::FDiv:
302 if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
303 case Instruction::SRem:
304 if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
305 case Instruction::URem:
306 if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
307 case Instruction::FRem:
308 if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
309 case Instruction::Shl:
310 if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
311 case Instruction::LShr:
312 if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
313 case Instruction::AShr:
314 if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
315 case Instruction::And:
316 if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
317 case Instruction::Or:
318 if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
319 case Instruction::Xor:
320 if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
322 case Instruction::GetElementPtr:
323 if (!SelectGetElementPtr(I, ValueMap)) return I;
326 case Instruction::Br: {
327 BranchInst *BI = cast<BranchInst>(I);
329 if (BI->isUnconditional()) {
330 MachineFunction::iterator NextMBB =
331 next(MachineFunction::iterator(MBB));
332 BasicBlock *LLVMSucc = BI->getSuccessor(0);
333 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
335 if (NextMBB != MF.end() && MSucc == NextMBB) {
336 // The unconditional fall-through case, which needs no instructions.
338 // The unconditional branch case.
339 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
341 MBB->addSuccessor(MSucc);
345 // Conditional branches are not handed yet.
346 // Halt "fast" selection and bail.
350 case Instruction::PHI:
351 // PHI nodes are already emitted.
354 case Instruction::BitCast:
355 if (!SelectBitCast(I, ValueMap)) return I; break;
357 case Instruction::FPToSI:
358 if (!SelectCast(I, ISD::FP_TO_SINT, ValueMap)) return I;
360 case Instruction::ZExt:
361 if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
363 case Instruction::SExt:
364 if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
366 case Instruction::SIToFP:
367 if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
370 case Instruction::IntToPtr: // Deliberate fall-through.
371 case Instruction::PtrToInt: {
372 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
373 MVT DstVT = TLI.getValueType(I->getType());
374 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
375 if (ValueMap[I->getOperand(0)]) {
376 ValueMap[I] = ValueMap[I->getOperand(0)];
381 } else if (DstVT.bitsGT(SrcVT)) {
382 if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
385 // TODO: Handle SrcVT > DstVT, where truncation is needed.
391 // Unhandled instruction. Halt "fast" selection and bail.
399 FastISel::FastISel(MachineFunction &mf)
401 MRI(mf.getRegInfo()),
403 TD(*TM.getTargetData()),
404 TII(*TM.getInstrInfo()),
405 TLI(*TM.getTargetLowering()) {
408 FastISel::~FastISel() {}
410 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, ISD::NodeType) {
414 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
415 ISD::NodeType, unsigned /*Op0*/) {
419 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
420 ISD::NodeType, unsigned /*Op0*/,
425 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
426 ISD::NodeType, uint64_t /*Imm*/) {
430 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
431 ISD::NodeType, ConstantFP * /*FPImm*/) {
435 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
436 ISD::NodeType, unsigned /*Op0*/,
441 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
442 ISD::NodeType, unsigned /*Op0*/,
443 ConstantFP * /*FPImm*/) {
447 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
449 unsigned /*Op0*/, unsigned /*Op1*/,
454 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
455 /// to emit an instruction with an immediate operand using FastEmit_ri.
456 /// If that fails, it materializes the immediate into a register and try
457 /// FastEmit_rr instead.
458 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
459 unsigned Op0, uint64_t Imm,
460 MVT::SimpleValueType ImmType) {
461 unsigned ResultReg = 0;
462 // First check if immediate type is legal. If not, we can't use the ri form.
463 if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
464 ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
467 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
468 if (MaterialReg == 0)
470 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
473 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
474 /// to emit an instruction with a floating-point immediate operand using
475 /// FastEmit_rf. If that fails, it materializes the immediate into a register
476 /// and try FastEmit_rr instead.
477 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
478 unsigned Op0, ConstantFP *FPImm,
479 MVT::SimpleValueType ImmType) {
480 unsigned ResultReg = 0;
481 // First check if immediate type is legal. If not, we can't use the rf form.
482 if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
483 ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
487 // Materialize the constant in a register.
488 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
489 if (MaterialReg == 0) {
490 // If the target doesn't have a way to directly enter a floating-point
491 // value into a register, use an alternate approach.
492 // TODO: The current approach only supports floating-point constants
493 // that can be constructed by conversion from integer values. This should
494 // be replaced by code that creates a load from a constant-pool entry,
495 // which will require some target-specific work.
496 const APFloat &Flt = FPImm->getValueAPF();
497 MVT IntVT = TLI.getPointerTy();
500 uint32_t IntBitWidth = IntVT.getSizeInBits();
501 if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
502 APFloat::rmTowardZero) != APFloat::opOK)
504 APInt IntVal(IntBitWidth, 2, x);
506 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
507 ISD::Constant, IntVal.getZExtValue());
510 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
511 ISD::SINT_TO_FP, IntegerReg);
512 if (MaterialReg == 0)
515 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
518 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
519 return MRI.createVirtualRegister(RC);
522 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
523 const TargetRegisterClass* RC) {
524 unsigned ResultReg = createResultReg(RC);
525 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
527 BuildMI(MBB, II, ResultReg);
531 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
532 const TargetRegisterClass *RC,
534 unsigned ResultReg = createResultReg(RC);
535 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
537 BuildMI(MBB, II, ResultReg).addReg(Op0);
541 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
542 const TargetRegisterClass *RC,
543 unsigned Op0, unsigned Op1) {
544 unsigned ResultReg = createResultReg(RC);
545 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
547 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
551 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
552 const TargetRegisterClass *RC,
553 unsigned Op0, uint64_t Imm) {
554 unsigned ResultReg = createResultReg(RC);
555 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
557 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
561 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
562 const TargetRegisterClass *RC,
563 unsigned Op0, ConstantFP *FPImm) {
564 unsigned ResultReg = createResultReg(RC);
565 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
567 BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
571 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
572 const TargetRegisterClass *RC,
573 unsigned Op0, unsigned Op1, uint64_t Imm) {
574 unsigned ResultReg = createResultReg(RC);
575 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
577 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
581 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
582 const TargetRegisterClass *RC,
584 unsigned ResultReg = createResultReg(RC);
585 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
587 BuildMI(MBB, II, ResultReg).addImm(Imm);